diff options
Diffstat (limited to 'sound/soc/codecs/wm_adsp.c')
-rw-r--r-- | sound/soc/codecs/wm_adsp.c | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 46ec0e9744d4..fb0c678939bf 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c | |||
@@ -1286,6 +1286,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) | |||
1286 | reg = wm_adsp_region_to_reg(mem, | 1286 | reg = wm_adsp_region_to_reg(mem, |
1287 | reg); | 1287 | reg); |
1288 | reg += offset; | 1288 | reg += offset; |
1289 | break; | ||
1289 | } | 1290 | } |
1290 | } | 1291 | } |
1291 | 1292 | ||
@@ -1468,19 +1469,23 @@ static int wm_adsp2_ena(struct wm_adsp *dsp) | |||
1468 | unsigned int val; | 1469 | unsigned int val; |
1469 | int ret, count; | 1470 | int ret, count; |
1470 | 1471 | ||
1471 | ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, | 1472 | ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, |
1472 | ADSP2_SYS_ENA, ADSP2_SYS_ENA); | 1473 | ADSP2_SYS_ENA, ADSP2_SYS_ENA); |
1473 | if (ret != 0) | 1474 | if (ret != 0) |
1474 | return ret; | 1475 | return ret; |
1475 | 1476 | ||
1476 | /* Wait for the RAM to start, should be near instantaneous */ | 1477 | /* Wait for the RAM to start, should be near instantaneous */ |
1477 | count = 0; | 1478 | for (count = 0; count < 10; ++count) { |
1478 | do { | ||
1479 | ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, | 1479 | ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, |
1480 | &val); | 1480 | &val); |
1481 | if (ret != 0) | 1481 | if (ret != 0) |
1482 | return ret; | 1482 | return ret; |
1483 | } while (!(val & ADSP2_RAM_RDY) && ++count < 10); | 1483 | |
1484 | if (val & ADSP2_RAM_RDY) | ||
1485 | break; | ||
1486 | |||
1487 | msleep(1); | ||
1488 | } | ||
1484 | 1489 | ||
1485 | if (!(val & ADSP2_RAM_RDY)) { | 1490 | if (!(val & ADSP2_RAM_RDY)) { |
1486 | adsp_err(dsp, "Failed to start DSP RAM\n"); | 1491 | adsp_err(dsp, "Failed to start DSP RAM\n"); |
@@ -1488,7 +1493,6 @@ static int wm_adsp2_ena(struct wm_adsp *dsp) | |||
1488 | } | 1493 | } |
1489 | 1494 | ||
1490 | adsp_dbg(dsp, "RAM ready after %d polls\n", count); | 1495 | adsp_dbg(dsp, "RAM ready after %d polls\n", count); |
1491 | adsp_info(dsp, "RAM ready after %d polls\n", count); | ||
1492 | 1496 | ||
1493 | return 0; | 1497 | return 0; |
1494 | } | 1498 | } |
@@ -1521,9 +1525,9 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, | |||
1521 | val = (val & ARIZONA_SYSCLK_FREQ_MASK) | 1525 | val = (val & ARIZONA_SYSCLK_FREQ_MASK) |
1522 | >> ARIZONA_SYSCLK_FREQ_SHIFT; | 1526 | >> ARIZONA_SYSCLK_FREQ_SHIFT; |
1523 | 1527 | ||
1524 | ret = regmap_update_bits(dsp->regmap, | 1528 | ret = regmap_update_bits_async(dsp->regmap, |
1525 | dsp->base + ADSP2_CLOCKING, | 1529 | dsp->base + ADSP2_CLOCKING, |
1526 | ADSP2_CLK_SEL_MASK, val); | 1530 | ADSP2_CLK_SEL_MASK, val); |
1527 | if (ret != 0) { | 1531 | if (ret != 0) { |
1528 | adsp_err(dsp, "Failed to set clock rate: %d\n", | 1532 | adsp_err(dsp, "Failed to set clock rate: %d\n", |
1529 | ret); | 1533 | ret); |
@@ -1586,10 +1590,10 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, | |||
1586 | if (ret != 0) | 1590 | if (ret != 0) |
1587 | goto err; | 1591 | goto err; |
1588 | 1592 | ||
1589 | ret = regmap_update_bits(dsp->regmap, | 1593 | ret = regmap_update_bits_async(dsp->regmap, |
1590 | dsp->base + ADSP2_CONTROL, | 1594 | dsp->base + ADSP2_CONTROL, |
1591 | ADSP2_CORE_ENA | ADSP2_START, | 1595 | ADSP2_CORE_ENA | ADSP2_START, |
1592 | ADSP2_CORE_ENA | ADSP2_START); | 1596 | ADSP2_CORE_ENA | ADSP2_START); |
1593 | if (ret != 0) | 1597 | if (ret != 0) |
1594 | goto err; | 1598 | goto err; |
1595 | 1599 | ||