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Diffstat (limited to 'sound/soc/codecs/wm9081.c')
-rw-r--r--sound/soc/codecs/wm9081.c229
1 files changed, 85 insertions, 144 deletions
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 156f2a4a5930..1f51dd542a46 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -168,84 +168,19 @@ struct wm9081_priv {
168 struct wm9081_retune_mobile_config *retune; 168 struct wm9081_retune_mobile_config *retune;
169}; 169};
170 170
171static int wm9081_reg_is_volatile(int reg) 171static int wm9081_volatile_register(unsigned int reg)
172{ 172{
173 switch (reg) { 173 switch (reg) {
174 case WM9081_SOFTWARE_RESET:
175 return 1;
174 default: 176 default:
175 return 0; 177 return 0;
176 } 178 }
177} 179}
178 180
179static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned int reg)
181{
182 u16 *cache = codec->reg_cache;
183 BUG_ON(reg > WM9081_MAX_REGISTER);
184 return cache[reg];
185}
186
187static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
188{
189 struct i2c_msg xfer[2];
190 u16 data;
191 int ret;
192 struct i2c_client *client = codec->control_data;
193
194 BUG_ON(reg > WM9081_MAX_REGISTER);
195
196 /* Write register */
197 xfer[0].addr = client->addr;
198 xfer[0].flags = 0;
199 xfer[0].len = 1;
200 xfer[0].buf = ®
201
202 /* Read data */
203 xfer[1].addr = client->addr;
204 xfer[1].flags = I2C_M_RD;
205 xfer[1].len = 2;
206 xfer[1].buf = (u8 *)&data;
207
208 ret = i2c_transfer(client->adapter, xfer, 2);
209 if (ret != 2) {
210 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
211 return 0;
212 }
213
214 return (data >> 8) | ((data & 0xff) << 8);
215}
216
217static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
218{
219 if (wm9081_reg_is_volatile(reg))
220 return wm9081_read_hw(codec, reg);
221 else
222 return wm9081_read_reg_cache(codec, reg);
223}
224
225static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
228 u16 *cache = codec->reg_cache;
229 u8 data[3];
230
231 BUG_ON(reg > WM9081_MAX_REGISTER);
232
233 if (!wm9081_reg_is_volatile(reg))
234 cache[reg] = value;
235
236 data[0] = reg;
237 data[1] = value >> 8;
238 data[2] = value & 0x00ff;
239
240 if (codec->hw_write(codec->control_data, data, 3) == 3)
241 return 0;
242 else
243 return -EIO;
244}
245
246static int wm9081_reset(struct snd_soc_codec *codec) 181static int wm9081_reset(struct snd_soc_codec *codec)
247{ 182{
248 return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0); 183 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
249} 184}
250 185
251static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); 186static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
@@ -356,7 +291,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
357 unsigned int reg; 292 unsigned int reg;
358 293
359 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 294 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
360 if (reg & WM9081_SPK_MODE) 295 if (reg & WM9081_SPK_MODE)
361 ucontrol->value.integer.value[0] = 1; 296 ucontrol->value.integer.value[0] = 1;
362 else 297 else
@@ -375,8 +310,8 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol) 310 struct snd_ctl_elem_value *ucontrol)
376{ 311{
377 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378 unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 313 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
379 unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 314 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
380 315
381 /* Are we changing anything? */ 316 /* Are we changing anything? */
382 if (ucontrol->value.integer.value[0] == 317 if (ucontrol->value.integer.value[0] ==
@@ -397,7 +332,7 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
397 reg2 &= ~WM9081_SPK_MODE; 332 reg2 &= ~WM9081_SPK_MODE;
398 } 333 }
399 334
400 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); 335 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
401 336
402 return 0; 337 return 0;
403} 338}
@@ -456,7 +391,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event) 391 struct snd_kcontrol *kcontrol, int event)
457{ 392{
458 struct snd_soc_codec *codec = w->codec; 393 struct snd_soc_codec *codec = w->codec;
459 unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 394 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
460 395
461 switch (event) { 396 switch (event) {
462 case SND_SOC_DAPM_POST_PMU: 397 case SND_SOC_DAPM_POST_PMU:
@@ -468,7 +403,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
468 break; 403 break;
469 } 404 }
470 405
471 wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg); 406 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
472 407
473 return 0; 408 return 0;
474} 409}
@@ -607,7 +542,7 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
607 if (ret != 0) 542 if (ret != 0)
608 return ret; 543 return ret;
609 544
610 reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5); 545 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
611 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; 546 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
612 547
613 switch (fll_id) { 548 switch (fll_id) {
@@ -621,44 +556,44 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
621 } 556 }
622 557
623 /* Disable CLK_SYS while we reconfigure */ 558 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 559 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 560 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, 561 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
627 clk_sys_reg & ~WM9081_CLK_SYS_ENA); 562 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
628 563
629 /* Any FLL configuration change requires that the FLL be 564 /* Any FLL configuration change requires that the FLL be
630 * disabled first. */ 565 * disabled first. */
631 reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1); 566 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
632 reg1 &= ~WM9081_FLL_ENA; 567 reg1 &= ~WM9081_FLL_ENA;
633 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 568 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
634 569
635 /* Apply the configuration */ 570 /* Apply the configuration */
636 if (fll_div.k) 571 if (fll_div.k)
637 reg1 |= WM9081_FLL_FRAC_MASK; 572 reg1 |= WM9081_FLL_FRAC_MASK;
638 else 573 else
639 reg1 &= ~WM9081_FLL_FRAC_MASK; 574 reg1 &= ~WM9081_FLL_FRAC_MASK;
640 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 575 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
641 576
642 wm9081_write(codec, WM9081_FLL_CONTROL_2, 577 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
643 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | 578 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
644 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); 579 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
645 wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); 580 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
646 581
647 reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4); 582 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
648 reg4 &= ~WM9081_FLL_N_MASK; 583 reg4 &= ~WM9081_FLL_N_MASK;
649 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; 584 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
650 wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4); 585 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
651 586
652 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; 587 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
653 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 588 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
654 wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5); 589 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
655 590
656 /* Enable the FLL */ 591 /* Enable the FLL */
657 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 592 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
658 593
659 /* Then bring CLK_SYS up again if it was disabled */ 594 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 595 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
661 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); 596 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
662 597
663 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 598 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
664 599
@@ -742,19 +677,19 @@ static int configure_clock(struct snd_soc_codec *codec)
742 return -EINVAL; 677 return -EINVAL;
743 } 678 }
744 679
745 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1); 680 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
746 if (mclkdiv) 681 if (mclkdiv)
747 reg |= WM9081_MCLKDIV2; 682 reg |= WM9081_MCLKDIV2;
748 else 683 else
749 reg &= ~WM9081_MCLKDIV2; 684 reg &= ~WM9081_MCLKDIV2;
750 wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg); 685 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
751 686
752 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 687 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
753 if (fll) 688 if (fll)
754 reg |= WM9081_CLK_SRC_SEL; 689 reg |= WM9081_CLK_SRC_SEL;
755 else 690 else
756 reg &= ~WM9081_CLK_SRC_SEL; 691 reg &= ~WM9081_CLK_SRC_SEL;
757 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg); 692 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
758 693
759 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); 694 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
760 695
@@ -854,76 +789,76 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
854 789
855 case SND_SOC_BIAS_PREPARE: 790 case SND_SOC_BIAS_PREPARE:
856 /* VMID=2*40k */ 791 /* VMID=2*40k */
857 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 792 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
858 reg &= ~WM9081_VMID_SEL_MASK; 793 reg &= ~WM9081_VMID_SEL_MASK;
859 reg |= 0x2; 794 reg |= 0x2;
860 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 795 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
861 796
862 /* Normal bias current */ 797 /* Normal bias current */
863 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 798 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
864 reg &= ~WM9081_STBY_BIAS_ENA; 799 reg &= ~WM9081_STBY_BIAS_ENA;
865 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 800 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
866 break; 801 break;
867 802
868 case SND_SOC_BIAS_STANDBY: 803 case SND_SOC_BIAS_STANDBY:
869 /* Initial cold start */ 804 /* Initial cold start */
870 if (codec->bias_level == SND_SOC_BIAS_OFF) { 805 if (codec->bias_level == SND_SOC_BIAS_OFF) {
871 /* Disable LINEOUT discharge */ 806 /* Disable LINEOUT discharge */
872 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 807 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
873 reg &= ~WM9081_LINEOUT_DISCH; 808 reg &= ~WM9081_LINEOUT_DISCH;
874 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 809 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
875 810
876 /* Select startup bias source */ 811 /* Select startup bias source */
877 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 812 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
878 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; 813 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
879 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 814 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
880 815
881 /* VMID 2*4k; Soft VMID ramp enable */ 816 /* VMID 2*4k; Soft VMID ramp enable */
882 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 817 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
883 reg |= WM9081_VMID_RAMP | 0x6; 818 reg |= WM9081_VMID_RAMP | 0x6;
884 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 819 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
885 820
886 mdelay(100); 821 mdelay(100);
887 822
888 /* Normal bias enable & soft start off */ 823 /* Normal bias enable & soft start off */
889 reg |= WM9081_BIAS_ENA; 824 reg |= WM9081_BIAS_ENA;
890 reg &= ~WM9081_VMID_RAMP; 825 reg &= ~WM9081_VMID_RAMP;
891 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 826 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
892 827
893 /* Standard bias source */ 828 /* Standard bias source */
894 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 829 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
895 reg &= ~WM9081_BIAS_SRC; 830 reg &= ~WM9081_BIAS_SRC;
896 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 831 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
897 } 832 }
898 833
899 /* VMID 2*240k */ 834 /* VMID 2*240k */
900 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 835 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
901 reg &= ~WM9081_VMID_SEL_MASK; 836 reg &= ~WM9081_VMID_SEL_MASK;
902 reg |= 0x40; 837 reg |= 0x40;
903 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 838 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
904 839
905 /* Standby bias current on */ 840 /* Standby bias current on */
906 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 841 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
907 reg |= WM9081_STBY_BIAS_ENA; 842 reg |= WM9081_STBY_BIAS_ENA;
908 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 843 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
909 break; 844 break;
910 845
911 case SND_SOC_BIAS_OFF: 846 case SND_SOC_BIAS_OFF:
912 /* Startup bias source */ 847 /* Startup bias source */
913 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 848 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
914 reg |= WM9081_BIAS_SRC; 849 reg |= WM9081_BIAS_SRC;
915 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 850 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
916 851
917 /* Disable VMID and biases with soft ramping */ 852 /* Disable VMID and biases with soft ramping */
918 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 853 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
919 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); 854 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
920 reg |= WM9081_VMID_RAMP; 855 reg |= WM9081_VMID_RAMP;
921 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 856 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
922 857
923 /* Actively discharge LINEOUT */ 858 /* Actively discharge LINEOUT */
924 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 859 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
925 reg |= WM9081_LINEOUT_DISCH; 860 reg |= WM9081_LINEOUT_DISCH;
926 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 861 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
927 break; 862 break;
928 } 863 }
929 864
@@ -937,7 +872,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
937{ 872{
938 struct snd_soc_codec *codec = dai->codec; 873 struct snd_soc_codec *codec = dai->codec;
939 struct wm9081_priv *wm9081 = codec->private_data; 874 struct wm9081_priv *wm9081 = codec->private_data;
940 unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 875 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
941 876
942 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | 877 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
943 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); 878 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
@@ -1018,7 +953,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
1018 return -EINVAL; 953 return -EINVAL;
1019 } 954 }
1020 955
1021 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 956 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1022 957
1023 return 0; 958 return 0;
1024} 959}
@@ -1032,18 +967,18 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1032 int ret, i, best, best_val, cur_val; 967 int ret, i, best, best_val, cur_val;
1033 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; 968 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1034 969
1035 clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2); 970 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1036 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); 971 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1037 972
1038 aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 973 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1039 974
1040 aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 975 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1041 aif2 &= ~WM9081_AIF_WL_MASK; 976 aif2 &= ~WM9081_AIF_WL_MASK;
1042 977
1043 aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3); 978 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1044 aif3 &= ~WM9081_BCLK_DIV_MASK; 979 aif3 &= ~WM9081_BCLK_DIV_MASK;
1045 980
1046 aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4); 981 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1047 aif4 &= ~WM9081_LRCLK_RATE_MASK; 982 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1048 983
1049 /* What BCLK do we need? */ 984 /* What BCLK do we need? */
@@ -1157,22 +1092,22 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1157 s->name, s->rate); 1092 s->name, s->rate);
1158 1093
1159 /* If the EQ is enabled then disable it while we write out */ 1094 /* If the EQ is enabled then disable it while we write out */
1160 eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; 1095 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1161 if (eq1 & WM9081_EQ_ENA) 1096 if (eq1 & WM9081_EQ_ENA)
1162 wm9081_write(codec, WM9081_EQ_1, 0); 1097 snd_soc_write(codec, WM9081_EQ_1, 0);
1163 1098
1164 /* Write out the other values */ 1099 /* Write out the other values */
1165 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1100 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1166 wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]); 1101 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1167 1102
1168 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); 1103 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1169 wm9081_write(codec, WM9081_EQ_1, eq1); 1104 snd_soc_write(codec, WM9081_EQ_1, eq1);
1170 } 1105 }
1171 1106
1172 wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); 1107 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1173 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 1108 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1174 wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); 1109 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1175 wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); 1110 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1176 1111
1177 return 0; 1112 return 0;
1178} 1113}
@@ -1182,14 +1117,14 @@ static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1182 struct snd_soc_codec *codec = codec_dai->codec; 1117 struct snd_soc_codec *codec = codec_dai->codec;
1183 unsigned int reg; 1118 unsigned int reg;
1184 1119
1185 reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2); 1120 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1186 1121
1187 if (mute) 1122 if (mute)
1188 reg |= WM9081_DAC_MUTE; 1123 reg |= WM9081_DAC_MUTE;
1189 else 1124 else
1190 reg &= ~WM9081_DAC_MUTE; 1125 reg &= ~WM9081_DAC_MUTE;
1191 1126
1192 wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg); 1127 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1193 1128
1194 return 0; 1129 return 0;
1195} 1130}
@@ -1218,7 +1153,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1218 unsigned int mask, int slots) 1153 unsigned int mask, int slots)
1219{ 1154{
1220 struct snd_soc_codec *codec = dai->codec; 1155 struct snd_soc_codec *codec = dai->codec;
1221 unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 1156 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1222 1157
1223 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); 1158 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1224 1159
@@ -1243,7 +1178,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1243 return -EINVAL; 1178 return -EINVAL;
1244 } 1179 }
1245 1180
1246 wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); 1181 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1247 1182
1248 return 0; 1183 return 0;
1249} 1184}
@@ -1365,7 +1300,7 @@ static int wm9081_resume(struct platform_device *pdev)
1365 if (i == WM9081_SOFTWARE_RESET) 1300 if (i == WM9081_SOFTWARE_RESET)
1366 continue; 1301 continue;
1367 1302
1368 wm9081_write(codec, i, reg_cache[i]); 1303 snd_soc_write(codec, i, reg_cache[i]);
1369 } 1304 }
1370 1305
1371 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1306 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1385,7 +1320,8 @@ struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1385}; 1320};
1386EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081); 1321EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1387 1322
1388static int wm9081_register(struct wm9081_priv *wm9081) 1323static int wm9081_register(struct wm9081_priv *wm9081,
1324 enum snd_soc_control_type control)
1389{ 1325{
1390 struct snd_soc_codec *codec = &wm9081->codec; 1326 struct snd_soc_codec *codec = &wm9081->codec;
1391 int ret; 1327 int ret;
@@ -1404,19 +1340,24 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1404 codec->private_data = wm9081; 1340 codec->private_data = wm9081;
1405 codec->name = "WM9081"; 1341 codec->name = "WM9081";
1406 codec->owner = THIS_MODULE; 1342 codec->owner = THIS_MODULE;
1407 codec->read = wm9081_read;
1408 codec->write = wm9081_write;
1409 codec->dai = &wm9081_dai; 1343 codec->dai = &wm9081_dai;
1410 codec->num_dai = 1; 1344 codec->num_dai = 1;
1411 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache); 1345 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1412 codec->reg_cache = &wm9081->reg_cache; 1346 codec->reg_cache = &wm9081->reg_cache;
1413 codec->bias_level = SND_SOC_BIAS_OFF; 1347 codec->bias_level = SND_SOC_BIAS_OFF;
1414 codec->set_bias_level = wm9081_set_bias_level; 1348 codec->set_bias_level = wm9081_set_bias_level;
1349 codec->volatile_register = wm9081_volatile_register;
1415 1350
1416 memcpy(codec->reg_cache, wm9081_reg_defaults, 1351 memcpy(codec->reg_cache, wm9081_reg_defaults,
1417 sizeof(wm9081_reg_defaults)); 1352 sizeof(wm9081_reg_defaults));
1418 1353
1419 reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET); 1354 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1355 if (ret != 0) {
1356 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1357 return ret;
1358 }
1359
1360 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1420 if (reg != 0x9081) { 1361 if (reg != 0x9081) {
1421 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); 1362 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1422 ret = -EINVAL; 1363 ret = -EINVAL;
@@ -1432,10 +1373,10 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1432 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1373 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1433 1374
1434 /* Enable zero cross by default */ 1375 /* Enable zero cross by default */
1435 reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT); 1376 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1436 wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); 1377 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1437 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); 1378 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1438 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, 1379 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1439 reg | WM9081_SPKPGAZC); 1380 reg | WM9081_SPKPGAZC);
1440 1381
1441 wm9081_dai.dev = codec->dev; 1382 wm9081_dai.dev = codec->dev;
@@ -1490,7 +1431,7 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1490 1431
1491 codec->dev = &i2c->dev; 1432 codec->dev = &i2c->dev;
1492 1433
1493 return wm9081_register(wm9081); 1434 return wm9081_register(wm9081, SND_SOC_I2C);
1494} 1435}
1495 1436
1496static __devexit int wm9081_i2c_remove(struct i2c_client *client) 1437static __devexit int wm9081_i2c_remove(struct i2c_client *client)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 12:02:29 -0500