aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/wm9081.c
diff options
context:
space:
mode:
Diffstat (limited to 'sound/soc/codecs/wm9081.c')
-rw-r--r--sound/soc/codecs/wm9081.c317
1 files changed, 147 insertions, 170 deletions
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 86fc57e25f97..c64e55aa63b6 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -165,87 +165,23 @@ struct wm9081_priv {
165 int master; 165 int master;
166 int fll_fref; 166 int fll_fref;
167 int fll_fout; 167 int fll_fout;
168 int tdm_width;
168 struct wm9081_retune_mobile_config *retune; 169 struct wm9081_retune_mobile_config *retune;
169}; 170};
170 171
171static int wm9081_reg_is_volatile(int reg) 172static int wm9081_volatile_register(unsigned int reg)
172{ 173{
173 switch (reg) { 174 switch (reg) {
175 case WM9081_SOFTWARE_RESET:
176 return 1;
174 default: 177 default:
175 return 0; 178 return 0;
176 } 179 }
177} 180}
178 181
179static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned int reg)
181{
182 u16 *cache = codec->reg_cache;
183 BUG_ON(reg > WM9081_MAX_REGISTER);
184 return cache[reg];
185}
186
187static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
188{
189 struct i2c_msg xfer[2];
190 u16 data;
191 int ret;
192 struct i2c_client *client = codec->control_data;
193
194 BUG_ON(reg > WM9081_MAX_REGISTER);
195
196 /* Write register */
197 xfer[0].addr = client->addr;
198 xfer[0].flags = 0;
199 xfer[0].len = 1;
200 xfer[0].buf = ®
201
202 /* Read data */
203 xfer[1].addr = client->addr;
204 xfer[1].flags = I2C_M_RD;
205 xfer[1].len = 2;
206 xfer[1].buf = (u8 *)&data;
207
208 ret = i2c_transfer(client->adapter, xfer, 2);
209 if (ret != 2) {
210 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
211 return 0;
212 }
213
214 return (data >> 8) | ((data & 0xff) << 8);
215}
216
217static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
218{
219 if (wm9081_reg_is_volatile(reg))
220 return wm9081_read_hw(codec, reg);
221 else
222 return wm9081_read_reg_cache(codec, reg);
223}
224
225static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
228 u16 *cache = codec->reg_cache;
229 u8 data[3];
230
231 BUG_ON(reg > WM9081_MAX_REGISTER);
232
233 if (!wm9081_reg_is_volatile(reg))
234 cache[reg] = value;
235
236 data[0] = reg;
237 data[1] = value >> 8;
238 data[2] = value & 0x00ff;
239
240 if (codec->hw_write(codec->control_data, data, 3) == 3)
241 return 0;
242 else
243 return -EIO;
244}
245
246static int wm9081_reset(struct snd_soc_codec *codec) 182static int wm9081_reset(struct snd_soc_codec *codec)
247{ 183{
248 return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0); 184 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
249} 185}
250 186
251static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); 187static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
@@ -356,7 +292,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 292 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
357 unsigned int reg; 293 unsigned int reg;
358 294
359 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 295 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
360 if (reg & WM9081_SPK_MODE) 296 if (reg & WM9081_SPK_MODE)
361 ucontrol->value.integer.value[0] = 1; 297 ucontrol->value.integer.value[0] = 1;
362 else 298 else
@@ -375,8 +311,8 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol) 311 struct snd_ctl_elem_value *ucontrol)
376{ 312{
377 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 313 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378 unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 314 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
379 unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 315 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
380 316
381 /* Are we changing anything? */ 317 /* Are we changing anything? */
382 if (ucontrol->value.integer.value[0] == 318 if (ucontrol->value.integer.value[0] ==
@@ -397,7 +333,7 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
397 reg2 &= ~WM9081_SPK_MODE; 333 reg2 &= ~WM9081_SPK_MODE;
398 } 334 }
399 335
400 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); 336 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
401 337
402 return 0; 338 return 0;
403} 339}
@@ -456,7 +392,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event) 392 struct snd_kcontrol *kcontrol, int event)
457{ 393{
458 struct snd_soc_codec *codec = w->codec; 394 struct snd_soc_codec *codec = w->codec;
459 unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 395 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
460 396
461 switch (event) { 397 switch (event) {
462 case SND_SOC_DAPM_POST_PMU: 398 case SND_SOC_DAPM_POST_PMU:
@@ -468,7 +404,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
468 break; 404 break;
469 } 405 }
470 406
471 wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg); 407 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
472 408
473 return 0; 409 return 0;
474} 410}
@@ -607,7 +543,7 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
607 if (ret != 0) 543 if (ret != 0)
608 return ret; 544 return ret;
609 545
610 reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5); 546 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
611 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; 547 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
612 548
613 switch (fll_id) { 549 switch (fll_id) {
@@ -621,44 +557,44 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
621 } 557 }
622 558
623 /* Disable CLK_SYS while we reconfigure */ 559 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 560 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 561 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, 562 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
627 clk_sys_reg & ~WM9081_CLK_SYS_ENA); 563 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
628 564
629 /* Any FLL configuration change requires that the FLL be 565 /* Any FLL configuration change requires that the FLL be
630 * disabled first. */ 566 * disabled first. */
631 reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1); 567 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
632 reg1 &= ~WM9081_FLL_ENA; 568 reg1 &= ~WM9081_FLL_ENA;
633 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 569 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
634 570
635 /* Apply the configuration */ 571 /* Apply the configuration */
636 if (fll_div.k) 572 if (fll_div.k)
637 reg1 |= WM9081_FLL_FRAC_MASK; 573 reg1 |= WM9081_FLL_FRAC_MASK;
638 else 574 else
639 reg1 &= ~WM9081_FLL_FRAC_MASK; 575 reg1 &= ~WM9081_FLL_FRAC_MASK;
640 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 576 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
641 577
642 wm9081_write(codec, WM9081_FLL_CONTROL_2, 578 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
643 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | 579 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
644 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); 580 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
645 wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); 581 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
646 582
647 reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4); 583 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
648 reg4 &= ~WM9081_FLL_N_MASK; 584 reg4 &= ~WM9081_FLL_N_MASK;
649 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; 585 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
650 wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4); 586 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
651 587
652 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; 588 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
653 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 589 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
654 wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5); 590 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
655 591
656 /* Enable the FLL */ 592 /* Enable the FLL */
657 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 593 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
658 594
659 /* Then bring CLK_SYS up again if it was disabled */ 595 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 596 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
661 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); 597 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
662 598
663 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 599 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
664 600
@@ -707,6 +643,10 @@ static int configure_clock(struct snd_soc_codec *codec)
707 target > 3000000) 643 target > 3000000)
708 break; 644 break;
709 } 645 }
646
647 if (i == ARRAY_SIZE(clk_sys_rates))
648 return -EINVAL;
649
710 } else if (wm9081->fs) { 650 } else if (wm9081->fs) {
711 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { 651 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
712 new_sysclk = clk_sys_rates[i].ratio 652 new_sysclk = clk_sys_rates[i].ratio
@@ -714,6 +654,10 @@ static int configure_clock(struct snd_soc_codec *codec)
714 if (new_sysclk > 3000000) 654 if (new_sysclk > 3000000)
715 break; 655 break;
716 } 656 }
657
658 if (i == ARRAY_SIZE(clk_sys_rates))
659 return -EINVAL;
660
717 } else { 661 } else {
718 new_sysclk = 12288000; 662 new_sysclk = 12288000;
719 } 663 }
@@ -734,19 +678,19 @@ static int configure_clock(struct snd_soc_codec *codec)
734 return -EINVAL; 678 return -EINVAL;
735 } 679 }
736 680
737 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1); 681 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
738 if (mclkdiv) 682 if (mclkdiv)
739 reg |= WM9081_MCLKDIV2; 683 reg |= WM9081_MCLKDIV2;
740 else 684 else
741 reg &= ~WM9081_MCLKDIV2; 685 reg &= ~WM9081_MCLKDIV2;
742 wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg); 686 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
743 687
744 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 688 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
745 if (fll) 689 if (fll)
746 reg |= WM9081_CLK_SRC_SEL; 690 reg |= WM9081_CLK_SRC_SEL;
747 else 691 else
748 reg &= ~WM9081_CLK_SRC_SEL; 692 reg &= ~WM9081_CLK_SRC_SEL;
749 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg); 693 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
750 694
751 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); 695 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
752 696
@@ -846,76 +790,76 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
846 790
847 case SND_SOC_BIAS_PREPARE: 791 case SND_SOC_BIAS_PREPARE:
848 /* VMID=2*40k */ 792 /* VMID=2*40k */
849 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 793 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
850 reg &= ~WM9081_VMID_SEL_MASK; 794 reg &= ~WM9081_VMID_SEL_MASK;
851 reg |= 0x2; 795 reg |= 0x2;
852 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 796 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
853 797
854 /* Normal bias current */ 798 /* Normal bias current */
855 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 799 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
856 reg &= ~WM9081_STBY_BIAS_ENA; 800 reg &= ~WM9081_STBY_BIAS_ENA;
857 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 801 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
858 break; 802 break;
859 803
860 case SND_SOC_BIAS_STANDBY: 804 case SND_SOC_BIAS_STANDBY:
861 /* Initial cold start */ 805 /* Initial cold start */
862 if (codec->bias_level == SND_SOC_BIAS_OFF) { 806 if (codec->bias_level == SND_SOC_BIAS_OFF) {
863 /* Disable LINEOUT discharge */ 807 /* Disable LINEOUT discharge */
864 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 808 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
865 reg &= ~WM9081_LINEOUT_DISCH; 809 reg &= ~WM9081_LINEOUT_DISCH;
866 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 810 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
867 811
868 /* Select startup bias source */ 812 /* Select startup bias source */
869 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 813 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
870 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; 814 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
871 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 815 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
872 816
873 /* VMID 2*4k; Soft VMID ramp enable */ 817 /* VMID 2*4k; Soft VMID ramp enable */
874 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 818 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
875 reg |= WM9081_VMID_RAMP | 0x6; 819 reg |= WM9081_VMID_RAMP | 0x6;
876 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 820 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
877 821
878 mdelay(100); 822 mdelay(100);
879 823
880 /* Normal bias enable & soft start off */ 824 /* Normal bias enable & soft start off */
881 reg |= WM9081_BIAS_ENA; 825 reg |= WM9081_BIAS_ENA;
882 reg &= ~WM9081_VMID_RAMP; 826 reg &= ~WM9081_VMID_RAMP;
883 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 827 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
884 828
885 /* Standard bias source */ 829 /* Standard bias source */
886 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 830 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
887 reg &= ~WM9081_BIAS_SRC; 831 reg &= ~WM9081_BIAS_SRC;
888 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 832 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
889 } 833 }
890 834
891 /* VMID 2*240k */ 835 /* VMID 2*240k */
892 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 836 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
893 reg &= ~WM9081_VMID_SEL_MASK; 837 reg &= ~WM9081_VMID_SEL_MASK;
894 reg |= 0x40; 838 reg |= 0x40;
895 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 839 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
896 840
897 /* Standby bias current on */ 841 /* Standby bias current on */
898 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 842 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
899 reg |= WM9081_STBY_BIAS_ENA; 843 reg |= WM9081_STBY_BIAS_ENA;
900 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 844 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
901 break; 845 break;
902 846
903 case SND_SOC_BIAS_OFF: 847 case SND_SOC_BIAS_OFF:
904 /* Startup bias source */ 848 /* Startup bias source */
905 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 849 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
906 reg |= WM9081_BIAS_SRC; 850 reg |= WM9081_BIAS_SRC;
907 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 851 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
908 852
909 /* Disable VMID and biases with soft ramping */ 853 /* Disable VMID and biases with soft ramping */
910 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 854 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
911 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); 855 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
912 reg |= WM9081_VMID_RAMP; 856 reg |= WM9081_VMID_RAMP;
913 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 857 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
914 858
915 /* Actively discharge LINEOUT */ 859 /* Actively discharge LINEOUT */
916 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 860 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
917 reg |= WM9081_LINEOUT_DISCH; 861 reg |= WM9081_LINEOUT_DISCH;
918 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 862 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
919 break; 863 break;
920 } 864 }
921 865
@@ -929,7 +873,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
929{ 873{
930 struct snd_soc_codec *codec = dai->codec; 874 struct snd_soc_codec *codec = dai->codec;
931 struct wm9081_priv *wm9081 = codec->private_data; 875 struct wm9081_priv *wm9081 = codec->private_data;
932 unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 876 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
933 877
934 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | 878 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
935 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); 879 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
@@ -1010,7 +954,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
1010 return -EINVAL; 954 return -EINVAL;
1011 } 955 }
1012 956
1013 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 957 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1014 958
1015 return 0; 959 return 0;
1016} 960}
@@ -1024,47 +968,51 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1024 int ret, i, best, best_val, cur_val; 968 int ret, i, best, best_val, cur_val;
1025 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; 969 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1026 970
1027 clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2); 971 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1028 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); 972 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1029 973
1030 aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 974 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1031 975
1032 aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 976 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1033 aif2 &= ~WM9081_AIF_WL_MASK; 977 aif2 &= ~WM9081_AIF_WL_MASK;
1034 978
1035 aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3); 979 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1036 aif3 &= ~WM9081_BCLK_DIV_MASK; 980 aif3 &= ~WM9081_BCLK_DIV_MASK;
1037 981
1038 aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4); 982 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1039 aif4 &= ~WM9081_LRCLK_RATE_MASK; 983 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1040 984
1041 /* What BCLK do we need? */
1042 wm9081->fs = params_rate(params); 985 wm9081->fs = params_rate(params);
1043 wm9081->bclk = 2 * wm9081->fs;
1044 switch (params_format(params)) {
1045 case SNDRV_PCM_FORMAT_S16_LE:
1046 wm9081->bclk *= 16;
1047 break;
1048 case SNDRV_PCM_FORMAT_S20_3LE:
1049 wm9081->bclk *= 20;
1050 aif2 |= 0x4;
1051 break;
1052 case SNDRV_PCM_FORMAT_S24_LE:
1053 wm9081->bclk *= 24;
1054 aif2 |= 0x8;
1055 break;
1056 case SNDRV_PCM_FORMAT_S32_LE:
1057 wm9081->bclk *= 32;
1058 aif2 |= 0xc;
1059 break;
1060 default:
1061 return -EINVAL;
1062 }
1063 986
1064 if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) { 987 if (wm9081->tdm_width) {
988 /* If TDM is set up then that fixes our BCLK. */
1065 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >> 989 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1066 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1; 990 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1067 wm9081->bclk *= slots; 991
992 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
993 } else {
994 /* Otherwise work out a BCLK from the sample size */
995 wm9081->bclk = 2 * wm9081->fs;
996
997 switch (params_format(params)) {
998 case SNDRV_PCM_FORMAT_S16_LE:
999 wm9081->bclk *= 16;
1000 break;
1001 case SNDRV_PCM_FORMAT_S20_3LE:
1002 wm9081->bclk *= 20;
1003 aif2 |= 0x4;
1004 break;
1005 case SNDRV_PCM_FORMAT_S24_LE:
1006 wm9081->bclk *= 24;
1007 aif2 |= 0x8;
1008 break;
1009 case SNDRV_PCM_FORMAT_S32_LE:
1010 wm9081->bclk *= 32;
1011 aif2 |= 0xc;
1012 break;
1013 default:
1014 return -EINVAL;
1015 }
1068 } 1016 }
1069 1017
1070 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk); 1018 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
@@ -1149,22 +1097,22 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1149 s->name, s->rate); 1097 s->name, s->rate);
1150 1098
1151 /* If the EQ is enabled then disable it while we write out */ 1099 /* If the EQ is enabled then disable it while we write out */
1152 eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; 1100 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1153 if (eq1 & WM9081_EQ_ENA) 1101 if (eq1 & WM9081_EQ_ENA)
1154 wm9081_write(codec, WM9081_EQ_1, 0); 1102 snd_soc_write(codec, WM9081_EQ_1, 0);
1155 1103
1156 /* Write out the other values */ 1104 /* Write out the other values */
1157 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1105 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1158 wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]); 1106 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1159 1107
1160 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); 1108 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1161 wm9081_write(codec, WM9081_EQ_1, eq1); 1109 snd_soc_write(codec, WM9081_EQ_1, eq1);
1162 } 1110 }
1163 1111
1164 wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); 1112 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1165 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 1113 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1166 wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); 1114 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1167 wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); 1115 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1168 1116
1169 return 0; 1117 return 0;
1170} 1118}
@@ -1174,14 +1122,14 @@ static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1174 struct snd_soc_codec *codec = codec_dai->codec; 1122 struct snd_soc_codec *codec = codec_dai->codec;
1175 unsigned int reg; 1123 unsigned int reg;
1176 1124
1177 reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2); 1125 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1178 1126
1179 if (mute) 1127 if (mute)
1180 reg |= WM9081_DAC_MUTE; 1128 reg |= WM9081_DAC_MUTE;
1181 else 1129 else
1182 reg &= ~WM9081_DAC_MUTE; 1130 reg &= ~WM9081_DAC_MUTE;
1183 1131
1184 wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg); 1132 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1185 1133
1186 return 0; 1134 return 0;
1187} 1135}
@@ -1207,19 +1155,25 @@ static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1207} 1155}
1208 1156
1209static int wm9081_set_tdm_slot(struct snd_soc_dai *dai, 1157static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1210 unsigned int mask, int slots) 1158 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1211{ 1159{
1212 struct snd_soc_codec *codec = dai->codec; 1160 struct snd_soc_codec *codec = dai->codec;
1213 unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 1161 struct wm9081_priv *wm9081 = codec->private_data;
1162 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1214 1163
1215 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); 1164 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1216 1165
1217 if (slots < 1 || slots > 4) 1166 if (slots < 0 || slots > 4)
1218 return -EINVAL; 1167 return -EINVAL;
1219 1168
1169 wm9081->tdm_width = slot_width;
1170
1171 if (slots == 0)
1172 slots = 1;
1173
1220 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT; 1174 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1221 1175
1222 switch (mask) { 1176 switch (rx_mask) {
1223 case 1: 1177 case 1:
1224 break; 1178 break;
1225 case 2: 1179 case 2:
@@ -1235,7 +1189,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1235 return -EINVAL; 1189 return -EINVAL;
1236 } 1190 }
1237 1191
1238 wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); 1192 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1239 1193
1240 return 0; 1194 return 0;
1241} 1195}
@@ -1357,7 +1311,7 @@ static int wm9081_resume(struct platform_device *pdev)
1357 if (i == WM9081_SOFTWARE_RESET) 1311 if (i == WM9081_SOFTWARE_RESET)
1358 continue; 1312 continue;
1359 1313
1360 wm9081_write(codec, i, reg_cache[i]); 1314 snd_soc_write(codec, i, reg_cache[i]);
1361 } 1315 }
1362 1316
1363 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1317 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1377,7 +1331,8 @@ struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1377}; 1331};
1378EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081); 1332EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1379 1333
1380static int wm9081_register(struct wm9081_priv *wm9081) 1334static int wm9081_register(struct wm9081_priv *wm9081,
1335 enum snd_soc_control_type control)
1381{ 1336{
1382 struct snd_soc_codec *codec = &wm9081->codec; 1337 struct snd_soc_codec *codec = &wm9081->codec;
1383 int ret; 1338 int ret;
@@ -1396,19 +1351,24 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1396 codec->private_data = wm9081; 1351 codec->private_data = wm9081;
1397 codec->name = "WM9081"; 1352 codec->name = "WM9081";
1398 codec->owner = THIS_MODULE; 1353 codec->owner = THIS_MODULE;
1399 codec->read = wm9081_read;
1400 codec->write = wm9081_write;
1401 codec->dai = &wm9081_dai; 1354 codec->dai = &wm9081_dai;
1402 codec->num_dai = 1; 1355 codec->num_dai = 1;
1403 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache); 1356 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1404 codec->reg_cache = &wm9081->reg_cache; 1357 codec->reg_cache = &wm9081->reg_cache;
1405 codec->bias_level = SND_SOC_BIAS_OFF; 1358 codec->bias_level = SND_SOC_BIAS_OFF;
1406 codec->set_bias_level = wm9081_set_bias_level; 1359 codec->set_bias_level = wm9081_set_bias_level;
1360 codec->volatile_register = wm9081_volatile_register;
1407 1361
1408 memcpy(codec->reg_cache, wm9081_reg_defaults, 1362 memcpy(codec->reg_cache, wm9081_reg_defaults,
1409 sizeof(wm9081_reg_defaults)); 1363 sizeof(wm9081_reg_defaults));
1410 1364
1411 reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET); 1365 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1366 if (ret != 0) {
1367 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1368 return ret;
1369 }
1370
1371 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1412 if (reg != 0x9081) { 1372 if (reg != 0x9081) {
1413 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); 1373 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1414 ret = -EINVAL; 1374 ret = -EINVAL;
@@ -1424,10 +1384,10 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1424 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1384 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1425 1385
1426 /* Enable zero cross by default */ 1386 /* Enable zero cross by default */
1427 reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT); 1387 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1428 wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); 1388 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1429 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); 1389 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1430 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, 1390 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1431 reg | WM9081_SPKPGAZC); 1391 reg | WM9081_SPKPGAZC);
1432 1392
1433 wm9081_dai.dev = codec->dev; 1393 wm9081_dai.dev = codec->dev;
@@ -1482,7 +1442,7 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1482 1442
1483 codec->dev = &i2c->dev; 1443 codec->dev = &i2c->dev;
1484 1444
1485 return wm9081_register(wm9081); 1445 return wm9081_register(wm9081, SND_SOC_I2C);
1486} 1446}
1487 1447
1488static __devexit int wm9081_i2c_remove(struct i2c_client *client) 1448static __devexit int wm9081_i2c_remove(struct i2c_client *client)
@@ -1492,6 +1452,21 @@ static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1492 return 0; 1452 return 0;
1493} 1453}
1494 1454
1455#ifdef CONFIG_PM
1456static int wm9081_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1457{
1458 return snd_soc_suspend_device(&client->dev);
1459}
1460
1461static int wm9081_i2c_resume(struct i2c_client *client)
1462{
1463 return snd_soc_resume_device(&client->dev);
1464}
1465#else
1466#define wm9081_i2c_suspend NULL
1467#define wm9081_i2c_resume NULL
1468#endif
1469
1495static const struct i2c_device_id wm9081_i2c_id[] = { 1470static const struct i2c_device_id wm9081_i2c_id[] = {
1496 { "wm9081", 0 }, 1471 { "wm9081", 0 },
1497 { } 1472 { }
@@ -1505,6 +1480,8 @@ static struct i2c_driver wm9081_i2c_driver = {
1505 }, 1480 },
1506 .probe = wm9081_i2c_probe, 1481 .probe = wm9081_i2c_probe,
1507 .remove = __devexit_p(wm9081_i2c_remove), 1482 .remove = __devexit_p(wm9081_i2c_remove),
1483 .suspend = wm9081_i2c_suspend,
1484 .resume = wm9081_i2c_resume,
1508 .id_table = wm9081_i2c_id, 1485 .id_table = wm9081_i2c_id,
1509}; 1486};
1510 1487
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 06:51:49 -0500