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-rw-r--r--sound/soc/codecs/wm8994.c2544
1 files changed, 831 insertions, 1713 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 4d3e6f1ac584..247a6a99feb8 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -18,15 +18,17 @@
18#include <linux/pm.h> 18#include <linux/pm.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
21#include <linux/regulator/consumer.h> 22#include <linux/regulator/consumer.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23#include <sound/core.h> 24#include <sound/core.h>
25#include <sound/jack.h>
24#include <sound/pcm.h> 26#include <sound/pcm.h>
25#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
26#include <sound/soc.h> 28#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 29#include <sound/initval.h>
29#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
30 32
31#include <linux/mfd/wm8994/core.h> 33#include <linux/mfd/wm8994/core.h>
32#include <linux/mfd/wm8994/registers.h> 34#include <linux/mfd/wm8994/registers.h>
@@ -57,8 +59,6 @@ static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF2_EQ_GAINS_1, 59 WM8994_AIF2_EQ_GAINS_1,
58}; 60};
59 61
60#define WM8994_REG_CACHE_SIZE 0x621
61
62struct wm8994_micdet { 62struct wm8994_micdet {
63 struct snd_soc_jack *jack; 63 struct snd_soc_jack *jack;
64 int det; 64 int det;
@@ -71,7 +71,6 @@ struct wm8994_priv {
71 enum snd_soc_control_type control_type; 71 enum snd_soc_control_type control_type;
72 void *control_data; 72 void *control_data;
73 struct snd_soc_codec *codec; 73 struct snd_soc_codec *codec;
74 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
75 int sysclk[2]; 74 int sysclk[2];
76 int sysclk_rate[2]; 75 int sysclk_rate[2];
77 int mclk[2]; 76 int mclk[2];
@@ -81,6 +80,8 @@ struct wm8994_priv {
81 int dac_rates[2]; 80 int dac_rates[2];
82 int lrclk_shared[2]; 81 int lrclk_shared[2];
83 82
83 int mbc_ena[3];
84
84 /* Platform dependant DRC configuration */ 85 /* Platform dependant DRC configuration */
85 const char **drc_texts; 86 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC]; 87 int drc_cfg[WM8994_NUM_DRC];
@@ -92,1588 +93,22 @@ struct wm8994_priv {
92 int retune_mobile_cfg[WM8994_NUM_EQ]; 93 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum; 94 struct soc_enum retune_mobile_enum;
94 95
96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
95 struct wm8994_micdet micdet[2]; 101 struct wm8994_micdet micdet[2];
96 102
103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
107
97 int revision; 108 int revision;
98 struct wm8994_pdata *pdata; 109 struct wm8994_pdata *pdata;
99}; 110};
100 111
101static const struct {
102 unsigned short readable; /* Mask of readable bits */
103 unsigned short writable; /* Mask of writable bits */
104} access_masks[] = {
105 { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
106 { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
107 { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
108 { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
109 { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
110 { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
111 { 0x003F, 0x003F }, /* R6 - Power Management (6) */
112 { 0x0000, 0x0000 }, /* R7 */
113 { 0x0000, 0x0000 }, /* R8 */
114 { 0x0000, 0x0000 }, /* R9 */
115 { 0x0000, 0x0000 }, /* R10 */
116 { 0x0000, 0x0000 }, /* R11 */
117 { 0x0000, 0x0000 }, /* R12 */
118 { 0x0000, 0x0000 }, /* R13 */
119 { 0x0000, 0x0000 }, /* R14 */
120 { 0x0000, 0x0000 }, /* R15 */
121 { 0x0000, 0x0000 }, /* R16 */
122 { 0x0000, 0x0000 }, /* R17 */
123 { 0x0000, 0x0000 }, /* R18 */
124 { 0x0000, 0x0000 }, /* R19 */
125 { 0x0000, 0x0000 }, /* R20 */
126 { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
127 { 0x0000, 0x0000 }, /* R22 */
128 { 0x0000, 0x0000 }, /* R23 */
129 { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
130 { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
131 { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
132 { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
133 { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
134 { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
135 { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
136 { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
137 { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
138 { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
139 { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
140 { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
141 { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
142 { 0x003F, 0x003F }, /* R37 - ClassD */
143 { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
144 { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
145 { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
146 { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
147 { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
148 { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
149 { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
150 { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
151 { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
152 { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
153 { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
154 { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
155 { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
156 { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
157 { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
158 { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
159 { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
160 { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
161 { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
162 { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
163 { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
164 { 0x000F, 0x000F }, /* R59 - LDO 1 */
165 { 0x0007, 0x0007 }, /* R60 - LDO 2 */
166 { 0x0000, 0x0000 }, /* R61 */
167 { 0x0000, 0x0000 }, /* R62 */
168 { 0x0000, 0x0000 }, /* R63 */
169 { 0x0000, 0x0000 }, /* R64 */
170 { 0x0000, 0x0000 }, /* R65 */
171 { 0x0000, 0x0000 }, /* R66 */
172 { 0x0000, 0x0000 }, /* R67 */
173 { 0x0000, 0x0000 }, /* R68 */
174 { 0x0000, 0x0000 }, /* R69 */
175 { 0x0000, 0x0000 }, /* R70 */
176 { 0x0000, 0x0000 }, /* R71 */
177 { 0x0000, 0x0000 }, /* R72 */
178 { 0x0000, 0x0000 }, /* R73 */
179 { 0x0000, 0x0000 }, /* R74 */
180 { 0x0000, 0x0000 }, /* R75 */
181 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
182 { 0x0000, 0x0000 }, /* R77 */
183 { 0x0000, 0x0000 }, /* R78 */
184 { 0x0000, 0x0000 }, /* R79 */
185 { 0x0000, 0x0000 }, /* R80 */
186 { 0x0301, 0x0301 }, /* R81 - Class W (1) */
187 { 0x0000, 0x0000 }, /* R82 */
188 { 0x0000, 0x0000 }, /* R83 */
189 { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
190 { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
191 { 0x0000, 0x0000 }, /* R86 */
192 { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
193 { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
194 { 0x0000, 0x0000 }, /* R89 */
195 { 0x0000, 0x0000 }, /* R90 */
196 { 0x0000, 0x0000 }, /* R91 */
197 { 0x0000, 0x0000 }, /* R92 */
198 { 0x0000, 0x0000 }, /* R93 */
199 { 0x0000, 0x0000 }, /* R94 */
200 { 0x0000, 0x0000 }, /* R95 */
201 { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
202 { 0x0000, 0x0000 }, /* R97 */
203 { 0x0000, 0x0000 }, /* R98 */
204 { 0x0000, 0x0000 }, /* R99 */
205 { 0x0000, 0x0000 }, /* R100 */
206 { 0x0000, 0x0000 }, /* R101 */
207 { 0x0000, 0x0000 }, /* R102 */
208 { 0x0000, 0x0000 }, /* R103 */
209 { 0x0000, 0x0000 }, /* R104 */
210 { 0x0000, 0x0000 }, /* R105 */
211 { 0x0000, 0x0000 }, /* R106 */
212 { 0x0000, 0x0000 }, /* R107 */
213 { 0x0000, 0x0000 }, /* R108 */
214 { 0x0000, 0x0000 }, /* R109 */
215 { 0x0000, 0x0000 }, /* R110 */
216 { 0x0000, 0x0000 }, /* R111 */
217 { 0x0000, 0x0000 }, /* R112 */
218 { 0x0000, 0x0000 }, /* R113 */
219 { 0x0000, 0x0000 }, /* R114 */
220 { 0x0000, 0x0000 }, /* R115 */
221 { 0x0000, 0x0000 }, /* R116 */
222 { 0x0000, 0x0000 }, /* R117 */
223 { 0x0000, 0x0000 }, /* R118 */
224 { 0x0000, 0x0000 }, /* R119 */
225 { 0x0000, 0x0000 }, /* R120 */
226 { 0x0000, 0x0000 }, /* R121 */
227 { 0x0000, 0x0000 }, /* R122 */
228 { 0x0000, 0x0000 }, /* R123 */
229 { 0x0000, 0x0000 }, /* R124 */
230 { 0x0000, 0x0000 }, /* R125 */
231 { 0x0000, 0x0000 }, /* R126 */
232 { 0x0000, 0x0000 }, /* R127 */
233 { 0x0000, 0x0000 }, /* R128 */
234 { 0x0000, 0x0000 }, /* R129 */
235 { 0x0000, 0x0000 }, /* R130 */
236 { 0x0000, 0x0000 }, /* R131 */
237 { 0x0000, 0x0000 }, /* R132 */
238 { 0x0000, 0x0000 }, /* R133 */
239 { 0x0000, 0x0000 }, /* R134 */
240 { 0x0000, 0x0000 }, /* R135 */
241 { 0x0000, 0x0000 }, /* R136 */
242 { 0x0000, 0x0000 }, /* R137 */
243 { 0x0000, 0x0000 }, /* R138 */
244 { 0x0000, 0x0000 }, /* R139 */
245 { 0x0000, 0x0000 }, /* R140 */
246 { 0x0000, 0x0000 }, /* R141 */
247 { 0x0000, 0x0000 }, /* R142 */
248 { 0x0000, 0x0000 }, /* R143 */
249 { 0x0000, 0x0000 }, /* R144 */
250 { 0x0000, 0x0000 }, /* R145 */
251 { 0x0000, 0x0000 }, /* R146 */
252 { 0x0000, 0x0000 }, /* R147 */
253 { 0x0000, 0x0000 }, /* R148 */
254 { 0x0000, 0x0000 }, /* R149 */
255 { 0x0000, 0x0000 }, /* R150 */
256 { 0x0000, 0x0000 }, /* R151 */
257 { 0x0000, 0x0000 }, /* R152 */
258 { 0x0000, 0x0000 }, /* R153 */
259 { 0x0000, 0x0000 }, /* R154 */
260 { 0x0000, 0x0000 }, /* R155 */
261 { 0x0000, 0x0000 }, /* R156 */
262 { 0x0000, 0x0000 }, /* R157 */
263 { 0x0000, 0x0000 }, /* R158 */
264 { 0x0000, 0x0000 }, /* R159 */
265 { 0x0000, 0x0000 }, /* R160 */
266 { 0x0000, 0x0000 }, /* R161 */
267 { 0x0000, 0x0000 }, /* R162 */
268 { 0x0000, 0x0000 }, /* R163 */
269 { 0x0000, 0x0000 }, /* R164 */
270 { 0x0000, 0x0000 }, /* R165 */
271 { 0x0000, 0x0000 }, /* R166 */
272 { 0x0000, 0x0000 }, /* R167 */
273 { 0x0000, 0x0000 }, /* R168 */
274 { 0x0000, 0x0000 }, /* R169 */
275 { 0x0000, 0x0000 }, /* R170 */
276 { 0x0000, 0x0000 }, /* R171 */
277 { 0x0000, 0x0000 }, /* R172 */
278 { 0x0000, 0x0000 }, /* R173 */
279 { 0x0000, 0x0000 }, /* R174 */
280 { 0x0000, 0x0000 }, /* R175 */
281 { 0x0000, 0x0000 }, /* R176 */
282 { 0x0000, 0x0000 }, /* R177 */
283 { 0x0000, 0x0000 }, /* R178 */
284 { 0x0000, 0x0000 }, /* R179 */
285 { 0x0000, 0x0000 }, /* R180 */
286 { 0x0000, 0x0000 }, /* R181 */
287 { 0x0000, 0x0000 }, /* R182 */
288 { 0x0000, 0x0000 }, /* R183 */
289 { 0x0000, 0x0000 }, /* R184 */
290 { 0x0000, 0x0000 }, /* R185 */
291 { 0x0000, 0x0000 }, /* R186 */
292 { 0x0000, 0x0000 }, /* R187 */
293 { 0x0000, 0x0000 }, /* R188 */
294 { 0x0000, 0x0000 }, /* R189 */
295 { 0x0000, 0x0000 }, /* R190 */
296 { 0x0000, 0x0000 }, /* R191 */
297 { 0x0000, 0x0000 }, /* R192 */
298 { 0x0000, 0x0000 }, /* R193 */
299 { 0x0000, 0x0000 }, /* R194 */
300 { 0x0000, 0x0000 }, /* R195 */
301 { 0x0000, 0x0000 }, /* R196 */
302 { 0x0000, 0x0000 }, /* R197 */
303 { 0x0000, 0x0000 }, /* R198 */
304 { 0x0000, 0x0000 }, /* R199 */
305 { 0x0000, 0x0000 }, /* R200 */
306 { 0x0000, 0x0000 }, /* R201 */
307 { 0x0000, 0x0000 }, /* R202 */
308 { 0x0000, 0x0000 }, /* R203 */
309 { 0x0000, 0x0000 }, /* R204 */
310 { 0x0000, 0x0000 }, /* R205 */
311 { 0x0000, 0x0000 }, /* R206 */
312 { 0x0000, 0x0000 }, /* R207 */
313 { 0x0000, 0x0000 }, /* R208 */
314 { 0x0000, 0x0000 }, /* R209 */
315 { 0x0000, 0x0000 }, /* R210 */
316 { 0x0000, 0x0000 }, /* R211 */
317 { 0x0000, 0x0000 }, /* R212 */
318 { 0x0000, 0x0000 }, /* R213 */
319 { 0x0000, 0x0000 }, /* R214 */
320 { 0x0000, 0x0000 }, /* R215 */
321 { 0x0000, 0x0000 }, /* R216 */
322 { 0x0000, 0x0000 }, /* R217 */
323 { 0x0000, 0x0000 }, /* R218 */
324 { 0x0000, 0x0000 }, /* R219 */
325 { 0x0000, 0x0000 }, /* R220 */
326 { 0x0000, 0x0000 }, /* R221 */
327 { 0x0000, 0x0000 }, /* R222 */
328 { 0x0000, 0x0000 }, /* R223 */
329 { 0x0000, 0x0000 }, /* R224 */
330 { 0x0000, 0x0000 }, /* R225 */
331 { 0x0000, 0x0000 }, /* R226 */
332 { 0x0000, 0x0000 }, /* R227 */
333 { 0x0000, 0x0000 }, /* R228 */
334 { 0x0000, 0x0000 }, /* R229 */
335 { 0x0000, 0x0000 }, /* R230 */
336 { 0x0000, 0x0000 }, /* R231 */
337 { 0x0000, 0x0000 }, /* R232 */
338 { 0x0000, 0x0000 }, /* R233 */
339 { 0x0000, 0x0000 }, /* R234 */
340 { 0x0000, 0x0000 }, /* R235 */
341 { 0x0000, 0x0000 }, /* R236 */
342 { 0x0000, 0x0000 }, /* R237 */
343 { 0x0000, 0x0000 }, /* R238 */
344 { 0x0000, 0x0000 }, /* R239 */
345 { 0x0000, 0x0000 }, /* R240 */
346 { 0x0000, 0x0000 }, /* R241 */
347 { 0x0000, 0x0000 }, /* R242 */
348 { 0x0000, 0x0000 }, /* R243 */
349 { 0x0000, 0x0000 }, /* R244 */
350 { 0x0000, 0x0000 }, /* R245 */
351 { 0x0000, 0x0000 }, /* R246 */
352 { 0x0000, 0x0000 }, /* R247 */
353 { 0x0000, 0x0000 }, /* R248 */
354 { 0x0000, 0x0000 }, /* R249 */
355 { 0x0000, 0x0000 }, /* R250 */
356 { 0x0000, 0x0000 }, /* R251 */
357 { 0x0000, 0x0000 }, /* R252 */
358 { 0x0000, 0x0000 }, /* R253 */
359 { 0x0000, 0x0000 }, /* R254 */
360 { 0x0000, 0x0000 }, /* R255 */
361 { 0x000F, 0x0000 }, /* R256 - Chip Revision */
362 { 0x0074, 0x0074 }, /* R257 - Control Interface */
363 { 0x0000, 0x0000 }, /* R258 */
364 { 0x0000, 0x0000 }, /* R259 */
365 { 0x0000, 0x0000 }, /* R260 */
366 { 0x0000, 0x0000 }, /* R261 */
367 { 0x0000, 0x0000 }, /* R262 */
368 { 0x0000, 0x0000 }, /* R263 */
369 { 0x0000, 0x0000 }, /* R264 */
370 { 0x0000, 0x0000 }, /* R265 */
371 { 0x0000, 0x0000 }, /* R266 */
372 { 0x0000, 0x0000 }, /* R267 */
373 { 0x0000, 0x0000 }, /* R268 */
374 { 0x0000, 0x0000 }, /* R269 */
375 { 0x0000, 0x0000 }, /* R270 */
376 { 0x0000, 0x0000 }, /* R271 */
377 { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
378 { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
379 { 0x0000, 0x0000 }, /* R274 */
380 { 0x0000, 0x0000 }, /* R275 */
381 { 0x0000, 0x0000 }, /* R276 */
382 { 0x0000, 0x0000 }, /* R277 */
383 { 0x0000, 0x0000 }, /* R278 */
384 { 0x0000, 0x0000 }, /* R279 */
385 { 0x0000, 0x0000 }, /* R280 */
386 { 0x0000, 0x0000 }, /* R281 */
387 { 0x0000, 0x0000 }, /* R282 */
388 { 0x0000, 0x0000 }, /* R283 */
389 { 0x0000, 0x0000 }, /* R284 */
390 { 0x0000, 0x0000 }, /* R285 */
391 { 0x0000, 0x0000 }, /* R286 */
392 { 0x0000, 0x0000 }, /* R287 */
393 { 0x0000, 0x0000 }, /* R288 */
394 { 0x0000, 0x0000 }, /* R289 */
395 { 0x0000, 0x0000 }, /* R290 */
396 { 0x0000, 0x0000 }, /* R291 */
397 { 0x0000, 0x0000 }, /* R292 */
398 { 0x0000, 0x0000 }, /* R293 */
399 { 0x0000, 0x0000 }, /* R294 */
400 { 0x0000, 0x0000 }, /* R295 */
401 { 0x0000, 0x0000 }, /* R296 */
402 { 0x0000, 0x0000 }, /* R297 */
403 { 0x0000, 0x0000 }, /* R298 */
404 { 0x0000, 0x0000 }, /* R299 */
405 { 0x0000, 0x0000 }, /* R300 */
406 { 0x0000, 0x0000 }, /* R301 */
407 { 0x0000, 0x0000 }, /* R302 */
408 { 0x0000, 0x0000 }, /* R303 */
409 { 0x0000, 0x0000 }, /* R304 */
410 { 0x0000, 0x0000 }, /* R305 */
411 { 0x0000, 0x0000 }, /* R306 */
412 { 0x0000, 0x0000 }, /* R307 */
413 { 0x0000, 0x0000 }, /* R308 */
414 { 0x0000, 0x0000 }, /* R309 */
415 { 0x0000, 0x0000 }, /* R310 */
416 { 0x0000, 0x0000 }, /* R311 */
417 { 0x0000, 0x0000 }, /* R312 */
418 { 0x0000, 0x0000 }, /* R313 */
419 { 0x0000, 0x0000 }, /* R314 */
420 { 0x0000, 0x0000 }, /* R315 */
421 { 0x0000, 0x0000 }, /* R316 */
422 { 0x0000, 0x0000 }, /* R317 */
423 { 0x0000, 0x0000 }, /* R318 */
424 { 0x0000, 0x0000 }, /* R319 */
425 { 0x0000, 0x0000 }, /* R320 */
426 { 0x0000, 0x0000 }, /* R321 */
427 { 0x0000, 0x0000 }, /* R322 */
428 { 0x0000, 0x0000 }, /* R323 */
429 { 0x0000, 0x0000 }, /* R324 */
430 { 0x0000, 0x0000 }, /* R325 */
431 { 0x0000, 0x0000 }, /* R326 */
432 { 0x0000, 0x0000 }, /* R327 */
433 { 0x0000, 0x0000 }, /* R328 */
434 { 0x0000, 0x0000 }, /* R329 */
435 { 0x0000, 0x0000 }, /* R330 */
436 { 0x0000, 0x0000 }, /* R331 */
437 { 0x0000, 0x0000 }, /* R332 */
438 { 0x0000, 0x0000 }, /* R333 */
439 { 0x0000, 0x0000 }, /* R334 */
440 { 0x0000, 0x0000 }, /* R335 */
441 { 0x0000, 0x0000 }, /* R336 */
442 { 0x0000, 0x0000 }, /* R337 */
443 { 0x0000, 0x0000 }, /* R338 */
444 { 0x0000, 0x0000 }, /* R339 */
445 { 0x0000, 0x0000 }, /* R340 */
446 { 0x0000, 0x0000 }, /* R341 */
447 { 0x0000, 0x0000 }, /* R342 */
448 { 0x0000, 0x0000 }, /* R343 */
449 { 0x0000, 0x0000 }, /* R344 */
450 { 0x0000, 0x0000 }, /* R345 */
451 { 0x0000, 0x0000 }, /* R346 */
452 { 0x0000, 0x0000 }, /* R347 */
453 { 0x0000, 0x0000 }, /* R348 */
454 { 0x0000, 0x0000 }, /* R349 */
455 { 0x0000, 0x0000 }, /* R350 */
456 { 0x0000, 0x0000 }, /* R351 */
457 { 0x0000, 0x0000 }, /* R352 */
458 { 0x0000, 0x0000 }, /* R353 */
459 { 0x0000, 0x0000 }, /* R354 */
460 { 0x0000, 0x0000 }, /* R355 */
461 { 0x0000, 0x0000 }, /* R356 */
462 { 0x0000, 0x0000 }, /* R357 */
463 { 0x0000, 0x0000 }, /* R358 */
464 { 0x0000, 0x0000 }, /* R359 */
465 { 0x0000, 0x0000 }, /* R360 */
466 { 0x0000, 0x0000 }, /* R361 */
467 { 0x0000, 0x0000 }, /* R362 */
468 { 0x0000, 0x0000 }, /* R363 */
469 { 0x0000, 0x0000 }, /* R364 */
470 { 0x0000, 0x0000 }, /* R365 */
471 { 0x0000, 0x0000 }, /* R366 */
472 { 0x0000, 0x0000 }, /* R367 */
473 { 0x0000, 0x0000 }, /* R368 */
474 { 0x0000, 0x0000 }, /* R369 */
475 { 0x0000, 0x0000 }, /* R370 */
476 { 0x0000, 0x0000 }, /* R371 */
477 { 0x0000, 0x0000 }, /* R372 */
478 { 0x0000, 0x0000 }, /* R373 */
479 { 0x0000, 0x0000 }, /* R374 */
480 { 0x0000, 0x0000 }, /* R375 */
481 { 0x0000, 0x0000 }, /* R376 */
482 { 0x0000, 0x0000 }, /* R377 */
483 { 0x0000, 0x0000 }, /* R378 */
484 { 0x0000, 0x0000 }, /* R379 */
485 { 0x0000, 0x0000 }, /* R380 */
486 { 0x0000, 0x0000 }, /* R381 */
487 { 0x0000, 0x0000 }, /* R382 */
488 { 0x0000, 0x0000 }, /* R383 */
489 { 0x0000, 0x0000 }, /* R384 */
490 { 0x0000, 0x0000 }, /* R385 */
491 { 0x0000, 0x0000 }, /* R386 */
492 { 0x0000, 0x0000 }, /* R387 */
493 { 0x0000, 0x0000 }, /* R388 */
494 { 0x0000, 0x0000 }, /* R389 */
495 { 0x0000, 0x0000 }, /* R390 */
496 { 0x0000, 0x0000 }, /* R391 */
497 { 0x0000, 0x0000 }, /* R392 */
498 { 0x0000, 0x0000 }, /* R393 */
499 { 0x0000, 0x0000 }, /* R394 */
500 { 0x0000, 0x0000 }, /* R395 */
501 { 0x0000, 0x0000 }, /* R396 */
502 { 0x0000, 0x0000 }, /* R397 */
503 { 0x0000, 0x0000 }, /* R398 */
504 { 0x0000, 0x0000 }, /* R399 */
505 { 0x0000, 0x0000 }, /* R400 */
506 { 0x0000, 0x0000 }, /* R401 */
507 { 0x0000, 0x0000 }, /* R402 */
508 { 0x0000, 0x0000 }, /* R403 */
509 { 0x0000, 0x0000 }, /* R404 */
510 { 0x0000, 0x0000 }, /* R405 */
511 { 0x0000, 0x0000 }, /* R406 */
512 { 0x0000, 0x0000 }, /* R407 */
513 { 0x0000, 0x0000 }, /* R408 */
514 { 0x0000, 0x0000 }, /* R409 */
515 { 0x0000, 0x0000 }, /* R410 */
516 { 0x0000, 0x0000 }, /* R411 */
517 { 0x0000, 0x0000 }, /* R412 */
518 { 0x0000, 0x0000 }, /* R413 */
519 { 0x0000, 0x0000 }, /* R414 */
520 { 0x0000, 0x0000 }, /* R415 */
521 { 0x0000, 0x0000 }, /* R416 */
522 { 0x0000, 0x0000 }, /* R417 */
523 { 0x0000, 0x0000 }, /* R418 */
524 { 0x0000, 0x0000 }, /* R419 */
525 { 0x0000, 0x0000 }, /* R420 */
526 { 0x0000, 0x0000 }, /* R421 */
527 { 0x0000, 0x0000 }, /* R422 */
528 { 0x0000, 0x0000 }, /* R423 */
529 { 0x0000, 0x0000 }, /* R424 */
530 { 0x0000, 0x0000 }, /* R425 */
531 { 0x0000, 0x0000 }, /* R426 */
532 { 0x0000, 0x0000 }, /* R427 */
533 { 0x0000, 0x0000 }, /* R428 */
534 { 0x0000, 0x0000 }, /* R429 */
535 { 0x0000, 0x0000 }, /* R430 */
536 { 0x0000, 0x0000 }, /* R431 */
537 { 0x0000, 0x0000 }, /* R432 */
538 { 0x0000, 0x0000 }, /* R433 */
539 { 0x0000, 0x0000 }, /* R434 */
540 { 0x0000, 0x0000 }, /* R435 */
541 { 0x0000, 0x0000 }, /* R436 */
542 { 0x0000, 0x0000 }, /* R437 */
543 { 0x0000, 0x0000 }, /* R438 */
544 { 0x0000, 0x0000 }, /* R439 */
545 { 0x0000, 0x0000 }, /* R440 */
546 { 0x0000, 0x0000 }, /* R441 */
547 { 0x0000, 0x0000 }, /* R442 */
548 { 0x0000, 0x0000 }, /* R443 */
549 { 0x0000, 0x0000 }, /* R444 */
550 { 0x0000, 0x0000 }, /* R445 */
551 { 0x0000, 0x0000 }, /* R446 */
552 { 0x0000, 0x0000 }, /* R447 */
553 { 0x0000, 0x0000 }, /* R448 */
554 { 0x0000, 0x0000 }, /* R449 */
555 { 0x0000, 0x0000 }, /* R450 */
556 { 0x0000, 0x0000 }, /* R451 */
557 { 0x0000, 0x0000 }, /* R452 */
558 { 0x0000, 0x0000 }, /* R453 */
559 { 0x0000, 0x0000 }, /* R454 */
560 { 0x0000, 0x0000 }, /* R455 */
561 { 0x0000, 0x0000 }, /* R456 */
562 { 0x0000, 0x0000 }, /* R457 */
563 { 0x0000, 0x0000 }, /* R458 */
564 { 0x0000, 0x0000 }, /* R459 */
565 { 0x0000, 0x0000 }, /* R460 */
566 { 0x0000, 0x0000 }, /* R461 */
567 { 0x0000, 0x0000 }, /* R462 */
568 { 0x0000, 0x0000 }, /* R463 */
569 { 0x0000, 0x0000 }, /* R464 */
570 { 0x0000, 0x0000 }, /* R465 */
571 { 0x0000, 0x0000 }, /* R466 */
572 { 0x0000, 0x0000 }, /* R467 */
573 { 0x0000, 0x0000 }, /* R468 */
574 { 0x0000, 0x0000 }, /* R469 */
575 { 0x0000, 0x0000 }, /* R470 */
576 { 0x0000, 0x0000 }, /* R471 */
577 { 0x0000, 0x0000 }, /* R472 */
578 { 0x0000, 0x0000 }, /* R473 */
579 { 0x0000, 0x0000 }, /* R474 */
580 { 0x0000, 0x0000 }, /* R475 */
581 { 0x0000, 0x0000 }, /* R476 */
582 { 0x0000, 0x0000 }, /* R477 */
583 { 0x0000, 0x0000 }, /* R478 */
584 { 0x0000, 0x0000 }, /* R479 */
585 { 0x0000, 0x0000 }, /* R480 */
586 { 0x0000, 0x0000 }, /* R481 */
587 { 0x0000, 0x0000 }, /* R482 */
588 { 0x0000, 0x0000 }, /* R483 */
589 { 0x0000, 0x0000 }, /* R484 */
590 { 0x0000, 0x0000 }, /* R485 */
591 { 0x0000, 0x0000 }, /* R486 */
592 { 0x0000, 0x0000 }, /* R487 */
593 { 0x0000, 0x0000 }, /* R488 */
594 { 0x0000, 0x0000 }, /* R489 */
595 { 0x0000, 0x0000 }, /* R490 */
596 { 0x0000, 0x0000 }, /* R491 */
597 { 0x0000, 0x0000 }, /* R492 */
598 { 0x0000, 0x0000 }, /* R493 */
599 { 0x0000, 0x0000 }, /* R494 */
600 { 0x0000, 0x0000 }, /* R495 */
601 { 0x0000, 0x0000 }, /* R496 */
602 { 0x0000, 0x0000 }, /* R497 */
603 { 0x0000, 0x0000 }, /* R498 */
604 { 0x0000, 0x0000 }, /* R499 */
605 { 0x0000, 0x0000 }, /* R500 */
606 { 0x0000, 0x0000 }, /* R501 */
607 { 0x0000, 0x0000 }, /* R502 */
608 { 0x0000, 0x0000 }, /* R503 */
609 { 0x0000, 0x0000 }, /* R504 */
610 { 0x0000, 0x0000 }, /* R505 */
611 { 0x0000, 0x0000 }, /* R506 */
612 { 0x0000, 0x0000 }, /* R507 */
613 { 0x0000, 0x0000 }, /* R508 */
614 { 0x0000, 0x0000 }, /* R509 */
615 { 0x0000, 0x0000 }, /* R510 */
616 { 0x0000, 0x0000 }, /* R511 */
617 { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
618 { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
619 { 0x0000, 0x0000 }, /* R514 */
620 { 0x0000, 0x0000 }, /* R515 */
621 { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
622 { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
623 { 0x0000, 0x0000 }, /* R518 */
624 { 0x0000, 0x0000 }, /* R519 */
625 { 0x001F, 0x001F }, /* R520 - Clocking (1) */
626 { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
627 { 0x0000, 0x0000 }, /* R522 */
628 { 0x0000, 0x0000 }, /* R523 */
629 { 0x0000, 0x0000 }, /* R524 */
630 { 0x0000, 0x0000 }, /* R525 */
631 { 0x0000, 0x0000 }, /* R526 */
632 { 0x0000, 0x0000 }, /* R527 */
633 { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
634 { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
635 { 0x000F, 0x0000 }, /* R530 - Rate Status */
636 { 0x0000, 0x0000 }, /* R531 */
637 { 0x0000, 0x0000 }, /* R532 */
638 { 0x0000, 0x0000 }, /* R533 */
639 { 0x0000, 0x0000 }, /* R534 */
640 { 0x0000, 0x0000 }, /* R535 */
641 { 0x0000, 0x0000 }, /* R536 */
642 { 0x0000, 0x0000 }, /* R537 */
643 { 0x0000, 0x0000 }, /* R538 */
644 { 0x0000, 0x0000 }, /* R539 */
645 { 0x0000, 0x0000 }, /* R540 */
646 { 0x0000, 0x0000 }, /* R541 */
647 { 0x0000, 0x0000 }, /* R542 */
648 { 0x0000, 0x0000 }, /* R543 */
649 { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
650 { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
651 { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
652 { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
653 { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
654 { 0x0000, 0x0000 }, /* R549 */
655 { 0x0000, 0x0000 }, /* R550 */
656 { 0x0000, 0x0000 }, /* R551 */
657 { 0x0000, 0x0000 }, /* R552 */
658 { 0x0000, 0x0000 }, /* R553 */
659 { 0x0000, 0x0000 }, /* R554 */
660 { 0x0000, 0x0000 }, /* R555 */
661 { 0x0000, 0x0000 }, /* R556 */
662 { 0x0000, 0x0000 }, /* R557 */
663 { 0x0000, 0x0000 }, /* R558 */
664 { 0x0000, 0x0000 }, /* R559 */
665 { 0x0000, 0x0000 }, /* R560 */
666 { 0x0000, 0x0000 }, /* R561 */
667 { 0x0000, 0x0000 }, /* R562 */
668 { 0x0000, 0x0000 }, /* R563 */
669 { 0x0000, 0x0000 }, /* R564 */
670 { 0x0000, 0x0000 }, /* R565 */
671 { 0x0000, 0x0000 }, /* R566 */
672 { 0x0000, 0x0000 }, /* R567 */
673 { 0x0000, 0x0000 }, /* R568 */
674 { 0x0000, 0x0000 }, /* R569 */
675 { 0x0000, 0x0000 }, /* R570 */
676 { 0x0000, 0x0000 }, /* R571 */
677 { 0x0000, 0x0000 }, /* R572 */
678 { 0x0000, 0x0000 }, /* R573 */
679 { 0x0000, 0x0000 }, /* R574 */
680 { 0x0000, 0x0000 }, /* R575 */
681 { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
682 { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
683 { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
684 { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
685 { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
686 { 0x0000, 0x0000 }, /* R581 */
687 { 0x0000, 0x0000 }, /* R582 */
688 { 0x0000, 0x0000 }, /* R583 */
689 { 0x0000, 0x0000 }, /* R584 */
690 { 0x0000, 0x0000 }, /* R585 */
691 { 0x0000, 0x0000 }, /* R586 */
692 { 0x0000, 0x0000 }, /* R587 */
693 { 0x0000, 0x0000 }, /* R588 */
694 { 0x0000, 0x0000 }, /* R589 */
695 { 0x0000, 0x0000 }, /* R590 */
696 { 0x0000, 0x0000 }, /* R591 */
697 { 0x0000, 0x0000 }, /* R592 */
698 { 0x0000, 0x0000 }, /* R593 */
699 { 0x0000, 0x0000 }, /* R594 */
700 { 0x0000, 0x0000 }, /* R595 */
701 { 0x0000, 0x0000 }, /* R596 */
702 { 0x0000, 0x0000 }, /* R597 */
703 { 0x0000, 0x0000 }, /* R598 */
704 { 0x0000, 0x0000 }, /* R599 */
705 { 0x0000, 0x0000 }, /* R600 */
706 { 0x0000, 0x0000 }, /* R601 */
707 { 0x0000, 0x0000 }, /* R602 */
708 { 0x0000, 0x0000 }, /* R603 */
709 { 0x0000, 0x0000 }, /* R604 */
710 { 0x0000, 0x0000 }, /* R605 */
711 { 0x0000, 0x0000 }, /* R606 */
712 { 0x0000, 0x0000 }, /* R607 */
713 { 0x0000, 0x0000 }, /* R608 */
714 { 0x0000, 0x0000 }, /* R609 */
715 { 0x0000, 0x0000 }, /* R610 */
716 { 0x0000, 0x0000 }, /* R611 */
717 { 0x0000, 0x0000 }, /* R612 */
718 { 0x0000, 0x0000 }, /* R613 */
719 { 0x0000, 0x0000 }, /* R614 */
720 { 0x0000, 0x0000 }, /* R615 */
721 { 0x0000, 0x0000 }, /* R616 */
722 { 0x0000, 0x0000 }, /* R617 */
723 { 0x0000, 0x0000 }, /* R618 */
724 { 0x0000, 0x0000 }, /* R619 */
725 { 0x0000, 0x0000 }, /* R620 */
726 { 0x0000, 0x0000 }, /* R621 */
727 { 0x0000, 0x0000 }, /* R622 */
728 { 0x0000, 0x0000 }, /* R623 */
729 { 0x0000, 0x0000 }, /* R624 */
730 { 0x0000, 0x0000 }, /* R625 */
731 { 0x0000, 0x0000 }, /* R626 */
732 { 0x0000, 0x0000 }, /* R627 */
733 { 0x0000, 0x0000 }, /* R628 */
734 { 0x0000, 0x0000 }, /* R629 */
735 { 0x0000, 0x0000 }, /* R630 */
736 { 0x0000, 0x0000 }, /* R631 */
737 { 0x0000, 0x0000 }, /* R632 */
738 { 0x0000, 0x0000 }, /* R633 */
739 { 0x0000, 0x0000 }, /* R634 */
740 { 0x0000, 0x0000 }, /* R635 */
741 { 0x0000, 0x0000 }, /* R636 */
742 { 0x0000, 0x0000 }, /* R637 */
743 { 0x0000, 0x0000 }, /* R638 */
744 { 0x0000, 0x0000 }, /* R639 */
745 { 0x0000, 0x0000 }, /* R640 */
746 { 0x0000, 0x0000 }, /* R641 */
747 { 0x0000, 0x0000 }, /* R642 */
748 { 0x0000, 0x0000 }, /* R643 */
749 { 0x0000, 0x0000 }, /* R644 */
750 { 0x0000, 0x0000 }, /* R645 */
751 { 0x0000, 0x0000 }, /* R646 */
752 { 0x0000, 0x0000 }, /* R647 */
753 { 0x0000, 0x0000 }, /* R648 */
754 { 0x0000, 0x0000 }, /* R649 */
755 { 0x0000, 0x0000 }, /* R650 */
756 { 0x0000, 0x0000 }, /* R651 */
757 { 0x0000, 0x0000 }, /* R652 */
758 { 0x0000, 0x0000 }, /* R653 */
759 { 0x0000, 0x0000 }, /* R654 */
760 { 0x0000, 0x0000 }, /* R655 */
761 { 0x0000, 0x0000 }, /* R656 */
762 { 0x0000, 0x0000 }, /* R657 */
763 { 0x0000, 0x0000 }, /* R658 */
764 { 0x0000, 0x0000 }, /* R659 */
765 { 0x0000, 0x0000 }, /* R660 */
766 { 0x0000, 0x0000 }, /* R661 */
767 { 0x0000, 0x0000 }, /* R662 */
768 { 0x0000, 0x0000 }, /* R663 */
769 { 0x0000, 0x0000 }, /* R664 */
770 { 0x0000, 0x0000 }, /* R665 */
771 { 0x0000, 0x0000 }, /* R666 */
772 { 0x0000, 0x0000 }, /* R667 */
773 { 0x0000, 0x0000 }, /* R668 */
774 { 0x0000, 0x0000 }, /* R669 */
775 { 0x0000, 0x0000 }, /* R670 */
776 { 0x0000, 0x0000 }, /* R671 */
777 { 0x0000, 0x0000 }, /* R672 */
778 { 0x0000, 0x0000 }, /* R673 */
779 { 0x0000, 0x0000 }, /* R674 */
780 { 0x0000, 0x0000 }, /* R675 */
781 { 0x0000, 0x0000 }, /* R676 */
782 { 0x0000, 0x0000 }, /* R677 */
783 { 0x0000, 0x0000 }, /* R678 */
784 { 0x0000, 0x0000 }, /* R679 */
785 { 0x0000, 0x0000 }, /* R680 */
786 { 0x0000, 0x0000 }, /* R681 */
787 { 0x0000, 0x0000 }, /* R682 */
788 { 0x0000, 0x0000 }, /* R683 */
789 { 0x0000, 0x0000 }, /* R684 */
790 { 0x0000, 0x0000 }, /* R685 */
791 { 0x0000, 0x0000 }, /* R686 */
792 { 0x0000, 0x0000 }, /* R687 */
793 { 0x0000, 0x0000 }, /* R688 */
794 { 0x0000, 0x0000 }, /* R689 */
795 { 0x0000, 0x0000 }, /* R690 */
796 { 0x0000, 0x0000 }, /* R691 */
797 { 0x0000, 0x0000 }, /* R692 */
798 { 0x0000, 0x0000 }, /* R693 */
799 { 0x0000, 0x0000 }, /* R694 */
800 { 0x0000, 0x0000 }, /* R695 */
801 { 0x0000, 0x0000 }, /* R696 */
802 { 0x0000, 0x0000 }, /* R697 */
803 { 0x0000, 0x0000 }, /* R698 */
804 { 0x0000, 0x0000 }, /* R699 */
805 { 0x0000, 0x0000 }, /* R700 */
806 { 0x0000, 0x0000 }, /* R701 */
807 { 0x0000, 0x0000 }, /* R702 */
808 { 0x0000, 0x0000 }, /* R703 */
809 { 0x0000, 0x0000 }, /* R704 */
810 { 0x0000, 0x0000 }, /* R705 */
811 { 0x0000, 0x0000 }, /* R706 */
812 { 0x0000, 0x0000 }, /* R707 */
813 { 0x0000, 0x0000 }, /* R708 */
814 { 0x0000, 0x0000 }, /* R709 */
815 { 0x0000, 0x0000 }, /* R710 */
816 { 0x0000, 0x0000 }, /* R711 */
817 { 0x0000, 0x0000 }, /* R712 */
818 { 0x0000, 0x0000 }, /* R713 */
819 { 0x0000, 0x0000 }, /* R714 */
820 { 0x0000, 0x0000 }, /* R715 */
821 { 0x0000, 0x0000 }, /* R716 */
822 { 0x0000, 0x0000 }, /* R717 */
823 { 0x0000, 0x0000 }, /* R718 */
824 { 0x0000, 0x0000 }, /* R719 */
825 { 0x0000, 0x0000 }, /* R720 */
826 { 0x0000, 0x0000 }, /* R721 */
827 { 0x0000, 0x0000 }, /* R722 */
828 { 0x0000, 0x0000 }, /* R723 */
829 { 0x0000, 0x0000 }, /* R724 */
830 { 0x0000, 0x0000 }, /* R725 */
831 { 0x0000, 0x0000 }, /* R726 */
832 { 0x0000, 0x0000 }, /* R727 */
833 { 0x0000, 0x0000 }, /* R728 */
834 { 0x0000, 0x0000 }, /* R729 */
835 { 0x0000, 0x0000 }, /* R730 */
836 { 0x0000, 0x0000 }, /* R731 */
837 { 0x0000, 0x0000 }, /* R732 */
838 { 0x0000, 0x0000 }, /* R733 */
839 { 0x0000, 0x0000 }, /* R734 */
840 { 0x0000, 0x0000 }, /* R735 */
841 { 0x0000, 0x0000 }, /* R736 */
842 { 0x0000, 0x0000 }, /* R737 */
843 { 0x0000, 0x0000 }, /* R738 */
844 { 0x0000, 0x0000 }, /* R739 */
845 { 0x0000, 0x0000 }, /* R740 */
846 { 0x0000, 0x0000 }, /* R741 */
847 { 0x0000, 0x0000 }, /* R742 */
848 { 0x0000, 0x0000 }, /* R743 */
849 { 0x0000, 0x0000 }, /* R744 */
850 { 0x0000, 0x0000 }, /* R745 */
851 { 0x0000, 0x0000 }, /* R746 */
852 { 0x0000, 0x0000 }, /* R747 */
853 { 0x0000, 0x0000 }, /* R748 */
854 { 0x0000, 0x0000 }, /* R749 */
855 { 0x0000, 0x0000 }, /* R750 */
856 { 0x0000, 0x0000 }, /* R751 */
857 { 0x0000, 0x0000 }, /* R752 */
858 { 0x0000, 0x0000 }, /* R753 */
859 { 0x0000, 0x0000 }, /* R754 */
860 { 0x0000, 0x0000 }, /* R755 */
861 { 0x0000, 0x0000 }, /* R756 */
862 { 0x0000, 0x0000 }, /* R757 */
863 { 0x0000, 0x0000 }, /* R758 */
864 { 0x0000, 0x0000 }, /* R759 */
865 { 0x0000, 0x0000 }, /* R760 */
866 { 0x0000, 0x0000 }, /* R761 */
867 { 0x0000, 0x0000 }, /* R762 */
868 { 0x0000, 0x0000 }, /* R763 */
869 { 0x0000, 0x0000 }, /* R764 */
870 { 0x0000, 0x0000 }, /* R765 */
871 { 0x0000, 0x0000 }, /* R766 */
872 { 0x0000, 0x0000 }, /* R767 */
873 { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
874 { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
875 { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
876 { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
877 { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
878 { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
879 { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
880 { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
881 { 0x0000, 0x0000 }, /* R776 */
882 { 0x0000, 0x0000 }, /* R777 */
883 { 0x0000, 0x0000 }, /* R778 */
884 { 0x0000, 0x0000 }, /* R779 */
885 { 0x0000, 0x0000 }, /* R780 */
886 { 0x0000, 0x0000 }, /* R781 */
887 { 0x0000, 0x0000 }, /* R782 */
888 { 0x0000, 0x0000 }, /* R783 */
889 { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
890 { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
891 { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
892 { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
893 { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
894 { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
895 { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
896 { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
897 { 0x0000, 0x0000 }, /* R792 */
898 { 0x0000, 0x0000 }, /* R793 */
899 { 0x0000, 0x0000 }, /* R794 */
900 { 0x0000, 0x0000 }, /* R795 */
901 { 0x0000, 0x0000 }, /* R796 */
902 { 0x0000, 0x0000 }, /* R797 */
903 { 0x0000, 0x0000 }, /* R798 */
904 { 0x0000, 0x0000 }, /* R799 */
905 { 0x0000, 0x0000 }, /* R800 */
906 { 0x0000, 0x0000 }, /* R801 */
907 { 0x0000, 0x0000 }, /* R802 */
908 { 0x0000, 0x0000 }, /* R803 */
909 { 0x0000, 0x0000 }, /* R804 */
910 { 0x0000, 0x0000 }, /* R805 */
911 { 0x0000, 0x0000 }, /* R806 */
912 { 0x0000, 0x0000 }, /* R807 */
913 { 0x0000, 0x0000 }, /* R808 */
914 { 0x0000, 0x0000 }, /* R809 */
915 { 0x0000, 0x0000 }, /* R810 */
916 { 0x0000, 0x0000 }, /* R811 */
917 { 0x0000, 0x0000 }, /* R812 */
918 { 0x0000, 0x0000 }, /* R813 */
919 { 0x0000, 0x0000 }, /* R814 */
920 { 0x0000, 0x0000 }, /* R815 */
921 { 0x0000, 0x0000 }, /* R816 */
922 { 0x0000, 0x0000 }, /* R817 */
923 { 0x0000, 0x0000 }, /* R818 */
924 { 0x0000, 0x0000 }, /* R819 */
925 { 0x0000, 0x0000 }, /* R820 */
926 { 0x0000, 0x0000 }, /* R821 */
927 { 0x0000, 0x0000 }, /* R822 */
928 { 0x0000, 0x0000 }, /* R823 */
929 { 0x0000, 0x0000 }, /* R824 */
930 { 0x0000, 0x0000 }, /* R825 */
931 { 0x0000, 0x0000 }, /* R826 */
932 { 0x0000, 0x0000 }, /* R827 */
933 { 0x0000, 0x0000 }, /* R828 */
934 { 0x0000, 0x0000 }, /* R829 */
935 { 0x0000, 0x0000 }, /* R830 */
936 { 0x0000, 0x0000 }, /* R831 */
937 { 0x0000, 0x0000 }, /* R832 */
938 { 0x0000, 0x0000 }, /* R833 */
939 { 0x0000, 0x0000 }, /* R834 */
940 { 0x0000, 0x0000 }, /* R835 */
941 { 0x0000, 0x0000 }, /* R836 */
942 { 0x0000, 0x0000 }, /* R837 */
943 { 0x0000, 0x0000 }, /* R838 */
944 { 0x0000, 0x0000 }, /* R839 */
945 { 0x0000, 0x0000 }, /* R840 */
946 { 0x0000, 0x0000 }, /* R841 */
947 { 0x0000, 0x0000 }, /* R842 */
948 { 0x0000, 0x0000 }, /* R843 */
949 { 0x0000, 0x0000 }, /* R844 */
950 { 0x0000, 0x0000 }, /* R845 */
951 { 0x0000, 0x0000 }, /* R846 */
952 { 0x0000, 0x0000 }, /* R847 */
953 { 0x0000, 0x0000 }, /* R848 */
954 { 0x0000, 0x0000 }, /* R849 */
955 { 0x0000, 0x0000 }, /* R850 */
956 { 0x0000, 0x0000 }, /* R851 */
957 { 0x0000, 0x0000 }, /* R852 */
958 { 0x0000, 0x0000 }, /* R853 */
959 { 0x0000, 0x0000 }, /* R854 */
960 { 0x0000, 0x0000 }, /* R855 */
961 { 0x0000, 0x0000 }, /* R856 */
962 { 0x0000, 0x0000 }, /* R857 */
963 { 0x0000, 0x0000 }, /* R858 */
964 { 0x0000, 0x0000 }, /* R859 */
965 { 0x0000, 0x0000 }, /* R860 */
966 { 0x0000, 0x0000 }, /* R861 */
967 { 0x0000, 0x0000 }, /* R862 */
968 { 0x0000, 0x0000 }, /* R863 */
969 { 0x0000, 0x0000 }, /* R864 */
970 { 0x0000, 0x0000 }, /* R865 */
971 { 0x0000, 0x0000 }, /* R866 */
972 { 0x0000, 0x0000 }, /* R867 */
973 { 0x0000, 0x0000 }, /* R868 */
974 { 0x0000, 0x0000 }, /* R869 */
975 { 0x0000, 0x0000 }, /* R870 */
976 { 0x0000, 0x0000 }, /* R871 */
977 { 0x0000, 0x0000 }, /* R872 */
978 { 0x0000, 0x0000 }, /* R873 */
979 { 0x0000, 0x0000 }, /* R874 */
980 { 0x0000, 0x0000 }, /* R875 */
981 { 0x0000, 0x0000 }, /* R876 */
982 { 0x0000, 0x0000 }, /* R877 */
983 { 0x0000, 0x0000 }, /* R878 */
984 { 0x0000, 0x0000 }, /* R879 */
985 { 0x0000, 0x0000 }, /* R880 */
986 { 0x0000, 0x0000 }, /* R881 */
987 { 0x0000, 0x0000 }, /* R882 */
988 { 0x0000, 0x0000 }, /* R883 */
989 { 0x0000, 0x0000 }, /* R884 */
990 { 0x0000, 0x0000 }, /* R885 */
991 { 0x0000, 0x0000 }, /* R886 */
992 { 0x0000, 0x0000 }, /* R887 */
993 { 0x0000, 0x0000 }, /* R888 */
994 { 0x0000, 0x0000 }, /* R889 */
995 { 0x0000, 0x0000 }, /* R890 */
996 { 0x0000, 0x0000 }, /* R891 */
997 { 0x0000, 0x0000 }, /* R892 */
998 { 0x0000, 0x0000 }, /* R893 */
999 { 0x0000, 0x0000 }, /* R894 */
1000 { 0x0000, 0x0000 }, /* R895 */
1001 { 0x0000, 0x0000 }, /* R896 */
1002 { 0x0000, 0x0000 }, /* R897 */
1003 { 0x0000, 0x0000 }, /* R898 */
1004 { 0x0000, 0x0000 }, /* R899 */
1005 { 0x0000, 0x0000 }, /* R900 */
1006 { 0x0000, 0x0000 }, /* R901 */
1007 { 0x0000, 0x0000 }, /* R902 */
1008 { 0x0000, 0x0000 }, /* R903 */
1009 { 0x0000, 0x0000 }, /* R904 */
1010 { 0x0000, 0x0000 }, /* R905 */
1011 { 0x0000, 0x0000 }, /* R906 */
1012 { 0x0000, 0x0000 }, /* R907 */
1013 { 0x0000, 0x0000 }, /* R908 */
1014 { 0x0000, 0x0000 }, /* R909 */
1015 { 0x0000, 0x0000 }, /* R910 */
1016 { 0x0000, 0x0000 }, /* R911 */
1017 { 0x0000, 0x0000 }, /* R912 */
1018 { 0x0000, 0x0000 }, /* R913 */
1019 { 0x0000, 0x0000 }, /* R914 */
1020 { 0x0000, 0x0000 }, /* R915 */
1021 { 0x0000, 0x0000 }, /* R916 */
1022 { 0x0000, 0x0000 }, /* R917 */
1023 { 0x0000, 0x0000 }, /* R918 */
1024 { 0x0000, 0x0000 }, /* R919 */
1025 { 0x0000, 0x0000 }, /* R920 */
1026 { 0x0000, 0x0000 }, /* R921 */
1027 { 0x0000, 0x0000 }, /* R922 */
1028 { 0x0000, 0x0000 }, /* R923 */
1029 { 0x0000, 0x0000 }, /* R924 */
1030 { 0x0000, 0x0000 }, /* R925 */
1031 { 0x0000, 0x0000 }, /* R926 */
1032 { 0x0000, 0x0000 }, /* R927 */
1033 { 0x0000, 0x0000 }, /* R928 */
1034 { 0x0000, 0x0000 }, /* R929 */
1035 { 0x0000, 0x0000 }, /* R930 */
1036 { 0x0000, 0x0000 }, /* R931 */
1037 { 0x0000, 0x0000 }, /* R932 */
1038 { 0x0000, 0x0000 }, /* R933 */
1039 { 0x0000, 0x0000 }, /* R934 */
1040 { 0x0000, 0x0000 }, /* R935 */
1041 { 0x0000, 0x0000 }, /* R936 */
1042 { 0x0000, 0x0000 }, /* R937 */
1043 { 0x0000, 0x0000 }, /* R938 */
1044 { 0x0000, 0x0000 }, /* R939 */
1045 { 0x0000, 0x0000 }, /* R940 */
1046 { 0x0000, 0x0000 }, /* R941 */
1047 { 0x0000, 0x0000 }, /* R942 */
1048 { 0x0000, 0x0000 }, /* R943 */
1049 { 0x0000, 0x0000 }, /* R944 */
1050 { 0x0000, 0x0000 }, /* R945 */
1051 { 0x0000, 0x0000 }, /* R946 */
1052 { 0x0000, 0x0000 }, /* R947 */
1053 { 0x0000, 0x0000 }, /* R948 */
1054 { 0x0000, 0x0000 }, /* R949 */
1055 { 0x0000, 0x0000 }, /* R950 */
1056 { 0x0000, 0x0000 }, /* R951 */
1057 { 0x0000, 0x0000 }, /* R952 */
1058 { 0x0000, 0x0000 }, /* R953 */
1059 { 0x0000, 0x0000 }, /* R954 */
1060 { 0x0000, 0x0000 }, /* R955 */
1061 { 0x0000, 0x0000 }, /* R956 */
1062 { 0x0000, 0x0000 }, /* R957 */
1063 { 0x0000, 0x0000 }, /* R958 */
1064 { 0x0000, 0x0000 }, /* R959 */
1065 { 0x0000, 0x0000 }, /* R960 */
1066 { 0x0000, 0x0000 }, /* R961 */
1067 { 0x0000, 0x0000 }, /* R962 */
1068 { 0x0000, 0x0000 }, /* R963 */
1069 { 0x0000, 0x0000 }, /* R964 */
1070 { 0x0000, 0x0000 }, /* R965 */
1071 { 0x0000, 0x0000 }, /* R966 */
1072 { 0x0000, 0x0000 }, /* R967 */
1073 { 0x0000, 0x0000 }, /* R968 */
1074 { 0x0000, 0x0000 }, /* R969 */
1075 { 0x0000, 0x0000 }, /* R970 */
1076 { 0x0000, 0x0000 }, /* R971 */
1077 { 0x0000, 0x0000 }, /* R972 */
1078 { 0x0000, 0x0000 }, /* R973 */
1079 { 0x0000, 0x0000 }, /* R974 */
1080 { 0x0000, 0x0000 }, /* R975 */
1081 { 0x0000, 0x0000 }, /* R976 */
1082 { 0x0000, 0x0000 }, /* R977 */
1083 { 0x0000, 0x0000 }, /* R978 */
1084 { 0x0000, 0x0000 }, /* R979 */
1085 { 0x0000, 0x0000 }, /* R980 */
1086 { 0x0000, 0x0000 }, /* R981 */
1087 { 0x0000, 0x0000 }, /* R982 */
1088 { 0x0000, 0x0000 }, /* R983 */
1089 { 0x0000, 0x0000 }, /* R984 */
1090 { 0x0000, 0x0000 }, /* R985 */
1091 { 0x0000, 0x0000 }, /* R986 */
1092 { 0x0000, 0x0000 }, /* R987 */
1093 { 0x0000, 0x0000 }, /* R988 */
1094 { 0x0000, 0x0000 }, /* R989 */
1095 { 0x0000, 0x0000 }, /* R990 */
1096 { 0x0000, 0x0000 }, /* R991 */
1097 { 0x0000, 0x0000 }, /* R992 */
1098 { 0x0000, 0x0000 }, /* R993 */
1099 { 0x0000, 0x0000 }, /* R994 */
1100 { 0x0000, 0x0000 }, /* R995 */
1101 { 0x0000, 0x0000 }, /* R996 */
1102 { 0x0000, 0x0000 }, /* R997 */
1103 { 0x0000, 0x0000 }, /* R998 */
1104 { 0x0000, 0x0000 }, /* R999 */
1105 { 0x0000, 0x0000 }, /* R1000 */
1106 { 0x0000, 0x0000 }, /* R1001 */
1107 { 0x0000, 0x0000 }, /* R1002 */
1108 { 0x0000, 0x0000 }, /* R1003 */
1109 { 0x0000, 0x0000 }, /* R1004 */
1110 { 0x0000, 0x0000 }, /* R1005 */
1111 { 0x0000, 0x0000 }, /* R1006 */
1112 { 0x0000, 0x0000 }, /* R1007 */
1113 { 0x0000, 0x0000 }, /* R1008 */
1114 { 0x0000, 0x0000 }, /* R1009 */
1115 { 0x0000, 0x0000 }, /* R1010 */
1116 { 0x0000, 0x0000 }, /* R1011 */
1117 { 0x0000, 0x0000 }, /* R1012 */
1118 { 0x0000, 0x0000 }, /* R1013 */
1119 { 0x0000, 0x0000 }, /* R1014 */
1120 { 0x0000, 0x0000 }, /* R1015 */
1121 { 0x0000, 0x0000 }, /* R1016 */
1122 { 0x0000, 0x0000 }, /* R1017 */
1123 { 0x0000, 0x0000 }, /* R1018 */
1124 { 0x0000, 0x0000 }, /* R1019 */
1125 { 0x0000, 0x0000 }, /* R1020 */
1126 { 0x0000, 0x0000 }, /* R1021 */
1127 { 0x0000, 0x0000 }, /* R1022 */
1128 { 0x0000, 0x0000 }, /* R1023 */
1129 { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
1130 { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
1131 { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
1132 { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
1133 { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
1134 { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
1135 { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
1136 { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
1137 { 0x0000, 0x0000 }, /* R1032 */
1138 { 0x0000, 0x0000 }, /* R1033 */
1139 { 0x0000, 0x0000 }, /* R1034 */
1140 { 0x0000, 0x0000 }, /* R1035 */
1141 { 0x0000, 0x0000 }, /* R1036 */
1142 { 0x0000, 0x0000 }, /* R1037 */
1143 { 0x0000, 0x0000 }, /* R1038 */
1144 { 0x0000, 0x0000 }, /* R1039 */
1145 { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
1146 { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
1147 { 0x0000, 0x0000 }, /* R1042 */
1148 { 0x0000, 0x0000 }, /* R1043 */
1149 { 0x0000, 0x0000 }, /* R1044 */
1150 { 0x0000, 0x0000 }, /* R1045 */
1151 { 0x0000, 0x0000 }, /* R1046 */
1152 { 0x0000, 0x0000 }, /* R1047 */
1153 { 0x0000, 0x0000 }, /* R1048 */
1154 { 0x0000, 0x0000 }, /* R1049 */
1155 { 0x0000, 0x0000 }, /* R1050 */
1156 { 0x0000, 0x0000 }, /* R1051 */
1157 { 0x0000, 0x0000 }, /* R1052 */
1158 { 0x0000, 0x0000 }, /* R1053 */
1159 { 0x0000, 0x0000 }, /* R1054 */
1160 { 0x0000, 0x0000 }, /* R1055 */
1161 { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
1162 { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
1163 { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
1164 { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
1165 { 0x0000, 0x0000 }, /* R1060 */
1166 { 0x0000, 0x0000 }, /* R1061 */
1167 { 0x0000, 0x0000 }, /* R1062 */
1168 { 0x0000, 0x0000 }, /* R1063 */
1169 { 0x0000, 0x0000 }, /* R1064 */
1170 { 0x0000, 0x0000 }, /* R1065 */
1171 { 0x0000, 0x0000 }, /* R1066 */
1172 { 0x0000, 0x0000 }, /* R1067 */
1173 { 0x0000, 0x0000 }, /* R1068 */
1174 { 0x0000, 0x0000 }, /* R1069 */
1175 { 0x0000, 0x0000 }, /* R1070 */
1176 { 0x0000, 0x0000 }, /* R1071 */
1177 { 0x0000, 0x0000 }, /* R1072 */
1178 { 0x0000, 0x0000 }, /* R1073 */
1179 { 0x0000, 0x0000 }, /* R1074 */
1180 { 0x0000, 0x0000 }, /* R1075 */
1181 { 0x0000, 0x0000 }, /* R1076 */
1182 { 0x0000, 0x0000 }, /* R1077 */
1183 { 0x0000, 0x0000 }, /* R1078 */
1184 { 0x0000, 0x0000 }, /* R1079 */
1185 { 0x0000, 0x0000 }, /* R1080 */
1186 { 0x0000, 0x0000 }, /* R1081 */
1187 { 0x0000, 0x0000 }, /* R1082 */
1188 { 0x0000, 0x0000 }, /* R1083 */
1189 { 0x0000, 0x0000 }, /* R1084 */
1190 { 0x0000, 0x0000 }, /* R1085 */
1191 { 0x0000, 0x0000 }, /* R1086 */
1192 { 0x0000, 0x0000 }, /* R1087 */
1193 { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
1194 { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
1195 { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
1196 { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
1197 { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
1198 { 0x0000, 0x0000 }, /* R1093 */
1199 { 0x0000, 0x0000 }, /* R1094 */
1200 { 0x0000, 0x0000 }, /* R1095 */
1201 { 0x0000, 0x0000 }, /* R1096 */
1202 { 0x0000, 0x0000 }, /* R1097 */
1203 { 0x0000, 0x0000 }, /* R1098 */
1204 { 0x0000, 0x0000 }, /* R1099 */
1205 { 0x0000, 0x0000 }, /* R1100 */
1206 { 0x0000, 0x0000 }, /* R1101 */
1207 { 0x0000, 0x0000 }, /* R1102 */
1208 { 0x0000, 0x0000 }, /* R1103 */
1209 { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
1210 { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
1211 { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
1212 { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
1213 { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
1214 { 0x0000, 0x0000 }, /* R1109 */
1215 { 0x0000, 0x0000 }, /* R1110 */
1216 { 0x0000, 0x0000 }, /* R1111 */
1217 { 0x0000, 0x0000 }, /* R1112 */
1218 { 0x0000, 0x0000 }, /* R1113 */
1219 { 0x0000, 0x0000 }, /* R1114 */
1220 { 0x0000, 0x0000 }, /* R1115 */
1221 { 0x0000, 0x0000 }, /* R1116 */
1222 { 0x0000, 0x0000 }, /* R1117 */
1223 { 0x0000, 0x0000 }, /* R1118 */
1224 { 0x0000, 0x0000 }, /* R1119 */
1225 { 0x0000, 0x0000 }, /* R1120 */
1226 { 0x0000, 0x0000 }, /* R1121 */
1227 { 0x0000, 0x0000 }, /* R1122 */
1228 { 0x0000, 0x0000 }, /* R1123 */
1229 { 0x0000, 0x0000 }, /* R1124 */
1230 { 0x0000, 0x0000 }, /* R1125 */
1231 { 0x0000, 0x0000 }, /* R1126 */
1232 { 0x0000, 0x0000 }, /* R1127 */
1233 { 0x0000, 0x0000 }, /* R1128 */
1234 { 0x0000, 0x0000 }, /* R1129 */
1235 { 0x0000, 0x0000 }, /* R1130 */
1236 { 0x0000, 0x0000 }, /* R1131 */
1237 { 0x0000, 0x0000 }, /* R1132 */
1238 { 0x0000, 0x0000 }, /* R1133 */
1239 { 0x0000, 0x0000 }, /* R1134 */
1240 { 0x0000, 0x0000 }, /* R1135 */
1241 { 0x0000, 0x0000 }, /* R1136 */
1242 { 0x0000, 0x0000 }, /* R1137 */
1243 { 0x0000, 0x0000 }, /* R1138 */
1244 { 0x0000, 0x0000 }, /* R1139 */
1245 { 0x0000, 0x0000 }, /* R1140 */
1246 { 0x0000, 0x0000 }, /* R1141 */
1247 { 0x0000, 0x0000 }, /* R1142 */
1248 { 0x0000, 0x0000 }, /* R1143 */
1249 { 0x0000, 0x0000 }, /* R1144 */
1250 { 0x0000, 0x0000 }, /* R1145 */
1251 { 0x0000, 0x0000 }, /* R1146 */
1252 { 0x0000, 0x0000 }, /* R1147 */
1253 { 0x0000, 0x0000 }, /* R1148 */
1254 { 0x0000, 0x0000 }, /* R1149 */
1255 { 0x0000, 0x0000 }, /* R1150 */
1256 { 0x0000, 0x0000 }, /* R1151 */
1257 { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1258 { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1259 { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1260 { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1261 { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1262 { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1263 { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1264 { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1265 { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1266 { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1267 { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1268 { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1269 { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1270 { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1271 { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1272 { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1273 { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1274 { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1275 { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1276 { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1277 { 0x0000, 0x0000 }, /* R1172 */
1278 { 0x0000, 0x0000 }, /* R1173 */
1279 { 0x0000, 0x0000 }, /* R1174 */
1280 { 0x0000, 0x0000 }, /* R1175 */
1281 { 0x0000, 0x0000 }, /* R1176 */
1282 { 0x0000, 0x0000 }, /* R1177 */
1283 { 0x0000, 0x0000 }, /* R1178 */
1284 { 0x0000, 0x0000 }, /* R1179 */
1285 { 0x0000, 0x0000 }, /* R1180 */
1286 { 0x0000, 0x0000 }, /* R1181 */
1287 { 0x0000, 0x0000 }, /* R1182 */
1288 { 0x0000, 0x0000 }, /* R1183 */
1289 { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1290 { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1291 { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1292 { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1293 { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1294 { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1295 { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1296 { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1297 { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1298 { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1299 { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1300 { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1301 { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1302 { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1303 { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1304 { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1305 { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1306 { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1307 { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1308 { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1309 { 0x0000, 0x0000 }, /* R1204 */
1310 { 0x0000, 0x0000 }, /* R1205 */
1311 { 0x0000, 0x0000 }, /* R1206 */
1312 { 0x0000, 0x0000 }, /* R1207 */
1313 { 0x0000, 0x0000 }, /* R1208 */
1314 { 0x0000, 0x0000 }, /* R1209 */
1315 { 0x0000, 0x0000 }, /* R1210 */
1316 { 0x0000, 0x0000 }, /* R1211 */
1317 { 0x0000, 0x0000 }, /* R1212 */
1318 { 0x0000, 0x0000 }, /* R1213 */
1319 { 0x0000, 0x0000 }, /* R1214 */
1320 { 0x0000, 0x0000 }, /* R1215 */
1321 { 0x0000, 0x0000 }, /* R1216 */
1322 { 0x0000, 0x0000 }, /* R1217 */
1323 { 0x0000, 0x0000 }, /* R1218 */
1324 { 0x0000, 0x0000 }, /* R1219 */
1325 { 0x0000, 0x0000 }, /* R1220 */
1326 { 0x0000, 0x0000 }, /* R1221 */
1327 { 0x0000, 0x0000 }, /* R1222 */
1328 { 0x0000, 0x0000 }, /* R1223 */
1329 { 0x0000, 0x0000 }, /* R1224 */
1330 { 0x0000, 0x0000 }, /* R1225 */
1331 { 0x0000, 0x0000 }, /* R1226 */
1332 { 0x0000, 0x0000 }, /* R1227 */
1333 { 0x0000, 0x0000 }, /* R1228 */
1334 { 0x0000, 0x0000 }, /* R1229 */
1335 { 0x0000, 0x0000 }, /* R1230 */
1336 { 0x0000, 0x0000 }, /* R1231 */
1337 { 0x0000, 0x0000 }, /* R1232 */
1338 { 0x0000, 0x0000 }, /* R1233 */
1339 { 0x0000, 0x0000 }, /* R1234 */
1340 { 0x0000, 0x0000 }, /* R1235 */
1341 { 0x0000, 0x0000 }, /* R1236 */
1342 { 0x0000, 0x0000 }, /* R1237 */
1343 { 0x0000, 0x0000 }, /* R1238 */
1344 { 0x0000, 0x0000 }, /* R1239 */
1345 { 0x0000, 0x0000 }, /* R1240 */
1346 { 0x0000, 0x0000 }, /* R1241 */
1347 { 0x0000, 0x0000 }, /* R1242 */
1348 { 0x0000, 0x0000 }, /* R1243 */
1349 { 0x0000, 0x0000 }, /* R1244 */
1350 { 0x0000, 0x0000 }, /* R1245 */
1351 { 0x0000, 0x0000 }, /* R1246 */
1352 { 0x0000, 0x0000 }, /* R1247 */
1353 { 0x0000, 0x0000 }, /* R1248 */
1354 { 0x0000, 0x0000 }, /* R1249 */
1355 { 0x0000, 0x0000 }, /* R1250 */
1356 { 0x0000, 0x0000 }, /* R1251 */
1357 { 0x0000, 0x0000 }, /* R1252 */
1358 { 0x0000, 0x0000 }, /* R1253 */
1359 { 0x0000, 0x0000 }, /* R1254 */
1360 { 0x0000, 0x0000 }, /* R1255 */
1361 { 0x0000, 0x0000 }, /* R1256 */
1362 { 0x0000, 0x0000 }, /* R1257 */
1363 { 0x0000, 0x0000 }, /* R1258 */
1364 { 0x0000, 0x0000 }, /* R1259 */
1365 { 0x0000, 0x0000 }, /* R1260 */
1366 { 0x0000, 0x0000 }, /* R1261 */
1367 { 0x0000, 0x0000 }, /* R1262 */
1368 { 0x0000, 0x0000 }, /* R1263 */
1369 { 0x0000, 0x0000 }, /* R1264 */
1370 { 0x0000, 0x0000 }, /* R1265 */
1371 { 0x0000, 0x0000 }, /* R1266 */
1372 { 0x0000, 0x0000 }, /* R1267 */
1373 { 0x0000, 0x0000 }, /* R1268 */
1374 { 0x0000, 0x0000 }, /* R1269 */
1375 { 0x0000, 0x0000 }, /* R1270 */
1376 { 0x0000, 0x0000 }, /* R1271 */
1377 { 0x0000, 0x0000 }, /* R1272 */
1378 { 0x0000, 0x0000 }, /* R1273 */
1379 { 0x0000, 0x0000 }, /* R1274 */
1380 { 0x0000, 0x0000 }, /* R1275 */
1381 { 0x0000, 0x0000 }, /* R1276 */
1382 { 0x0000, 0x0000 }, /* R1277 */
1383 { 0x0000, 0x0000 }, /* R1278 */
1384 { 0x0000, 0x0000 }, /* R1279 */
1385 { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
1386 { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
1387 { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
1388 { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
1389 { 0x0000, 0x0000 }, /* R1284 */
1390 { 0x0000, 0x0000 }, /* R1285 */
1391 { 0x0000, 0x0000 }, /* R1286 */
1392 { 0x0000, 0x0000 }, /* R1287 */
1393 { 0x0000, 0x0000 }, /* R1288 */
1394 { 0x0000, 0x0000 }, /* R1289 */
1395 { 0x0000, 0x0000 }, /* R1290 */
1396 { 0x0000, 0x0000 }, /* R1291 */
1397 { 0x0000, 0x0000 }, /* R1292 */
1398 { 0x0000, 0x0000 }, /* R1293 */
1399 { 0x0000, 0x0000 }, /* R1294 */
1400 { 0x0000, 0x0000 }, /* R1295 */
1401 { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
1402 { 0x0000, 0x0000 }, /* R1297 */
1403 { 0x0000, 0x0000 }, /* R1298 */
1404 { 0x0000, 0x0000 }, /* R1299 */
1405 { 0x0000, 0x0000 }, /* R1300 */
1406 { 0x0000, 0x0000 }, /* R1301 */
1407 { 0x0000, 0x0000 }, /* R1302 */
1408 { 0x0000, 0x0000 }, /* R1303 */
1409 { 0x0000, 0x0000 }, /* R1304 */
1410 { 0x0000, 0x0000 }, /* R1305 */
1411 { 0x0000, 0x0000 }, /* R1306 */
1412 { 0x0000, 0x0000 }, /* R1307 */
1413 { 0x0000, 0x0000 }, /* R1308 */
1414 { 0x0000, 0x0000 }, /* R1309 */
1415 { 0x0000, 0x0000 }, /* R1310 */
1416 { 0x0000, 0x0000 }, /* R1311 */
1417 { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
1418 { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
1419 { 0x0000, 0x0000 }, /* R1314 */
1420 { 0x0000, 0x0000 }, /* R1315 */
1421 { 0x0000, 0x0000 }, /* R1316 */
1422 { 0x0000, 0x0000 }, /* R1317 */
1423 { 0x0000, 0x0000 }, /* R1318 */
1424 { 0x0000, 0x0000 }, /* R1319 */
1425 { 0x0000, 0x0000 }, /* R1320 */
1426 { 0x0000, 0x0000 }, /* R1321 */
1427 { 0x0000, 0x0000 }, /* R1322 */
1428 { 0x0000, 0x0000 }, /* R1323 */
1429 { 0x0000, 0x0000 }, /* R1324 */
1430 { 0x0000, 0x0000 }, /* R1325 */
1431 { 0x0000, 0x0000 }, /* R1326 */
1432 { 0x0000, 0x0000 }, /* R1327 */
1433 { 0x0000, 0x0000 }, /* R1328 */
1434 { 0x0000, 0x0000 }, /* R1329 */
1435 { 0x0000, 0x0000 }, /* R1330 */
1436 { 0x0000, 0x0000 }, /* R1331 */
1437 { 0x0000, 0x0000 }, /* R1332 */
1438 { 0x0000, 0x0000 }, /* R1333 */
1439 { 0x0000, 0x0000 }, /* R1334 */
1440 { 0x0000, 0x0000 }, /* R1335 */
1441 { 0x0000, 0x0000 }, /* R1336 */
1442 { 0x0000, 0x0000 }, /* R1337 */
1443 { 0x0000, 0x0000 }, /* R1338 */
1444 { 0x0000, 0x0000 }, /* R1339 */
1445 { 0x0000, 0x0000 }, /* R1340 */
1446 { 0x0000, 0x0000 }, /* R1341 */
1447 { 0x0000, 0x0000 }, /* R1342 */
1448 { 0x0000, 0x0000 }, /* R1343 */
1449 { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
1450 { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
1451 { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
1452 { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
1453 { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
1454 { 0x0000, 0x0000 }, /* R1349 */
1455 { 0x0000, 0x0000 }, /* R1350 */
1456 { 0x0000, 0x0000 }, /* R1351 */
1457 { 0x0000, 0x0000 }, /* R1352 */
1458 { 0x0000, 0x0000 }, /* R1353 */
1459 { 0x0000, 0x0000 }, /* R1354 */
1460 { 0x0000, 0x0000 }, /* R1355 */
1461 { 0x0000, 0x0000 }, /* R1356 */
1462 { 0x0000, 0x0000 }, /* R1357 */
1463 { 0x0000, 0x0000 }, /* R1358 */
1464 { 0x0000, 0x0000 }, /* R1359 */
1465 { 0x0000, 0x0000 }, /* R1360 */
1466 { 0x0000, 0x0000 }, /* R1361 */
1467 { 0x0000, 0x0000 }, /* R1362 */
1468 { 0x0000, 0x0000 }, /* R1363 */
1469 { 0x0000, 0x0000 }, /* R1364 */
1470 { 0x0000, 0x0000 }, /* R1365 */
1471 { 0x0000, 0x0000 }, /* R1366 */
1472 { 0x0000, 0x0000 }, /* R1367 */
1473 { 0x0000, 0x0000 }, /* R1368 */
1474 { 0x0000, 0x0000 }, /* R1369 */
1475 { 0x0000, 0x0000 }, /* R1370 */
1476 { 0x0000, 0x0000 }, /* R1371 */
1477 { 0x0000, 0x0000 }, /* R1372 */
1478 { 0x0000, 0x0000 }, /* R1373 */
1479 { 0x0000, 0x0000 }, /* R1374 */
1480 { 0x0000, 0x0000 }, /* R1375 */
1481 { 0x0000, 0x0000 }, /* R1376 */
1482 { 0x0000, 0x0000 }, /* R1377 */
1483 { 0x0000, 0x0000 }, /* R1378 */
1484 { 0x0000, 0x0000 }, /* R1379 */
1485 { 0x0000, 0x0000 }, /* R1380 */
1486 { 0x0000, 0x0000 }, /* R1381 */
1487 { 0x0000, 0x0000 }, /* R1382 */
1488 { 0x0000, 0x0000 }, /* R1383 */
1489 { 0x0000, 0x0000 }, /* R1384 */
1490 { 0x0000, 0x0000 }, /* R1385 */
1491 { 0x0000, 0x0000 }, /* R1386 */
1492 { 0x0000, 0x0000 }, /* R1387 */
1493 { 0x0000, 0x0000 }, /* R1388 */
1494 { 0x0000, 0x0000 }, /* R1389 */
1495 { 0x0000, 0x0000 }, /* R1390 */
1496 { 0x0000, 0x0000 }, /* R1391 */
1497 { 0x0000, 0x0000 }, /* R1392 */
1498 { 0x0000, 0x0000 }, /* R1393 */
1499 { 0x0000, 0x0000 }, /* R1394 */
1500 { 0x0000, 0x0000 }, /* R1395 */
1501 { 0x0000, 0x0000 }, /* R1396 */
1502 { 0x0000, 0x0000 }, /* R1397 */
1503 { 0x0000, 0x0000 }, /* R1398 */
1504 { 0x0000, 0x0000 }, /* R1399 */
1505 { 0x0000, 0x0000 }, /* R1400 */
1506 { 0x0000, 0x0000 }, /* R1401 */
1507 { 0x0000, 0x0000 }, /* R1402 */
1508 { 0x0000, 0x0000 }, /* R1403 */
1509 { 0x0000, 0x0000 }, /* R1404 */
1510 { 0x0000, 0x0000 }, /* R1405 */
1511 { 0x0000, 0x0000 }, /* R1406 */
1512 { 0x0000, 0x0000 }, /* R1407 */
1513 { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
1514 { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
1515 { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
1516 { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
1517 { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
1518 { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
1519 { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
1520 { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
1521 { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
1522 { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
1523 { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
1524 { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
1525 { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
1526 { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
1527 { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
1528 { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
1529 { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
1530 { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
1531 { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
1532 { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
1533 { 0x0000, 0x0000 }, /* R1428 */
1534 { 0x0000, 0x0000 }, /* R1429 */
1535 { 0x0000, 0x0000 }, /* R1430 */
1536 { 0x0000, 0x0000 }, /* R1431 */
1537 { 0x0000, 0x0000 }, /* R1432 */
1538 { 0x0000, 0x0000 }, /* R1433 */
1539 { 0x0000, 0x0000 }, /* R1434 */
1540 { 0x0000, 0x0000 }, /* R1435 */
1541 { 0x0000, 0x0000 }, /* R1436 */
1542 { 0x0000, 0x0000 }, /* R1437 */
1543 { 0x0000, 0x0000 }, /* R1438 */
1544 { 0x0000, 0x0000 }, /* R1439 */
1545 { 0x0000, 0x0000 }, /* R1440 */
1546 { 0x0000, 0x0000 }, /* R1441 */
1547 { 0x0000, 0x0000 }, /* R1442 */
1548 { 0x0000, 0x0000 }, /* R1443 */
1549 { 0x0000, 0x0000 }, /* R1444 */
1550 { 0x0000, 0x0000 }, /* R1445 */
1551 { 0x0000, 0x0000 }, /* R1446 */
1552 { 0x0000, 0x0000 }, /* R1447 */
1553 { 0x0000, 0x0000 }, /* R1448 */
1554 { 0x0000, 0x0000 }, /* R1449 */
1555 { 0x0000, 0x0000 }, /* R1450 */
1556 { 0x0000, 0x0000 }, /* R1451 */
1557 { 0x0000, 0x0000 }, /* R1452 */
1558 { 0x0000, 0x0000 }, /* R1453 */
1559 { 0x0000, 0x0000 }, /* R1454 */
1560 { 0x0000, 0x0000 }, /* R1455 */
1561 { 0x0000, 0x0000 }, /* R1456 */
1562 { 0x0000, 0x0000 }, /* R1457 */
1563 { 0x0000, 0x0000 }, /* R1458 */
1564 { 0x0000, 0x0000 }, /* R1459 */
1565 { 0x0000, 0x0000 }, /* R1460 */
1566 { 0x0000, 0x0000 }, /* R1461 */
1567 { 0x0000, 0x0000 }, /* R1462 */
1568 { 0x0000, 0x0000 }, /* R1463 */
1569 { 0x0000, 0x0000 }, /* R1464 */
1570 { 0x0000, 0x0000 }, /* R1465 */
1571 { 0x0000, 0x0000 }, /* R1466 */
1572 { 0x0000, 0x0000 }, /* R1467 */
1573 { 0x0000, 0x0000 }, /* R1468 */
1574 { 0x0000, 0x0000 }, /* R1469 */
1575 { 0x0000, 0x0000 }, /* R1470 */
1576 { 0x0000, 0x0000 }, /* R1471 */
1577 { 0x0000, 0x0000 }, /* R1472 */
1578 { 0x0000, 0x0000 }, /* R1473 */
1579 { 0x0000, 0x0000 }, /* R1474 */
1580 { 0x0000, 0x0000 }, /* R1475 */
1581 { 0x0000, 0x0000 }, /* R1476 */
1582 { 0x0000, 0x0000 }, /* R1477 */
1583 { 0x0000, 0x0000 }, /* R1478 */
1584 { 0x0000, 0x0000 }, /* R1479 */
1585 { 0x0000, 0x0000 }, /* R1480 */
1586 { 0x0000, 0x0000 }, /* R1481 */
1587 { 0x0000, 0x0000 }, /* R1482 */
1588 { 0x0000, 0x0000 }, /* R1483 */
1589 { 0x0000, 0x0000 }, /* R1484 */
1590 { 0x0000, 0x0000 }, /* R1485 */
1591 { 0x0000, 0x0000 }, /* R1486 */
1592 { 0x0000, 0x0000 }, /* R1487 */
1593 { 0x0000, 0x0000 }, /* R1488 */
1594 { 0x0000, 0x0000 }, /* R1489 */
1595 { 0x0000, 0x0000 }, /* R1490 */
1596 { 0x0000, 0x0000 }, /* R1491 */
1597 { 0x0000, 0x0000 }, /* R1492 */
1598 { 0x0000, 0x0000 }, /* R1493 */
1599 { 0x0000, 0x0000 }, /* R1494 */
1600 { 0x0000, 0x0000 }, /* R1495 */
1601 { 0x0000, 0x0000 }, /* R1496 */
1602 { 0x0000, 0x0000 }, /* R1497 */
1603 { 0x0000, 0x0000 }, /* R1498 */
1604 { 0x0000, 0x0000 }, /* R1499 */
1605 { 0x0000, 0x0000 }, /* R1500 */
1606 { 0x0000, 0x0000 }, /* R1501 */
1607 { 0x0000, 0x0000 }, /* R1502 */
1608 { 0x0000, 0x0000 }, /* R1503 */
1609 { 0x0000, 0x0000 }, /* R1504 */
1610 { 0x0000, 0x0000 }, /* R1505 */
1611 { 0x0000, 0x0000 }, /* R1506 */
1612 { 0x0000, 0x0000 }, /* R1507 */
1613 { 0x0000, 0x0000 }, /* R1508 */
1614 { 0x0000, 0x0000 }, /* R1509 */
1615 { 0x0000, 0x0000 }, /* R1510 */
1616 { 0x0000, 0x0000 }, /* R1511 */
1617 { 0x0000, 0x0000 }, /* R1512 */
1618 { 0x0000, 0x0000 }, /* R1513 */
1619 { 0x0000, 0x0000 }, /* R1514 */
1620 { 0x0000, 0x0000 }, /* R1515 */
1621 { 0x0000, 0x0000 }, /* R1516 */
1622 { 0x0000, 0x0000 }, /* R1517 */
1623 { 0x0000, 0x0000 }, /* R1518 */
1624 { 0x0000, 0x0000 }, /* R1519 */
1625 { 0x0000, 0x0000 }, /* R1520 */
1626 { 0x0000, 0x0000 }, /* R1521 */
1627 { 0x0000, 0x0000 }, /* R1522 */
1628 { 0x0000, 0x0000 }, /* R1523 */
1629 { 0x0000, 0x0000 }, /* R1524 */
1630 { 0x0000, 0x0000 }, /* R1525 */
1631 { 0x0000, 0x0000 }, /* R1526 */
1632 { 0x0000, 0x0000 }, /* R1527 */
1633 { 0x0000, 0x0000 }, /* R1528 */
1634 { 0x0000, 0x0000 }, /* R1529 */
1635 { 0x0000, 0x0000 }, /* R1530 */
1636 { 0x0000, 0x0000 }, /* R1531 */
1637 { 0x0000, 0x0000 }, /* R1532 */
1638 { 0x0000, 0x0000 }, /* R1533 */
1639 { 0x0000, 0x0000 }, /* R1534 */
1640 { 0x0000, 0x0000 }, /* R1535 */
1641 { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
1642 { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
1643 { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
1644 { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
1645 { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
1646 { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
1647 { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1648 { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1649 { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1650 { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1651 { 0x0000, 0x0000 }, /* R1546 */
1652 { 0x0000, 0x0000 }, /* R1547 */
1653 { 0x0000, 0x0000 }, /* R1548 */
1654 { 0x0000, 0x0000 }, /* R1549 */
1655 { 0x0000, 0x0000 }, /* R1550 */
1656 { 0x0000, 0x0000 }, /* R1551 */
1657 { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
1658 { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
1659 { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
1660 { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
1661 { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
1662 { 0x0000, 0x0000 }, /* R1557 */
1663 { 0x0000, 0x0000 }, /* R1558 */
1664 { 0x0000, 0x0000 }, /* R1559 */
1665 { 0x0000, 0x0000 }, /* R1560 */
1666 { 0x0000, 0x0000 }, /* R1561 */
1667 { 0x0000, 0x0000 }, /* R1562 */
1668 { 0x0000, 0x0000 }, /* R1563 */
1669 { 0x0000, 0x0000 }, /* R1564 */
1670 { 0x0000, 0x0000 }, /* R1565 */
1671 { 0x0000, 0x0000 }, /* R1566 */
1672 { 0x0000, 0x0000 }, /* R1567 */
1673 { 0x0003, 0x0003 }, /* R1568 - Oversampling */
1674 { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
1675};
1676
1677static int wm8994_readable(unsigned int reg) 112static int wm8994_readable(unsigned int reg)
1678{ 113{
1679 switch (reg) { 114 switch (reg) {
@@ -1696,14 +131,14 @@ static int wm8994_readable(unsigned int reg)
1696 break; 131 break;
1697 } 132 }
1698 133
1699 if (reg >= ARRAY_SIZE(access_masks)) 134 if (reg >= WM8994_CACHE_SIZE)
1700 return 0; 135 return 0;
1701 return access_masks[reg].readable != 0; 136 return wm8994_access_masks[reg].readable != 0;
1702} 137}
1703 138
1704static int wm8994_volatile(unsigned int reg) 139static int wm8994_volatile(unsigned int reg)
1705{ 140{
1706 if (reg >= WM8994_REG_CACHE_SIZE) 141 if (reg >= WM8994_CACHE_SIZE)
1707 return 1; 142 return 1;
1708 143
1709 switch (reg) { 144 switch (reg) {
@@ -1714,6 +149,8 @@ static int wm8994_volatile(unsigned int reg)
1714 case WM8994_RATE_STATUS: 149 case WM8994_RATE_STATUS:
1715 case WM8994_LDO_1: 150 case WM8994_LDO_1:
1716 case WM8994_LDO_2: 151 case WM8994_LDO_2:
152 case WM8958_DSP2_EXECCONTROL:
153 case WM8958_MIC_DETECT_3:
1717 return 1; 154 return 1;
1718 default: 155 default:
1719 return 0; 156 return 0;
@@ -1723,14 +160,16 @@ static int wm8994_volatile(unsigned int reg)
1723static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 160static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1724 unsigned int value) 161 unsigned int value)
1725{ 162{
1726 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 163 int ret;
1727 164
1728 BUG_ON(reg > WM8994_MAX_REGISTER); 165 BUG_ON(reg > WM8994_MAX_REGISTER);
1729 166
1730 if (!wm8994_volatile(reg)) 167 if (!wm8994_volatile(reg)) {
1731 wm8994->reg_cache[reg] = value; 168 ret = snd_soc_cache_write(codec, reg, value);
1732 169 if (ret != 0)
1733 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); 170 dev_err(codec->dev, "Cache write to %x failed: %d\n",
171 reg, ret);
172 }
1734 173
1735 return wm8994_reg_write(codec->control_data, reg, value); 174 return wm8994_reg_write(codec->control_data, reg, value);
1736} 175}
@@ -1738,14 +177,22 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1738static unsigned int wm8994_read(struct snd_soc_codec *codec, 177static unsigned int wm8994_read(struct snd_soc_codec *codec,
1739 unsigned int reg) 178 unsigned int reg)
1740{ 179{
1741 u16 *reg_cache = codec->reg_cache; 180 unsigned int val;
181 int ret;
1742 182
1743 BUG_ON(reg > WM8994_MAX_REGISTER); 183 BUG_ON(reg > WM8994_MAX_REGISTER);
1744 184
1745 if (wm8994_volatile(reg)) 185 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
1746 return wm8994_reg_read(codec->control_data, reg); 186 reg < codec->driver->reg_cache_size) {
1747 else 187 ret = snd_soc_cache_read(codec, reg, &val);
1748 return reg_cache[reg]; 188 if (ret >= 0)
189 return val;
190 else
191 dev_err(codec->dev, "Cache read from %x failed: %d\n",
192 reg, ret);
193 }
194
195 return wm8994_reg_read(codec->control_data, reg);
1749} 196}
1750 197
1751static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 198static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
@@ -1837,7 +284,7 @@ static int configure_clock(struct snd_soc_codec *codec)
1837 284
1838 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 285 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1839 286
1840 snd_soc_dapm_sync(codec); 287 snd_soc_dapm_sync(&codec->dapm);
1841 288
1842 return 0; 289 return 0;
1843} 290}
@@ -1864,6 +311,19 @@ static const char *sidetone_hpf_text[] = {
1864static const struct soc_enum sidetone_hpf = 311static const struct soc_enum sidetone_hpf =
1865 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1866 313
314static const char *adc_hpf_text[] = {
315 "HiFi", "Voice 1", "Voice 2", "Voice 3"
316};
317
318static const struct soc_enum aif1adc1_hpf =
319 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
320
321static const struct soc_enum aif1adc2_hpf =
322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
323
324static const struct soc_enum aif2adc_hpf =
325 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
326
1867static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 327static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1868static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 328static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1869static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 329static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
@@ -2071,21 +531,252 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2071 return 0; 531 return 0;
2072} 532}
2073 533
2074static const char *aifdac_src_text[] = { 534static const char *aif_chan_src_text[] = {
2075 "Left", "Right" 535 "Left", "Right"
2076}; 536};
2077 537
538static const struct soc_enum aif1adcl_src =
539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
540
541static const struct soc_enum aif1adcr_src =
542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
543
544static const struct soc_enum aif2adcl_src =
545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
546
547static const struct soc_enum aif2adcr_src =
548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
549
2078static const struct soc_enum aif1dacl_src = 550static const struct soc_enum aif1dacl_src =
2079 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aifdac_src_text); 551 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
2080 552
2081static const struct soc_enum aif1dacr_src = 553static const struct soc_enum aif1dacr_src =
2082 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aifdac_src_text); 554 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
2083 555
2084static const struct soc_enum aif2dacl_src = 556static const struct soc_enum aif2dacl_src =
2085 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aifdac_src_text); 557 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
2086 558
2087static const struct soc_enum aif2dacr_src = 559static const struct soc_enum aif2dacr_src =
2088 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aifdac_src_text); 560 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
561
562static const char *osr_text[] = {
563 "Low Power", "High Performance",
564};
565
566static const struct soc_enum dac_osr =
567 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
568
569static const struct soc_enum adc_osr =
570 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
571
572static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
573{
574 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
575 struct wm8994_pdata *pdata = wm8994->pdata;
576 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
577 int ena, reg, aif, i;
578
579 switch (mbc) {
580 case 0:
581 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
582 aif = 0;
583 break;
584 case 1:
585 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
586 aif = 0;
587 break;
588 case 2:
589 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
590 aif = 1;
591 break;
592 default:
593 BUG();
594 return;
595 }
596
597 /* We can only enable the MBC if the AIF is enabled and we
598 * want it to be enabled. */
599 ena = pwr_reg && wm8994->mbc_ena[mbc];
600
601 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
602
603 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
604 mbc, start, pwr_reg, reg);
605
606 if (start && ena) {
607 /* If the DSP is already running then noop */
608 if (reg & WM8958_DSP2_ENA)
609 return;
610
611 /* Switch the clock over to the appropriate AIF */
612 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
613 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
614 aif << WM8958_DSP2CLK_SRC_SHIFT |
615 WM8958_DSP2CLK_ENA);
616
617 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
618 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
619
620 /* If we've got user supplied MBC settings use them */
621 if (pdata && pdata->num_mbc_cfgs) {
622 struct wm8958_mbc_cfg *cfg
623 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
624
625 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
626 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
627 cfg->coeff_regs[i]);
628
629 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
630 snd_soc_write(codec,
631 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
632 cfg->cutoff_regs[i]);
633 }
634
635 /* Run the DSP */
636 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
637 WM8958_DSP2_RUNR);
638
639 /* And we're off! */
640 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
641 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
642 mbc << WM8958_MBC_SEL_SHIFT |
643 WM8958_MBC_ENA);
644 } else {
645 /* If the DSP is already stopped then noop */
646 if (!(reg & WM8958_DSP2_ENA))
647 return;
648
649 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
650 WM8958_MBC_ENA, 0);
651 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
652 WM8958_DSP2_ENA, 0);
653 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
654 WM8958_DSP2CLK_ENA, 0);
655 }
656}
657
658static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
659 struct snd_kcontrol *kcontrol, int event)
660{
661 struct snd_soc_codec *codec = w->codec;
662 int mbc;
663
664 switch (w->shift) {
665 case 13:
666 case 12:
667 mbc = 2;
668 break;
669 case 11:
670 case 10:
671 mbc = 1;
672 break;
673 case 9:
674 case 8:
675 mbc = 0;
676 break;
677 default:
678 BUG();
679 return -EINVAL;
680 }
681
682 switch (event) {
683 case SND_SOC_DAPM_POST_PMU:
684 wm8958_mbc_apply(codec, mbc, 1);
685 break;
686 case SND_SOC_DAPM_POST_PMD:
687 wm8958_mbc_apply(codec, mbc, 0);
688 break;
689 }
690
691 return 0;
692}
693
694static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
698 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
699 struct wm8994_pdata *pdata = wm8994->pdata;
700 int value = ucontrol->value.integer.value[0];
701 int reg;
702
703 /* Don't allow on the fly reconfiguration */
704 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
705 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
706 return -EBUSY;
707
708 if (value >= pdata->num_mbc_cfgs)
709 return -EINVAL;
710
711 wm8994->mbc_cfg = value;
712
713 return 0;
714}
715
716static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
717 struct snd_ctl_elem_value *ucontrol)
718{
719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
720 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
721
722 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
723
724 return 0;
725}
726
727static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_info *uinfo)
729{
730 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
731 uinfo->count = 1;
732 uinfo->value.integer.min = 0;
733 uinfo->value.integer.max = 1;
734 return 0;
735}
736
737static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
739{
740 int mbc = kcontrol->private_value;
741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
742 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
743
744 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
745
746 return 0;
747}
748
749static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
750 struct snd_ctl_elem_value *ucontrol)
751{
752 int mbc = kcontrol->private_value;
753 int i;
754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
756
757 if (ucontrol->value.integer.value[0] > 1)
758 return -EINVAL;
759
760 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
761 if (mbc != i && wm8994->mbc_ena[i]) {
762 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
763 return -EBUSY;
764 }
765 }
766
767 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
768
769 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
770
771 return 0;
772}
773
774#define WM8958_MBC_SWITCH(xname, xval) {\
775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
776 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
777 .info = wm8958_mbc_info, \
778 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
779 .private_value = xval }
2089 780
2090static const struct snd_kcontrol_new wm8994_snd_controls[] = { 781static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2091SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 782SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
@@ -2098,10 +789,15 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2098 WM8994_AIF2_ADC_RIGHT_VOLUME, 789 WM8994_AIF2_ADC_RIGHT_VOLUME,
2099 1, 119, 0, digital_tlv), 790 1, 119, 0, digital_tlv),
2100 791
792SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
793SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
794SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
795SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
796
2101SOC_ENUM("AIF1DACL Source", aif1dacl_src), 797SOC_ENUM("AIF1DACL Source", aif1dacl_src),
2102SOC_ENUM("AIF1DACR Source", aif1dacr_src), 798SOC_ENUM("AIF1DACR Source", aif1dacr_src),
2103SOC_ENUM("AIF2DACL Source", aif1dacl_src), 799SOC_ENUM("AIF2DACL Source", aif2dacl_src),
2104SOC_ENUM("AIF2DACR Source", aif1dacr_src), 800SOC_ENUM("AIF2DACR Source", aif2dacr_src),
2105 801
2106SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 802SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2107 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 803 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
@@ -2140,6 +836,18 @@ SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2140SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 836SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2141SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 837SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2142 838
839SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
840SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
841
842SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
843SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
844
845SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
846SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
847
848SOC_ENUM("ADC OSR", adc_osr),
849SOC_ENUM("DAC OSR", dac_osr),
850
2143SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 851SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2144 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 852 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2145SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 853SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
@@ -2162,15 +870,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2162 870
2163SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 871SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2164 10, 15, 0, wm8994_3d_tlv), 872 10, 15, 0, wm8994_3d_tlv),
2165SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 873SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
2166 8, 1, 0), 874 8, 1, 0),
2167SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 875SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2168 10, 15, 0, wm8994_3d_tlv), 876 10, 15, 0, wm8994_3d_tlv),
2169SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 877SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2170 8, 1, 0), 878 8, 1, 0),
2171SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 879SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
2172 10, 15, 0, wm8994_3d_tlv), 880 10, 15, 0, wm8994_3d_tlv),
2173SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 881SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
2174 8, 1, 0), 882 8, 1, 0),
2175}; 883};
2176 884
@@ -2209,6 +917,13 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2209 eq_tlv), 917 eq_tlv),
2210}; 918};
2211 919
920static const struct snd_kcontrol_new wm8958_snd_controls[] = {
921SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
922WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
923WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
924WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
925};
926
2212static int clk_sys_event(struct snd_soc_dapm_widget *w, 927static int clk_sys_event(struct snd_soc_dapm_widget *w,
2213 struct snd_kcontrol *kcontrol, int event) 928 struct snd_kcontrol *kcontrol, int event)
2214{ 929{
@@ -2228,6 +943,7 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
2228 943
2229static void wm8994_update_class_w(struct snd_soc_codec *codec) 944static void wm8994_update_class_w(struct snd_soc_codec *codec)
2230{ 945{
946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2231 int enable = 1; 947 int enable = 1;
2232 int source = 0; /* GCC flow analysis can't track enable */ 948 int source = 0; /* GCC flow analysis can't track enable */
2233 int reg, reg_r; 949 int reg, reg_r;
@@ -2278,11 +994,13 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
2278 WM8994_CP_DYN_PWR | 994 WM8994_CP_DYN_PWR |
2279 WM8994_CP_DYN_SRC_SEL_MASK, 995 WM8994_CP_DYN_SRC_SEL_MASK,
2280 source | WM8994_CP_DYN_PWR); 996 source | WM8994_CP_DYN_PWR);
997 wm8994->hubs.class_w = true;
2281 998
2282 } else { 999 } else {
2283 dev_dbg(codec->dev, "Class W disabled\n"); 1000 dev_dbg(codec->dev, "Class W disabled\n");
2284 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1001 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2285 WM8994_CP_DYN_PWR, 0); 1002 WM8994_CP_DYN_PWR, 0);
1003 wm8994->hubs.class_w = false;
2286 } 1004 }
2287} 1005}
2288 1006
@@ -2512,14 +1230,47 @@ static const struct snd_kcontrol_new aif2adc_mux =
2512 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1230 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2513 1231
2514static const char *aif3adc_text[] = { 1232static const char *aif3adc_text[] = {
2515 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", 1233 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
2516}; 1234};
2517 1235
2518static const struct soc_enum aif3adc_enum = 1236static const struct soc_enum wm8994_aif3adc_enum =
2519 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1237 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2520 1238
2521static const struct snd_kcontrol_new aif3adc_mux = 1239static const struct snd_kcontrol_new wm8994_aif3adc_mux =
2522 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); 1240 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1241
1242static const struct soc_enum wm8958_aif3adc_enum =
1243 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1244
1245static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1246 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1247
1248static const char *mono_pcm_out_text[] = {
1249 "None", "AIF2ADCL", "AIF2ADCR",
1250};
1251
1252static const struct soc_enum mono_pcm_out_enum =
1253 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1254
1255static const struct snd_kcontrol_new mono_pcm_out_mux =
1256 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1257
1258static const char *aif2dac_src_text[] = {
1259 "AIF2", "AIF3",
1260};
1261
1262/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1263static const struct soc_enum aif2dacl_src_enum =
1264 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1265
1266static const struct snd_kcontrol_new aif2dacl_src_mux =
1267 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1268
1269static const struct soc_enum aif2dacr_src_enum =
1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1271
1272static const struct snd_kcontrol_new aif2dacr_src_mux =
1273 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
2523 1274
2524static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1275static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2525SND_SOC_DAPM_INPUT("DMIC1DAT"), 1276SND_SOC_DAPM_INPUT("DMIC1DAT"),
@@ -2540,19 +1291,23 @@ SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
2540 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1291 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2541SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 1292SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
2542 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1293 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2543SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, 1294SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
2544 WM8994_POWER_MANAGEMENT_5, 9, 0), 1295 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
2545SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, 1296 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2546 WM8994_POWER_MANAGEMENT_5, 8, 0), 1297SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1298 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1299 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2547 1300
2548SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 1301SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
2549 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1302 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2550SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 1303SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
2551 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1304 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2552SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, 1305SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
2553 WM8994_POWER_MANAGEMENT_5, 11, 0), 1306 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
2554SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, 1307 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2555 WM8994_POWER_MANAGEMENT_5, 10, 0), 1308SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1309 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1310 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2556 1311
2557SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1312SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2558 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1313 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
@@ -2581,10 +1336,12 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2581 WM8994_POWER_MANAGEMENT_4, 13, 0), 1336 WM8994_POWER_MANAGEMENT_4, 13, 0),
2582SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1337SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2583 WM8994_POWER_MANAGEMENT_4, 12, 0), 1338 WM8994_POWER_MANAGEMENT_4, 12, 0),
2584SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, 1339SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
2585 WM8994_POWER_MANAGEMENT_5, 13, 0), 1340 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
2586SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, 1341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2587 WM8994_POWER_MANAGEMENT_5, 12, 0), 1342SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1343 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1344 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2588 1345
2589SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1346SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2590SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1347SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
@@ -2593,7 +1350,6 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2593SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1350SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2594SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1351SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2595SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1352SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2596SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2597 1353
2598SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1354SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2599SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1355SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
@@ -2631,8 +1387,18 @@ SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2631SND_SOC_DAPM_POST("Debug log", post_ev), 1387SND_SOC_DAPM_POST("Debug log", post_ev),
2632}; 1388};
2633 1389
2634static const struct snd_soc_dapm_route intercon[] = { 1390static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1391SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1392};
1393
1394static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1395SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1396SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1397SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1398SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1399};
2635 1400
1401static const struct snd_soc_dapm_route intercon[] = {
2636 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1402 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2637 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1403 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2638 1404
@@ -2740,9 +1506,6 @@ static const struct snd_soc_dapm_route intercon[] = {
2740 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1506 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2741 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1507 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2742 1508
2743 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2744 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2745
2746 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1509 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2747 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1510 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2748 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1511 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
@@ -2815,6 +1578,26 @@ static const struct snd_soc_dapm_route intercon[] = {
2815 { "Right Headphone Mux", "DAC", "DAC1R" }, 1578 { "Right Headphone Mux", "DAC", "DAC1R" },
2816}; 1579};
2817 1580
1581static const struct snd_soc_dapm_route wm8994_intercon[] = {
1582 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1583 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1584};
1585
1586static const struct snd_soc_dapm_route wm8958_intercon[] = {
1587 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1588 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1589
1590 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1591 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1592 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1593 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1594
1595 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1596 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1597
1598 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1599};
1600
2818/* The size in bits of the FLL divide multiplied by 10 1601/* The size in bits of the FLL divide multiplied by 10
2819 * to allow rounding later */ 1602 * to allow rounding later */
2820#define FIXED_FLL_SIZE ((1 << 16) * 10) 1603#define FIXED_FLL_SIZE ((1 << 16) * 10)
@@ -2930,6 +1713,7 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2930 /* Allow no source specification when stopping */ 1713 /* Allow no source specification when stopping */
2931 if (freq_out) 1714 if (freq_out)
2932 return -EINVAL; 1715 return -EINVAL;
1716 src = wm8994->fll[id].src;
2933 break; 1717 break;
2934 case WM8994_FLL_SRC_MCLK1: 1718 case WM8994_FLL_SRC_MCLK1:
2935 case WM8994_FLL_SRC_MCLK2: 1719 case WM8994_FLL_SRC_MCLK2:
@@ -3094,6 +1878,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
3094static int wm8994_set_bias_level(struct snd_soc_codec *codec, 1878static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3095 enum snd_soc_bias_level level) 1879 enum snd_soc_bias_level level)
3096{ 1880{
1881 struct wm8994 *control = codec->control_data;
3097 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1882 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3098 1883
3099 switch (level) { 1884 switch (level) {
@@ -3107,16 +1892,36 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3107 break; 1892 break;
3108 1893
3109 case SND_SOC_BIAS_STANDBY: 1894 case SND_SOC_BIAS_STANDBY:
3110 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1895 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
3111 /* Tweak DC servo and DSP configuration for 1896 pm_runtime_get_sync(codec->dev);
3112 * improved performance. */ 1897
3113 if (wm8994->revision < 4) { 1898 switch (control->type) {
3114 /* Tweak DC servo and DSP configuration for 1899 case WM8994:
3115 * improved performance. */ 1900 if (wm8994->revision < 4) {
3116 snd_soc_write(codec, 0x102, 0x3); 1901 /* Tweak DC servo and DSP
3117 snd_soc_write(codec, 0x56, 0x3); 1902 * configuration for improved
3118 snd_soc_write(codec, 0x817, 0); 1903 * performance. */
3119 snd_soc_write(codec, 0x102, 0); 1904 snd_soc_write(codec, 0x102, 0x3);
1905 snd_soc_write(codec, 0x56, 0x3);
1906 snd_soc_write(codec, 0x817, 0);
1907 snd_soc_write(codec, 0x102, 0);
1908 }
1909 break;
1910
1911 case WM8958:
1912 if (wm8994->revision == 0) {
1913 /* Optimise performance for rev A */
1914 snd_soc_write(codec, 0x102, 0x3);
1915 snd_soc_write(codec, 0xcb, 0x81);
1916 snd_soc_write(codec, 0x817, 0);
1917 snd_soc_write(codec, 0x102, 0);
1918
1919 snd_soc_update_bits(codec,
1920 WM8958_CHARGE_PUMP_2,
1921 WM8958_CP_DISCH,
1922 WM8958_CP_DISCH);
1923 }
1924 break;
3120 } 1925 }
3121 1926
3122 /* Discharge LINEOUT1 & 2 */ 1927 /* Discharge LINEOUT1 & 2 */
@@ -3151,7 +1956,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3151 break; 1956 break;
3152 1957
3153 case SND_SOC_BIAS_OFF: 1958 case SND_SOC_BIAS_OFF:
3154 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 1959 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3155 /* Switch over to startup biases */ 1960 /* Switch over to startup biases */
3156 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3157 WM8994_BIAS_SRC | 1962 WM8994_BIAS_SRC |
@@ -3183,16 +1988,19 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3183 WM8994_STARTUP_BIAS_ENA | 1988 WM8994_STARTUP_BIAS_ENA |
3184 WM8994_VMID_BUF_ENA | 1989 WM8994_VMID_BUF_ENA |
3185 WM8994_VMID_RAMP_MASK, 0); 1990 WM8994_VMID_RAMP_MASK, 0);
1991
1992 pm_runtime_put(codec->dev);
3186 } 1993 }
3187 break; 1994 break;
3188 } 1995 }
3189 codec->bias_level = level; 1996 codec->dapm.bias_level = level;
3190 return 0; 1997 return 0;
3191} 1998}
3192 1999
3193static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2000static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3194{ 2001{
3195 struct snd_soc_codec *codec = dai->codec; 2002 struct snd_soc_codec *codec = dai->codec;
2003 struct wm8994 *control = codec->control_data;
3196 int ms_reg; 2004 int ms_reg;
3197 int aif1_reg; 2005 int aif1_reg;
3198 int ms = 0; 2006 int ms = 0;
@@ -3277,6 +2085,13 @@ static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3277 return -EINVAL; 2085 return -EINVAL;
3278 } 2086 }
3279 2087
2088 /* The AIF2 format configuration needs to be mirrored to AIF3
2089 * on WM8958 if it's in use so just do it all the time. */
2090 if (control->type == WM8958 && dai->id == 2)
2091 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2092 WM8994_AIF1_LRCLK_INV |
2093 WM8958_AIF3_FMT_MASK, aif1);
2094
3280 snd_soc_update_bits(codec, aif1_reg, 2095 snd_soc_update_bits(codec, aif1_reg,
3281 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2096 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3282 WM8994_AIF1_FMT_MASK, 2097 WM8994_AIF1_FMT_MASK,
@@ -3317,12 +2132,15 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3317 struct snd_soc_dai *dai) 2132 struct snd_soc_dai *dai)
3318{ 2133{
3319 struct snd_soc_codec *codec = dai->codec; 2134 struct snd_soc_codec *codec = dai->codec;
2135 struct wm8994 *control = codec->control_data;
3320 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2136 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3321 int aif1_reg; 2137 int aif1_reg;
2138 int aif2_reg;
3322 int bclk_reg; 2139 int bclk_reg;
3323 int lrclk_reg; 2140 int lrclk_reg;
3324 int rate_reg; 2141 int rate_reg;
3325 int aif1 = 0; 2142 int aif1 = 0;
2143 int aif2 = 0;
3326 int bclk = 0; 2144 int bclk = 0;
3327 int lrclk = 0; 2145 int lrclk = 0;
3328 int rate_val = 0; 2146 int rate_val = 0;
@@ -3333,6 +2151,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3333 switch (dai->id) { 2151 switch (dai->id) {
3334 case 1: 2152 case 1:
3335 aif1_reg = WM8994_AIF1_CONTROL_1; 2153 aif1_reg = WM8994_AIF1_CONTROL_1;
2154 aif2_reg = WM8994_AIF1_CONTROL_2;
3336 bclk_reg = WM8994_AIF1_BCLK; 2155 bclk_reg = WM8994_AIF1_BCLK;
3337 rate_reg = WM8994_AIF1_RATE; 2156 rate_reg = WM8994_AIF1_RATE;
3338 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
@@ -3345,6 +2164,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3345 break; 2164 break;
3346 case 2: 2165 case 2:
3347 aif1_reg = WM8994_AIF2_CONTROL_1; 2166 aif1_reg = WM8994_AIF2_CONTROL_1;
2167 aif2_reg = WM8994_AIF2_CONTROL_2;
3348 bclk_reg = WM8994_AIF2_BCLK; 2168 bclk_reg = WM8994_AIF2_BCLK;
3349 rate_reg = WM8994_AIF2_RATE; 2169 rate_reg = WM8994_AIF2_RATE;
3350 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
@@ -3355,6 +2175,14 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3355 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2175 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
3356 } 2176 }
3357 break; 2177 break;
2178 case 3:
2179 switch (control->type) {
2180 case WM8958:
2181 aif1_reg = WM8958_AIF3_CONTROL_1;
2182 break;
2183 default:
2184 return 0;
2185 }
3358 default: 2186 default:
3359 return -EINVAL; 2187 return -EINVAL;
3360 } 2188 }
@@ -3392,6 +2220,10 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3392 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2220 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3393 dai->id, wm8994->aifclk[id], bclk_rate); 2221 dai->id, wm8994->aifclk[id], bclk_rate);
3394 2222
2223 if (params_channels(params) == 1 &&
2224 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2225 aif2 |= WM8994_AIF1_MONO;
2226
3395 if (wm8994->aifclk[id] == 0) { 2227 if (wm8994->aifclk[id] == 0) {
3396 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2228 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3397 return -EINVAL; 2229 return -EINVAL;
@@ -3435,6 +2267,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3435 lrclk, bclk_rate / lrclk); 2267 lrclk, bclk_rate / lrclk);
3436 2268
3437 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2269 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2270 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
3438 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2271 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3439 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2272 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3440 lrclk); 2273 lrclk);
@@ -3458,6 +2291,47 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3458 return 0; 2291 return 0;
3459} 2292}
3460 2293
2294static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2295 struct snd_pcm_hw_params *params,
2296 struct snd_soc_dai *dai)
2297{
2298 struct snd_soc_codec *codec = dai->codec;
2299 struct wm8994 *control = codec->control_data;
2300 int aif1_reg;
2301 int aif1 = 0;
2302
2303 switch (dai->id) {
2304 case 3:
2305 switch (control->type) {
2306 case WM8958:
2307 aif1_reg = WM8958_AIF3_CONTROL_1;
2308 break;
2309 default:
2310 return 0;
2311 }
2312 default:
2313 return 0;
2314 }
2315
2316 switch (params_format(params)) {
2317 case SNDRV_PCM_FORMAT_S16_LE:
2318 break;
2319 case SNDRV_PCM_FORMAT_S20_3LE:
2320 aif1 |= 0x20;
2321 break;
2322 case SNDRV_PCM_FORMAT_S24_LE:
2323 aif1 |= 0x40;
2324 break;
2325 case SNDRV_PCM_FORMAT_S32_LE:
2326 aif1 |= 0x60;
2327 break;
2328 default:
2329 return -EINVAL;
2330 }
2331
2332 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2333}
2334
3461static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2335static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3462{ 2336{
3463 struct snd_soc_codec *codec = codec_dai->codec; 2337 struct snd_soc_codec *codec = codec_dai->codec;
@@ -3539,6 +2413,7 @@ static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3539}; 2413};
3540 2414
3541static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2415static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2416 .hw_params = wm8994_aif3_hw_params,
3542 .set_tristate = wm8994_set_tristate, 2417 .set_tristate = wm8994_set_tristate,
3543}; 2418};
3544 2419
@@ -3548,14 +2423,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3548 .id = 1, 2423 .id = 1,
3549 .playback = { 2424 .playback = {
3550 .stream_name = "AIF1 Playback", 2425 .stream_name = "AIF1 Playback",
3551 .channels_min = 2, 2426 .channels_min = 1,
3552 .channels_max = 2, 2427 .channels_max = 2,
3553 .rates = WM8994_RATES, 2428 .rates = WM8994_RATES,
3554 .formats = WM8994_FORMATS, 2429 .formats = WM8994_FORMATS,
3555 }, 2430 },
3556 .capture = { 2431 .capture = {
3557 .stream_name = "AIF1 Capture", 2432 .stream_name = "AIF1 Capture",
3558 .channels_min = 2, 2433 .channels_min = 1,
3559 .channels_max = 2, 2434 .channels_max = 2,
3560 .rates = WM8994_RATES, 2435 .rates = WM8994_RATES,
3561 .formats = WM8994_FORMATS, 2436 .formats = WM8994_FORMATS,
@@ -3567,14 +2442,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3567 .id = 2, 2442 .id = 2,
3568 .playback = { 2443 .playback = {
3569 .stream_name = "AIF2 Playback", 2444 .stream_name = "AIF2 Playback",
3570 .channels_min = 2, 2445 .channels_min = 1,
3571 .channels_max = 2, 2446 .channels_max = 2,
3572 .rates = WM8994_RATES, 2447 .rates = WM8994_RATES,
3573 .formats = WM8994_FORMATS, 2448 .formats = WM8994_FORMATS,
3574 }, 2449 },
3575 .capture = { 2450 .capture = {
3576 .stream_name = "AIF2 Capture", 2451 .stream_name = "AIF2 Capture",
3577 .channels_min = 2, 2452 .channels_min = 1,
3578 .channels_max = 2, 2453 .channels_max = 2,
3579 .rates = WM8994_RATES, 2454 .rates = WM8994_RATES,
3580 .formats = WM8994_FORMATS, 2455 .formats = WM8994_FORMATS,
@@ -3586,14 +2461,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3586 .id = 3, 2461 .id = 3,
3587 .playback = { 2462 .playback = {
3588 .stream_name = "AIF3 Playback", 2463 .stream_name = "AIF3 Playback",
3589 .channels_min = 2, 2464 .channels_min = 1,
3590 .channels_max = 2, 2465 .channels_max = 2,
3591 .rates = WM8994_RATES, 2466 .rates = WM8994_RATES,
3592 .formats = WM8994_FORMATS, 2467 .formats = WM8994_FORMATS,
3593 }, 2468 },
3594 .capture = { 2469 .capture = {
3595 .stream_name = "AIF3 Capture", 2470 .stream_name = "AIF3 Capture",
3596 .channels_min = 2, 2471 .channels_min = 1,
3597 .channels_max = 2, 2472 .channels_max = 2,
3598 .rates = WM8994_RATES, 2473 .rates = WM8994_RATES,
3599 .formats = WM8994_FORMATS, 2474 .formats = WM8994_FORMATS,
@@ -3625,26 +2500,12 @@ static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
3625static int wm8994_resume(struct snd_soc_codec *codec) 2500static int wm8994_resume(struct snd_soc_codec *codec)
3626{ 2501{
3627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2502 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3628 u16 *reg_cache = codec->reg_cache;
3629 int i, ret; 2503 int i, ret;
3630 2504
3631 /* Restore the registers */ 2505 /* Restore the registers */
3632 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { 2506 ret = snd_soc_cache_sync(codec);
3633 switch (i) { 2507 if (ret != 0)
3634 case WM8994_LDO_1: 2508 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
3635 case WM8994_LDO_2:
3636 case WM8994_SOFTWARE_RESET:
3637 /* Handled by other MFD drivers */
3638 continue;
3639 default:
3640 break;
3641 }
3642
3643 if (!access_masks[i].writable)
3644 continue;
3645
3646 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3647 }
3648 2509
3649 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2510 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3650 2511
@@ -3794,6 +2655,34 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3794 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2655 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3795 pdata->num_retune_mobile_cfgs); 2656 pdata->num_retune_mobile_cfgs);
3796 2657
2658 if (pdata->num_mbc_cfgs) {
2659 struct snd_kcontrol_new control[] = {
2660 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2661 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2662 };
2663
2664 /* We need an array of texts for the enum API */
2665 wm8994->mbc_texts = kmalloc(sizeof(char *)
2666 * pdata->num_mbc_cfgs, GFP_KERNEL);
2667 if (!wm8994->mbc_texts) {
2668 dev_err(wm8994->codec->dev,
2669 "Failed to allocate %d MBC config texts\n",
2670 pdata->num_mbc_cfgs);
2671 return;
2672 }
2673
2674 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2675 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2676
2677 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2678 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2679
2680 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2681 if (ret != 0)
2682 dev_err(wm8994->codec->dev,
2683 "Failed to add MBC mode controls: %d\n", ret);
2684 }
2685
3797 if (pdata->num_retune_mobile_cfgs) 2686 if (pdata->num_retune_mobile_cfgs)
3798 wm8994_handle_retune_mobile_pdata(wm8994); 2687 wm8994_handle_retune_mobile_pdata(wm8994);
3799 else 2688 else
@@ -3823,8 +2712,12 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3823{ 2712{
3824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2713 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3825 struct wm8994_micdet *micdet; 2714 struct wm8994_micdet *micdet;
2715 struct wm8994 *control = codec->control_data;
3826 int reg; 2716 int reg;
3827 2717
2718 if (control->type != WM8994)
2719 return -EINVAL;
2720
3828 switch (micbias) { 2721 switch (micbias) {
3829 case 1: 2722 case 1:
3830 micdet = &wm8994->micdet[0]; 2723 micdet = &wm8994->micdet[0];
@@ -3863,6 +2756,10 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3863 int reg; 2756 int reg;
3864 int report; 2757 int report;
3865 2758
2759#ifndef CONFIG_SND_SOC_WM8994_MODULE
2760 trace_snd_soc_jack_irq(dev_name(codec->dev));
2761#endif
2762
3866 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2763 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3867 if (reg < 0) { 2764 if (reg < 0) {
3868 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2765 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -3891,77 +2788,251 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3891 return IRQ_HANDLED; 2788 return IRQ_HANDLED;
3892} 2789}
3893 2790
2791/* Default microphone detection handler for WM8958 - the user can
2792 * override this if they wish.
2793 */
2794static void wm8958_default_micdet(u16 status, void *data)
2795{
2796 struct snd_soc_codec *codec = data;
2797 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2798 int report = 0;
2799
2800 /* If nothing present then clear our statuses */
2801 if (!(status & WM8958_MICD_STS)) {
2802 wm8994->jack_is_video = false;
2803 wm8994->jack_is_mic = false;
2804 goto done;
2805 }
2806
2807 /* Assume anything over 475 ohms is a microphone and remember
2808 * that we've seen one (since buttons override it) */
2809 if (status & 0x600)
2810 wm8994->jack_is_mic = true;
2811 if (wm8994->jack_is_mic)
2812 report |= SND_JACK_MICROPHONE;
2813
2814 /* Video has an impedence of approximately 75 ohms; assume
2815 * this isn't used as a button and remember it since buttons
2816 * override it. */
2817 if (status & 0x40)
2818 wm8994->jack_is_video = true;
2819 if (wm8994->jack_is_video)
2820 report |= SND_JACK_VIDEOOUT;
2821
2822 /* Everything else is buttons; just assign slots */
2823 if (status & 0x4)
2824 report |= SND_JACK_BTN_0;
2825 if (status & 0x8)
2826 report |= SND_JACK_BTN_1;
2827 if (status & 0x10)
2828 report |= SND_JACK_BTN_2;
2829 if (status & 0x20)
2830 report |= SND_JACK_BTN_3;
2831 if (status & 0x80)
2832 report |= SND_JACK_BTN_4;
2833 if (status & 0x100)
2834 report |= SND_JACK_BTN_5;
2835
2836done:
2837 snd_soc_jack_report(wm8994->micdet[0].jack,
2838 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2839 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2840 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2841 report);
2842}
2843
2844/**
2845 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2846 *
2847 * @codec: WM8958 codec
2848 * @jack: jack to report detection events on
2849 *
2850 * Enable microphone detection functionality for the WM8958. By
2851 * default simple detection which supports the detection of up to 6
2852 * buttons plus video and microphone functionality is supported.
2853 *
2854 * The WM8958 has an advanced jack detection facility which is able to
2855 * support complex accessory detection, especially when used in
2856 * conjunction with external circuitry. In order to provide maximum
2857 * flexiblity a callback is provided which allows a completely custom
2858 * detection algorithm.
2859 */
2860int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2861 wm8958_micdet_cb cb, void *cb_data)
2862{
2863 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2864 struct wm8994 *control = codec->control_data;
2865
2866 if (control->type != WM8958)
2867 return -EINVAL;
2868
2869 if (jack) {
2870 if (!cb) {
2871 dev_dbg(codec->dev, "Using default micdet callback\n");
2872 cb = wm8958_default_micdet;
2873 cb_data = codec;
2874 }
2875
2876 wm8994->micdet[0].jack = jack;
2877 wm8994->jack_cb = cb;
2878 wm8994->jack_cb_data = cb_data;
2879
2880 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2881 WM8958_MICD_ENA, WM8958_MICD_ENA);
2882 } else {
2883 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2884 WM8958_MICD_ENA, 0);
2885 }
2886
2887 return 0;
2888}
2889EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2890
2891static irqreturn_t wm8958_mic_irq(int irq, void *data)
2892{
2893 struct wm8994_priv *wm8994 = data;
2894 struct snd_soc_codec *codec = wm8994->codec;
2895 int reg;
2896
2897 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2898 if (reg < 0) {
2899 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2900 reg);
2901 return IRQ_NONE;
2902 }
2903
2904 if (!(reg & WM8958_MICD_VALID)) {
2905 dev_dbg(codec->dev, "Mic detect data not valid\n");
2906 goto out;
2907 }
2908
2909#ifndef CONFIG_SND_SOC_WM8994_MODULE
2910 trace_snd_soc_jack_irq(dev_name(codec->dev));
2911#endif
2912
2913 if (wm8994->jack_cb)
2914 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2915 else
2916 dev_warn(codec->dev, "Accessory detection with no callback\n");
2917
2918out:
2919 return IRQ_HANDLED;
2920}
2921
3894static int wm8994_codec_probe(struct snd_soc_codec *codec) 2922static int wm8994_codec_probe(struct snd_soc_codec *codec)
3895{ 2923{
2924 struct wm8994 *control;
3896 struct wm8994_priv *wm8994; 2925 struct wm8994_priv *wm8994;
2926 struct snd_soc_dapm_context *dapm = &codec->dapm;
3897 int ret, i; 2927 int ret, i;
3898 2928
3899 codec->control_data = dev_get_drvdata(codec->dev->parent); 2929 codec->control_data = dev_get_drvdata(codec->dev->parent);
2930 control = codec->control_data;
3900 2931
3901 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 2932 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3902 if (wm8994 == NULL) 2933 if (wm8994 == NULL)
3903 return -ENOMEM; 2934 return -ENOMEM;
3904 snd_soc_codec_set_drvdata(codec, wm8994); 2935 snd_soc_codec_set_drvdata(codec, wm8994);
3905 2936
3906 codec->reg_cache = &wm8994->reg_cache;
3907
3908 wm8994->pdata = dev_get_platdata(codec->dev->parent); 2937 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3909 wm8994->codec = codec; 2938 wm8994->codec = codec;
3910 2939
3911 /* Fill the cache with physical values we inherited; don't reset */ 2940 pm_runtime_enable(codec->dev);
3912 ret = wm8994_bulk_read(codec->control_data, 0, 2941 pm_runtime_resume(codec->dev);
3913 ARRAY_SIZE(wm8994->reg_cache) - 1,
3914 codec->reg_cache);
3915 if (ret < 0) {
3916 dev_err(codec->dev, "Failed to fill register cache: %d\n",
3917 ret);
3918 goto err;
3919 }
3920 2942
3921 /* Clear the cached values for unreadable/volatile registers to 2943 /* Read our current status back from the chip - we don't want to
3922 * avoid potential confusion. 2944 * reset as this may interfere with the GPIO or LDO operation. */
3923 */ 2945 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3924 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) 2946 if (!wm8994_readable(i) || wm8994_volatile(i))
3925 if (wm8994_volatile(i) || !wm8994_readable(i)) 2947 continue;
3926 wm8994->reg_cache[i] = 0; 2948
2949 ret = wm8994_reg_read(codec->control_data, i);
2950 if (ret <= 0)
2951 continue;
2952
2953 ret = snd_soc_cache_write(codec, i, ret);
2954 if (ret != 0) {
2955 dev_err(codec->dev,
2956 "Failed to initialise cache for 0x%x: %d\n",
2957 i, ret);
2958 goto err;
2959 }
2960 }
3927 2961
3928 /* Set revision-specific configuration */ 2962 /* Set revision-specific configuration */
3929 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 2963 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3930 switch (wm8994->revision) { 2964 switch (control->type) {
3931 case 2: 2965 case WM8994:
3932 case 3: 2966 switch (wm8994->revision) {
3933 wm8994->hubs.dcs_codes = -5; 2967 case 2:
3934 wm8994->hubs.hp_startup_mode = 1; 2968 case 3:
2969 wm8994->hubs.dcs_codes = -5;
2970 wm8994->hubs.hp_startup_mode = 1;
2971 wm8994->hubs.dcs_readback_mode = 1;
2972 break;
2973 default:
2974 wm8994->hubs.dcs_readback_mode = 1;
2975 break;
2976 }
2977
2978 case WM8958:
3935 wm8994->hubs.dcs_readback_mode = 1; 2979 wm8994->hubs.dcs_readback_mode = 1;
3936 break; 2980 break;
2981
3937 default: 2982 default:
3938 wm8994->hubs.dcs_readback_mode = 1;
3939 break; 2983 break;
3940 } 2984 }
3941 2985
3942 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 2986 switch (control->type) {
3943 wm8994_mic_irq, "Mic 1 detect", wm8994); 2987 case WM8994:
3944 if (ret != 0) 2988 ret = wm8994_request_irq(codec->control_data,
3945 dev_warn(codec->dev, 2989 WM8994_IRQ_MIC1_DET,
3946 "Failed to request Mic1 detect IRQ: %d\n", ret); 2990 wm8994_mic_irq, "Mic 1 detect",
3947 2991 wm8994);
3948 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 2992 if (ret != 0)
3949 wm8994_mic_irq, "Mic 1 short", wm8994); 2993 dev_warn(codec->dev,
3950 if (ret != 0) 2994 "Failed to request Mic1 detect IRQ: %d\n",
3951 dev_warn(codec->dev, 2995 ret);
3952 "Failed to request Mic1 short IRQ: %d\n", ret); 2996
3953 2997 ret = wm8994_request_irq(codec->control_data,
3954 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 2998 WM8994_IRQ_MIC1_SHRT,
3955 wm8994_mic_irq, "Mic 2 detect", wm8994); 2999 wm8994_mic_irq, "Mic 1 short",
3956 if (ret != 0) 3000 wm8994);
3957 dev_warn(codec->dev, 3001 if (ret != 0)
3958 "Failed to request Mic2 detect IRQ: %d\n", ret); 3002 dev_warn(codec->dev,
3003 "Failed to request Mic1 short IRQ: %d\n",
3004 ret);
3005
3006 ret = wm8994_request_irq(codec->control_data,
3007 WM8994_IRQ_MIC2_DET,
3008 wm8994_mic_irq, "Mic 2 detect",
3009 wm8994);
3010 if (ret != 0)
3011 dev_warn(codec->dev,
3012 "Failed to request Mic2 detect IRQ: %d\n",
3013 ret);
3014
3015 ret = wm8994_request_irq(codec->control_data,
3016 WM8994_IRQ_MIC2_SHRT,
3017 wm8994_mic_irq, "Mic 2 short",
3018 wm8994);
3019 if (ret != 0)
3020 dev_warn(codec->dev,
3021 "Failed to request Mic2 short IRQ: %d\n",
3022 ret);
3023 break;
3959 3024
3960 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3025 case WM8958:
3961 wm8994_mic_irq, "Mic 2 short", wm8994); 3026 ret = wm8994_request_irq(codec->control_data,
3962 if (ret != 0) 3027 WM8994_IRQ_MIC1_DET,
3963 dev_warn(codec->dev, 3028 wm8958_mic_irq, "Mic detect",
3964 "Failed to request Mic2 short IRQ: %d\n", ret); 3029 wm8994);
3030 if (ret != 0)
3031 dev_warn(codec->dev,
3032 "Failed to request Mic detect IRQ: %d\n",
3033 ret);
3034 break;
3035 }
3965 3036
3966 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3037 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3967 * configured on init - if a system wants to do this dynamically 3038 * configured on init - if a system wants to do this dynamically
@@ -4034,10 +3105,36 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
4034 wm_hubs_add_analogue_controls(codec); 3105 wm_hubs_add_analogue_controls(codec);
4035 snd_soc_add_controls(codec, wm8994_snd_controls, 3106 snd_soc_add_controls(codec, wm8994_snd_controls,
4036 ARRAY_SIZE(wm8994_snd_controls)); 3107 ARRAY_SIZE(wm8994_snd_controls));
4037 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, 3108 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4038 ARRAY_SIZE(wm8994_dapm_widgets)); 3109 ARRAY_SIZE(wm8994_dapm_widgets));
3110
3111 switch (control->type) {
3112 case WM8994:
3113 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3114 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3115 break;
3116 case WM8958:
3117 snd_soc_add_controls(codec, wm8958_snd_controls,
3118 ARRAY_SIZE(wm8958_snd_controls));
3119 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3120 ARRAY_SIZE(wm8958_dapm_widgets));
3121 break;
3122 }
3123
3124
4039 wm_hubs_add_analogue_routes(codec, 0, 0); 3125 wm_hubs_add_analogue_routes(codec, 0, 0);
4040 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 3126 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3127
3128 switch (control->type) {
3129 case WM8994:
3130 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3131 ARRAY_SIZE(wm8994_intercon));
3132 break;
3133 case WM8958:
3134 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3135 ARRAY_SIZE(wm8958_intercon));
3136 break;
3137 }
4041 3138
4042 return 0; 3139 return 0;
4043 3140
@@ -4054,13 +3151,29 @@ err:
4054static int wm8994_codec_remove(struct snd_soc_codec *codec) 3151static int wm8994_codec_remove(struct snd_soc_codec *codec)
4055{ 3152{
4056 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3153 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3154 struct wm8994 *control = codec->control_data;
4057 3155
4058 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3156 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4059 3157
4060 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3158 pm_runtime_disable(codec->dev);
4061 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3159
4062 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3160 switch (control->type) {
4063 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3161 case WM8994:
3162 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3163 wm8994);
3164 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3165 wm8994);
3166 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3167 wm8994);
3168 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3169 wm8994);
3170 break;
3171
3172 case WM8958:
3173 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3174 wm8994);
3175 break;
3176 }
4064 kfree(wm8994->retune_mobile_texts); 3177 kfree(wm8994->retune_mobile_texts);
4065 kfree(wm8994->drc_texts); 3178 kfree(wm8994->drc_texts);
4066 kfree(wm8994); 3179 kfree(wm8994);
@@ -4073,11 +3186,16 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4073 .remove = wm8994_codec_remove, 3186 .remove = wm8994_codec_remove,
4074 .suspend = wm8994_suspend, 3187 .suspend = wm8994_suspend,
4075 .resume = wm8994_resume, 3188 .resume = wm8994_resume,
4076 .read = wm8994_read, 3189 .read = wm8994_read,
4077 .write = wm8994_write, 3190 .write = wm8994_write,
4078 .readable_register = wm8994_readable, 3191 .readable_register = wm8994_readable,
4079 .volatile_register = wm8994_volatile, 3192 .volatile_register = wm8994_volatile,
4080 .set_bias_level = wm8994_set_bias_level, 3193 .set_bias_level = wm8994_set_bias_level,
3194
3195 .reg_cache_size = WM8994_CACHE_SIZE,
3196 .reg_cache_default = wm8994_reg_defaults,
3197 .reg_word_size = 2,
3198 .compress_type = SND_SOC_RBTREE_COMPRESSION,
4081}; 3199};
4082 3200
4083static int __devinit wm8994_probe(struct platform_device *pdev) 3201static int __devinit wm8994_probe(struct platform_device *pdev)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 07:44:14 -0500