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Diffstat (limited to 'sound/soc/codecs/wm8991.h')
-rw-r--r-- | sound/soc/codecs/wm8991.h | 833 |
1 files changed, 833 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8991.h b/sound/soc/codecs/wm8991.h new file mode 100644 index 000000000000..8a942efd18a5 --- /dev/null +++ b/sound/soc/codecs/wm8991.h | |||
@@ -0,0 +1,833 @@ | |||
1 | /* | ||
2 | * wm8991.h -- audio driver for WM8991 | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC. | ||
5 | * Author: Graeme Gregory | ||
6 | * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #ifndef _WM8991_H | ||
15 | #define _WM8991_H | ||
16 | |||
17 | /* | ||
18 | * Register values. | ||
19 | */ | ||
20 | #define WM8991_RESET 0x00 | ||
21 | #define WM8991_POWER_MANAGEMENT_1 0x01 | ||
22 | #define WM8991_POWER_MANAGEMENT_2 0x02 | ||
23 | #define WM8991_POWER_MANAGEMENT_3 0x03 | ||
24 | #define WM8991_AUDIO_INTERFACE_1 0x04 | ||
25 | #define WM8991_AUDIO_INTERFACE_2 0x05 | ||
26 | #define WM8991_CLOCKING_1 0x06 | ||
27 | #define WM8991_CLOCKING_2 0x07 | ||
28 | #define WM8991_AUDIO_INTERFACE_3 0x08 | ||
29 | #define WM8991_AUDIO_INTERFACE_4 0x09 | ||
30 | #define WM8991_DAC_CTRL 0x0A | ||
31 | #define WM8991_LEFT_DAC_DIGITAL_VOLUME 0x0B | ||
32 | #define WM8991_RIGHT_DAC_DIGITAL_VOLUME 0x0C | ||
33 | #define WM8991_DIGITAL_SIDE_TONE 0x0D | ||
34 | #define WM8991_ADC_CTRL 0x0E | ||
35 | #define WM8991_LEFT_ADC_DIGITAL_VOLUME 0x0F | ||
36 | #define WM8991_RIGHT_ADC_DIGITAL_VOLUME 0x10 | ||
37 | #define WM8991_GPIO_CTRL_1 0x12 | ||
38 | #define WM8991_GPIO1_GPIO2 0x13 | ||
39 | #define WM8991_GPIO3_GPIO4 0x14 | ||
40 | #define WM8991_GPIO5_GPIO6 0x15 | ||
41 | #define WM8991_GPIOCTRL_2 0x16 | ||
42 | #define WM8991_GPIO_POL 0x17 | ||
43 | #define WM8991_LEFT_LINE_INPUT_1_2_VOLUME 0x18 | ||
44 | #define WM8991_LEFT_LINE_INPUT_3_4_VOLUME 0x19 | ||
45 | #define WM8991_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A | ||
46 | #define WM8991_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B | ||
47 | #define WM8991_LEFT_OUTPUT_VOLUME 0x1C | ||
48 | #define WM8991_RIGHT_OUTPUT_VOLUME 0x1D | ||
49 | #define WM8991_LINE_OUTPUTS_VOLUME 0x1E | ||
50 | #define WM8991_OUT3_4_VOLUME 0x1F | ||
51 | #define WM8991_LEFT_OPGA_VOLUME 0x20 | ||
52 | #define WM8991_RIGHT_OPGA_VOLUME 0x21 | ||
53 | #define WM8991_SPEAKER_VOLUME 0x22 | ||
54 | #define WM8991_CLASSD1 0x23 | ||
55 | #define WM8991_CLASSD3 0x25 | ||
56 | #define WM8991_INPUT_MIXER1 0x27 | ||
57 | #define WM8991_INPUT_MIXER2 0x28 | ||
58 | #define WM8991_INPUT_MIXER3 0x29 | ||
59 | #define WM8991_INPUT_MIXER4 0x2A | ||
60 | #define WM8991_INPUT_MIXER5 0x2B | ||
61 | #define WM8991_INPUT_MIXER6 0x2C | ||
62 | #define WM8991_OUTPUT_MIXER1 0x2D | ||
63 | #define WM8991_OUTPUT_MIXER2 0x2E | ||
64 | #define WM8991_OUTPUT_MIXER3 0x2F | ||
65 | #define WM8991_OUTPUT_MIXER4 0x30 | ||
66 | #define WM8991_OUTPUT_MIXER5 0x31 | ||
67 | #define WM8991_OUTPUT_MIXER6 0x32 | ||
68 | #define WM8991_OUT3_4_MIXER 0x33 | ||
69 | #define WM8991_LINE_MIXER1 0x34 | ||
70 | #define WM8991_LINE_MIXER2 0x35 | ||
71 | #define WM8991_SPEAKER_MIXER 0x36 | ||
72 | #define WM8991_ADDITIONAL_CONTROL 0x37 | ||
73 | #define WM8991_ANTIPOP1 0x38 | ||
74 | #define WM8991_ANTIPOP2 0x39 | ||
75 | #define WM8991_MICBIAS 0x3A | ||
76 | #define WM8991_PLL1 0x3C | ||
77 | #define WM8991_PLL2 0x3D | ||
78 | #define WM8991_PLL3 0x3E | ||
79 | #define WM8991_INTDRIVBITS 0x3F | ||
80 | |||
81 | #define WM8991_REGISTER_COUNT 60 | ||
82 | #define WM8991_MAX_REGISTER 0x3F | ||
83 | |||
84 | /* | ||
85 | * Field Definitions. | ||
86 | */ | ||
87 | |||
88 | /* | ||
89 | * R0 (0x00) - Reset | ||
90 | */ | ||
91 | #define WM8991_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID - [15:0] */ | ||
92 | |||
93 | /* | ||
94 | * R1 (0x01) - Power Management (1) | ||
95 | */ | ||
96 | #define WM8991_SPK_ENA 0x1000 /* SPK_ENA */ | ||
97 | #define WM8991_SPK_ENA_BIT 12 | ||
98 | #define WM8991_OUT3_ENA 0x0800 /* OUT3_ENA */ | ||
99 | #define WM8991_OUT3_ENA_BIT 11 | ||
100 | #define WM8991_OUT4_ENA 0x0400 /* OUT4_ENA */ | ||
101 | #define WM8991_OUT4_ENA_BIT 10 | ||
102 | #define WM8991_LOUT_ENA 0x0200 /* LOUT_ENA */ | ||
103 | #define WM8991_LOUT_ENA_BIT 9 | ||
104 | #define WM8991_ROUT_ENA 0x0100 /* ROUT_ENA */ | ||
105 | #define WM8991_ROUT_ENA_BIT 8 | ||
106 | #define WM8991_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */ | ||
107 | #define WM8991_MICBIAS_ENA_BIT 4 | ||
108 | #define WM8991_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */ | ||
109 | #define WM8991_VREF_ENA 0x0001 /* VREF_ENA */ | ||
110 | #define WM8991_VREF_ENA_BIT 0 | ||
111 | |||
112 | /* | ||
113 | * R2 (0x02) - Power Management (2) | ||
114 | */ | ||
115 | #define WM8991_PLL_ENA 0x8000 /* PLL_ENA */ | ||
116 | #define WM8991_PLL_ENA_BIT 15 | ||
117 | #define WM8991_TSHUT_ENA 0x4000 /* TSHUT_ENA */ | ||
118 | #define WM8991_TSHUT_ENA_BIT 14 | ||
119 | #define WM8991_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ | ||
120 | #define WM8991_TSHUT_OPDIS_BIT 13 | ||
121 | #define WM8991_OPCLK_ENA 0x0800 /* OPCLK_ENA */ | ||
122 | #define WM8991_OPCLK_ENA_BIT 11 | ||
123 | #define WM8991_AINL_ENA 0x0200 /* AINL_ENA */ | ||
124 | #define WM8991_AINL_ENA_BIT 9 | ||
125 | #define WM8991_AINR_ENA 0x0100 /* AINR_ENA */ | ||
126 | #define WM8991_AINR_ENA_BIT 8 | ||
127 | #define WM8991_LIN34_ENA 0x0080 /* LIN34_ENA */ | ||
128 | #define WM8991_LIN34_ENA_BIT 7 | ||
129 | #define WM8991_LIN12_ENA 0x0040 /* LIN12_ENA */ | ||
130 | #define WM8991_LIN12_ENA_BIT 6 | ||
131 | #define WM8991_RIN34_ENA 0x0020 /* RIN34_ENA */ | ||
132 | #define WM8991_RIN34_ENA_BIT 5 | ||
133 | #define WM8991_RIN12_ENA 0x0010 /* RIN12_ENA */ | ||
134 | #define WM8991_RIN12_ENA_BIT 4 | ||
135 | #define WM8991_ADCL_ENA 0x0002 /* ADCL_ENA */ | ||
136 | #define WM8991_ADCL_ENA_BIT 1 | ||
137 | #define WM8991_ADCR_ENA 0x0001 /* ADCR_ENA */ | ||
138 | #define WM8991_ADCR_ENA_BIT 0 | ||
139 | |||
140 | /* | ||
141 | * R3 (0x03) - Power Management (3) | ||
142 | */ | ||
143 | #define WM8991_LON_ENA 0x2000 /* LON_ENA */ | ||
144 | #define WM8991_LON_ENA_BIT 13 | ||
145 | #define WM8991_LOP_ENA 0x1000 /* LOP_ENA */ | ||
146 | #define WM8991_LOP_ENA_BIT 12 | ||
147 | #define WM8991_RON_ENA 0x0800 /* RON_ENA */ | ||
148 | #define WM8991_RON_ENA_BIT 11 | ||
149 | #define WM8991_ROP_ENA 0x0400 /* ROP_ENA */ | ||
150 | #define WM8991_ROP_ENA_BIT 10 | ||
151 | #define WM8991_LOPGA_ENA 0x0080 /* LOPGA_ENA */ | ||
152 | #define WM8991_LOPGA_ENA_BIT 7 | ||
153 | #define WM8991_ROPGA_ENA 0x0040 /* ROPGA_ENA */ | ||
154 | #define WM8991_ROPGA_ENA_BIT 6 | ||
155 | #define WM8991_LOMIX_ENA 0x0020 /* LOMIX_ENA */ | ||
156 | #define WM8991_LOMIX_ENA_BIT 5 | ||
157 | #define WM8991_ROMIX_ENA 0x0010 /* ROMIX_ENA */ | ||
158 | #define WM8991_ROMIX_ENA_BIT 4 | ||
159 | #define WM8991_DACL_ENA 0x0002 /* DACL_ENA */ | ||
160 | #define WM8991_DACL_ENA_BIT 1 | ||
161 | #define WM8991_DACR_ENA 0x0001 /* DACR_ENA */ | ||
162 | #define WM8991_DACR_ENA_BIT 0 | ||
163 | |||
164 | /* | ||
165 | * R4 (0x04) - Audio Interface (1) | ||
166 | */ | ||
167 | #define WM8991_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */ | ||
168 | #define WM8991_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */ | ||
169 | #define WM8991_AIFADC_TDM 0x2000 /* AIFADC_TDM */ | ||
170 | #define WM8991_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */ | ||
171 | #define WM8991_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */ | ||
172 | #define WM8991_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */ | ||
173 | #define WM8991_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */ | ||
174 | #define WM8991_AIF_WL_16BITS (0 << 5) | ||
175 | #define WM8991_AIF_WL_20BITS (1 << 5) | ||
176 | #define WM8991_AIF_WL_24BITS (2 << 5) | ||
177 | #define WM8991_AIF_WL_32BITS (3 << 5) | ||
178 | #define WM8991_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */ | ||
179 | #define WM8991_AIF_TMF_RIGHTJ (0 << 3) | ||
180 | #define WM8991_AIF_TMF_LEFTJ (1 << 3) | ||
181 | #define WM8991_AIF_TMF_I2S (2 << 3) | ||
182 | #define WM8991_AIF_TMF_DSP (3 << 3) | ||
183 | |||
184 | /* | ||
185 | * R5 (0x05) - Audio Interface (2) | ||
186 | */ | ||
187 | #define WM8991_DACL_SRC 0x8000 /* DACL_SRC */ | ||
188 | #define WM8991_DACR_SRC 0x4000 /* DACR_SRC */ | ||
189 | #define WM8991_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ | ||
190 | #define WM8991_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ | ||
191 | #define WM8991_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */ | ||
192 | #define WM8991_DAC_COMP 0x0010 /* DAC_COMP */ | ||
193 | #define WM8991_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ | ||
194 | #define WM8991_ADC_COMP 0x0004 /* ADC_COMP */ | ||
195 | #define WM8991_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ | ||
196 | #define WM8991_LOOPBACK 0x0001 /* LOOPBACK */ | ||
197 | |||
198 | /* | ||
199 | * R6 (0x06) - Clocking (1) | ||
200 | */ | ||
201 | #define WM8991_TOCLK_RATE 0x8000 /* TOCLK_RATE */ | ||
202 | #define WM8991_TOCLK_ENA 0x4000 /* TOCLK_ENA */ | ||
203 | #define WM8991_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */ | ||
204 | #define WM8991_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ | ||
205 | #define WM8991_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */ | ||
206 | #define WM8991_BCLK_DIV_1 (0x0 << 1) | ||
207 | #define WM8991_BCLK_DIV_1_5 (0x1 << 1) | ||
208 | #define WM8991_BCLK_DIV_2 (0x2 << 1) | ||
209 | #define WM8991_BCLK_DIV_3 (0x3 << 1) | ||
210 | #define WM8991_BCLK_DIV_4 (0x4 << 1) | ||
211 | #define WM8991_BCLK_DIV_5_5 (0x5 << 1) | ||
212 | #define WM8991_BCLK_DIV_6 (0x6 << 1) | ||
213 | #define WM8991_BCLK_DIV_8 (0x7 << 1) | ||
214 | #define WM8991_BCLK_DIV_11 (0x8 << 1) | ||
215 | #define WM8991_BCLK_DIV_12 (0x9 << 1) | ||
216 | #define WM8991_BCLK_DIV_16 (0xA << 1) | ||
217 | #define WM8991_BCLK_DIV_22 (0xB << 1) | ||
218 | #define WM8991_BCLK_DIV_24 (0xC << 1) | ||
219 | #define WM8991_BCLK_DIV_32 (0xD << 1) | ||
220 | #define WM8991_BCLK_DIV_44 (0xE << 1) | ||
221 | #define WM8991_BCLK_DIV_48 (0xF << 1) | ||
222 | |||
223 | /* | ||
224 | * R7 (0x07) - Clocking (2) | ||
225 | */ | ||
226 | #define WM8991_MCLK_SRC 0x8000 /* MCLK_SRC */ | ||
227 | #define WM8991_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ | ||
228 | #define WM8991_CLK_FORCE 0x2000 /* CLK_FORCE */ | ||
229 | #define WM8991_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */ | ||
230 | #define WM8991_MCLK_DIV_1 (0 << 11) | ||
231 | #define WM8991_MCLK_DIV_2 ( 2 << 11) | ||
232 | #define WM8991_MCLK_INV 0x0400 /* MCLK_INV */ | ||
233 | #define WM8991_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */ | ||
234 | #define WM8991_ADC_CLKDIV_1 (0 << 5) | ||
235 | #define WM8991_ADC_CLKDIV_1_5 (1 << 5) | ||
236 | #define WM8991_ADC_CLKDIV_2 (2 << 5) | ||
237 | #define WM8991_ADC_CLKDIV_3 (3 << 5) | ||
238 | #define WM8991_ADC_CLKDIV_4 (4 << 5) | ||
239 | #define WM8991_ADC_CLKDIV_5_5 (5 << 5) | ||
240 | #define WM8991_ADC_CLKDIV_6 (6 << 5) | ||
241 | #define WM8991_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */ | ||
242 | #define WM8991_DAC_CLKDIV_1 (0 << 2) | ||
243 | #define WM8991_DAC_CLKDIV_1_5 (1 << 2) | ||
244 | #define WM8991_DAC_CLKDIV_2 (2 << 2) | ||
245 | #define WM8991_DAC_CLKDIV_3 (3 << 2) | ||
246 | #define WM8991_DAC_CLKDIV_4 (4 << 2) | ||
247 | #define WM8991_DAC_CLKDIV_5_5 (5 << 2) | ||
248 | #define WM8991_DAC_CLKDIV_6 (6 << 2) | ||
249 | |||
250 | /* | ||
251 | * R8 (0x08) - Audio Interface (3) | ||
252 | */ | ||
253 | #define WM8991_AIF_MSTR1 0x8000 /* AIF_MSTR1 */ | ||
254 | #define WM8991_AIF_MSTR2 0x4000 /* AIF_MSTR2 */ | ||
255 | #define WM8991_AIF_SEL 0x2000 /* AIF_SEL */ | ||
256 | #define WM8991_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */ | ||
257 | #define WM8991_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */ | ||
258 | |||
259 | /* | ||
260 | * R9 (0x09) - Audio Interface (4) | ||
261 | */ | ||
262 | #define WM8991_ALRCGPIO1 0x8000 /* ALRCGPIO1 */ | ||
263 | #define WM8991_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */ | ||
264 | #define WM8991_AIF_TRIS 0x2000 /* AIF_TRIS */ | ||
265 | #define WM8991_DACLRC_DIR 0x0800 /* DACLRC_DIR */ | ||
266 | #define WM8991_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */ | ||
267 | |||
268 | /* | ||
269 | * R10 (0x0A) - DAC CTRL | ||
270 | */ | ||
271 | #define WM8991_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */ | ||
272 | #define WM8991_DAC_MONO 0x0200 /* DAC_MONO */ | ||
273 | #define WM8991_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */ | ||
274 | #define WM8991_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */ | ||
275 | #define WM8991_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */ | ||
276 | #define WM8991_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */ | ||
277 | #define WM8991_DAC_MUTE 0x0004 /* DAC_MUTE */ | ||
278 | #define WM8991_DACL_DATINV 0x0002 /* DACL_DATINV */ | ||
279 | #define WM8991_DACR_DATINV 0x0001 /* DACR_DATINV */ | ||
280 | |||
281 | /* | ||
282 | * R11 (0x0B) - Left DAC Digital Volume | ||
283 | */ | ||
284 | #define WM8991_DAC_VU 0x0100 /* DAC_VU */ | ||
285 | #define WM8991_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ | ||
286 | #define WM8991_DACL_VOL_SHIFT 0 | ||
287 | /* | ||
288 | * R12 (0x0C) - Right DAC Digital Volume | ||
289 | */ | ||
290 | #define WM8991_DAC_VU 0x0100 /* DAC_VU */ | ||
291 | #define WM8991_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ | ||
292 | #define WM8991_DACR_VOL_SHIFT 0 | ||
293 | /* | ||
294 | * R13 (0x0D) - Digital Side Tone | ||
295 | */ | ||
296 | #define WM8991_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL - [12:9] */ | ||
297 | #define WM8991_ADCL_DAC_SVOL_SHIFT 9 | ||
298 | #define WM8991_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL - [8:5] */ | ||
299 | #define WM8991_ADCR_DAC_SVOL_SHIFT 5 | ||
300 | #define WM8991_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */ | ||
301 | #define WM8991_ADC_TO_DACL_SHIFT 2 | ||
302 | #define WM8991_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */ | ||
303 | #define WM8991_ADC_TO_DACR_SHIFT 0 | ||
304 | |||
305 | /* | ||
306 | * R14 (0x0E) - ADC CTRL | ||
307 | */ | ||
308 | #define WM8991_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */ | ||
309 | #define WM8991_ADC_HPF_ENA_BIT 8 | ||
310 | #define WM8991_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */ | ||
311 | #define WM8991_ADC_HPF_CUT_SHIFT 5 | ||
312 | #define WM8991_ADCL_DATINV 0x0002 /* ADCL_DATINV */ | ||
313 | #define WM8991_ADCL_DATINV_BIT 1 | ||
314 | #define WM8991_ADCR_DATINV 0x0001 /* ADCR_DATINV */ | ||
315 | #define WM8991_ADCR_DATINV_BIT 0 | ||
316 | |||
317 | /* | ||
318 | * R15 (0x0F) - Left ADC Digital Volume | ||
319 | */ | ||
320 | #define WM8991_ADC_VU 0x0100 /* ADC_VU */ | ||
321 | #define WM8991_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ | ||
322 | #define WM8991_ADCL_VOL_SHIFT 0 | ||
323 | |||
324 | /* | ||
325 | * R16 (0x10) - Right ADC Digital Volume | ||
326 | */ | ||
327 | #define WM8991_ADC_VU 0x0100 /* ADC_VU */ | ||
328 | #define WM8991_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ | ||
329 | #define WM8991_ADCR_VOL_SHIFT 0 | ||
330 | |||
331 | /* | ||
332 | * R18 (0x12) - GPIO CTRL 1 | ||
333 | */ | ||
334 | #define WM8991_IRQ 0x1000 /* IRQ */ | ||
335 | #define WM8991_TEMPOK 0x0800 /* TEMPOK */ | ||
336 | #define WM8991_MICSHRT 0x0400 /* MICSHRT */ | ||
337 | #define WM8991_MICDET 0x0200 /* MICDET */ | ||
338 | #define WM8991_PLL_LCK 0x0100 /* PLL_LCK */ | ||
339 | #define WM8991_GPI8_STATUS 0x0080 /* GPI8_STATUS */ | ||
340 | #define WM8991_GPI7_STATUS 0x0040 /* GPI7_STATUS */ | ||
341 | #define WM8991_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */ | ||
342 | #define WM8991_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */ | ||
343 | #define WM8991_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */ | ||
344 | #define WM8991_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */ | ||
345 | #define WM8991_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */ | ||
346 | #define WM8991_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */ | ||
347 | |||
348 | /* | ||
349 | * R19 (0x13) - GPIO1 & GPIO2 | ||
350 | */ | ||
351 | #define WM8991_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ | ||
352 | #define WM8991_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ | ||
353 | #define WM8991_GPIO2_PU 0x2000 /* GPIO2_PU */ | ||
354 | #define WM8991_GPIO2_PD 0x1000 /* GPIO2_PD */ | ||
355 | #define WM8991_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ | ||
356 | #define WM8991_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ | ||
357 | #define WM8991_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ | ||
358 | #define WM8991_GPIO1_PU 0x0020 /* GPIO1_PU */ | ||
359 | #define WM8991_GPIO1_PD 0x0010 /* GPIO1_PD */ | ||
360 | #define WM8991_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ | ||
361 | |||
362 | /* | ||
363 | * R20 (0x14) - GPIO3 & GPIO4 | ||
364 | */ | ||
365 | #define WM8991_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ | ||
366 | #define WM8991_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ | ||
367 | #define WM8991_GPIO4_PU 0x2000 /* GPIO4_PU */ | ||
368 | #define WM8991_GPIO4_PD 0x1000 /* GPIO4_PD */ | ||
369 | #define WM8991_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ | ||
370 | #define WM8991_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ | ||
371 | #define WM8991_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ | ||
372 | #define WM8991_GPIO3_PU 0x0020 /* GPIO3_PU */ | ||
373 | #define WM8991_GPIO3_PD 0x0010 /* GPIO3_PD */ | ||
374 | #define WM8991_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ | ||
375 | |||
376 | /* | ||
377 | * R21 (0x15) - GPIO5 & GPIO6 | ||
378 | */ | ||
379 | #define WM8991_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ | ||
380 | #define WM8991_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ | ||
381 | #define WM8991_GPIO6_PU 0x2000 /* GPIO6_PU */ | ||
382 | #define WM8991_GPIO6_PD 0x1000 /* GPIO6_PD */ | ||
383 | #define WM8991_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ | ||
384 | #define WM8991_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ | ||
385 | #define WM8991_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ | ||
386 | #define WM8991_GPIO5_PU 0x0020 /* GPIO5_PU */ | ||
387 | #define WM8991_GPIO5_PD 0x0010 /* GPIO5_PD */ | ||
388 | #define WM8991_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ | ||
389 | |||
390 | /* | ||
391 | * R22 (0x16) - GPIOCTRL 2 | ||
392 | */ | ||
393 | #define WM8991_RD_3W_ENA 0x8000 /* RD_3W_ENA */ | ||
394 | #define WM8991_MODE_3W4W 0x4000 /* MODE_3W4W */ | ||
395 | #define WM8991_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ | ||
396 | #define WM8991_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */ | ||
397 | #define WM8991_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */ | ||
398 | #define WM8991_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */ | ||
399 | #define WM8991_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ | ||
400 | #define WM8991_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ | ||
401 | #define WM8991_GPI8_ENA 0x0010 /* GPI8_ENA */ | ||
402 | #define WM8991_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ | ||
403 | #define WM8991_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ | ||
404 | #define WM8991_GPI7_ENA 0x0001 /* GPI7_ENA */ | ||
405 | |||
406 | /* | ||
407 | * R23 (0x17) - GPIO_POL | ||
408 | */ | ||
409 | #define WM8991_IRQ_INV 0x1000 /* IRQ_INV */ | ||
410 | #define WM8991_TEMPOK_POL 0x0800 /* TEMPOK_POL */ | ||
411 | #define WM8991_MICSHRT_POL 0x0400 /* MICSHRT_POL */ | ||
412 | #define WM8991_MICDET_POL 0x0200 /* MICDET_POL */ | ||
413 | #define WM8991_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */ | ||
414 | #define WM8991_GPI8_POL 0x0080 /* GPI8_POL */ | ||
415 | #define WM8991_GPI7_POL 0x0040 /* GPI7_POL */ | ||
416 | #define WM8991_GPIO6_POL 0x0020 /* GPIO6_POL */ | ||
417 | #define WM8991_GPIO5_POL 0x0010 /* GPIO5_POL */ | ||
418 | #define WM8991_GPIO4_POL 0x0008 /* GPIO4_POL */ | ||
419 | #define WM8991_GPIO3_POL 0x0004 /* GPIO3_POL */ | ||
420 | #define WM8991_GPIO2_POL 0x0002 /* GPIO2_POL */ | ||
421 | #define WM8991_GPIO1_POL 0x0001 /* GPIO1_POL */ | ||
422 | |||
423 | /* | ||
424 | * R24 (0x18) - Left Line Input 1&2 Volume | ||
425 | */ | ||
426 | #define WM8991_IPVU 0x0100 /* IPVU */ | ||
427 | #define WM8991_LI12MUTE 0x0080 /* LI12MUTE */ | ||
428 | #define WM8991_LI12MUTE_BIT 7 | ||
429 | #define WM8991_LI12ZC 0x0040 /* LI12ZC */ | ||
430 | #define WM8991_LI12ZC_BIT 6 | ||
431 | #define WM8991_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */ | ||
432 | #define WM8991_LIN12VOL_SHIFT 0 | ||
433 | /* | ||
434 | * R25 (0x19) - Left Line Input 3&4 Volume | ||
435 | */ | ||
436 | #define WM8991_IPVU 0x0100 /* IPVU */ | ||
437 | #define WM8991_LI34MUTE 0x0080 /* LI34MUTE */ | ||
438 | #define WM8991_LI34MUTE_BIT 7 | ||
439 | #define WM8991_LI34ZC 0x0040 /* LI34ZC */ | ||
440 | #define WM8991_LI34ZC_BIT 6 | ||
441 | #define WM8991_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */ | ||
442 | #define WM8991_LIN34VOL_SHIFT 0 | ||
443 | |||
444 | /* | ||
445 | * R26 (0x1A) - Right Line Input 1&2 Volume | ||
446 | */ | ||
447 | #define WM8991_IPVU 0x0100 /* IPVU */ | ||
448 | #define WM8991_RI12MUTE 0x0080 /* RI12MUTE */ | ||
449 | #define WM8991_RI12MUTE_BIT 7 | ||
450 | #define WM8991_RI12ZC 0x0040 /* RI12ZC */ | ||
451 | #define WM8991_RI12ZC_BIT 6 | ||
452 | #define WM8991_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */ | ||
453 | #define WM8991_RIN12VOL_SHIFT 0 | ||
454 | |||
455 | /* | ||
456 | * R27 (0x1B) - Right Line Input 3&4 Volume | ||
457 | */ | ||
458 | #define WM8991_IPVU 0x0100 /* IPVU */ | ||
459 | #define WM8991_RI34MUTE 0x0080 /* RI34MUTE */ | ||
460 | #define WM8991_RI34MUTE_BIT 7 | ||
461 | #define WM8991_RI34ZC 0x0040 /* RI34ZC */ | ||
462 | #define WM8991_RI34ZC_BIT 6 | ||
463 | #define WM8991_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */ | ||
464 | #define WM8991_RIN34VOL_SHIFT 0 | ||
465 | |||
466 | /* | ||
467 | * R28 (0x1C) - Left Output Volume | ||
468 | */ | ||
469 | #define WM8991_OPVU 0x0100 /* OPVU */ | ||
470 | #define WM8991_LOZC 0x0080 /* LOZC */ | ||
471 | #define WM8991_LOZC_BIT 7 | ||
472 | #define WM8991_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */ | ||
473 | #define WM8991_LOUTVOL_SHIFT 0 | ||
474 | /* | ||
475 | * R29 (0x1D) - Right Output Volume | ||
476 | */ | ||
477 | #define WM8991_OPVU 0x0100 /* OPVU */ | ||
478 | #define WM8991_ROZC 0x0080 /* ROZC */ | ||
479 | #define WM8991_ROZC_BIT 7 | ||
480 | #define WM8991_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */ | ||
481 | #define WM8991_ROUTVOL_SHIFT 0 | ||
482 | /* | ||
483 | * R30 (0x1E) - Line Outputs Volume | ||
484 | */ | ||
485 | #define WM8991_LONMUTE 0x0040 /* LONMUTE */ | ||
486 | #define WM8991_LONMUTE_BIT 6 | ||
487 | #define WM8991_LOPMUTE 0x0020 /* LOPMUTE */ | ||
488 | #define WM8991_LOPMUTE_BIT 5 | ||
489 | #define WM8991_LOATTN 0x0010 /* LOATTN */ | ||
490 | #define WM8991_LOATTN_BIT 4 | ||
491 | #define WM8991_RONMUTE 0x0004 /* RONMUTE */ | ||
492 | #define WM8991_RONMUTE_BIT 2 | ||
493 | #define WM8991_ROPMUTE 0x0002 /* ROPMUTE */ | ||
494 | #define WM8991_ROPMUTE_BIT 1 | ||
495 | #define WM8991_ROATTN 0x0001 /* ROATTN */ | ||
496 | #define WM8991_ROATTN_BIT 0 | ||
497 | |||
498 | /* | ||
499 | * R31 (0x1F) - Out3/4 Volume | ||
500 | */ | ||
501 | #define WM8991_OUT3MUTE 0x0020 /* OUT3MUTE */ | ||
502 | #define WM8991_OUT3MUTE_BIT 5 | ||
503 | #define WM8991_OUT3ATTN 0x0010 /* OUT3ATTN */ | ||
504 | #define WM8991_OUT3ATTN_BIT 4 | ||
505 | #define WM8991_OUT4MUTE 0x0002 /* OUT4MUTE */ | ||
506 | #define WM8991_OUT4MUTE_BIT 1 | ||
507 | #define WM8991_OUT4ATTN 0x0001 /* OUT4ATTN */ | ||
508 | #define WM8991_OUT4ATTN_BIT 0 | ||
509 | |||
510 | /* | ||
511 | * R32 (0x20) - Left OPGA Volume | ||
512 | */ | ||
513 | #define WM8991_OPVU 0x0100 /* OPVU */ | ||
514 | #define WM8991_LOPGAZC 0x0080 /* LOPGAZC */ | ||
515 | #define WM8991_LOPGAZC_BIT 7 | ||
516 | #define WM8991_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */ | ||
517 | #define WM8991_LOPGAVOL_SHIFT 0 | ||
518 | |||
519 | /* | ||
520 | * R33 (0x21) - Right OPGA Volume | ||
521 | */ | ||
522 | #define WM8991_OPVU 0x0100 /* OPVU */ | ||
523 | #define WM8991_ROPGAZC 0x0080 /* ROPGAZC */ | ||
524 | #define WM8991_ROPGAZC_BIT 7 | ||
525 | #define WM8991_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */ | ||
526 | #define WM8991_ROPGAVOL_SHIFT 0 | ||
527 | /* | ||
528 | * R34 (0x22) - Speaker Volume | ||
529 | */ | ||
530 | #define WM8991_SPKVOL_MASK 0x0003 /* SPKVOL - [1:0] */ | ||
531 | #define WM8991_SPKVOL_SHIFT 0 | ||
532 | |||
533 | /* | ||
534 | * R35 (0x23) - ClassD1 | ||
535 | */ | ||
536 | #define WM8991_CDMODE 0x0100 /* CDMODE */ | ||
537 | #define WM8991_CDMODE_BIT 8 | ||
538 | |||
539 | /* | ||
540 | * R37 (0x25) - ClassD3 | ||
541 | */ | ||
542 | #define WM8991_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */ | ||
543 | #define WM8991_DCGAIN_SHIFT 3 | ||
544 | #define WM8991_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */ | ||
545 | #define WM8991_ACGAIN_SHIFT 0 | ||
546 | /* | ||
547 | * R39 (0x27) - Input Mixer1 | ||
548 | */ | ||
549 | #define WM8991_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */ | ||
550 | #define WM8991_AINLMODE_SHIFT 2 | ||
551 | #define WM8991_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */ | ||
552 | #define WM8991_AINRMODE_SHIFT 0 | ||
553 | |||
554 | /* | ||
555 | * R40 (0x28) - Input Mixer2 | ||
556 | */ | ||
557 | #define WM8991_LMP4 0x0080 /* LMP4 */ | ||
558 | #define WM8991_LMP4_BIT 7 /* LMP4 */ | ||
559 | #define WM8991_LMN3 0x0040 /* LMN3 */ | ||
560 | #define WM8991_LMN3_BIT 6 /* LMN3 */ | ||
561 | #define WM8991_LMP2 0x0020 /* LMP2 */ | ||
562 | #define WM8991_LMP2_BIT 5 /* LMP2 */ | ||
563 | #define WM8991_LMN1 0x0010 /* LMN1 */ | ||
564 | #define WM8991_LMN1_BIT 4 /* LMN1 */ | ||
565 | #define WM8991_RMP4 0x0008 /* RMP4 */ | ||
566 | #define WM8991_RMP4_BIT 3 /* RMP4 */ | ||
567 | #define WM8991_RMN3 0x0004 /* RMN3 */ | ||
568 | #define WM8991_RMN3_BIT 2 /* RMN3 */ | ||
569 | #define WM8991_RMP2 0x0002 /* RMP2 */ | ||
570 | #define WM8991_RMP2_BIT 1 /* RMP2 */ | ||
571 | #define WM8991_RMN1 0x0001 /* RMN1 */ | ||
572 | #define WM8991_RMN1_BIT 0 /* RMN1 */ | ||
573 | |||
574 | /* | ||
575 | * R41 (0x29) - Input Mixer3 | ||
576 | */ | ||
577 | #define WM8991_L34MNB 0x0100 /* L34MNB */ | ||
578 | #define WM8991_L34MNB_BIT 8 | ||
579 | #define WM8991_L34MNBST 0x0080 /* L34MNBST */ | ||
580 | #define WM8991_L34MNBST_BIT 7 | ||
581 | #define WM8991_L12MNB 0x0020 /* L12MNB */ | ||
582 | #define WM8991_L12MNB_BIT 5 | ||
583 | #define WM8991_L12MNBST 0x0010 /* L12MNBST */ | ||
584 | #define WM8991_L12MNBST_BIT 4 | ||
585 | #define WM8991_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */ | ||
586 | #define WM8991_LDBVOL_SHIFT 0 | ||
587 | |||
588 | /* | ||
589 | * R42 (0x2A) - Input Mixer4 | ||
590 | */ | ||
591 | #define WM8991_R34MNB 0x0100 /* R34MNB */ | ||
592 | #define WM8991_R34MNB_BIT 8 | ||
593 | #define WM8991_R34MNBST 0x0080 /* R34MNBST */ | ||
594 | #define WM8991_R34MNBST_BIT 7 | ||
595 | #define WM8991_R12MNB 0x0020 /* R12MNB */ | ||
596 | #define WM8991_R12MNB_BIT 5 | ||
597 | #define WM8991_R12MNBST 0x0010 /* R12MNBST */ | ||
598 | #define WM8991_R12MNBST_BIT 4 | ||
599 | #define WM8991_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */ | ||
600 | #define WM8991_RDBVOL_SHIFT 0 | ||
601 | |||
602 | /* | ||
603 | * R43 (0x2B) - Input Mixer5 | ||
604 | */ | ||
605 | #define WM8991_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */ | ||
606 | #define WM8991_LI2BVOL_SHIFT 6 | ||
607 | #define WM8991_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */ | ||
608 | #define WM8991_LR4BVOL_SHIFT 3 | ||
609 | #define WM8991_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */ | ||
610 | #define WM8991_LL4BVOL_SHIFT 0 | ||
611 | |||
612 | /* | ||
613 | * R44 (0x2C) - Input Mixer6 | ||
614 | */ | ||
615 | #define WM8991_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */ | ||
616 | #define WM8991_RI2BVOL_SHIFT 6 | ||
617 | #define WM8991_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */ | ||
618 | #define WM8991_RL4BVOL_SHIFT 3 | ||
619 | #define WM8991_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */ | ||
620 | #define WM8991_RR4BVOL_SHIFT 0 | ||
621 | |||
622 | /* | ||
623 | * R45 (0x2D) - Output Mixer1 | ||
624 | */ | ||
625 | #define WM8991_LRBLO 0x0080 /* LRBLO */ | ||
626 | #define WM8991_LRBLO_BIT 7 | ||
627 | #define WM8991_LLBLO 0x0040 /* LLBLO */ | ||
628 | #define WM8991_LLBLO_BIT 6 | ||
629 | #define WM8991_LRI3LO 0x0020 /* LRI3LO */ | ||
630 | #define WM8991_LRI3LO_BIT 5 | ||
631 | #define WM8991_LLI3LO 0x0010 /* LLI3LO */ | ||
632 | #define WM8991_LLI3LO_BIT 4 | ||
633 | #define WM8991_LR12LO 0x0008 /* LR12LO */ | ||
634 | #define WM8991_LR12LO_BIT 3 | ||
635 | #define WM8991_LL12LO 0x0004 /* LL12LO */ | ||
636 | #define WM8991_LL12LO_BIT 2 | ||
637 | #define WM8991_LDLO 0x0001 /* LDLO */ | ||
638 | #define WM8991_LDLO_BIT 0 | ||
639 | |||
640 | /* | ||
641 | * R46 (0x2E) - Output Mixer2 | ||
642 | */ | ||
643 | #define WM8991_RLBRO 0x0080 /* RLBRO */ | ||
644 | #define WM8991_RLBRO_BIT 7 | ||
645 | #define WM8991_RRBRO 0x0040 /* RRBRO */ | ||
646 | #define WM8991_RRBRO_BIT 6 | ||
647 | #define WM8991_RLI3RO 0x0020 /* RLI3RO */ | ||
648 | #define WM8991_RLI3RO_BIT 5 | ||
649 | #define WM8991_RRI3RO 0x0010 /* RRI3RO */ | ||
650 | #define WM8991_RRI3RO_BIT 4 | ||
651 | #define WM8991_RL12RO 0x0008 /* RL12RO */ | ||
652 | #define WM8991_RL12RO_BIT 3 | ||
653 | #define WM8991_RR12RO 0x0004 /* RR12RO */ | ||
654 | #define WM8991_RR12RO_BIT 2 | ||
655 | #define WM8991_RDRO 0x0001 /* RDRO */ | ||
656 | #define WM8991_RDRO_BIT 0 | ||
657 | |||
658 | /* | ||
659 | * R47 (0x2F) - Output Mixer3 | ||
660 | */ | ||
661 | #define WM8991_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */ | ||
662 | #define WM8991_LLI3LOVOL_SHIFT 6 | ||
663 | #define WM8991_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */ | ||
664 | #define WM8991_LR12LOVOL_SHIFT 3 | ||
665 | #define WM8991_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */ | ||
666 | #define WM8991_LL12LOVOL_SHIFT 0 | ||
667 | |||
668 | /* | ||
669 | * R48 (0x30) - Output Mixer4 | ||
670 | */ | ||
671 | #define WM8991_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */ | ||
672 | #define WM8991_RRI3ROVOL_SHIFT 6 | ||
673 | #define WM8991_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */ | ||
674 | #define WM8991_RL12ROVOL_SHIFT 3 | ||
675 | #define WM8991_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */ | ||
676 | #define WM8991_RR12ROVOL_SHIFT 0 | ||
677 | |||
678 | /* | ||
679 | * R49 (0x31) - Output Mixer5 | ||
680 | */ | ||
681 | #define WM8991_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */ | ||
682 | #define WM8991_LRI3LOVOL_SHIFT 6 | ||
683 | #define WM8991_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */ | ||
684 | #define WM8991_LRBLOVOL_SHIFT 3 | ||
685 | #define WM8991_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */ | ||
686 | #define WM8991_LLBLOVOL_SHIFT 0 | ||
687 | |||
688 | /* | ||
689 | * R50 (0x32) - Output Mixer6 | ||
690 | */ | ||
691 | #define WM8991_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */ | ||
692 | #define WM8991_RLI3ROVOL_SHIFT 6 | ||
693 | #define WM8991_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */ | ||
694 | #define WM8991_RLBROVOL_SHIFT 3 | ||
695 | #define WM8991_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */ | ||
696 | #define WM8991_RRBROVOL_SHIFT 0 | ||
697 | |||
698 | /* | ||
699 | * R51 (0x33) - Out3/4 Mixer | ||
700 | */ | ||
701 | #define WM8991_VSEL_MASK 0x0180 /* VSEL - [8:7] */ | ||
702 | #define WM8991_LI4O3 0x0020 /* LI4O3 */ | ||
703 | #define WM8991_LI4O3_BIT 5 | ||
704 | #define WM8991_LPGAO3 0x0010 /* LPGAO3 */ | ||
705 | #define WM8991_LPGAO3_BIT 4 | ||
706 | #define WM8991_RI4O4 0x0002 /* RI4O4 */ | ||
707 | #define WM8991_RI4O4_BIT 1 | ||
708 | #define WM8991_RPGAO4 0x0001 /* RPGAO4 */ | ||
709 | #define WM8991_RPGAO4_BIT 0 | ||
710 | /* | ||
711 | * R52 (0x34) - Line Mixer1 | ||
712 | */ | ||
713 | #define WM8991_LLOPGALON 0x0040 /* LLOPGALON */ | ||
714 | #define WM8991_LLOPGALON_BIT 6 | ||
715 | #define WM8991_LROPGALON 0x0020 /* LROPGALON */ | ||
716 | #define WM8991_LROPGALON_BIT 5 | ||
717 | #define WM8991_LOPLON 0x0010 /* LOPLON */ | ||
718 | #define WM8991_LOPLON_BIT 4 | ||
719 | #define WM8991_LR12LOP 0x0004 /* LR12LOP */ | ||
720 | #define WM8991_LR12LOP_BIT 2 | ||
721 | #define WM8991_LL12LOP 0x0002 /* LL12LOP */ | ||
722 | #define WM8991_LL12LOP_BIT 1 | ||
723 | #define WM8991_LLOPGALOP 0x0001 /* LLOPGALOP */ | ||
724 | #define WM8991_LLOPGALOP_BIT 0 | ||
725 | /* | ||
726 | * R53 (0x35) - Line Mixer2 | ||
727 | */ | ||
728 | #define WM8991_RROPGARON 0x0040 /* RROPGARON */ | ||
729 | #define WM8991_RROPGARON_BIT 6 | ||
730 | #define WM8991_RLOPGARON 0x0020 /* RLOPGARON */ | ||
731 | #define WM8991_RLOPGARON_BIT 5 | ||
732 | #define WM8991_ROPRON 0x0010 /* ROPRON */ | ||
733 | #define WM8991_ROPRON_BIT 4 | ||
734 | #define WM8991_RL12ROP 0x0004 /* RL12ROP */ | ||
735 | #define WM8991_RL12ROP_BIT 2 | ||
736 | #define WM8991_RR12ROP 0x0002 /* RR12ROP */ | ||
737 | #define WM8991_RR12ROP_BIT 1 | ||
738 | #define WM8991_RROPGAROP 0x0001 /* RROPGAROP */ | ||
739 | #define WM8991_RROPGAROP_BIT 0 | ||
740 | |||
741 | /* | ||
742 | * R54 (0x36) - Speaker Mixer | ||
743 | */ | ||
744 | #define WM8991_LB2SPK 0x0080 /* LB2SPK */ | ||
745 | #define WM8991_LB2SPK_BIT 7 | ||
746 | #define WM8991_RB2SPK 0x0040 /* RB2SPK */ | ||
747 | #define WM8991_RB2SPK_BIT 6 | ||
748 | #define WM8991_LI2SPK 0x0020 /* LI2SPK */ | ||
749 | #define WM8991_LI2SPK_BIT 5 | ||
750 | #define WM8991_RI2SPK 0x0010 /* RI2SPK */ | ||
751 | #define WM8991_RI2SPK_BIT 4 | ||
752 | #define WM8991_LOPGASPK 0x0008 /* LOPGASPK */ | ||
753 | #define WM8991_LOPGASPK_BIT 3 | ||
754 | #define WM8991_ROPGASPK 0x0004 /* ROPGASPK */ | ||
755 | #define WM8991_ROPGASPK_BIT 2 | ||
756 | #define WM8991_LDSPK 0x0002 /* LDSPK */ | ||
757 | #define WM8991_LDSPK_BIT 1 | ||
758 | #define WM8991_RDSPK 0x0001 /* RDSPK */ | ||
759 | #define WM8991_RDSPK_BIT 0 | ||
760 | |||
761 | /* | ||
762 | * R55 (0x37) - Additional Control | ||
763 | */ | ||
764 | #define WM8991_VROI 0x0001 /* VROI */ | ||
765 | |||
766 | /* | ||
767 | * R56 (0x38) - AntiPOP1 | ||
768 | */ | ||
769 | #define WM8991_DIS_LLINE 0x0020 /* DIS_LLINE */ | ||
770 | #define WM8991_DIS_RLINE 0x0010 /* DIS_RLINE */ | ||
771 | #define WM8991_DIS_OUT3 0x0008 /* DIS_OUT3 */ | ||
772 | #define WM8991_DIS_OUT4 0x0004 /* DIS_OUT4 */ | ||
773 | #define WM8991_DIS_LOUT 0x0002 /* DIS_LOUT */ | ||
774 | #define WM8991_DIS_ROUT 0x0001 /* DIS_ROUT */ | ||
775 | |||
776 | /* | ||
777 | * R57 (0x39) - AntiPOP2 | ||
778 | */ | ||
779 | #define WM8991_SOFTST 0x0040 /* SOFTST */ | ||
780 | #define WM8991_BUFIOEN 0x0008 /* BUFIOEN */ | ||
781 | #define WM8991_BUFDCOPEN 0x0004 /* BUFDCOPEN */ | ||
782 | #define WM8991_POBCTRL 0x0002 /* POBCTRL */ | ||
783 | #define WM8991_VMIDTOG 0x0001 /* VMIDTOG */ | ||
784 | |||
785 | /* | ||
786 | * R58 (0x3A) - MICBIAS | ||
787 | */ | ||
788 | #define WM8991_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */ | ||
789 | #define WM8991_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */ | ||
790 | #define WM8991_MCD 0x0004 /* MCD */ | ||
791 | #define WM8991_MBSEL 0x0001 /* MBSEL */ | ||
792 | |||
793 | /* | ||
794 | * R60 (0x3C) - PLL1 | ||
795 | */ | ||
796 | #define WM8991_SDM 0x0080 /* SDM */ | ||
797 | #define WM8991_PRESCALE 0x0040 /* PRESCALE */ | ||
798 | #define WM8991_PLLN_MASK 0x000F /* PLLN - [3:0] */ | ||
799 | |||
800 | /* | ||
801 | * R61 (0x3D) - PLL2 | ||
802 | */ | ||
803 | #define WM8991_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */ | ||
804 | |||
805 | /* | ||
806 | * R62 (0x3E) - PLL3 | ||
807 | */ | ||
808 | #define WM8991_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */ | ||
809 | |||
810 | /* | ||
811 | * R63 (0x3F) - Internal Driver Bits | ||
812 | */ | ||
813 | #define WM8991_INMIXL_PWR_BIT 0 | ||
814 | #define WM8991_AINLMUX_PWR_BIT 1 | ||
815 | #define WM8991_INMIXR_PWR_BIT 2 | ||
816 | #define WM8991_AINRMUX_PWR_BIT 3 | ||
817 | |||
818 | #define WM8991_MCLK_DIV 0 | ||
819 | #define WM8991_DACCLK_DIV 1 | ||
820 | #define WM8991_ADCCLK_DIV 2 | ||
821 | #define WM8991_BCLK_DIV 3 | ||
822 | |||
823 | #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ | ||
824 | tlv_array) \ | ||
825 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ | ||
826 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | ||
827 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | ||
828 | .tlv.p = (tlv_array), \ | ||
829 | .info = snd_soc_info_volsw, \ | ||
830 | .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ | ||
831 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | ||
832 | |||
833 | #endif /* _WM8991_H */ | ||