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path: root/sound/soc/codecs/tlv320aic32x4.c
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Diffstat (limited to 'sound/soc/codecs/tlv320aic32x4.c')
-rw-r--r--sound/soc/codecs/tlv320aic32x4.c110
1 files changed, 51 insertions, 59 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c
index eb401ef021fb..372b0b83bd9f 100644
--- a/sound/soc/codecs/tlv320aic32x4.c
+++ b/sound/soc/codecs/tlv320aic32x4.c
@@ -60,7 +60,6 @@ struct aic32x4_rate_divs {
60 60
61struct aic32x4_priv { 61struct aic32x4_priv {
62 u32 sysclk; 62 u32 sysclk;
63 s32 master;
64 u8 page_no; 63 u8 page_no;
65 void *control_data; 64 void *control_data;
66 u32 power_cfg; 65 u32 power_cfg;
@@ -369,7 +368,6 @@ static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
369static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 368static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
370{ 369{
371 struct snd_soc_codec *codec = codec_dai->codec; 370 struct snd_soc_codec *codec = codec_dai->codec;
372 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
373 u8 iface_reg_1; 371 u8 iface_reg_1;
374 u8 iface_reg_2; 372 u8 iface_reg_2;
375 u8 iface_reg_3; 373 u8 iface_reg_3;
@@ -384,11 +382,9 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
384 /* set master/slave audio interface */ 382 /* set master/slave audio interface */
385 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 383 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
386 case SND_SOC_DAIFMT_CBM_CFM: 384 case SND_SOC_DAIFMT_CBM_CFM:
387 aic32x4->master = 1;
388 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 385 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
389 break; 386 break;
390 case SND_SOC_DAIFMT_CBS_CFS: 387 case SND_SOC_DAIFMT_CBS_CFS:
391 aic32x4->master = 0;
392 break; 388 break;
393 default: 389 default:
394 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 390 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
@@ -526,64 +522,58 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
526static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 522static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
527 enum snd_soc_bias_level level) 523 enum snd_soc_bias_level level)
528{ 524{
529 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
530
531 switch (level) { 525 switch (level) {
532 case SND_SOC_BIAS_ON: 526 case SND_SOC_BIAS_ON:
533 if (aic32x4->master) { 527 /* Switch on PLL */
534 /* Switch on PLL */ 528 snd_soc_update_bits(codec, AIC32X4_PLLPR,
535 snd_soc_update_bits(codec, AIC32X4_PLLPR, 529 AIC32X4_PLLEN, AIC32X4_PLLEN);
536 AIC32X4_PLLEN, AIC32X4_PLLEN); 530
537 531 /* Switch on NDAC Divider */
538 /* Switch on NDAC Divider */ 532 snd_soc_update_bits(codec, AIC32X4_NDAC,
539 snd_soc_update_bits(codec, AIC32X4_NDAC, 533 AIC32X4_NDACEN, AIC32X4_NDACEN);
540 AIC32X4_NDACEN, AIC32X4_NDACEN); 534
541 535 /* Switch on MDAC Divider */
542 /* Switch on MDAC Divider */ 536 snd_soc_update_bits(codec, AIC32X4_MDAC,
543 snd_soc_update_bits(codec, AIC32X4_MDAC, 537 AIC32X4_MDACEN, AIC32X4_MDACEN);
544 AIC32X4_MDACEN, AIC32X4_MDACEN); 538
545 539 /* Switch on NADC Divider */
546 /* Switch on NADC Divider */ 540 snd_soc_update_bits(codec, AIC32X4_NADC,
547 snd_soc_update_bits(codec, AIC32X4_NADC, 541 AIC32X4_NADCEN, AIC32X4_NADCEN);
548 AIC32X4_NADCEN, AIC32X4_NADCEN); 542
549 543 /* Switch on MADC Divider */
550 /* Switch on MADC Divider */ 544 snd_soc_update_bits(codec, AIC32X4_MADC,
551 snd_soc_update_bits(codec, AIC32X4_MADC, 545 AIC32X4_MADCEN, AIC32X4_MADCEN);
552 AIC32X4_MADCEN, AIC32X4_MADCEN); 546
553 547 /* Switch on BCLK_N Divider */
554 /* Switch on BCLK_N Divider */ 548 snd_soc_update_bits(codec, AIC32X4_BCLKN,
555 snd_soc_update_bits(codec, AIC32X4_BCLKN, 549 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
556 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
557 }
558 break; 550 break;
559 case SND_SOC_BIAS_PREPARE: 551 case SND_SOC_BIAS_PREPARE:
560 break; 552 break;
561 case SND_SOC_BIAS_STANDBY: 553 case SND_SOC_BIAS_STANDBY:
562 if (aic32x4->master) { 554 /* Switch off PLL */
563 /* Switch off PLL */ 555 snd_soc_update_bits(codec, AIC32X4_PLLPR,
564 snd_soc_update_bits(codec, AIC32X4_PLLPR, 556 AIC32X4_PLLEN, 0);
565 AIC32X4_PLLEN, 0); 557
566 558 /* Switch off NDAC Divider */
567 /* Switch off NDAC Divider */ 559 snd_soc_update_bits(codec, AIC32X4_NDAC,
568 snd_soc_update_bits(codec, AIC32X4_NDAC, 560 AIC32X4_NDACEN, 0);
569 AIC32X4_NDACEN, 0); 561
570 562 /* Switch off MDAC Divider */
571 /* Switch off MDAC Divider */ 563 snd_soc_update_bits(codec, AIC32X4_MDAC,
572 snd_soc_update_bits(codec, AIC32X4_MDAC, 564 AIC32X4_MDACEN, 0);
573 AIC32X4_MDACEN, 0); 565
574 566 /* Switch off NADC Divider */
575 /* Switch off NADC Divider */ 567 snd_soc_update_bits(codec, AIC32X4_NADC,
576 snd_soc_update_bits(codec, AIC32X4_NADC, 568 AIC32X4_NADCEN, 0);
577 AIC32X4_NADCEN, 0); 569
578 570 /* Switch off MADC Divider */
579 /* Switch off MADC Divider */ 571 snd_soc_update_bits(codec, AIC32X4_MADC,
580 snd_soc_update_bits(codec, AIC32X4_MADC, 572 AIC32X4_MADCEN, 0);
581 AIC32X4_MADCEN, 0); 573
582 574 /* Switch off BCLK_N Divider */
583 /* Switch off BCLK_N Divider */ 575 snd_soc_update_bits(codec, AIC32X4_BCLKN,
584 snd_soc_update_bits(codec, AIC32X4_BCLKN, 576 AIC32X4_BCLKEN, 0);
585 AIC32X4_BCLKEN, 0);
586 }
587 break; 577 break;
588 case SND_SOC_BIAS_OFF: 578 case SND_SOC_BIAS_OFF:
589 break; 579 break;
@@ -651,9 +641,11 @@ static int aic32x4_probe(struct snd_soc_codec *codec)
651 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) { 641 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
652 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 642 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
653 } 643 }
654 if (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) { 644
655 snd_soc_write(codec, AIC32X4_LDOCTL, AIC32X4_LDOCTLEN); 645 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
656 } 646 AIC32X4_LDOCTLEN : 0;
647 snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
648
657 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 649 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
658 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) { 650 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
659 tmp_reg |= AIC32X4_LDOIN_18_36; 651 tmp_reg |= AIC32X4_LDOIN_18_36;