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-rw-r--r--sound/soc/codecs/rt5677.c1198
1 files changed, 1131 insertions, 67 deletions
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 16aa4d99a713..81fe1464d268 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -20,6 +20,7 @@
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/firmware.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <sound/core.h> 25#include <sound/core.h>
25#include <sound/pcm.h> 26#include <sound/pcm.h>
@@ -31,6 +32,7 @@
31 32
32#include "rl6231.h" 33#include "rl6231.h"
33#include "rt5677.h" 34#include "rt5677.h"
35#include "rt5677-spi.h"
34 36
35#define RT5677_DEVICE_ID 0x6327 37#define RT5677_DEVICE_ID 0x6327
36 38
@@ -53,12 +55,13 @@ static const struct regmap_range_cfg rt5677_ranges[] = {
53}; 55};
54 56
55static const struct reg_default init_list[] = { 57static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
56 {RT5677_PR_BASE + 0x3d, 0x364d}, 59 {RT5677_PR_BASE + 0x3d, 0x364d},
57 {RT5677_PR_BASE + 0x17, 0x4fc0}, 60 {RT5677_PR_BASE + 0x17, 0x4fc0},
58 {RT5677_PR_BASE + 0x13, 0x0312}, 61 {RT5677_PR_BASE + 0x13, 0x0312},
59 {RT5677_PR_BASE + 0x1e, 0x0000}, 62 {RT5677_PR_BASE + 0x1e, 0x0000},
60 {RT5677_PR_BASE + 0x12, 0x0eaa}, 63 {RT5677_PR_BASE + 0x12, 0x0eaa},
61 {RT5677_PR_BASE + 0x14, 0x018a}, 64 {RT5677_PR_BASE + 0x14, 0x018a},
62}; 65};
63#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 66#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
64 67
@@ -171,7 +174,7 @@ static const struct reg_default rt5677_reg[] = {
171 {RT5677_ASRC_9 , 0x0000}, 174 {RT5677_ASRC_9 , 0x0000},
172 {RT5677_ASRC_10 , 0x0000}, 175 {RT5677_ASRC_10 , 0x0000},
173 {RT5677_ASRC_11 , 0x0000}, 176 {RT5677_ASRC_11 , 0x0000},
174 {RT5677_ASRC_12 , 0x0008}, 177 {RT5677_ASRC_12 , 0x0018},
175 {RT5677_ASRC_13 , 0x0000}, 178 {RT5677_ASRC_13 , 0x0000},
176 {RT5677_ASRC_14 , 0x0000}, 179 {RT5677_ASRC_14 , 0x0000},
177 {RT5677_ASRC_15 , 0x0000}, 180 {RT5677_ASRC_15 , 0x0000},
@@ -537,10 +540,232 @@ static bool rt5677_readable_register(struct device *dev, unsigned int reg)
537 } 540 }
538} 541}
539 542
543/**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
552static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
554{
555 struct snd_soc_codec *codec = rt5677->codec;
556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599}
600
601/**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
606 *
607 *
608 * Returns 0 for success or negative error code.
609 */
610static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
612{
613 struct snd_soc_codec *codec = rt5677->codec;
614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
643
644err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648}
649
650/**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
659static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
661{
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
663 value, 0x0001);
664}
665
666/**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
671 *
672 *
673 * Returns 0 for success or negative error code.
674 */
675static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
677{
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
680
681 *value &= 0xffff;
682
683 return ret;
684}
685
686static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
687{
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
689
690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
696 }
697}
698
699static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700{
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
705 if (on && !activity) {
706 activity = true;
707
708 regcache_cache_only(rt5677->regmap, false);
709 regcache_cache_bypass(rt5677->regmap, true);
710
711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
712 regmap_update_bits(rt5677->regmap,
713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
715 RT5677_LDO1_SEL_MASK, 0x0);
716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
717 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
725 rt5677_set_dsp_mode(codec, true);
726
727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
728 codec->dev);
729 if (ret == 0) {
730 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
731 release_firmware(rt5677->fw1);
732 }
733
734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
735 codec->dev);
736 if (ret == 0) {
737 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
738 release_firmware(rt5677->fw2);
739 }
740
741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
742
743 regcache_cache_bypass(rt5677->regmap, false);
744 regcache_cache_only(rt5677->regmap, true);
745 } else if (!on && activity) {
746 activity = false;
747
748 regcache_cache_only(rt5677->regmap, false);
749 regcache_cache_bypass(rt5677->regmap, true);
750
751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
752 rt5677_set_dsp_mode(codec, false);
753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
754
755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
756
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_mark_dirty(rt5677->regmap);
759 regcache_sync(rt5677->regmap);
760 }
761
762 return 0;
763}
764
540static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 765static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
541static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 766static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
542static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 767static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
543static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 768static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
544static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 769static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
545static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 770static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
546 771
@@ -556,6 +781,31 @@ static unsigned int bst_tlv[] = {
556 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), 781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
557}; 782};
558 783
784static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
786{
787 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
788 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
789
790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
791
792 return 0;
793}
794
795static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
796 struct snd_ctl_elem_value *ucontrol)
797{
798 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
799 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
800
801 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
802
803 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
804 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
805
806 return 0;
807}
808
559static const struct snd_kcontrol_new rt5677_snd_controls[] = { 809static const struct snd_kcontrol_new rt5677_snd_controls[] = {
560 /* OUTPUT Control */ 810 /* OUTPUT Control */
561 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 811 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
@@ -567,13 +817,13 @@ static const struct snd_kcontrol_new rt5677_snd_controls[] = {
567 817
568 /* DAC Digital Volume */ 818 /* DAC Digital Volume */
569 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 819 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
570 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), 820 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
571 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 821 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
572 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), 822 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
573 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 823 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
574 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), 824 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
575 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 825 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
576 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), 826 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
577 827
578 /* IN1/IN2 Control */ 828 /* IN1/IN2 Control */
579 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 829 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
@@ -592,19 +842,19 @@ static const struct snd_kcontrol_new rt5677_snd_controls[] = {
592 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 842 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
593 843
594 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 844 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
595 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, 845 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
596 adc_vol_tlv), 846 adc_vol_tlv),
597 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 847 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
598 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, 848 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
599 adc_vol_tlv), 849 adc_vol_tlv),
600 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 850 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
601 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, 851 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
602 adc_vol_tlv), 852 adc_vol_tlv),
603 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 853 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
604 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, 854 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
605 adc_vol_tlv), 855 adc_vol_tlv),
606 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 856 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
607 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0, 857 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
608 adc_vol_tlv), 858 adc_vol_tlv),
609 859
610 /* Sidetone Control */ 860 /* Sidetone Control */
@@ -627,6 +877,9 @@ static const struct snd_kcontrol_new rt5677_snd_controls[] = {
627 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 877 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
628 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 878 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
629 adc_bst_tlv), 879 adc_bst_tlv),
880
881 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
882 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
630}; 883};
631 884
632/** 885/**
@@ -1086,7 +1339,7 @@ static SOC_ENUM_SINGLE_DECL(
1086static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1339static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1087 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1340 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1088 1341
1089/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1342/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1090static const char * const rt5677_stereo_adc2_src[] = { 1343static const char * const rt5677_stereo_adc2_src[] = {
1091 "DD MIX1", "DMIC", "Stereo DAC MIX" 1344 "DD MIX1", "DMIC", "Stereo DAC MIX"
1092}; 1345};
@@ -1171,7 +1424,7 @@ static SOC_ENUM_SINGLE_DECL(
1171static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1424static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1172 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1425 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1173 1426
1174/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1427/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1175static const char * const rt5677_stereo_adc1_src[] = { 1428static const char * const rt5677_stereo_adc1_src[] = {
1176 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1429 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1177}; 1430};
@@ -1443,7 +1696,7 @@ static SOC_ENUM_SINGLE_DECL(
1443static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 1696static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1444 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 1697 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1445 1698
1446/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/ 1699/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1447static const char * const rt5677_if12_adc1_src[] = { 1700static const char * const rt5677_if12_adc1_src[] = {
1448 "STO1 ADC MIX", "OB01", "VAD ADC" 1701 "STO1 ADC MIX", "OB01", "VAD ADC"
1449}; 1702};
@@ -1521,7 +1774,7 @@ static SOC_ENUM_SINGLE_DECL(
1521static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 1774static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1522 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 1775 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1523 1776
1524/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 1777/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1525static const char * const rt5677_if12_adc4_src[] = { 1778static const char * const rt5677_if12_adc4_src[] = {
1526 "STO4 ADC MIX", "OB67", "OB01" 1779 "STO4 ADC MIX", "OB67", "OB01"
1527}; 1780};
@@ -1547,7 +1800,7 @@ static SOC_ENUM_SINGLE_DECL(
1547static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 1800static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1548 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 1801 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1549 1802
1550/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/ 1803/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1551static const char * const rt5677_if34_adc_src[] = { 1804static const char * const rt5677_if34_adc_src[] = {
1552 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 1805 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1553 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 1806 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
@@ -1567,6 +1820,213 @@ static SOC_ENUM_SINGLE_DECL(
1567static const struct snd_kcontrol_new rt5677_if4_adc_mux = 1820static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1568 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 1821 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1569 1822
1823/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1824static const char * const rt5677_if12_adc_swap_src[] = {
1825 "L/R", "R/L", "L/L", "R/R"
1826};
1827
1828static SOC_ENUM_SINGLE_DECL(
1829 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1830 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1831
1832static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1833 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1834
1835static SOC_ENUM_SINGLE_DECL(
1836 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1837 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1838
1839static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1840 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1841
1842static SOC_ENUM_SINGLE_DECL(
1843 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1844 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1845
1846static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1847 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1848
1849static SOC_ENUM_SINGLE_DECL(
1850 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1851 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1852
1853static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1854 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1855
1856static SOC_ENUM_SINGLE_DECL(
1857 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1858 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1859
1860static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1861 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1862
1863static SOC_ENUM_SINGLE_DECL(
1864 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1865 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1866
1867static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1868 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1869
1870static SOC_ENUM_SINGLE_DECL(
1871 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1872 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1873
1874static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1875 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1876
1877static SOC_ENUM_SINGLE_DECL(
1878 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1879 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1880
1881static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1882 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1883
1884/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1885static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1886 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1887 "3/1/2/4", "3/4/1/2"
1888};
1889
1890static SOC_ENUM_SINGLE_DECL(
1891 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1892 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1893
1894static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1895 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1896
1897/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1898static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1899 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1900 "2/3/1/4", "3/4/1/2"
1901};
1902
1903static SOC_ENUM_SINGLE_DECL(
1904 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1905 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1906
1907static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
1908 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
1909
1910/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
1911 MX-3F[14:12][10:8][6:4][2:0]
1912 MX-43[14:12][10:8][6:4][2:0]
1913 MX-44[14:12][10:8][6:4][2:0] */
1914static const char * const rt5677_if12_dac_tdm_sel_src[] = {
1915 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
1916};
1917
1918static SOC_ENUM_SINGLE_DECL(
1919 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
1920 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
1921
1922static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
1923 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
1924
1925static SOC_ENUM_SINGLE_DECL(
1926 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
1927 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
1928
1929static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
1930 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
1931
1932static SOC_ENUM_SINGLE_DECL(
1933 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
1934 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
1935
1936static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
1937 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
1938
1939static SOC_ENUM_SINGLE_DECL(
1940 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
1941 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
1942
1943static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
1944 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
1945
1946static SOC_ENUM_SINGLE_DECL(
1947 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
1948 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
1949
1950static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
1951 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
1952
1953static SOC_ENUM_SINGLE_DECL(
1954 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
1955 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
1956
1957static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
1958 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
1959
1960static SOC_ENUM_SINGLE_DECL(
1961 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
1962 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
1963
1964static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
1965 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
1966
1967static SOC_ENUM_SINGLE_DECL(
1968 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
1969 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
1970
1971static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
1972 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
1973
1974static SOC_ENUM_SINGLE_DECL(
1975 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
1976 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
1977
1978static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
1979 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
1980
1981static SOC_ENUM_SINGLE_DECL(
1982 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
1983 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
1984
1985static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
1986 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
1987
1988static SOC_ENUM_SINGLE_DECL(
1989 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
1990 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
1991
1992static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
1993 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
1994
1995static SOC_ENUM_SINGLE_DECL(
1996 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
1997 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
1998
1999static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2000 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2001
2002static SOC_ENUM_SINGLE_DECL(
2003 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2004 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2005
2006static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2007 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2008
2009static SOC_ENUM_SINGLE_DECL(
2010 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2011 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2012
2013static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2014 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2015
2016static SOC_ENUM_SINGLE_DECL(
2017 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2018 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2019
2020static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2021 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2022
2023static SOC_ENUM_SINGLE_DECL(
2024 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2025 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2026
2027static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2028 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2029
1570static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2030static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1571 struct snd_kcontrol *kcontrol, int event) 2031 struct snd_kcontrol *kcontrol, int event)
1572{ 2032{
@@ -1678,6 +2138,77 @@ static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1678 return 0; 2138 return 0;
1679} 2139}
1680 2140
2141static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2142 struct snd_kcontrol *kcontrol, int event)
2143{
2144 struct snd_soc_codec *codec = w->codec;
2145 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2146 unsigned int value;
2147
2148 switch (event) {
2149 case SND_SOC_DAPM_PRE_PMU:
2150 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2151 if (value & RT5677_IF1_ADC_CTRL_MASK)
2152 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2153 RT5677_IF1_ADC_MODE_MASK,
2154 RT5677_IF1_ADC_MODE_TDM);
2155 break;
2156
2157 default:
2158 return 0;
2159 }
2160
2161 return 0;
2162}
2163
2164static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2165 struct snd_kcontrol *kcontrol, int event)
2166{
2167 struct snd_soc_codec *codec = w->codec;
2168 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2169 unsigned int value;
2170
2171 switch (event) {
2172 case SND_SOC_DAPM_PRE_PMU:
2173 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2174 if (value & RT5677_IF2_ADC_CTRL_MASK)
2175 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2176 RT5677_IF2_ADC_MODE_MASK,
2177 RT5677_IF2_ADC_MODE_TDM);
2178 break;
2179
2180 default:
2181 return 0;
2182 }
2183
2184 return 0;
2185}
2186
2187static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2188 struct snd_kcontrol *kcontrol, int event)
2189{
2190 struct snd_soc_codec *codec = w->codec;
2191 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2192
2193 switch (event) {
2194 case SND_SOC_DAPM_POST_PMU:
2195 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2196 !rt5677->is_vref_slow) {
2197 mdelay(20);
2198 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2199 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2200 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2201 rt5677->is_vref_slow = true;
2202 }
2203 break;
2204
2205 default:
2206 return 0;
2207 }
2208
2209 return 0;
2210}
2211
1681static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2212static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1682 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2213 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1683 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU), 2214 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
@@ -1837,10 +2368,8 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1837 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2368 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1838 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2369 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2370 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1840 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2371 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1841 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2372 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1842 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1843 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1844 2373
1845 /* DSP */ 2374 /* DSP */
1846 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2375 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
@@ -1963,6 +2492,17 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1963 &rt5677_if1_adc3_mux), 2492 &rt5677_if1_adc3_mux),
1964 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2493 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1965 &rt5677_if1_adc4_mux), 2494 &rt5677_if1_adc4_mux),
2495 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2496 &rt5677_if1_adc1_swap_mux),
2497 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2498 &rt5677_if1_adc2_swap_mux),
2499 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2500 &rt5677_if1_adc3_swap_mux),
2501 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2502 &rt5677_if1_adc4_swap_mux),
2503 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2504 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2505 SND_SOC_DAPM_PRE_PMU),
1966 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2506 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1967 &rt5677_if2_adc1_mux), 2507 &rt5677_if2_adc1_mux),
1968 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2508 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
@@ -1971,6 +2511,17 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1971 &rt5677_if2_adc3_mux), 2511 &rt5677_if2_adc3_mux),
1972 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2512 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1973 &rt5677_if2_adc4_mux), 2513 &rt5677_if2_adc4_mux),
2514 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2515 &rt5677_if2_adc1_swap_mux),
2516 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2517 &rt5677_if2_adc2_swap_mux),
2518 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2519 &rt5677_if2_adc3_swap_mux),
2520 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2521 &rt5677_if2_adc4_swap_mux),
2522 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2523 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2524 SND_SOC_DAPM_PRE_PMU),
1974 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2525 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1975 &rt5677_if3_adc_mux), 2526 &rt5677_if3_adc_mux),
1976 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 2527 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
@@ -1984,6 +2535,40 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1984 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 2535 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1985 &rt5677_slb_adc4_mux), 2536 &rt5677_slb_adc4_mux),
1986 2537
2538 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2539 &rt5677_if1_dac0_tdm_sel_mux),
2540 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2541 &rt5677_if1_dac1_tdm_sel_mux),
2542 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2543 &rt5677_if1_dac2_tdm_sel_mux),
2544 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2545 &rt5677_if1_dac3_tdm_sel_mux),
2546 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2547 &rt5677_if1_dac4_tdm_sel_mux),
2548 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2549 &rt5677_if1_dac5_tdm_sel_mux),
2550 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2551 &rt5677_if1_dac6_tdm_sel_mux),
2552 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2553 &rt5677_if1_dac7_tdm_sel_mux),
2554
2555 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2556 &rt5677_if2_dac0_tdm_sel_mux),
2557 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2558 &rt5677_if2_dac1_tdm_sel_mux),
2559 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2560 &rt5677_if2_dac2_tdm_sel_mux),
2561 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2562 &rt5677_if2_dac3_tdm_sel_mux),
2563 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2564 &rt5677_if2_dac4_tdm_sel_mux),
2565 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2566 &rt5677_if2_dac5_tdm_sel_mux),
2567 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2568 &rt5677_if2_dac6_tdm_sel_mux),
2569 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2570 &rt5677_if2_dac7_tdm_sel_mux),
2571
1987 /* Audio Interface */ 2572 /* Audio Interface */
1988 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2573 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2574 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
@@ -2022,7 +2607,7 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2022 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 2607 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2023 2608
2024 /* Output Side */ 2609 /* Output Side */
2025 /* DAC mixer before sound effect */ 2610 /* DAC mixer before sound effect */
2026 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2611 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2027 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 2612 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2028 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2613 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
@@ -2109,13 +2694,20 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2109 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 2694 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2110 1, &rt5677_pdm2_r_mux), 2695 1, &rt5677_pdm2_r_mux),
2111 2696
2112 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 2697 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2113 0, NULL, 0), 2698 0, NULL, 0),
2114 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 2699 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2115 0, NULL, 0), 2700 0, NULL, 0),
2116 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 2701 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2117 0, NULL, 0), 2702 0, NULL, 0),
2118 2703
2704 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2705 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2706 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2707 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2708 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2709 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2710
2119 /* Output Lines */ 2711 /* Output Lines */
2120 SND_SOC_DAPM_OUTPUT("LOUT1"), 2712 SND_SOC_DAPM_OUTPUT("LOUT1"),
2121 SND_SOC_DAPM_OUTPUT("LOUT2"), 2713 SND_SOC_DAPM_OUTPUT("LOUT2"),
@@ -2124,6 +2716,8 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2124 SND_SOC_DAPM_OUTPUT("PDM1R"), 2716 SND_SOC_DAPM_OUTPUT("PDM1R"),
2125 SND_SOC_DAPM_OUTPUT("PDM2L"), 2717 SND_SOC_DAPM_OUTPUT("PDM2L"),
2126 SND_SOC_DAPM_OUTPUT("PDM2R"), 2718 SND_SOC_DAPM_OUTPUT("PDM2R"),
2719
2720 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
2127}; 2721};
2128 2722
2129static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 2723static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
@@ -2354,11 +2948,42 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2354 { "IF1 ADC4 Mux", "OB67", "OB67" }, 2948 { "IF1 ADC4 Mux", "OB67", "OB67" },
2355 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 2949 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2356 2950
2951 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
2952 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
2953 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
2954 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
2955
2956 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
2957 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
2958 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
2959 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
2960
2961 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
2962 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
2963 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
2964 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
2965
2966 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
2967 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
2968 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
2969 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
2970
2971 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
2972 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
2973 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
2974 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
2975
2976 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
2977 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
2978 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
2979 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
2980 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
2981 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
2982 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
2983 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
2984
2357 { "AIF1TX", NULL, "I2S1" }, 2985 { "AIF1TX", NULL, "I2S1" },
2358 { "AIF1TX", NULL, "IF1 ADC1 Mux" }, 2986 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
2359 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2360 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2361 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2362 2987
2363 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 2988 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2364 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 2989 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
@@ -2375,11 +3000,42 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2375 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3000 { "IF2 ADC4 Mux", "OB67", "OB67" },
2376 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3001 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2377 3002
3003 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3004 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3005 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3006 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3007
3008 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3009 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3010 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3011 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3012
3013 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3014 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3015 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3016 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3017
3018 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3019 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3020 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3021 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3022
3023 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3024 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3025 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3026 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3027
3028 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3029 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3030 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3031 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3032 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3033 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3034 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3035 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3036
2378 { "AIF2TX", NULL, "I2S2" }, 3037 { "AIF2TX", NULL, "I2S2" },
2379 { "AIF2TX", NULL, "IF2 ADC1 Mux" }, 3038 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
2380 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2381 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2382 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2383 3039
2384 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3040 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2385 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3041 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
@@ -2569,14 +3225,86 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2569 { "IF1 DAC6", NULL, "I2S1" }, 3225 { "IF1 DAC6", NULL, "I2S1" },
2570 { "IF1 DAC7", NULL, "I2S1" }, 3226 { "IF1 DAC7", NULL, "I2S1" },
2571 3227
2572 { "IF1 DAC01", NULL, "IF1 DAC0" }, 3228 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
2573 { "IF1 DAC01", NULL, "IF1 DAC1" }, 3229 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
2574 { "IF1 DAC23", NULL, "IF1 DAC2" }, 3230 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
2575 { "IF1 DAC23", NULL, "IF1 DAC3" }, 3231 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
2576 { "IF1 DAC45", NULL, "IF1 DAC4" }, 3232 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
2577 { "IF1 DAC45", NULL, "IF1 DAC5" }, 3233 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
2578 { "IF1 DAC67", NULL, "IF1 DAC6" }, 3234 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
2579 { "IF1 DAC67", NULL, "IF1 DAC7" }, 3235 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3236
3237 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3238 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3239 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3240 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3241 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3242 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3243 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3244 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3245
3246 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3247 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3248 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3249 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3250 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3251 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3252 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3253 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3254
3255 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3256 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3257 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3258 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3259 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3260 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3261 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3262 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3263
3264 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3265 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3266 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3267 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3268 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3269 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3270 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3271 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3272
3273 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3274 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3275 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3276 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3277 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3278 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3279 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3280 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3281
3282 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3283 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3284 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3285 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3286 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3287 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3288 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3289 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3290
3291 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3292 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3293 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3294 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3295 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3296 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3297 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3298 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3299
3300 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3301 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3302 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3303 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3304 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3305 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3306 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3307 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
2580 3308
2581 { "IF2 DAC0", NULL, "AIF2RX" }, 3309 { "IF2 DAC0", NULL, "AIF2RX" },
2582 { "IF2 DAC1", NULL, "AIF2RX" }, 3310 { "IF2 DAC1", NULL, "AIF2RX" },
@@ -2595,14 +3323,86 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2595 { "IF2 DAC6", NULL, "I2S2" }, 3323 { "IF2 DAC6", NULL, "I2S2" },
2596 { "IF2 DAC7", NULL, "I2S2" }, 3324 { "IF2 DAC7", NULL, "I2S2" },
2597 3325
2598 { "IF2 DAC01", NULL, "IF2 DAC0" }, 3326 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
2599 { "IF2 DAC01", NULL, "IF2 DAC1" }, 3327 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
2600 { "IF2 DAC23", NULL, "IF2 DAC2" }, 3328 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
2601 { "IF2 DAC23", NULL, "IF2 DAC3" }, 3329 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
2602 { "IF2 DAC45", NULL, "IF2 DAC4" }, 3330 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
2603 { "IF2 DAC45", NULL, "IF2 DAC5" }, 3331 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
2604 { "IF2 DAC67", NULL, "IF2 DAC6" }, 3332 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
2605 { "IF2 DAC67", NULL, "IF2 DAC7" }, 3333 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3334
3335 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3336 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3337 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3338 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3339 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3340 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3341 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3342 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3343
3344 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3345 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3346 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3347 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3348 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3349 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3350 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3351 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3352
3353 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3354 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3355 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3356 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3357 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3358 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3359 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3360 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3361
3362 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3363 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3364 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3365 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3366 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3367 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3368 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3369 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3370
3371 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3372 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3373 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3374 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3375 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3376 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3377 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3378 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3379
3380 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3381 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3382 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3383 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3384 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3385 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3386 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3387 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3388
3389 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3390 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3391 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3392 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3393 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3394 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3395 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3396 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3397
3398 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3399 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3400 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3401 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3402 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3403 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3404 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3405 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
2606 3406
2607 { "IF3 DAC", NULL, "AIF3RX" }, 3407 { "IF3 DAC", NULL, "AIF3RX" },
2608 { "IF3 DAC", NULL, "I2S3" }, 3408 { "IF3 DAC", NULL, "I2S3" },
@@ -2806,9 +3606,13 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2806 { "LOUT2 amp", NULL, "DAC 2" }, 3606 { "LOUT2 amp", NULL, "DAC 2" },
2807 { "LOUT3 amp", NULL, "DAC 3" }, 3607 { "LOUT3 amp", NULL, "DAC 3" },
2808 3608
2809 { "LOUT1", NULL, "LOUT1 amp" }, 3609 { "LOUT1 vref", NULL, "LOUT1 amp" },
2810 { "LOUT2", NULL, "LOUT2 amp" }, 3610 { "LOUT2 vref", NULL, "LOUT2 amp" },
2811 { "LOUT3", NULL, "LOUT3 amp" }, 3611 { "LOUT3 vref", NULL, "LOUT3 amp" },
3612
3613 { "LOUT1", NULL, "LOUT1 vref" },
3614 { "LOUT2", NULL, "LOUT2 vref" },
3615 { "LOUT3", NULL, "LOUT3 vref" },
2812 3616
2813 { "PDM1L", NULL, "PDM1 L Mux" }, 3617 { "PDM1L", NULL, "PDM1 L Mux" },
2814 { "PDM1R", NULL, "PDM1 R Mux" }, 3618 { "PDM1R", NULL, "PDM1 R Mux" },
@@ -2837,7 +3641,8 @@ static int rt5677_hw_params(struct snd_pcm_substream *substream,
2837 rt5677->lrck[dai->id] = params_rate(params); 3641 rt5677->lrck[dai->id] = params_rate(params);
2838 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 3642 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2839 if (pre_div < 0) { 3643 if (pre_div < 0) {
2840 dev_err(codec->dev, "Unsupported clock setting\n"); 3644 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3645 rt5677->sysclk, rt5677->lrck[dai->id]);
2841 return -EINVAL; 3646 return -EINVAL;
2842 } 3647 }
2843 frame_size = snd_soc_params_to_frame_size(params); 3648 frame_size = snd_soc_params_to_frame_size(params);
@@ -3181,6 +3986,8 @@ static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3181 3986
3182 case SND_SOC_BIAS_PREPARE: 3987 case SND_SOC_BIAS_PREPARE:
3183 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 3988 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3989 rt5677_set_dsp_vad(codec, false);
3990
3184 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 3991 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3185 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 3992 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3186 0x0055); 3993 0x0055);
@@ -3188,14 +3995,12 @@ static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3188 RT5677_PR_BASE + RT5677_BIAS_CUR4, 3995 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3189 0x0f00, 0x0f00); 3996 0x0f00, 0x0f00);
3190 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 3997 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3998 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
3191 RT5677_PWR_VREF1 | RT5677_PWR_MB | 3999 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3192 RT5677_PWR_BG | RT5677_PWR_VREF2, 4000 RT5677_PWR_BG | RT5677_PWR_VREF2,
3193 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4001 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3194 RT5677_PWR_BG | RT5677_PWR_VREF2); 4002 RT5677_PWR_BG | RT5677_PWR_VREF2);
3195 mdelay(20); 4003 rt5677->is_vref_slow = false;
3196 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3197 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3198 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3199 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4004 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3200 RT5677_PWR_CORE, RT5677_PWR_CORE); 4005 RT5677_PWR_CORE, RT5677_PWR_CORE);
3201 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4006 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
@@ -3214,6 +4019,9 @@ static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3214 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); 4019 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3215 regmap_update_bits(rt5677->regmap, 4020 regmap_update_bits(rt5677->regmap,
3216 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4021 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4022
4023 if (rt5677->dsp_vad_en)
4024 rt5677_set_dsp_vad(codec, true);
3217 break; 4025 break;
3218 4026
3219 default: 4027 default:
@@ -3309,6 +4117,78 @@ static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3309 return 0; 4117 return 0;
3310} 4118}
3311 4119
4120/** Configures the gpio as
4121 * 0 - floating
4122 * 1 - pull down
4123 * 2 - pull up
4124 */
4125static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4126 int value)
4127{
4128 int shift;
4129
4130 switch (offset) {
4131 case RT5677_GPIO1 ... RT5677_GPIO2:
4132 shift = 2 * (1 - offset);
4133 regmap_update_bits(rt5677->regmap,
4134 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4135 0x3 << shift,
4136 (value & 0x3) << shift);
4137 break;
4138
4139 case RT5677_GPIO3 ... RT5677_GPIO6:
4140 shift = 2 * (9 - offset);
4141 regmap_update_bits(rt5677->regmap,
4142 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4143 0x3 << shift,
4144 (value & 0x3) << shift);
4145 break;
4146
4147 default:
4148 break;
4149 }
4150}
4151
4152static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4153{
4154 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4155 struct regmap_irq_chip_data *data = rt5677->irq_data;
4156 int irq;
4157
4158 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4159 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4160 (rt5677->pdata.jd1_gpio == 2 &&
4161 offset == RT5677_GPIO2) ||
4162 (rt5677->pdata.jd1_gpio == 3 &&
4163 offset == RT5677_GPIO3)) {
4164 irq = RT5677_IRQ_JD1;
4165 } else {
4166 return -ENXIO;
4167 }
4168 }
4169
4170 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4171 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4172 (rt5677->pdata.jd2_gpio == 2 &&
4173 offset == RT5677_GPIO5) ||
4174 (rt5677->pdata.jd2_gpio == 3 &&
4175 offset == RT5677_GPIO6)) {
4176 irq = RT5677_IRQ_JD2;
4177 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4178 offset == RT5677_GPIO4) ||
4179 (rt5677->pdata.jd3_gpio == 2 &&
4180 offset == RT5677_GPIO5) ||
4181 (rt5677->pdata.jd3_gpio == 3 &&
4182 offset == RT5677_GPIO6)) {
4183 irq = RT5677_IRQ_JD3;
4184 } else {
4185 return -ENXIO;
4186 }
4187 }
4188
4189 return regmap_irq_get_virq(data, irq);
4190}
4191
3312static struct gpio_chip rt5677_template_chip = { 4192static struct gpio_chip rt5677_template_chip = {
3313 .label = "rt5677", 4193 .label = "rt5677",
3314 .owner = THIS_MODULE, 4194 .owner = THIS_MODULE,
@@ -3316,6 +4196,7 @@ static struct gpio_chip rt5677_template_chip = {
3316 .set = rt5677_gpio_set, 4196 .set = rt5677_gpio_set,
3317 .direction_input = rt5677_gpio_direction_in, 4197 .direction_input = rt5677_gpio_direction_in,
3318 .get = rt5677_gpio_get, 4198 .get = rt5677_gpio_get,
4199 .to_irq = rt5677_to_irq,
3319 .can_sleep = 1, 4200 .can_sleep = 1,
3320}; 4201};
3321 4202
@@ -3341,6 +4222,11 @@ static void rt5677_free_gpio(struct i2c_client *i2c)
3341 gpiochip_remove(&rt5677->gpio_chip); 4222 gpiochip_remove(&rt5677->gpio_chip);
3342} 4223}
3343#else 4224#else
4225static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4226 int value)
4227{
4228}
4229
3344static void rt5677_init_gpio(struct i2c_client *i2c) 4230static void rt5677_init_gpio(struct i2c_client *i2c)
3345{ 4231{
3346} 4232}
@@ -3353,6 +4239,7 @@ static void rt5677_free_gpio(struct i2c_client *i2c)
3353static int rt5677_probe(struct snd_soc_codec *codec) 4239static int rt5677_probe(struct snd_soc_codec *codec)
3354{ 4240{
3355 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4241 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4242 int i;
3356 4243
3357 rt5677->codec = codec; 4244 rt5677->codec = codec;
3358 4245
@@ -3371,6 +4258,37 @@ static int rt5677_probe(struct snd_soc_codec *codec)
3371 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); 4258 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3372 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); 4259 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3373 4260
4261 for (i = 0; i < RT5677_GPIO_NUM; i++)
4262 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4263
4264 if (rt5677->irq_data) {
4265 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4266 0x8000);
4267 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4268 0x0008);
4269
4270 if (rt5677->pdata.jd1_gpio)
4271 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4272 RT5677_SEL_GPIO_JD1_MASK,
4273 rt5677->pdata.jd1_gpio <<
4274 RT5677_SEL_GPIO_JD1_SFT);
4275
4276 if (rt5677->pdata.jd2_gpio)
4277 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4278 RT5677_SEL_GPIO_JD2_MASK,
4279 rt5677->pdata.jd2_gpio <<
4280 RT5677_SEL_GPIO_JD2_SFT);
4281
4282 if (rt5677->pdata.jd3_gpio)
4283 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4284 RT5677_SEL_GPIO_JD3_MASK,
4285 rt5677->pdata.jd3_gpio <<
4286 RT5677_SEL_GPIO_JD3_SFT);
4287 }
4288
4289 mutex_init(&rt5677->dsp_cmd_lock);
4290 mutex_init(&rt5677->dsp_pri_lock);
4291
3374 return 0; 4292 return 0;
3375} 4293}
3376 4294
@@ -3390,8 +4308,11 @@ static int rt5677_suspend(struct snd_soc_codec *codec)
3390{ 4308{
3391 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4309 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3392 4310
3393 regcache_cache_only(rt5677->regmap, true); 4311 if (!rt5677->dsp_vad_en) {
3394 regcache_mark_dirty(rt5677->regmap); 4312 regcache_cache_only(rt5677->regmap, true);
4313 regcache_mark_dirty(rt5677->regmap);
4314 }
4315
3395 if (gpio_is_valid(rt5677->pow_ldo2)) 4316 if (gpio_is_valid(rt5677->pow_ldo2))
3396 gpio_set_value_cansleep(rt5677->pow_ldo2, 0); 4317 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
3397 4318
@@ -3406,8 +4327,11 @@ static int rt5677_resume(struct snd_soc_codec *codec)
3406 gpio_set_value_cansleep(rt5677->pow_ldo2, 1); 4327 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
3407 msleep(10); 4328 msleep(10);
3408 } 4329 }
3409 regcache_cache_only(rt5677->regmap, false); 4330
3410 regcache_sync(rt5677->regmap); 4331 if (!rt5677->dsp_vad_en) {
4332 regcache_cache_only(rt5677->regmap, false);
4333 regcache_sync(rt5677->regmap);
4334 }
3411 4335
3412 return 0; 4336 return 0;
3413} 4337}
@@ -3416,6 +4340,51 @@ static int rt5677_resume(struct snd_soc_codec *codec)
3416#define rt5677_resume NULL 4340#define rt5677_resume NULL
3417#endif 4341#endif
3418 4342
4343static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4344{
4345 struct i2c_client *client = context;
4346 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4347
4348 if (rt5677->is_dsp_mode) {
4349 if (reg > 0xff) {
4350 mutex_lock(&rt5677->dsp_pri_lock);
4351 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4352 reg & 0xff);
4353 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4354 mutex_unlock(&rt5677->dsp_pri_lock);
4355 } else {
4356 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4357 }
4358 } else {
4359 regmap_read(rt5677->regmap_physical, reg, val);
4360 }
4361
4362 return 0;
4363}
4364
4365static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4366{
4367 struct i2c_client *client = context;
4368 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4369
4370 if (rt5677->is_dsp_mode) {
4371 if (reg > 0xff) {
4372 mutex_lock(&rt5677->dsp_pri_lock);
4373 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4374 reg & 0xff);
4375 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4376 val);
4377 mutex_unlock(&rt5677->dsp_pri_lock);
4378 } else {
4379 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4380 }
4381 } else {
4382 regmap_write(rt5677->regmap_physical, reg, val);
4383 }
4384
4385 return 0;
4386}
4387
3419#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 4388#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3420#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 4389#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3421 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 4390 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
@@ -3541,6 +4510,20 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3541 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 4510 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3542}; 4511};
3543 4512
4513static const struct regmap_config rt5677_regmap_physical = {
4514 .name = "physical",
4515 .reg_bits = 8,
4516 .val_bits = 16,
4517
4518 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4519 RT5677_PR_SPACING),
4520 .readable_reg = rt5677_readable_register,
4521
4522 .cache_type = REGCACHE_NONE,
4523 .ranges = rt5677_ranges,
4524 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4525};
4526
3544static const struct regmap_config rt5677_regmap = { 4527static const struct regmap_config rt5677_regmap = {
3545 .reg_bits = 8, 4528 .reg_bits = 8,
3546 .val_bits = 16, 4529 .val_bits = 16,
@@ -3550,6 +4533,8 @@ static const struct regmap_config rt5677_regmap = {
3550 4533
3551 .volatile_reg = rt5677_volatile_register, 4534 .volatile_reg = rt5677_volatile_register,
3552 .readable_reg = rt5677_readable_register, 4535 .readable_reg = rt5677_readable_register,
4536 .reg_read = rt5677_read,
4537 .reg_write = rt5677_write,
3553 4538
3554 .cache_type = REGCACHE_RBTREE, 4539 .cache_type = REGCACHE_RBTREE,
3555 .reg_defaults = rt5677_reg, 4540 .reg_defaults = rt5677_reg,
@@ -3590,9 +4575,77 @@ static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
3590 (rt5677->pow_ldo2 != -ENOENT)) 4575 (rt5677->pow_ldo2 != -ENOENT))
3591 return rt5677->pow_ldo2; 4576 return rt5677->pow_ldo2;
3592 4577
4578 of_property_read_u8_array(np, "realtek,gpio-config",
4579 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4580
4581 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4582 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4583 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4584
4585 return 0;
4586}
4587
4588static struct regmap_irq rt5677_irqs[] = {
4589 [RT5677_IRQ_JD1] = {
4590 .reg_offset = 0,
4591 .mask = RT5677_EN_IRQ_GPIO_JD1,
4592 },
4593 [RT5677_IRQ_JD2] = {
4594 .reg_offset = 0,
4595 .mask = RT5677_EN_IRQ_GPIO_JD2,
4596 },
4597 [RT5677_IRQ_JD3] = {
4598 .reg_offset = 0,
4599 .mask = RT5677_EN_IRQ_GPIO_JD3,
4600 },
4601};
4602
4603static struct regmap_irq_chip rt5677_irq_chip = {
4604 .name = "rt5677",
4605 .irqs = rt5677_irqs,
4606 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4607
4608 .num_regs = 1,
4609 .status_base = RT5677_IRQ_CTRL1,
4610 .mask_base = RT5677_IRQ_CTRL1,
4611 .mask_invert = 1,
4612};
4613
4614static int rt5677_init_irq(struct i2c_client *i2c)
4615{
4616 int ret;
4617 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4618
4619 if (!rt5677->pdata.jd1_gpio &&
4620 !rt5677->pdata.jd2_gpio &&
4621 !rt5677->pdata.jd3_gpio)
4622 return 0;
4623
4624 if (!i2c->irq) {
4625 dev_err(&i2c->dev, "No interrupt specified\n");
4626 return -EINVAL;
4627 }
4628
4629 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4630 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4631 &rt5677_irq_chip, &rt5677->irq_data);
4632
4633 if (ret != 0) {
4634 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4635 return ret;
4636 }
4637
3593 return 0; 4638 return 0;
3594} 4639}
3595 4640
4641static void rt5677_free_irq(struct i2c_client *i2c)
4642{
4643 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4644
4645 if (rt5677->irq_data)
4646 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4647}
4648
3596static int rt5677_i2c_probe(struct i2c_client *i2c, 4649static int rt5677_i2c_probe(struct i2c_client *i2c,
3597 const struct i2c_device_id *id) 4650 const struct i2c_device_id *id)
3598{ 4651{
@@ -3638,7 +4691,16 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
3638 msleep(10); 4691 msleep(10);
3639 } 4692 }
3640 4693
3641 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap); 4694 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4695 &rt5677_regmap_physical);
4696 if (IS_ERR(rt5677->regmap_physical)) {
4697 ret = PTR_ERR(rt5677->regmap_physical);
4698 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4699 ret);
4700 return ret;
4701 }
4702
4703 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
3642 if (IS_ERR(rt5677->regmap)) { 4704 if (IS_ERR(rt5677->regmap)) {
3643 ret = PTR_ERR(rt5677->regmap); 4705 ret = PTR_ERR(rt5677->regmap);
3644 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4706 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
@@ -3690,6 +4752,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
3690 } 4752 }
3691 4753
3692 rt5677_init_gpio(i2c); 4754 rt5677_init_gpio(i2c);
4755 rt5677_init_irq(i2c);
3693 4756
3694 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, 4757 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3695 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 4758 rt5677_dai, ARRAY_SIZE(rt5677_dai));
@@ -3698,6 +4761,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
3698static int rt5677_i2c_remove(struct i2c_client *i2c) 4761static int rt5677_i2c_remove(struct i2c_client *i2c)
3699{ 4762{
3700 snd_soc_unregister_codec(&i2c->dev); 4763 snd_soc_unregister_codec(&i2c->dev);
4764 rt5677_free_irq(i2c);
3701 rt5677_free_gpio(i2c); 4765 rt5677_free_gpio(i2c);
3702 4766
3703 return 0; 4767 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 11:14:21 -0500