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Diffstat (limited to 'sound/soc/codecs/cs42l52.h')
-rw-r--r-- | sound/soc/codecs/cs42l52.h | 274 |
1 files changed, 274 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs42l52.h b/sound/soc/codecs/cs42l52.h new file mode 100644 index 000000000000..60985c059071 --- /dev/null +++ b/sound/soc/codecs/cs42l52.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /* | ||
2 | * cs42l52.h -- CS42L52 ALSA SoC audio driver | ||
3 | * | ||
4 | * Copyright 2012 CirrusLogic, Inc. | ||
5 | * | ||
6 | * Author: Georgi Vlaev <joe@nucleusys.com> | ||
7 | * Author: Brian Austin <brian.austin@cirrus.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #ifndef __CS42L52_H__ | ||
16 | #define __CS42L52_H__ | ||
17 | |||
18 | #define CS42L52_NAME "CS42L52" | ||
19 | #define CS42L52_DEFAULT_CLK 12000000 | ||
20 | #define CS42L52_MIN_CLK 11000000 | ||
21 | #define CS42L52_MAX_CLK 27000000 | ||
22 | #define CS42L52_DEFAULT_FORMAT SNDRV_PCM_FMTBIT_S16_LE | ||
23 | #define CS42L52_DEFAULT_MAX_CHANS 2 | ||
24 | #define CS42L52_SYSCLK 1 | ||
25 | |||
26 | #define CS42L52_CHIP_SWICTH (1 << 17) | ||
27 | #define CS42L52_ALL_IN_ONE (1 << 16) | ||
28 | #define CS42L52_CHIP_ONE 0x00 | ||
29 | #define CS42L52_CHIP_TWO 0x01 | ||
30 | #define CS42L52_CHIP_THR 0x02 | ||
31 | #define CS42L52_CHIP_MASK 0x0f | ||
32 | |||
33 | #define CS42L52_FIX_BITS_CTL 0x00 | ||
34 | #define CS42L52_CHIP 0x01 | ||
35 | #define CS42L52_CHIP_ID 0xE0 | ||
36 | #define CS42L52_CHIP_ID_MASK 0xF8 | ||
37 | #define CS42L52_CHIP_REV_A0 0x00 | ||
38 | #define CS42L52_CHIP_REV_A1 0x01 | ||
39 | #define CS42L52_CHIP_REV_B0 0x02 | ||
40 | #define CS42L52_CHIP_REV_MASK 0x03 | ||
41 | |||
42 | #define CS42L52_PWRCTL1 0x02 | ||
43 | #define CS42L52_PWRCTL1_PDN_ALL 0x9F | ||
44 | #define CS42L52_PWRCTL1_PDN_CHRG 0x80 | ||
45 | #define CS42L52_PWRCTL1_PDN_PGAB 0x10 | ||
46 | #define CS42L52_PWRCTL1_PDN_PGAA 0x08 | ||
47 | #define CS42L52_PWRCTL1_PDN_ADCB 0x04 | ||
48 | #define CS42L52_PWRCTL1_PDN_ADCA 0x02 | ||
49 | #define CS42L52_PWRCTL1_PDN_CODEC 0x01 | ||
50 | |||
51 | #define CS42L52_PWRCTL2 0x03 | ||
52 | #define CS42L52_PWRCTL2_OVRDB (1 << 4) | ||
53 | #define CS42L52_PWRCTL2_OVRDA (1 << 3) | ||
54 | #define CS42L52_PWRCTL2_PDN_MICB (1 << 2) | ||
55 | #define CS42L52_PWRCTL2_PDN_MICB_SHIFT 2 | ||
56 | #define CS42L52_PWRCTL2_PDN_MICA (1 << 1) | ||
57 | #define CS42L52_PWRCTL2_PDN_MICA_SHIFT 1 | ||
58 | #define CS42L52_PWRCTL2_PDN_MICBIAS (1 << 0) | ||
59 | #define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT 0 | ||
60 | |||
61 | #define CS42L52_PWRCTL3 0x04 | ||
62 | #define CS42L52_PWRCTL3_HPB_PDN_SHIFT 6 | ||
63 | #define CS42L52_PWRCTL3_HPB_ON_LOW 0x00 | ||
64 | #define CS42L52_PWRCTL3_HPB_ON_HIGH 0x01 | ||
65 | #define CS42L52_PWRCTL3_HPB_ALWAYS_ON 0x02 | ||
66 | #define CS42L52_PWRCTL3_HPB_ALWAYS_OFF 0x03 | ||
67 | #define CS42L52_PWRCTL3_HPA_PDN_SHIFT 4 | ||
68 | #define CS42L52_PWRCTL3_HPA_ON_LOW 0x00 | ||
69 | #define CS42L52_PWRCTL3_HPA_ON_HIGH 0x01 | ||
70 | #define CS42L52_PWRCTL3_HPA_ALWAYS_ON 0x02 | ||
71 | #define CS42L52_PWRCTL3_HPA_ALWAYS_OFF 0x03 | ||
72 | #define CS42L52_PWRCTL3_SPKB_PDN_SHIFT 2 | ||
73 | #define CS42L52_PWRCTL3_SPKB_ON_LOW 0x00 | ||
74 | #define CS42L52_PWRCTL3_SPKB_ON_HIGH 0x01 | ||
75 | #define CS42L52_PWRCTL3_SPKB_ALWAYS_ON 0x02 | ||
76 | #define CS42L52_PWRCTL3_PDN_SPKB (1 << 2) | ||
77 | #define CS42L52_PWRCTL3_PDN_SPKA (1 << 0) | ||
78 | #define CS42L52_PWRCTL3_SPKA_PDN_SHIFT 0 | ||
79 | #define CS42L52_PWRCTL3_SPKA_ON_LOW 0x00 | ||
80 | #define CS42L52_PWRCTL3_SPKA_ON_HIGH 0x01 | ||
81 | #define CS42L52_PWRCTL3_SPKA_ALWAYS_ON 0x02 | ||
82 | |||
83 | #define CS42L52_DEFAULT_OUTPUT_STATE 0x05 | ||
84 | #define CS42L52_PWRCTL3_CONF_MASK 0x03 | ||
85 | |||
86 | #define CS42L52_CLK_CTL 0x05 | ||
87 | #define CLK_AUTODECT_ENABLE (1 << 7) | ||
88 | #define CLK_SPEED_SHIFT 5 | ||
89 | #define CLK_DS_MODE 0x00 | ||
90 | #define CLK_SS_MODE 0x01 | ||
91 | #define CLK_HS_MODE 0x02 | ||
92 | #define CLK_QS_MODE 0x03 | ||
93 | #define CLK_32K_SR_SHIFT 4 | ||
94 | #define CLK_32K 0x01 | ||
95 | #define CLK_NO_32K 0x00 | ||
96 | #define CLK_27M_MCLK_SHIFT 3 | ||
97 | #define CLK_27M_MCLK 0x01 | ||
98 | #define CLK_NO_27M 0x00 | ||
99 | #define CLK_RATIO_SHIFT 1 | ||
100 | #define CLK_R_128 0x00 | ||
101 | #define CLK_R_125 0x01 | ||
102 | #define CLK_R_132 0x02 | ||
103 | #define CLK_R_136 0x03 | ||
104 | |||
105 | #define CS42L52_IFACE_CTL1 0x06 | ||
106 | #define CS42L52_IFACE_CTL1_MASTER (1 << 7) | ||
107 | #define CS42L52_IFACE_CTL1_SLAVE (0 << 7) | ||
108 | #define CS42L52_IFACE_CTL1_INV_SCLK (1 << 6) | ||
109 | #define CS42L52_IFACE_CTL1_ADC_FMT_I2S (1 << 5) | ||
110 | #define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J (0 << 5) | ||
111 | #define CS42L52_IFACE_CTL1_DSP_MODE_EN (1 << 4) | ||
112 | #define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J (0 << 2) | ||
113 | #define CS42L52_IFACE_CTL1_DAC_FMT_I2S (1 << 2) | ||
114 | #define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J (2 << 2) | ||
115 | #define CS42L52_IFACE_CTL1_WL_32BIT (0x00) | ||
116 | #define CS42L52_IFACE_CTL1_WL_24BIT (0x01) | ||
117 | #define CS42L52_IFACE_CTL1_WL_20BIT (0x02) | ||
118 | #define CS42L52_IFACE_CTL1_WL_16BIT (0x03) | ||
119 | #define CS42L52_IFACE_CTL1_WL_MASK 0xFFFF | ||
120 | |||
121 | #define CS42L52_IFACE_CTL2 0x07 | ||
122 | #define CS42L52_IFACE_CTL2_SC_MC_EQ (1 << 6) | ||
123 | #define CS42L52_IFACE_CTL2_LOOPBACK (1 << 5) | ||
124 | #define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN (0 << 4) | ||
125 | #define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ (1 << 4) | ||
126 | #define CS42L52_IFACE_CTL2_HP_SW_INV (1 << 3) | ||
127 | #define CS42L52_IFACE_CTL2_BIAS_LVL 0x07 | ||
128 | |||
129 | #define CS42L52_ADC_PGA_A 0x08 | ||
130 | #define CS42L52_ADC_PGA_B 0x09 | ||
131 | #define CS42L52_ADC_SEL_SHIFT 5 | ||
132 | #define CS42L52_ADC_SEL_AIN1 0x00 | ||
133 | #define CS42L52_ADC_SEL_AIN2 0x01 | ||
134 | #define CS42L52_ADC_SEL_AIN3 0x02 | ||
135 | #define CS42L52_ADC_SEL_AIN4 0x03 | ||
136 | #define CS42L52_ADC_SEL_PGA 0x04 | ||
137 | |||
138 | #define CS42L52_ANALOG_HPF_CTL 0x0A | ||
139 | #define CS42L52_HPF_CTL_ANLGSFTB (1 << 3) | ||
140 | #define CS42L52_HPF_CTL_ANLGSFTA (1 << 0) | ||
141 | |||
142 | #define CS42L52_ADC_HPF_FREQ 0x0B | ||
143 | #define CS42L52_ADC_MISC_CTL 0x0C | ||
144 | #define CS42L52_ADC_MISC_CTL_SOURCE_DSP (1 << 6) | ||
145 | |||
146 | #define CS42L52_PB_CTL1 0x0D | ||
147 | #define CS42L52_PB_CTL1_HP_GAIN_SHIFT 5 | ||
148 | #define CS42L52_PB_CTL1_HP_GAIN_03959 0x00 | ||
149 | #define CS42L52_PB_CTL1_HP_GAIN_04571 0x01 | ||
150 | #define CS42L52_PB_CTL1_HP_GAIN_05111 0x02 | ||
151 | #define CS42L52_PB_CTL1_HP_GAIN_06047 0x03 | ||
152 | #define CS42L52_PB_CTL1_HP_GAIN_07099 0x04 | ||
153 | #define CS42L52_PB_CTL1_HP_GAIN_08399 0x05 | ||
154 | #define CS42L52_PB_CTL1_HP_GAIN_10000 0x06 | ||
155 | #define CS42L52_PB_CTL1_HP_GAIN_11430 0x07 | ||
156 | #define CS42L52_PB_CTL1_INV_PCMB (1 << 3) | ||
157 | #define CS42L52_PB_CTL1_INV_PCMA (1 << 2) | ||
158 | #define CS42L52_PB_CTL1_MSTB_MUTE (1 << 1) | ||
159 | #define CS42L52_PB_CTL1_MSTA_MUTE (1 << 0) | ||
160 | #define CS42L52_PB_CTL1_MUTE_MASK 0xFFFD | ||
161 | #define CS42L52_PB_CTL1_MUTE 3 | ||
162 | #define CS42L52_PB_CTL1_UNMUTE 0 | ||
163 | |||
164 | #define CS42L52_MISC_CTL 0x0E | ||
165 | #define CS42L52_MISC_CTL_DEEMPH (1 << 2) | ||
166 | #define CS42L52_MISC_CTL_DIGSFT (1 << 1) | ||
167 | #define CS42L52_MISC_CTL_DIGZC (1 << 0) | ||
168 | |||
169 | #define CS42L52_PB_CTL2 0x0F | ||
170 | #define CS42L52_PB_CTL2_HPB_MUTE (1 << 7) | ||
171 | #define CS42L52_PB_CTL2_HPA_MUTE (1 << 6) | ||
172 | #define CS42L52_PB_CTL2_SPKB_MUTE (1 << 5) | ||
173 | #define CS42L52_PB_CTL2_SPKA_MUTE (1 << 4) | ||
174 | #define CS42L52_PB_CTL2_SPK_SWAP (1 << 2) | ||
175 | #define CS42L52_PB_CTL2_SPK_MONO (1 << 1) | ||
176 | #define CS42L52_PB_CTL2_SPK_MUTE50 (1 << 0) | ||
177 | |||
178 | #define CS42L52_MICA_CTL 0x10 | ||
179 | #define CS42L52_MICB_CTL 0x11 | ||
180 | #define CS42L52_MIC_CTL_MIC_SEL_MASK 0xBF | ||
181 | #define CS42L52_MIC_CTL_MIC_SEL_SHIFT 6 | ||
182 | #define CS42L52_MIC_CTL_TYPE_MASK 0xDF | ||
183 | #define CS42L52_MIC_CTL_TYPE_SHIFT 5 | ||
184 | |||
185 | |||
186 | #define CS42L52_PGAA_CTL 0x12 | ||
187 | #define CS42L52_PGAB_CTL 0x13 | ||
188 | #define CS42L52_PGAX_CTL_VOL_12DB 24 | ||
189 | #define CS42L52_PGAX_CTL_VOL_6DB 12 /*step size 0.5db*/ | ||
190 | |||
191 | #define CS42L52_PASSTHRUA_VOL 0x14 | ||
192 | #define CS42L52_PASSTHRUB_VOL 0x15 | ||
193 | |||
194 | #define CS42L52_ADCA_VOL 0x16 | ||
195 | #define CS42L52_ADCB_VOL 0x17 | ||
196 | #define CS42L52_ADCX_VOL_24DB 24 /*step size 1db*/ | ||
197 | #define CS42L52_ADCX_VOL_12DB 12 | ||
198 | #define CS42L52_ADCX_VOL_6DB 6 | ||
199 | |||
200 | #define CS42L52_ADCA_MIXER_VOL 0x18 | ||
201 | #define CS42L52_ADCB_MIXER_VOL 0x19 | ||
202 | #define CS42L52_ADC_MIXER_VOL_12DB 0x18 | ||
203 | |||
204 | #define CS42L52_PCMA_MIXER_VOL 0x1A | ||
205 | #define CS42L52_PCMB_MIXER_VOL 0x1B | ||
206 | |||
207 | #define CS42L52_BEEP_FREQ 0x1C | ||
208 | #define CS42L52_BEEP_VOL 0x1D | ||
209 | #define CS42L52_BEEP_TONE_CTL 0x1E | ||
210 | #define CS42L52_BEEP_RATE_SHIFT 4 | ||
211 | #define CS42L52_BEEP_RATE_MASK 0x0F | ||
212 | |||
213 | #define CS42L52_TONE_CTL 0x1F | ||
214 | #define CS42L52_BEEP_EN_MASK 0x3F | ||
215 | |||
216 | #define CS42L52_MASTERA_VOL 0x20 | ||
217 | #define CS42L52_MASTERB_VOL 0x21 | ||
218 | |||
219 | #define CS42L52_HPA_VOL 0x22 | ||
220 | #define CS42L52_HPB_VOL 0x23 | ||
221 | #define CS42L52_DEFAULT_HP_VOL 0xF0 | ||
222 | |||
223 | #define CS42L52_SPKA_VOL 0x24 | ||
224 | #define CS42L52_SPKB_VOL 0x25 | ||
225 | #define CS42L52_DEFAULT_SPK_VOL 0xF0 | ||
226 | |||
227 | #define CS42L52_ADC_PCM_MIXER 0x26 | ||
228 | |||
229 | #define CS42L52_LIMITER_CTL1 0x27 | ||
230 | #define CS42L52_LIMITER_CTL2 0x28 | ||
231 | #define CS42L52_LIMITER_AT_RATE 0x29 | ||
232 | |||
233 | #define CS42L52_ALC_CTL 0x2A | ||
234 | #define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT 7 | ||
235 | #define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT 6 | ||
236 | #define CS42L52_ALC_CTL_FASTEST_ATTACK 0 | ||
237 | |||
238 | #define CS42L52_ALC_RATE 0x2B | ||
239 | #define CS42L52_ALC_SLOWEST_RELEASE 0x3F | ||
240 | |||
241 | #define CS42L52_ALC_THRESHOLD 0x2C | ||
242 | #define CS42L52_ALC_MAX_RATE_SHIFT 5 | ||
243 | #define CS42L52_ALC_MIN_RATE_SHIFT 2 | ||
244 | #define CS42L52_ALC_RATE_0DB 0 | ||
245 | #define CS42L52_ALC_RATE_3DB 1 | ||
246 | #define CS42L52_ALC_RATE_6DB 2 | ||
247 | |||
248 | #define CS42L52_NOISE_GATE_CTL 0x2D | ||
249 | #define CS42L52_NG_ENABLE_SHIFT 6 | ||
250 | #define CS42L52_NG_THRESHOLD_SHIFT 2 | ||
251 | #define CS42L52_NG_MIN_70DB 2 | ||
252 | #define CS42L52_NG_DELAY_SHIFT 0 | ||
253 | #define CS42L52_NG_DELAY_100MS 1 | ||
254 | |||
255 | #define CS42L52_CLK_STATUS 0x2E | ||
256 | #define CS42L52_BATT_COMPEN 0x2F | ||
257 | |||
258 | #define CS42L52_BATT_LEVEL 0x30 | ||
259 | #define CS42L52_SPK_STATUS 0x31 | ||
260 | #define CS42L52_SPK_STATUS_PIN_SHIFT 3 | ||
261 | #define CS42L52_SPK_STATUS_PIN_HIGH 1 | ||
262 | |||
263 | #define CS42L52_TEM_CTL 0x32 | ||
264 | #define CS42L52_TEM_CTL_SET 0x80 | ||
265 | #define CS42L52_THE_FOLDBACK 0x33 | ||
266 | #define CS42L52_CHARGE_PUMP 0x34 | ||
267 | #define CS42L52_CHARGE_PUMP_MASK 0xF0 | ||
268 | #define CS42L52_CHARGE_PUMP_SHIFT 4 | ||
269 | #define CS42L52_FIX_BITS1 0x3E | ||
270 | #define CS42L52_FIX_BITS2 0x47 | ||
271 | |||
272 | #define CS42L52_MAX_REGISTER 0x34 | ||
273 | |||
274 | #endif | ||