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Diffstat (limited to 'sound/soc/codecs/cs42l52.c')
-rw-r--r--sound/soc/codecs/cs42l52.c93
1 files changed, 54 insertions, 39 deletions
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index be2ba1b6fe4a..8b427c977083 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -17,6 +17,7 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/gpio.h>
20#include <linux/pm.h> 21#include <linux/pm.h>
21#include <linux/i2c.h> 22#include <linux/i2c.h>
22#include <linux/input.h> 23#include <linux/input.h>
@@ -1116,40 +1117,6 @@ static int cs42l52_probe(struct snd_soc_codec *codec)
1116 cs42l52->sysclk = CS42L52_DEFAULT_CLK; 1117 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1117 cs42l52->config.format = CS42L52_DEFAULT_FORMAT; 1118 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1118 1119
1119 /* Set Platform MICx CFG */
1120 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1121 CS42L52_MIC_CTL_TYPE_MASK,
1122 cs42l52->pdata.mica_cfg <<
1123 CS42L52_MIC_CTL_TYPE_SHIFT);
1124
1125 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1126 CS42L52_MIC_CTL_TYPE_MASK,
1127 cs42l52->pdata.micb_cfg <<
1128 CS42L52_MIC_CTL_TYPE_SHIFT);
1129
1130 /* if Single Ended, Get Mic_Select */
1131 if (cs42l52->pdata.mica_cfg)
1132 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1133 CS42L52_MIC_CTL_MIC_SEL_MASK,
1134 cs42l52->pdata.mica_sel <<
1135 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1136 if (cs42l52->pdata.micb_cfg)
1137 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1138 CS42L52_MIC_CTL_MIC_SEL_MASK,
1139 cs42l52->pdata.micb_sel <<
1140 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1141
1142 /* Set Platform Charge Pump Freq */
1143 snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,
1144 CS42L52_CHARGE_PUMP_MASK,
1145 cs42l52->pdata.chgfreq <<
1146 CS42L52_CHARGE_PUMP_SHIFT);
1147
1148 /* Set Platform Bias Level */
1149 snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,
1150 CS42L52_IFACE_CTL2_BIAS_LVL,
1151 cs42l52->pdata.micbias_lvl);
1152
1153 return ret; 1120 return ret;
1154} 1121}
1155 1122
@@ -1205,6 +1172,7 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1205 const struct i2c_device_id *id) 1172 const struct i2c_device_id *id)
1206{ 1173{
1207 struct cs42l52_private *cs42l52; 1174 struct cs42l52_private *cs42l52;
1175 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1208 int ret; 1176 int ret;
1209 unsigned int devid = 0; 1177 unsigned int devid = 0;
1210 unsigned int reg; 1178 unsigned int reg;
@@ -1222,11 +1190,22 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1222 return ret; 1190 return ret;
1223 } 1191 }
1224 1192
1225 i2c_set_clientdata(i2c_client, cs42l52); 1193 if (pdata)
1194 cs42l52->pdata = *pdata;
1195
1196 if (cs42l52->pdata.reset_gpio) {
1197 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1198 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1199 if (ret < 0) {
1200 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1201 cs42l52->pdata.reset_gpio, ret);
1202 return ret;
1203 }
1204 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1205 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1206 }
1226 1207
1227 if (dev_get_platdata(&i2c_client->dev)) 1208 i2c_set_clientdata(i2c_client, cs42l52);
1228 memcpy(&cs42l52->pdata, dev_get_platdata(&i2c_client->dev),
1229 sizeof(cs42l52->pdata));
1230 1209
1231 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch, 1210 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1232 ARRAY_SIZE(cs42l52_threshold_patch)); 1211 ARRAY_SIZE(cs42l52_threshold_patch));
@@ -1244,7 +1223,43 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1244 return ret; 1223 return ret;
1245 } 1224 }
1246 1225
1247 regcache_cache_only(cs42l52->regmap, true); 1226 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1227 reg & 0xFF);
1228
1229 /* Set Platform Data */
1230 if (cs42l52->pdata.mica_cfg)
1231 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1232 CS42L52_MIC_CTL_TYPE_MASK,
1233 cs42l52->pdata.mica_cfg <<
1234 CS42L52_MIC_CTL_TYPE_SHIFT);
1235
1236 if (cs42l52->pdata.micb_cfg)
1237 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1238 CS42L52_MIC_CTL_TYPE_MASK,
1239 cs42l52->pdata.micb_cfg <<
1240 CS42L52_MIC_CTL_TYPE_SHIFT);
1241
1242 if (cs42l52->pdata.mica_sel)
1243 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1244 CS42L52_MIC_CTL_MIC_SEL_MASK,
1245 cs42l52->pdata.mica_sel <<
1246 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1247 if (cs42l52->pdata.micb_sel)
1248 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1249 CS42L52_MIC_CTL_MIC_SEL_MASK,
1250 cs42l52->pdata.micb_sel <<
1251 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1252
1253 if (cs42l52->pdata.chgfreq)
1254 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1255 CS42L52_CHARGE_PUMP_MASK,
1256 cs42l52->pdata.chgfreq <<
1257 CS42L52_CHARGE_PUMP_SHIFT);
1258
1259 if (cs42l52->pdata.micbias_lvl)
1260 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1261 CS42L52_IFACE_CTL2_BIAS_LVL,
1262 cs42l52->pdata.micbias_lvl);
1248 1263
1249 ret = snd_soc_register_codec(&i2c_client->dev, 1264 ret = snd_soc_register_codec(&i2c_client->dev,
1250 &soc_codec_dev_cs42l52, &cs42l52_dai, 1); 1265 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);