diff options
Diffstat (limited to 'sound/soc/cirrus/ep93xx-ac97.c')
-rw-r--r-- | sound/soc/cirrus/ep93xx-ac97.c | 435 |
1 files changed, 435 insertions, 0 deletions
diff --git a/sound/soc/cirrus/ep93xx-ac97.c b/sound/soc/cirrus/ep93xx-ac97.c new file mode 100644 index 000000000000..c3521653cfd3 --- /dev/null +++ b/sound/soc/cirrus/ep93xx-ac97.c | |||
@@ -0,0 +1,435 @@ | |||
1 | /* | ||
2 | * ASoC driver for Cirrus Logic EP93xx AC97 controller. | ||
3 | * | ||
4 | * Copyright (c) 2010 Mika Westerberg | ||
5 | * | ||
6 | * Based on s3c-ac97 ASoC driver by Jaswinder Singh. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/delay.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | #include <linux/slab.h> | ||
19 | |||
20 | #include <sound/core.h> | ||
21 | #include <sound/ac97_codec.h> | ||
22 | #include <sound/soc.h> | ||
23 | |||
24 | #include <linux/platform_data/dma-ep93xx.h> | ||
25 | #include "ep93xx-pcm.h" | ||
26 | |||
27 | /* | ||
28 | * Per channel (1-4) registers. | ||
29 | */ | ||
30 | #define AC97CH(n) (((n) - 1) * 0x20) | ||
31 | |||
32 | #define AC97DR(n) (AC97CH(n) + 0x0000) | ||
33 | |||
34 | #define AC97RXCR(n) (AC97CH(n) + 0x0004) | ||
35 | #define AC97RXCR_REN BIT(0) | ||
36 | #define AC97RXCR_RX3 BIT(3) | ||
37 | #define AC97RXCR_RX4 BIT(4) | ||
38 | #define AC97RXCR_CM BIT(15) | ||
39 | |||
40 | #define AC97TXCR(n) (AC97CH(n) + 0x0008) | ||
41 | #define AC97TXCR_TEN BIT(0) | ||
42 | #define AC97TXCR_TX3 BIT(3) | ||
43 | #define AC97TXCR_TX4 BIT(4) | ||
44 | #define AC97TXCR_CM BIT(15) | ||
45 | |||
46 | #define AC97SR(n) (AC97CH(n) + 0x000c) | ||
47 | #define AC97SR_TXFE BIT(1) | ||
48 | #define AC97SR_TXUE BIT(6) | ||
49 | |||
50 | #define AC97RISR(n) (AC97CH(n) + 0x0010) | ||
51 | #define AC97ISR(n) (AC97CH(n) + 0x0014) | ||
52 | #define AC97IE(n) (AC97CH(n) + 0x0018) | ||
53 | |||
54 | /* | ||
55 | * Global AC97 controller registers. | ||
56 | */ | ||
57 | #define AC97S1DATA 0x0080 | ||
58 | #define AC97S2DATA 0x0084 | ||
59 | #define AC97S12DATA 0x0088 | ||
60 | |||
61 | #define AC97RGIS 0x008c | ||
62 | #define AC97GIS 0x0090 | ||
63 | #define AC97IM 0x0094 | ||
64 | /* | ||
65 | * Common bits for RGIS, GIS and IM registers. | ||
66 | */ | ||
67 | #define AC97_SLOT2RXVALID BIT(1) | ||
68 | #define AC97_CODECREADY BIT(5) | ||
69 | #define AC97_SLOT2TXCOMPLETE BIT(6) | ||
70 | |||
71 | #define AC97EOI 0x0098 | ||
72 | #define AC97EOI_WINT BIT(0) | ||
73 | #define AC97EOI_CODECREADY BIT(1) | ||
74 | |||
75 | #define AC97GCR 0x009c | ||
76 | #define AC97GCR_AC97IFE BIT(0) | ||
77 | |||
78 | #define AC97RESET 0x00a0 | ||
79 | #define AC97RESET_TIMEDRESET BIT(0) | ||
80 | |||
81 | #define AC97SYNC 0x00a4 | ||
82 | #define AC97SYNC_TIMEDSYNC BIT(0) | ||
83 | |||
84 | #define AC97_TIMEOUT msecs_to_jiffies(5) | ||
85 | |||
86 | /** | ||
87 | * struct ep93xx_ac97_info - EP93xx AC97 controller info structure | ||
88 | * @lock: mutex serializing access to the bus (slot 1 & 2 ops) | ||
89 | * @dev: pointer to the platform device dev structure | ||
90 | * @regs: mapped AC97 controller registers | ||
91 | * @done: bus ops wait here for an interrupt | ||
92 | */ | ||
93 | struct ep93xx_ac97_info { | ||
94 | struct mutex lock; | ||
95 | struct device *dev; | ||
96 | void __iomem *regs; | ||
97 | struct completion done; | ||
98 | }; | ||
99 | |||
100 | /* currently ALSA only supports a single AC97 device */ | ||
101 | static struct ep93xx_ac97_info *ep93xx_ac97_info; | ||
102 | |||
103 | static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_out = { | ||
104 | .name = "ac97-pcm-out", | ||
105 | .dma_port = EP93XX_DMA_AAC1, | ||
106 | }; | ||
107 | |||
108 | static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_in = { | ||
109 | .name = "ac97-pcm-in", | ||
110 | .dma_port = EP93XX_DMA_AAC1, | ||
111 | }; | ||
112 | |||
113 | static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info, | ||
114 | unsigned reg) | ||
115 | { | ||
116 | return __raw_readl(info->regs + reg); | ||
117 | } | ||
118 | |||
119 | static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info, | ||
120 | unsigned reg, unsigned val) | ||
121 | { | ||
122 | __raw_writel(val, info->regs + reg); | ||
123 | } | ||
124 | |||
125 | static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97, | ||
126 | unsigned short reg) | ||
127 | { | ||
128 | struct ep93xx_ac97_info *info = ep93xx_ac97_info; | ||
129 | unsigned short val; | ||
130 | |||
131 | mutex_lock(&info->lock); | ||
132 | |||
133 | ep93xx_ac97_write_reg(info, AC97S1DATA, reg); | ||
134 | ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID); | ||
135 | if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) { | ||
136 | dev_warn(info->dev, "timeout reading register %x\n", reg); | ||
137 | mutex_unlock(&info->lock); | ||
138 | return -ETIMEDOUT; | ||
139 | } | ||
140 | val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA); | ||
141 | |||
142 | mutex_unlock(&info->lock); | ||
143 | return val; | ||
144 | } | ||
145 | |||
146 | static void ep93xx_ac97_write(struct snd_ac97 *ac97, | ||
147 | unsigned short reg, | ||
148 | unsigned short val) | ||
149 | { | ||
150 | struct ep93xx_ac97_info *info = ep93xx_ac97_info; | ||
151 | |||
152 | mutex_lock(&info->lock); | ||
153 | |||
154 | /* | ||
155 | * Writes to the codec need to be done so that slot 2 is filled in | ||
156 | * before slot 1. | ||
157 | */ | ||
158 | ep93xx_ac97_write_reg(info, AC97S2DATA, val); | ||
159 | ep93xx_ac97_write_reg(info, AC97S1DATA, reg); | ||
160 | |||
161 | ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE); | ||
162 | if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) | ||
163 | dev_warn(info->dev, "timeout writing register %x\n", reg); | ||
164 | |||
165 | mutex_unlock(&info->lock); | ||
166 | } | ||
167 | |||
168 | static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97) | ||
169 | { | ||
170 | struct ep93xx_ac97_info *info = ep93xx_ac97_info; | ||
171 | |||
172 | mutex_lock(&info->lock); | ||
173 | |||
174 | /* | ||
175 | * We are assuming that before this functions gets called, the codec | ||
176 | * BIT_CLK is stopped by forcing the codec into powerdown mode. We can | ||
177 | * control the SYNC signal directly via AC97SYNC register. Using | ||
178 | * TIMEDSYNC the controller will keep the SYNC high > 1us. | ||
179 | */ | ||
180 | ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC); | ||
181 | ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); | ||
182 | if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) | ||
183 | dev_warn(info->dev, "codec warm reset timeout\n"); | ||
184 | |||
185 | mutex_unlock(&info->lock); | ||
186 | } | ||
187 | |||
188 | static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97) | ||
189 | { | ||
190 | struct ep93xx_ac97_info *info = ep93xx_ac97_info; | ||
191 | |||
192 | mutex_lock(&info->lock); | ||
193 | |||
194 | /* | ||
195 | * For doing cold reset, we disable the AC97 controller interface, clear | ||
196 | * WINT and CODECREADY bits, and finally enable the interface again. | ||
197 | */ | ||
198 | ep93xx_ac97_write_reg(info, AC97GCR, 0); | ||
199 | ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT); | ||
200 | ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE); | ||
201 | |||
202 | /* | ||
203 | * Now, assert the reset and wait for the codec to become ready. | ||
204 | */ | ||
205 | ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET); | ||
206 | ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); | ||
207 | if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) | ||
208 | dev_warn(info->dev, "codec cold reset timeout\n"); | ||
209 | |||
210 | /* | ||
211 | * Give the codec some time to come fully out from the reset. This way | ||
212 | * we ensure that the subsequent reads/writes will work. | ||
213 | */ | ||
214 | usleep_range(15000, 20000); | ||
215 | |||
216 | mutex_unlock(&info->lock); | ||
217 | } | ||
218 | |||
219 | static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id) | ||
220 | { | ||
221 | struct ep93xx_ac97_info *info = dev_id; | ||
222 | unsigned status, mask; | ||
223 | |||
224 | /* | ||
225 | * Just mask out the interrupt and wake up the waiting thread. | ||
226 | * Interrupts are cleared via reading/writing to slot 1 & 2 registers by | ||
227 | * the waiting thread. | ||
228 | */ | ||
229 | status = ep93xx_ac97_read_reg(info, AC97GIS); | ||
230 | mask = ep93xx_ac97_read_reg(info, AC97IM); | ||
231 | mask &= ~status; | ||
232 | ep93xx_ac97_write_reg(info, AC97IM, mask); | ||
233 | |||
234 | complete(&info->done); | ||
235 | return IRQ_HANDLED; | ||
236 | } | ||
237 | |||
238 | struct snd_ac97_bus_ops soc_ac97_ops = { | ||
239 | .read = ep93xx_ac97_read, | ||
240 | .write = ep93xx_ac97_write, | ||
241 | .reset = ep93xx_ac97_cold_reset, | ||
242 | .warm_reset = ep93xx_ac97_warm_reset, | ||
243 | }; | ||
244 | EXPORT_SYMBOL_GPL(soc_ac97_ops); | ||
245 | |||
246 | static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream, | ||
247 | int cmd, struct snd_soc_dai *dai) | ||
248 | { | ||
249 | struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai); | ||
250 | unsigned v = 0; | ||
251 | |||
252 | switch (cmd) { | ||
253 | case SNDRV_PCM_TRIGGER_START: | ||
254 | case SNDRV_PCM_TRIGGER_RESUME: | ||
255 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | ||
256 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | ||
257 | /* | ||
258 | * Enable compact mode, TX slots 3 & 4, and the TX FIFO | ||
259 | * itself. | ||
260 | */ | ||
261 | v |= AC97TXCR_CM; | ||
262 | v |= AC97TXCR_TX3 | AC97TXCR_TX4; | ||
263 | v |= AC97TXCR_TEN; | ||
264 | ep93xx_ac97_write_reg(info, AC97TXCR(1), v); | ||
265 | } else { | ||
266 | /* | ||
267 | * Enable compact mode, RX slots 3 & 4, and the RX FIFO | ||
268 | * itself. | ||
269 | */ | ||
270 | v |= AC97RXCR_CM; | ||
271 | v |= AC97RXCR_RX3 | AC97RXCR_RX4; | ||
272 | v |= AC97RXCR_REN; | ||
273 | ep93xx_ac97_write_reg(info, AC97RXCR(1), v); | ||
274 | } | ||
275 | break; | ||
276 | |||
277 | case SNDRV_PCM_TRIGGER_STOP: | ||
278 | case SNDRV_PCM_TRIGGER_SUSPEND: | ||
279 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | ||
280 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | ||
281 | /* | ||
282 | * As per Cirrus EP93xx errata described below: | ||
283 | * | ||
284 | * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf | ||
285 | * | ||
286 | * we will wait for the TX FIFO to be empty before | ||
287 | * clearing the TEN bit. | ||
288 | */ | ||
289 | unsigned long timeout = jiffies + AC97_TIMEOUT; | ||
290 | |||
291 | do { | ||
292 | v = ep93xx_ac97_read_reg(info, AC97SR(1)); | ||
293 | if (time_after(jiffies, timeout)) { | ||
294 | dev_warn(info->dev, "TX timeout\n"); | ||
295 | break; | ||
296 | } | ||
297 | } while (!(v & (AC97SR_TXFE | AC97SR_TXUE))); | ||
298 | |||
299 | /* disable the TX FIFO */ | ||
300 | ep93xx_ac97_write_reg(info, AC97TXCR(1), 0); | ||
301 | } else { | ||
302 | /* disable the RX FIFO */ | ||
303 | ep93xx_ac97_write_reg(info, AC97RXCR(1), 0); | ||
304 | } | ||
305 | break; | ||
306 | |||
307 | default: | ||
308 | dev_warn(info->dev, "unknown command %d\n", cmd); | ||
309 | return -EINVAL; | ||
310 | } | ||
311 | |||
312 | return 0; | ||
313 | } | ||
314 | |||
315 | static int ep93xx_ac97_startup(struct snd_pcm_substream *substream, | ||
316 | struct snd_soc_dai *dai) | ||
317 | { | ||
318 | struct ep93xx_pcm_dma_params *dma_data; | ||
319 | |||
320 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | ||
321 | dma_data = &ep93xx_ac97_pcm_out; | ||
322 | else | ||
323 | dma_data = &ep93xx_ac97_pcm_in; | ||
324 | |||
325 | snd_soc_dai_set_dma_data(dai, substream, dma_data); | ||
326 | return 0; | ||
327 | } | ||
328 | |||
329 | static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = { | ||
330 | .startup = ep93xx_ac97_startup, | ||
331 | .trigger = ep93xx_ac97_trigger, | ||
332 | }; | ||
333 | |||
334 | static struct snd_soc_dai_driver ep93xx_ac97_dai = { | ||
335 | .name = "ep93xx-ac97", | ||
336 | .id = 0, | ||
337 | .ac97_control = 1, | ||
338 | .playback = { | ||
339 | .stream_name = "AC97 Playback", | ||
340 | .channels_min = 2, | ||
341 | .channels_max = 2, | ||
342 | .rates = SNDRV_PCM_RATE_8000_48000, | ||
343 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | ||
344 | }, | ||
345 | .capture = { | ||
346 | .stream_name = "AC97 Capture", | ||
347 | .channels_min = 2, | ||
348 | .channels_max = 2, | ||
349 | .rates = SNDRV_PCM_RATE_8000_48000, | ||
350 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | ||
351 | }, | ||
352 | .ops = &ep93xx_ac97_dai_ops, | ||
353 | }; | ||
354 | |||
355 | static int __devinit ep93xx_ac97_probe(struct platform_device *pdev) | ||
356 | { | ||
357 | struct ep93xx_ac97_info *info; | ||
358 | struct resource *res; | ||
359 | unsigned int irq; | ||
360 | int ret; | ||
361 | |||
362 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | ||
363 | if (!info) | ||
364 | return -ENOMEM; | ||
365 | |||
366 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
367 | if (!res) | ||
368 | return -ENODEV; | ||
369 | |||
370 | info->regs = devm_request_and_ioremap(&pdev->dev, res); | ||
371 | if (!info->regs) | ||
372 | return -ENXIO; | ||
373 | |||
374 | irq = platform_get_irq(pdev, 0); | ||
375 | if (!irq) | ||
376 | return -ENODEV; | ||
377 | |||
378 | ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt, | ||
379 | IRQF_TRIGGER_HIGH, pdev->name, info); | ||
380 | if (ret) | ||
381 | goto fail; | ||
382 | |||
383 | dev_set_drvdata(&pdev->dev, info); | ||
384 | |||
385 | mutex_init(&info->lock); | ||
386 | init_completion(&info->done); | ||
387 | info->dev = &pdev->dev; | ||
388 | |||
389 | ep93xx_ac97_info = info; | ||
390 | platform_set_drvdata(pdev, info); | ||
391 | |||
392 | ret = snd_soc_register_dai(&pdev->dev, &ep93xx_ac97_dai); | ||
393 | if (ret) | ||
394 | goto fail; | ||
395 | |||
396 | return 0; | ||
397 | |||
398 | fail: | ||
399 | platform_set_drvdata(pdev, NULL); | ||
400 | ep93xx_ac97_info = NULL; | ||
401 | dev_set_drvdata(&pdev->dev, NULL); | ||
402 | return ret; | ||
403 | } | ||
404 | |||
405 | static int __devexit ep93xx_ac97_remove(struct platform_device *pdev) | ||
406 | { | ||
407 | struct ep93xx_ac97_info *info = platform_get_drvdata(pdev); | ||
408 | |||
409 | snd_soc_unregister_dai(&pdev->dev); | ||
410 | |||
411 | /* disable the AC97 controller */ | ||
412 | ep93xx_ac97_write_reg(info, AC97GCR, 0); | ||
413 | |||
414 | platform_set_drvdata(pdev, NULL); | ||
415 | ep93xx_ac97_info = NULL; | ||
416 | dev_set_drvdata(&pdev->dev, NULL); | ||
417 | |||
418 | return 0; | ||
419 | } | ||
420 | |||
421 | static struct platform_driver ep93xx_ac97_driver = { | ||
422 | .probe = ep93xx_ac97_probe, | ||
423 | .remove = __devexit_p(ep93xx_ac97_remove), | ||
424 | .driver = { | ||
425 | .name = "ep93xx-ac97", | ||
426 | .owner = THIS_MODULE, | ||
427 | }, | ||
428 | }; | ||
429 | |||
430 | module_platform_driver(ep93xx_ac97_driver); | ||
431 | |||
432 | MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver"); | ||
433 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | ||
434 | MODULE_LICENSE("GPL"); | ||
435 | MODULE_ALIAS("platform:ep93xx-ac97"); | ||