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-rw-r--r--sound/soc/at91/at91-i2s.c673
1 files changed, 673 insertions, 0 deletions
diff --git a/sound/soc/at91/at91-i2s.c b/sound/soc/at91/at91-i2s.c
new file mode 100644
index 000000000000..b452e8e6a724
--- /dev/null
+++ b/sound/soc/at91/at91-i2s.c
@@ -0,0 +1,673 @@
1/*
2 * at91-i2s.c -- ALSA SoC I2S Audio Layer Platform driver
3 *
4 * Author: Frank Mandarino <fmandarino@endrelia.com>
5 * Endrelia Technologies Inc.
6 *
7 * Based on pxa2xx Platform drivers by
8 * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Revision history
16 * 3rd Mar 2006 Initial version.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/device.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <sound/driver.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/initval.h>
29#include <sound/soc.h>
30
31#include <asm/arch/hardware.h>
32#include <asm/arch/at91_pmc.h>
33#include <asm/arch/at91_ssc.h>
34#include <asm/arch/at91_pdc.h>
35
36#include "at91-pcm.h"
37
38#if 0
39#define DBG(x...) printk(KERN_DEBUG "at91-i2s:" x)
40#else
41#define DBG(x...)
42#endif
43
44#if defined(CONFIG_ARCH_AT91SAM9260)
45#define NUM_SSC_DEVICES 1
46#else
47#define NUM_SSC_DEVICES 3
48#endif
49
50
51#define AT91_I2S_DAIFMT \
52 (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF)
53
54#define AT91_I2S_DIR \
55 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
56
57/* priv is (SSC_CMR.DIV << 16 | SSC_TCMR.PERIOD ) */
58static struct snd_soc_dai_mode at91_i2s[] = {
59
60 /* 8k: BCLK = (MCLK/10) = (60MHz/50) = 1.2MHz */
61 {
62 .fmt = AT91_I2S_DAIFMT,
63 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
64 .pcmrate = SNDRV_PCM_RATE_8000,
65 .pcmdir = AT91_I2S_DIR,
66 .flags = SND_SOC_DAI_BFS_DIV,
67 .fs = 1500,
68 .bfs = SND_SOC_FSBD(10),
69 .priv = (25 << 16 | 74),
70 },
71
72 /* 16k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
73 {
74 .fmt = AT91_I2S_DAIFMT,
75 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
76 .pcmrate = SNDRV_PCM_RATE_16000,
77 .pcmdir = AT91_I2S_DIR,
78 .flags = SND_SOC_DAI_BFS_DIV,
79 .fs = 750,
80 .bfs = SND_SOC_FSBD(3),
81 .priv = (7 << 16 | 133),
82 },
83
84 /* 32k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
85 {
86 .fmt = AT91_I2S_DAIFMT,
87 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
88 .pcmrate = SNDRV_PCM_RATE_32000,
89 .pcmdir = AT91_I2S_DIR,
90 .flags = SND_SOC_DAI_BFS_DIV,
91 .fs = 375,
92 .bfs = SND_SOC_FSBD(3),
93 .priv = (7 << 16 | 66),
94 },
95
96 /* 48k: BCLK = (MCLK/5) ~= (60MHz/26) = 2.3076923MHz */
97 {
98 .fmt = AT91_I2S_DAIFMT,
99 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
100 .pcmrate = SNDRV_PCM_RATE_48000,
101 .pcmdir = AT91_I2S_DIR,
102 .flags = SND_SOC_DAI_BFS_DIV,
103 .fs = 250,
104 .bfs SND_SOC_FSBD(5),
105 .priv = (13 << 16 | 23),
106 },
107};
108
109
110/*
111 * SSC PDC registers required by the PCM DMA engine.
112 */
113static struct at91_pdc_regs pdc_tx_reg = {
114 .xpr = AT91_PDC_TPR,
115 .xcr = AT91_PDC_TCR,
116 .xnpr = AT91_PDC_TNPR,
117 .xncr = AT91_PDC_TNCR,
118};
119
120static struct at91_pdc_regs pdc_rx_reg = {
121 .xpr = AT91_PDC_RPR,
122 .xcr = AT91_PDC_RCR,
123 .xnpr = AT91_PDC_RNPR,
124 .xncr = AT91_PDC_RNCR,
125};
126
127/*
128 * SSC & PDC status bits for transmit and receive.
129 */
130static struct at91_ssc_mask ssc_tx_mask = {
131 .ssc_enable = AT91_SSC_TXEN,
132 .ssc_disable = AT91_SSC_TXDIS,
133 .ssc_endx = AT91_SSC_ENDTX,
134 .ssc_endbuf = AT91_SSC_TXBUFE,
135 .pdc_enable = AT91_PDC_TXTEN,
136 .pdc_disable = AT91_PDC_TXTDIS,
137};
138
139static struct at91_ssc_mask ssc_rx_mask = {
140 .ssc_enable = AT91_SSC_RXEN,
141 .ssc_disable = AT91_SSC_RXDIS,
142 .ssc_endx = AT91_SSC_ENDRX,
143 .ssc_endbuf = AT91_SSC_RXBUFF,
144 .pdc_enable = AT91_PDC_RXTEN,
145 .pdc_disable = AT91_PDC_RXTDIS,
146};
147
148
149/*
150 * DMA parameters.
151 */
152static struct at91_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
153 {{
154 .name = "SSC0/I2S PCM Stereo out",
155 .pdc = &pdc_tx_reg,
156 .mask = &ssc_tx_mask,
157 },
158 {
159 .name = "SSC0/I2S PCM Stereo in",
160 .pdc = &pdc_rx_reg,
161 .mask = &ssc_rx_mask,
162 }},
163#if NUM_SSC_DEVICES == 3
164 {{
165 .name = "SSC1/I2S PCM Stereo out",
166 .pdc = &pdc_tx_reg,
167 .mask = &ssc_tx_mask,
168 },
169 {
170 .name = "SSC1/I2S PCM Stereo in",
171 .pdc = &pdc_rx_reg,
172 .mask = &ssc_rx_mask,
173 }},
174 {{
175 .name = "SSC2/I2S PCM Stereo out",
176 .pdc = &pdc_tx_reg,
177 .mask = &ssc_tx_mask,
178 },
179 {
180 .name = "SSC1/I2S PCM Stereo in",
181 .pdc = &pdc_rx_reg,
182 .mask = &ssc_rx_mask,
183 }},
184#endif
185};
186
187
188/*
189 * A MUTEX is used to protect an SSC initialzed flag which allows
190 * the substream hw_params() call to initialize the SSC only if
191 * there are no other substreams open. If there are other
192 * substreams open, the hw_param() call can only check that
193 * it is using the same format and rate.
194 */
195static DECLARE_MUTEX(ssc0_mutex);
196#if NUM_SSC_DEVICES == 3
197static DECLARE_MUTEX(ssc1_mutex);
198static DECLARE_MUTEX(ssc2_mutex);
199#endif
200
201
202struct at91_ssc_state {
203 u32 ssc_cmr;
204 u32 ssc_rcmr;
205 u32 ssc_rfmr;
206 u32 ssc_tcmr;
207 u32 ssc_tfmr;
208 u32 ssc_sr;
209 u32 ssc_imr;
210};
211
212
213static struct at91_ssc_info {
214 char *name;
215 struct at91_ssc_periph ssc;
216 spinlock_t lock; /* lock for dir_mask */
217 int dir_mask; /* 0=unused, 1=playback, 2=capture */
218 struct semaphore *mutex;
219 int initialized;
220 int pcmfmt;
221 int rate;
222 struct at91_pcm_dma_params *dma_params[2];
223 struct at91_ssc_state ssc_state;
224
225} ssc_info[NUM_SSC_DEVICES] = {
226 {
227 .name = "ssc0",
228 .lock = SPIN_LOCK_UNLOCKED,
229 .dir_mask = 0,
230 .mutex = &ssc0_mutex,
231 .initialized = 0,
232 },
233#if NUM_SSC_DEVICES == 3
234 {
235 .name = "ssc1",
236 .lock = SPIN_LOCK_UNLOCKED,
237 .dir_mask = 0,
238 .mutex = &ssc1_mutex,
239 .initialized = 0,
240 },
241 {
242 .name = "ssc2",
243 .lock = SPIN_LOCK_UNLOCKED,
244 .dir_mask = 0,
245 .mutex = &ssc2_mutex,
246 .initialized = 0,
247 },
248#endif
249};
250
251
252static irqreturn_t at91_i2s_interrupt(int irq, void *dev_id)
253{
254 struct at91_ssc_info *ssc_p = dev_id;
255 struct at91_pcm_dma_params *dma_params;
256 u32 ssc_sr;
257 int i;
258
259 ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)
260 & at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
261
262 /*
263 * Loop through the substreams attached to this SSC. If
264 * a DMA-related interrupt occurred on that substream, call
265 * the DMA interrupt handler function, if one has been
266 * registered in the dma_params structure by the PCM driver.
267 */
268 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
269 dma_params = ssc_p->dma_params[i];
270
271 if (dma_params != NULL && dma_params->dma_intr_handler != NULL &&
272 (ssc_sr &
273 (dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf)))
274
275 dma_params->dma_intr_handler(ssc_sr, dma_params->substream);
276 }
277
278 return IRQ_HANDLED;
279}
280
281static int at91_i2s_startup(struct snd_pcm_substream *substream)
282{
283 struct snd_soc_pcm_runtime *rtd = substream->private_data;
284 struct at91_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
285 int dir_mask;
286
287 DBG("i2s_startup: SSC_SR=0x%08lx\n",
288 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
289 dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2;
290
291 spin_lock_irq(&ssc_p->lock);
292 if (ssc_p->dir_mask & dir_mask) {
293 spin_unlock_irq(&ssc_p->lock);
294 return -EBUSY;
295 }
296 ssc_p->dir_mask |= dir_mask;
297 spin_unlock_irq(&ssc_p->lock);
298
299 return 0;
300}
301
302static void at91_i2s_shutdown(struct snd_pcm_substream *substream)
303{
304 struct snd_soc_pcm_runtime *rtd = substream->private_data;
305 struct at91_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
306 struct at91_pcm_dma_params *dma_params = rtd->cpu_dai->dma_data;
307 int dir, dir_mask;
308
309 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
310
311 if (dma_params != NULL) {
312 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
313 dma_params->mask->ssc_disable);
314 DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"),
315 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
316
317 dma_params->ssc_base = NULL;
318 dma_params->substream = NULL;
319 ssc_p->dma_params[dir] = NULL;
320 }
321
322 dir_mask = 1 << dir;
323
324 spin_lock_irq(&ssc_p->lock);
325 ssc_p->dir_mask &= ~dir_mask;
326 if (!ssc_p->dir_mask) {
327 /* Shutdown the SSC clock. */
328 DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
329 at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid);
330
331 if (ssc_p->initialized)
332 free_irq(ssc_p->ssc.pid, ssc_p);
333
334 /* Reset the SSC */
335 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
336
337 /* Force a re-init on the next hw_params() call. */
338 ssc_p->initialized = 0;
339 }
340 spin_unlock_irq(&ssc_p->lock);
341}
342
343#ifdef CONFIG_PM
344static int at91_i2s_suspend(struct platform_device *pdev,
345 struct snd_soc_cpu_dai *dai)
346{
347 struct at91_ssc_info *ssc_p;
348
349 if(!dai->active)
350 return 0;
351
352 ssc_p = &ssc_info[dai->id];
353
354 /* Save the status register before disabling transmit and receive. */
355 ssc_p->state->ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR);
356 at91_ssc_write(ssc_p->ssc.base +
357 AT91_SSC_CR, AT91_SSC_TXDIS | AT91_SSC_RXDIS);
358
359 /* Save the current interrupt mask, then disable unmasked interrupts. */
360 ssc_p->state->ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
361 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->state->ssc_imr);
362
363 ssc_p->state->ssc_cmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR);
364 ssc_p->state->ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
365 ssc_p->state->ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
366 ssc_p->state->ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
367 ssc_p->state->ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
368
369 return 0;
370}
371
372static int at91_i2s_resume(struct platform_device *pdev,
373 struct snd_soc_cpu_dai *dai)
374{
375 struct at91_ssc_info *ssc_p;
376 u32 cr_mask;
377
378 if(!dai->active)
379 return 0;
380
381 ssc_p = &ssc_info[dai->id];
382
383 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->state->ssc_tfmr);
384 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->state->ssc_tcmr);
385 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->state->ssc_rfmr);
386 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->state->ssc_rcmr);
387 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->state->ssc_cmr);
388
389 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IER, ssc_p->state->ssc_imr);
390
391 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
392 ((ssc_p->state->ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) |
393 ((ssc_p->state->ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0));
394
395 return 0;
396}
397
398#else
399#define at91_i2s_suspend NULL
400#define at91_i2s_resume NULL
401#endif
402
403static unsigned int at91_i2s_config_sysclk(
404 struct snd_soc_cpu_dai *iface, struct snd_soc_clock_info *info,
405 unsigned int clk)
406{
407 /* Currently, there is only support for USB (12Mhz) mode */
408 if (clk != 12000000)
409 return 0;
410 return 12000000;
411}
412
413static int at91_i2s_hw_params(struct snd_pcm_substream *substream,
414 struct snd_pcm_hw_params *params)
415{
416 struct snd_soc_pcm_runtime *rtd = substream->private_data;
417 int id = rtd->cpu_dai->id;
418 struct at91_ssc_info *ssc_p = &ssc_info[id];
419 struct at91_pcm_dma_params *dma_params;
420 unsigned int pcmfmt, rate;
421 int dir, channels, bits;
422 struct clk *mck_clk;
423 u32 div, period, tfmr, rfmr, tcmr, rcmr;
424 int ret;
425
426 /*
427 * Currently, there is only one set of dma params for
428 * each direction. If more are added, this code will
429 * have to be changed to select the proper set.
430 */
431 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
432
433 dma_params = &ssc_dma_params[id][dir];
434 dma_params->ssc_base = ssc_p->ssc.base;
435 dma_params->substream = substream;
436
437 ssc_p->dma_params[dir] = dma_params;
438 rtd->cpu_dai->dma_data = dma_params;
439
440 rate = params_rate(params);
441 channels = params_channels(params);
442
443 pcmfmt = rtd->cpu_dai->dai_runtime.pcmfmt;
444 switch (pcmfmt) {
445 case SNDRV_PCM_FMTBIT_S16_LE:
446 /* likely this is all we'll ever support, but ... */
447 bits = 16;
448 dma_params->pdc_xfer_size = 2;
449 break;
450 default:
451 printk(KERN_WARNING "at91-i2s: unsupported format %x\n",
452 pcmfmt);
453 return -EINVAL;
454 }
455
456 /* Don't allow both SSC substreams to initialize at the same time. */
457 down(ssc_p->mutex);
458
459 /*
460 * If this SSC is alreadly initialized, then this substream must use
461 * the same format and rate.
462 */
463 if (ssc_p->initialized) {
464 if (pcmfmt != ssc_p->pcmfmt || rate != ssc_p->rate) {
465 printk(KERN_WARNING "at91-i2s: "
466 "incompatible substream in other direction\n");
467 up(ssc_p->mutex);
468 return -EINVAL;
469 }
470 } else {
471 /* Enable PMC peripheral clock for this SSC */
472 DBG("Starting pid %d clock\n", ssc_p->ssc.pid);
473 at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
474
475 /* Reset the SSC */
476 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
477
478 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RPR, 0);
479 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RCR, 0);
480 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RNPR, 0);
481 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_RNCR, 0);
482 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TPR, 0);
483 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TCR, 0);
484 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TNPR, 0);
485 at91_ssc_write(ssc_p->ssc.base + AT91_PDC_TNCR, 0);
486
487 div = rtd->cpu_dai->dai_runtime.priv >> 16;
488 period = rtd->cpu_dai->dai_runtime.priv & 0xffff;
489
490 mck_clk = clk_get(NULL, "mck");
491
492 DBG("mck %lu fsbd %u bfs %llu bfs_real %u bclk %lu div %u period %u\n",
493 clk_get_rate(mck_clk),
494 SND_SOC_FSBD(6),
495 rtd->cpu_dai->dai_runtime.bfs,
496 SND_SOC_FSBD_REAL(rtd->cpu_dai->dai_runtime.bfs),
497 clk_get_rate(mck_clk) / (2 * div),
498 div,
499 period);
500
501 clk_put(mck_clk);
502
503 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, div);
504
505 /*
506 * Setup the TFMR and RFMR for the proper data format.
507 */
508 tfmr =
509 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
510 | (( 0 << 23) & AT91_SSC_FSDEN)
511 | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
512 | (((bits - 1) << 16) & AT91_SSC_FSLEN)
513 | (((channels - 1) << 8) & AT91_SSC_DATNB)
514 | (( 1 << 7) & AT91_SSC_MSBF)
515 | (( 0 << 5) & AT91_SSC_DATDEF)
516 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
517 DBG("SSC_TFMR=0x%08x\n", tfmr);
518 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr);
519
520 rfmr =
521 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
522 | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
523 | (( 0 << 16) & AT91_SSC_FSLEN)
524 | (((channels - 1) << 8) & AT91_SSC_DATNB)
525 | (( 1 << 7) & AT91_SSC_MSBF)
526 | (( 0 << 5) & AT91_SSC_LOOP)
527 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
528
529 DBG("SSC_RFMR=0x%08x\n", rfmr);
530 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr);
531
532 /*
533 * Setup the TCMR and RCMR to generate the proper BCLK
534 * and LRC signals.
535 */
536 tcmr =
537 (( period << 24) & AT91_SSC_PERIOD)
538 | (( 1 << 16) & AT91_SSC_STTDLY)
539 | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
540 | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
541 | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
542 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
543
544 DBG("SSC_TCMR=0x%08x\n", tcmr);
545 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr);
546
547 rcmr =
548 (( 0 << 24) & AT91_SSC_PERIOD)
549 | (( 1 << 16) & AT91_SSC_STTDLY)
550 | (( AT91_SSC_START_TX_RX ) & AT91_SSC_START)
551 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
552 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
553 | (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS);
554
555 DBG("SSC_RCMR=0x%08x\n", rcmr);
556 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr);
557
558 if ((ret = request_irq(ssc_p->ssc.pid, at91_i2s_interrupt,
559 0, ssc_p->name, ssc_p)) < 0) {
560 printk(KERN_WARNING "at91-i2s: request_irq failure\n");
561 return ret;
562 }
563
564 /*
565 * Save the current substream parameters in order to check
566 * that the substream in the opposite direction uses the
567 * same parameters.
568 */
569 ssc_p->pcmfmt = pcmfmt;
570 ssc_p->rate = rate;
571 ssc_p->initialized = 1;
572
573 DBG("hw_params: SSC initialized\n");
574 }
575
576 up(ssc_p->mutex);
577
578 return 0;
579}
580
581
582static int at91_i2s_prepare(struct snd_pcm_substream *substream)
583{
584 struct snd_soc_pcm_runtime *rtd = substream->private_data;
585 struct at91_pcm_dma_params *dma_params = rtd->cpu_dai->dma_data;
586
587 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
588 dma_params->mask->ssc_enable);
589
590 DBG("%s enabled SSC_SR=0x%08lx\n",
591 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "transmit" : "receive",
592 at91_ssc_read(ssc_info[rtd->cpu_dai->id].ssc.base + AT91_SSC_SR));
593 return 0;
594}
595
596
597struct snd_soc_cpu_dai at91_i2s_dai[NUM_SSC_DEVICES] = {
598 { .name = "at91_ssc0/i2s",
599 .id = 0,
600 .type = SND_SOC_DAI_I2S,
601 .suspend = at91_i2s_suspend,
602 .resume = at91_i2s_resume,
603 .config_sysclk = at91_i2s_config_sysclk,
604 .playback = {
605 .channels_min = 1,
606 .channels_max = 2,},
607 .capture = {
608 .channels_min = 1,
609 .channels_max = 2,},
610 .ops = {
611 .startup = at91_i2s_startup,
612 .shutdown = at91_i2s_shutdown,
613 .prepare = at91_i2s_prepare,
614 .hw_params = at91_i2s_hw_params,},
615 .caps = {
616 .mode = &at91_i2s[0],
617 .num_modes = ARRAY_SIZE(at91_i2s),},
618 .private_data = &ssc_info[0].ssc,
619 },
620#if NUM_SSC_DEVICES == 3
621 { .name = "at91_ssc1/i2s",
622 .id = 1,
623 .type = SND_SOC_DAI_I2S,
624 .suspend = at91_i2s_suspend,
625 .resume = at91_i2s_resume,
626 .config_sysclk = at91_i2s_config_sysclk,
627 .playback = {
628 .channels_min = 1,
629 .channels_max = 2,},
630 .capture = {
631 .channels_min = 1,
632 .channels_max = 2,},
633 .ops = {
634 .startup = at91_i2s_startup,
635 .shutdown = at91_i2s_shutdown,
636 .prepare = at91_i2s_prepare,
637 .hw_params = at91_i2s_hw_params,},
638 .caps = {
639 .mode = &at91_i2s[0],
640 .num_modes = ARRAY_SIZE(at91_i2s),},
641 .private_data = &ssc_info[1].ssc,
642 },
643 { .name = "at91_ssc2/i2s",
644 .id = 2,
645 .type = SND_SOC_DAI_I2S,
646 .suspend = at91_i2s_suspend,
647 .resume = at91_i2s_resume,
648 .config_sysclk = at91_i2s_config_sysclk,
649 .playback = {
650 .channels_min = 1,
651 .channels_max = 2,},
652 .capture = {
653 .channels_min = 1,
654 .channels_max = 2,},
655 .ops = {
656 .startup = at91_i2s_startup,
657 .shutdown = at91_i2s_shutdown,
658 .prepare = at91_i2s_prepare,
659 .hw_params = at91_i2s_hw_params,},
660 .caps = {
661 .mode = &at91_i2s[0],
662 .num_modes = ARRAY_SIZE(at91_i2s),},
663 .private_data = &ssc_info[2].ssc,
664 },
665#endif
666};
667
668EXPORT_SYMBOL_GPL(at91_i2s_dai);
669
670/* Module information */
671MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
672MODULE_DESCRIPTION("AT91 I2S ASoC Interface");
673MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 13:50:38 -0500