diff options
Diffstat (limited to 'sound/pci')
-rw-r--r-- | sound/pci/hda/hda_codec.c | 2 | ||||
-rw-r--r-- | sound/pci/hda/hda_codec.h | 2 | ||||
-rw-r--r-- | sound/pci/hda/hda_intel.c | 103 | ||||
-rw-r--r-- | sound/pci/hda/patch_realtek.c | 4 | ||||
-rw-r--r-- | sound/pci/hda/patch_sigmatel.c | 9 |
5 files changed, 86 insertions, 34 deletions
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index 88480c0c58a0..c7df01b72cac 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c | |||
@@ -174,7 +174,7 @@ static int codec_exec_verb(struct hda_codec *codec, unsigned int cmd, | |||
174 | mutex_lock(&bus->cmd_mutex); | 174 | mutex_lock(&bus->cmd_mutex); |
175 | err = bus->ops.command(bus, cmd); | 175 | err = bus->ops.command(bus, cmd); |
176 | if (!err && res) | 176 | if (!err && res) |
177 | *res = bus->ops.get_response(bus); | 177 | *res = bus->ops.get_response(bus, codec->addr); |
178 | mutex_unlock(&bus->cmd_mutex); | 178 | mutex_unlock(&bus->cmd_mutex); |
179 | snd_hda_power_down(codec); | 179 | snd_hda_power_down(codec); |
180 | if (res && *res == -1 && bus->rirb_error) { | 180 | if (res && *res == -1 && bus->rirb_error) { |
diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h index cad79efaabc9..1b75f28ed092 100644 --- a/sound/pci/hda/hda_codec.h +++ b/sound/pci/hda/hda_codec.h | |||
@@ -568,7 +568,7 @@ struct hda_bus_ops { | |||
568 | /* send a single command */ | 568 | /* send a single command */ |
569 | int (*command)(struct hda_bus *bus, unsigned int cmd); | 569 | int (*command)(struct hda_bus *bus, unsigned int cmd); |
570 | /* get a response from the last command */ | 570 | /* get a response from the last command */ |
571 | unsigned int (*get_response)(struct hda_bus *bus); | 571 | unsigned int (*get_response)(struct hda_bus *bus, unsigned int addr); |
572 | /* free the private data */ | 572 | /* free the private data */ |
573 | void (*private_free)(struct hda_bus *); | 573 | void (*private_free)(struct hda_bus *); |
574 | /* attach a PCM stream */ | 574 | /* attach a PCM stream */ |
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 77c1b840ca8b..175f07a381ba 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c | |||
@@ -253,7 +253,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |||
253 | 253 | ||
254 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ | 254 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ |
255 | #define AZX_MAX_CODECS 4 | 255 | #define AZX_MAX_CODECS 4 |
256 | #define STATESTS_INT_MASK 0x0f | 256 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
257 | 257 | ||
258 | /* SD_CTL bits */ | 258 | /* SD_CTL bits */ |
259 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | 259 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ |
@@ -361,8 +361,8 @@ struct azx_rb { | |||
361 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | 361 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ |
362 | /* for RIRB */ | 362 | /* for RIRB */ |
363 | unsigned short rp, wp; /* read/write pointers */ | 363 | unsigned short rp, wp; /* read/write pointers */ |
364 | int cmds; /* number of pending requests */ | 364 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ |
365 | u32 res; /* last read value */ | 365 | u32 res[AZX_MAX_CODECS]; /* last read value */ |
366 | }; | 366 | }; |
367 | 367 | ||
368 | struct azx { | 368 | struct azx { |
@@ -418,7 +418,7 @@ struct azx { | |||
418 | unsigned int probing :1; /* codec probing phase */ | 418 | unsigned int probing :1; /* codec probing phase */ |
419 | 419 | ||
420 | /* for debugging */ | 420 | /* for debugging */ |
421 | unsigned int last_cmd; /* last issued command (to sync) */ | 421 | unsigned int last_cmd[AZX_MAX_CODECS]; |
422 | 422 | ||
423 | /* for pending irqs */ | 423 | /* for pending irqs */ |
424 | struct work_struct irq_pending_work; | 424 | struct work_struct irq_pending_work; |
@@ -513,6 +513,7 @@ static int azx_alloc_cmd_io(struct azx *chip) | |||
513 | 513 | ||
514 | static void azx_init_cmd_io(struct azx *chip) | 514 | static void azx_init_cmd_io(struct azx *chip) |
515 | { | 515 | { |
516 | spin_lock_irq(&chip->reg_lock); | ||
516 | /* CORB set up */ | 517 | /* CORB set up */ |
517 | chip->corb.addr = chip->rb.addr; | 518 | chip->corb.addr = chip->rb.addr; |
518 | chip->corb.buf = (u32 *)chip->rb.area; | 519 | chip->corb.buf = (u32 *)chip->rb.area; |
@@ -531,7 +532,8 @@ static void azx_init_cmd_io(struct azx *chip) | |||
531 | /* RIRB set up */ | 532 | /* RIRB set up */ |
532 | chip->rirb.addr = chip->rb.addr + 2048; | 533 | chip->rirb.addr = chip->rb.addr + 2048; |
533 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | 534 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); |
534 | chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0; | 535 | chip->rirb.wp = chip->rirb.rp = 0; |
536 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | ||
535 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | 537 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
536 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); | 538 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); |
537 | 539 | ||
@@ -543,30 +545,60 @@ static void azx_init_cmd_io(struct azx *chip) | |||
543 | azx_writew(chip, RINTCNT, 1); | 545 | azx_writew(chip, RINTCNT, 1); |
544 | /* enable rirb dma and response irq */ | 546 | /* enable rirb dma and response irq */ |
545 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | 547 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
548 | spin_unlock_irq(&chip->reg_lock); | ||
546 | } | 549 | } |
547 | 550 | ||
548 | static void azx_free_cmd_io(struct azx *chip) | 551 | static void azx_free_cmd_io(struct azx *chip) |
549 | { | 552 | { |
553 | spin_lock_irq(&chip->reg_lock); | ||
550 | /* disable ringbuffer DMAs */ | 554 | /* disable ringbuffer DMAs */ |
551 | azx_writeb(chip, RIRBCTL, 0); | 555 | azx_writeb(chip, RIRBCTL, 0); |
552 | azx_writeb(chip, CORBCTL, 0); | 556 | azx_writeb(chip, CORBCTL, 0); |
557 | spin_unlock_irq(&chip->reg_lock); | ||
558 | } | ||
559 | |||
560 | static unsigned int azx_command_addr(u32 cmd) | ||
561 | { | ||
562 | unsigned int addr = cmd >> 28; | ||
563 | |||
564 | if (addr >= AZX_MAX_CODECS) { | ||
565 | snd_BUG(); | ||
566 | addr = 0; | ||
567 | } | ||
568 | |||
569 | return addr; | ||
570 | } | ||
571 | |||
572 | static unsigned int azx_response_addr(u32 res) | ||
573 | { | ||
574 | unsigned int addr = res & 0xf; | ||
575 | |||
576 | if (addr >= AZX_MAX_CODECS) { | ||
577 | snd_BUG(); | ||
578 | addr = 0; | ||
579 | } | ||
580 | |||
581 | return addr; | ||
553 | } | 582 | } |
554 | 583 | ||
555 | /* send a command */ | 584 | /* send a command */ |
556 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) | 585 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) |
557 | { | 586 | { |
558 | struct azx *chip = bus->private_data; | 587 | struct azx *chip = bus->private_data; |
588 | unsigned int addr = azx_command_addr(val); | ||
559 | unsigned int wp; | 589 | unsigned int wp; |
560 | 590 | ||
591 | spin_lock_irq(&chip->reg_lock); | ||
592 | |||
561 | /* add command to corb */ | 593 | /* add command to corb */ |
562 | wp = azx_readb(chip, CORBWP); | 594 | wp = azx_readb(chip, CORBWP); |
563 | wp++; | 595 | wp++; |
564 | wp %= ICH6_MAX_CORB_ENTRIES; | 596 | wp %= ICH6_MAX_CORB_ENTRIES; |
565 | 597 | ||
566 | spin_lock_irq(&chip->reg_lock); | 598 | chip->rirb.cmds[addr]++; |
567 | chip->rirb.cmds++; | ||
568 | chip->corb.buf[wp] = cpu_to_le32(val); | 599 | chip->corb.buf[wp] = cpu_to_le32(val); |
569 | azx_writel(chip, CORBWP, wp); | 600 | azx_writel(chip, CORBWP, wp); |
601 | |||
570 | spin_unlock_irq(&chip->reg_lock); | 602 | spin_unlock_irq(&chip->reg_lock); |
571 | 603 | ||
572 | return 0; | 604 | return 0; |
@@ -578,13 +610,14 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) | |||
578 | static void azx_update_rirb(struct azx *chip) | 610 | static void azx_update_rirb(struct azx *chip) |
579 | { | 611 | { |
580 | unsigned int rp, wp; | 612 | unsigned int rp, wp; |
613 | unsigned int addr; | ||
581 | u32 res, res_ex; | 614 | u32 res, res_ex; |
582 | 615 | ||
583 | wp = azx_readb(chip, RIRBWP); | 616 | wp = azx_readb(chip, RIRBWP); |
584 | if (wp == chip->rirb.wp) | 617 | if (wp == chip->rirb.wp) |
585 | return; | 618 | return; |
586 | chip->rirb.wp = wp; | 619 | chip->rirb.wp = wp; |
587 | 620 | ||
588 | while (chip->rirb.rp != wp) { | 621 | while (chip->rirb.rp != wp) { |
589 | chip->rirb.rp++; | 622 | chip->rirb.rp++; |
590 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | 623 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; |
@@ -592,18 +625,24 @@ static void azx_update_rirb(struct azx *chip) | |||
592 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | 625 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ |
593 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | 626 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); |
594 | res = le32_to_cpu(chip->rirb.buf[rp]); | 627 | res = le32_to_cpu(chip->rirb.buf[rp]); |
628 | addr = azx_response_addr(res_ex); | ||
595 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | 629 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
596 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | 630 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); |
597 | else if (chip->rirb.cmds) { | 631 | else if (chip->rirb.cmds[addr]) { |
598 | chip->rirb.res = res; | 632 | chip->rirb.res[addr] = res; |
599 | smp_wmb(); | 633 | smp_wmb(); |
600 | chip->rirb.cmds--; | 634 | chip->rirb.cmds[addr]--; |
601 | } | 635 | } else |
636 | snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " | ||
637 | "last cmd=%#08x\n", | ||
638 | res, res_ex, | ||
639 | chip->last_cmd[addr]); | ||
602 | } | 640 | } |
603 | } | 641 | } |
604 | 642 | ||
605 | /* receive a response */ | 643 | /* receive a response */ |
606 | static unsigned int azx_rirb_get_response(struct hda_bus *bus) | 644 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, |
645 | unsigned int addr) | ||
607 | { | 646 | { |
608 | struct azx *chip = bus->private_data; | 647 | struct azx *chip = bus->private_data; |
609 | unsigned long timeout; | 648 | unsigned long timeout; |
@@ -616,10 +655,10 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus) | |||
616 | azx_update_rirb(chip); | 655 | azx_update_rirb(chip); |
617 | spin_unlock_irq(&chip->reg_lock); | 656 | spin_unlock_irq(&chip->reg_lock); |
618 | } | 657 | } |
619 | if (!chip->rirb.cmds) { | 658 | if (!chip->rirb.cmds[addr]) { |
620 | smp_rmb(); | 659 | smp_rmb(); |
621 | bus->rirb_error = 0; | 660 | bus->rirb_error = 0; |
622 | return chip->rirb.res; /* the last value */ | 661 | return chip->rirb.res[addr]; /* the last value */ |
623 | } | 662 | } |
624 | if (time_after(jiffies, timeout)) | 663 | if (time_after(jiffies, timeout)) |
625 | break; | 664 | break; |
@@ -633,7 +672,8 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus) | |||
633 | 672 | ||
634 | if (chip->msi) { | 673 | if (chip->msi) { |
635 | snd_printk(KERN_WARNING SFX "No response from codec, " | 674 | snd_printk(KERN_WARNING SFX "No response from codec, " |
636 | "disabling MSI: last cmd=0x%08x\n", chip->last_cmd); | 675 | "disabling MSI: last cmd=0x%08x\n", |
676 | chip->last_cmd[addr]); | ||
637 | free_irq(chip->irq, chip); | 677 | free_irq(chip->irq, chip); |
638 | chip->irq = -1; | 678 | chip->irq = -1; |
639 | pci_disable_msi(chip->pci); | 679 | pci_disable_msi(chip->pci); |
@@ -648,7 +688,7 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus) | |||
648 | if (!chip->polling_mode) { | 688 | if (!chip->polling_mode) { |
649 | snd_printk(KERN_WARNING SFX "azx_get_response timeout, " | 689 | snd_printk(KERN_WARNING SFX "azx_get_response timeout, " |
650 | "switching to polling mode: last cmd=0x%08x\n", | 690 | "switching to polling mode: last cmd=0x%08x\n", |
651 | chip->last_cmd); | 691 | chip->last_cmd[addr]); |
652 | chip->polling_mode = 1; | 692 | chip->polling_mode = 1; |
653 | goto again; | 693 | goto again; |
654 | } | 694 | } |
@@ -672,7 +712,7 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus) | |||
672 | 712 | ||
673 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | 713 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " |
674 | "switching to single_cmd mode: last cmd=0x%08x\n", | 714 | "switching to single_cmd mode: last cmd=0x%08x\n", |
675 | chip->last_cmd); | 715 | chip->last_cmd[addr]); |
676 | chip->single_cmd = 1; | 716 | chip->single_cmd = 1; |
677 | bus->response_reset = 0; | 717 | bus->response_reset = 0; |
678 | /* re-initialize CORB/RIRB */ | 718 | /* re-initialize CORB/RIRB */ |
@@ -692,7 +732,7 @@ static unsigned int azx_rirb_get_response(struct hda_bus *bus) | |||
692 | */ | 732 | */ |
693 | 733 | ||
694 | /* receive a response */ | 734 | /* receive a response */ |
695 | static int azx_single_wait_for_response(struct azx *chip) | 735 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
696 | { | 736 | { |
697 | int timeout = 50; | 737 | int timeout = 50; |
698 | 738 | ||
@@ -700,7 +740,7 @@ static int azx_single_wait_for_response(struct azx *chip) | |||
700 | /* check IRV busy bit */ | 740 | /* check IRV busy bit */ |
701 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | 741 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { |
702 | /* reuse rirb.res as the response return value */ | 742 | /* reuse rirb.res as the response return value */ |
703 | chip->rirb.res = azx_readl(chip, IR); | 743 | chip->rirb.res[addr] = azx_readl(chip, IR); |
704 | return 0; | 744 | return 0; |
705 | } | 745 | } |
706 | udelay(1); | 746 | udelay(1); |
@@ -708,7 +748,7 @@ static int azx_single_wait_for_response(struct azx *chip) | |||
708 | if (printk_ratelimit()) | 748 | if (printk_ratelimit()) |
709 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", | 749 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", |
710 | azx_readw(chip, IRS)); | 750 | azx_readw(chip, IRS)); |
711 | chip->rirb.res = -1; | 751 | chip->rirb.res[addr] = -1; |
712 | return -EIO; | 752 | return -EIO; |
713 | } | 753 | } |
714 | 754 | ||
@@ -716,6 +756,7 @@ static int azx_single_wait_for_response(struct azx *chip) | |||
716 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) | 756 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) |
717 | { | 757 | { |
718 | struct azx *chip = bus->private_data; | 758 | struct azx *chip = bus->private_data; |
759 | unsigned int addr = azx_command_addr(val); | ||
719 | int timeout = 50; | 760 | int timeout = 50; |
720 | 761 | ||
721 | bus->rirb_error = 0; | 762 | bus->rirb_error = 0; |
@@ -728,7 +769,7 @@ static int azx_single_send_cmd(struct hda_bus *bus, u32 val) | |||
728 | azx_writel(chip, IC, val); | 769 | azx_writel(chip, IC, val); |
729 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | 770 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
730 | ICH6_IRS_BUSY); | 771 | ICH6_IRS_BUSY); |
731 | return azx_single_wait_for_response(chip); | 772 | return azx_single_wait_for_response(chip, addr); |
732 | } | 773 | } |
733 | udelay(1); | 774 | udelay(1); |
734 | } | 775 | } |
@@ -739,10 +780,11 @@ static int azx_single_send_cmd(struct hda_bus *bus, u32 val) | |||
739 | } | 780 | } |
740 | 781 | ||
741 | /* receive a response */ | 782 | /* receive a response */ |
742 | static unsigned int azx_single_get_response(struct hda_bus *bus) | 783 | static unsigned int azx_single_get_response(struct hda_bus *bus, |
784 | unsigned int addr) | ||
743 | { | 785 | { |
744 | struct azx *chip = bus->private_data; | 786 | struct azx *chip = bus->private_data; |
745 | return chip->rirb.res; | 787 | return chip->rirb.res[addr]; |
746 | } | 788 | } |
747 | 789 | ||
748 | /* | 790 | /* |
@@ -757,7 +799,7 @@ static int azx_send_cmd(struct hda_bus *bus, unsigned int val) | |||
757 | { | 799 | { |
758 | struct azx *chip = bus->private_data; | 800 | struct azx *chip = bus->private_data; |
759 | 801 | ||
760 | chip->last_cmd = val; | 802 | chip->last_cmd[azx_command_addr(val)] = val; |
761 | if (chip->single_cmd) | 803 | if (chip->single_cmd) |
762 | return azx_single_send_cmd(bus, val); | 804 | return azx_single_send_cmd(bus, val); |
763 | else | 805 | else |
@@ -765,13 +807,14 @@ static int azx_send_cmd(struct hda_bus *bus, unsigned int val) | |||
765 | } | 807 | } |
766 | 808 | ||
767 | /* get a response */ | 809 | /* get a response */ |
768 | static unsigned int azx_get_response(struct hda_bus *bus) | 810 | static unsigned int azx_get_response(struct hda_bus *bus, |
811 | unsigned int addr) | ||
769 | { | 812 | { |
770 | struct azx *chip = bus->private_data; | 813 | struct azx *chip = bus->private_data; |
771 | if (chip->single_cmd) | 814 | if (chip->single_cmd) |
772 | return azx_single_get_response(bus); | 815 | return azx_single_get_response(bus, addr); |
773 | else | 816 | else |
774 | return azx_rirb_get_response(bus); | 817 | return azx_rirb_get_response(bus, addr); |
775 | } | 818 | } |
776 | 819 | ||
777 | #ifdef CONFIG_SND_HDA_POWER_SAVE | 820 | #ifdef CONFIG_SND_HDA_POWER_SAVE |
@@ -1243,10 +1286,12 @@ static int probe_codec(struct azx *chip, int addr) | |||
1243 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | 1286 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; |
1244 | unsigned int res; | 1287 | unsigned int res; |
1245 | 1288 | ||
1289 | mutex_lock(&chip->bus->cmd_mutex); | ||
1246 | chip->probing = 1; | 1290 | chip->probing = 1; |
1247 | azx_send_cmd(chip->bus, cmd); | 1291 | azx_send_cmd(chip->bus, cmd); |
1248 | res = azx_get_response(chip->bus); | 1292 | res = azx_get_response(chip->bus, addr); |
1249 | chip->probing = 0; | 1293 | chip->probing = 0; |
1294 | mutex_unlock(&chip->bus->cmd_mutex); | ||
1250 | if (res == -1) | 1295 | if (res == -1) |
1251 | return -EIO; | 1296 | return -EIO; |
1252 | snd_printdd(SFX "codec #%d probed OK\n", addr); | 1297 | snd_printdd(SFX "codec #%d probed OK\n", addr); |
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index b95df5d5dcc2..51c44fdbc0f0 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c | |||
@@ -559,7 +559,7 @@ static int alc_pin_mode_get(struct snd_kcontrol *kcontrol, | |||
559 | 559 | ||
560 | /* Find enumerated value for current pinctl setting */ | 560 | /* Find enumerated value for current pinctl setting */ |
561 | i = alc_pin_mode_min(dir); | 561 | i = alc_pin_mode_min(dir); |
562 | while (alc_pin_mode_values[i] != pinctl && i <= alc_pin_mode_max(dir)) | 562 | while (i <= alc_pin_mode_max(dir) && alc_pin_mode_values[i] != pinctl) |
563 | i++; | 563 | i++; |
564 | *valp = i <= alc_pin_mode_max(dir) ? i: alc_pin_mode_min(dir); | 564 | *valp = i <= alc_pin_mode_max(dir) ? i: alc_pin_mode_min(dir); |
565 | return 0; | 565 | return 0; |
@@ -15157,7 +15157,7 @@ static struct snd_pci_quirk alc861vd_cfg_tbl[] = { | |||
15157 | SND_PCI_QUIRK(0x10de, 0x03f0, "Realtek ALC660 demo", ALC660VD_3ST), | 15157 | SND_PCI_QUIRK(0x10de, 0x03f0, "Realtek ALC660 demo", ALC660VD_3ST), |
15158 | SND_PCI_QUIRK(0x1179, 0xff00, "Toshiba A135", ALC861VD_LENOVO), | 15158 | SND_PCI_QUIRK(0x1179, 0xff00, "Toshiba A135", ALC861VD_LENOVO), |
15159 | /*SND_PCI_QUIRK(0x1179, 0xff00, "DALLAS", ALC861VD_DALLAS),*/ /*lenovo*/ | 15159 | /*SND_PCI_QUIRK(0x1179, 0xff00, "DALLAS", ALC861VD_DALLAS),*/ /*lenovo*/ |
15160 | SND_PCI_QUIRK(0x1179, 0xff01, "DALLAS", ALC861VD_DALLAS), | 15160 | SND_PCI_QUIRK(0x1179, 0xff01, "Toshiba A135", ALC861VD_LENOVO), |
15161 | SND_PCI_QUIRK(0x1179, 0xff03, "Toshiba P205", ALC861VD_LENOVO), | 15161 | SND_PCI_QUIRK(0x1179, 0xff03, "Toshiba P205", ALC861VD_LENOVO), |
15162 | SND_PCI_QUIRK(0x1179, 0xff31, "Toshiba L30-149", ALC861VD_DALLAS), | 15162 | SND_PCI_QUIRK(0x1179, 0xff31, "Toshiba L30-149", ALC861VD_DALLAS), |
15163 | SND_PCI_QUIRK(0x1565, 0x820d, "Biostar NF61S SE", ALC861VD_6ST_DIG), | 15163 | SND_PCI_QUIRK(0x1565, 0x820d, "Biostar NF61S SE", ALC861VD_6ST_DIG), |
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 5383d8cff88b..456ef6ac12e4 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c | |||
@@ -2266,7 +2266,7 @@ static struct snd_pci_quirk stac927x_cfg_tbl[] = { | |||
2266 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f3, "Dell Inspiron 1420", STAC_DELL_BIOS), | 2266 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f3, "Dell Inspiron 1420", STAC_DELL_BIOS), |
2267 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0227, "Dell Vostro 1400 ", STAC_DELL_BIOS), | 2267 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0227, "Dell Vostro 1400 ", STAC_DELL_BIOS), |
2268 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022e, "Dell ", STAC_DELL_BIOS), | 2268 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022e, "Dell ", STAC_DELL_BIOS), |
2269 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell Inspiron 1525", STAC_DELL_3ST), | 2269 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell Inspiron 1525", STAC_DELL_BIOS), |
2270 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0242, "Dell ", STAC_DELL_BIOS), | 2270 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0242, "Dell ", STAC_DELL_BIOS), |
2271 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0243, "Dell ", STAC_DELL_BIOS), | 2271 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0243, "Dell ", STAC_DELL_BIOS), |
2272 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ff, "Dell ", STAC_DELL_BIOS), | 2272 | SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ff, "Dell ", STAC_DELL_BIOS), |
@@ -5645,6 +5645,13 @@ static int patch_stac927x(struct hda_codec *codec) | |||
5645 | /* GPIO2 High = Enable EAPD */ | 5645 | /* GPIO2 High = Enable EAPD */ |
5646 | spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x04; | 5646 | spec->eapd_mask = spec->gpio_mask = spec->gpio_dir = 0x04; |
5647 | spec->gpio_data = 0x04; | 5647 | spec->gpio_data = 0x04; |
5648 | switch (codec->subsystem_id) { | ||
5649 | case 0x1028022f: | ||
5650 | /* correct EAPD to be GPIO0 */ | ||
5651 | spec->eapd_mask = spec->gpio_mask = 0x01; | ||
5652 | spec->gpio_dir = spec->gpio_data = 0x01; | ||
5653 | break; | ||
5654 | }; | ||
5648 | spec->dmic_nids = stac927x_dmic_nids; | 5655 | spec->dmic_nids = stac927x_dmic_nids; |
5649 | spec->num_dmics = STAC927X_NUM_DMICS; | 5656 | spec->num_dmics = STAC927X_NUM_DMICS; |
5650 | 5657 | ||