diff options
Diffstat (limited to 'sound/pci')
-rw-r--r-- | sound/pci/Kconfig | 10 | ||||
-rw-r--r-- | sound/pci/Makefile | 1 | ||||
-rw-r--r-- | sound/pci/lx6464es/Makefile | 2 | ||||
-rw-r--r-- | sound/pci/lx6464es/lx6464es.c | 1152 | ||||
-rw-r--r-- | sound/pci/lx6464es/lx6464es.h | 114 | ||||
-rw-r--r-- | sound/pci/lx6464es/lx_core.c | 1442 | ||||
-rw-r--r-- | sound/pci/lx6464es/lx_core.h | 242 | ||||
-rw-r--r-- | sound/pci/lx6464es/lx_defs.h | 376 |
8 files changed, 3339 insertions, 0 deletions
diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig index 93422e3a3f0c..e912b70b6f9c 100644 --- a/sound/pci/Kconfig +++ b/sound/pci/Kconfig | |||
@@ -622,6 +622,16 @@ config SND_KORG1212 | |||
622 | To compile this driver as a module, choose M here: the module | 622 | To compile this driver as a module, choose M here: the module |
623 | will be called snd-korg1212. | 623 | will be called snd-korg1212. |
624 | 624 | ||
625 | config SND_LX6464ES | ||
626 | tristate "Digigram LX6464ES" | ||
627 | select SND_PCM | ||
628 | help | ||
629 | Say Y here to include support for Digigram LX6464ES boards. | ||
630 | |||
631 | To compile this driver as a module, choose M here: the module | ||
632 | will be called snd-lx6464es. | ||
633 | |||
634 | |||
625 | config SND_MAESTRO3 | 635 | config SND_MAESTRO3 |
626 | tristate "ESS Allegro/Maestro3" | 636 | tristate "ESS Allegro/Maestro3" |
627 | select SND_AC97_CODEC | 637 | select SND_AC97_CODEC |
diff --git a/sound/pci/Makefile b/sound/pci/Makefile index 65b25d221cd2..7d83e084dcf4 100644 --- a/sound/pci/Makefile +++ b/sound/pci/Makefile | |||
@@ -62,6 +62,7 @@ obj-$(CONFIG_SND) += \ | |||
62 | ca0106/ \ | 62 | ca0106/ \ |
63 | cs46xx/ \ | 63 | cs46xx/ \ |
64 | cs5535audio/ \ | 64 | cs5535audio/ \ |
65 | lx6464es/ \ | ||
65 | echoaudio/ \ | 66 | echoaudio/ \ |
66 | emu10k1/ \ | 67 | emu10k1/ \ |
67 | hda/ \ | 68 | hda/ \ |
diff --git a/sound/pci/lx6464es/Makefile b/sound/pci/lx6464es/Makefile new file mode 100644 index 000000000000..eb04a6c73d8b --- /dev/null +++ b/sound/pci/lx6464es/Makefile | |||
@@ -0,0 +1,2 @@ | |||
1 | snd-lx6464es-objs := lx6464es.o lx_core.o | ||
2 | obj-$(CONFIG_SND_LX6464ES) += snd-lx6464es.o | ||
diff --git a/sound/pci/lx6464es/lx6464es.c b/sound/pci/lx6464es/lx6464es.c new file mode 100644 index 000000000000..7bc8b8caa992 --- /dev/null +++ b/sound/pci/lx6464es/lx6464es.c | |||
@@ -0,0 +1,1152 @@ | |||
1 | /* -*- linux-c -*- * | ||
2 | * | ||
3 | * ALSA driver for the digigram lx6464es interface | ||
4 | * | ||
5 | * Copyright (c) 2008, 2009 Tim Blechmann <tim@klingt.org> | ||
6 | * | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, write to | ||
20 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | ||
21 | * Boston, MA 02111-1307, USA. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #include <linux/module.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/pci.h> | ||
28 | #include <linux/delay.h> | ||
29 | |||
30 | #include <sound/initval.h> | ||
31 | #include <sound/control.h> | ||
32 | #include <sound/info.h> | ||
33 | |||
34 | #include "lx6464es.h" | ||
35 | |||
36 | MODULE_AUTHOR("Tim Blechmann"); | ||
37 | MODULE_LICENSE("GPL"); | ||
38 | MODULE_DESCRIPTION("digigram lx6464es"); | ||
39 | MODULE_SUPPORTED_DEVICE("{digigram lx6464es{}}"); | ||
40 | |||
41 | |||
42 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | ||
43 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | ||
44 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | ||
45 | |||
46 | static const char card_name[] = "LX6464ES"; | ||
47 | |||
48 | |||
49 | #define PCI_DEVICE_ID_PLX_LX6464ES PCI_DEVICE_ID_PLX_9056 | ||
50 | |||
51 | static struct pci_device_id snd_lx6464es_ids[] = { | ||
52 | { PCI_DEVICE(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES), | ||
53 | .subvendor = PCI_VENDOR_ID_DIGIGRAM, | ||
54 | .subdevice = PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM | ||
55 | }, /* LX6464ES */ | ||
56 | { PCI_DEVICE(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES), | ||
57 | .subvendor = PCI_VENDOR_ID_DIGIGRAM, | ||
58 | .subdevice = PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM | ||
59 | }, /* LX6464ES-CAE */ | ||
60 | { 0, }, | ||
61 | }; | ||
62 | |||
63 | MODULE_DEVICE_TABLE(pci, snd_lx6464es_ids); | ||
64 | |||
65 | |||
66 | |||
67 | /* PGO pour USERo dans le registre pci_0x06/loc_0xEC */ | ||
68 | #define CHIPSC_RESET_XILINX (1L<<16) | ||
69 | |||
70 | |||
71 | /* alsa callbacks */ | ||
72 | static struct snd_pcm_hardware lx_caps = { | ||
73 | .info = (SNDRV_PCM_INFO_MMAP | | ||
74 | SNDRV_PCM_INFO_INTERLEAVED | | ||
75 | SNDRV_PCM_INFO_MMAP_VALID | | ||
76 | SNDRV_PCM_INFO_SYNC_START), | ||
77 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | ||
78 | SNDRV_PCM_FMTBIT_S16_BE | | ||
79 | SNDRV_PCM_FMTBIT_S24_3LE | | ||
80 | SNDRV_PCM_FMTBIT_S24_3BE), | ||
81 | .rates = (SNDRV_PCM_RATE_CONTINUOUS | | ||
82 | SNDRV_PCM_RATE_8000_192000), | ||
83 | .rate_min = 8000, | ||
84 | .rate_max = 192000, | ||
85 | .channels_min = 2, | ||
86 | .channels_max = 64, | ||
87 | .buffer_bytes_max = 64*2*3*MICROBLAZE_IBL_MAX*MAX_STREAM_BUFFER, | ||
88 | .period_bytes_min = (2*2*MICROBLAZE_IBL_MIN*2), | ||
89 | .period_bytes_max = (4*64*MICROBLAZE_IBL_MAX*MAX_STREAM_BUFFER), | ||
90 | .periods_min = 2, | ||
91 | .periods_max = MAX_STREAM_BUFFER, | ||
92 | }; | ||
93 | |||
94 | static int lx_set_granularity(struct lx6464es *chip, u32 gran); | ||
95 | |||
96 | |||
97 | static int lx_hardware_open(struct lx6464es *chip, | ||
98 | struct snd_pcm_substream *substream) | ||
99 | { | ||
100 | int err = 0; | ||
101 | struct snd_pcm_runtime *runtime = substream->runtime; | ||
102 | int channels = runtime->channels; | ||
103 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
104 | |||
105 | snd_pcm_uframes_t period_size = runtime->period_size; | ||
106 | |||
107 | snd_printd(LXP "allocating pipe for %d channels\n", channels); | ||
108 | err = lx_pipe_allocate(chip, 0, is_capture, channels); | ||
109 | if (err < 0) { | ||
110 | snd_printk(KERN_ERR LXP "allocating pipe failed\n"); | ||
111 | return err; | ||
112 | } | ||
113 | |||
114 | err = lx_set_granularity(chip, period_size); | ||
115 | if (err < 0) { | ||
116 | snd_printk(KERN_ERR LXP "setting granularity to %ld failed\n", | ||
117 | period_size); | ||
118 | return err; | ||
119 | } | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | |||
124 | static int lx_hardware_start(struct lx6464es *chip, | ||
125 | struct snd_pcm_substream *substream) | ||
126 | { | ||
127 | int err = 0; | ||
128 | struct snd_pcm_runtime *runtime = substream->runtime; | ||
129 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
130 | |||
131 | snd_printd(LXP "setting stream format\n"); | ||
132 | err = lx_stream_set_format(chip, runtime, 0, is_capture); | ||
133 | if (err < 0) { | ||
134 | snd_printk(KERN_ERR LXP "setting stream format failed\n"); | ||
135 | return err; | ||
136 | } | ||
137 | |||
138 | snd_printd(LXP "starting pipe\n"); | ||
139 | err = lx_pipe_start(chip, 0, is_capture); | ||
140 | if (err < 0) { | ||
141 | snd_printk(KERN_ERR LXP "starting pipe failed\n"); | ||
142 | return err; | ||
143 | } | ||
144 | |||
145 | snd_printd(LXP "waiting for pipe to start\n"); | ||
146 | err = lx_pipe_wait_for_start(chip, 0, is_capture); | ||
147 | if (err < 0) { | ||
148 | snd_printk(KERN_ERR LXP "waiting for pipe failed\n"); | ||
149 | return err; | ||
150 | } | ||
151 | |||
152 | return err; | ||
153 | } | ||
154 | |||
155 | |||
156 | static int lx_hardware_stop(struct lx6464es *chip, | ||
157 | struct snd_pcm_substream *substream) | ||
158 | { | ||
159 | int err = 0; | ||
160 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
161 | |||
162 | snd_printd(LXP "pausing pipe\n"); | ||
163 | err = lx_pipe_pause(chip, 0, is_capture); | ||
164 | if (err < 0) { | ||
165 | snd_printk(KERN_ERR LXP "pausing pipe failed\n"); | ||
166 | return err; | ||
167 | } | ||
168 | |||
169 | snd_printd(LXP "waiting for pipe to become idle\n"); | ||
170 | err = lx_pipe_wait_for_idle(chip, 0, is_capture); | ||
171 | if (err < 0) { | ||
172 | snd_printk(KERN_ERR LXP "waiting for pipe failed\n"); | ||
173 | return err; | ||
174 | } | ||
175 | |||
176 | snd_printd(LXP "stopping pipe\n"); | ||
177 | err = lx_pipe_stop(chip, 0, is_capture); | ||
178 | if (err < 0) { | ||
179 | snd_printk(LXP "stopping pipe failed\n"); | ||
180 | return err; | ||
181 | } | ||
182 | |||
183 | return err; | ||
184 | } | ||
185 | |||
186 | |||
187 | static int lx_hardware_close(struct lx6464es *chip, | ||
188 | struct snd_pcm_substream *substream) | ||
189 | { | ||
190 | int err = 0; | ||
191 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
192 | |||
193 | snd_printd(LXP "releasing pipe\n"); | ||
194 | err = lx_pipe_release(chip, 0, is_capture); | ||
195 | if (err < 0) { | ||
196 | snd_printk(LXP "releasing pipe failed\n"); | ||
197 | return err; | ||
198 | } | ||
199 | |||
200 | return err; | ||
201 | } | ||
202 | |||
203 | |||
204 | static int lx_pcm_open(struct snd_pcm_substream *substream) | ||
205 | { | ||
206 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
207 | struct snd_pcm_runtime *runtime = substream->runtime; | ||
208 | int err = 0; | ||
209 | int board_rate; | ||
210 | |||
211 | snd_printdd("->lx_pcm_open\n"); | ||
212 | mutex_lock(&chip->setup_mutex); | ||
213 | |||
214 | /* copy the struct snd_pcm_hardware struct */ | ||
215 | runtime->hw = lx_caps; | ||
216 | |||
217 | #if 0 | ||
218 | /* buffer-size should better be multiple of period-size */ | ||
219 | err = snd_pcm_hw_constraint_integer(runtime, | ||
220 | SNDRV_PCM_HW_PARAM_PERIODS); | ||
221 | if (err < 0) { | ||
222 | snd_printk(KERN_WARNING LXP "could not constrain periods\n"); | ||
223 | goto exit; | ||
224 | } | ||
225 | #endif | ||
226 | |||
227 | /* the clock rate cannot be changed */ | ||
228 | board_rate = chip->board_sample_rate; | ||
229 | err = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_RATE, | ||
230 | board_rate, board_rate); | ||
231 | |||
232 | if (err < 0) { | ||
233 | snd_printk(KERN_WARNING LXP "could not constrain periods\n"); | ||
234 | goto exit; | ||
235 | } | ||
236 | |||
237 | /* constrain period size */ | ||
238 | err = snd_pcm_hw_constraint_minmax(runtime, | ||
239 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | ||
240 | MICROBLAZE_IBL_MIN, | ||
241 | MICROBLAZE_IBL_MAX); | ||
242 | if (err < 0) { | ||
243 | snd_printk(KERN_WARNING LXP | ||
244 | "could not constrain period size\n"); | ||
245 | goto exit; | ||
246 | } | ||
247 | |||
248 | snd_pcm_hw_constraint_step(runtime, 0, | ||
249 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32); | ||
250 | |||
251 | snd_pcm_set_sync(substream); | ||
252 | err = 0; | ||
253 | |||
254 | exit: | ||
255 | runtime->private_data = chip; | ||
256 | |||
257 | mutex_unlock(&chip->setup_mutex); | ||
258 | snd_printdd("<-lx_pcm_open, %d\n", err); | ||
259 | return err; | ||
260 | } | ||
261 | |||
262 | static int lx_pcm_close(struct snd_pcm_substream *substream) | ||
263 | { | ||
264 | int err = 0; | ||
265 | snd_printdd("->lx_pcm_close\n"); | ||
266 | return err; | ||
267 | } | ||
268 | |||
269 | static snd_pcm_uframes_t lx_pcm_stream_pointer(struct snd_pcm_substream | ||
270 | *substream) | ||
271 | { | ||
272 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
273 | snd_pcm_uframes_t pos; | ||
274 | unsigned long flags; | ||
275 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
276 | |||
277 | struct lx_stream *lx_stream = is_capture ? &chip->capture_stream : | ||
278 | &chip->playback_stream; | ||
279 | |||
280 | snd_printdd("->lx_pcm_stream_pointer\n"); | ||
281 | |||
282 | spin_lock_irqsave(&chip->lock, flags); | ||
283 | pos = lx_stream->frame_pos * substream->runtime->period_size; | ||
284 | spin_unlock_irqrestore(&chip->lock, flags); | ||
285 | |||
286 | snd_printdd(LXP "stream_pointer at %ld\n", pos); | ||
287 | return pos; | ||
288 | } | ||
289 | |||
290 | static int lx_pcm_prepare(struct snd_pcm_substream *substream) | ||
291 | { | ||
292 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
293 | int err = 0; | ||
294 | const int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
295 | |||
296 | snd_printdd("->lx_pcm_prepare\n"); | ||
297 | |||
298 | mutex_lock(&chip->setup_mutex); | ||
299 | |||
300 | if (chip->hardware_running[is_capture]) { | ||
301 | err = lx_hardware_stop(chip, substream); | ||
302 | if (err < 0) { | ||
303 | snd_printk(KERN_ERR LXP "failed to stop hardware. " | ||
304 | "Error code %d\n", err); | ||
305 | goto exit; | ||
306 | } | ||
307 | |||
308 | err = lx_hardware_close(chip, substream); | ||
309 | if (err < 0) { | ||
310 | snd_printk(KERN_ERR LXP "failed to close hardware. " | ||
311 | "Error code %d\n", err); | ||
312 | goto exit; | ||
313 | } | ||
314 | } | ||
315 | |||
316 | snd_printd(LXP "opening hardware\n"); | ||
317 | err = lx_hardware_open(chip, substream); | ||
318 | if (err < 0) { | ||
319 | snd_printk(KERN_ERR LXP "failed to open hardware. " | ||
320 | "Error code %d\n", err); | ||
321 | goto exit; | ||
322 | } | ||
323 | |||
324 | err = lx_hardware_start(chip, substream); | ||
325 | if (err < 0) { | ||
326 | snd_printk(KERN_ERR LXP "failed to start hardware. " | ||
327 | "Error code %d\n", err); | ||
328 | goto exit; | ||
329 | } | ||
330 | |||
331 | chip->hardware_running[is_capture] = 1; | ||
332 | |||
333 | if (chip->board_sample_rate != substream->runtime->rate) { | ||
334 | if (!err) | ||
335 | chip->board_sample_rate = substream->runtime->rate; | ||
336 | } | ||
337 | |||
338 | exit: | ||
339 | mutex_unlock(&chip->setup_mutex); | ||
340 | return err; | ||
341 | } | ||
342 | |||
343 | static int lx_pcm_hw_params(struct snd_pcm_substream *substream, | ||
344 | struct snd_pcm_hw_params *hw_params, int is_capture) | ||
345 | { | ||
346 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
347 | int err = 0; | ||
348 | |||
349 | snd_printdd("->lx_pcm_hw_params\n"); | ||
350 | |||
351 | mutex_lock(&chip->setup_mutex); | ||
352 | |||
353 | /* set dma buffer */ | ||
354 | err = snd_pcm_lib_malloc_pages(substream, | ||
355 | params_buffer_bytes(hw_params)); | ||
356 | |||
357 | if (is_capture) | ||
358 | chip->capture_stream.stream = substream; | ||
359 | else | ||
360 | chip->playback_stream.stream = substream; | ||
361 | |||
362 | mutex_unlock(&chip->setup_mutex); | ||
363 | return err; | ||
364 | } | ||
365 | |||
366 | static int lx_pcm_hw_params_playback(struct snd_pcm_substream *substream, | ||
367 | struct snd_pcm_hw_params *hw_params) | ||
368 | { | ||
369 | return lx_pcm_hw_params(substream, hw_params, 0); | ||
370 | } | ||
371 | |||
372 | static int lx_pcm_hw_params_capture(struct snd_pcm_substream *substream, | ||
373 | struct snd_pcm_hw_params *hw_params) | ||
374 | { | ||
375 | return lx_pcm_hw_params(substream, hw_params, 1); | ||
376 | } | ||
377 | |||
378 | static int lx_pcm_hw_free(struct snd_pcm_substream *substream) | ||
379 | { | ||
380 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
381 | int err = 0; | ||
382 | int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
383 | |||
384 | snd_printdd("->lx_pcm_hw_free\n"); | ||
385 | mutex_lock(&chip->setup_mutex); | ||
386 | |||
387 | if (chip->hardware_running[is_capture]) { | ||
388 | err = lx_hardware_stop(chip, substream); | ||
389 | if (err < 0) { | ||
390 | snd_printk(KERN_ERR LXP "failed to stop hardware. " | ||
391 | "Error code %d\n", err); | ||
392 | goto exit; | ||
393 | } | ||
394 | |||
395 | err = lx_hardware_close(chip, substream); | ||
396 | if (err < 0) { | ||
397 | snd_printk(KERN_ERR LXP "failed to close hardware. " | ||
398 | "Error code %d\n", err); | ||
399 | goto exit; | ||
400 | } | ||
401 | |||
402 | chip->hardware_running[is_capture] = 0; | ||
403 | } | ||
404 | |||
405 | err = snd_pcm_lib_free_pages(substream); | ||
406 | |||
407 | if (is_capture) | ||
408 | chip->capture_stream.stream = 0; | ||
409 | else | ||
410 | chip->playback_stream.stream = 0; | ||
411 | |||
412 | exit: | ||
413 | mutex_unlock(&chip->setup_mutex); | ||
414 | return err; | ||
415 | } | ||
416 | |||
417 | static void lx_trigger_start(struct lx6464es *chip, struct lx_stream *lx_stream) | ||
418 | { | ||
419 | struct snd_pcm_substream *substream = lx_stream->stream; | ||
420 | const int is_capture = lx_stream->is_capture; | ||
421 | |||
422 | int err; | ||
423 | |||
424 | const u32 channels = substream->runtime->channels; | ||
425 | const u32 bytes_per_frame = channels * 3; | ||
426 | const u32 period_size = substream->runtime->period_size; | ||
427 | const u32 periods = substream->runtime->periods; | ||
428 | const u32 period_bytes = period_size * bytes_per_frame; | ||
429 | |||
430 | dma_addr_t buf = substream->dma_buffer.addr; | ||
431 | int i; | ||
432 | |||
433 | u32 needed, freed; | ||
434 | u32 size_array[5]; | ||
435 | |||
436 | for (i = 0; i != periods; ++i) { | ||
437 | u32 buffer_index = 0; | ||
438 | |||
439 | err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, | ||
440 | size_array); | ||
441 | snd_printdd(LXP "starting: needed %d, freed %d\n", | ||
442 | needed, freed); | ||
443 | |||
444 | err = lx_buffer_give(chip, 0, is_capture, period_bytes, | ||
445 | lower_32_bits(buf), upper_32_bits(buf), | ||
446 | &buffer_index); | ||
447 | |||
448 | snd_printdd(LXP "starting: buffer index %x on %p (%d bytes)\n", | ||
449 | buffer_index, (void *)buf, period_bytes); | ||
450 | buf += period_bytes; | ||
451 | } | ||
452 | |||
453 | err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); | ||
454 | snd_printdd(LXP "starting: needed %d, freed %d\n", needed, freed); | ||
455 | |||
456 | snd_printd(LXP "starting: starting stream\n"); | ||
457 | err = lx_stream_start(chip, 0, is_capture); | ||
458 | if (err < 0) | ||
459 | snd_printk(KERN_ERR LXP "couldn't start stream\n"); | ||
460 | else | ||
461 | lx_stream->status = LX_STREAM_STATUS_RUNNING; | ||
462 | |||
463 | lx_stream->frame_pos = 0; | ||
464 | } | ||
465 | |||
466 | static void lx_trigger_stop(struct lx6464es *chip, struct lx_stream *lx_stream) | ||
467 | { | ||
468 | const int is_capture = lx_stream->is_capture; | ||
469 | int err; | ||
470 | |||
471 | snd_printd(LXP "stopping: stopping stream\n"); | ||
472 | err = lx_stream_stop(chip, 0, is_capture); | ||
473 | if (err < 0) | ||
474 | snd_printk(KERN_ERR LXP "couldn't stop stream\n"); | ||
475 | else | ||
476 | lx_stream->status = LX_STREAM_STATUS_FREE; | ||
477 | |||
478 | } | ||
479 | |||
480 | static void lx_trigger_tasklet_dispatch_stream(struct lx6464es *chip, | ||
481 | struct lx_stream *lx_stream) | ||
482 | { | ||
483 | switch (lx_stream->status) { | ||
484 | case LX_STREAM_STATUS_SCHEDULE_RUN: | ||
485 | lx_trigger_start(chip, lx_stream); | ||
486 | break; | ||
487 | |||
488 | case LX_STREAM_STATUS_SCHEDULE_STOP: | ||
489 | lx_trigger_stop(chip, lx_stream); | ||
490 | break; | ||
491 | |||
492 | default: | ||
493 | break; | ||
494 | } | ||
495 | } | ||
496 | |||
497 | static void lx_trigger_tasklet(unsigned long data) | ||
498 | { | ||
499 | struct lx6464es *chip = (struct lx6464es *)data; | ||
500 | unsigned long flags; | ||
501 | |||
502 | snd_printdd("->lx_trigger_tasklet\n"); | ||
503 | |||
504 | spin_lock_irqsave(&chip->lock, flags); | ||
505 | lx_trigger_tasklet_dispatch_stream(chip, &chip->capture_stream); | ||
506 | lx_trigger_tasklet_dispatch_stream(chip, &chip->playback_stream); | ||
507 | spin_unlock_irqrestore(&chip->lock, flags); | ||
508 | } | ||
509 | |||
510 | static int lx_pcm_trigger_dispatch(struct lx6464es *chip, | ||
511 | struct lx_stream *lx_stream, int cmd) | ||
512 | { | ||
513 | int err = 0; | ||
514 | |||
515 | switch (cmd) { | ||
516 | case SNDRV_PCM_TRIGGER_START: | ||
517 | lx_stream->status = LX_STREAM_STATUS_SCHEDULE_RUN; | ||
518 | break; | ||
519 | |||
520 | case SNDRV_PCM_TRIGGER_STOP: | ||
521 | lx_stream->status = LX_STREAM_STATUS_SCHEDULE_STOP; | ||
522 | break; | ||
523 | |||
524 | default: | ||
525 | err = -EINVAL; | ||
526 | goto exit; | ||
527 | } | ||
528 | tasklet_schedule(&chip->trigger_tasklet); | ||
529 | |||
530 | exit: | ||
531 | return err; | ||
532 | } | ||
533 | |||
534 | |||
535 | static int lx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | ||
536 | { | ||
537 | struct lx6464es *chip = snd_pcm_substream_chip(substream); | ||
538 | const int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); | ||
539 | struct lx_stream *stream = is_capture ? &chip->capture_stream : | ||
540 | &chip->playback_stream; | ||
541 | |||
542 | snd_printdd("->lx_pcm_trigger\n"); | ||
543 | |||
544 | return lx_pcm_trigger_dispatch(chip, stream, cmd); | ||
545 | } | ||
546 | |||
547 | static int snd_lx6464es_free(struct lx6464es *chip) | ||
548 | { | ||
549 | snd_printdd("->snd_lx6464es_free\n"); | ||
550 | |||
551 | lx_irq_disable(chip); | ||
552 | |||
553 | if (chip->irq >= 0) | ||
554 | free_irq(chip->irq, chip); | ||
555 | |||
556 | iounmap(chip->port_dsp_bar); | ||
557 | ioport_unmap(chip->port_plx_remapped); | ||
558 | |||
559 | pci_release_regions(chip->pci); | ||
560 | pci_disable_device(chip->pci); | ||
561 | |||
562 | kfree(chip); | ||
563 | |||
564 | return 0; | ||
565 | } | ||
566 | |||
567 | static int snd_lx6464es_dev_free(struct snd_device *device) | ||
568 | { | ||
569 | return snd_lx6464es_free(device->device_data); | ||
570 | } | ||
571 | |||
572 | /* reset the dsp during initialization */ | ||
573 | static int __devinit lx_init_xilinx_reset(struct lx6464es *chip) | ||
574 | { | ||
575 | int i; | ||
576 | u32 plx_reg = lx_plx_reg_read(chip, ePLX_CHIPSC); | ||
577 | |||
578 | snd_printdd("->lx_init_xilinx_reset\n"); | ||
579 | |||
580 | /* activate reset of xilinx */ | ||
581 | plx_reg &= ~CHIPSC_RESET_XILINX; | ||
582 | |||
583 | lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg); | ||
584 | msleep(1); | ||
585 | |||
586 | lx_plx_reg_write(chip, ePLX_MBOX3, 0); | ||
587 | msleep(1); | ||
588 | |||
589 | plx_reg |= CHIPSC_RESET_XILINX; | ||
590 | lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg); | ||
591 | |||
592 | /* deactivate reset of xilinx */ | ||
593 | for (i = 0; i != 100; ++i) { | ||
594 | u32 reg_mbox3; | ||
595 | msleep(10); | ||
596 | reg_mbox3 = lx_plx_reg_read(chip, ePLX_MBOX3); | ||
597 | if (reg_mbox3) { | ||
598 | snd_printd(LXP "xilinx reset done\n"); | ||
599 | snd_printdd(LXP "xilinx took %d loops\n", i); | ||
600 | break; | ||
601 | } | ||
602 | } | ||
603 | |||
604 | /* todo: add some error handling? */ | ||
605 | |||
606 | /* clear mr */ | ||
607 | lx_dsp_reg_write(chip, eReg_CSM, 0); | ||
608 | |||
609 | /* le xilinx ES peut ne pas etre encore pret, on attend. */ | ||
610 | msleep(600); | ||
611 | |||
612 | return 0; | ||
613 | } | ||
614 | |||
615 | static int __devinit lx_init_xilinx_test(struct lx6464es *chip) | ||
616 | { | ||
617 | u32 reg; | ||
618 | |||
619 | snd_printdd("->lx_init_xilinx_test\n"); | ||
620 | |||
621 | /* TEST if we have access to Xilinx/MicroBlaze */ | ||
622 | lx_dsp_reg_write(chip, eReg_CSM, 0); | ||
623 | |||
624 | reg = lx_dsp_reg_read(chip, eReg_CSM); | ||
625 | |||
626 | if (reg) { | ||
627 | snd_printk(KERN_ERR LXP "Problem: Reg_CSM %x.\n", reg); | ||
628 | |||
629 | /* PCI9056_SPACE0_REMAP */ | ||
630 | lx_plx_reg_write(chip, ePLX_PCICR, 1); | ||
631 | |||
632 | reg = lx_dsp_reg_read(chip, eReg_CSM); | ||
633 | if (reg) { | ||
634 | snd_printk(KERN_ERR LXP "Error: Reg_CSM %x.\n", reg); | ||
635 | return -EAGAIN; /* seems to be appropriate */ | ||
636 | } | ||
637 | } | ||
638 | |||
639 | snd_printd(LXP "Xilinx/MicroBlaze access test successful\n"); | ||
640 | |||
641 | return 0; | ||
642 | } | ||
643 | |||
644 | /* initialize ethersound */ | ||
645 | static int __devinit lx_init_ethersound_config(struct lx6464es *chip) | ||
646 | { | ||
647 | int i; | ||
648 | u32 orig_conf_es = lx_dsp_reg_read(chip, eReg_CONFES); | ||
649 | |||
650 | u32 default_conf_es = (64 << IOCR_OUTPUTS_OFFSET) | | ||
651 | (64 << IOCR_INPUTS_OFFSET) | | ||
652 | (FREQ_RATIO_SINGLE_MODE << FREQ_RATIO_OFFSET); | ||
653 | |||
654 | u32 conf_es = (orig_conf_es & CONFES_READ_PART_MASK) | ||
655 | | (default_conf_es & CONFES_WRITE_PART_MASK); | ||
656 | |||
657 | snd_printdd("->lx_init_ethersound\n"); | ||
658 | |||
659 | chip->freq_ratio = FREQ_RATIO_SINGLE_MODE; | ||
660 | |||
661 | /* | ||
662 | * write it to the card ! | ||
663 | * this actually kicks the ES xilinx, the first time since poweron. | ||
664 | * the MAC address in the Reg_ADMACESMSB Reg_ADMACESLSB registers | ||
665 | * is not ready before this is done, and the bit 2 in Reg_CSES is set. | ||
666 | * */ | ||
667 | lx_dsp_reg_write(chip, eReg_CONFES, conf_es); | ||
668 | |||
669 | for (i = 0; i != 1000; ++i) { | ||
670 | if (lx_dsp_reg_read(chip, eReg_CSES) & 4) { | ||
671 | snd_printd(LXP "ethersound initialized after %dms\n", | ||
672 | i); | ||
673 | goto ethersound_initialized; | ||
674 | } | ||
675 | msleep(1); | ||
676 | } | ||
677 | snd_printk(KERN_WARNING LXP | ||
678 | "ethersound could not be initialized after %dms\n", i); | ||
679 | return -ETIMEDOUT; | ||
680 | |||
681 | ethersound_initialized: | ||
682 | snd_printd(LXP "ethersound initialized\n"); | ||
683 | return 0; | ||
684 | } | ||
685 | |||
686 | static int __devinit lx_init_get_version_features(struct lx6464es *chip) | ||
687 | { | ||
688 | u32 dsp_version; | ||
689 | |||
690 | int err; | ||
691 | |||
692 | snd_printdd("->lx_init_get_version_features\n"); | ||
693 | |||
694 | err = lx_dsp_get_version(chip, &dsp_version); | ||
695 | |||
696 | if (err == 0) { | ||
697 | u32 freq; | ||
698 | |||
699 | snd_printk(LXP "DSP version: V%02d.%02d #%d\n", | ||
700 | (dsp_version>>16) & 0xff, (dsp_version>>8) & 0xff, | ||
701 | dsp_version & 0xff); | ||
702 | |||
703 | /* later: what firmware version do we expect? */ | ||
704 | |||
705 | /* retrieve Play/Rec features */ | ||
706 | /* done here because we may have to handle alternate | ||
707 | * DSP files. */ | ||
708 | /* later */ | ||
709 | |||
710 | /* init the EtherSound sample rate */ | ||
711 | err = lx_dsp_get_clock_frequency(chip, &freq); | ||
712 | if (err == 0) | ||
713 | chip->board_sample_rate = freq; | ||
714 | snd_printd(LXP "actual clock frequency %d\n", freq); | ||
715 | } else { | ||
716 | snd_printk(KERN_ERR LXP "DSP corrupted \n"); | ||
717 | err = -EAGAIN; | ||
718 | } | ||
719 | |||
720 | return err; | ||
721 | } | ||
722 | |||
723 | static int lx_set_granularity(struct lx6464es *chip, u32 gran) | ||
724 | { | ||
725 | int err = 0; | ||
726 | u32 snapped_gran = MICROBLAZE_IBL_MIN; | ||
727 | |||
728 | snd_printdd("->lx_set_granularity\n"); | ||
729 | |||
730 | /* blocksize is a power of 2 */ | ||
731 | while ((snapped_gran < gran) && | ||
732 | (snapped_gran < MICROBLAZE_IBL_MAX)) { | ||
733 | snapped_gran *= 2; | ||
734 | } | ||
735 | |||
736 | if (snapped_gran == chip->pcm_granularity) | ||
737 | return 0; | ||
738 | |||
739 | err = lx_dsp_set_granularity(chip, snapped_gran); | ||
740 | if (err < 0) { | ||
741 | snd_printk(KERN_WARNING LXP "could not set granularity\n"); | ||
742 | err = -EAGAIN; | ||
743 | } | ||
744 | |||
745 | if (snapped_gran != gran) | ||
746 | snd_printk(LXP "snapped blocksize to %d\n", snapped_gran); | ||
747 | |||
748 | snd_printd(LXP "set blocksize on board %d\n", snapped_gran); | ||
749 | chip->pcm_granularity = snapped_gran; | ||
750 | |||
751 | return err; | ||
752 | } | ||
753 | |||
754 | /* initialize and test the xilinx dsp chip */ | ||
755 | static int __devinit lx_init_dsp(struct lx6464es *chip) | ||
756 | { | ||
757 | int err; | ||
758 | u8 mac_address[6]; | ||
759 | int i; | ||
760 | |||
761 | snd_printdd("->lx_init_dsp\n"); | ||
762 | |||
763 | snd_printd(LXP "initialize board\n"); | ||
764 | err = lx_init_xilinx_reset(chip); | ||
765 | if (err) | ||
766 | return err; | ||
767 | |||
768 | snd_printd(LXP "testing board\n"); | ||
769 | err = lx_init_xilinx_test(chip); | ||
770 | if (err) | ||
771 | return err; | ||
772 | |||
773 | snd_printd(LXP "initialize ethersound configuration\n"); | ||
774 | err = lx_init_ethersound_config(chip); | ||
775 | if (err) | ||
776 | return err; | ||
777 | |||
778 | lx_irq_enable(chip); | ||
779 | |||
780 | /** \todo the mac address should be ready by not, but it isn't, | ||
781 | * so we wait for it */ | ||
782 | for (i = 0; i != 1000; ++i) { | ||
783 | err = lx_dsp_get_mac(chip, mac_address); | ||
784 | if (err) | ||
785 | return err; | ||
786 | if (mac_address[0] || mac_address[1] || mac_address[2] || | ||
787 | mac_address[3] || mac_address[4] || mac_address[5]) | ||
788 | goto mac_ready; | ||
789 | msleep(1); | ||
790 | } | ||
791 | return -ETIMEDOUT; | ||
792 | |||
793 | mac_ready: | ||
794 | snd_printd(LXP "mac address ready read after: %dms\n", i); | ||
795 | snd_printk(LXP "mac address: %02X.%02X.%02X.%02X.%02X.%02X\n", | ||
796 | mac_address[0], mac_address[1], mac_address[2], | ||
797 | mac_address[3], mac_address[4], mac_address[5]); | ||
798 | |||
799 | err = lx_init_get_version_features(chip); | ||
800 | if (err) | ||
801 | return err; | ||
802 | |||
803 | lx_set_granularity(chip, MICROBLAZE_IBL_DEFAULT); | ||
804 | |||
805 | chip->playback_mute = 0; | ||
806 | |||
807 | return err; | ||
808 | } | ||
809 | |||
810 | static struct snd_pcm_ops lx_ops_playback = { | ||
811 | .open = lx_pcm_open, | ||
812 | .close = lx_pcm_close, | ||
813 | .ioctl = snd_pcm_lib_ioctl, | ||
814 | .prepare = lx_pcm_prepare, | ||
815 | .hw_params = lx_pcm_hw_params_playback, | ||
816 | .hw_free = lx_pcm_hw_free, | ||
817 | .trigger = lx_pcm_trigger, | ||
818 | .pointer = lx_pcm_stream_pointer, | ||
819 | }; | ||
820 | |||
821 | static struct snd_pcm_ops lx_ops_capture = { | ||
822 | .open = lx_pcm_open, | ||
823 | .close = lx_pcm_close, | ||
824 | .ioctl = snd_pcm_lib_ioctl, | ||
825 | .prepare = lx_pcm_prepare, | ||
826 | .hw_params = lx_pcm_hw_params_capture, | ||
827 | .hw_free = lx_pcm_hw_free, | ||
828 | .trigger = lx_pcm_trigger, | ||
829 | .pointer = lx_pcm_stream_pointer, | ||
830 | }; | ||
831 | |||
832 | static int __devinit lx_pcm_create(struct lx6464es *chip) | ||
833 | { | ||
834 | int err; | ||
835 | struct snd_pcm *pcm; | ||
836 | |||
837 | u32 size = 64 * /* channels */ | ||
838 | 3 * /* 24 bit samples */ | ||
839 | MAX_STREAM_BUFFER * /* periods */ | ||
840 | MICROBLAZE_IBL_MAX * /* frames per period */ | ||
841 | 2; /* duplex */ | ||
842 | |||
843 | size = PAGE_ALIGN(size); | ||
844 | |||
845 | /* hardcoded device name & channel count */ | ||
846 | err = snd_pcm_new(chip->card, (char *)card_name, 0, | ||
847 | 1, 1, &pcm); | ||
848 | |||
849 | pcm->private_data = chip; | ||
850 | |||
851 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &lx_ops_playback); | ||
852 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &lx_ops_capture); | ||
853 | |||
854 | pcm->info_flags = 0; | ||
855 | strcpy(pcm->name, card_name); | ||
856 | |||
857 | err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | ||
858 | snd_dma_pci_data(chip->pci), | ||
859 | size, size); | ||
860 | if (err < 0) | ||
861 | return err; | ||
862 | |||
863 | chip->pcm = pcm; | ||
864 | chip->capture_stream.is_capture = 1; | ||
865 | |||
866 | return 0; | ||
867 | } | ||
868 | |||
869 | static int lx_control_playback_info(struct snd_kcontrol *kcontrol, | ||
870 | struct snd_ctl_elem_info *uinfo) | ||
871 | { | ||
872 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | ||
873 | uinfo->count = 1; | ||
874 | uinfo->value.integer.min = 0; | ||
875 | uinfo->value.integer.max = 1; | ||
876 | return 0; | ||
877 | } | ||
878 | |||
879 | static int lx_control_playback_get(struct snd_kcontrol *kcontrol, | ||
880 | struct snd_ctl_elem_value *ucontrol) | ||
881 | { | ||
882 | struct lx6464es *chip = snd_kcontrol_chip(kcontrol); | ||
883 | ucontrol->value.integer.value[0] = chip->playback_mute; | ||
884 | return 0; | ||
885 | } | ||
886 | |||
887 | static int lx_control_playback_put(struct snd_kcontrol *kcontrol, | ||
888 | struct snd_ctl_elem_value *ucontrol) | ||
889 | { | ||
890 | struct lx6464es *chip = snd_kcontrol_chip(kcontrol); | ||
891 | int changed = 0; | ||
892 | int current_value = chip->playback_mute; | ||
893 | |||
894 | if (current_value != ucontrol->value.integer.value[0]) { | ||
895 | lx_level_unmute(chip, 0, !current_value); | ||
896 | chip->playback_mute = !current_value; | ||
897 | changed = 1; | ||
898 | } | ||
899 | return changed; | ||
900 | } | ||
901 | |||
902 | static struct snd_kcontrol_new lx_control_playback_switch __devinitdata = { | ||
903 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | ||
904 | .name = "PCM Playback Switch", | ||
905 | .index = 0, | ||
906 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, | ||
907 | .private_value = 0, | ||
908 | .info = lx_control_playback_info, | ||
909 | .get = lx_control_playback_get, | ||
910 | .put = lx_control_playback_put | ||
911 | }; | ||
912 | |||
913 | |||
914 | |||
915 | static void lx_proc_levels_read(struct snd_info_entry *entry, | ||
916 | struct snd_info_buffer *buffer) | ||
917 | { | ||
918 | u32 levels[64]; | ||
919 | int err; | ||
920 | int i, j; | ||
921 | struct lx6464es *chip = entry->private_data; | ||
922 | |||
923 | snd_iprintf(buffer, "capture levels:\n"); | ||
924 | err = lx_level_peaks(chip, 1, 64, levels); | ||
925 | if (err < 0) | ||
926 | return; | ||
927 | |||
928 | for (i = 0; i != 8; ++i) { | ||
929 | for (j = 0; j != 8; ++j) | ||
930 | snd_iprintf(buffer, "%08x ", levels[i*8+j]); | ||
931 | snd_iprintf(buffer, "\n"); | ||
932 | } | ||
933 | |||
934 | snd_iprintf(buffer, "\nplayback levels:\n"); | ||
935 | |||
936 | err = lx_level_peaks(chip, 0, 64, levels); | ||
937 | if (err < 0) | ||
938 | return; | ||
939 | |||
940 | for (i = 0; i != 8; ++i) { | ||
941 | for (j = 0; j != 8; ++j) | ||
942 | snd_iprintf(buffer, "%08x ", levels[i*8+j]); | ||
943 | snd_iprintf(buffer, "\n"); | ||
944 | } | ||
945 | |||
946 | snd_iprintf(buffer, "\n"); | ||
947 | } | ||
948 | |||
949 | static int __devinit lx_proc_create(struct snd_card *card, struct lx6464es *chip) | ||
950 | { | ||
951 | struct snd_info_entry *entry; | ||
952 | int err = snd_card_proc_new(card, "levels", &entry); | ||
953 | if (err < 0) | ||
954 | return err; | ||
955 | |||
956 | snd_info_set_text_ops(entry, chip, lx_proc_levels_read); | ||
957 | return 0; | ||
958 | } | ||
959 | |||
960 | |||
961 | static int __devinit snd_lx6464es_create(struct snd_card *card, | ||
962 | struct pci_dev *pci, | ||
963 | struct lx6464es **rchip) | ||
964 | { | ||
965 | struct lx6464es *chip; | ||
966 | int err; | ||
967 | |||
968 | static struct snd_device_ops ops = { | ||
969 | .dev_free = snd_lx6464es_dev_free, | ||
970 | }; | ||
971 | |||
972 | snd_printdd("->snd_lx6464es_create\n"); | ||
973 | |||
974 | *rchip = NULL; | ||
975 | |||
976 | /* enable PCI device */ | ||
977 | err = pci_enable_device(pci); | ||
978 | if (err < 0) | ||
979 | return err; | ||
980 | |||
981 | pci_set_master(pci); | ||
982 | |||
983 | /* check if we can restrict PCI DMA transfers to 32 bits */ | ||
984 | err = pci_set_dma_mask(pci, DMA_32BIT_MASK); | ||
985 | if (err < 0) { | ||
986 | snd_printk(KERN_ERR "architecture does not support " | ||
987 | "32bit PCI busmaster DMA\n"); | ||
988 | pci_disable_device(pci); | ||
989 | return -ENXIO; | ||
990 | } | ||
991 | |||
992 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | ||
993 | if (chip == NULL) { | ||
994 | err = -ENOMEM; | ||
995 | goto alloc_failed; | ||
996 | } | ||
997 | |||
998 | chip->card = card; | ||
999 | chip->pci = pci; | ||
1000 | chip->irq = -1; | ||
1001 | |||
1002 | /* initialize synchronization structs */ | ||
1003 | spin_lock_init(&chip->lock); | ||
1004 | spin_lock_init(&chip->msg_lock); | ||
1005 | mutex_init(&chip->setup_mutex); | ||
1006 | tasklet_init(&chip->trigger_tasklet, lx_trigger_tasklet, | ||
1007 | (unsigned long)chip); | ||
1008 | tasklet_init(&chip->tasklet_capture, lx_tasklet_capture, | ||
1009 | (unsigned long)chip); | ||
1010 | tasklet_init(&chip->tasklet_playback, lx_tasklet_playback, | ||
1011 | (unsigned long)chip); | ||
1012 | |||
1013 | /* request resources */ | ||
1014 | err = pci_request_regions(pci, card_name); | ||
1015 | if (err < 0) | ||
1016 | goto request_regions_failed; | ||
1017 | |||
1018 | /* plx port */ | ||
1019 | chip->port_plx = pci_resource_start(pci, 1); | ||
1020 | chip->port_plx_remapped = ioport_map(chip->port_plx, | ||
1021 | pci_resource_len(pci, 1)); | ||
1022 | |||
1023 | /* dsp port */ | ||
1024 | chip->port_dsp_bar = pci_ioremap_bar(pci, 2); | ||
1025 | |||
1026 | err = request_irq(pci->irq, lx_interrupt, IRQF_SHARED, | ||
1027 | card_name, chip); | ||
1028 | if (err) { | ||
1029 | snd_printk(KERN_ERR LXP "unable to grab IRQ %d\n", pci->irq); | ||
1030 | goto request_irq_failed; | ||
1031 | } | ||
1032 | chip->irq = pci->irq; | ||
1033 | |||
1034 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); | ||
1035 | if (err < 0) | ||
1036 | goto device_new_failed; | ||
1037 | |||
1038 | err = lx_init_dsp(chip); | ||
1039 | if (err < 0) { | ||
1040 | snd_printk(KERN_ERR LXP "error during DSP initialization\n"); | ||
1041 | return err; | ||
1042 | } | ||
1043 | |||
1044 | err = lx_pcm_create(chip); | ||
1045 | if (err < 0) | ||
1046 | return err; | ||
1047 | |||
1048 | err = lx_proc_create(card, chip); | ||
1049 | if (err < 0) | ||
1050 | return err; | ||
1051 | |||
1052 | err = snd_ctl_add(card, snd_ctl_new1(&lx_control_playback_switch, | ||
1053 | chip)); | ||
1054 | if (err < 0) | ||
1055 | return err; | ||
1056 | |||
1057 | snd_card_set_dev(card, &pci->dev); | ||
1058 | |||
1059 | *rchip = chip; | ||
1060 | return 0; | ||
1061 | |||
1062 | device_new_failed: | ||
1063 | free_irq(pci->irq, chip); | ||
1064 | |||
1065 | request_irq_failed: | ||
1066 | pci_release_regions(pci); | ||
1067 | |||
1068 | request_regions_failed: | ||
1069 | kfree(chip); | ||
1070 | |||
1071 | alloc_failed: | ||
1072 | pci_disable_device(pci); | ||
1073 | |||
1074 | return err; | ||
1075 | } | ||
1076 | |||
1077 | static int __devinit snd_lx6464es_probe(struct pci_dev *pci, | ||
1078 | const struct pci_device_id *pci_id) | ||
1079 | { | ||
1080 | static int dev; | ||
1081 | struct snd_card *card; | ||
1082 | struct lx6464es *chip; | ||
1083 | int err; | ||
1084 | |||
1085 | snd_printdd("->snd_lx6464es_probe\n"); | ||
1086 | |||
1087 | if (dev >= SNDRV_CARDS) | ||
1088 | return -ENODEV; | ||
1089 | if (!enable[dev]) { | ||
1090 | dev++; | ||
1091 | return -ENOENT; | ||
1092 | } | ||
1093 | |||
1094 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); | ||
1095 | if (card == NULL) | ||
1096 | return -ENOMEM; | ||
1097 | |||
1098 | err = snd_lx6464es_create(card, pci, &chip); | ||
1099 | if (err < 0) { | ||
1100 | snd_printk(KERN_ERR LXP "error during snd_lx6464es_create\n"); | ||
1101 | goto out_free; | ||
1102 | } | ||
1103 | |||
1104 | strcpy(card->driver, "lx6464es"); | ||
1105 | strcpy(card->shortname, "Digigram LX6464ES"); | ||
1106 | sprintf(card->longname, "%s at 0x%lx, 0x%p, irq %i", | ||
1107 | card->shortname, chip->port_plx, | ||
1108 | chip->port_dsp_bar, chip->irq); | ||
1109 | |||
1110 | err = snd_card_register(card); | ||
1111 | if (err < 0) | ||
1112 | goto out_free; | ||
1113 | |||
1114 | snd_printdd(LXP "initialization successful\n"); | ||
1115 | pci_set_drvdata(pci, card); | ||
1116 | dev++; | ||
1117 | return 0; | ||
1118 | |||
1119 | out_free: | ||
1120 | snd_card_free(card); | ||
1121 | return err; | ||
1122 | |||
1123 | } | ||
1124 | |||
1125 | static void __devexit snd_lx6464es_remove(struct pci_dev *pci) | ||
1126 | { | ||
1127 | snd_card_free(pci_get_drvdata(pci)); | ||
1128 | pci_set_drvdata(pci, NULL); | ||
1129 | } | ||
1130 | |||
1131 | |||
1132 | static struct pci_driver driver = { | ||
1133 | .name = "Digigram LX6464ES", | ||
1134 | .id_table = snd_lx6464es_ids, | ||
1135 | .probe = snd_lx6464es_probe, | ||
1136 | .remove = __devexit_p(snd_lx6464es_remove), | ||
1137 | }; | ||
1138 | |||
1139 | |||
1140 | /* module initialization */ | ||
1141 | static int __init mod_init(void) | ||
1142 | { | ||
1143 | return pci_register_driver(&driver); | ||
1144 | } | ||
1145 | |||
1146 | static void __exit mod_exit(void) | ||
1147 | { | ||
1148 | pci_unregister_driver(&driver); | ||
1149 | } | ||
1150 | |||
1151 | module_init(mod_init); | ||
1152 | module_exit(mod_exit); | ||
diff --git a/sound/pci/lx6464es/lx6464es.h b/sound/pci/lx6464es/lx6464es.h new file mode 100644 index 000000000000..012c010c8c89 --- /dev/null +++ b/sound/pci/lx6464es/lx6464es.h | |||
@@ -0,0 +1,114 @@ | |||
1 | /* -*- linux-c -*- * | ||
2 | * | ||
3 | * ALSA driver for the digigram lx6464es interface | ||
4 | * | ||
5 | * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> | ||
6 | * | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, write to | ||
20 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | ||
21 | * Boston, MA 02111-1307, USA. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef LX6464ES_H | ||
26 | #define LX6464ES_H | ||
27 | |||
28 | #include <linux/spinlock.h> | ||
29 | #include <asm/atomic.h> | ||
30 | |||
31 | #include <sound/core.h> | ||
32 | #include <sound/pcm.h> | ||
33 | |||
34 | #include "lx_core.h" | ||
35 | |||
36 | #define LXP "LX6464ES: " | ||
37 | |||
38 | enum { | ||
39 | ES_cmd_free = 0, /* no command executing */ | ||
40 | ES_cmd_processing = 1, /* execution of a read/write command */ | ||
41 | ES_read_pending = 2, /* a asynchron read command is pending */ | ||
42 | ES_read_finishing = 3, /* a read command has finished waiting (set by | ||
43 | * Interrupt or CancelIrp) */ | ||
44 | }; | ||
45 | |||
46 | enum lx_stream_status { | ||
47 | LX_STREAM_STATUS_FREE, | ||
48 | /* LX_STREAM_STATUS_OPEN, */ | ||
49 | LX_STREAM_STATUS_SCHEDULE_RUN, | ||
50 | /* LX_STREAM_STATUS_STARTED, */ | ||
51 | LX_STREAM_STATUS_RUNNING, | ||
52 | LX_STREAM_STATUS_SCHEDULE_STOP, | ||
53 | /* LX_STREAM_STATUS_STOPPED, */ | ||
54 | /* LX_STREAM_STATUS_PAUSED */ | ||
55 | }; | ||
56 | |||
57 | |||
58 | struct lx_stream { | ||
59 | struct snd_pcm_substream *stream; | ||
60 | snd_pcm_uframes_t frame_pos; | ||
61 | enum lx_stream_status status; /* free, open, running, draining | ||
62 | * pause */ | ||
63 | int is_capture:1; | ||
64 | }; | ||
65 | |||
66 | |||
67 | struct lx6464es { | ||
68 | struct snd_card *card; | ||
69 | struct pci_dev *pci; | ||
70 | int irq; | ||
71 | |||
72 | spinlock_t lock; /* interrupt spinlock */ | ||
73 | struct mutex setup_mutex; /* mutex used in hw_params, open | ||
74 | * and close */ | ||
75 | |||
76 | struct tasklet_struct trigger_tasklet; /* trigger tasklet */ | ||
77 | struct tasklet_struct tasklet_capture; | ||
78 | struct tasklet_struct tasklet_playback; | ||
79 | |||
80 | /* ports */ | ||
81 | unsigned long port_plx; /* io port (size=256) */ | ||
82 | void __iomem *port_plx_remapped; /* remapped plx port */ | ||
83 | void __iomem *port_dsp_bar; /* memory port (32-bit, | ||
84 | * non-prefetchable, | ||
85 | * size=8K) */ | ||
86 | |||
87 | /* messaging */ | ||
88 | spinlock_t msg_lock; /* message spinlock */ | ||
89 | atomic_t send_message_locked; | ||
90 | struct lx_rmh rmh; | ||
91 | |||
92 | /* configuration */ | ||
93 | uint freq_ratio : 2; | ||
94 | uint playback_mute : 1; | ||
95 | uint hardware_running[2]; | ||
96 | u32 board_sample_rate; /* sample rate read from | ||
97 | * board */ | ||
98 | u32 sample_rate; /* our sample rate */ | ||
99 | u16 pcm_granularity; /* board blocksize */ | ||
100 | |||
101 | /* dma */ | ||
102 | struct snd_dma_buffer capture_dma_buf; | ||
103 | struct snd_dma_buffer playback_dma_buf; | ||
104 | |||
105 | /* pcm */ | ||
106 | struct snd_pcm *pcm; | ||
107 | |||
108 | /* streams */ | ||
109 | struct lx_stream capture_stream; | ||
110 | struct lx_stream playback_stream; | ||
111 | }; | ||
112 | |||
113 | |||
114 | #endif /* LX6464ES_H */ | ||
diff --git a/sound/pci/lx6464es/lx_core.c b/sound/pci/lx6464es/lx_core.c new file mode 100644 index 000000000000..a9f8f882b107 --- /dev/null +++ b/sound/pci/lx6464es/lx_core.c | |||
@@ -0,0 +1,1442 @@ | |||
1 | /* -*- linux-c -*- * | ||
2 | * | ||
3 | * ALSA driver for the digigram lx6464es interface | ||
4 | * low-level interface | ||
5 | * | ||
6 | * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, write to | ||
20 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | ||
21 | * Boston, MA 02111-1307, USA. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | /* #define RMH_DEBUG 1 */ | ||
26 | |||
27 | #include <linux/module.h> | ||
28 | #include <linux/pci.h> | ||
29 | #include <linux/delay.h> | ||
30 | |||
31 | #include "lx6464es.h" | ||
32 | #include "lx_core.h" | ||
33 | |||
34 | /* low-level register access */ | ||
35 | |||
36 | static const unsigned long dsp_port_offsets[] = { | ||
37 | 0, | ||
38 | 0x400, | ||
39 | 0x401, | ||
40 | 0x402, | ||
41 | 0x403, | ||
42 | 0x404, | ||
43 | 0x405, | ||
44 | 0x406, | ||
45 | 0x407, | ||
46 | 0x408, | ||
47 | 0x409, | ||
48 | 0x40a, | ||
49 | 0x40b, | ||
50 | 0x40c, | ||
51 | |||
52 | 0x410, | ||
53 | 0x411, | ||
54 | 0x412, | ||
55 | 0x413, | ||
56 | 0x414, | ||
57 | 0x415, | ||
58 | 0x416, | ||
59 | |||
60 | 0x420, | ||
61 | 0x430, | ||
62 | 0x431, | ||
63 | 0x432, | ||
64 | 0x433, | ||
65 | 0x434, | ||
66 | 0x440 | ||
67 | }; | ||
68 | |||
69 | static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) | ||
70 | { | ||
71 | void __iomem *base_address = chip->port_dsp_bar; | ||
72 | return base_address + dsp_port_offsets[port]*4; | ||
73 | } | ||
74 | |||
75 | unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) | ||
76 | { | ||
77 | void __iomem *address = lx_dsp_register(chip, port); | ||
78 | return ioread32(address); | ||
79 | } | ||
80 | |||
81 | void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len) | ||
82 | { | ||
83 | void __iomem *address = lx_dsp_register(chip, port); | ||
84 | memcpy_fromio(data, address, len*sizeof(u32)); | ||
85 | } | ||
86 | |||
87 | |||
88 | void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) | ||
89 | { | ||
90 | void __iomem *address = lx_dsp_register(chip, port); | ||
91 | iowrite32(data, address); | ||
92 | } | ||
93 | |||
94 | void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data, | ||
95 | u32 len) | ||
96 | { | ||
97 | void __iomem *address = lx_dsp_register(chip, port); | ||
98 | memcpy_toio(address, data, len*sizeof(u32)); | ||
99 | } | ||
100 | |||
101 | |||
102 | static const unsigned long plx_port_offsets[] = { | ||
103 | 0x04, | ||
104 | 0x40, | ||
105 | 0x44, | ||
106 | 0x48, | ||
107 | 0x4c, | ||
108 | 0x50, | ||
109 | 0x54, | ||
110 | 0x58, | ||
111 | 0x5c, | ||
112 | 0x64, | ||
113 | 0x68, | ||
114 | 0x6C | ||
115 | }; | ||
116 | |||
117 | static void __iomem *lx_plx_register(struct lx6464es *chip, int port) | ||
118 | { | ||
119 | void __iomem *base_address = chip->port_plx_remapped; | ||
120 | return base_address + plx_port_offsets[port]; | ||
121 | } | ||
122 | |||
123 | unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) | ||
124 | { | ||
125 | void __iomem *address = lx_plx_register(chip, port); | ||
126 | return ioread32(address); | ||
127 | } | ||
128 | |||
129 | void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) | ||
130 | { | ||
131 | void __iomem *address = lx_plx_register(chip, port); | ||
132 | iowrite32(data, address); | ||
133 | } | ||
134 | |||
135 | u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr) | ||
136 | { | ||
137 | int index; | ||
138 | |||
139 | switch (mbox_nr) { | ||
140 | case 1: | ||
141 | index = ePLX_MBOX1; break; | ||
142 | case 2: | ||
143 | index = ePLX_MBOX2; break; | ||
144 | case 3: | ||
145 | index = ePLX_MBOX3; break; | ||
146 | case 4: | ||
147 | index = ePLX_MBOX4; break; | ||
148 | case 5: | ||
149 | index = ePLX_MBOX5; break; | ||
150 | case 6: | ||
151 | index = ePLX_MBOX6; break; | ||
152 | case 7: | ||
153 | index = ePLX_MBOX7; break; | ||
154 | case 0: /* reserved for HF flags */ | ||
155 | snd_BUG(); | ||
156 | default: | ||
157 | return 0xdeadbeef; | ||
158 | } | ||
159 | |||
160 | return lx_plx_reg_read(chip, index); | ||
161 | } | ||
162 | |||
163 | int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value) | ||
164 | { | ||
165 | int index = -1; | ||
166 | |||
167 | switch (mbox_nr) { | ||
168 | case 1: | ||
169 | index = ePLX_MBOX1; break; | ||
170 | case 3: | ||
171 | index = ePLX_MBOX3; break; | ||
172 | case 4: | ||
173 | index = ePLX_MBOX4; break; | ||
174 | case 5: | ||
175 | index = ePLX_MBOX5; break; | ||
176 | case 6: | ||
177 | index = ePLX_MBOX6; break; | ||
178 | case 7: | ||
179 | index = ePLX_MBOX7; break; | ||
180 | case 0: /* reserved for HF flags */ | ||
181 | case 2: /* reserved for Pipe States | ||
182 | * the DSP keeps an image of it */ | ||
183 | snd_BUG(); | ||
184 | return -EBADRQC; | ||
185 | } | ||
186 | |||
187 | lx_plx_reg_write(chip, index, value); | ||
188 | return 0; | ||
189 | } | ||
190 | |||
191 | |||
192 | /* rmh */ | ||
193 | |||
194 | #ifdef CONFIG_SND_DEBUG | ||
195 | #define CMD_NAME(a) a | ||
196 | #else | ||
197 | #define CMD_NAME(a) NULL | ||
198 | #endif | ||
199 | |||
200 | #define Reg_CSM_MR 0x00000002 | ||
201 | #define Reg_CSM_MC 0x00000001 | ||
202 | |||
203 | struct dsp_cmd_info { | ||
204 | u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits | ||
205 | * word).*/ | ||
206 | u16 dcCmdLength; /* Command length in words of 24 bits.*/ | ||
207 | u16 dcStatusType; /* Status type: 0 for fixed length, 1 for | ||
208 | * random. */ | ||
209 | u16 dcStatusLength; /* Status length (if fixed).*/ | ||
210 | char *dcOpName; | ||
211 | }; | ||
212 | |||
213 | /* | ||
214 | Initialization and control data for the Microblaze interface | ||
215 | - OpCode: | ||
216 | the opcode field of the command set at the proper offset | ||
217 | - CmdLength | ||
218 | the number of command words | ||
219 | - StatusType | ||
220 | offset in the status registers: 0 means that the return value may be | ||
221 | different from 0, and must be read | ||
222 | - StatusLength | ||
223 | the number of status words (in addition to the return value) | ||
224 | */ | ||
225 | |||
226 | static struct dsp_cmd_info dsp_commands[] = | ||
227 | { | ||
228 | { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ | ||
229 | , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, | ||
230 | { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ | ||
231 | , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, | ||
232 | { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ | ||
233 | , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, | ||
234 | { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ | ||
235 | , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, | ||
236 | { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ | ||
237 | , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, | ||
238 | { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ | ||
239 | , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, | ||
240 | { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ | ||
241 | , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, | ||
242 | { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ | ||
243 | , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, | ||
244 | { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ | ||
245 | , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, | ||
246 | { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ | ||
247 | , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, | ||
248 | { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ | ||
249 | , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, | ||
250 | { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ | ||
251 | , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, | ||
252 | { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ | ||
253 | , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, | ||
254 | { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ | ||
255 | , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, | ||
256 | { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ | ||
257 | , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, | ||
258 | { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ | ||
259 | , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, | ||
260 | { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ | ||
261 | , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, | ||
262 | { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ | ||
263 | , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, | ||
264 | { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ | ||
265 | , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, | ||
266 | { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ | ||
267 | , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, | ||
268 | }; | ||
269 | |||
270 | static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) | ||
271 | { | ||
272 | snd_BUG_ON(cmd >= CMD_14_INVALID); | ||
273 | |||
274 | rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; | ||
275 | rmh->cmd_len = dsp_commands[cmd].dcCmdLength; | ||
276 | rmh->stat_len = dsp_commands[cmd].dcStatusLength; | ||
277 | rmh->dsp_stat = dsp_commands[cmd].dcStatusType; | ||
278 | rmh->cmd_idx = cmd; | ||
279 | memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); | ||
280 | |||
281 | #ifdef CONFIG_SND_DEBUG | ||
282 | memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); | ||
283 | #endif | ||
284 | #ifdef RMH_DEBUG | ||
285 | rmh->cmd_idx = cmd; | ||
286 | #endif | ||
287 | } | ||
288 | |||
289 | #ifdef RMH_DEBUG | ||
290 | #define LXRMH "lx6464es rmh: " | ||
291 | static void lx_message_dump(struct lx_rmh *rmh) | ||
292 | { | ||
293 | u8 idx = rmh->cmd_idx; | ||
294 | int i; | ||
295 | |||
296 | snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); | ||
297 | |||
298 | for (i = 0; i != rmh->cmd_len; ++i) | ||
299 | snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); | ||
300 | |||
301 | for (i = 0; i != rmh->stat_len; ++i) | ||
302 | snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); | ||
303 | snd_printk("\n"); | ||
304 | } | ||
305 | #else | ||
306 | static inline void lx_message_dump(struct lx_rmh *rmh) | ||
307 | {} | ||
308 | #endif | ||
309 | |||
310 | |||
311 | |||
312 | /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ | ||
313 | #define XILINX_TIMEOUT_MS 40 | ||
314 | #define XILINX_POLL_NO_SLEEP 100 | ||
315 | #define XILINX_POLL_ITERATIONS 150 | ||
316 | |||
317 | static int lx_message_send(struct lx6464es *chip, struct lx_rmh *rmh) | ||
318 | { | ||
319 | u32 reg = ED_DSP_TIMED_OUT; | ||
320 | int dwloop; | ||
321 | int answer_received; | ||
322 | |||
323 | if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { | ||
324 | snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); | ||
325 | return -EBUSY; | ||
326 | } | ||
327 | |||
328 | /* write command */ | ||
329 | lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); | ||
330 | |||
331 | snd_BUG_ON(atomic_read(&chip->send_message_locked) != 0); | ||
332 | atomic_set(&chip->send_message_locked, 1); | ||
333 | |||
334 | /* MicoBlaze gogogo */ | ||
335 | lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); | ||
336 | |||
337 | /* wait for interrupt to answer */ | ||
338 | for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS; ++dwloop) { | ||
339 | answer_received = atomic_read(&chip->send_message_locked); | ||
340 | if (answer_received == 0) | ||
341 | break; | ||
342 | msleep(1); | ||
343 | } | ||
344 | |||
345 | if (answer_received == 0) { | ||
346 | /* in Debug mode verify Reg_CSM_MR */ | ||
347 | snd_BUG_ON(!(lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)); | ||
348 | |||
349 | /* command finished, read status */ | ||
350 | if (rmh->dsp_stat == 0) | ||
351 | reg = lx_dsp_reg_read(chip, eReg_CRM1); | ||
352 | else | ||
353 | reg = 0; | ||
354 | } else { | ||
355 | int i; | ||
356 | snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! " | ||
357 | "Interrupts disabled?\n"); | ||
358 | |||
359 | /* attente bit Reg_CSM_MR */ | ||
360 | for (i = 0; i != XILINX_POLL_ITERATIONS; i++) { | ||
361 | if ((lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)) { | ||
362 | if (rmh->dsp_stat == 0) | ||
363 | reg = lx_dsp_reg_read(chip, eReg_CRM1); | ||
364 | else | ||
365 | reg = 0; | ||
366 | goto polling_successful; | ||
367 | } | ||
368 | |||
369 | if (i > XILINX_POLL_NO_SLEEP) | ||
370 | msleep(1); | ||
371 | } | ||
372 | snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! " | ||
373 | "polling failed\n"); | ||
374 | |||
375 | polling_successful: | ||
376 | atomic_set(&chip->send_message_locked, 0); | ||
377 | } | ||
378 | |||
379 | if ((reg & ERROR_VALUE) == 0) { | ||
380 | /* read response */ | ||
381 | if (rmh->stat_len) { | ||
382 | snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); | ||
383 | |||
384 | lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, | ||
385 | rmh->stat_len); | ||
386 | } | ||
387 | } else | ||
388 | snd_printk(KERN_WARNING LXP "lx_message_send: error_value %x\n", | ||
389 | reg); | ||
390 | |||
391 | /* clear Reg_CSM_MR */ | ||
392 | lx_dsp_reg_write(chip, eReg_CSM, 0); | ||
393 | |||
394 | switch (reg) { | ||
395 | case ED_DSP_TIMED_OUT: | ||
396 | snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); | ||
397 | return -ETIMEDOUT; | ||
398 | |||
399 | case ED_DSP_CRASHED: | ||
400 | snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); | ||
401 | return -EAGAIN; | ||
402 | } | ||
403 | |||
404 | lx_message_dump(rmh); | ||
405 | return 0; | ||
406 | } | ||
407 | |||
408 | static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) | ||
409 | { | ||
410 | u32 reg = ED_DSP_TIMED_OUT; | ||
411 | int dwloop; | ||
412 | |||
413 | if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { | ||
414 | snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); | ||
415 | return -EBUSY; | ||
416 | } | ||
417 | |||
418 | /* write command */ | ||
419 | lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); | ||
420 | |||
421 | /* MicoBlaze gogogo */ | ||
422 | lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); | ||
423 | |||
424 | /* wait for interrupt to answer */ | ||
425 | for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { | ||
426 | if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { | ||
427 | if (rmh->dsp_stat == 0) | ||
428 | reg = lx_dsp_reg_read(chip, eReg_CRM1); | ||
429 | else | ||
430 | reg = 0; | ||
431 | goto polling_successful; | ||
432 | } else | ||
433 | udelay(1); | ||
434 | } | ||
435 | snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! " | ||
436 | "polling failed\n"); | ||
437 | |||
438 | polling_successful: | ||
439 | if ((reg & ERROR_VALUE) == 0) { | ||
440 | /* read response */ | ||
441 | if (rmh->stat_len) { | ||
442 | snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); | ||
443 | lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, | ||
444 | rmh->stat_len); | ||
445 | } | ||
446 | } else | ||
447 | snd_printk(LXP "rmh error: %08x\n", reg); | ||
448 | |||
449 | /* clear Reg_CSM_MR */ | ||
450 | lx_dsp_reg_write(chip, eReg_CSM, 0); | ||
451 | |||
452 | switch (reg) { | ||
453 | case ED_DSP_TIMED_OUT: | ||
454 | snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); | ||
455 | return -ETIMEDOUT; | ||
456 | |||
457 | case ED_DSP_CRASHED: | ||
458 | snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); | ||
459 | return -EAGAIN; | ||
460 | } | ||
461 | |||
462 | lx_message_dump(rmh); | ||
463 | |||
464 | return reg; | ||
465 | } | ||
466 | |||
467 | |||
468 | /* low-level dsp access */ | ||
469 | int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) | ||
470 | { | ||
471 | u16 ret; | ||
472 | unsigned long flags; | ||
473 | |||
474 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
475 | |||
476 | lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); | ||
477 | ret = lx_message_send_atomic(chip, &chip->rmh); | ||
478 | |||
479 | *rdsp_version = chip->rmh.stat[1]; | ||
480 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
481 | return ret; | ||
482 | } | ||
483 | |||
484 | int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) | ||
485 | { | ||
486 | u16 ret = 0; | ||
487 | unsigned long flags; | ||
488 | u32 freq_raw = 0; | ||
489 | u32 freq = 0; | ||
490 | u32 frequency = 0; | ||
491 | |||
492 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
493 | |||
494 | lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); | ||
495 | ret = lx_message_send_atomic(chip, &chip->rmh); | ||
496 | |||
497 | if (ret == 0) { | ||
498 | freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; | ||
499 | freq = freq_raw & XES_FREQ_COUNT8_MASK; | ||
500 | |||
501 | if ((freq < XES_FREQ_COUNT8_48_MAX) || | ||
502 | (freq > XES_FREQ_COUNT8_44_MIN)) | ||
503 | frequency = 0; /* unknown */ | ||
504 | else if (freq >= XES_FREQ_COUNT8_44_MAX) | ||
505 | frequency = 44100; | ||
506 | else | ||
507 | frequency = 48000; | ||
508 | } | ||
509 | |||
510 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
511 | |||
512 | *rfreq = frequency * chip->freq_ratio; | ||
513 | |||
514 | return ret; | ||
515 | } | ||
516 | |||
517 | int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address) | ||
518 | { | ||
519 | u32 macmsb, maclsb; | ||
520 | |||
521 | macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; | ||
522 | maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; | ||
523 | |||
524 | /* todo: endianess handling */ | ||
525 | mac_address[5] = ((u8 *)(&maclsb))[0]; | ||
526 | mac_address[4] = ((u8 *)(&maclsb))[1]; | ||
527 | mac_address[3] = ((u8 *)(&maclsb))[2]; | ||
528 | mac_address[2] = ((u8 *)(&macmsb))[0]; | ||
529 | mac_address[1] = ((u8 *)(&macmsb))[1]; | ||
530 | mac_address[0] = ((u8 *)(&macmsb))[2]; | ||
531 | |||
532 | return 0; | ||
533 | } | ||
534 | |||
535 | |||
536 | int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) | ||
537 | { | ||
538 | unsigned long flags; | ||
539 | int ret; | ||
540 | |||
541 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
542 | |||
543 | lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); | ||
544 | chip->rmh.cmd[0] |= gran; | ||
545 | |||
546 | ret = lx_message_send_atomic(chip, &chip->rmh); | ||
547 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
548 | return ret; | ||
549 | } | ||
550 | |||
551 | int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) | ||
552 | { | ||
553 | unsigned long flags; | ||
554 | int ret; | ||
555 | |||
556 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
557 | |||
558 | lx_message_init(&chip->rmh, CMD_04_GET_EVENT); | ||
559 | chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ | ||
560 | |||
561 | ret = lx_message_send_atomic(chip, &chip->rmh); | ||
562 | |||
563 | if (!ret) | ||
564 | memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); | ||
565 | |||
566 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
567 | return ret; | ||
568 | } | ||
569 | |||
570 | #define CSES_TIMEOUT 100 /* microseconds */ | ||
571 | #define CSES_CE 0x0001 | ||
572 | #define CSES_BROADCAST 0x0002 | ||
573 | #define CSES_UPDATE_LDSV 0x0004 | ||
574 | |||
575 | int lx_dsp_es_check_pipeline(struct lx6464es *chip) | ||
576 | { | ||
577 | int i; | ||
578 | |||
579 | for (i = 0; i != CSES_TIMEOUT; ++i) { | ||
580 | /* | ||
581 | * le bit CSES_UPDATE_LDSV est à1 dés que le macprog | ||
582 | * est pret. il re-passe à0 lorsque le premier read a | ||
583 | * été fait. pour l'instant on retire le test car ce bit | ||
584 | * passe a 1 environ 200 à400 ms aprés que le registre | ||
585 | * confES àété écrit (kick du xilinx ES). | ||
586 | * | ||
587 | * On ne teste que le bit CE. | ||
588 | * */ | ||
589 | |||
590 | u32 cses = lx_dsp_reg_read(chip, eReg_CSES); | ||
591 | |||
592 | if ((cses & CSES_CE) == 0) | ||
593 | return 0; | ||
594 | |||
595 | udelay(1); | ||
596 | } | ||
597 | |||
598 | return -ETIMEDOUT; | ||
599 | } | ||
600 | |||
601 | |||
602 | #define PIPE_INFO_TO_CMD(capture, pipe) \ | ||
603 | ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) | ||
604 | |||
605 | |||
606 | |||
607 | /* low-level pipe handling */ | ||
608 | int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, | ||
609 | int channels) | ||
610 | { | ||
611 | int err; | ||
612 | unsigned long flags; | ||
613 | |||
614 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
615 | |||
616 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
617 | lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); | ||
618 | |||
619 | chip->rmh.cmd[0] |= pipe_cmd; | ||
620 | chip->rmh.cmd[0] |= channels; | ||
621 | |||
622 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
623 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
624 | |||
625 | if (err != 0) | ||
626 | snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n"); | ||
627 | |||
628 | return err; | ||
629 | } | ||
630 | |||
631 | int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) | ||
632 | { | ||
633 | int err; | ||
634 | unsigned long flags; | ||
635 | |||
636 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
637 | |||
638 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
639 | lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); | ||
640 | |||
641 | chip->rmh.cmd[0] |= pipe_cmd; | ||
642 | |||
643 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
644 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
645 | |||
646 | return err; | ||
647 | } | ||
648 | |||
649 | int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, | ||
650 | u32 *r_needed, u32 *r_freed, u32 *size_array) | ||
651 | { | ||
652 | int err; | ||
653 | unsigned long flags; | ||
654 | |||
655 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
656 | |||
657 | #ifdef CONFIG_SND_DEBUG | ||
658 | if (size_array) | ||
659 | memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); | ||
660 | #endif | ||
661 | |||
662 | *r_needed = 0; | ||
663 | *r_freed = 0; | ||
664 | |||
665 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
666 | lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); | ||
667 | |||
668 | chip->rmh.cmd[0] |= pipe_cmd; | ||
669 | |||
670 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
671 | |||
672 | if (!err) { | ||
673 | int i; | ||
674 | for (i = 0; i < MAX_STREAM_BUFFER; ++i) { | ||
675 | u32 stat = chip->rmh.stat[i]; | ||
676 | if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { | ||
677 | /* finished */ | ||
678 | *r_freed += 1; | ||
679 | if (size_array) | ||
680 | size_array[i] = stat & MASK_DATA_SIZE; | ||
681 | } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) | ||
682 | == 0) | ||
683 | /* free */ | ||
684 | *r_needed += 1; | ||
685 | } | ||
686 | |||
687 | #if 0 | ||
688 | snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", | ||
689 | *r_needed, *r_freed); | ||
690 | for (i = 0; i < MAX_STREAM_BUFFER; ++i) { | ||
691 | for (i = 0; i != chip->rmh.stat_len; ++i) | ||
692 | snd_printdd(" stat[%d]: %x, %x\n", i, | ||
693 | chip->rmh.stat[i], | ||
694 | chip->rmh.stat[i] & MASK_DATA_SIZE); | ||
695 | } | ||
696 | #endif | ||
697 | } | ||
698 | |||
699 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
700 | return err; | ||
701 | } | ||
702 | |||
703 | |||
704 | int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) | ||
705 | { | ||
706 | int err; | ||
707 | unsigned long flags; | ||
708 | |||
709 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
710 | |||
711 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
712 | lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); | ||
713 | |||
714 | chip->rmh.cmd[0] |= pipe_cmd; | ||
715 | |||
716 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
717 | |||
718 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
719 | return err; | ||
720 | } | ||
721 | |||
722 | static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) | ||
723 | { | ||
724 | int err; | ||
725 | unsigned long flags; | ||
726 | |||
727 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
728 | |||
729 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
730 | lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); | ||
731 | |||
732 | chip->rmh.cmd[0] |= pipe_cmd; | ||
733 | |||
734 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
735 | |||
736 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
737 | return err; | ||
738 | } | ||
739 | |||
740 | |||
741 | int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) | ||
742 | { | ||
743 | int err; | ||
744 | |||
745 | err = lx_pipe_wait_for_idle(chip, pipe, is_capture); | ||
746 | if (err < 0) | ||
747 | return err; | ||
748 | |||
749 | err = lx_pipe_toggle_state(chip, pipe, is_capture); | ||
750 | |||
751 | return err; | ||
752 | } | ||
753 | |||
754 | int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) | ||
755 | { | ||
756 | int err = 0; | ||
757 | |||
758 | err = lx_pipe_wait_for_start(chip, pipe, is_capture); | ||
759 | if (err < 0) | ||
760 | return err; | ||
761 | |||
762 | err = lx_pipe_toggle_state(chip, pipe, is_capture); | ||
763 | |||
764 | return err; | ||
765 | } | ||
766 | |||
767 | |||
768 | int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, | ||
769 | u64 *rsample_count) | ||
770 | { | ||
771 | int err; | ||
772 | unsigned long flags; | ||
773 | |||
774 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
775 | |||
776 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
777 | lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); | ||
778 | |||
779 | chip->rmh.cmd[0] |= pipe_cmd; | ||
780 | chip->rmh.stat_len = 2; /* need all words here! */ | ||
781 | |||
782 | err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ | ||
783 | |||
784 | if (err != 0) | ||
785 | snd_printk(KERN_ERR | ||
786 | "lx6464es: could not query pipe's sample count\n"); | ||
787 | else { | ||
788 | *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) | ||
789 | << 24) /* hi part */ | ||
790 | + chip->rmh.stat[1]; /* lo part */ | ||
791 | } | ||
792 | |||
793 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
794 | return err; | ||
795 | } | ||
796 | |||
797 | int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) | ||
798 | { | ||
799 | int err; | ||
800 | unsigned long flags; | ||
801 | |||
802 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
803 | |||
804 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
805 | lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); | ||
806 | |||
807 | chip->rmh.cmd[0] |= pipe_cmd; | ||
808 | |||
809 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
810 | |||
811 | if (err != 0) | ||
812 | snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n"); | ||
813 | else | ||
814 | *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; | ||
815 | |||
816 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
817 | return err; | ||
818 | } | ||
819 | |||
820 | static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, | ||
821 | int is_capture, u16 state) | ||
822 | { | ||
823 | int i; | ||
824 | |||
825 | /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: | ||
826 | * timeout 50 ms */ | ||
827 | for (i = 0; i != 50; ++i) { | ||
828 | u16 current_state; | ||
829 | int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); | ||
830 | |||
831 | if (err < 0) | ||
832 | return err; | ||
833 | |||
834 | if (current_state == state) | ||
835 | return 0; | ||
836 | |||
837 | mdelay(1); | ||
838 | } | ||
839 | |||
840 | return -ETIMEDOUT; | ||
841 | } | ||
842 | |||
843 | int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) | ||
844 | { | ||
845 | return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); | ||
846 | } | ||
847 | |||
848 | int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) | ||
849 | { | ||
850 | return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); | ||
851 | } | ||
852 | |||
853 | /* low-level stream handling */ | ||
854 | int lx_stream_set_state(struct lx6464es *chip, u32 pipe, | ||
855 | int is_capture, enum stream_state_t state) | ||
856 | { | ||
857 | int err; | ||
858 | unsigned long flags; | ||
859 | |||
860 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
861 | |||
862 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
863 | lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); | ||
864 | |||
865 | chip->rmh.cmd[0] |= pipe_cmd; | ||
866 | chip->rmh.cmd[0] |= state; | ||
867 | |||
868 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
869 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
870 | |||
871 | return err; | ||
872 | } | ||
873 | |||
874 | int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, | ||
875 | u32 pipe, int is_capture) | ||
876 | { | ||
877 | int err; | ||
878 | unsigned long flags; | ||
879 | |||
880 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
881 | |||
882 | u32 channels = runtime->channels; | ||
883 | |||
884 | if (runtime->channels != channels) | ||
885 | snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d", | ||
886 | runtime->channels, channels); | ||
887 | |||
888 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
889 | lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); | ||
890 | |||
891 | chip->rmh.cmd[0] |= pipe_cmd; | ||
892 | |||
893 | if (runtime->sample_bits == 16) | ||
894 | /* 16 bit format */ | ||
895 | chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); | ||
896 | |||
897 | if (snd_pcm_format_little_endian(runtime->format)) | ||
898 | /* little endian/intel format */ | ||
899 | chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); | ||
900 | |||
901 | chip->rmh.cmd[0] |= channels-1; | ||
902 | |||
903 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
904 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
905 | |||
906 | return err; | ||
907 | } | ||
908 | |||
909 | int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, | ||
910 | int *rstate) | ||
911 | { | ||
912 | int err; | ||
913 | unsigned long flags; | ||
914 | |||
915 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
916 | |||
917 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
918 | lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); | ||
919 | |||
920 | chip->rmh.cmd[0] |= pipe_cmd; | ||
921 | |||
922 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
923 | |||
924 | *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; | ||
925 | |||
926 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
927 | return err; | ||
928 | } | ||
929 | |||
930 | int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, | ||
931 | u64 *r_bytepos) | ||
932 | { | ||
933 | int err; | ||
934 | unsigned long flags; | ||
935 | |||
936 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
937 | |||
938 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
939 | lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); | ||
940 | |||
941 | chip->rmh.cmd[0] |= pipe_cmd; | ||
942 | |||
943 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
944 | |||
945 | *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) | ||
946 | << 32) /* hi part */ | ||
947 | + chip->rmh.stat[1]; /* lo part */ | ||
948 | |||
949 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
950 | return err; | ||
951 | } | ||
952 | |||
953 | /* low-level buffer handling */ | ||
954 | int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, | ||
955 | u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, | ||
956 | u32 *r_buffer_index) | ||
957 | { | ||
958 | int err; | ||
959 | unsigned long flags; | ||
960 | |||
961 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
962 | |||
963 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
964 | lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); | ||
965 | |||
966 | chip->rmh.cmd[0] |= pipe_cmd; | ||
967 | chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ | ||
968 | |||
969 | /* todo: pause request, circular buffer */ | ||
970 | |||
971 | chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; | ||
972 | chip->rmh.cmd[2] = buf_address_lo; | ||
973 | |||
974 | if (buf_address_hi) { | ||
975 | chip->rmh.cmd_len = 4; | ||
976 | chip->rmh.cmd[3] = buf_address_hi; | ||
977 | chip->rmh.cmd[0] |= BF_64BITS_ADR; | ||
978 | } | ||
979 | |||
980 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
981 | |||
982 | if (err == 0) { | ||
983 | *r_buffer_index = chip->rmh.stat[0]; | ||
984 | goto done; | ||
985 | } | ||
986 | |||
987 | if (err == EB_RBUFFERS_TABLE_OVERFLOW) | ||
988 | snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); | ||
989 | |||
990 | if (err == EB_INVALID_STREAM) | ||
991 | snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n"); | ||
992 | |||
993 | if (err == EB_CMD_REFUSED) | ||
994 | snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n"); | ||
995 | |||
996 | done: | ||
997 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
998 | return err; | ||
999 | } | ||
1000 | |||
1001 | int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, | ||
1002 | u32 *r_buffer_size) | ||
1003 | { | ||
1004 | int err; | ||
1005 | unsigned long flags; | ||
1006 | |||
1007 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
1008 | |||
1009 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
1010 | lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); | ||
1011 | |||
1012 | chip->rmh.cmd[0] |= pipe_cmd; | ||
1013 | chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the | ||
1014 | * microblaze will seek for it */ | ||
1015 | |||
1016 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
1017 | |||
1018 | if (err == 0) | ||
1019 | *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; | ||
1020 | |||
1021 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
1022 | return err; | ||
1023 | } | ||
1024 | |||
1025 | int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, | ||
1026 | u32 buffer_index) | ||
1027 | { | ||
1028 | int err; | ||
1029 | unsigned long flags; | ||
1030 | |||
1031 | u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); | ||
1032 | |||
1033 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
1034 | lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); | ||
1035 | |||
1036 | chip->rmh.cmd[0] |= pipe_cmd; | ||
1037 | chip->rmh.cmd[0] |= buffer_index; | ||
1038 | |||
1039 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
1040 | |||
1041 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
1042 | return err; | ||
1043 | } | ||
1044 | |||
1045 | |||
1046 | /* low-level gain/peak handling | ||
1047 | * | ||
1048 | * \todo: can we unmute capture/playback channels independently? | ||
1049 | * | ||
1050 | * */ | ||
1051 | int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) | ||
1052 | { | ||
1053 | int err; | ||
1054 | unsigned long flags; | ||
1055 | |||
1056 | /* bit set to 1: channel muted */ | ||
1057 | u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; | ||
1058 | |||
1059 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
1060 | lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); | ||
1061 | |||
1062 | chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); | ||
1063 | |||
1064 | chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ | ||
1065 | chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ | ||
1066 | |||
1067 | snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], | ||
1068 | chip->rmh.cmd[2]); | ||
1069 | |||
1070 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
1071 | |||
1072 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
1073 | return err; | ||
1074 | } | ||
1075 | |||
1076 | static u32 peak_map[] = { | ||
1077 | 0x00000109, /* -90.308dB */ | ||
1078 | 0x0000083B, /* -72.247dB */ | ||
1079 | 0x000020C4, /* -60.205dB */ | ||
1080 | 0x00008273, /* -48.030dB */ | ||
1081 | 0x00020756, /* -36.005dB */ | ||
1082 | 0x00040C37, /* -30.001dB */ | ||
1083 | 0x00081385, /* -24.002dB */ | ||
1084 | 0x00101D3F, /* -18.000dB */ | ||
1085 | 0x0016C310, /* -15.000dB */ | ||
1086 | 0x002026F2, /* -12.001dB */ | ||
1087 | 0x002D6A86, /* -9.000dB */ | ||
1088 | 0x004026E6, /* -6.004dB */ | ||
1089 | 0x005A9DF6, /* -3.000dB */ | ||
1090 | 0x0065AC8B, /* -2.000dB */ | ||
1091 | 0x00721481, /* -1.000dB */ | ||
1092 | 0x007FFFFF, /* FS */ | ||
1093 | }; | ||
1094 | |||
1095 | int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, | ||
1096 | u32 *r_levels) | ||
1097 | { | ||
1098 | int err = 0; | ||
1099 | unsigned long flags; | ||
1100 | int i; | ||
1101 | spin_lock_irqsave(&chip->msg_lock, flags); | ||
1102 | |||
1103 | for (i = 0; i < channels; i += 4) { | ||
1104 | u32 s0, s1, s2, s3; | ||
1105 | |||
1106 | lx_message_init(&chip->rmh, CMD_12_GET_PEAK); | ||
1107 | chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); | ||
1108 | |||
1109 | err = lx_message_send_atomic(chip, &chip->rmh); | ||
1110 | |||
1111 | if (err == 0) { | ||
1112 | s0 = peak_map[chip->rmh.stat[0] & 0x0F]; | ||
1113 | s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; | ||
1114 | s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; | ||
1115 | s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; | ||
1116 | } else | ||
1117 | s0 = s1 = s2 = s3 = 0; | ||
1118 | |||
1119 | r_levels[0] = s0; | ||
1120 | r_levels[1] = s1; | ||
1121 | r_levels[2] = s2; | ||
1122 | r_levels[3] = s3; | ||
1123 | |||
1124 | r_levels += 4; | ||
1125 | } | ||
1126 | |||
1127 | spin_unlock_irqrestore(&chip->msg_lock, flags); | ||
1128 | return err; | ||
1129 | } | ||
1130 | |||
1131 | /* interrupt handling */ | ||
1132 | #define PCX_IRQ_NONE 0 | ||
1133 | #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */ | ||
1134 | #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */ | ||
1135 | #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */ | ||
1136 | |||
1137 | static u32 lx_interrupt_test_ack(struct lx6464es *chip) | ||
1138 | { | ||
1139 | u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); | ||
1140 | |||
1141 | /* Test if PCI Doorbell interrupt is active */ | ||
1142 | if (irqcs & IRQCS_ACTIVE_PCIDB) { | ||
1143 | u32 temp; | ||
1144 | irqcs = PCX_IRQ_NONE; | ||
1145 | |||
1146 | while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { | ||
1147 | /* RAZ interrupt */ | ||
1148 | irqcs |= temp; | ||
1149 | lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); | ||
1150 | } | ||
1151 | |||
1152 | return irqcs; | ||
1153 | } | ||
1154 | return PCX_IRQ_NONE; | ||
1155 | } | ||
1156 | |||
1157 | static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, | ||
1158 | int *r_async_pending, int *r_async_escmd) | ||
1159 | { | ||
1160 | u32 irq_async; | ||
1161 | u32 irqsrc = lx_interrupt_test_ack(chip); | ||
1162 | |||
1163 | if (irqsrc == PCX_IRQ_NONE) | ||
1164 | return 0; | ||
1165 | |||
1166 | *r_irqsrc = irqsrc; | ||
1167 | |||
1168 | irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response | ||
1169 | * (set by xilinx) + EOB */ | ||
1170 | |||
1171 | if (irq_async & MASK_SYS_STATUS_ESA) { | ||
1172 | irq_async &= ~MASK_SYS_STATUS_ESA; | ||
1173 | *r_async_escmd = 1; | ||
1174 | } | ||
1175 | |||
1176 | if (irqsrc & MASK_SYS_STATUS_CMD_DONE) | ||
1177 | /* xilinx command notification */ | ||
1178 | atomic_set(&chip->send_message_locked, 0); | ||
1179 | |||
1180 | if (irq_async) { | ||
1181 | /* snd_printd("interrupt: async event pending\n"); */ | ||
1182 | *r_async_pending = 1; | ||
1183 | } | ||
1184 | |||
1185 | return 1; | ||
1186 | } | ||
1187 | |||
1188 | static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, | ||
1189 | int *r_freq_changed, | ||
1190 | u64 *r_notified_in_pipe_mask, | ||
1191 | u64 *r_notified_out_pipe_mask) | ||
1192 | { | ||
1193 | int err; | ||
1194 | u32 stat[9]; /* answer from CMD_04_GET_EVENT */ | ||
1195 | |||
1196 | /* On peut optimiser pour ne pas lire les evenements vides | ||
1197 | * les mots de réponse sont dans l'ordre suivant : | ||
1198 | * Stat[0] mot de status général | ||
1199 | * Stat[1] fin de buffer OUT pF | ||
1200 | * Stat[2] fin de buffer OUT pf | ||
1201 | * Stat[3] fin de buffer IN pF | ||
1202 | * Stat[4] fin de buffer IN pf | ||
1203 | * Stat[5] underrun poid fort | ||
1204 | * Stat[6] underrun poid faible | ||
1205 | * Stat[7] overrun poid fort | ||
1206 | * Stat[8] overrun poid faible | ||
1207 | * */ | ||
1208 | |||
1209 | u64 orun_mask; | ||
1210 | u64 urun_mask; | ||
1211 | #if 0 | ||
1212 | int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0; | ||
1213 | int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0; | ||
1214 | #endif | ||
1215 | int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; | ||
1216 | int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; | ||
1217 | |||
1218 | *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; | ||
1219 | |||
1220 | err = lx_dsp_read_async_events(chip, stat); | ||
1221 | if (err < 0) | ||
1222 | return err; | ||
1223 | |||
1224 | if (eb_pending_in) { | ||
1225 | *r_notified_in_pipe_mask = ((u64)stat[3] << 32) | ||
1226 | + stat[4]; | ||
1227 | snd_printdd(LXP "interrupt: EOBI pending %llx\n", | ||
1228 | *r_notified_in_pipe_mask); | ||
1229 | } | ||
1230 | if (eb_pending_out) { | ||
1231 | *r_notified_out_pipe_mask = ((u64)stat[1] << 32) | ||
1232 | + stat[2]; | ||
1233 | snd_printdd(LXP "interrupt: EOBO pending %llx\n", | ||
1234 | *r_notified_out_pipe_mask); | ||
1235 | } | ||
1236 | |||
1237 | orun_mask = ((u64)stat[7] << 32) + stat[8]; | ||
1238 | urun_mask = ((u64)stat[5] << 32) + stat[6]; | ||
1239 | |||
1240 | /* todo: handle xrun notification */ | ||
1241 | |||
1242 | return err; | ||
1243 | } | ||
1244 | |||
1245 | static int lx_interrupt_request_new_buffer(struct lx6464es *chip, | ||
1246 | struct lx_stream *lx_stream) | ||
1247 | { | ||
1248 | struct snd_pcm_substream *substream = lx_stream->stream; | ||
1249 | int is_capture = lx_stream->is_capture; | ||
1250 | int err; | ||
1251 | unsigned long flags; | ||
1252 | |||
1253 | const u32 channels = substream->runtime->channels; | ||
1254 | const u32 bytes_per_frame = channels * 3; | ||
1255 | const u32 period_size = substream->runtime->period_size; | ||
1256 | const u32 period_bytes = period_size * bytes_per_frame; | ||
1257 | const u32 pos = lx_stream->frame_pos; | ||
1258 | const u32 next_pos = ((pos+1) == substream->runtime->periods) ? | ||
1259 | 0 : pos + 1; | ||
1260 | |||
1261 | dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; | ||
1262 | u32 buf_hi = 0; | ||
1263 | u32 buf_lo = 0; | ||
1264 | u32 buffer_index = 0; | ||
1265 | |||
1266 | u32 needed, freed; | ||
1267 | u32 size_array[MAX_STREAM_BUFFER]; | ||
1268 | |||
1269 | snd_printdd("->lx_interrupt_request_new_buffer\n"); | ||
1270 | |||
1271 | spin_lock_irqsave(&chip->lock, flags); | ||
1272 | |||
1273 | err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); | ||
1274 | snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed); | ||
1275 | |||
1276 | unpack_pointer(buf, &buf_lo, &buf_hi); | ||
1277 | err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, | ||
1278 | &buffer_index); | ||
1279 | snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n", | ||
1280 | buffer_index, (void *)buf, period_bytes); | ||
1281 | |||
1282 | lx_stream->frame_pos = next_pos; | ||
1283 | spin_unlock_irqrestore(&chip->lock, flags); | ||
1284 | |||
1285 | return err; | ||
1286 | } | ||
1287 | |||
1288 | void lx_tasklet_playback(unsigned long data) | ||
1289 | { | ||
1290 | struct lx6464es *chip = (struct lx6464es *)data; | ||
1291 | struct lx_stream *lx_stream = &chip->playback_stream; | ||
1292 | int err; | ||
1293 | |||
1294 | snd_printdd("->lx_tasklet_playback\n"); | ||
1295 | |||
1296 | err = lx_interrupt_request_new_buffer(chip, lx_stream); | ||
1297 | if (err < 0) | ||
1298 | snd_printk(KERN_ERR LXP | ||
1299 | "cannot request new buffer for playback\n"); | ||
1300 | |||
1301 | snd_pcm_period_elapsed(lx_stream->stream); | ||
1302 | } | ||
1303 | |||
1304 | void lx_tasklet_capture(unsigned long data) | ||
1305 | { | ||
1306 | struct lx6464es *chip = (struct lx6464es *)data; | ||
1307 | struct lx_stream *lx_stream = &chip->capture_stream; | ||
1308 | int err; | ||
1309 | |||
1310 | snd_printdd("->lx_tasklet_capture\n"); | ||
1311 | err = lx_interrupt_request_new_buffer(chip, lx_stream); | ||
1312 | if (err < 0) | ||
1313 | snd_printk(KERN_ERR LXP | ||
1314 | "cannot request new buffer for capture\n"); | ||
1315 | |||
1316 | snd_pcm_period_elapsed(lx_stream->stream); | ||
1317 | } | ||
1318 | |||
1319 | |||
1320 | |||
1321 | static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, | ||
1322 | u64 notified_in_pipe_mask, | ||
1323 | u64 notified_out_pipe_mask) | ||
1324 | { | ||
1325 | int err = 0; | ||
1326 | |||
1327 | if (notified_in_pipe_mask) { | ||
1328 | snd_printdd(LXP "requesting audio transfer for capture\n"); | ||
1329 | tasklet_hi_schedule(&chip->tasklet_capture); | ||
1330 | } | ||
1331 | |||
1332 | if (notified_out_pipe_mask) { | ||
1333 | snd_printdd(LXP "requesting audio transfer for playback\n"); | ||
1334 | tasklet_hi_schedule(&chip->tasklet_playback); | ||
1335 | } | ||
1336 | |||
1337 | return err; | ||
1338 | } | ||
1339 | |||
1340 | |||
1341 | irqreturn_t lx_interrupt(int irq, void *dev_id) | ||
1342 | { | ||
1343 | struct lx6464es *chip = dev_id; | ||
1344 | int async_pending, async_escmd; | ||
1345 | u32 irqsrc; | ||
1346 | |||
1347 | spin_lock(&chip->lock); | ||
1348 | |||
1349 | snd_printdd("**************************************************\n"); | ||
1350 | |||
1351 | if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { | ||
1352 | spin_unlock(&chip->lock); | ||
1353 | snd_printdd("IRQ_NONE\n"); | ||
1354 | return IRQ_NONE; /* this device did not cause the interrupt */ | ||
1355 | } | ||
1356 | |||
1357 | if (irqsrc & MASK_SYS_STATUS_CMD_DONE) | ||
1358 | goto exit; | ||
1359 | |||
1360 | #if 0 | ||
1361 | if (irqsrc & MASK_SYS_STATUS_EOBI) | ||
1362 | snd_printdd(LXP "interrupt: EOBI\n"); | ||
1363 | |||
1364 | if (irqsrc & MASK_SYS_STATUS_EOBO) | ||
1365 | snd_printdd(LXP "interrupt: EOBO\n"); | ||
1366 | |||
1367 | if (irqsrc & MASK_SYS_STATUS_URUN) | ||
1368 | snd_printdd(LXP "interrupt: URUN\n"); | ||
1369 | |||
1370 | if (irqsrc & MASK_SYS_STATUS_ORUN) | ||
1371 | snd_printdd(LXP "interrupt: ORUN\n"); | ||
1372 | #endif | ||
1373 | |||
1374 | if (async_pending) { | ||
1375 | u64 notified_in_pipe_mask = 0; | ||
1376 | u64 notified_out_pipe_mask = 0; | ||
1377 | int freq_changed; | ||
1378 | int err; | ||
1379 | |||
1380 | /* handle async events */ | ||
1381 | err = lx_interrupt_handle_async_events(chip, irqsrc, | ||
1382 | &freq_changed, | ||
1383 | ¬ified_in_pipe_mask, | ||
1384 | ¬ified_out_pipe_mask); | ||
1385 | if (err) | ||
1386 | snd_printk(KERN_ERR LXP | ||
1387 | "error handling async events\n"); | ||
1388 | |||
1389 | err = lx_interrupt_handle_audio_transfer(chip, | ||
1390 | notified_in_pipe_mask, | ||
1391 | notified_out_pipe_mask | ||
1392 | ); | ||
1393 | if (err) | ||
1394 | snd_printk(KERN_ERR LXP | ||
1395 | "error during audio transfer\n"); | ||
1396 | } | ||
1397 | |||
1398 | if (async_escmd) { | ||
1399 | #if 0 | ||
1400 | /* backdoor for ethersound commands | ||
1401 | * | ||
1402 | * for now, we do not need this | ||
1403 | * | ||
1404 | * */ | ||
1405 | |||
1406 | snd_printdd("lx6464es: interrupt requests escmd handling\n"); | ||
1407 | #endif | ||
1408 | } | ||
1409 | |||
1410 | exit: | ||
1411 | spin_unlock(&chip->lock); | ||
1412 | return IRQ_HANDLED; /* this device caused the interrupt */ | ||
1413 | } | ||
1414 | |||
1415 | |||
1416 | static void lx_irq_set(struct lx6464es *chip, int enable) | ||
1417 | { | ||
1418 | u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); | ||
1419 | |||
1420 | /* enable/disable interrupts | ||
1421 | * | ||
1422 | * Set the Doorbell and PCI interrupt enable bits | ||
1423 | * | ||
1424 | * */ | ||
1425 | if (enable) | ||
1426 | reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); | ||
1427 | else | ||
1428 | reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); | ||
1429 | lx_plx_reg_write(chip, ePLX_IRQCS, reg); | ||
1430 | } | ||
1431 | |||
1432 | void lx_irq_enable(struct lx6464es *chip) | ||
1433 | { | ||
1434 | snd_printdd("->lx_irq_enable\n"); | ||
1435 | lx_irq_set(chip, 1); | ||
1436 | } | ||
1437 | |||
1438 | void lx_irq_disable(struct lx6464es *chip) | ||
1439 | { | ||
1440 | snd_printdd("->lx_irq_disable\n"); | ||
1441 | lx_irq_set(chip, 0); | ||
1442 | } | ||
diff --git a/sound/pci/lx6464es/lx_core.h b/sound/pci/lx6464es/lx_core.h new file mode 100644 index 000000000000..6bd9cbbbc68d --- /dev/null +++ b/sound/pci/lx6464es/lx_core.h | |||
@@ -0,0 +1,242 @@ | |||
1 | /* -*- linux-c -*- * | ||
2 | * | ||
3 | * ALSA driver for the digigram lx6464es interface | ||
4 | * low-level interface | ||
5 | * | ||
6 | * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, write to | ||
20 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | ||
21 | * Boston, MA 02111-1307, USA. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef LX_CORE_H | ||
26 | #define LX_CORE_H | ||
27 | |||
28 | #include <linux/interrupt.h> | ||
29 | |||
30 | #include "lx_defs.h" | ||
31 | |||
32 | #define REG_CRM_NUMBER 12 | ||
33 | |||
34 | struct lx6464es; | ||
35 | |||
36 | /* low-level register access */ | ||
37 | |||
38 | /* dsp register access */ | ||
39 | enum { | ||
40 | eReg_BASE, | ||
41 | eReg_CSM, | ||
42 | eReg_CRM1, | ||
43 | eReg_CRM2, | ||
44 | eReg_CRM3, | ||
45 | eReg_CRM4, | ||
46 | eReg_CRM5, | ||
47 | eReg_CRM6, | ||
48 | eReg_CRM7, | ||
49 | eReg_CRM8, | ||
50 | eReg_CRM9, | ||
51 | eReg_CRM10, | ||
52 | eReg_CRM11, | ||
53 | eReg_CRM12, | ||
54 | |||
55 | eReg_ICR, | ||
56 | eReg_CVR, | ||
57 | eReg_ISR, | ||
58 | eReg_RXHTXH, | ||
59 | eReg_RXMTXM, | ||
60 | eReg_RHLTXL, | ||
61 | eReg_RESETDSP, | ||
62 | |||
63 | eReg_CSUF, | ||
64 | eReg_CSES, | ||
65 | eReg_CRESMSB, | ||
66 | eReg_CRESLSB, | ||
67 | eReg_ADMACESMSB, | ||
68 | eReg_ADMACESLSB, | ||
69 | eReg_CONFES, | ||
70 | |||
71 | eMaxPortLx | ||
72 | }; | ||
73 | |||
74 | unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port); | ||
75 | void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len); | ||
76 | void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data); | ||
77 | void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data, | ||
78 | u32 len); | ||
79 | |||
80 | /* plx register access */ | ||
81 | enum { | ||
82 | ePLX_PCICR, | ||
83 | |||
84 | ePLX_MBOX0, | ||
85 | ePLX_MBOX1, | ||
86 | ePLX_MBOX2, | ||
87 | ePLX_MBOX3, | ||
88 | ePLX_MBOX4, | ||
89 | ePLX_MBOX5, | ||
90 | ePLX_MBOX6, | ||
91 | ePLX_MBOX7, | ||
92 | |||
93 | ePLX_L2PCIDB, | ||
94 | ePLX_IRQCS, | ||
95 | ePLX_CHIPSC, | ||
96 | |||
97 | eMaxPort | ||
98 | }; | ||
99 | |||
100 | unsigned long lx_plx_reg_read(struct lx6464es *chip, int port); | ||
101 | void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data); | ||
102 | |||
103 | /* rhm */ | ||
104 | struct lx_rmh { | ||
105 | u16 cmd_len; /* length of the command to send (WORDs) */ | ||
106 | u16 stat_len; /* length of the status received (WORDs) */ | ||
107 | u16 dsp_stat; /* status type, RMP_SSIZE_XXX */ | ||
108 | u16 cmd_idx; /* index of the command */ | ||
109 | u32 cmd[REG_CRM_NUMBER]; | ||
110 | u32 stat[REG_CRM_NUMBER]; | ||
111 | }; | ||
112 | |||
113 | |||
114 | /* low-level dsp access */ | ||
115 | int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version); | ||
116 | int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq); | ||
117 | int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran); | ||
118 | int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data); | ||
119 | int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address); | ||
120 | |||
121 | |||
122 | /* low-level pipe handling */ | ||
123 | int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, | ||
124 | int channels); | ||
125 | int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture); | ||
126 | int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, | ||
127 | u64 *rsample_count); | ||
128 | int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate); | ||
129 | int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture); | ||
130 | int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture); | ||
131 | int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture); | ||
132 | |||
133 | int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture); | ||
134 | int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture); | ||
135 | |||
136 | /* low-level stream handling */ | ||
137 | int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, | ||
138 | u32 pipe, int is_capture); | ||
139 | int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, | ||
140 | int *rstate); | ||
141 | int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, | ||
142 | u64 *r_bytepos); | ||
143 | |||
144 | int lx_stream_set_state(struct lx6464es *chip, u32 pipe, | ||
145 | int is_capture, enum stream_state_t state); | ||
146 | |||
147 | static inline int lx_stream_start(struct lx6464es *chip, u32 pipe, | ||
148 | int is_capture) | ||
149 | { | ||
150 | snd_printdd("->lx_stream_start\n"); | ||
151 | return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN); | ||
152 | } | ||
153 | |||
154 | static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe, | ||
155 | int is_capture) | ||
156 | { | ||
157 | snd_printdd("->lx_stream_pause\n"); | ||
158 | return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE); | ||
159 | } | ||
160 | |||
161 | static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe, | ||
162 | int is_capture) | ||
163 | { | ||
164 | snd_printdd("->lx_stream_stop\n"); | ||
165 | return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP); | ||
166 | } | ||
167 | |||
168 | /* low-level buffer handling */ | ||
169 | int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, | ||
170 | u32 *r_needed, u32 *r_freed, u32 *size_array); | ||
171 | int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, | ||
172 | u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, | ||
173 | u32 *r_buffer_index); | ||
174 | int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, | ||
175 | u32 *r_buffer_size); | ||
176 | int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, | ||
177 | u32 buffer_index); | ||
178 | |||
179 | /* low-level gain/peak handling */ | ||
180 | int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute); | ||
181 | int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, | ||
182 | u32 *r_levels); | ||
183 | |||
184 | |||
185 | /* interrupt handling */ | ||
186 | irqreturn_t lx_interrupt(int irq, void *dev_id); | ||
187 | void lx_irq_enable(struct lx6464es *chip); | ||
188 | void lx_irq_disable(struct lx6464es *chip); | ||
189 | |||
190 | void lx_tasklet_capture(unsigned long data); | ||
191 | void lx_tasklet_playback(unsigned long data); | ||
192 | |||
193 | |||
194 | /* Stream Format Header Defines (for LIN and IEEE754) */ | ||
195 | #define HEADER_FMT_BASE HEADER_FMT_BASE_LIN | ||
196 | #define HEADER_FMT_BASE_LIN 0xFED00000 | ||
197 | #define HEADER_FMT_BASE_FLOAT 0xFAD00000 | ||
198 | #define HEADER_FMT_MONO 0x00000080 /* bit 23 in header_lo. WARNING: old | ||
199 | * bit 22 is ignored in float | ||
200 | * format */ | ||
201 | #define HEADER_FMT_INTEL 0x00008000 | ||
202 | #define HEADER_FMT_16BITS 0x00002000 | ||
203 | #define HEADER_FMT_24BITS 0x00004000 | ||
204 | #define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k. | ||
205 | * */ | ||
206 | #define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less | ||
207 | * then 32k.*/ | ||
208 | |||
209 | |||
210 | #define BIT_FMP_HEADER 23 | ||
211 | #define BIT_FMP_SD 22 | ||
212 | #define BIT_FMP_MULTICHANNEL 19 | ||
213 | |||
214 | #define START_STATE 1 | ||
215 | #define PAUSE_STATE 0 | ||
216 | |||
217 | |||
218 | |||
219 | |||
220 | |||
221 | /* from PcxAll_e.h */ | ||
222 | /* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */ | ||
223 | #define START_PAUSE_IMMEDIATE 0 | ||
224 | #define START_PAUSE_ON_SYNCHRO 1 | ||
225 | #define START_PAUSE_ON_TIME_CODE 2 | ||
226 | |||
227 | |||
228 | /* Pipe / Stream state */ | ||
229 | #define START_STATE 1 | ||
230 | #define PAUSE_STATE 0 | ||
231 | |||
232 | static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high) | ||
233 | { | ||
234 | *r_low = (u32)(ptr & 0xffffffff); | ||
235 | #if BITS_PER_LONG == 32 | ||
236 | *r_high = 0; | ||
237 | #else | ||
238 | *r_high = (u32)((u64)ptr>>32); | ||
239 | #endif | ||
240 | } | ||
241 | |||
242 | #endif /* LX_CORE_H */ | ||
diff --git a/sound/pci/lx6464es/lx_defs.h b/sound/pci/lx6464es/lx_defs.h new file mode 100644 index 000000000000..49d36bdd512c --- /dev/null +++ b/sound/pci/lx6464es/lx_defs.h | |||
@@ -0,0 +1,376 @@ | |||
1 | /* -*- linux-c -*- * | ||
2 | * | ||
3 | * ALSA driver for the digigram lx6464es interface | ||
4 | * adapted upstream headers | ||
5 | * | ||
6 | * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, write to | ||
20 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | ||
21 | * Boston, MA 02111-1307, USA. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef LX_DEFS_H | ||
26 | #define LX_DEFS_H | ||
27 | |||
28 | /* code adapted from ethersound.h */ | ||
29 | #define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */ | ||
30 | #define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M / | ||
31 | * [ 44k - ( 44.1k + 48k ) / 2 ] | ||
32 | * * 8 */ | ||
33 | #define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ] | ||
34 | * * 8 */ | ||
35 | #define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M / | ||
36 | * [ 48k + ( 44.1k + 48k ) / 2 ] | ||
37 | * * 8 */ | ||
38 | |||
39 | /* code adapted from LXES_registers.h */ | ||
40 | |||
41 | #define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the | ||
42 | * ConfES register. */ | ||
43 | #define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the | ||
44 | * ConfES register. */ | ||
45 | #define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the | ||
46 | * ConfES register. */ | ||
47 | #define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio: | ||
48 | * sample rate = frequency rate. */ | ||
49 | |||
50 | #define CONFES_READ_PART_MASK 0x00070000 | ||
51 | #define CONFES_WRITE_PART_MASK 0x00F80000 | ||
52 | |||
53 | /* code adapted from if_drv_mb.h */ | ||
54 | |||
55 | #define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if | ||
56 | * not yet pending */ | ||
57 | #define MASK_SYS_STATUS_URUN (1L << 30) | ||
58 | #define MASK_SYS_STATUS_ORUN (1L << 29) | ||
59 | #define MASK_SYS_STATUS_EOBO (1L << 28) | ||
60 | #define MASK_SYS_STATUS_EOBI (1L << 27) | ||
61 | #define MASK_SYS_STATUS_FREQ (1L << 26) | ||
62 | #define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the | ||
63 | * XES */ | ||
64 | #define MASK_SYS_STATUS_TIMER (1L << 24) | ||
65 | |||
66 | #define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \ | ||
67 | MASK_SYS_STATUS_URUN | \ | ||
68 | MASK_SYS_STATUS_ORUN | \ | ||
69 | MASK_SYS_STATUS_EOBO | \ | ||
70 | MASK_SYS_STATUS_EOBI | \ | ||
71 | MASK_SYS_STATUS_FREQ | \ | ||
72 | MASK_SYS_STATUS_ESA) | ||
73 | |||
74 | #define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \ | ||
75 | MASK_SYS_STATUS_TIMER) | ||
76 | |||
77 | #define MASK_SYS_TIMER_COUNT 0x0000FFFF | ||
78 | |||
79 | #define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains | ||
80 | * internal: reserved fo end | ||
81 | * of plx dma */ | ||
82 | #define MASK_SYS_STATUS_XES (1L << 21) /* event that remains | ||
83 | * internal: pending XES | ||
84 | * IRQ */ | ||
85 | #define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command | ||
86 | * management: notify driver | ||
87 | * instead of polling */ | ||
88 | |||
89 | |||
90 | #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */ | ||
91 | |||
92 | #define MICROBLAZE_IBL_MIN 32 | ||
93 | #define MICROBLAZE_IBL_DEFAULT 128 | ||
94 | #define MICROBLAZE_IBL_MAX 512 | ||
95 | /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */ | ||
96 | |||
97 | |||
98 | |||
99 | /* command opcodes, see reference for details */ | ||
100 | |||
101 | /* | ||
102 | the capture bit position in the object_id field in driver commands | ||
103 | depends upon the number of managed channels. For now, 64 IN + 64 OUT are | ||
104 | supported. HOwever, the communication protocol forsees 1024 channels, hence | ||
105 | bit 10 indicates a capture (input) object). | ||
106 | */ | ||
107 | #define ID_IS_CAPTURE (1L << 10) | ||
108 | #define ID_OFFSET 13 /* object ID is at the 13th bit in the | ||
109 | * 1st command word.*/ | ||
110 | #define ID_CH_MASK 0x3F | ||
111 | #define OPCODE_OFFSET 24 /* offset of the command opcode in the first | ||
112 | * command word.*/ | ||
113 | |||
114 | enum cmd_mb_opcodes { | ||
115 | CMD_00_INFO_DEBUG = 0x00, | ||
116 | CMD_01_GET_SYS_CFG = 0x01, | ||
117 | CMD_02_SET_GRANULARITY = 0x02, | ||
118 | CMD_03_SET_TIMER_IRQ = 0x03, | ||
119 | CMD_04_GET_EVENT = 0x04, | ||
120 | CMD_05_GET_PIPES = 0x05, | ||
121 | |||
122 | CMD_06_ALLOCATE_PIPE = 0x06, | ||
123 | CMD_07_RELEASE_PIPE = 0x07, | ||
124 | CMD_08_ASK_BUFFERS = 0x08, | ||
125 | CMD_09_STOP_PIPE = 0x09, | ||
126 | CMD_0A_GET_PIPE_SPL_COUNT = 0x0a, | ||
127 | CMD_0B_TOGGLE_PIPE_STATE = 0x0b, | ||
128 | |||
129 | CMD_0C_DEF_STREAM = 0x0c, | ||
130 | CMD_0D_SET_MUTE = 0x0d, | ||
131 | CMD_0E_GET_STREAM_SPL_COUNT = 0x0e, | ||
132 | CMD_0F_UPDATE_BUFFER = 0x0f, | ||
133 | CMD_10_GET_BUFFER = 0x10, | ||
134 | CMD_11_CANCEL_BUFFER = 0x11, | ||
135 | CMD_12_GET_PEAK = 0x12, | ||
136 | CMD_13_SET_STREAM_STATE = 0x13, | ||
137 | CMD_14_INVALID = 0x14, | ||
138 | }; | ||
139 | |||
140 | /* pipe states */ | ||
141 | enum pipe_state_t { | ||
142 | PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ | ||
143 | * (free or stopped, or paused). */ | ||
144 | PSTATE_RUN = 1, /* sustained play/record state. */ | ||
145 | PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do | ||
146 | * not DMA, record pipe do a last DMA. */ | ||
147 | PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do | ||
148 | * not yet increase their sample count, record | ||
149 | * pipes do not DMA. */ | ||
150 | PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet | ||
151 | * receive an "alloc" command. */ | ||
152 | }; | ||
153 | |||
154 | /* stream states */ | ||
155 | enum stream_state_t { | ||
156 | SSTATE_STOP = 0x00, /* setting to stop resets the stream spl | ||
157 | * count.*/ | ||
158 | SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */ | ||
159 | SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */ | ||
160 | }; | ||
161 | |||
162 | /* buffer flags */ | ||
163 | enum buffer_flags { | ||
164 | BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/ | ||
165 | BF_CURRENT = 0x40, /* set if this is the current buffer (there is | ||
166 | * always a current buffer).*/ | ||
167 | BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event | ||
168 | * when finished.*/ | ||
169 | BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0] | ||
170 | * by the end of this buffer.*/ | ||
171 | BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/ | ||
172 | BF_xx = 0x04, /* future extension.*/ | ||
173 | BF_EOB = 0x02, /* set if finished, but not yet free.*/ | ||
174 | BF_PAUSE = 0x01, /* pause stream at buffer end.*/ | ||
175 | BF_ZERO = 0x00, /* no flags (init).*/ | ||
176 | }; | ||
177 | |||
178 | /** | ||
179 | * Stream Flags definitions | ||
180 | */ | ||
181 | enum stream_flags { | ||
182 | SF_ZERO = 0x00000000, /* no flags (stream invalid). */ | ||
183 | SF_VALID = 0x10000000, /* the stream has a valid DMA_conf | ||
184 | * info (setstreamformat). */ | ||
185 | SF_XRUN = 0x20000000, /* the stream is un x-run state. */ | ||
186 | SF_START = 0x40000000, /* the DMA is running.*/ | ||
187 | SF_ASIO = 0x80000000, /* ASIO.*/ | ||
188 | }; | ||
189 | |||
190 | |||
191 | #define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */ | ||
192 | #define PSTATE_OFFSET 28 /* 4 MSBits are status bits */ | ||
193 | |||
194 | |||
195 | #define MASK_STREAM_HAS_MAPPING (1L << 12) | ||
196 | #define MASK_STREAM_IS_ASIO (1L << 9) | ||
197 | #define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th | ||
198 | * bit in the command word. */ | ||
199 | |||
200 | #define STREAM_FMT_16b 0x02 | ||
201 | #define STREAM_FMT_intel 0x01 | ||
202 | |||
203 | #define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response | ||
204 | * word */ | ||
205 | |||
206 | #define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the | ||
207 | * response word. */ | ||
208 | #define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of | ||
209 | * datasize in the buffer_t structure. */ | ||
210 | |||
211 | #define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID, | ||
212 | * may be 0xFF for "current". */ | ||
213 | |||
214 | |||
215 | /* code adapted from PcxErr_e.h */ | ||
216 | |||
217 | /* Bits masks */ | ||
218 | |||
219 | #define ERROR_MASK 0x8000 | ||
220 | |||
221 | #define SOURCE_MASK 0x7800 | ||
222 | |||
223 | #define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */ | ||
224 | #define E_SOURCE_DRV 0x2000 /* 4 >> 1 */ | ||
225 | #define E_SOURCE_API 0x1000 /* 2 >> 1 */ | ||
226 | /* Error tools */ | ||
227 | #define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */ | ||
228 | /* Error pcxaudio */ | ||
229 | #define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */ | ||
230 | /* Error virtual pcx */ | ||
231 | #define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */ | ||
232 | /* Error dispatcher */ | ||
233 | #define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */ | ||
234 | /* Error from CobraNet firmware */ | ||
235 | #define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */ | ||
236 | |||
237 | #define E_SOURCE_USER 0x7800 | ||
238 | |||
239 | #define CLASS_MASK 0x0700 | ||
240 | |||
241 | #define CODE_MASK 0x00FF | ||
242 | |||
243 | /* Bits values */ | ||
244 | |||
245 | /* Values for the error/warning bit */ | ||
246 | #define ERROR_VALUE 0x8000 | ||
247 | #define WARNING_VALUE 0x0000 | ||
248 | |||
249 | /* Class values */ | ||
250 | #define E_CLASS_GENERAL 0x0000 | ||
251 | #define E_CLASS_INVALID_CMD 0x0100 | ||
252 | #define E_CLASS_INVALID_STD_OBJECT 0x0200 | ||
253 | #define E_CLASS_RSRC_IMPOSSIBLE 0x0300 | ||
254 | #define E_CLASS_WRONG_CONTEXT 0x0400 | ||
255 | #define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500 | ||
256 | #define E_CLASS_REAL_TIME_ERROR 0x0600 | ||
257 | #define E_CLASS_DIRECTSHOW 0x0700 | ||
258 | #define E_CLASS_FREE 0x0700 | ||
259 | |||
260 | |||
261 | /* Complete DRV error code for the general class */ | ||
262 | #define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL) | ||
263 | #define ED_CONCURRENCY (ED_GN | 0x01) | ||
264 | #define ED_DSP_CRASHED (ED_GN | 0x02) | ||
265 | #define ED_UNKNOWN_BOARD (ED_GN | 0x03) | ||
266 | #define ED_NOT_INSTALLED (ED_GN | 0x04) | ||
267 | #define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05) | ||
268 | #define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06) | ||
269 | #define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07) | ||
270 | #define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08) | ||
271 | #define ED_CANCELLED (ED_GN | 0x09) | ||
272 | #define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10) | ||
273 | #define ED_INVALID_ADDRESS (ED_GN | 0x11) | ||
274 | #define ED_DSP_CORRUPTED (ED_GN | 0x12) | ||
275 | #define ED_PENDING_OPERATION (ED_GN | 0x13) | ||
276 | #define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14) | ||
277 | #define ED_NET_REGISTER_ERROR (ED_GN | 0x15) | ||
278 | #define ED_NET_THREAD_ERROR (ED_GN | 0x16) | ||
279 | #define ED_NET_OPEN_ERROR (ED_GN | 0x17) | ||
280 | #define ED_NET_CLOSE_ERROR (ED_GN | 0x18) | ||
281 | #define ED_NET_NO_MORE_PACKET (ED_GN | 0x19) | ||
282 | #define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A) | ||
283 | #define ED_NET_SEND_ERROR (ED_GN | 0x1B) | ||
284 | #define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C) | ||
285 | #define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D) | ||
286 | #define ED_NET_WAIT_ERROR (ED_GN | 0x1E) | ||
287 | #define ED_NET_EEPROM_ERROR (ED_GN | 0x1F) | ||
288 | #define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20) | ||
289 | #define ED_INVALID_RS232_INIT (ED_GN | 0x21) | ||
290 | #define ED_FILE_ERROR (ED_GN | 0x22) | ||
291 | #define ED_INVALID_GPIO_CMD (ED_GN | 0x23) | ||
292 | #define ED_RS232_ALREADY_OPENED (ED_GN | 0x24) | ||
293 | #define ED_RS232_NOT_OPENED (ED_GN | 0x25) | ||
294 | #define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26) | ||
295 | #define ED_GPIO_NOT_OPENED (ED_GN | 0x27) | ||
296 | #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */ | ||
297 | #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */ | ||
298 | |||
299 | #define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage | ||
300 | * pour RCX | ||
301 | * (old 0x28) | ||
302 | * */ | ||
303 | #define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */ | ||
304 | #define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */ | ||
305 | #define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */ | ||
306 | #define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */ | ||
307 | #define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */ | ||
308 | #define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */ | ||
309 | #define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */ | ||
310 | |||
311 | #define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour | ||
312 | * PCX (old 0x14) */ | ||
313 | #define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */ | ||
314 | #define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */ | ||
315 | #define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */ | ||
316 | #define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */ | ||
317 | |||
318 | #define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37) | ||
319 | |||
320 | #define ED_NO_CURRENT_CLOCK (ED_GN | 0x38) | ||
321 | |||
322 | /* Complete DRV error code for real time class */ | ||
323 | #define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR) | ||
324 | #define ED_DSP_TIMED_OUT (ED_RT | 0x01) | ||
325 | #define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02) | ||
326 | #define ED_STREAM_OVERRUN (ED_RT | 0x03) | ||
327 | #define ED_DSP_BUSY (ED_RT | 0x04) | ||
328 | #define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05) | ||
329 | #define ED_BOARD_TIME_OUT (ED_RT | 0x06) | ||
330 | #define ED_XILINX_ERROR (ED_RT | 0x07) | ||
331 | #define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08) | ||
332 | |||
333 | /* Complete BOARD error code for the invaid standard object class */ | ||
334 | #define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \ | ||
335 | E_CLASS_INVALID_STD_OBJECT) | ||
336 | #define EB_INVALID_EFFECT (EB_ISO | 0x00) | ||
337 | #define EB_INVALID_PIPE (EB_ISO | 0x40) | ||
338 | #define EB_INVALID_STREAM (EB_ISO | 0x80) | ||
339 | #define EB_INVALID_AUDIO (EB_ISO | 0xC0) | ||
340 | |||
341 | /* Complete BOARD error code for impossible resource allocation class */ | ||
342 | #define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE) | ||
343 | #define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01) | ||
344 | #define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02) | ||
345 | |||
346 | #define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \ | ||
347 | EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE | ||
348 | #define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \ | ||
349 | EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE | ||
350 | |||
351 | #define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03) | ||
352 | #define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04) | ||
353 | #define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05) | ||
354 | #define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08) | ||
355 | #define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09) | ||
356 | #define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A) | ||
357 | #define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B) | ||
358 | #define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D) | ||
359 | #define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E) | ||
360 | #define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F) | ||
361 | #define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40) | ||
362 | #define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80) | ||
363 | #define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0) | ||
364 | |||
365 | /* Complete BOARD error code for wrong call context class */ | ||
366 | #define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT) | ||
367 | #define EB_CMD_REFUSED (EB_WCC | 0x00) | ||
368 | #define EB_START_STREAM_REFUSED (EB_WCC | 0xFC) | ||
369 | #define EB_SPC_REFUSED (EB_WCC | 0xFD) | ||
370 | #define EB_CSN_REFUSED (EB_WCC | 0xFE) | ||
371 | #define EB_CSE_REFUSED (EB_WCC | 0xFF) | ||
372 | |||
373 | |||
374 | |||
375 | |||
376 | #endif /* LX_DEFS_H */ | ||