aboutsummaryrefslogtreecommitdiffstats
path: root/sound/pci/pcxhr
diff options
context:
space:
mode:
Diffstat (limited to 'sound/pci/pcxhr')
-rw-r--r--sound/pci/pcxhr/Makefile2
-rw-r--r--sound/pci/pcxhr/pcxhr.c1367
-rw-r--r--sound/pci/pcxhr/pcxhr.h188
-rw-r--r--sound/pci/pcxhr/pcxhr_core.c1214
-rw-r--r--sound/pci/pcxhr/pcxhr_core.h200
-rw-r--r--sound/pci/pcxhr/pcxhr_hwdep.c438
-rw-r--r--sound/pci/pcxhr/pcxhr_hwdep.h40
-rw-r--r--sound/pci/pcxhr/pcxhr_mixer.c1020
-rw-r--r--sound/pci/pcxhr/pcxhr_mixer.h29
9 files changed, 4498 insertions, 0 deletions
diff --git a/sound/pci/pcxhr/Makefile b/sound/pci/pcxhr/Makefile
new file mode 100644
index 000000000000..10473c05918d
--- /dev/null
+++ b/sound/pci/pcxhr/Makefile
@@ -0,0 +1,2 @@
1snd-pcxhr-objs := pcxhr.o pcxhr_hwdep.o pcxhr_mixer.o pcxhr_core.o
2obj-$(CONFIG_SND_PCXHR) += snd-pcxhr.o
diff --git a/sound/pci/pcxhr/pcxhr.c b/sound/pci/pcxhr/pcxhr.c
new file mode 100644
index 000000000000..b8c0853a8278
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr.c
@@ -0,0 +1,1367 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * main file with alsa callbacks
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23
24#include <sound/driver.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/slab.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/moduleparam.h>
31#include <sound/core.h>
32#include <sound/initval.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include "pcxhr.h"
38#include "pcxhr_mixer.h"
39#include "pcxhr_hwdep.h"
40#include "pcxhr_core.h"
41
42#define DRIVER_NAME "pcxhr"
43
44MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
45MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
46MODULE_LICENSE("GPL");
47MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
48
49static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
50static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
51static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
52static int mono[SNDRV_CARDS]; /* capture in mono only */
53
54module_param_array(index, int, NULL, 0444);
55MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
56module_param_array(id, charp, NULL, 0444);
57MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
58module_param_array(enable, bool, NULL, 0444);
59MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
60module_param_array(mono, bool, NULL, 0444);
61MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
62
63enum {
64 PCI_ID_VX882HR,
65 PCI_ID_PCX882HR,
66 PCI_ID_VX881HR,
67 PCI_ID_PCX881HR,
68 PCI_ID_PCX1222HR,
69 PCI_ID_PCX1221HR,
70 PCI_ID_LAST
71};
72
73static struct pci_device_id pcxhr_ids[] = {
74 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */
75 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */
76 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */
77 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */
78 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
79 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
80 { 0, }
81};
82
83MODULE_DEVICE_TABLE(pci, pcxhr_ids);
84
85struct board_parameters {
86 char* board_name;
87 short playback_chips;
88 short capture_chips;
89 short firmware_num;
90};
91static struct board_parameters pcxhr_board_params[] = {
92[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
93[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
94[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
95[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
96[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
97[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
98};
99
100
101static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
102 unsigned int* realfreq)
103{
104 unsigned int reg;
105
106 if (freq < 6900 || freq > 110250)
107 return -EINVAL;
108 reg = (28224000 * 10) / freq;
109 reg = (reg + 5) / 10;
110 if (reg < 0x200)
111 *pllreg = reg + 0x800;
112 else if (reg < 0x400)
113 *pllreg = reg & 0x1ff;
114 else if (reg < 0x800) {
115 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
116 reg &= ~1;
117 } else {
118 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
119 reg &= ~3;
120 }
121 if (realfreq)
122 *realfreq = ((28224000 * 10) / reg + 5) / 10;
123 return 0;
124}
125
126
127#define PCXHR_FREQ_REG_MASK 0x1f
128#define PCXHR_FREQ_QUARTZ_48000 0x00
129#define PCXHR_FREQ_QUARTZ_24000 0x01
130#define PCXHR_FREQ_QUARTZ_12000 0x09
131#define PCXHR_FREQ_QUARTZ_32000 0x08
132#define PCXHR_FREQ_QUARTZ_16000 0x04
133#define PCXHR_FREQ_QUARTZ_8000 0x0c
134#define PCXHR_FREQ_QUARTZ_44100 0x02
135#define PCXHR_FREQ_QUARTZ_22050 0x0a
136#define PCXHR_FREQ_QUARTZ_11025 0x06
137#define PCXHR_FREQ_PLL 0x05
138#define PCXHR_FREQ_QUARTZ_192000 0x10
139#define PCXHR_FREQ_QUARTZ_96000 0x18
140#define PCXHR_FREQ_QUARTZ_176400 0x14
141#define PCXHR_FREQ_QUARTZ_88200 0x1c
142#define PCXHR_FREQ_QUARTZ_128000 0x12
143#define PCXHR_FREQ_QUARTZ_64000 0x1a
144
145#define PCXHR_FREQ_WORD_CLOCK 0x0f
146#define PCXHR_FREQ_SYNC_AES 0x0e
147#define PCXHR_FREQ_AES_1 0x07
148#define PCXHR_FREQ_AES_2 0x0b
149#define PCXHR_FREQ_AES_3 0x03
150#define PCXHR_FREQ_AES_4 0x0d
151
152#define PCXHR_MODIFY_CLOCK_S_BIT 0x04
153
154#define PCXHR_IRQ_TIMER_FREQ 92000
155#define PCXHR_IRQ_TIMER_PERIOD 48
156
157static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
158 unsigned int *reg, unsigned int *freq)
159{
160 unsigned int val, realfreq, pllreg;
161 struct pcxhr_rmh rmh;
162 int err;
163
164 realfreq = rate;
165 switch (mgr->use_clock_type) {
166 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
167 switch (rate) {
168 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
169 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
170 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
171 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
172 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
173 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
174 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
175 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
176 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
177 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
178 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
179 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
180 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
181 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
182 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
183 default :
184 val = PCXHR_FREQ_PLL;
185 /* get the value for the pll register */
186 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
187 if (err)
188 return err;
189 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
190 rmh.cmd[0] |= IO_NUM_REG_GENCLK;
191 rmh.cmd[1] = pllreg & MASK_DSP_WORD;
192 rmh.cmd[2] = pllreg >> 24;
193 rmh.cmd_len = 3;
194 err = pcxhr_send_msg(mgr, &rmh);
195 if (err < 0) {
196 snd_printk(KERN_ERR
197 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
198 err );
199 return err;
200 }
201 }
202 break;
203 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
204 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
205 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
206 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
207 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
208 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
209 default : return -EINVAL;
210 }
211 *reg = val;
212 *freq = realfreq;
213 return 0;
214}
215
216
217int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
218{
219 unsigned int val, realfreq, speed;
220 struct pcxhr_rmh rmh;
221 int err, changed;
222
223 if (rate == 0)
224 return 0; /* nothing to do */
225
226 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
227 if (err)
228 return err;
229
230 /* codec speed modes */
231 if (rate < 55000)
232 speed = 0; /* single speed */
233 else if (rate < 100000)
234 speed = 1; /* dual speed */
235 else
236 speed = 2; /* quad speed */
237 if (mgr->codec_speed != speed) {
238 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
239 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
240 err = pcxhr_send_msg(mgr, &rmh);
241 if (err)
242 return err;
243
244 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
245 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
246 rmh.cmd[1] = speed;
247 rmh.cmd_len = 2;
248 err = pcxhr_send_msg(mgr, &rmh);
249 if (err)
250 return err;
251 }
252 /* set the new frequency */
253 snd_printdd("clock register : set %x\n", val);
254 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
255 if (err)
256 return err;
257 mgr->sample_rate_real = realfreq;
258 mgr->cur_clock_type = mgr->use_clock_type;
259
260 /* unmute after codec speed modes */
261 if (mgr->codec_speed != speed) {
262 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
263 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
264 err = pcxhr_send_msg(mgr, &rmh);
265 if (err)
266 return err;
267 mgr->codec_speed = speed; /* save new codec speed */
268 }
269
270 if (changed) {
271 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
272 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
273 if (rate < PCXHR_IRQ_TIMER_FREQ)
274 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
275 else
276 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
277 rmh.cmd[2] = rate;
278 rmh.cmd_len = 3;
279 err = pcxhr_send_msg(mgr, &rmh);
280 if (err)
281 return err;
282 }
283 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
284 return 0;
285}
286
287
288int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
289 int *sample_rate)
290{
291 struct pcxhr_rmh rmh;
292 unsigned char reg;
293 int err, rate;
294
295 switch (clock_type) {
296 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
297 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
298 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
299 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
300 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
301 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
302 default : return -EINVAL;
303 }
304 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
305 rmh.cmd_len = 2;
306 rmh.cmd[0] |= IO_NUM_REG_STATUS;
307 if (mgr->last_reg_stat != reg) {
308 rmh.cmd[1] = reg;
309 err = pcxhr_send_msg(mgr, &rmh);
310 if (err)
311 return err;
312 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
313 mgr->last_reg_stat = reg;
314 }
315 rmh.cmd[1] = REG_STATUS_CURRENT;
316 err = pcxhr_send_msg(mgr, &rmh);
317 if (err)
318 return err;
319 switch (rmh.stat[1] & 0x0f) {
320 case REG_STATUS_SYNC_32000 : rate = 32000; break;
321 case REG_STATUS_SYNC_44100 : rate = 44100; break;
322 case REG_STATUS_SYNC_48000 : rate = 48000; break;
323 case REG_STATUS_SYNC_64000 : rate = 64000; break;
324 case REG_STATUS_SYNC_88200 : rate = 88200; break;
325 case REG_STATUS_SYNC_96000 : rate = 96000; break;
326 case REG_STATUS_SYNC_128000 : rate = 128000; break;
327 case REG_STATUS_SYNC_176400 : rate = 176400; break;
328 case REG_STATUS_SYNC_192000 : rate = 192000; break;
329 default: rate = 0;
330 }
331 snd_printdd("External clock is at %d Hz\n", rate);
332 *sample_rate = rate;
333 return 0;
334}
335
336
337/*
338 * start or stop playback/capture substream
339 */
340static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
341{
342 int err;
343 struct snd_pcxhr *chip;
344 struct pcxhr_rmh rmh;
345 int stream_mask, start;
346
347 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
348 start = 1;
349 else {
350 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
351 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
352 return -EINVAL;
353 }
354 start = 0;
355 }
356 if (!stream->substream)
357 return -EINVAL;
358
359 stream->timer_abs_periods = 0;
360 stream->timer_period_frag = 0; /* reset theoretical stream pos */
361 stream->timer_buf_periods = 0;
362 stream->timer_is_synced = 0;
363
364 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
365
366 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
367 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
368 stream->pipe->first_audio, 0, stream_mask);
369
370 chip = snd_pcm_substream_chip(stream->substream);
371
372 err = pcxhr_send_msg(chip->mgr, &rmh);
373 if (err)
374 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
375 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
376 return err;
377}
378
379#define HEADER_FMT_BASE_LIN 0xfed00000
380#define HEADER_FMT_BASE_FLOAT 0xfad00000
381#define HEADER_FMT_INTEL 0x00008000
382#define HEADER_FMT_24BITS 0x00004000
383#define HEADER_FMT_16BITS 0x00002000
384#define HEADER_FMT_UPTO11 0x00000200
385#define HEADER_FMT_UPTO32 0x00000100
386#define HEADER_FMT_MONO 0x00000080
387
388static int pcxhr_set_format(struct pcxhr_stream *stream)
389{
390 int err, is_capture, sample_rate, stream_num;
391 struct snd_pcxhr *chip;
392 struct pcxhr_rmh rmh;
393 unsigned int header;
394
395 switch (stream->format) {
396 case SNDRV_PCM_FORMAT_U8:
397 header = HEADER_FMT_BASE_LIN;
398 break;
399 case SNDRV_PCM_FORMAT_S16_LE:
400 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
401 break;
402 case SNDRV_PCM_FORMAT_S16_BE:
403 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
404 break;
405 case SNDRV_PCM_FORMAT_S24_3LE:
406 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
407 break;
408 case SNDRV_PCM_FORMAT_S24_3BE:
409 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
410 break;
411 case SNDRV_PCM_FORMAT_FLOAT_LE:
412 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
413 break;
414 default:
415 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
416 return -EINVAL;
417 }
418 chip = snd_pcm_substream_chip(stream->substream);
419
420 sample_rate = chip->mgr->sample_rate;
421 if (sample_rate <= 32000 && sample_rate !=0) {
422 if (sample_rate <= 11025)
423 header |= HEADER_FMT_UPTO11;
424 else
425 header |= HEADER_FMT_UPTO32;
426 }
427 if (stream->channels == 1)
428 header |= HEADER_FMT_MONO;
429
430 is_capture = stream->pipe->is_capture;
431 stream_num = is_capture ? 0 : stream->substream->number;
432
433 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
434 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
435 if (is_capture)
436 rmh.cmd[0] |= 1<<12;
437 rmh.cmd[1] = 0;
438 rmh.cmd[2] = header >> 8;
439 rmh.cmd[3] = (header & 0xff) << 16;
440 rmh.cmd_len = 4;
441 err = pcxhr_send_msg(chip->mgr, &rmh);
442 if (err)
443 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
444 return err;
445}
446
447static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
448{
449 int err, is_capture, stream_num;
450 struct pcxhr_rmh rmh;
451 struct snd_pcm_substream *subs = stream->substream;
452 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
453
454 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
455 stream_num = is_capture ? 0 : subs->number;
456
457 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%x) subs(%d)\n",
458 is_capture ? 'c' : 'p',
459 chip->chip_idx, (void*)subs->runtime->dma_addr,
460 subs->runtime->dma_bytes, subs->number);
461
462 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
463 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
464
465 snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */
466 rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */
467 rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */
468 rmh.cmd[2] |= 1<<19; /* this is a circular buffer */
469 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */
470 rmh.cmd_len = 4;
471 err = pcxhr_send_msg(chip->mgr, &rmh);
472 if (err)
473 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
474 return err;
475}
476
477
478#if 0
479static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
480{
481 struct pcxhr_rmh rmh;
482 int err;
483 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
484 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
485 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
486 1<<stream->pipe->first_audio);
487 err = pcxhr_send_msg(chip->mgr, &rmh);
488 if (err == 0) {
489 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
490 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
491 }
492 snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
493 return err;
494}
495#endif
496
497static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
498 struct pcxhr_pipe **pipe)
499{
500 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
501 *pipe = stream->pipe;
502 return 1;
503 }
504 return 0;
505}
506
507static void pcxhr_trigger_tasklet(unsigned long arg)
508{
509 unsigned long flags;
510 int i, j, err;
511 struct pcxhr_pipe *pipe;
512 struct snd_pcxhr *chip;
513 struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
514 int capture_mask = 0;
515 int playback_mask = 0;
516
517#ifdef CONFIG_SND_DEBUG_DETECT
518 struct timeval my_tv1, my_tv2;
519 do_gettimeofday(&my_tv1);
520#endif
521 down(&mgr->setup_mutex);
522
523 /* check the pipes concerned and build pipe_array */
524 for (i = 0; i < mgr->num_cards; i++) {
525 chip = mgr->chip[i];
526 for (j = 0; j < chip->nb_streams_capt; j++) {
527 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
528 capture_mask |= (1 << pipe->first_audio);
529 }
530 for (j = 0; j < chip->nb_streams_play; j++) {
531 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
532 playback_mask |= (1 << pipe->first_audio);
533 break; /* add only once, as all playback streams of
534 * one chip use the same pipe
535 */
536 }
537 }
538 }
539 if (capture_mask == 0 && playback_mask == 0) {
540 up(&mgr->setup_mutex);
541 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
542 return;
543 }
544
545 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
546 playback_mask, capture_mask);
547
548 /* synchronous stop of all the pipes concerned */
549 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
550 if (err) {
551 up(&mgr->setup_mutex);
552 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
553 playback_mask, capture_mask);
554 return;
555 }
556
557 /* unfortunately the dsp lost format and buffer info with the stop pipe */
558 for (i = 0; i < mgr->num_cards; i++) {
559 struct pcxhr_stream *stream;
560 chip = mgr->chip[i];
561 for (j = 0; j < chip->nb_streams_capt; j++) {
562 stream = &chip->capture_stream[j];
563 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
564 err = pcxhr_set_format(stream);
565 err = pcxhr_update_r_buffer(stream);
566 }
567 }
568 for (j = 0; j < chip->nb_streams_play; j++) {
569 stream = &chip->playback_stream[j];
570 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
571 err = pcxhr_set_format(stream);
572 err = pcxhr_update_r_buffer(stream);
573 }
574 }
575 }
576 /* start all the streams */
577 for (i = 0; i < mgr->num_cards; i++) {
578 struct pcxhr_stream *stream;
579 chip = mgr->chip[i];
580 for (j = 0; j < chip->nb_streams_capt; j++) {
581 stream = &chip->capture_stream[j];
582 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
583 err = pcxhr_set_stream_state(stream);
584 }
585 for (j = 0; j < chip->nb_streams_play; j++) {
586 stream = &chip->playback_stream[j];
587 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
588 err = pcxhr_set_stream_state(stream);
589 }
590 }
591
592 /* synchronous start of all the pipes concerned */
593 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
594 if (err) {
595 up(&mgr->setup_mutex);
596 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
597 playback_mask, capture_mask);
598 return;
599 }
600
601 /* put the streams into the running state now (increment pointer by interrupt) */
602 spin_lock_irqsave(&mgr->lock, flags);
603 for ( i =0; i < mgr->num_cards; i++) {
604 struct pcxhr_stream *stream;
605 chip = mgr->chip[i];
606 for(j = 0; j < chip->nb_streams_capt; j++) {
607 stream = &chip->capture_stream[j];
608 if(stream->status == PCXHR_STREAM_STATUS_STARTED)
609 stream->status = PCXHR_STREAM_STATUS_RUNNING;
610 }
611 for (j = 0; j < chip->nb_streams_play; j++) {
612 stream = &chip->playback_stream[j];
613 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
614 /* playback will already have advanced ! */
615 stream->timer_period_frag += PCXHR_GRANULARITY;
616 stream->status = PCXHR_STREAM_STATUS_RUNNING;
617 }
618 }
619 }
620 spin_unlock_irqrestore(&mgr->lock, flags);
621
622 up(&mgr->setup_mutex);
623
624#ifdef CONFIG_SND_DEBUG_DETECT
625 do_gettimeofday(&my_tv2);
626 snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
627 my_tv2.tv_usec - my_tv1.tv_usec, err);
628#endif
629}
630
631
632/*
633 * trigger callback
634 */
635static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
636{
637 struct pcxhr_stream *stream;
638 struct list_head *pos;
639 struct snd_pcm_substream *s;
640 int i;
641
642 switch (cmd) {
643 case SNDRV_PCM_TRIGGER_START:
644 snd_printdd("SNDRV_PCM_TRIGGER_START\n");
645 i = 0;
646 snd_pcm_group_for_each(pos, subs) {
647 s = snd_pcm_group_substream_entry(pos);
648 stream = s->runtime->private_data;
649 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
650 snd_pcm_trigger_done(s, subs);
651 i++;
652 }
653 if (i==1) {
654 snd_printdd("Only one Substream %c %d\n",
655 stream->pipe->is_capture ? 'C' : 'P',
656 stream->pipe->first_audio);
657 if (pcxhr_set_format(stream))
658 return -EINVAL;
659 if (pcxhr_update_r_buffer(stream))
660 return -EINVAL;
661
662 if (pcxhr_set_stream_state(stream))
663 return -EINVAL;
664 stream->status = PCXHR_STREAM_STATUS_RUNNING;
665 } else {
666 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
667 tasklet_hi_schedule(&chip->mgr->trigger_taskq);
668 }
669 break;
670 case SNDRV_PCM_TRIGGER_STOP:
671 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
672 snd_pcm_group_for_each(pos, subs) {
673 s = snd_pcm_group_substream_entry(pos);
674 stream = s->runtime->private_data;
675 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
676 if (pcxhr_set_stream_state(stream))
677 return -EINVAL;
678 snd_pcm_trigger_done(s, subs);
679 }
680 break;
681 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
682 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
683 /* TODO */
684 default:
685 return -EINVAL;
686 }
687 return 0;
688}
689
690
691static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
692{
693 struct pcxhr_rmh rmh;
694 int err;
695
696 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
697 if (start) {
698 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */
699 rmh.cmd[0] |= PCXHR_GRANULARITY;
700 }
701 err = pcxhr_send_msg(mgr, &rmh);
702 if (err < 0)
703 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
704 return err;
705}
706
707/*
708 * prepare callback for all pcms
709 */
710static int pcxhr_prepare(struct snd_pcm_substream *subs)
711{
712 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
713 struct pcxhr_mgr *mgr = chip->mgr;
714 /*
715 struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
716 */
717 int err = 0;
718
719 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
720 subs->runtime->period_size, subs->runtime->periods,
721 subs->runtime->buffer_size);
722
723 /*
724 if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
725 snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
726 (unsigned int)subs->runtime->period_size);
727 return -EINVAL;
728 }
729 */
730
731 down(&mgr->setup_mutex);
732
733 do {
734 /* if the stream was stopped before, format and buffer were reset */
735 /*
736 if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
737 err = pcxhr_set_format(stream);
738 if(err) break;
739 err = pcxhr_update_r_buffer(stream);
740 if(err) break;
741 }
742 */
743
744 /* only the first stream can choose the sample rate */
745 /* the further opened streams will be limited to its frequency (see open) */
746 /* set the clock only once (first stream) */
747 if (mgr->sample_rate == 0) {
748 err = pcxhr_set_clock(mgr, subs->runtime->rate);
749 if (err)
750 break;
751 mgr->sample_rate = subs->runtime->rate;
752
753 err = pcxhr_hardware_timer(mgr, 1); /* start the DSP-timer */
754 }
755 } while(0); /* do only once (so we can use break instead of goto) */
756
757 up(&mgr->setup_mutex);
758
759 return err;
760}
761
762
763/*
764 * HW_PARAMS callback for all pcms
765 */
766static int pcxhr_hw_params(struct snd_pcm_substream *subs,
767 struct snd_pcm_hw_params *hw)
768{
769 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
770 struct pcxhr_mgr *mgr = chip->mgr;
771 struct pcxhr_stream *stream = subs->runtime->private_data;
772 snd_pcm_format_t format;
773 int err;
774 int channels;
775
776 /* set up channels */
777 channels = params_channels(hw);
778
779 /* set up format for the stream */
780 format = params_format(hw);
781
782 down(&mgr->setup_mutex);
783
784 stream->channels = channels;
785 stream->format = format;
786
787 /* set the format to the board */
788 /*
789 err = pcxhr_set_format(stream);
790 if(err) {
791 up(&mgr->setup_mutex);
792 return err;
793 }
794 */
795 /* allocate buffer */
796 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
797
798 /*
799 if (err > 0) {
800 err = pcxhr_update_r_buffer(stream);
801 }
802 */
803 up(&mgr->setup_mutex);
804
805 return err;
806}
807
808static int pcxhr_hw_free(struct snd_pcm_substream *subs)
809{
810 snd_pcm_lib_free_pages(subs);
811 return 0;
812}
813
814
815/*
816 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
817 */
818static struct snd_pcm_hardware pcxhr_caps =
819{
820 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
821 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
822 0 /*SNDRV_PCM_INFO_PAUSE*/),
823 .formats = ( SNDRV_PCM_FMTBIT_U8 |
824 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
825 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
826 SNDRV_PCM_FMTBIT_FLOAT_LE ),
827 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
828 .rate_min = 8000,
829 .rate_max = 192000,
830 .channels_min = 1,
831 .channels_max = 2,
832 .buffer_bytes_max = (32*1024),
833 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
834 .period_bytes_min = (2*PCXHR_GRANULARITY),
835 .period_bytes_max = (16*1024),
836 .periods_min = 2,
837 .periods_max = (32*1024/PCXHR_GRANULARITY),
838};
839
840
841static int pcxhr_open(struct snd_pcm_substream *subs)
842{
843 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
844 struct pcxhr_mgr *mgr = chip->mgr;
845 struct snd_pcm_runtime *runtime = subs->runtime;
846 struct pcxhr_stream *stream;
847 int is_capture;
848
849 down(&mgr->setup_mutex);
850
851 /* copy the struct snd_pcm_hardware struct */
852 runtime->hw = pcxhr_caps;
853
854 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
855 snd_printdd("pcxhr_open playback chip%d subs%d\n",
856 chip->chip_idx, subs->number);
857 is_capture = 0;
858 stream = &chip->playback_stream[subs->number];
859 } else {
860 snd_printdd("pcxhr_open capture chip%d subs%d\n",
861 chip->chip_idx, subs->number);
862 is_capture = 1;
863 if (mgr->mono_capture)
864 runtime->hw.channels_max = 1;
865 else
866 runtime->hw.channels_min = 2;
867 stream = &chip->capture_stream[subs->number];
868 }
869 if (stream->status != PCXHR_STREAM_STATUS_FREE){
870 /* streams in use */
871 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
872 chip->chip_idx, subs->number);
873 up(&mgr->setup_mutex);
874 return -EBUSY;
875 }
876
877 /* if a sample rate is already used or fixed by external clock,
878 * the stream cannot change
879 */
880 if (mgr->sample_rate)
881 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
882 else {
883 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
884 int external_rate;
885 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
886 &external_rate) ||
887 external_rate == 0) {
888 /* cannot detect the external clock rate */
889 up(&mgr->setup_mutex);
890 return -EBUSY;
891 }
892 runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
893 }
894 }
895
896 stream->status = PCXHR_STREAM_STATUS_OPEN;
897 stream->substream = subs;
898 stream->channels = 0; /* not configured yet */
899
900 runtime->private_data = stream;
901
902 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
903 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
904
905 mgr->ref_count_rate++;
906
907 up(&mgr->setup_mutex);
908 return 0;
909}
910
911
912static int pcxhr_close(struct snd_pcm_substream *subs)
913{
914 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
915 struct pcxhr_mgr *mgr = chip->mgr;
916 struct pcxhr_stream *stream = subs->runtime->private_data;
917
918 down(&mgr->setup_mutex);
919
920 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
921
922 /* sample rate released */
923 if (--mgr->ref_count_rate == 0) {
924 mgr->sample_rate = 0; /* the sample rate is no more locked */
925 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
926 }
927
928 stream->status = PCXHR_STREAM_STATUS_FREE;
929 stream->substream = NULL;
930
931 up(&mgr->setup_mutex);
932
933 return 0;
934}
935
936
937static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
938{
939 unsigned long flags;
940 u_int32_t timer_period_frag;
941 int timer_buf_periods;
942 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
943 struct snd_pcm_runtime *runtime = subs->runtime;
944 struct pcxhr_stream *stream = runtime->private_data;
945
946 spin_lock_irqsave(&chip->mgr->lock, flags);
947
948 /* get the period fragment and the nb of periods in the buffer */
949 timer_period_frag = stream->timer_period_frag;
950 timer_buf_periods = stream->timer_buf_periods;
951
952 spin_unlock_irqrestore(&chip->mgr->lock, flags);
953
954 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
955 timer_period_frag);
956}
957
958
959static struct snd_pcm_ops pcxhr_ops = {
960 .open = pcxhr_open,
961 .close = pcxhr_close,
962 .ioctl = snd_pcm_lib_ioctl,
963 .prepare = pcxhr_prepare,
964 .hw_params = pcxhr_hw_params,
965 .hw_free = pcxhr_hw_free,
966 .trigger = pcxhr_trigger,
967 .pointer = pcxhr_stream_pointer,
968};
969
970/*
971 */
972int pcxhr_create_pcm(struct snd_pcxhr *chip)
973{
974 int err;
975 struct snd_pcm *pcm;
976 char name[32];
977
978 sprintf(name, "pcxhr %d", chip->chip_idx);
979 if ((err = snd_pcm_new(chip->card, name, 0,
980 chip->nb_streams_play,
981 chip->nb_streams_capt, &pcm)) < 0) {
982 snd_printk(KERN_ERR "cannot create pcm %s\n", name);
983 return err;
984 }
985 pcm->private_data = chip;
986
987 if (chip->nb_streams_play)
988 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
989 if (chip->nb_streams_capt)
990 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
991
992 pcm->info_flags = 0;
993 strcpy(pcm->name, name);
994
995 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
996 snd_dma_pci_data(chip->mgr->pci),
997 32*1024, 32*1024);
998 chip->pcm = pcm;
999 return 0;
1000}
1001
1002static int pcxhr_chip_free(struct snd_pcxhr *chip)
1003{
1004 kfree(chip);
1005 return 0;
1006}
1007
1008static int pcxhr_chip_dev_free(struct snd_device *device)
1009{
1010 struct snd_pcxhr *chip = device->device_data;
1011 return pcxhr_chip_free(chip);
1012}
1013
1014
1015/*
1016 */
1017static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
1018{
1019 int err;
1020 struct snd_pcxhr *chip;
1021 static struct snd_device_ops ops = {
1022 .dev_free = pcxhr_chip_dev_free,
1023 };
1024
1025 mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1026 if (! chip) {
1027 snd_printk(KERN_ERR "cannot allocate chip\n");
1028 return -ENOMEM;
1029 }
1030
1031 chip->card = card;
1032 chip->chip_idx = idx;
1033 chip->mgr = mgr;
1034
1035 if (idx < mgr->playback_chips)
1036 /* stereo or mono streams */
1037 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1038
1039 if (idx < mgr->capture_chips) {
1040 if (mgr->mono_capture)
1041 chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */
1042 else
1043 chip->nb_streams_capt = 1; /* or 1 stereo stream */
1044 }
1045
1046 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1047 pcxhr_chip_free(chip);
1048 return err;
1049 }
1050
1051 snd_card_set_dev(card, &mgr->pci->dev);
1052
1053 return 0;
1054}
1055
1056/* proc interface */
1057static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1058{
1059 struct snd_pcxhr *chip = entry->private_data;
1060 struct pcxhr_mgr *mgr = chip->mgr;
1061
1062 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1063
1064 /* stats available when embedded DSP is running */
1065 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1066 struct pcxhr_rmh rmh;
1067 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1068 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1069 short ver_build = mgr->dsp_version & 0xff;
1070 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
1071 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
1072 if (mgr->board_has_analog)
1073 snd_iprintf(buffer, "analog io available\n");
1074 else
1075 snd_iprintf(buffer, "digital only board\n");
1076
1077 /* calc cpu load of the dsp */
1078 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1079 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1080 int cur = rmh.stat[0];
1081 int ref = rmh.stat[1];
1082 if (ref > 0) {
1083 if (mgr->sample_rate_real != 0 &&
1084 mgr->sample_rate_real != 48000) {
1085 ref = (ref * 48000) / mgr->sample_rate_real;
1086 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
1087 ref *= 2;
1088 }
1089 cur = 100 - (100 * cur) / ref;
1090 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1091 snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
1092 rmh.stat[2], rmh.stat[3]);
1093 }
1094 }
1095 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
1096 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
1097 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1098 mgr->async_err_pipe_xrun);
1099 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1100 mgr->async_err_stream_xrun);
1101 snd_iprintf(buffer, "dsp async last other error : %x\n",
1102 mgr->async_err_other_last);
1103 /* debug zone dsp */
1104 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1105 rmh.cmd_len = 1;
1106 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1107 rmh.dsp_stat = 0;
1108 rmh.cmd_idx = CMD_LAST_INDEX;
1109 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1110 int i;
1111 for (i = 0; i < rmh.stat_len; i++)
1112 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
1113 }
1114 } else
1115 snd_iprintf(buffer, "no firmware loaded\n");
1116 snd_iprintf(buffer, "\n");
1117}
1118static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1119{
1120 struct snd_pcxhr *chip = entry->private_data;
1121 struct pcxhr_mgr *mgr = chip->mgr;
1122 static char *texts[7] = {
1123 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
1124 };
1125
1126 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1127 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
1128 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
1129
1130 /* commands available when embedded DSP is running */
1131 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1132 int i, err, sample_rate;
1133 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
1134 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1135 if (err)
1136 break;
1137 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
1138 }
1139 } else
1140 snd_iprintf(buffer, "no firmware loaded\n");
1141 snd_iprintf(buffer, "\n");
1142}
1143
1144static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
1145{
1146 struct snd_info_entry *entry;
1147
1148 if (! snd_card_proc_new(chip->card, "info", &entry))
1149 snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_info);
1150 if (! snd_card_proc_new(chip->card, "sync", &entry))
1151 snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_sync);
1152}
1153/* end of proc interface */
1154
1155/*
1156 * release all the cards assigned to a manager instance
1157 */
1158static int pcxhr_free(struct pcxhr_mgr *mgr)
1159{
1160 unsigned int i;
1161
1162 for (i = 0; i < mgr->num_cards; i++) {
1163 if (mgr->chip[i])
1164 snd_card_free(mgr->chip[i]->card);
1165 }
1166
1167 /* reset board if some firmware was loaded */
1168 if(mgr->dsp_loaded) {
1169 pcxhr_reset_board(mgr);
1170 snd_printdd("reset pcxhr !\n");
1171 }
1172
1173 /* release irq */
1174 if (mgr->irq >= 0)
1175 free_irq(mgr->irq, mgr);
1176
1177 pci_release_regions(mgr->pci);
1178
1179 /* free hostport purgebuffer */
1180 if (mgr->hostport.area) {
1181 snd_dma_free_pages(&mgr->hostport);
1182 mgr->hostport.area = NULL;
1183 }
1184
1185 kfree(mgr->prmh);
1186
1187 pci_disable_device(mgr->pci);
1188 kfree(mgr);
1189 return 0;
1190}
1191
1192/*
1193 * probe function - creates the card manager
1194 */
1195static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1196{
1197 static int dev;
1198 struct pcxhr_mgr *mgr;
1199 unsigned int i;
1200 int err;
1201 size_t size;
1202 char *card_name;
1203
1204 if (dev >= SNDRV_CARDS)
1205 return -ENODEV;
1206 if (! enable[dev]) {
1207 dev++;
1208 return -ENOENT;
1209 }
1210
1211 /* enable PCI device */
1212 if ((err = pci_enable_device(pci)) < 0)
1213 return err;
1214 pci_set_master(pci);
1215
1216 /* check if we can restrict PCI DMA transfers to 32 bits */
1217 if (pci_set_dma_mask(pci, 0xffffffff) < 0) {
1218 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
1219 pci_disable_device(pci);
1220 return -ENXIO;
1221 }
1222
1223 /* alloc card manager */
1224 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1225 if (! mgr) {
1226 pci_disable_device(pci);
1227 return -ENOMEM;
1228 }
1229
1230 snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
1231 card_name = pcxhr_board_params[pci_id->driver_data].board_name;
1232 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
1233 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
1234 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
1235 mgr->mono_capture = mono[dev];
1236
1237 /* resource assignment */
1238 if ((err = pci_request_regions(pci, card_name)) < 0) {
1239 kfree(mgr);
1240 pci_disable_device(pci);
1241 return err;
1242 }
1243 for (i = 0; i < 3; i++)
1244 mgr->port[i] = pci_resource_start(pci, i);
1245
1246 mgr->pci = pci;
1247 mgr->irq = -1;
1248
1249 if (request_irq(pci->irq, pcxhr_interrupt, SA_INTERRUPT|SA_SHIRQ,
1250 card_name, mgr)) {
1251 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1252 pcxhr_free(mgr);
1253 return -EBUSY;
1254 }
1255 mgr->irq = pci->irq;
1256
1257 sprintf(mgr->shortname, "Digigram %s", card_name);
1258 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
1259 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1260
1261 /* ISR spinlock */
1262 spin_lock_init(&mgr->lock);
1263 spin_lock_init(&mgr->msg_lock);
1264
1265 /* init setup mutex*/
1266 init_MUTEX(&mgr->setup_mutex);
1267
1268 /* init taslket */
1269 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
1270 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
1271 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1272 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
1273 GFP_KERNEL);
1274 if (! mgr->prmh) {
1275 pcxhr_free(mgr);
1276 return -ENOMEM;
1277 }
1278
1279 for (i=0; i < PCXHR_MAX_CARDS; i++) {
1280 struct snd_card *card;
1281 char tmpid[16];
1282 int idx;
1283
1284 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1285 break;
1286 mgr->num_cards++;
1287
1288 if (index[dev] < 0)
1289 idx = index[dev];
1290 else
1291 idx = index[dev] + i;
1292
1293 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
1294 card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
1295
1296 if (! card) {
1297 snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
1298 pcxhr_free(mgr);
1299 return -ENOMEM;
1300 }
1301
1302 strcpy(card->driver, DRIVER_NAME);
1303 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1304 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1305
1306 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1307 pcxhr_free(mgr);
1308 return err;
1309 }
1310
1311 if (i == 0)
1312 /* init proc interface only for chip0 */
1313 pcxhr_proc_init(mgr->chip[i]);
1314
1315 if ((err = snd_card_register(card)) < 0) {
1316 pcxhr_free(mgr);
1317 return err;
1318 }
1319 }
1320
1321 /* create hostport purgebuffer */
1322 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1323 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1324 size, &mgr->hostport) < 0) {
1325 pcxhr_free(mgr);
1326 return -ENOMEM;
1327 }
1328 /* init purgebuffer */
1329 memset(mgr->hostport.area, 0, size);
1330
1331 /* create a DSP loader */
1332 err = pcxhr_setup_firmware(mgr);
1333 if (err < 0) {
1334 pcxhr_free(mgr);
1335 return err;
1336 }
1337
1338 pci_set_drvdata(pci, mgr);
1339 dev++;
1340 return 0;
1341}
1342
1343static void __devexit pcxhr_remove(struct pci_dev *pci)
1344{
1345 pcxhr_free(pci_get_drvdata(pci));
1346 pci_set_drvdata(pci, NULL);
1347}
1348
1349static struct pci_driver driver = {
1350 .name = "Digigram pcxhr",
1351 .id_table = pcxhr_ids,
1352 .probe = pcxhr_probe,
1353 .remove = __devexit_p(pcxhr_remove),
1354};
1355
1356static int __init pcxhr_module_init(void)
1357{
1358 return pci_register_driver(&driver);
1359}
1360
1361static void __exit pcxhr_module_exit(void)
1362{
1363 pci_unregister_driver(&driver);
1364}
1365
1366module_init(pcxhr_module_init)
1367module_exit(pcxhr_module_exit)
diff --git a/sound/pci/pcxhr/pcxhr.h b/sound/pci/pcxhr/pcxhr.h
new file mode 100644
index 000000000000..049f2b3f2867
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr.h
@@ -0,0 +1,188 @@
1/*
2 * Driver for Digigram pcxhr soundcards
3 *
4 * main header file
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_PCXHR_H
24#define __SOUND_PCXHR_H
25
26#include <linux/interrupt.h>
27#include <sound/pcm.h>
28
29#define PCXHR_DRIVER_VERSION 0x000804 /* 0.8.4 */
30#define PCXHR_DRIVER_VERSION_STRING "0.8.4" /* 0.8.4 */
31
32
33#define PCXHR_MAX_CARDS 6
34#define PCXHR_PLAYBACK_STREAMS 4
35
36#define PCXHR_GRANULARITY 96 /* transfer granularity (should be min 96 and multiple of 48) */
37#define PCXHR_GRANULARITY_MIN 96 /* transfer granularity of pipes and the dsp time (MBOX4) */
38
39struct snd_pcxhr;
40struct pcxhr_mgr;
41
42struct pcxhr_stream;
43struct pcxhr_pipe;
44
45enum pcxhr_clock_type {
46 PCXHR_CLOCK_TYPE_INTERNAL = 0,
47 PCXHR_CLOCK_TYPE_WORD_CLOCK,
48 PCXHR_CLOCK_TYPE_AES_SYNC,
49 PCXHR_CLOCK_TYPE_AES_1,
50 PCXHR_CLOCK_TYPE_AES_2,
51 PCXHR_CLOCK_TYPE_AES_3,
52 PCXHR_CLOCK_TYPE_AES_4,
53};
54
55struct pcxhr_mgr {
56 unsigned int num_cards;
57 struct snd_pcxhr *chip[PCXHR_MAX_CARDS];
58
59 struct pci_dev *pci;
60
61 int irq;
62
63 /* card access with 1 mem bar and 2 io bar's */
64 unsigned long port[3];
65
66 /* share the name */
67 char shortname[32]; /* short name of this soundcard */
68 char longname[96]; /* name of this soundcard */
69
70 /* message tasklet */
71 struct tasklet_struct msg_taskq;
72 struct pcxhr_rmh *prmh;
73 /* trigger tasklet */
74 struct tasklet_struct trigger_taskq;
75
76 spinlock_t lock; /* interrupt spinlock */
77 spinlock_t msg_lock; /* message spinlock */
78
79 struct semaphore setup_mutex; /* mutex used in hw_params, open and close */
80 struct semaphore mixer_mutex; /* mutex for mixer */
81
82 /* hardware interface */
83 unsigned int dsp_loaded; /* bit flags of loaded dsp indices */
84 unsigned int dsp_version; /* read from embedded once firmware is loaded */
85 int board_has_analog; /* if 0 the board is digital only */
86 int mono_capture; /* if 1 the board does mono capture */
87 int playback_chips; /* 4 or 6 */
88 int capture_chips; /* 4 or 1 */
89 int firmware_num; /* 41 or 42 */
90
91 struct snd_dma_buffer hostport;
92
93 enum pcxhr_clock_type use_clock_type; /* clock type selected by mixer */
94 enum pcxhr_clock_type cur_clock_type; /* current clock type synced */
95 int sample_rate;
96 int ref_count_rate;
97 int timer_toggle; /* timer interrupt toggles between the two values 0x200 and 0x300 */
98 int dsp_time_last; /* the last dsp time (read by interrupt) */
99 int dsp_time_err; /* dsp time errors */
100 unsigned int src_it_dsp; /* dsp interrupt source */
101 unsigned int io_num_reg_cont; /* backup of IO_NUM_REG_CONT */
102 unsigned int codec_speed; /* speed mode of the codecs */
103 unsigned int sample_rate_real; /* current real sample rate */
104 int last_reg_stat;
105 int async_err_stream_xrun;
106 int async_err_pipe_xrun;
107 int async_err_other_last;
108};
109
110
111enum pcxhr_stream_status {
112 PCXHR_STREAM_STATUS_FREE,
113 PCXHR_STREAM_STATUS_OPEN,
114 PCXHR_STREAM_STATUS_SCHEDULE_RUN,
115 PCXHR_STREAM_STATUS_STARTED,
116 PCXHR_STREAM_STATUS_RUNNING,
117 PCXHR_STREAM_STATUS_SCHEDULE_STOP,
118 PCXHR_STREAM_STATUS_STOPPED,
119 PCXHR_STREAM_STATUS_PAUSED
120};
121
122struct pcxhr_stream {
123 struct snd_pcm_substream *substream;
124 snd_pcm_format_t format;
125 struct pcxhr_pipe *pipe;
126
127 enum pcxhr_stream_status status; /* free, open, running, draining, pause */
128
129 u_int64_t timer_abs_periods; /* timer: samples elapsed since TRIGGER_START (multiple of period_size) */
130 u_int32_t timer_period_frag; /* timer: samples elapsed since last call to snd_pcm_period_elapsed (0..period_size) */
131 u_int32_t timer_buf_periods; /* nb of periods in the buffer that have already elapsed */
132 int timer_is_synced; /* if(0) : timer needs to be resynced with real hardware pointer */
133
134 int channels;
135};
136
137
138enum pcxhr_pipe_status {
139 PCXHR_PIPE_UNDEFINED,
140 PCXHR_PIPE_DEFINED
141};
142
143struct pcxhr_pipe {
144 enum pcxhr_pipe_status status;
145 int is_capture; /* this is a capture pipe */
146 int first_audio; /* first audio num */
147};
148
149
150struct snd_pcxhr {
151 struct snd_card *card;
152 struct pcxhr_mgr *mgr;
153 int chip_idx; /* zero based */
154
155 struct snd_pcm *pcm; /* PCM */
156
157 struct pcxhr_pipe playback_pipe; /* 1 stereo pipe only */
158 struct pcxhr_pipe capture_pipe[2]; /* 1 stereo pipe or 2 mono pipes */
159
160 struct pcxhr_stream playback_stream[PCXHR_PLAYBACK_STREAMS];
161 struct pcxhr_stream capture_stream[2]; /* 1 stereo stream or 2 mono streams */
162 int nb_streams_play;
163 int nb_streams_capt;
164
165 int analog_playback_active[2]; /* Mixer : Master Playback active (!mute) */
166 int analog_playback_volume[2]; /* Mixer : Master Playback Volume */
167 int analog_capture_volume[2]; /* Mixer : Master Capture Volume */
168 int digital_playback_active[PCXHR_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Active [streams][stereo]*/
169 int digital_playback_volume[PCXHR_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Volume [streams][stereo]*/
170 int digital_capture_volume[2]; /* Mixer : Digital Capture Volume [stereo] */
171 int monitoring_active[2]; /* Mixer : Monitoring Active */
172 int monitoring_volume[2]; /* Mixer : Monitoring Volume */
173 int audio_capture_source; /* Mixer : Audio Capture Source */
174 unsigned char aes_bits[5]; /* Mixer : IEC958_AES bits */
175};
176
177struct pcxhr_hostport
178{
179 char purgebuffer[6];
180 char reserved[2];
181};
182
183/* exported */
184int pcxhr_create_pcm(struct snd_pcxhr *chip);
185int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate);
186int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate);
187
188#endif /* __SOUND_PCXHR_H */
diff --git a/sound/pci/pcxhr/pcxhr_core.c b/sound/pci/pcxhr/pcxhr_core.c
new file mode 100644
index 000000000000..fa0d27e2c79b
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_core.c
@@ -0,0 +1,1214 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * low level interface with interrupt and message handling implementation
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <sound/driver.h>
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/interrupt.h>
27#include <asm/io.h>
28#include <sound/core.h>
29#include "pcxhr.h"
30#include "pcxhr_mixer.h"
31#include "pcxhr_hwdep.h"
32#include "pcxhr_core.h"
33
34
35/* registers used on the PLX (port 1) */
36#define PCXHR_PLX_OFFSET_MIN 0x40
37#define PCXHR_PLX_MBOX0 0x40
38#define PCXHR_PLX_MBOX1 0x44
39#define PCXHR_PLX_MBOX2 0x48
40#define PCXHR_PLX_MBOX3 0x4C
41#define PCXHR_PLX_MBOX4 0x50
42#define PCXHR_PLX_MBOX5 0x54
43#define PCXHR_PLX_MBOX6 0x58
44#define PCXHR_PLX_MBOX7 0x5C
45#define PCXHR_PLX_L2PCIDB 0x64
46#define PCXHR_PLX_IRQCS 0x68
47#define PCXHR_PLX_CHIPSC 0x6C
48
49/* registers used on the DSP (port 2) */
50#define PCXHR_DSP_ICR 0x00
51#define PCXHR_DSP_CVR 0x04
52#define PCXHR_DSP_ISR 0x08
53#define PCXHR_DSP_IVR 0x0C
54#define PCXHR_DSP_RXH 0x14
55#define PCXHR_DSP_TXH 0x14
56#define PCXHR_DSP_RXM 0x18
57#define PCXHR_DSP_TXM 0x18
58#define PCXHR_DSP_RXL 0x1C
59#define PCXHR_DSP_TXL 0x1C
60#define PCXHR_DSP_RESET 0x20
61#define PCXHR_DSP_OFFSET_MAX 0x20
62
63/* access to the card */
64#define PCXHR_PLX 1
65#define PCXHR_DSP 2
66
67#if (PCXHR_DSP_OFFSET_MAX > PCXHR_PLX_OFFSET_MIN)
68#undef PCXHR_REG_TO_PORT(x)
69#else
70#define PCXHR_REG_TO_PORT(x) ((x)>PCXHR_DSP_OFFSET_MAX ? PCXHR_PLX : PCXHR_DSP)
71#endif
72#define PCXHR_INPB(mgr,x) inb((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
73#define PCXHR_INPL(mgr,x) inl((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
74#define PCXHR_OUTPB(mgr,x,data) outb((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
75#define PCXHR_OUTPL(mgr,x,data) outl((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
76/* attention : access the PCXHR_DSP_* registers with inb and outb only ! */
77
78/* params used with PCXHR_PLX_MBOX0 */
79#define PCXHR_MBOX0_HF5 (1 << 0)
80#define PCXHR_MBOX0_HF4 (1 << 1)
81#define PCXHR_MBOX0_BOOT_HERE (1 << 23)
82/* params used with PCXHR_PLX_IRQCS */
83#define PCXHR_IRQCS_ENABLE_PCIIRQ (1 << 8)
84#define PCXHR_IRQCS_ENABLE_PCIDB (1 << 9)
85#define PCXHR_IRQCS_ACTIVE_PCIDB (1 << 13)
86/* params used with PCXHR_PLX_CHIPSC */
87#define PCXHR_CHIPSC_INIT_VALUE 0x100D767E
88#define PCXHR_CHIPSC_RESET_XILINX (1 << 16)
89#define PCXHR_CHIPSC_GPI_USERI (1 << 17)
90#define PCXHR_CHIPSC_DATA_CLK (1 << 24)
91#define PCXHR_CHIPSC_DATA_IN (1 << 26)
92
93/* params used with PCXHR_DSP_ICR */
94#define PCXHR_ICR_HI08_RREQ 0x01
95#define PCXHR_ICR_HI08_TREQ 0x02
96#define PCXHR_ICR_HI08_HDRQ 0x04
97#define PCXHR_ICR_HI08_HF0 0x08
98#define PCXHR_ICR_HI08_HF1 0x10
99#define PCXHR_ICR_HI08_HLEND 0x20
100#define PCXHR_ICR_HI08_INIT 0x80
101/* params used with PCXHR_DSP_CVR */
102#define PCXHR_CVR_HI08_HC 0x80
103/* params used with PCXHR_DSP_ISR */
104#define PCXHR_ISR_HI08_RXDF 0x01
105#define PCXHR_ISR_HI08_TXDE 0x02
106#define PCXHR_ISR_HI08_TRDY 0x04
107#define PCXHR_ISR_HI08_ERR 0x08
108#define PCXHR_ISR_HI08_CHK 0x10
109#define PCXHR_ISR_HI08_HREQ 0x80
110
111
112/* constants used for delay in msec */
113#define PCXHR_WAIT_DEFAULT 2
114#define PCXHR_WAIT_IT 25
115#define PCXHR_WAIT_IT_EXTRA 65
116
117/*
118 * pcxhr_check_reg_bit - wait for the specified bit is set/reset on a register
119 * @reg: register to check
120 * @mask: bit mask
121 * @bit: resultant bit to be checked
122 * @time: time-out of loop in msec
123 *
124 * returns zero if a bit matches, or a negative error code.
125 */
126static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg,
127 unsigned char mask, unsigned char bit, int time,
128 unsigned char* read)
129{
130 int i = 0;
131 unsigned long end_time = jiffies + (time * HZ + 999) / 1000;
132 do {
133 *read = PCXHR_INPB(mgr, reg);
134 if ((*read & mask) == bit) {
135 if (i > 100)
136 snd_printdd("ATTENTION! check_reg(%x) loopcount=%d\n",
137 reg, i);
138 return 0;
139 }
140 i++;
141 } while (time_after_eq(end_time, jiffies));
142 snd_printk(KERN_ERR "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=0x%x\n",
143 reg, mask, *read);
144 return -EIO;
145}
146
147/* constants used with pcxhr_check_reg_bit() */
148#define PCXHR_TIMEOUT_DSP 200
149
150
151#define PCXHR_MASK_EXTRA_INFO 0x0000FE
152#define PCXHR_MASK_IT_HF0 0x000100
153#define PCXHR_MASK_IT_HF1 0x000200
154#define PCXHR_MASK_IT_NO_HF0_HF1 0x000400
155#define PCXHR_MASK_IT_MANAGE_HF5 0x000800
156#define PCXHR_MASK_IT_WAIT 0x010000
157#define PCXHR_MASK_IT_WAIT_EXTRA 0x020000
158
159#define PCXHR_IT_SEND_BYTE_XILINX (0x0000003C | PCXHR_MASK_IT_HF0)
160#define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \
161 PCXHR_MASK_IT_MANAGE_HF5)
162#define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \
163 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT)
164#define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \
165 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT_EXTRA)
166#define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \
167 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT)
168#define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1)
169#define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1)
170#define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1)
171#define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1)
172#define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1)
173
174static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atomic)
175{
176 int err;
177 unsigned char reg;
178
179 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
180 /* clear hf5 bit */
181 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0,
182 PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5);
183 }
184 if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) {
185 reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ;
186 if (itdsp & PCXHR_MASK_IT_HF0)
187 reg |= PCXHR_ICR_HI08_HF0;
188 if (itdsp & PCXHR_MASK_IT_HF1)
189 reg |= PCXHR_ICR_HI08_HF1;
190 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
191 }
192 reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | PCXHR_CVR_HI08_HC);
193 PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg);
194 if (itdsp & PCXHR_MASK_IT_WAIT) {
195 if (atomic)
196 mdelay(PCXHR_WAIT_IT);
197 else
198 msleep(PCXHR_WAIT_IT);
199 }
200 if (itdsp & PCXHR_MASK_IT_WAIT_EXTRA) {
201 if (atomic)
202 mdelay(PCXHR_WAIT_IT_EXTRA);
203 else
204 msleep(PCXHR_WAIT_IT);
205 }
206 /* wait for CVR_HI08_HC == 0 */
207 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_CVR, PCXHR_CVR_HI08_HC, 0,
208 PCXHR_TIMEOUT_DSP, &reg);
209 if (err) {
210 snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT CVR\n");
211 return err;
212 }
213 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
214 /* wait for hf5 bit */
215 err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5,
216 PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &reg);
217 if (err) {
218 snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT HF5\n");
219 return err;
220 }
221 }
222 return 0; /* retry not handled here */
223}
224
225void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr)
226{
227 /* reset second xilinx */
228 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC,
229 PCXHR_CHIPSC_INIT_VALUE & ~PCXHR_CHIPSC_RESET_XILINX);
230}
231
232static void pcxhr_enable_irq(struct pcxhr_mgr *mgr, int enable)
233{
234 unsigned int reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS);
235 /* enable/disable interrupts */
236 if (enable)
237 reg |= (PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB);
238 else
239 reg &= ~(PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB);
240 PCXHR_OUTPL(mgr, PCXHR_PLX_IRQCS, reg);
241}
242
243void pcxhr_reset_dsp(struct pcxhr_mgr *mgr)
244{
245 /* disable interrupts */
246 pcxhr_enable_irq(mgr, 0);
247
248 /* let's reset the DSP */
249 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 0);
250 msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
251 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 3);
252 msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
253
254 /* reset mailbox */
255 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, 0);
256}
257
258void pcxhr_enable_dsp(struct pcxhr_mgr *mgr)
259{
260 /* enable interrupts */
261 pcxhr_enable_irq(mgr, 1);
262}
263
264/*
265 * load the xilinx image
266 */
267int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second)
268{
269 unsigned int i;
270 unsigned int chipsc;
271 unsigned char data;
272 unsigned char mask;
273 unsigned char *image;
274
275 /* test first xilinx */
276 chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC);
277 if (!second) {
278 if (chipsc & PCXHR_CHIPSC_GPI_USERI) {
279 snd_printdd("no need to load first xilinx\n");
280 return 0; /* first xilinx is already present and cannot be reset */
281 }
282 } else {
283 if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) {
284 snd_printk(KERN_ERR "error loading first xilinx\n");
285 return -EINVAL;
286 }
287 /* activate second xilinx */
288 chipsc |= PCXHR_CHIPSC_RESET_XILINX;
289 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
290 msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
291 }
292 image = xilinx->data;
293 for (i = 0; i < xilinx->size; i++, image++) {
294 data = *image;
295 mask = 0x80;
296 while (mask) {
297 chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN);
298 if (data & mask)
299 chipsc |= PCXHR_CHIPSC_DATA_IN;
300 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
301 chipsc |= PCXHR_CHIPSC_DATA_CLK;
302 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
303 mask >>= 1;
304 }
305 /* don't take too much time in this loop... */
306 cond_resched();
307 }
308 chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN);
309 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
310 /* wait 2 msec (time to boot the xilinx before any access) */
311 msleep( PCXHR_WAIT_DEFAULT );
312 return 0;
313}
314
315/*
316 * send an executable file to the DSP
317 */
318static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp)
319{
320 int err;
321 unsigned int i;
322 unsigned int len;
323 unsigned char *data;
324 unsigned char dummy;
325 /* check the length of boot image */
326 snd_assert(dsp->size > 0, return -EINVAL);
327 snd_assert(dsp->size % 3 == 0, return -EINVAL);
328 snd_assert(dsp->data, return -EINVAL);
329 /* transfert data buffer from PC to DSP */
330 for (i = 0; i < dsp->size; i += 3) {
331 data = dsp->data + i;
332 if (i == 0) {
333 /* test data header consistency */
334 len = (unsigned int)((data[0]<<16) + (data[1]<<8) + data[2]);
335 snd_assert((len==0) || (dsp->size == (len+2)*3), return -EINVAL);
336 }
337 /* wait DSP ready for new transfer */
338 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
339 PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &dummy);
340 if (err) {
341 snd_printk(KERN_ERR "dsp loading error at position %d\n", i);
342 return err;
343 }
344 /* send host data */
345 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, data[0]);
346 PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, data[1]);
347 PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, data[2]);
348
349 /* don't take too much time in this loop... */
350 cond_resched();
351 }
352 /* give some time to boot the DSP */
353 msleep(PCXHR_WAIT_DEFAULT);
354 return 0;
355}
356
357/*
358 * load the eeprom image
359 */
360int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom)
361{
362 int err;
363 unsigned char reg;
364
365 /* init value of the ICR register */
366 reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ;
367 if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) {
368 /* no need to load the eeprom binary, but init the HI08 interface */
369 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT);
370 msleep(PCXHR_WAIT_DEFAULT);
371 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
372 msleep(PCXHR_WAIT_DEFAULT);
373 snd_printdd("no need to load eeprom boot\n");
374 return 0;
375 }
376 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
377
378 err = pcxhr_download_dsp(mgr, eeprom);
379 if (err)
380 return err;
381 /* wait for chk bit */
382 return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
383 PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
384}
385
386/*
387 * load the boot image
388 */
389int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot)
390{
391 int err;
392 unsigned int physaddr = mgr->hostport.addr;
393 unsigned char dummy;
394
395 /* send the hostport address to the DSP (only the upper 24 bit !) */
396 snd_assert((physaddr & 0xff) == 0, return -EINVAL);
397 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX1, (physaddr >> 8));
398
399 err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_BOOT, 0);
400 if (err)
401 return err;
402 /* clear hf5 bit */
403 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0,
404 PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5);
405
406 err = pcxhr_download_dsp(mgr, boot);
407 if (err)
408 return err;
409 /* wait for hf5 bit */
410 return pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5,
411 PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &dummy);
412}
413
414/*
415 * load the final dsp image
416 */
417int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp)
418{
419 int err;
420 unsigned char dummy;
421 err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_BOARD_FUNC, 0);
422 if (err)
423 return err;
424 err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_DSP, 0);
425 if (err)
426 return err;
427 err = pcxhr_download_dsp(mgr, dsp);
428 if (err)
429 return err;
430 /* wait for chk bit */
431 return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
432 PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &dummy);
433}
434
435
436struct pcxhr_cmd_info {
437 u32 opcode; /* command word */
438 u16 st_length; /* status length */
439 u16 st_type; /* status type (RMH_SSIZE_XXX) */
440};
441
442/* RMH status type */
443enum {
444 RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */
445 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte (used with st_length = 1) */
446 RMH_SSIZE_MASK = 2, /* status size given in bitmask (used with st_length = 1) */
447};
448
449/*
450 * Array of DSP commands
451 */
452static struct pcxhr_cmd_info pcxhr_dsp_cmds[] = {
453[CMD_VERSION] = { 0x010000, 1, RMH_SSIZE_FIXED },
454[CMD_SUPPORTED] = { 0x020000, 4, RMH_SSIZE_FIXED },
455[CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED },
456[CMD_SEND_IRQA] = { 0x070001, 0, RMH_SSIZE_FIXED },
457[CMD_ACCESS_IO_WRITE] = { 0x090000, 1, RMH_SSIZE_ARG },
458[CMD_ACCESS_IO_READ] = { 0x094000, 1, RMH_SSIZE_ARG },
459[CMD_ASYNC] = { 0x0a0000, 1, RMH_SSIZE_ARG },
460[CMD_MODIFY_CLOCK] = { 0x0d0000, 0, RMH_SSIZE_FIXED },
461[CMD_RESYNC_AUDIO_INPUTS] = { 0x0e0000, 0, RMH_SSIZE_FIXED },
462[CMD_GET_DSP_RESOURCES] = { 0x100000, 4, RMH_SSIZE_FIXED },
463[CMD_SET_TIMER_INTERRUPT] = { 0x110000, 0, RMH_SSIZE_FIXED },
464[CMD_RES_PIPE] = { 0x400000, 0, RMH_SSIZE_FIXED },
465[CMD_FREE_PIPE] = { 0x410000, 0, RMH_SSIZE_FIXED },
466[CMD_CONF_PIPE] = { 0x422101, 0, RMH_SSIZE_FIXED },
467[CMD_STOP_PIPE] = { 0x470004, 0, RMH_SSIZE_FIXED },
468[CMD_PIPE_SAMPLE_COUNT] = { 0x49a000, 2, RMH_SSIZE_FIXED },
469[CMD_CAN_START_PIPE] = { 0x4b0000, 1, RMH_SSIZE_FIXED },
470[CMD_START_STREAM] = { 0x802000, 0, RMH_SSIZE_FIXED },
471[CMD_STREAM_OUT_LEVEL_ADJUST] = { 0x822000, 0, RMH_SSIZE_FIXED },
472[CMD_STOP_STREAM] = { 0x832000, 0, RMH_SSIZE_FIXED },
473[CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED },
474[CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED },
475[CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED },
476[CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, /* stat_len = nb_streams * 2 */
477[CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED },
478};
479
480#ifdef CONFIG_SND_DEBUG_DETECT
481static char* cmd_names[] = {
482[CMD_VERSION] = "CMD_VERSION",
483[CMD_SUPPORTED] = "CMD_SUPPORTED",
484[CMD_TEST_IT] = "CMD_TEST_IT",
485[CMD_SEND_IRQA] = "CMD_SEND_IRQA",
486[CMD_ACCESS_IO_WRITE] = "CMD_ACCESS_IO_WRITE",
487[CMD_ACCESS_IO_READ] = "CMD_ACCESS_IO_READ",
488[CMD_ASYNC] = "CMD_ASYNC",
489[CMD_MODIFY_CLOCK] = "CMD_MODIFY_CLOCK",
490[CMD_RESYNC_AUDIO_INPUTS] = "CMD_RESYNC_AUDIO_INPUTS",
491[CMD_GET_DSP_RESOURCES] = "CMD_GET_DSP_RESOURCES",
492[CMD_SET_TIMER_INTERRUPT] = "CMD_SET_TIMER_INTERRUPT",
493[CMD_RES_PIPE] = "CMD_RES_PIPE",
494[CMD_FREE_PIPE] = "CMD_FREE_PIPE",
495[CMD_CONF_PIPE] = "CMD_CONF_PIPE",
496[CMD_STOP_PIPE] = "CMD_STOP_PIPE",
497[CMD_PIPE_SAMPLE_COUNT] = "CMD_PIPE_SAMPLE_COUNT",
498[CMD_CAN_START_PIPE] = "CMD_CAN_START_PIPE",
499[CMD_START_STREAM] = "CMD_START_STREAM",
500[CMD_STREAM_OUT_LEVEL_ADJUST] = "CMD_STREAM_OUT_LEVEL_ADJUST",
501[CMD_STOP_STREAM] = "CMD_STOP_STREAM",
502[CMD_UPDATE_R_BUFFERS] = "CMD_UPDATE_R_BUFFERS",
503[CMD_FORMAT_STREAM_OUT] = "CMD_FORMAT_STREAM_OUT",
504[CMD_FORMAT_STREAM_IN] = "CMD_FORMAT_STREAM_IN",
505[CMD_STREAM_SAMPLE_COUNT] = "CMD_STREAM_SAMPLE_COUNT",
506[CMD_AUDIO_LEVEL_ADJUST] = "CMD_AUDIO_LEVEL_ADJUST",
507};
508#endif
509
510
511static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
512{
513 int err;
514 int i;
515 u32 data;
516 u32 size_mask;
517 unsigned char reg;
518 int max_stat_len;
519
520 if (rmh->stat_len < PCXHR_SIZE_MAX_STATUS)
521 max_stat_len = PCXHR_SIZE_MAX_STATUS;
522 else max_stat_len = rmh->stat_len;
523
524 for (i = 0; i < rmh->stat_len; i++) {
525 /* wait for receiver full */
526 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF,
527 PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg);
528 if (err) {
529 snd_printk(KERN_ERR "ERROR RMH stat: ISR:RXDF=1 (ISR = %x; i=%d )\n",
530 reg, i);
531 return err;
532 }
533 /* read data */
534 data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16;
535 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8;
536 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
537
538 /* need to update rmh->stat_len on the fly ?? */
539 if (i==0) {
540 if (rmh->dsp_stat != RMH_SSIZE_FIXED) {
541 if (rmh->dsp_stat == RMH_SSIZE_ARG) {
542 rmh->stat_len = (u16)(data & 0x0000ff) + 1;
543 data &= 0xffff00;
544 } else {
545 /* rmh->dsp_stat == RMH_SSIZE_MASK */
546 rmh->stat_len = 1;
547 size_mask = data;
548 while (size_mask) {
549 if (size_mask & 1)
550 rmh->stat_len++;
551 size_mask >>= 1;
552 }
553 }
554 }
555 }
556#ifdef CONFIG_SND_DEBUG_DETECT
557 if (rmh->cmd_idx < CMD_LAST_INDEX)
558 snd_printdd(" stat[%d]=%x\n", i, data);
559#endif
560 if (i < max_stat_len)
561 rmh->stat[i] = data;
562 }
563 if (rmh->stat_len > max_stat_len) {
564 snd_printdd("PCXHR : rmh->stat_len=%x too big\n", rmh->stat_len);
565 rmh->stat_len = max_stat_len;
566 }
567 return 0;
568}
569
570static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
571{
572 int err;
573 int i;
574 u32 data;
575 unsigned char reg;
576
577 snd_assert(rmh->cmd_len<PCXHR_SIZE_MAX_CMD, return -EINVAL);
578 err = pcxhr_send_it_dsp(mgr, PCXHR_IT_MESSAGE, 1);
579 if (err) {
580 snd_printk(KERN_ERR "pcxhr_send_message : ED_DSP_CRASHED\n");
581 return err;
582 }
583 /* wait for chk bit */
584 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
585 PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
586 if (err)
587 return err;
588 /* reset irq chk */
589 err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_CHK, 1);
590 if (err)
591 return err;
592 /* wait for chk bit == 0*/
593 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, 0,
594 PCXHR_TIMEOUT_DSP, &reg);
595 if (err)
596 return err;
597
598 data = rmh->cmd[0];
599
600 if (rmh->cmd_len > 1)
601 data |= 0x008000; /* MASK_MORE_THAN_1_WORD_COMMAND */
602 else
603 data &= 0xff7fff; /* MASK_1_WORD_COMMAND */
604#ifdef CONFIG_SND_DEBUG_DETECT
605 if (rmh->cmd_idx < CMD_LAST_INDEX)
606 snd_printdd("MSG cmd[0]=%x (%s)\n", data, cmd_names[rmh->cmd_idx]);
607#endif
608
609 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
610 PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg);
611 if (err)
612 return err;
613 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
614 PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
615 PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
616
617 if (rmh->cmd_len > 1) {
618 /* send length */
619 data = rmh->cmd_len - 1;
620 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
621 PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg);
622 if (err)
623 return err;
624 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
625 PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
626 PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
627
628 for (i=1; i < rmh->cmd_len; i++) {
629 /* send other words */
630 data = rmh->cmd[i];
631#ifdef CONFIG_SND_DEBUG_DETECT
632 if (rmh->cmd_idx < CMD_LAST_INDEX)
633 snd_printdd(" cmd[%d]=%x\n", i, data);
634#endif
635 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
636 PCXHR_ISR_HI08_TRDY,
637 PCXHR_ISR_HI08_TRDY,
638 PCXHR_TIMEOUT_DSP, &reg);
639 if (err)
640 return err;
641 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
642 PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
643 PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
644 }
645 }
646 /* wait for chk bit */
647 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
648 PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
649 if (err)
650 return err;
651 /* test status ISR */
652 if (reg & PCXHR_ISR_HI08_ERR) {
653 /* ERROR, wait for receiver full */
654 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF,
655 PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg);
656 if (err) {
657 snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg);
658 return err;
659 }
660 /* read error code */
661 data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16;
662 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8;
663 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
664 snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n", rmh->cmd_idx, data);
665 err = -EINVAL;
666 } else {
667 /* read the response data */
668 err = pcxhr_read_rmh_status(mgr, rmh);
669 }
670 /* reset semaphore */
671 if (pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_SEMAPHORE, 1) < 0)
672 return -EIO;
673 return err;
674}
675
676
677/**
678 * pcxhr_init_rmh - initialize the RMH instance
679 * @rmh: the rmh pointer to be initialized
680 * @cmd: the rmh command to be set
681 */
682void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd)
683{
684 snd_assert(cmd < CMD_LAST_INDEX, return);
685 rmh->cmd[0] = pcxhr_dsp_cmds[cmd].opcode;
686 rmh->cmd_len = 1;
687 rmh->stat_len = pcxhr_dsp_cmds[cmd].st_length;
688 rmh->dsp_stat = pcxhr_dsp_cmds[cmd].st_type;
689 rmh->cmd_idx = cmd;
690}
691
692
693void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh *rmh, int capture,
694 unsigned int param1, unsigned int param2,
695 unsigned int param3)
696{
697 snd_assert(param1 <= MASK_FIRST_FIELD);
698 if (capture)
699 rmh->cmd[0] |= 0x800; /* COMMAND_RECORD_MASK */
700 if (param1)
701 rmh->cmd[0] |= (param1 << FIELD_SIZE);
702 if (param2) {
703 snd_assert(param2 <= MASK_FIRST_FIELD);
704 rmh->cmd[0] |= param2;
705 }
706 if(param3) {
707 snd_assert(param3 <= MASK_DSP_WORD);
708 rmh->cmd[1] = param3;
709 rmh->cmd_len = 2;
710 }
711}
712
713/*
714 * pcxhr_send_msg - send a DSP message with spinlock
715 * @rmh: the rmh record to send and receive
716 *
717 * returns 0 if successful, or a negative error code.
718 */
719int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
720{
721 unsigned long flags;
722 int err;
723 spin_lock_irqsave(&mgr->msg_lock, flags);
724 err = pcxhr_send_msg_nolock(mgr, rmh);
725 spin_unlock_irqrestore(&mgr->msg_lock, flags);
726 return err;
727}
728
729static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr)
730{
731 int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2);
732 /* least segnificant 12 bits are the pipe states for the playback audios */
733 /* next 12 bits are the pipe states for the capture audios
734 * (PCXHR_PIPE_STATE_CAPTURE_OFFSET)
735 */
736 start_mask &= 0xffffff;
737 snd_printdd("CMD_PIPE_STATE MBOX2=0x%06x\n", start_mask);
738 return start_mask;
739}
740
741#define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12
742#define MAX_WAIT_FOR_DSP 20
743
744static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *retry)
745{
746 struct pcxhr_rmh rmh;
747 int err;
748 int audio = 0;
749
750 *retry = 0;
751 while (audio_mask) {
752 if (audio_mask & 1) {
753 pcxhr_init_rmh(&rmh, CMD_CAN_START_PIPE);
754 if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) {
755 /* can start playback pipe */
756 pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);
757 } else {
758 /* can start capture pipe */
759 pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
760 PCXHR_PIPE_STATE_CAPTURE_OFFSET,
761 0, 0);
762 }
763 err = pcxhr_send_msg(mgr, &rmh);
764 if (err) {
765 snd_printk(KERN_ERR
766 "error pipe start (CMD_CAN_START_PIPE) err=%x!\n",
767 err);
768 return err;
769 }
770 /* if the pipe couldn't be prepaired for start, retry it later */
771 if (rmh.stat[0] == 0)
772 *retry |= (1<<audio);
773 }
774 audio_mask>>=1;
775 audio++;
776 }
777 return 0;
778}
779
780static int pcxhr_stop_pipes(struct pcxhr_mgr *mgr, int audio_mask)
781{
782 struct pcxhr_rmh rmh;
783 int err;
784 int audio = 0;
785
786 while (audio_mask) {
787 if (audio_mask & 1) {
788 pcxhr_init_rmh(&rmh, CMD_STOP_PIPE);
789 if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) {
790 /* stop playback pipe */
791 pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);
792 } else {
793 /* stop capture pipe */
794 pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
795 PCXHR_PIPE_STATE_CAPTURE_OFFSET,
796 0, 0);
797 }
798 err = pcxhr_send_msg(mgr, &rmh);
799 if (err) {
800 snd_printk(KERN_ERR
801 "error pipe stop (CMD_STOP_PIPE) err=%x!\n",
802 err);
803 return err;
804 }
805 }
806 audio_mask>>=1;
807 audio++;
808 }
809 return 0;
810}
811
812static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask)
813{
814 struct pcxhr_rmh rmh;
815 int err;
816 int audio = 0;
817
818 while (audio_mask) {
819 if (audio_mask & 1) {
820 pcxhr_init_rmh(&rmh, CMD_CONF_PIPE);
821 if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET)
822 pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, 1 << audio);
823 else
824 pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0,
825 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET));
826 err = pcxhr_send_msg(mgr, &rmh);
827 if (err) {
828 snd_printk(KERN_ERR
829 "error pipe start (CMD_CONF_PIPE) err=%x!\n",
830 err);
831 return err;
832 }
833 }
834 audio_mask>>=1;
835 audio++;
836 }
837 /* now fire the interrupt on the card */
838 pcxhr_init_rmh(&rmh, CMD_SEND_IRQA);
839 err = pcxhr_send_msg(mgr, &rmh);
840 if (err) {
841 snd_printk(KERN_ERR "error pipe start (CMD_SEND_IRQA) err=%x!\n", err );
842 return err;
843 }
844 return 0;
845}
846
847
848
849int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start)
850{
851 int state, i, err;
852 int audio_mask;
853
854#ifdef CONFIG_SND_DEBUG_DETECT
855 struct timeval my_tv1, my_tv2;
856 do_gettimeofday(&my_tv1);
857#endif
858 audio_mask = (playback_mask | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET));
859 /* current pipe state (playback + record) */
860 state = pcxhr_pipes_running(mgr);
861 snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n",
862 start ? "START" : "STOP", audio_mask, state);
863 if (start) {
864 audio_mask &= ~state; /* start only pipes that are not yet started */
865 state = audio_mask;
866 for (i = 0; i < MAX_WAIT_FOR_DSP; i++) {
867 err = pcxhr_prepair_pipe_start(mgr, state, &state);
868 if (err)
869 return err;
870 if (state == 0)
871 break; /* success, all pipes prepaired for start */
872 mdelay(1); /* otherwise wait 1 millisecond and retry */
873 }
874 } else {
875 audio_mask &= state; /* stop only pipes that are started */
876 }
877 if (audio_mask == 0)
878 return 0;
879
880 err = pcxhr_toggle_pipes(mgr, audio_mask);
881 if (err)
882 return err;
883
884 i = 0;
885 while (1) {
886 state = pcxhr_pipes_running(mgr);
887 /* have all pipes the new state ? */
888 if ((state & audio_mask) == (start ? audio_mask : 0))
889 break;
890 if (++i >= MAX_WAIT_FOR_DSP * 100) {
891 snd_printk(KERN_ERR "error pipe start/stop (ED_NO_RESPONSE_AT_IRQA)\n");
892 return -EBUSY;
893 }
894 udelay(10); /* wait 10 microseconds */
895 }
896 if (!start) {
897 err = pcxhr_stop_pipes(mgr, audio_mask);
898 if (err)
899 return err;
900 }
901#ifdef CONFIG_SND_DEBUG_DETECT
902 do_gettimeofday(&my_tv2);
903 snd_printdd("***SET PIPE STATE*** TIME = %ld (err = %x)\n",
904 my_tv2.tv_usec - my_tv1.tv_usec, err);
905#endif
906 return 0;
907}
908
909int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
910 unsigned int value, int *changed)
911{
912 struct pcxhr_rmh rmh;
913 unsigned long flags;
914 int err;
915
916 spin_lock_irqsave(&mgr->msg_lock, flags);
917 if ((mgr->io_num_reg_cont & mask) == value) {
918 snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n", mask, value);
919 if (changed)
920 *changed = 0;
921 spin_unlock_irqrestore(&mgr->msg_lock, flags);
922 return 0; /* already programmed */
923 }
924 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
925 rmh.cmd[0] |= IO_NUM_REG_CONT;
926 rmh.cmd[1] = mask;
927 rmh.cmd[2] = value;
928 rmh.cmd_len = 3;
929 err = pcxhr_send_msg_nolock(mgr, &rmh);
930 if (err == 0) {
931 mgr->io_num_reg_cont &= ~mask;
932 mgr->io_num_reg_cont |= value;
933 if (changed)
934 *changed = 1;
935 }
936 spin_unlock_irqrestore(&mgr->msg_lock, flags);
937 return err;
938}
939
940#define PCXHR_IRQ_TIMER 0x000300
941#define PCXHR_IRQ_FREQ_CHANGE 0x000800
942#define PCXHR_IRQ_TIME_CODE 0x001000
943#define PCXHR_IRQ_NOTIFY 0x002000
944#define PCXHR_IRQ_ASYNC 0x008000
945#define PCXHR_IRQ_MASK 0x00bb00
946#define PCXHR_FATAL_DSP_ERR 0xff0000
947
948enum pcxhr_async_err_src {
949 PCXHR_ERR_PIPE,
950 PCXHR_ERR_STREAM,
951 PCXHR_ERR_AUDIO
952};
953
954static int pcxhr_handle_async_err(struct pcxhr_mgr *mgr, u32 err,
955 enum pcxhr_async_err_src err_src, int pipe,
956 int is_capture)
957{
958#ifdef CONFIG_SND_DEBUG_DETECT
959 static char* err_src_name[] = {
960 [PCXHR_ERR_PIPE] = "Pipe",
961 [PCXHR_ERR_STREAM] = "Stream",
962 [PCXHR_ERR_AUDIO] = "Audio"
963 };
964#endif
965 if (err & 0xfff)
966 err &= 0xfff;
967 else
968 err = ((err >> 12) & 0xfff);
969 if (!err)
970 return 0;
971 snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n", err_src_name[err_src],
972 is_capture ? "Record" : "Play", pipe, err);
973 if (err == 0xe01)
974 mgr->async_err_stream_xrun++;
975 else if (err == 0xe10)
976 mgr->async_err_pipe_xrun++;
977 else
978 mgr->async_err_other_last = (int)err;
979 return 1;
980}
981
982
983void pcxhr_msg_tasklet(unsigned long arg)
984{
985 struct pcxhr_mgr *mgr = (struct pcxhr_mgr *)(arg);
986 struct pcxhr_rmh *prmh = mgr->prmh;
987 int err;
988 int i, j;
989
990 if (mgr->src_it_dsp & PCXHR_IRQ_FREQ_CHANGE)
991 snd_printdd("TASKLET : PCXHR_IRQ_FREQ_CHANGE event occured\n");
992 if (mgr->src_it_dsp & PCXHR_IRQ_TIME_CODE)
993 snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n");
994 if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY)
995 snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n");
996 if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) {
997 snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n");
998
999 pcxhr_init_rmh(prmh, CMD_ASYNC);
1000 prmh->cmd[0] |= 1; /* add SEL_ASYNC_EVENTS */
1001 /* this is the only one extra long response command */
1002 prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS;
1003 err = pcxhr_send_msg(mgr, prmh);
1004 if (err)
1005 snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n", err);
1006 i = 1;
1007 while (i < prmh->stat_len) {
1008 int nb_audio = (prmh->stat[i] >> FIELD_SIZE) & MASK_FIRST_FIELD;
1009 int nb_stream = (prmh->stat[i] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD;
1010 int pipe = prmh->stat[i] & MASK_FIRST_FIELD;
1011 int is_capture = prmh->stat[i] & 0x400000;
1012 u32 err;
1013
1014 if (prmh->stat[i] & 0x800000) { /* if BIT_END */
1015 snd_printdd("TASKLET : End%sPipe %d\n",
1016 is_capture ? "Record" : "Play", pipe);
1017 }
1018 i++;
1019 err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
1020 if (err)
1021 pcxhr_handle_async_err(mgr, err, PCXHR_ERR_PIPE,
1022 pipe, is_capture);
1023 i += 2;
1024 for (j = 0; j < nb_stream; j++) {
1025 err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
1026 if (err)
1027 pcxhr_handle_async_err(mgr, err, PCXHR_ERR_STREAM,
1028 pipe, is_capture);
1029 i += 2;
1030 }
1031 for (j = 0; j < nb_audio; j++) {
1032 err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
1033 if (err)
1034 pcxhr_handle_async_err(mgr, err, PCXHR_ERR_AUDIO,
1035 pipe, is_capture);
1036 i += 2;
1037 }
1038 }
1039 }
1040}
1041
1042static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr,
1043 struct pcxhr_stream *stream)
1044{
1045 u_int64_t hw_sample_count;
1046 struct pcxhr_rmh rmh;
1047 int err, stream_mask;
1048
1049 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
1050
1051 /* get sample count for one stream */
1052 pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT);
1053 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
1054 stream->pipe->first_audio, 0, stream_mask);
1055 /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */
1056
1057 err = pcxhr_send_msg(mgr, &rmh);
1058 if (err)
1059 return 0;
1060
1061 hw_sample_count = ((u_int64_t)rmh.stat[0]) << 24;
1062 hw_sample_count += (u_int64_t)rmh.stat[1];
1063
1064 snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n",
1065 stream->pipe->is_capture ? 'C':'P', stream->substream->number,
1066 (long unsigned int)hw_sample_count,
1067 (long unsigned int)(stream->timer_abs_periods +
1068 stream->timer_period_frag + PCXHR_GRANULARITY));
1069
1070 return hw_sample_count;
1071}
1072
1073static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
1074 struct pcxhr_stream *stream, int samples_to_add)
1075{
1076 if (stream->substream && (stream->status == PCXHR_STREAM_STATUS_RUNNING)) {
1077 u_int64_t new_sample_count;
1078 int elapsed = 0;
1079 int hardware_read = 0;
1080 struct snd_pcm_runtime *runtime = stream->substream->runtime;
1081
1082 if (samples_to_add < 0) {
1083 stream->timer_is_synced = 0;
1084 /* add default if no hardware_read possible */
1085 samples_to_add = PCXHR_GRANULARITY;
1086 }
1087
1088 if (!stream->timer_is_synced) {
1089 if (stream->timer_abs_periods != 0 ||
1090 stream->timer_period_frag + PCXHR_GRANULARITY >=
1091 runtime->period_size) {
1092 new_sample_count = pcxhr_stream_read_position(mgr, stream);
1093 hardware_read = 1;
1094 if (new_sample_count >= PCXHR_GRANULARITY_MIN) {
1095 /* sub security offset because of jitter and
1096 * finer granularity of dsp time (MBOX4)
1097 */
1098 new_sample_count -= PCXHR_GRANULARITY_MIN;
1099 stream->timer_is_synced = 1;
1100 }
1101 }
1102 }
1103 if (!hardware_read) {
1104 /* if we didn't try to sync the position, increment it
1105 * by PCXHR_GRANULARITY every timer interrupt
1106 */
1107 new_sample_count = stream->timer_abs_periods +
1108 stream->timer_period_frag + samples_to_add;
1109 }
1110 while (1) {
1111 u_int64_t new_elapse_pos = stream->timer_abs_periods +
1112 runtime->period_size;
1113 if (new_elapse_pos > new_sample_count)
1114 break;
1115 elapsed = 1;
1116 stream->timer_buf_periods++;
1117 if (stream->timer_buf_periods >= runtime->periods)
1118 stream->timer_buf_periods = 0;
1119 stream->timer_abs_periods = new_elapse_pos;
1120 }
1121 if (new_sample_count >= stream->timer_abs_periods)
1122 stream->timer_period_frag = (u_int32_t)(new_sample_count -
1123 stream->timer_abs_periods);
1124 else
1125 snd_printk(KERN_ERR "ERROR new_sample_count too small ??? %lx\n",
1126 (long unsigned int)new_sample_count);
1127
1128 if (elapsed) {
1129 spin_unlock(&mgr->lock);
1130 snd_pcm_period_elapsed(stream->substream);
1131 spin_lock(&mgr->lock);
1132 }
1133 }
1134}
1135
1136
1137irqreturn_t pcxhr_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1138{
1139 struct pcxhr_mgr *mgr = dev_id;
1140 unsigned int reg;
1141 int i, j;
1142 struct snd_pcxhr *chip;
1143
1144 spin_lock(&mgr->lock);
1145
1146 reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS);
1147 if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) {
1148 spin_unlock(&mgr->lock);
1149 return IRQ_NONE; /* this device did not cause the interrupt */
1150 }
1151
1152 /* clear interrupt */
1153 reg = PCXHR_INPL(mgr, PCXHR_PLX_L2PCIDB);
1154 PCXHR_OUTPL(mgr, PCXHR_PLX_L2PCIDB, reg);
1155
1156 /* timer irq occured */
1157 if (reg & PCXHR_IRQ_TIMER) {
1158 int timer_toggle = reg & PCXHR_IRQ_TIMER;
1159 /* is a 24 bit counter */
1160 int dsp_time_new = PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK;
1161 int dsp_time_diff = dsp_time_new - mgr->dsp_time_last;
1162
1163 if (dsp_time_diff < 0 && mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID) {
1164 snd_printdd("ERROR DSP TIME old(%d) new(%d) -> "
1165 "resynchronize all streams\n",
1166 mgr->dsp_time_last, dsp_time_new);
1167 mgr->dsp_time_err++;
1168 }
1169#ifdef CONFIG_SND_DEBUG_DETECT
1170 if (dsp_time_diff == 0)
1171 snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n", dsp_time_new);
1172 else if (dsp_time_diff >= (2*PCXHR_GRANULARITY))
1173 snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n",
1174 mgr->dsp_time_last, dsp_time_new - mgr->dsp_time_last);
1175#endif
1176 mgr->dsp_time_last = dsp_time_new;
1177
1178 if (timer_toggle == mgr->timer_toggle)
1179 snd_printk(KERN_ERR "ERROR TIMER TOGGLE\n");
1180 mgr->timer_toggle = timer_toggle;
1181
1182 reg &= ~PCXHR_IRQ_TIMER;
1183 for (i = 0; i < mgr->num_cards; i++) {
1184 chip = mgr->chip[i];
1185 for (j = 0; j < chip->nb_streams_capt; j++)
1186 pcxhr_update_timer_pos(mgr, &chip->capture_stream[j],
1187 dsp_time_diff);
1188 }
1189 for (i = 0; i < mgr->num_cards; i++) {
1190 chip = mgr->chip[i];
1191 for (j = 0; j < chip->nb_streams_play; j++)
1192 pcxhr_update_timer_pos(mgr, &chip->playback_stream[j],
1193 dsp_time_diff);
1194 }
1195 }
1196 /* other irq's handled in the tasklet */
1197 if (reg & PCXHR_IRQ_MASK) {
1198
1199 /* as we didn't request any notifications, some kind of xrun error
1200 * will probably occured
1201 */
1202 /* better resynchronize all streams next interrupt : */
1203 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
1204
1205 mgr->src_it_dsp = reg;
1206 tasklet_hi_schedule(&mgr->msg_taskq);
1207 }
1208#ifdef CONFIG_SND_DEBUG_DETECT
1209 if (reg & PCXHR_FATAL_DSP_ERR)
1210 snd_printdd("FATAL DSP ERROR : %x\n", reg);
1211#endif
1212 spin_unlock(&mgr->lock);
1213 return IRQ_HANDLED; /* this device caused the interrupt */
1214}
diff --git a/sound/pci/pcxhr/pcxhr_core.h b/sound/pci/pcxhr/pcxhr_core.h
new file mode 100644
index 000000000000..e7415d6d1826
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_core.h
@@ -0,0 +1,200 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * low level interface with interrupt ans message handling
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_PCXHR_CORE_H
24#define __SOUND_PCXHR_CORE_H
25
26struct firmware;
27struct pcxhr_mgr;
28
29/* init and firmware download commands */
30void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr);
31void pcxhr_reset_dsp(struct pcxhr_mgr *mgr);
32void pcxhr_enable_dsp(struct pcxhr_mgr *mgr);
33int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second);
34int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom);
35int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot);
36int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp);
37
38/* DSP time available on MailBox4 register : 24 bit time samples() */
39#define PCXHR_DSP_TIME_MASK 0x00ffffff
40#define PCXHR_DSP_TIME_INVALID 0x10000000
41
42
43#define PCXHR_SIZE_MAX_CMD 8
44#define PCXHR_SIZE_MAX_STATUS 16
45#define PCXHR_SIZE_MAX_LONG_STATUS 256
46
47struct pcxhr_rmh {
48 u16 cmd_len; /* length of the command to send (WORDs) */
49 u16 stat_len; /* length of the status received (WORDs) */
50 u16 dsp_stat; /* status type, RMP_SSIZE_XXX */
51 u16 cmd_idx; /* index of the command */
52 u32 cmd[PCXHR_SIZE_MAX_CMD];
53 u32 stat[PCXHR_SIZE_MAX_STATUS];
54};
55
56enum {
57 CMD_VERSION, /* cmd_len = 2 stat_len = 1 */
58 CMD_SUPPORTED, /* cmd_len = 1 stat_len = 4 */
59 CMD_TEST_IT, /* cmd_len = 1 stat_len = 1 */
60 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
61 CMD_ACCESS_IO_WRITE, /* cmd_len >= 1 stat_len >= 1 */
62 CMD_ACCESS_IO_READ, /* cmd_len >= 1 stat_len >= 1 */
63 CMD_ASYNC, /* cmd_len = 1 stat_len = 1 */
64 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
65 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
66 CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */
67 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
68 CMD_RES_PIPE, /* cmd_len = 2 stat_len = 0 */
69 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
70 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
71 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
72 CMD_PIPE_SAMPLE_COUNT, /* cmd_len = 2 stat_len = 2 */
73 CMD_CAN_START_PIPE, /* cmd_len >= 1 stat_len = 1 */
74 CMD_START_STREAM, /* cmd_len = 2 stat_len = 0 */
75 CMD_STREAM_OUT_LEVEL_ADJUST, /* cmd_len >= 1 stat_len = 0 */
76 CMD_STOP_STREAM, /* cmd_len = 2 stat_len = 0 */
77 CMD_UPDATE_R_BUFFERS, /* cmd_len = 4 stat_len = 0 */
78 CMD_FORMAT_STREAM_OUT, /* cmd_len >= 2 stat_len = 0 */
79 CMD_FORMAT_STREAM_IN, /* cmd_len >= 4 stat_len = 0 */
80 CMD_STREAM_SAMPLE_COUNT, /* cmd_len = 2 stat_len = (2 * nb_stream) */
81 CMD_AUDIO_LEVEL_ADJUST, /* cmd_len = 3 stat_len = 0 */
82 CMD_LAST_INDEX
83};
84
85#define MASK_DSP_WORD 0x00ffffff
86#define MASK_ALL_STREAM 0x00ffffff
87#define MASK_DSP_WORD_LEVEL 0x000001ff
88#define MASK_FIRST_FIELD 0x0000001f
89#define FIELD_SIZE 5
90
91/*
92 init the rmh struct; by default cmd_len is set to 1
93 */
94void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd);
95
96void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1,
97 unsigned int param2, unsigned int param3);
98
99/*
100 send the rmh
101 */
102int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh);
103
104
105/* values used for CMD_ACCESS_IO_WRITE and CMD_ACCESS_IO_READ */
106#define IO_NUM_REG_CONT 0
107#define IO_NUM_REG_GENCLK 1
108#define IO_NUM_REG_MUTE_OUT 2
109#define IO_NUM_SPEED_RATIO 4
110#define IO_NUM_REG_STATUS 5
111#define IO_NUM_REG_CUER 10
112#define IO_NUM_UER_CHIP_REG 11
113#define IO_NUM_REG_OUT_ANA_LEVEL 20
114#define IO_NUM_REG_IN_ANA_LEVEL 21
115
116
117#define REG_CONT_UNMUTE_INPUTS 0x020000
118
119/* parameters used with register IO_NUM_REG_STATUS */
120#define REG_STATUS_OPTIONS 0
121#define REG_STATUS_AES_SYNC 8
122#define REG_STATUS_AES_1 9
123#define REG_STATUS_AES_2 10
124#define REG_STATUS_AES_3 11
125#define REG_STATUS_AES_4 12
126#define REG_STATUS_WORD_CLOCK 13
127#define REG_STATUS_INTER_SYNC 14
128#define REG_STATUS_CURRENT 0x80
129/* results */
130#define REG_STATUS_OPT_NO_VIDEO_SIGNAL 0x01
131#define REG_STATUS_OPT_DAUGHTER_MASK 0x1c
132#define REG_STATUS_OPT_ANALOG_BOARD 0x00
133#define REG_STATUS_OPT_NO_DAUGHTER 0x1c
134#define REG_STATUS_OPT_COMPANION_MASK 0xe0
135#define REG_STATUS_OPT_NO_COMPANION 0xe0
136#define REG_STATUS_SYNC_32000 0x00
137#define REG_STATUS_SYNC_44100 0x01
138#define REG_STATUS_SYNC_48000 0x02
139#define REG_STATUS_SYNC_64000 0x03
140#define REG_STATUS_SYNC_88200 0x04
141#define REG_STATUS_SYNC_96000 0x05
142#define REG_STATUS_SYNC_128000 0x06
143#define REG_STATUS_SYNC_176400 0x07
144#define REG_STATUS_SYNC_192000 0x08
145
146int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start);
147
148int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
149 unsigned int value, int *changed);
150
151/* codec parameters */
152#define CS8416_RUN 0x200401
153#define CS8416_FORMAT_DETECT 0x200b00
154#define CS8416_CSB0 0x201900
155#define CS8416_CSB1 0x201a00
156#define CS8416_CSB2 0x201b00
157#define CS8416_CSB3 0x201c00
158#define CS8416_CSB4 0x201d00
159#define CS8416_VERSION 0x207f00
160
161#define CS8420_DATA_FLOW_CTL 0x200301
162#define CS8420_CLOCK_SRC_CTL 0x200401
163#define CS8420_RECEIVER_ERRORS 0x201000
164#define CS8420_SRC_RATIO 0x201e00
165#define CS8420_CSB0 0x202000
166#define CS8420_CSB1 0x202100
167#define CS8420_CSB2 0x202200
168#define CS8420_CSB3 0x202300
169#define CS8420_CSB4 0x202400
170#define CS8420_VERSION 0x207f00
171
172#define CS4271_MODE_CTL_1 0x200101
173#define CS4271_DAC_CTL 0x200201
174#define CS4271_VOLMIX 0x200301
175#define CS4271_VOLMUTE_LEFT 0x200401
176#define CS4271_VOLMUTE_RIGHT 0x200501
177#define CS4271_ADC_CTL 0x200601
178#define CS4271_MODE_CTL_2 0x200701
179
180#define CHIP_SIG_AND_MAP_SPI 0xff7f00
181
182/* codec selection */
183#define CS4271_01_CS 0x160018
184#define CS4271_23_CS 0x160019
185#define CS4271_45_CS 0x16001a
186#define CS4271_67_CS 0x16001b
187#define CS4271_89_CS 0x16001c
188#define CS4271_AB_CS 0x16001d
189#define CS8420_01_CS 0x080090
190#define CS8420_23_CS 0x080092
191#define CS8420_45_CS 0x080094
192#define CS8420_67_CS 0x080096
193#define CS8416_01_CS 0x080098
194
195
196/* interrupt handling */
197irqreturn_t pcxhr_interrupt(int irq, void *dev_id, struct pt_regs *regs);
198void pcxhr_msg_tasklet(unsigned long arg);
199
200#endif /* __SOUND_PCXHR_CORE_H */
diff --git a/sound/pci/pcxhr/pcxhr_hwdep.c b/sound/pci/pcxhr/pcxhr_hwdep.c
new file mode 100644
index 000000000000..03517c10e99c
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_hwdep.c
@@ -0,0 +1,438 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * hwdep device manager
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <sound/driver.h>
24#include <linux/interrupt.h>
25#include <linux/vmalloc.h>
26#include <linux/firmware.h>
27#include <linux/pci.h>
28#include <asm/io.h>
29#include <sound/core.h>
30#include <sound/hwdep.h>
31#include "pcxhr.h"
32#include "pcxhr_mixer.h"
33#include "pcxhr_hwdep.h"
34#include "pcxhr_core.h"
35
36
37#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
38#if !defined(CONFIG_USE_PCXHRLOADER) && !defined(CONFIG_SND_PCXHR) /* built-in kernel */
39#define SND_PCXHR_FW_LOADER /* use the standard firmware loader */
40#endif
41#endif
42
43
44/*
45 * get basic information and init pcxhr card
46 */
47
48static int pcxhr_init_board(struct pcxhr_mgr *mgr)
49{
50 int err;
51 struct pcxhr_rmh rmh;
52 int card_streams;
53
54 /* calc the number of all streams used */
55 if (mgr->mono_capture)
56 card_streams = mgr->capture_chips * 2;
57 else
58 card_streams = mgr->capture_chips;
59 card_streams += mgr->playback_chips * PCXHR_PLAYBACK_STREAMS;
60
61 /* enable interrupts */
62 pcxhr_enable_dsp(mgr);
63
64 pcxhr_init_rmh(&rmh, CMD_SUPPORTED);
65 err = pcxhr_send_msg(mgr, &rmh);
66 if (err)
67 return err;
68 /* test 8 or 12 phys out */
69 snd_assert((rmh.stat[0] & MASK_FIRST_FIELD) == mgr->playback_chips*2,
70 return -EINVAL);
71 /* test 8 or 2 phys in */
72 snd_assert(((rmh.stat[0] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD) ==
73 mgr->capture_chips * 2, return -EINVAL);
74 /* test max nb substream per board */
75 snd_assert((rmh.stat[1] & 0x5F) >= card_streams, return -EINVAL);
76 /* test max nb substream per pipe */
77 snd_assert(((rmh.stat[1]>>7)&0x5F) >= PCXHR_PLAYBACK_STREAMS, return -EINVAL);
78
79 pcxhr_init_rmh(&rmh, CMD_VERSION);
80 /* firmware num for DSP */
81 rmh.cmd[0] |= mgr->firmware_num;
82 /* transfer granularity in samples (should be multiple of 48) */
83 rmh.cmd[1] = (1<<23) + PCXHR_GRANULARITY;
84 rmh.cmd_len = 2;
85 err = pcxhr_send_msg(mgr, &rmh);
86 if (err)
87 return err;
88 snd_printdd("PCXHR DSP version is %d.%d.%d\n",
89 (rmh.stat[0]>>16)&0xff, (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff);
90 mgr->dsp_version = rmh.stat[0];
91
92 /* get options */
93 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
94 rmh.cmd[0] |= IO_NUM_REG_STATUS;
95 rmh.cmd[1] = REG_STATUS_OPTIONS;
96 rmh.cmd_len = 2;
97 err = pcxhr_send_msg(mgr, &rmh);
98 if (err)
99 return err;
100
101 if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) == REG_STATUS_OPT_ANALOG_BOARD)
102 mgr->board_has_analog = 1; /* analog addon board available */
103 else
104 /* analog addon board not available -> no support for instance */
105 return -EINVAL;
106
107 /* unmute inputs */
108 err = pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS,
109 REG_CONT_UNMUTE_INPUTS, NULL);
110 if (err)
111 return err;
112 /* unmute outputs */
113 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* a write to IO_NUM_REG_MUTE_OUT mutes! */
114 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
115 err = pcxhr_send_msg(mgr, &rmh);
116 return err;
117}
118
119void pcxhr_reset_board(struct pcxhr_mgr *mgr)
120{
121 struct pcxhr_rmh rmh;
122
123 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
124 /* mute outputs */
125 /* a read to IO_NUM_REG_MUTE_OUT register unmutes! */
126 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
127 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
128 pcxhr_send_msg(mgr, &rmh);
129 /* mute inputs */
130 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS, 0, NULL);
131 }
132 /* reset pcxhr dsp */
133 if (mgr->dsp_loaded & ( 1 << PCXHR_FIRMWARE_DSP_EPRM_INDEX))
134 pcxhr_reset_dsp(mgr);
135 /* reset second xilinx */
136 if (mgr->dsp_loaded & ( 1 << PCXHR_FIRMWARE_XLX_COM_INDEX))
137 pcxhr_reset_xilinx_com(mgr);
138 return;
139}
140
141
142/*
143 * allocate a playback/capture pipe (pcmp0/pcmc0)
144 */
145static int pcxhr_dsp_allocate_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe,
146 int is_capture, int pin)
147{
148 int stream_count, audio_count;
149 int err;
150 struct pcxhr_rmh rmh;
151
152 if (is_capture) {
153 stream_count = 1;
154 if (mgr->mono_capture)
155 audio_count = 1;
156 else
157 audio_count = 2;
158 } else {
159 stream_count = PCXHR_PLAYBACK_STREAMS;
160 audio_count = 2; /* always stereo */
161 }
162 snd_printdd("snd_add_ref_pipe pin(%d) pcm%c0\n", pin, is_capture ? 'c' : 'p');
163 pipe->is_capture = is_capture;
164 pipe->first_audio = pin;
165 /* define pipe (P_PCM_ONLY_MASK (0x020000) is not necessary) */
166 pcxhr_init_rmh(&rmh, CMD_RES_PIPE);
167 pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin, audio_count, stream_count);
168 err = pcxhr_send_msg(mgr, &rmh);
169 if (err < 0) {
170 snd_printk(KERN_ERR "error pipe allocation (CMD_RES_PIPE) err=%x!\n", err );
171 return err;
172 }
173 pipe->status = PCXHR_PIPE_DEFINED;
174
175 return 0;
176}
177
178/*
179 * free playback/capture pipe (pcmp0/pcmc0)
180 */
181#if 0
182static int pcxhr_dsp_free_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe)
183{
184 struct pcxhr_rmh rmh;
185 int capture_mask = 0;
186 int playback_mask = 0;
187 int err = 0;
188
189 if (pipe->is_capture)
190 capture_mask = (1 << pipe->first_audio);
191 else
192 playback_mask = (1 << pipe->first_audio);
193
194 /* stop one pipe */
195 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
196 if (err < 0)
197 snd_printk(KERN_ERR "error stopping pipe!\n");
198 /* release the pipe */
199 pcxhr_init_rmh(&rmh, CMD_FREE_PIPE);
200 pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio, 0, 0);
201 err = pcxhr_send_msg(mgr, &rmh);
202 if (err < 0)
203 snd_printk(KERN_ERR "error pipe release (CMD_FREE_PIPE) err(%x)\n", err);
204 pipe->status = PCXHR_PIPE_UNDEFINED;
205 return err;
206}
207#endif
208
209
210static int pcxhr_config_pipes(struct pcxhr_mgr *mgr)
211{
212 int err, i, j;
213 struct snd_pcxhr *chip;
214 struct pcxhr_pipe *pipe;
215
216 /* allocate the pipes on the dsp */
217 for (i = 0; i < mgr->num_cards; i++) {
218 chip = mgr->chip[i];
219 if (chip->nb_streams_play) {
220 pipe = &chip->playback_pipe;
221 err = pcxhr_dsp_allocate_pipe( mgr, pipe, 0, i*2);
222 if (err)
223 return err;
224 for(j = 0; j < chip->nb_streams_play; j++)
225 chip->playback_stream[j].pipe = pipe;
226 }
227 for (j = 0; j < chip->nb_streams_capt; j++) {
228 pipe = &chip->capture_pipe[j];
229 err = pcxhr_dsp_allocate_pipe(mgr, pipe, 1, i*2 + j);
230 if (err)
231 return err;
232 chip->capture_stream[j].pipe = pipe;
233 }
234 }
235 return 0;
236}
237
238static int pcxhr_start_pipes(struct pcxhr_mgr *mgr)
239{
240 int i, j;
241 struct snd_pcxhr *chip;
242 int playback_mask = 0;
243 int capture_mask = 0;
244
245 /* start all the pipes on the dsp */
246 for (i = 0; i < mgr->num_cards; i++) {
247 chip = mgr->chip[i];
248 if (chip->nb_streams_play)
249 playback_mask |= (1 << chip->playback_pipe.first_audio);
250 for (j = 0; j < chip->nb_streams_capt; j++)
251 capture_mask |= (1 << chip->capture_pipe[j].first_audio);
252 }
253 return pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
254}
255
256
257static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index, const struct firmware *dsp)
258{
259 int err, card_index;
260
261 snd_printdd("loading dsp [%d] size = %Zd\n", index, dsp->size);
262
263 switch (index) {
264 case PCXHR_FIRMWARE_XLX_INT_INDEX:
265 pcxhr_reset_xilinx_com(mgr);
266 return pcxhr_load_xilinx_binary(mgr, dsp, 0);
267
268 case PCXHR_FIRMWARE_XLX_COM_INDEX:
269 pcxhr_reset_xilinx_com(mgr);
270 return pcxhr_load_xilinx_binary(mgr, dsp, 1);
271
272 case PCXHR_FIRMWARE_DSP_EPRM_INDEX:
273 pcxhr_reset_dsp(mgr);
274 return pcxhr_load_eeprom_binary(mgr, dsp);
275
276 case PCXHR_FIRMWARE_DSP_BOOT_INDEX:
277 return pcxhr_load_boot_binary(mgr, dsp);
278
279 case PCXHR_FIRMWARE_DSP_MAIN_INDEX:
280 err = pcxhr_load_dsp_binary(mgr, dsp);
281 if (err)
282 return err;
283 break; /* continue with first init */
284 default:
285 snd_printk(KERN_ERR "wrong file index\n");
286 return -EFAULT;
287 } /* end of switch file index*/
288
289 /* first communication with embedded */
290 err = pcxhr_init_board(mgr);
291 if (err < 0) {
292 snd_printk(KERN_ERR "pcxhr could not be set up\n");
293 return err;
294 }
295 err = pcxhr_config_pipes(mgr);
296 if (err < 0) {
297 snd_printk(KERN_ERR "pcxhr pipes could not be set up\n");
298 return err;
299 }
300 /* create devices and mixer in accordance with HW options*/
301 for (card_index = 0; card_index < mgr->num_cards; card_index++) {
302 struct snd_pcxhr *chip = mgr->chip[card_index];
303
304 if ((err = pcxhr_create_pcm(chip)) < 0)
305 return err;
306
307 if (card_index == 0) {
308 if ((err = pcxhr_create_mixer(chip->mgr)) < 0)
309 return err;
310 }
311 if ((err = snd_card_register(chip->card)) < 0)
312 return err;
313 }
314 err = pcxhr_start_pipes(mgr);
315 if (err < 0) {
316 snd_printk(KERN_ERR "pcxhr pipes could not be started\n");
317 return err;
318 }
319 snd_printdd("pcxhr firmware downloaded and successfully set up\n");
320
321 return 0;
322}
323
324/*
325 * fw loader entry
326 */
327#ifdef SND_PCXHR_FW_LOADER
328
329int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
330{
331 static char *fw_files[5] = {
332 "xi_1_882.dat",
333 "xc_1_882.dat",
334 "e321_512.e56",
335 "b321_512.b56",
336 "d321_512.d56"
337 };
338 char path[32];
339
340 const struct firmware *fw_entry;
341 int i, err;
342
343 for (i = 0; i < ARRAY_SIZE(fw_files); i++) {
344 sprintf(path, "pcxhr/%s", fw_files[i]);
345 if (request_firmware(&fw_entry, path, &mgr->pci->dev)) {
346 snd_printk(KERN_ERR "pcxhr: can't load firmware %s\n", path);
347 return -ENOENT;
348 }
349 /* fake hwdep dsp record */
350 err = pcxhr_dsp_load(mgr, i, fw_entry);
351 release_firmware(fw_entry);
352 if (err < 0)
353 return err;
354 mgr->dsp_loaded |= 1 << i;
355 }
356 return 0;
357}
358
359#else /* old style firmware loading */
360
361/* pcxhr hwdep interface id string */
362#define PCXHR_HWDEP_ID "pcxhr loader"
363
364
365static int pcxhr_hwdep_dsp_status(struct snd_hwdep *hw,
366 struct snd_hwdep_dsp_status *info)
367{
368 strcpy(info->id, "pcxhr");
369 info->num_dsps = PCXHR_FIRMWARE_FILES_MAX_INDEX;
370
371 if (hw->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))
372 info->chip_ready = 1;
373
374 info->version = PCXHR_DRIVER_VERSION;
375 return 0;
376}
377
378static int pcxhr_hwdep_dsp_load(struct snd_hwdep *hw,
379 struct snd_hwdep_dsp_image *dsp)
380{
381 struct pcxhr_mgr *mgr = hw->private_data;
382 int err;
383 struct firmware fw;
384
385 fw.size = dsp->length;
386 fw.data = vmalloc(fw.size);
387 if (! fw.data) {
388 snd_printk(KERN_ERR "pcxhr: cannot allocate dsp image (%d bytes)\n",
389 fw.size);
390 return -ENOMEM;
391 }
392 if (copy_from_user(fw.data, dsp->image, dsp->length)) {
393 vfree(fw.data);
394 return -EFAULT;
395 }
396 err = pcxhr_dsp_load(mgr, dsp->index, &fw);
397 vfree(fw.data);
398 if (err < 0)
399 return err;
400 mgr->dsp_loaded |= 1 << dsp->index;
401 return 0;
402}
403
404static int pcxhr_hwdep_open(struct snd_hwdep *hw, struct file *file)
405{
406 return 0;
407}
408
409static int pcxhr_hwdep_release(struct snd_hwdep *hw, struct file *file)
410{
411 return 0;
412}
413
414int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
415{
416 int err;
417 struct snd_hwdep *hw;
418
419 /* only create hwdep interface for first cardX (see "index" module parameter)*/
420 if ((err = snd_hwdep_new(mgr->chip[0]->card, PCXHR_HWDEP_ID, 0, &hw)) < 0)
421 return err;
422
423 hw->iface = SNDRV_HWDEP_IFACE_PCXHR;
424 hw->private_data = mgr;
425 hw->ops.open = pcxhr_hwdep_open;
426 hw->ops.release = pcxhr_hwdep_release;
427 hw->ops.dsp_status = pcxhr_hwdep_dsp_status;
428 hw->ops.dsp_load = pcxhr_hwdep_dsp_load;
429 hw->exclusive = 1;
430 mgr->dsp_loaded = 0;
431 sprintf(hw->name, PCXHR_HWDEP_ID);
432
433 if ((err = snd_card_register(mgr->chip[0]->card)) < 0)
434 return err;
435 return 0;
436}
437
438#endif /* SND_PCXHR_FW_LOADER */
diff --git a/sound/pci/pcxhr/pcxhr_hwdep.h b/sound/pci/pcxhr/pcxhr_hwdep.h
new file mode 100644
index 000000000000..f561909dc05f
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_hwdep.h
@@ -0,0 +1,40 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * definitions and makros for basic card access
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_PCXHR_HWDEP_H
24#define __SOUND_PCXHR_HWDEP_H
25
26
27/* firmware status codes */
28#define PCXHR_FIRMWARE_XLX_INT_INDEX 0
29#define PCXHR_FIRMWARE_XLX_COM_INDEX 1
30#define PCXHR_FIRMWARE_DSP_EPRM_INDEX 2
31#define PCXHR_FIRMWARE_DSP_BOOT_INDEX 3
32#define PCXHR_FIRMWARE_DSP_MAIN_INDEX 4
33#define PCXHR_FIRMWARE_FILES_MAX_INDEX 5
34
35
36/* exported */
37int pcxhr_setup_firmware(struct pcxhr_mgr *mgr);
38void pcxhr_reset_board(struct pcxhr_mgr *mgr);
39
40#endif /* __SOUND_PCXHR_HWDEP_H */
diff --git a/sound/pci/pcxhr/pcxhr_mixer.c b/sound/pci/pcxhr/pcxhr_mixer.c
new file mode 100644
index 000000000000..760e733ac25e
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_mixer.c
@@ -0,0 +1,1020 @@
1#define __NO_VERSION__
2/*
3 * Driver for Digigram pcxhr compatible soundcards
4 *
5 * mixer callbacks
6 *
7 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <sound/driver.h>
25#include <linux/time.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28#include <sound/core.h>
29#include "pcxhr.h"
30#include "pcxhr_hwdep.h"
31#include "pcxhr_core.h"
32#include <sound/control.h>
33#include <sound/asoundef.h>
34#include "pcxhr_mixer.h"
35
36
37#define PCXHR_ANALOG_CAPTURE_LEVEL_MIN 0 /* -96.0 dB */
38#define PCXHR_ANALOG_CAPTURE_LEVEL_MAX 255 /* +31.5 dB */
39#define PCXHR_ANALOG_CAPTURE_ZERO_LEVEL 224 /* +16.0 dB ( +31.5 dB - fix level +15.5 dB ) */
40
41#define PCXHR_ANALOG_PLAYBACK_LEVEL_MIN 0 /* -128.0 dB */
42#define PCXHR_ANALOG_PLAYBACK_LEVEL_MAX 128 /* 0.0 dB */
43#define PCXHR_ANALOG_PLAYBACK_ZERO_LEVEL 104 /* -24.0 dB ( 0.0 dB - fix level +24.0 dB ) */
44
45static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip, int is_capture, int channel)
46{
47 int err, vol;
48 struct pcxhr_rmh rmh;
49
50 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
51 if (is_capture) {
52 rmh.cmd[0] |= IO_NUM_REG_IN_ANA_LEVEL;
53 rmh.cmd[2] = chip->analog_capture_volume[channel];
54 } else {
55 rmh.cmd[0] |= IO_NUM_REG_OUT_ANA_LEVEL;
56 if (chip->analog_playback_active[channel])
57 vol = chip->analog_playback_volume[channel];
58 else
59 vol = PCXHR_ANALOG_PLAYBACK_LEVEL_MIN;
60 rmh.cmd[2] = PCXHR_ANALOG_PLAYBACK_LEVEL_MAX - vol; /* playback analog levels are inversed */
61 }
62 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */
63 rmh.cmd_len = 3;
64 err = pcxhr_send_msg(chip->mgr, &rmh);
65 if (err < 0) {
66 snd_printk(KERN_DEBUG "error update_analog_audio_level card(%d) "
67 "is_capture(%d) err(%x)\n", chip->chip_idx, is_capture, err);
68 return -EINVAL;
69 }
70 return 0;
71}
72
73/*
74 * analog level control
75 */
76static int pcxhr_analog_vol_info(struct snd_kcontrol *kcontrol,
77 struct snd_ctl_elem_info *uinfo)
78{
79 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
80 uinfo->count = 2;
81 if (kcontrol->private_value == 0) { /* playback */
82 uinfo->value.integer.min = PCXHR_ANALOG_PLAYBACK_LEVEL_MIN; /* -128 dB */
83 uinfo->value.integer.max = PCXHR_ANALOG_PLAYBACK_LEVEL_MAX; /* 0 dB */
84 } else { /* capture */
85 uinfo->value.integer.min = PCXHR_ANALOG_CAPTURE_LEVEL_MIN; /* -96 dB */
86 uinfo->value.integer.max = PCXHR_ANALOG_CAPTURE_LEVEL_MAX; /* 31.5 dB */
87 }
88 return 0;
89}
90
91static int pcxhr_analog_vol_get(struct snd_kcontrol *kcontrol,
92 struct snd_ctl_elem_value *ucontrol)
93{
94 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
95 down(&chip->mgr->mixer_mutex);
96 if (kcontrol->private_value == 0) { /* playback */
97 ucontrol->value.integer.value[0] = chip->analog_playback_volume[0];
98 ucontrol->value.integer.value[1] = chip->analog_playback_volume[1];
99 } else { /* capture */
100 ucontrol->value.integer.value[0] = chip->analog_capture_volume[0];
101 ucontrol->value.integer.value[1] = chip->analog_capture_volume[1];
102 }
103 up(&chip->mgr->mixer_mutex);
104 return 0;
105}
106
107static int pcxhr_analog_vol_put(struct snd_kcontrol *kcontrol,
108 struct snd_ctl_elem_value *ucontrol)
109{
110 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
111 int changed = 0;
112 int is_capture, i;
113
114 down(&chip->mgr->mixer_mutex);
115 is_capture = (kcontrol->private_value != 0);
116 for (i = 0; i < 2; i++) {
117 int new_volume = ucontrol->value.integer.value[i];
118 int* stored_volume = is_capture ? &chip->analog_capture_volume[i] :
119 &chip->analog_playback_volume[i];
120 if (*stored_volume != new_volume) {
121 *stored_volume = new_volume;
122 changed = 1;
123 pcxhr_update_analog_audio_level(chip, is_capture, i);
124 }
125 }
126 up(&chip->mgr->mixer_mutex);
127 return changed;
128}
129
130static struct snd_kcontrol_new pcxhr_control_analog_level = {
131 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
132 /* name will be filled later */
133 .info = pcxhr_analog_vol_info,
134 .get = pcxhr_analog_vol_get,
135 .put = pcxhr_analog_vol_put,
136};
137
138/* shared */
139static int pcxhr_sw_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
140{
141 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
142 uinfo->count = 2;
143 uinfo->value.integer.min = 0;
144 uinfo->value.integer.max = 1;
145 return 0;
146}
147
148static int pcxhr_audio_sw_get(struct snd_kcontrol *kcontrol,
149 struct snd_ctl_elem_value *ucontrol)
150{
151 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
152
153 down(&chip->mgr->mixer_mutex);
154 ucontrol->value.integer.value[0] = chip->analog_playback_active[0];
155 ucontrol->value.integer.value[1] = chip->analog_playback_active[1];
156 up(&chip->mgr->mixer_mutex);
157 return 0;
158}
159
160static int pcxhr_audio_sw_put(struct snd_kcontrol *kcontrol,
161 struct snd_ctl_elem_value *ucontrol)
162{
163 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
164 int i, changed = 0;
165 down(&chip->mgr->mixer_mutex);
166 for(i = 0; i < 2; i++) {
167 if (chip->analog_playback_active[i] != ucontrol->value.integer.value[i]) {
168 chip->analog_playback_active[i] = ucontrol->value.integer.value[i];
169 changed = 1;
170 pcxhr_update_analog_audio_level(chip, 0, i); /* update playback levels */
171 }
172 }
173 up(&chip->mgr->mixer_mutex);
174 return changed;
175}
176
177static struct snd_kcontrol_new pcxhr_control_output_switch = {
178 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
179 .name = "Master Playback Switch",
180 .info = pcxhr_sw_info, /* shared */
181 .get = pcxhr_audio_sw_get,
182 .put = pcxhr_audio_sw_put
183};
184
185
186#define PCXHR_DIGITAL_LEVEL_MIN 0x000 /* -110 dB */
187#define PCXHR_DIGITAL_LEVEL_MAX 0x1ff /* +18 dB */
188#define PCXHR_DIGITAL_ZERO_LEVEL 0x1b7 /* 0 dB */
189
190
191#define MORE_THAN_ONE_STREAM_LEVEL 0x000001
192#define VALID_STREAM_PAN_LEVEL_MASK 0x800000
193#define VALID_STREAM_LEVEL_MASK 0x400000
194#define VALID_STREAM_LEVEL_1_MASK 0x200000
195#define VALID_STREAM_LEVEL_2_MASK 0x100000
196
197static int pcxhr_update_playback_stream_level(struct snd_pcxhr* chip, int idx)
198{
199 int err;
200 struct pcxhr_rmh rmh;
201 struct pcxhr_pipe *pipe = &chip->playback_pipe;
202 int left, right;
203
204 if (chip->digital_playback_active[idx][0])
205 left = chip->digital_playback_volume[idx][0];
206 else
207 left = PCXHR_DIGITAL_LEVEL_MIN;
208 if (chip->digital_playback_active[idx][1])
209 right = chip->digital_playback_volume[idx][1];
210 else
211 right = PCXHR_DIGITAL_LEVEL_MIN;
212
213 pcxhr_init_rmh(&rmh, CMD_STREAM_OUT_LEVEL_ADJUST);
214 /* add pipe and stream mask */
215 pcxhr_set_pipe_cmd_params(&rmh, 0, pipe->first_audio, 0, 1<<idx);
216 /* volume left->left / right->right panoramic level */
217 rmh.cmd[0] |= MORE_THAN_ONE_STREAM_LEVEL;
218 rmh.cmd[2] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_1_MASK;
219 rmh.cmd[2] |= (left << 10);
220 rmh.cmd[3] = VALID_STREAM_PAN_LEVEL_MASK | VALID_STREAM_LEVEL_2_MASK;
221 rmh.cmd[3] |= right;
222 rmh.cmd_len = 4;
223
224 err = pcxhr_send_msg(chip->mgr, &rmh);
225 if (err < 0) {
226 snd_printk(KERN_DEBUG "error update_playback_stream_level "
227 "card(%d) err(%x)\n", chip->chip_idx, err);
228 return -EINVAL;
229 }
230 return 0;
231}
232
233#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
234#define AUDIO_IO_HAS_MUTE_MONITOR_1 0x200000
235#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x000001
236#define VALID_AUDIO_IO_MONITOR_LEVEL 0x000002
237#define VALID_AUDIO_IO_MUTE_LEVEL 0x000004
238#define VALID_AUDIO_IO_MUTE_MONITOR_1 0x000008
239
240static int pcxhr_update_audio_pipe_level(struct snd_pcxhr* chip, int capture, int channel)
241{
242 int err;
243 struct pcxhr_rmh rmh;
244 struct pcxhr_pipe *pipe;
245
246 if (capture)
247 pipe = &chip->capture_pipe[0];
248 else
249 pipe = &chip->playback_pipe;
250
251 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST);
252 /* add channel mask */
253 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0, 1 << (channel + pipe->first_audio));
254 /* TODO : if mask (3 << pipe->first_audio) is used, left and right channel
255 * will be programmed to the same params
256 */
257 if (capture) {
258 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL;
259 /* VALID_AUDIO_IO_MUTE_LEVEL not yet handled (capture pipe level) */
260 rmh.cmd[2] = chip->digital_capture_volume[channel];
261 } else {
262 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL | VALID_AUDIO_IO_MUTE_MONITOR_1;
263 /* VALID_AUDIO_IO_DIGITAL_LEVEL and VALID_AUDIO_IO_MUTE_LEVEL not yet
264 * handled (playback pipe level)
265 */
266 rmh.cmd[2] = chip->monitoring_volume[channel] << 10;
267 if (chip->monitoring_active[channel] == 0)
268 rmh.cmd[2] |= AUDIO_IO_HAS_MUTE_MONITOR_1;
269 }
270 rmh.cmd_len = 3;
271
272 err = pcxhr_send_msg(chip->mgr, &rmh);
273 if(err<0) {
274 snd_printk(KERN_DEBUG "error update_audio_level card(%d) err(%x)\n",
275 chip->chip_idx, err);
276 return -EINVAL;
277 }
278 return 0;
279}
280
281
282/* shared */
283static int pcxhr_digital_vol_info(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_info *uinfo)
285{
286 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
287 uinfo->count = 2;
288 uinfo->value.integer.min = PCXHR_DIGITAL_LEVEL_MIN; /* -109.5 dB */
289 uinfo->value.integer.max = PCXHR_DIGITAL_LEVEL_MAX; /* 18.0 dB */
290 return 0;
291}
292
293
294static int pcxhr_pcm_vol_get(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_value *ucontrol)
296{
297 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
298 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
299 int *stored_volume;
300 int is_capture = kcontrol->private_value;
301
302 down(&chip->mgr->mixer_mutex);
303 if (is_capture)
304 stored_volume = chip->digital_capture_volume; /* digital capture */
305 else
306 stored_volume = chip->digital_playback_volume[idx]; /* digital playback */
307 ucontrol->value.integer.value[0] = stored_volume[0];
308 ucontrol->value.integer.value[1] = stored_volume[1];
309 up(&chip->mgr->mixer_mutex);
310 return 0;
311}
312
313static int pcxhr_pcm_vol_put(struct snd_kcontrol *kcontrol,
314 struct snd_ctl_elem_value *ucontrol)
315{
316 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
317 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
318 int changed = 0;
319 int is_capture = kcontrol->private_value;
320 int *stored_volume;
321 int i;
322
323 down(&chip->mgr->mixer_mutex);
324 if (is_capture)
325 stored_volume = chip->digital_capture_volume; /* digital capture */
326 else
327 stored_volume = chip->digital_playback_volume[idx]; /* digital playback */
328 for (i = 0; i < 2; i++) {
329 if (stored_volume[i] != ucontrol->value.integer.value[i]) {
330 stored_volume[i] = ucontrol->value.integer.value[i];
331 changed = 1;
332 if (is_capture) /* update capture volume */
333 pcxhr_update_audio_pipe_level(chip, 1, i);
334 }
335 }
336 if (! is_capture && changed)
337 pcxhr_update_playback_stream_level(chip, idx); /* update playback volume */
338 up(&chip->mgr->mixer_mutex);
339 return changed;
340}
341
342static struct snd_kcontrol_new snd_pcxhr_pcm_vol =
343{
344 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
345 /* name will be filled later */
346 /* count will be filled later */
347 .info = pcxhr_digital_vol_info, /* shared */
348 .get = pcxhr_pcm_vol_get,
349 .put = pcxhr_pcm_vol_put,
350};
351
352
353static int pcxhr_pcm_sw_get(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355{
356 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
357 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
358
359 down(&chip->mgr->mixer_mutex);
360 ucontrol->value.integer.value[0] = chip->digital_playback_active[idx][0];
361 ucontrol->value.integer.value[1] = chip->digital_playback_active[idx][1];
362 up(&chip->mgr->mixer_mutex);
363 return 0;
364}
365
366static int pcxhr_pcm_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
367{
368 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
369 int changed = 0;
370 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
371 int i, j;
372
373 down(&chip->mgr->mixer_mutex);
374 j = idx;
375 for (i = 0; i < 2; i++) {
376 if (chip->digital_playback_active[j][i] != ucontrol->value.integer.value[i]) {
377 chip->digital_playback_active[j][i] = ucontrol->value.integer.value[i];
378 changed = 1;
379 }
380 }
381 if (changed)
382 pcxhr_update_playback_stream_level(chip, idx);
383 up(&chip->mgr->mixer_mutex);
384 return changed;
385}
386
387static struct snd_kcontrol_new pcxhr_control_pcm_switch = {
388 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
389 .name = "PCM Playback Switch",
390 .count = PCXHR_PLAYBACK_STREAMS,
391 .info = pcxhr_sw_info, /* shared */
392 .get = pcxhr_pcm_sw_get,
393 .put = pcxhr_pcm_sw_put
394};
395
396
397/*
398 * monitoring level control
399 */
400
401static int pcxhr_monitor_vol_get(struct snd_kcontrol *kcontrol,
402 struct snd_ctl_elem_value *ucontrol)
403{
404 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
405 down(&chip->mgr->mixer_mutex);
406 ucontrol->value.integer.value[0] = chip->monitoring_volume[0];
407 ucontrol->value.integer.value[1] = chip->monitoring_volume[1];
408 up(&chip->mgr->mixer_mutex);
409 return 0;
410}
411
412static int pcxhr_monitor_vol_put(struct snd_kcontrol *kcontrol,
413 struct snd_ctl_elem_value *ucontrol)
414{
415 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
416 int changed = 0;
417 int i;
418
419 down(&chip->mgr->mixer_mutex);
420 for (i = 0; i < 2; i++) {
421 if (chip->monitoring_volume[i] != ucontrol->value.integer.value[i]) {
422 chip->monitoring_volume[i] = ucontrol->value.integer.value[i];
423 if(chip->monitoring_active[i]) /* do only when monitoring is unmuted */
424 /* update monitoring volume and mute */
425 pcxhr_update_audio_pipe_level(chip, 0, i);
426 changed = 1;
427 }
428 }
429 up(&chip->mgr->mixer_mutex);
430 return changed;
431}
432
433static struct snd_kcontrol_new pcxhr_control_monitor_vol = {
434 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
435 .name = "Monitoring Volume",
436 .info = pcxhr_digital_vol_info, /* shared */
437 .get = pcxhr_monitor_vol_get,
438 .put = pcxhr_monitor_vol_put,
439};
440
441/*
442 * monitoring switch control
443 */
444
445static int pcxhr_monitor_sw_get(struct snd_kcontrol *kcontrol,
446 struct snd_ctl_elem_value *ucontrol)
447{
448 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
449 down(&chip->mgr->mixer_mutex);
450 ucontrol->value.integer.value[0] = chip->monitoring_active[0];
451 ucontrol->value.integer.value[1] = chip->monitoring_active[1];
452 up(&chip->mgr->mixer_mutex);
453 return 0;
454}
455
456static int pcxhr_monitor_sw_put(struct snd_kcontrol *kcontrol,
457 struct snd_ctl_elem_value *ucontrol)
458{
459 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
460 int changed = 0;
461 int i;
462
463 down(&chip->mgr->mixer_mutex);
464 for (i = 0; i < 2; i++) {
465 if (chip->monitoring_active[i] != ucontrol->value.integer.value[i]) {
466 chip->monitoring_active[i] = ucontrol->value.integer.value[i];
467 changed |= (1<<i); /* mask 0x01 and 0x02 */
468 }
469 }
470 if(changed & 0x01)
471 /* update left monitoring volume and mute */
472 pcxhr_update_audio_pipe_level(chip, 0, 0);
473 if(changed & 0x02)
474 /* update right monitoring volume and mute */
475 pcxhr_update_audio_pipe_level(chip, 0, 1);
476
477 up(&chip->mgr->mixer_mutex);
478 return (changed != 0);
479}
480
481static struct snd_kcontrol_new pcxhr_control_monitor_sw = {
482 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
483 .name = "Monitoring Switch",
484 .info = pcxhr_sw_info, /* shared */
485 .get = pcxhr_monitor_sw_get,
486 .put = pcxhr_monitor_sw_put
487};
488
489
490
491/*
492 * audio source select
493 */
494#define PCXHR_SOURCE_AUDIO01_UER 0x000100
495#define PCXHR_SOURCE_AUDIO01_SYNC 0x000200
496#define PCXHR_SOURCE_AUDIO23_UER 0x000400
497#define PCXHR_SOURCE_AUDIO45_UER 0x001000
498#define PCXHR_SOURCE_AUDIO67_UER 0x040000
499
500static int pcxhr_set_audio_source(struct snd_pcxhr* chip)
501{
502 struct pcxhr_rmh rmh;
503 unsigned int mask, reg;
504 unsigned int codec;
505 int err, use_src, changed;
506
507 switch (chip->chip_idx) {
508 case 0 : mask = PCXHR_SOURCE_AUDIO01_UER; codec = CS8420_01_CS; break;
509 case 1 : mask = PCXHR_SOURCE_AUDIO23_UER; codec = CS8420_23_CS; break;
510 case 2 : mask = PCXHR_SOURCE_AUDIO45_UER; codec = CS8420_45_CS; break;
511 case 3 : mask = PCXHR_SOURCE_AUDIO67_UER; codec = CS8420_67_CS; break;
512 default: return -EINVAL;
513 }
514 reg = 0; /* audio source from analog plug */
515 use_src = 0; /* do not activate codec SRC */
516
517 if (chip->audio_capture_source != 0) {
518 reg = mask; /* audio source from digital plug */
519 if (chip->audio_capture_source == 2)
520 use_src = 1;
521 }
522 /* set the input source */
523 pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed);
524 /* resync them (otherwise channel inversion possible) */
525 if (changed) {
526 pcxhr_init_rmh(&rmh, CMD_RESYNC_AUDIO_INPUTS);
527 rmh.cmd[0] |= (1 << chip->chip_idx);
528 err = pcxhr_send_msg(chip->mgr, &rmh);
529 if (err)
530 return err;
531 }
532 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set codec SRC on off */
533 rmh.cmd_len = 3;
534 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
535 rmh.cmd[1] = codec;
536 rmh.cmd[2] = (CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x54);
537 err = pcxhr_send_msg(chip->mgr, &rmh);
538 if(err)
539 return err;
540 rmh.cmd[2] = (CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x49);
541 err = pcxhr_send_msg(chip->mgr, &rmh);
542 return err;
543}
544
545static int pcxhr_audio_src_info(struct snd_kcontrol *kcontrol,
546 struct snd_ctl_elem_info *uinfo)
547{
548 static char *texts[3] = {"Analog", "Digital", "Digi+SRC"};
549
550 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
551 uinfo->count = 1;
552 uinfo->value.enumerated.items = 3;
553 if (uinfo->value.enumerated.item > 2)
554 uinfo->value.enumerated.item = 2;
555 strcpy(uinfo->value.enumerated.name,
556 texts[uinfo->value.enumerated.item]);
557 return 0;
558}
559
560static int pcxhr_audio_src_get(struct snd_kcontrol *kcontrol,
561 struct snd_ctl_elem_value *ucontrol)
562{
563 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
564 ucontrol->value.enumerated.item[0] = chip->audio_capture_source;
565 return 0;
566}
567
568static int pcxhr_audio_src_put(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
570{
571 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
572 int ret = 0;
573
574 down(&chip->mgr->mixer_mutex);
575 if (chip->audio_capture_source != ucontrol->value.enumerated.item[0]) {
576 chip->audio_capture_source = ucontrol->value.enumerated.item[0];
577 pcxhr_set_audio_source(chip);
578 ret = 1;
579 }
580 up(&chip->mgr->mixer_mutex);
581 return ret;
582}
583
584static struct snd_kcontrol_new pcxhr_control_audio_src = {
585 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
586 .name = "Capture Source",
587 .info = pcxhr_audio_src_info,
588 .get = pcxhr_audio_src_get,
589 .put = pcxhr_audio_src_put,
590};
591
592
593/*
594 * clock type selection
595 * enum pcxhr_clock_type {
596 * PCXHR_CLOCK_TYPE_INTERNAL = 0,
597 * PCXHR_CLOCK_TYPE_WORD_CLOCK,
598 * PCXHR_CLOCK_TYPE_AES_SYNC,
599 * PCXHR_CLOCK_TYPE_AES_1,
600 * PCXHR_CLOCK_TYPE_AES_2,
601 * PCXHR_CLOCK_TYPE_AES_3,
602 * PCXHR_CLOCK_TYPE_AES_4,
603 * };
604 */
605
606static int pcxhr_clock_type_info(struct snd_kcontrol *kcontrol,
607 struct snd_ctl_elem_info *uinfo)
608{
609 static char *texts[7] = {
610 "Internal", "WordClock", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
611 };
612 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
613 int clock_items = 3 + mgr->capture_chips;
614
615 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
616 uinfo->count = 1;
617 uinfo->value.enumerated.items = clock_items;
618 if (uinfo->value.enumerated.item >= clock_items)
619 uinfo->value.enumerated.item = clock_items-1;
620 strcpy(uinfo->value.enumerated.name,
621 texts[uinfo->value.enumerated.item]);
622 return 0;
623}
624
625static int pcxhr_clock_type_get(struct snd_kcontrol *kcontrol,
626 struct snd_ctl_elem_value *ucontrol)
627{
628 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
629 ucontrol->value.enumerated.item[0] = mgr->use_clock_type;
630 return 0;
631}
632
633static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol,
634 struct snd_ctl_elem_value *ucontrol)
635{
636 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
637 int rate, ret = 0;
638
639 down(&mgr->mixer_mutex);
640 if (mgr->use_clock_type != ucontrol->value.enumerated.item[0]) {
641 down(&mgr->setup_mutex);
642 mgr->use_clock_type = ucontrol->value.enumerated.item[0];
643 if (mgr->use_clock_type)
644 pcxhr_get_external_clock(mgr, mgr->use_clock_type, &rate);
645 else
646 rate = mgr->sample_rate;
647 if (rate) {
648 pcxhr_set_clock(mgr, rate);
649 if (mgr->sample_rate)
650 mgr->sample_rate = rate;
651 }
652 up(&mgr->setup_mutex);
653 ret = 1; /* return 1 even if the set was not done. ok ? */
654 }
655 up(&mgr->mixer_mutex);
656 return ret;
657}
658
659static struct snd_kcontrol_new pcxhr_control_clock_type = {
660 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
661 .name = "Clock Mode",
662 .info = pcxhr_clock_type_info,
663 .get = pcxhr_clock_type_get,
664 .put = pcxhr_clock_type_put,
665};
666
667/*
668 * clock rate control
669 * specific control that scans the sample rates on the external plugs
670 */
671static int pcxhr_clock_rate_info(struct snd_kcontrol *kcontrol,
672 struct snd_ctl_elem_info *uinfo)
673{
674 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
675 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
676 uinfo->count = 3 + mgr->capture_chips;
677 uinfo->value.integer.min = 0; /* clock not present */
678 uinfo->value.integer.max = 192000; /* max sample rate 192 kHz */
679 return 0;
680}
681
682static int pcxhr_clock_rate_get(struct snd_kcontrol *kcontrol,
683 struct snd_ctl_elem_value *ucontrol)
684{
685 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
686 int i, err, rate;
687
688 down(&mgr->mixer_mutex);
689 for(i = 0; i < 3 + mgr->capture_chips; i++) {
690 if (i == PCXHR_CLOCK_TYPE_INTERNAL)
691 rate = mgr->sample_rate_real;
692 else {
693 err = pcxhr_get_external_clock(mgr, i, &rate);
694 if (err)
695 break;
696 }
697 ucontrol->value.integer.value[i] = rate;
698 }
699 up(&mgr->mixer_mutex);
700 return 0;
701}
702
703static struct snd_kcontrol_new pcxhr_control_clock_rate = {
704 .access = SNDRV_CTL_ELEM_ACCESS_READ,
705 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
706 .name = "Clock Rates",
707 .info = pcxhr_clock_rate_info,
708 .get = pcxhr_clock_rate_get,
709};
710
711/*
712 * IEC958 status bits
713 */
714static int pcxhr_iec958_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
715{
716 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
717 uinfo->count = 1;
718 return 0;
719}
720
721static int pcxhr_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char* aes_bits)
722{
723 int i, err;
724 unsigned char temp;
725 struct pcxhr_rmh rmh;
726
727 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
728 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
729 switch (chip->chip_idx) {
730 case 0: rmh.cmd[1] = CS8420_01_CS; break; /* use CS8416_01_CS for AES SYNC plug */
731 case 1: rmh.cmd[1] = CS8420_23_CS; break;
732 case 2: rmh.cmd[1] = CS8420_45_CS; break;
733 case 3: rmh.cmd[1] = CS8420_67_CS; break;
734 default: return -EINVAL;
735 }
736 switch (aes_idx) {
737 case 0: rmh.cmd[2] = CS8420_CSB0; break; /* use CS8416_CSBx for AES SYNC plug */
738 case 1: rmh.cmd[2] = CS8420_CSB1; break;
739 case 2: rmh.cmd[2] = CS8420_CSB2; break;
740 case 3: rmh.cmd[2] = CS8420_CSB3; break;
741 case 4: rmh.cmd[2] = CS8420_CSB4; break;
742 default: return -EINVAL;
743 }
744 rmh.cmd[1] &= 0x0fffff; /* size and code the chip id for the fpga */
745 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI; /* chip signature + map for spi read */
746 rmh.cmd_len = 3;
747 err = pcxhr_send_msg(chip->mgr, &rmh);
748 if (err)
749 return err;
750 temp = 0;
751 for (i = 0; i < 8; i++) {
752 /* attention : reversed bit order (not with CS8416_01_CS) */
753 temp <<= 1;
754 if (rmh.stat[1] & (1 << i))
755 temp |= 1;
756 }
757 snd_printdd("read iec958 AES %d byte %d = 0x%x\n", chip->chip_idx, aes_idx, temp);
758 *aes_bits = temp;
759 return 0;
760}
761
762static int pcxhr_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
763{
764 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
765 unsigned char aes_bits;
766 int i, err;
767
768 down(&chip->mgr->mixer_mutex);
769 for(i = 0; i < 5; i++) {
770 if (kcontrol->private_value == 0) /* playback */
771 aes_bits = chip->aes_bits[i];
772 else { /* capture */
773 err = pcxhr_iec958_capture_byte(chip, i, &aes_bits);
774 if (err)
775 break;
776 }
777 ucontrol->value.iec958.status[i] = aes_bits;
778 }
779 up(&chip->mgr->mixer_mutex);
780 return 0;
781}
782
783static int pcxhr_iec958_mask_get(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785{
786 int i;
787 for (i = 0; i < 5; i++)
788 ucontrol->value.iec958.status[i] = 0xff;
789 return 0;
790}
791
792static int pcxhr_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char aes_bits)
793{
794 int i, err, cmd;
795 unsigned char new_bits = aes_bits;
796 unsigned char old_bits = chip->aes_bits[aes_idx];
797 struct pcxhr_rmh rmh;
798
799 for (i = 0; i < 8; i++) {
800 if ((old_bits & 0x01) != (new_bits & 0x01)) {
801 cmd = chip->chip_idx & 0x03; /* chip index 0..3 */
802 if(chip->chip_idx > 3)
803 /* new bit used if chip_idx>3 (PCX1222HR) */
804 cmd |= 1 << 22;
805 cmd |= ((aes_idx << 3) + i) << 2; /* add bit offset */
806 cmd |= (new_bits & 0x01) << 23; /* add bit value */
807 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
808 rmh.cmd[0] |= IO_NUM_REG_CUER;
809 rmh.cmd[1] = cmd;
810 rmh.cmd_len = 2;
811 snd_printdd("write iec958 AES %d byte %d bit %d (cmd %x)\n",
812 chip->chip_idx, aes_idx, i, cmd);
813 err = pcxhr_send_msg(chip->mgr, &rmh);
814 if (err)
815 return err;
816 }
817 old_bits >>= 1;
818 new_bits >>= 1;
819 }
820 chip->aes_bits[aes_idx] = aes_bits;
821 return 0;
822}
823
824static int pcxhr_iec958_put(struct snd_kcontrol *kcontrol,
825 struct snd_ctl_elem_value *ucontrol)
826{
827 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
828 int i, changed = 0;
829
830 /* playback */
831 down(&chip->mgr->mixer_mutex);
832 for (i = 0; i < 5; i++) {
833 if (ucontrol->value.iec958.status[i] != chip->aes_bits[i]) {
834 pcxhr_iec958_update_byte(chip, i, ucontrol->value.iec958.status[i]);
835 changed = 1;
836 }
837 }
838 up(&chip->mgr->mixer_mutex);
839 return changed;
840}
841
842static struct snd_kcontrol_new pcxhr_control_playback_iec958_mask = {
843 .access = SNDRV_CTL_ELEM_ACCESS_READ,
844 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
845 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
846 .info = pcxhr_iec958_info,
847 .get = pcxhr_iec958_mask_get
848};
849static struct snd_kcontrol_new pcxhr_control_playback_iec958 = {
850 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
851 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
852 .info = pcxhr_iec958_info,
853 .get = pcxhr_iec958_get,
854 .put = pcxhr_iec958_put,
855 .private_value = 0 /* playback */
856};
857
858static struct snd_kcontrol_new pcxhr_control_capture_iec958_mask = {
859 .access = SNDRV_CTL_ELEM_ACCESS_READ,
860 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
861 .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK),
862 .info = pcxhr_iec958_info,
863 .get = pcxhr_iec958_mask_get
864};
865static struct snd_kcontrol_new pcxhr_control_capture_iec958 = {
866 .access = SNDRV_CTL_ELEM_ACCESS_READ,
867 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
868 .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT),
869 .info = pcxhr_iec958_info,
870 .get = pcxhr_iec958_get,
871 .private_value = 1 /* capture */
872};
873
874static void pcxhr_init_audio_levels(struct snd_pcxhr *chip)
875{
876 int i;
877
878 for (i = 0; i < 2; i++) {
879 if (chip->nb_streams_play) {
880 int j;
881 /* at boot time the digital volumes are unmuted 0dB */
882 for (j = 0; j < PCXHR_PLAYBACK_STREAMS; j++) {
883 chip->digital_playback_active[j][i] = 1;
884 chip->digital_playback_volume[j][i] = PCXHR_DIGITAL_ZERO_LEVEL;
885 }
886 /* after boot, only two bits are set on the uer interface */
887 chip->aes_bits[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_FS_48000;
888/* only for test purpose, remove later */
889#ifdef CONFIG_SND_DEBUG
890 /* analog volumes for playback (is LEVEL_MIN after boot) */
891 chip->analog_playback_active[i] = 1;
892 chip->analog_playback_volume[i] = PCXHR_ANALOG_PLAYBACK_ZERO_LEVEL;
893 pcxhr_update_analog_audio_level(chip, 0, i);
894#endif
895/* test end */
896 }
897 if (chip->nb_streams_capt) {
898 /* at boot time the digital volumes are unmuted 0dB */
899 chip->digital_capture_volume[i] = PCXHR_DIGITAL_ZERO_LEVEL;
900/* only for test purpose, remove later */
901#ifdef CONFIG_SND_DEBUG
902 /* analog volumes for playback (is LEVEL_MIN after boot) */
903 chip->analog_capture_volume[i] = PCXHR_ANALOG_CAPTURE_ZERO_LEVEL;
904 pcxhr_update_analog_audio_level(chip, 1, i);
905#endif
906/* test end */
907 }
908 }
909
910 return;
911}
912
913
914int pcxhr_create_mixer(struct pcxhr_mgr *mgr)
915{
916 struct snd_pcxhr *chip;
917 int err, i;
918
919 init_MUTEX(&mgr->mixer_mutex); /* can be in another place */
920
921 for (i = 0; i < mgr->num_cards; i++) {
922 struct snd_kcontrol_new temp;
923 chip = mgr->chip[i];
924
925 if (chip->nb_streams_play) {
926 /* analog output level control */
927 temp = pcxhr_control_analog_level;
928 temp.name = "Master Playback Volume";
929 temp.private_value = 0; /* playback */
930 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0)
931 return err;
932 /* output mute controls */
933 if ((err = snd_ctl_add(chip->card,
934 snd_ctl_new1(&pcxhr_control_output_switch,
935 chip))) < 0)
936 return err;
937
938 temp = snd_pcxhr_pcm_vol;
939 temp.name = "PCM Playback Volume";
940 temp.count = PCXHR_PLAYBACK_STREAMS;
941 temp.private_value = 0; /* playback */
942 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0)
943 return err;
944
945 if ((err = snd_ctl_add(chip->card,
946 snd_ctl_new1(&pcxhr_control_pcm_switch,
947 chip))) < 0)
948 return err;
949
950 /* IEC958 controls */
951 if ((err = snd_ctl_add(chip->card,
952 snd_ctl_new1(&pcxhr_control_playback_iec958_mask,
953 chip))) < 0)
954 return err;
955 if ((err = snd_ctl_add(chip->card,
956 snd_ctl_new1(&pcxhr_control_playback_iec958,
957 chip))) < 0)
958 return err;
959 }
960 if (chip->nb_streams_capt) {
961 /* analog input level control only on first two chips !*/
962 temp = pcxhr_control_analog_level;
963 temp.name = "Master Capture Volume";
964 temp.private_value = 1; /* capture */
965 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0)
966 return err;
967
968 temp = snd_pcxhr_pcm_vol;
969 temp.name = "PCM Capture Volume";
970 temp.count = 1;
971 temp.private_value = 1; /* capture */
972 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0)
973 return err;
974 /* Audio source */
975 if ((err = snd_ctl_add(chip->card,
976 snd_ctl_new1(&pcxhr_control_audio_src,
977 chip))) < 0)
978 return err;
979 /* IEC958 controls */
980 if ((err = snd_ctl_add(chip->card,
981 snd_ctl_new1(&pcxhr_control_capture_iec958_mask,
982 chip))) < 0)
983 return err;
984 if ((err = snd_ctl_add(chip->card,
985 snd_ctl_new1(&pcxhr_control_capture_iec958,
986 chip))) < 0)
987 return err;
988 }
989 /* monitoring only if playback and capture device available */
990 if (chip->nb_streams_capt > 0 && chip->nb_streams_play > 0) {
991 /* monitoring */
992 if ((err = snd_ctl_add(chip->card,
993 snd_ctl_new1(&pcxhr_control_monitor_vol,
994 chip))) < 0)
995 return err;
996 if ((err = snd_ctl_add(chip->card,
997 snd_ctl_new1(&pcxhr_control_monitor_sw,
998 chip))) < 0)
999 return err;
1000 }
1001
1002 if (i == 0) {
1003 /* clock mode only one control per pcxhr */
1004 if ((err = snd_ctl_add(chip->card,
1005 snd_ctl_new1(&pcxhr_control_clock_type,
1006 mgr))) < 0)
1007 return err;
1008 /* non standard control used to scan the external clock presence/frequencies */
1009 if ((err = snd_ctl_add(chip->card,
1010 snd_ctl_new1(&pcxhr_control_clock_rate,
1011 mgr))) < 0)
1012 return err;
1013 }
1014
1015 /* init values for the mixer data */
1016 pcxhr_init_audio_levels(chip);
1017 }
1018
1019 return 0;
1020}
diff --git a/sound/pci/pcxhr/pcxhr_mixer.h b/sound/pci/pcxhr/pcxhr_mixer.h
new file mode 100644
index 000000000000..4348d0e55ba3
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_mixer.h
@@ -0,0 +1,29 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * include file for mixer
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_PCXHR_MIXER_H
24#define __SOUND_PCXHR_MIXER_H
25
26/* exported */
27int pcxhr_create_mixer(struct pcxhr_mgr *mgr);
28
29#endif /* __SOUND_PCXHR_MIXER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 19:02:24 -0500