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1/*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97#include <sound/driver.h>
98#include <asm/io.h>
99#include <linux/delay.h>
100#include <linux/interrupt.h>
101#include <linux/init.h>
102#include <linux/pci.h>
103#include <linux/slab.h>
104#include <linux/gameport.h>
105#include <linux/moduleparam.h>
106#include <sound/core.h>
107#include <sound/pcm.h>
108#include <sound/mpu401.h>
109#include <sound/ac97_codec.h>
110#include <sound/initval.h>
111
112#define CARD_NAME "ESS Maestro1/2"
113#define DRIVER_NAME "ES1968"
114
115MODULE_DESCRIPTION("ESS Maestro");
116MODULE_LICENSE("GPL");
117MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
118 "{ESS,Maestro 2},"
119 "{ESS,Maestro 1},"
120 "{TerraTec,DMX}}");
121
122#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
123#define SUPPORT_JOYSTICK 1
124#endif
125
126static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
127static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
128static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
129static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
130static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
131static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
132static int clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
133static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
134static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
135#ifdef SUPPORT_JOYSTICK
136static int joystick[SNDRV_CARDS];
137#endif
138
139module_param_array(index, int, NULL, 0444);
140MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
141module_param_array(id, charp, NULL, 0444);
142MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
143module_param_array(enable, bool, NULL, 0444);
144MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
145module_param_array(total_bufsize, int, NULL, 0444);
146MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
147module_param_array(pcm_substreams_p, int, NULL, 0444);
148MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
149module_param_array(pcm_substreams_c, int, NULL, 0444);
150MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
151module_param_array(clock, int, NULL, 0444);
152MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
153module_param_array(use_pm, int, NULL, 0444);
154MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
155module_param_array(enable_mpu, int, NULL, 0444);
156MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
157#ifdef SUPPORT_JOYSTICK
158module_param_array(joystick, bool, NULL, 0444);
159MODULE_PARM_DESC(joystick, "Enable joystick.");
160#endif
161
162
163/* PCI Dev ID's */
164
165#ifndef PCI_VENDOR_ID_ESS
166#define PCI_VENDOR_ID_ESS 0x125D
167#endif
168
169#define PCI_VENDOR_ID_ESS_OLD 0x1285 /* Platform Tech, the people the ESS
170 was bought form */
171
172#ifndef PCI_DEVICE_ID_ESS_M2E
173#define PCI_DEVICE_ID_ESS_M2E 0x1978
174#endif
175#ifndef PCI_DEVICE_ID_ESS_M2
176#define PCI_DEVICE_ID_ESS_M2 0x1968
177#endif
178#ifndef PCI_DEVICE_ID_ESS_M1
179#define PCI_DEVICE_ID_ESS_M1 0x0100
180#endif
181
182#define NR_APUS 64
183#define NR_APU_REGS 16
184
185/* NEC Versas ? */
186#define NEC_VERSA_SUBID1 0x80581033
187#define NEC_VERSA_SUBID2 0x803c1033
188
189/* Mode Flags */
190#define ESS_FMT_STEREO 0x01
191#define ESS_FMT_16BIT 0x02
192
193#define DAC_RUNNING 1
194#define ADC_RUNNING 2
195
196/* Values for the ESM_LEGACY_AUDIO_CONTROL */
197
198#define ESS_ENABLE_AUDIO 0x8000
199#define ESS_ENABLE_SERIAL_IRQ 0x4000
200#define IO_ADRESS_ALIAS 0x0020
201#define MPU401_IRQ_ENABLE 0x0010
202#define MPU401_IO_ENABLE 0x0008
203#define GAME_IO_ENABLE 0x0004
204#define FM_IO_ENABLE 0x0002
205#define SB_IO_ENABLE 0x0001
206
207/* Values for the ESM_CONFIG_A */
208
209#define PIC_SNOOP1 0x4000
210#define PIC_SNOOP2 0x2000
211#define SAFEGUARD 0x0800
212#define DMA_CLEAR 0x0700
213#define DMA_DDMA 0x0000
214#define DMA_TDMA 0x0100
215#define DMA_PCPCI 0x0200
216#define POST_WRITE 0x0080
217#define ISA_TIMING 0x0040
218#define SWAP_LR 0x0020
219#define SUBTR_DECODE 0x0002
220
221/* Values for the ESM_CONFIG_B */
222
223#define SPDIF_CONFB 0x0100
224#define HWV_CONFB 0x0080
225#define DEBOUNCE 0x0040
226#define GPIO_CONFB 0x0020
227#define CHI_CONFB 0x0010
228#define IDMA_CONFB 0x0008 /*undoc */
229#define MIDI_FIX 0x0004 /*undoc */
230#define IRQ_TO_ISA 0x0001 /*undoc */
231
232/* Values for Ring Bus Control B */
233#define RINGB_2CODEC_ID_MASK 0x0003
234#define RINGB_DIS_VALIDATION 0x0008
235#define RINGB_EN_SPDIF 0x0010
236#define RINGB_EN_2CODEC 0x0020
237#define RINGB_SING_BIT_DUAL 0x0040
238
239/* ****Port Adresses**** */
240
241/* Write & Read */
242#define ESM_INDEX 0x02
243#define ESM_DATA 0x00
244
245/* AC97 + RingBus */
246#define ESM_AC97_INDEX 0x30
247#define ESM_AC97_DATA 0x32
248#define ESM_RING_BUS_DEST 0x34
249#define ESM_RING_BUS_CONTR_A 0x36
250#define ESM_RING_BUS_CONTR_B 0x38
251#define ESM_RING_BUS_SDO 0x3A
252
253/* WaveCache*/
254#define WC_INDEX 0x10
255#define WC_DATA 0x12
256#define WC_CONTROL 0x14
257
258/* ASSP*/
259#define ASSP_INDEX 0x80
260#define ASSP_MEMORY 0x82
261#define ASSP_DATA 0x84
262#define ASSP_CONTROL_A 0xA2
263#define ASSP_CONTROL_B 0xA4
264#define ASSP_CONTROL_C 0xA6
265#define ASSP_HOSTW_INDEX 0xA8
266#define ASSP_HOSTW_DATA 0xAA
267#define ASSP_HOSTW_IRQ 0xAC
268/* Midi */
269#define ESM_MPU401_PORT 0x98
270/* Others */
271#define ESM_PORT_HOST_IRQ 0x18
272
273#define IDR0_DATA_PORT 0x00
274#define IDR1_CRAM_POINTER 0x01
275#define IDR2_CRAM_DATA 0x02
276#define IDR3_WAVE_DATA 0x03
277#define IDR4_WAVE_PTR_LOW 0x04
278#define IDR5_WAVE_PTR_HI 0x05
279#define IDR6_TIMER_CTRL 0x06
280#define IDR7_WAVE_ROMRAM 0x07
281
282#define WRITEABLE_MAP 0xEFFFFF
283#define READABLE_MAP 0x64003F
284
285/* PCI Register */
286
287#define ESM_LEGACY_AUDIO_CONTROL 0x40
288#define ESM_ACPI_COMMAND 0x54
289#define ESM_CONFIG_A 0x50
290#define ESM_CONFIG_B 0x52
291#define ESM_DDMA 0x60
292
293/* Bob Bits */
294#define ESM_BOB_ENABLE 0x0001
295#define ESM_BOB_START 0x0001
296
297/* Host IRQ Control Bits */
298#define ESM_RESET_MAESTRO 0x8000
299#define ESM_RESET_DIRECTSOUND 0x4000
300#define ESM_HIRQ_ClkRun 0x0100
301#define ESM_HIRQ_HW_VOLUME 0x0040
302#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
303#define ESM_HIRQ_ASSP 0x0010
304#define ESM_HIRQ_DSIE 0x0004
305#define ESM_HIRQ_MPU401 0x0002
306#define ESM_HIRQ_SB 0x0001
307
308/* Host IRQ Status Bits */
309#define ESM_MPU401_IRQ 0x02
310#define ESM_SB_IRQ 0x01
311#define ESM_SOUND_IRQ 0x04
312#define ESM_ASSP_IRQ 0x10
313#define ESM_HWVOL_IRQ 0x40
314
315#define ESS_SYSCLK 50000000
316#define ESM_BOB_FREQ 200
317#define ESM_BOB_FREQ_MAX 800
318
319#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
320#define ESM_FREQ_ESM2 (50000000L / 1024L)
321
322/* APU Modes: reg 0x00, bit 4-7 */
323#define ESM_APU_MODE_SHIFT 4
324#define ESM_APU_MODE_MASK (0xf << 4)
325#define ESM_APU_OFF 0x00
326#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
327#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
328#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
329#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
330#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
331#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
332#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
333#define ESM_APU_CORRELATOR 0x08 /* Correlator */
334#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
335#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
336#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
337#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
338#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
339#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
340#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
341
342/* reg 0x00 */
343#define ESM_APU_FILTER_Q_SHIFT 0
344#define ESM_APU_FILTER_Q_MASK (3 << 0)
345/* APU Filtey Q Control */
346#define ESM_APU_FILTER_LESSQ 0x00
347#define ESM_APU_FILTER_MOREQ 0x03
348
349#define ESM_APU_FILTER_TYPE_SHIFT 2
350#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
351#define ESM_APU_ENV_TYPE_SHIFT 8
352#define ESM_APU_ENV_TYPE_MASK (3 << 8)
353#define ESM_APU_ENV_STATE_SHIFT 10
354#define ESM_APU_ENV_STATE_MASK (3 << 10)
355#define ESM_APU_END_CURVE (1 << 12)
356#define ESM_APU_INT_ON_LOOP (1 << 13)
357#define ESM_APU_DMA_ENABLE (1 << 14)
358
359/* reg 0x02 */
360#define ESM_APU_SUBMIX_GROUP_SHIRT 0
361#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
362#define ESM_APU_SUBMIX_MODE (1 << 3)
363#define ESM_APU_6dB (1 << 4)
364#define ESM_APU_DUAL_EFFECT (1 << 5)
365#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
366#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
367
368/* reg 0x03 */
369#define ESM_APU_STEP_SIZE_MASK 0x0fff
370
371/* reg 0x04 */
372#define ESM_APU_PHASE_SHIFT 0
373#define ESM_APU_PHASE_MASK (0xff << 0)
374#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
375#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
376
377/* reg 0x05 - wave start offset */
378/* reg 0x06 - wave end offset */
379/* reg 0x07 - wave loop length */
380
381/* reg 0x08 */
382#define ESM_APU_EFFECT_GAIN_SHIFT 0
383#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
384#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
385#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
386#define ESM_APU_TREMOLO_RATE_SHIFT 12
387#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
388
389/* reg 0x09 */
390/* bit 0-7 amplitude dest? */
391#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
392#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
393
394/* reg 0x0a */
395#define ESM_APU_POLAR_PAN_SHIFT 0
396#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
397/* Polar Pan Control */
398#define ESM_APU_PAN_CENTER_CIRCLE 0x00
399#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
400#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
401
402#define ESM_APU_FILTER_TUNING_SHIFT 8
403#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
404
405/* reg 0x0b */
406#define ESM_APU_DATA_SRC_A_SHIFT 0
407#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
408#define ESM_APU_INV_POL_A (1 << 7)
409#define ESM_APU_DATA_SRC_B_SHIFT 8
410#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
411#define ESM_APU_INV_POL_B (1 << 15)
412
413#define ESM_APU_VIBRATO_RATE_SHIFT 0
414#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
415#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
416#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
417#define ESM_APU_VIBRATO_PHASE_SHIFT 8
418#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
419
420/* reg 0x0c */
421#define ESM_APU_RADIUS_SELECT (1 << 6)
422
423/* APU Filter Control */
424#define ESM_APU_FILTER_2POLE_LOPASS 0x00
425#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
426#define ESM_APU_FILTER_2POLE_HIPASS 0x02
427#define ESM_APU_FILTER_1POLE_LOPASS 0x03
428#define ESM_APU_FILTER_1POLE_HIPASS 0x04
429#define ESM_APU_FILTER_OFF 0x05
430
431/* APU ATFP Type */
432#define ESM_APU_ATFP_AMPLITUDE 0x00
433#define ESM_APU_ATFP_TREMELO 0x01
434#define ESM_APU_ATFP_FILTER 0x02
435#define ESM_APU_ATFP_PAN 0x03
436
437/* APU ATFP Flags */
438#define ESM_APU_ATFP_FLG_OFF 0x00
439#define ESM_APU_ATFP_FLG_WAIT 0x01
440#define ESM_APU_ATFP_FLG_DONE 0x02
441#define ESM_APU_ATFP_FLG_INPROCESS 0x03
442
443
444/* capture mixing buffer size */
445#define ESM_MEM_ALIGN 0x1000
446#define ESM_MIXBUF_SIZE 0x400
447
448#define ESM_MODE_PLAY 0
449#define ESM_MODE_CAPTURE 1
450
451/* acpi states */
452enum {
453 ACPI_D0=0,
454 ACPI_D1,
455 ACPI_D2,
456 ACPI_D3
457};
458
459/* bits in the acpi masks */
460#define ACPI_12MHZ ( 1 << 15)
461#define ACPI_24MHZ ( 1 << 14)
462#define ACPI_978 ( 1 << 13)
463#define ACPI_SPDIF ( 1 << 12)
464#define ACPI_GLUE ( 1 << 11)
465#define ACPI__10 ( 1 << 10) /* reserved */
466#define ACPI_PCIINT ( 1 << 9)
467#define ACPI_HV ( 1 << 8) /* hardware volume */
468#define ACPI_GPIO ( 1 << 7)
469#define ACPI_ASSP ( 1 << 6)
470#define ACPI_SB ( 1 << 5) /* sb emul */
471#define ACPI_FM ( 1 << 4) /* fm emul */
472#define ACPI_RB ( 1 << 3) /* ringbus / aclink */
473#define ACPI_MIDI ( 1 << 2)
474#define ACPI_GP ( 1 << 1) /* game port */
475#define ACPI_WP ( 1 << 0) /* wave processor */
476
477#define ACPI_ALL (0xffff)
478#define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \
479 ACPI_MIDI|ACPI_GP|ACPI_WP))
480#define ACPI_NONE (ACPI__10)
481
482/* these masks indicate which units we care about at
483 which states */
484static u16 acpi_state_mask[] = {
485 [ACPI_D0] = ACPI_ALL,
486 [ACPI_D1] = ACPI_SLEEP,
487 [ACPI_D2] = ACPI_SLEEP,
488 [ACPI_D3] = ACPI_NONE
489};
490
491
492typedef struct snd_es1968 es1968_t;
493typedef struct snd_esschan esschan_t;
494typedef struct snd_esm_memory esm_memory_t;
495
496/* APU use in the driver */
497enum snd_enum_apu_type {
498 ESM_APU_PCM_PLAY,
499 ESM_APU_PCM_CAPTURE,
500 ESM_APU_PCM_RATECONV,
501 ESM_APU_FREE
502};
503
504/* chip type */
505enum {
506 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
507};
508
509/* DMA Hack! */
510struct snd_esm_memory {
511 struct snd_dma_buffer buf;
512 int empty; /* status */
513 struct list_head list;
514};
515
516/* Playback Channel */
517struct snd_esschan {
518 int running;
519
520 u8 apu[4];
521 u8 apu_mode[4];
522
523 /* playback/capture pcm buffer */
524 esm_memory_t *memory;
525 /* capture mixer buffer */
526 esm_memory_t *mixbuf;
527
528 unsigned int hwptr; /* current hw pointer in bytes */
529 unsigned int count; /* sample counter in bytes */
530 unsigned int dma_size; /* total buffer size in bytes */
531 unsigned int frag_size; /* period size in bytes */
532 unsigned int wav_shift;
533 u16 base[4]; /* offset for ptr */
534
535 /* stereo/16bit flag */
536 unsigned char fmt;
537 int mode; /* playback / capture */
538
539 int bob_freq; /* required timer frequency */
540
541 snd_pcm_substream_t *substream;
542
543 /* linked list */
544 struct list_head list;
545
546#ifdef CONFIG_PM
547 u16 wc_map[4];
548#endif
549};
550
551struct snd_es1968 {
552 /* Module Config */
553 int total_bufsize; /* in bytes */
554
555 int playback_streams, capture_streams;
556
557 unsigned int clock; /* clock */
558 /* for clock measurement */
559 unsigned int in_measurement: 1;
560 unsigned int measure_apu;
561 unsigned int measure_lastpos;
562 unsigned int measure_count;
563
564 /* buffer */
565 struct snd_dma_buffer dma;
566
567 /* Resources... */
568 int irq;
569 unsigned long io_port;
570 int type;
571 struct pci_dev *pci;
572 snd_card_t *card;
573 snd_pcm_t *pcm;
574 int do_pm; /* power-management enabled */
575
576 /* DMA memory block */
577 struct list_head buf_list;
578
579 /* ALSA Stuff */
580 ac97_t *ac97;
581 snd_kcontrol_t *master_switch; /* for h/w volume control */
582 snd_kcontrol_t *master_volume;
583
584 snd_rawmidi_t *rmidi;
585
586 spinlock_t reg_lock;
587 spinlock_t ac97_lock;
588 struct tasklet_struct hwvol_tq;
589 unsigned int in_suspend;
590
591 /* Maestro Stuff */
592 u16 maestro_map[32];
593 int bobclient; /* active timer instancs */
594 int bob_freq; /* timer frequency */
595 struct semaphore memory_mutex; /* memory lock */
596
597 /* APU states */
598 unsigned char apu[NR_APUS];
599
600 /* active substreams */
601 struct list_head substream_list;
602 spinlock_t substream_lock;
603
604#ifdef CONFIG_PM
605 u16 apu_map[NR_APUS][NR_APU_REGS];
606#endif
607
608#ifdef SUPPORT_JOYSTICK
609 struct gameport *gameport;
610#endif
611};
612
613static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs);
614
615static struct pci_device_id snd_es1968_ids[] = {
616 /* Maestro 1 */
617 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
618 /* Maestro 2 */
619 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
620 /* Maestro 2E */
621 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
622 { 0, }
623};
624
625MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
626
627/* *********************
628 * Low Level Funcs! *
629 *********************/
630
631/* no spinlock */
632static void __maestro_write(es1968_t *chip, u16 reg, u16 data)
633{
634 outw(reg, chip->io_port + ESM_INDEX);
635 outw(data, chip->io_port + ESM_DATA);
636 chip->maestro_map[reg] = data;
637}
638
639inline static void maestro_write(es1968_t *chip, u16 reg, u16 data)
640{
641 unsigned long flags;
642 spin_lock_irqsave(&chip->reg_lock, flags);
643 __maestro_write(chip, reg, data);
644 spin_unlock_irqrestore(&chip->reg_lock, flags);
645}
646
647/* no spinlock */
648static u16 __maestro_read(es1968_t *chip, u16 reg)
649{
650 if (READABLE_MAP & (1 << reg)) {
651 outw(reg, chip->io_port + ESM_INDEX);
652 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
653 }
654 return chip->maestro_map[reg];
655}
656
657inline static u16 maestro_read(es1968_t *chip, u16 reg)
658{
659 unsigned long flags;
660 u16 result;
661 spin_lock_irqsave(&chip->reg_lock, flags);
662 result = __maestro_read(chip, reg);
663 spin_unlock_irqrestore(&chip->reg_lock, flags);
664 return result;
665}
666
667#define big_mdelay(msec) do {\
668 set_current_state(TASK_UNINTERRUPTIBLE);\
669 schedule_timeout(((msec) * HZ + 999) / 1000);\
670} while (0)
671
672/* Wait for the codec bus to be free */
673static int snd_es1968_ac97_wait(es1968_t *chip)
674{
675 int timeout = 100000;
676
677 while (timeout-- > 0) {
678 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
679 return 0;
680 cond_resched();
681 }
682 snd_printd("es1968: ac97 timeout\n");
683 return 1; /* timeout */
684}
685
686static void snd_es1968_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
687{
688 es1968_t *chip = ac97->private_data;
689 unsigned long flags;
690
691 snd_es1968_ac97_wait(chip);
692
693 /* Write the bus */
694 spin_lock_irqsave(&chip->ac97_lock, flags);
695 outw(val, chip->io_port + ESM_AC97_DATA);
696 /*msleep(1);*/
697 outb(reg, chip->io_port + ESM_AC97_INDEX);
698 /*msleep(1);*/
699 spin_unlock_irqrestore(&chip->ac97_lock, flags);
700}
701
702static unsigned short snd_es1968_ac97_read(ac97_t *ac97, unsigned short reg)
703{
704 u16 data = 0;
705 es1968_t *chip = ac97->private_data;
706 unsigned long flags;
707
708 snd_es1968_ac97_wait(chip);
709
710 spin_lock_irqsave(&chip->ac97_lock, flags);
711 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
712 /*msleep(1);*/
713
714 if (! snd_es1968_ac97_wait(chip)) {
715 data = inw(chip->io_port + ESM_AC97_DATA);
716 /*msleep(1);*/
717 }
718 spin_unlock_irqrestore(&chip->ac97_lock, flags);
719
720 return data;
721}
722
723/* no spinlock */
724static void apu_index_set(es1968_t *chip, u16 index)
725{
726 int i;
727 __maestro_write(chip, IDR1_CRAM_POINTER, index);
728 for (i = 0; i < 1000; i++)
729 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
730 return;
731 snd_printd("es1968: APU register select failed. (Timeout)\n");
732}
733
734/* no spinlock */
735static void apu_data_set(es1968_t *chip, u16 data)
736{
737 int i;
738 for (i = 0; i < 1000; i++) {
739 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
740 return;
741 __maestro_write(chip, IDR0_DATA_PORT, data);
742 }
743 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
744}
745
746/* no spinlock */
747static void __apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
748{
749 snd_assert(channel < NR_APUS, return);
750#ifdef CONFIG_PM
751 chip->apu_map[channel][reg] = data;
752#endif
753 reg |= (channel << 4);
754 apu_index_set(chip, reg);
755 apu_data_set(chip, data);
756}
757
758inline static void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
759{
760 unsigned long flags;
761 spin_lock_irqsave(&chip->reg_lock, flags);
762 __apu_set_register(chip, channel, reg, data);
763 spin_unlock_irqrestore(&chip->reg_lock, flags);
764}
765
766static u16 __apu_get_register(es1968_t *chip, u16 channel, u8 reg)
767{
768 snd_assert(channel < NR_APUS, return 0);
769 reg |= (channel << 4);
770 apu_index_set(chip, reg);
771 return __maestro_read(chip, IDR0_DATA_PORT);
772}
773
774inline static u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg)
775{
776 unsigned long flags;
777 u16 v;
778 spin_lock_irqsave(&chip->reg_lock, flags);
779 v = __apu_get_register(chip, channel, reg);
780 spin_unlock_irqrestore(&chip->reg_lock, flags);
781 return v;
782}
783
784#if 0 /* ASSP is not supported */
785
786static void assp_set_register(es1968_t *chip, u32 reg, u32 value)
787{
788 unsigned long flags;
789
790 spin_lock_irqsave(&chip->reg_lock, flags);
791 outl(reg, chip->io_port + ASSP_INDEX);
792 outl(value, chip->io_port + ASSP_DATA);
793 spin_unlock_irqrestore(&chip->reg_lock, flags);
794}
795
796static u32 assp_get_register(es1968_t *chip, u32 reg)
797{
798 unsigned long flags;
799 u32 value;
800
801 spin_lock_irqsave(&chip->reg_lock, flags);
802 outl(reg, chip->io_port + ASSP_INDEX);
803 value = inl(chip->io_port + ASSP_DATA);
804 spin_unlock_irqrestore(&chip->reg_lock, flags);
805
806 return value;
807}
808
809#endif
810
811static void wave_set_register(es1968_t *chip, u16 reg, u16 value)
812{
813 unsigned long flags;
814
815 spin_lock_irqsave(&chip->reg_lock, flags);
816 outw(reg, chip->io_port + WC_INDEX);
817 outw(value, chip->io_port + WC_DATA);
818 spin_unlock_irqrestore(&chip->reg_lock, flags);
819}
820
821static u16 wave_get_register(es1968_t *chip, u16 reg)
822{
823 unsigned long flags;
824 u16 value;
825
826 spin_lock_irqsave(&chip->reg_lock, flags);
827 outw(reg, chip->io_port + WC_INDEX);
828 value = inw(chip->io_port + WC_DATA);
829 spin_unlock_irqrestore(&chip->reg_lock, flags);
830
831 return value;
832}
833
834/* *******************
835 * Bob the Timer! *
836 *******************/
837
838static void snd_es1968_bob_stop(es1968_t *chip)
839{
840 u16 reg;
841
842 reg = __maestro_read(chip, 0x11);
843 reg &= ~ESM_BOB_ENABLE;
844 __maestro_write(chip, 0x11, reg);
845 reg = __maestro_read(chip, 0x17);
846 reg &= ~ESM_BOB_START;
847 __maestro_write(chip, 0x17, reg);
848}
849
850static void snd_es1968_bob_start(es1968_t *chip)
851{
852 int prescale;
853 int divide;
854
855 /* compute ideal interrupt frequency for buffer size & play rate */
856 /* first, find best prescaler value to match freq */
857 for (prescale = 5; prescale < 12; prescale++)
858 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
859 break;
860
861 /* next, back off prescaler whilst getting divider into optimum range */
862 divide = 1;
863 while ((prescale > 5) && (divide < 32)) {
864 prescale--;
865 divide <<= 1;
866 }
867 divide >>= 1;
868
869 /* now fine-tune the divider for best match */
870 for (; divide < 31; divide++)
871 if (chip->bob_freq >
872 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
873
874 /* divide = 0 is illegal, but don't let prescale = 4! */
875 if (divide == 0) {
876 divide++;
877 if (prescale > 5)
878 prescale--;
879 } else if (divide > 1)
880 divide--;
881
882 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
883
884 /* Now set IDR 11/17 */
885 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
886 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
887}
888
889/* call with substream spinlock */
890static void snd_es1968_bob_inc(es1968_t *chip, int freq)
891{
892 chip->bobclient++;
893 if (chip->bobclient == 1) {
894 chip->bob_freq = freq;
895 snd_es1968_bob_start(chip);
896 } else if (chip->bob_freq < freq) {
897 snd_es1968_bob_stop(chip);
898 chip->bob_freq = freq;
899 snd_es1968_bob_start(chip);
900 }
901}
902
903/* call with substream spinlock */
904static void snd_es1968_bob_dec(es1968_t *chip)
905{
906 chip->bobclient--;
907 if (chip->bobclient <= 0)
908 snd_es1968_bob_stop(chip);
909 else if (chip->bob_freq > ESM_BOB_FREQ) {
910 /* check reduction of timer frequency */
911 struct list_head *p;
912 int max_freq = ESM_BOB_FREQ;
913 list_for_each(p, &chip->substream_list) {
914 esschan_t *es = list_entry(p, esschan_t, list);
915 if (max_freq < es->bob_freq)
916 max_freq = es->bob_freq;
917 }
918 if (max_freq != chip->bob_freq) {
919 snd_es1968_bob_stop(chip);
920 chip->bob_freq = max_freq;
921 snd_es1968_bob_start(chip);
922 }
923 }
924}
925
926static int
927snd_es1968_calc_bob_rate(es1968_t *chip, esschan_t *es,
928 snd_pcm_runtime_t *runtime)
929{
930 /* we acquire 4 interrupts per period for precise control.. */
931 int freq = runtime->rate * 4;
932 if (es->fmt & ESS_FMT_STEREO)
933 freq <<= 1;
934 if (es->fmt & ESS_FMT_16BIT)
935 freq <<= 1;
936 freq /= es->frag_size;
937 if (freq < ESM_BOB_FREQ)
938 freq = ESM_BOB_FREQ;
939 else if (freq > ESM_BOB_FREQ_MAX)
940 freq = ESM_BOB_FREQ_MAX;
941 return freq;
942}
943
944
945/*************
946 * PCM Part *
947 *************/
948
949static u32 snd_es1968_compute_rate(es1968_t *chip, u32 freq)
950{
951 u32 rate = (freq << 16) / chip->clock;
952#if 0 /* XXX: do we need this? */
953 if (rate > 0x10000)
954 rate = 0x10000;
955#endif
956 return rate;
957}
958
959/* get current pointer */
960inline static unsigned int
961snd_es1968_get_dma_ptr(es1968_t *chip, esschan_t *es)
962{
963 unsigned int offset;
964
965 offset = apu_get_register(chip, es->apu[0], 5);
966
967 offset -= es->base[0];
968
969 return (offset & 0xFFFE); /* hardware is in words */
970}
971
972static void snd_es1968_apu_set_freq(es1968_t *chip, int apu, int freq)
973{
974 apu_set_register(chip, apu, 2,
975 (apu_get_register(chip, apu, 2) & 0x00FF) |
976 ((freq & 0xff) << 8) | 0x10);
977 apu_set_register(chip, apu, 3, freq >> 8);
978}
979
980/* spin lock held */
981inline static void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode)
982{
983 /* set the APU mode */
984 __apu_set_register(esm, apu, 0,
985 (__apu_get_register(esm, apu, 0) & 0xff0f) |
986 (mode << 4));
987}
988
989static void snd_es1968_pcm_start(es1968_t *chip, esschan_t *es)
990{
991 spin_lock(&chip->reg_lock);
992 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
993 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
994 if (es->mode == ESM_MODE_CAPTURE) {
995 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
996 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
997 }
998 if (es->fmt & ESS_FMT_STEREO) {
999 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
1000 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
1001 if (es->mode == ESM_MODE_CAPTURE) {
1002 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
1003 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
1004 }
1005 }
1006 spin_unlock(&chip->reg_lock);
1007}
1008
1009static void snd_es1968_pcm_stop(es1968_t *chip, esschan_t *es)
1010{
1011 spin_lock(&chip->reg_lock);
1012 snd_es1968_trigger_apu(chip, es->apu[0], 0);
1013 snd_es1968_trigger_apu(chip, es->apu[1], 0);
1014 if (es->mode == ESM_MODE_CAPTURE) {
1015 snd_es1968_trigger_apu(chip, es->apu[2], 0);
1016 snd_es1968_trigger_apu(chip, es->apu[3], 0);
1017 }
1018 spin_unlock(&chip->reg_lock);
1019}
1020
1021/* set the wavecache control reg */
1022static void snd_es1968_program_wavecache(es1968_t *chip, esschan_t *es,
1023 int channel, u32 addr, int capture)
1024{
1025 u32 tmpval = (addr - 0x10) & 0xFFF8;
1026
1027 if (! capture) {
1028 if (!(es->fmt & ESS_FMT_16BIT))
1029 tmpval |= 4; /* 8bit */
1030 if (es->fmt & ESS_FMT_STEREO)
1031 tmpval |= 2; /* stereo */
1032 }
1033
1034 /* set the wavecache control reg */
1035 wave_set_register(chip, es->apu[channel] << 3, tmpval);
1036
1037#ifdef CONFIG_PM
1038 es->wc_map[channel] = tmpval;
1039#endif
1040}
1041
1042
1043static void snd_es1968_playback_setup(es1968_t *chip, esschan_t *es,
1044 snd_pcm_runtime_t *runtime)
1045{
1046 u32 pa;
1047 int high_apu = 0;
1048 int channel, apu;
1049 int i, size;
1050 unsigned long flags;
1051 u32 freq;
1052
1053 size = es->dma_size >> es->wav_shift;
1054
1055 if (es->fmt & ESS_FMT_STEREO)
1056 high_apu++;
1057
1058 for (channel = 0; channel <= high_apu; channel++) {
1059 apu = es->apu[channel];
1060
1061 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1062
1063 /* Offset to PCMBAR */
1064 pa = es->memory->buf.addr;
1065 pa -= chip->dma.addr;
1066 pa >>= 1; /* words */
1067
1068 pa |= 0x00400000; /* System RAM (Bit 22) */
1069
1070 if (es->fmt & ESS_FMT_STEREO) {
1071 /* Enable stereo */
1072 if (channel)
1073 pa |= 0x00800000; /* (Bit 23) */
1074 if (es->fmt & ESS_FMT_16BIT)
1075 pa >>= 1;
1076 }
1077
1078 /* base offset of dma calcs when reading the pointer
1079 on this left one */
1080 es->base[channel] = pa & 0xFFFF;
1081
1082 for (i = 0; i < 16; i++)
1083 apu_set_register(chip, apu, i, 0x0000);
1084
1085 /* Load the buffer into the wave engine */
1086 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1087 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1088 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1089 /* setting loop == sample len */
1090 apu_set_register(chip, apu, 7, size);
1091
1092 /* clear effects/env.. */
1093 apu_set_register(chip, apu, 8, 0x0000);
1094 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1095 apu_set_register(chip, apu, 9, 0xD000);
1096
1097 /* clear routing stuff */
1098 apu_set_register(chip, apu, 11, 0x0000);
1099 /* dma on, no envelopes, filter to all 1s) */
1100 apu_set_register(chip, apu, 0, 0x400F);
1101
1102 if (es->fmt & ESS_FMT_16BIT)
1103 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1104 else
1105 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1106
1107 if (es->fmt & ESS_FMT_STEREO) {
1108 /* set panning: left or right */
1109 /* Check: different panning. On my Canyon 3D Chipset the
1110 Channels are swapped. I don't know, about the output
1111 to the SPDif Link. Perhaps you have to change this
1112 and not the APU Regs 4-5. */
1113 apu_set_register(chip, apu, 10,
1114 0x8F00 | (channel ? 0 : 0x10));
1115 es->apu_mode[channel] += 1; /* stereo */
1116 } else
1117 apu_set_register(chip, apu, 10, 0x8F08);
1118 }
1119
1120 spin_lock_irqsave(&chip->reg_lock, flags);
1121 /* clear WP interrupts */
1122 outw(1, chip->io_port + 0x04);
1123 /* enable WP ints */
1124 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1125 spin_unlock_irqrestore(&chip->reg_lock, flags);
1126
1127 freq = runtime->rate;
1128 /* set frequency */
1129 if (freq > 48000)
1130 freq = 48000;
1131 if (freq < 4000)
1132 freq = 4000;
1133
1134 /* hmmm.. */
1135 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1136 freq >>= 1;
1137
1138 freq = snd_es1968_compute_rate(chip, freq);
1139
1140 /* Load the frequency, turn on 6dB */
1141 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1142 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1143}
1144
1145
1146static void init_capture_apu(es1968_t *chip, esschan_t *es, int channel,
1147 unsigned int pa, unsigned int bsize,
1148 int mode, int route)
1149{
1150 int i, apu = es->apu[channel];
1151
1152 es->apu_mode[channel] = mode;
1153
1154 /* set the wavecache control reg */
1155 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1156
1157 /* Offset to PCMBAR */
1158 pa -= chip->dma.addr;
1159 pa >>= 1; /* words */
1160
1161 /* base offset of dma calcs when reading the pointer
1162 on this left one */
1163 es->base[channel] = pa & 0xFFFF;
1164 pa |= 0x00400000; /* bit 22 -> System RAM */
1165
1166 /* Begin loading the APU */
1167 for (i = 0; i < 16; i++)
1168 apu_set_register(chip, apu, i, 0x0000);
1169
1170 /* need to enable subgroups.. and we should probably
1171 have different groups for different /dev/dsps.. */
1172 apu_set_register(chip, apu, 2, 0x8);
1173
1174 /* Load the buffer into the wave engine */
1175 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1176 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1177 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1178 apu_set_register(chip, apu, 7, bsize);
1179 /* clear effects/env.. */
1180 apu_set_register(chip, apu, 8, 0x00F0);
1181 /* amplitude now? sure. why not. */
1182 apu_set_register(chip, apu, 9, 0x0000);
1183 /* set filter tune, radius, polar pan */
1184 apu_set_register(chip, apu, 10, 0x8F08);
1185 /* route input */
1186 apu_set_register(chip, apu, 11, route);
1187 /* dma on, no envelopes, filter to all 1s) */
1188 apu_set_register(chip, apu, 0, 0x400F);
1189}
1190
1191static void snd_es1968_capture_setup(es1968_t *chip, esschan_t *es,
1192 snd_pcm_runtime_t *runtime)
1193{
1194 int size;
1195 u32 freq;
1196 unsigned long flags;
1197
1198 size = es->dma_size >> es->wav_shift;
1199
1200 /* APU assignments:
1201 0 = mono/left SRC
1202 1 = right SRC
1203 2 = mono/left Input Mixer
1204 3 = right Input Mixer
1205 */
1206 /* data seems to flow from the codec, through an apu into
1207 the 'mixbuf' bit of page, then through the SRC apu
1208 and out to the real 'buffer'. ok. sure. */
1209
1210 /* input mixer (left/mono) */
1211 /* parallel in crap, see maestro reg 0xC [8-11] */
1212 init_capture_apu(chip, es, 2,
1213 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1214 ESM_APU_INPUTMIXER, 0x14);
1215 /* SRC (left/mono); get input from inputing apu */
1216 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1217 ESM_APU_SRCONVERTOR, es->apu[2]);
1218 if (es->fmt & ESS_FMT_STEREO) {
1219 /* input mixer (right) */
1220 init_capture_apu(chip, es, 3,
1221 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1222 ESM_MIXBUF_SIZE/4, /* in words */
1223 ESM_APU_INPUTMIXER, 0x15);
1224 /* SRC (right) */
1225 init_capture_apu(chip, es, 1,
1226 es->memory->buf.addr + size*2, size,
1227 ESM_APU_SRCONVERTOR, es->apu[3]);
1228 }
1229
1230 freq = runtime->rate;
1231 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1232 if (freq > 47999)
1233 freq = 47999;
1234 if (freq < 4000)
1235 freq = 4000;
1236
1237 freq = snd_es1968_compute_rate(chip, freq);
1238
1239 /* Load the frequency, turn on 6dB */
1240 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1241 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1242
1243 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1244 freq = 0x10000;
1245 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1246 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1247
1248 spin_lock_irqsave(&chip->reg_lock, flags);
1249 /* clear WP interrupts */
1250 outw(1, chip->io_port + 0x04);
1251 /* enable WP ints */
1252 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1253 spin_unlock_irqrestore(&chip->reg_lock, flags);
1254}
1255
1256/*******************
1257 * ALSA Interface *
1258 *******************/
1259
1260static int snd_es1968_pcm_prepare(snd_pcm_substream_t *substream)
1261{
1262 es1968_t *chip = snd_pcm_substream_chip(substream);
1263 snd_pcm_runtime_t *runtime = substream->runtime;
1264 esschan_t *es = runtime->private_data;
1265
1266 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1267 es->frag_size = snd_pcm_lib_period_bytes(substream);
1268
1269 es->wav_shift = 1; /* maestro handles always 16bit */
1270 es->fmt = 0;
1271 if (snd_pcm_format_width(runtime->format) == 16)
1272 es->fmt |= ESS_FMT_16BIT;
1273 if (runtime->channels > 1) {
1274 es->fmt |= ESS_FMT_STEREO;
1275 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1276 es->wav_shift++;
1277 }
1278 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1279
1280 switch (es->mode) {
1281 case ESM_MODE_PLAY:
1282 snd_es1968_playback_setup(chip, es, runtime);
1283 break;
1284 case ESM_MODE_CAPTURE:
1285 snd_es1968_capture_setup(chip, es, runtime);
1286 break;
1287 }
1288
1289 return 0;
1290}
1291
1292static int snd_es1968_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1293{
1294 es1968_t *chip = snd_pcm_substream_chip(substream);
1295 esschan_t *es = substream->runtime->private_data;
1296
1297 spin_lock(&chip->substream_lock);
1298 switch (cmd) {
1299 case SNDRV_PCM_TRIGGER_START:
1300 case SNDRV_PCM_TRIGGER_RESUME:
1301 if (es->running)
1302 break;
1303 snd_es1968_bob_inc(chip, es->bob_freq);
1304 es->count = 0;
1305 es->hwptr = 0;
1306 snd_es1968_pcm_start(chip, es);
1307 es->running = 1;
1308 break;
1309 case SNDRV_PCM_TRIGGER_STOP:
1310 case SNDRV_PCM_TRIGGER_SUSPEND:
1311 if (! es->running)
1312 break;
1313 snd_es1968_pcm_stop(chip, es);
1314 es->running = 0;
1315 snd_es1968_bob_dec(chip);
1316 break;
1317 }
1318 spin_unlock(&chip->substream_lock);
1319 return 0;
1320}
1321
1322static snd_pcm_uframes_t snd_es1968_pcm_pointer(snd_pcm_substream_t *substream)
1323{
1324 es1968_t *chip = snd_pcm_substream_chip(substream);
1325 esschan_t *es = substream->runtime->private_data;
1326 unsigned int ptr;
1327
1328 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1329
1330 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1331}
1332
1333static snd_pcm_hardware_t snd_es1968_playback = {
1334 .info = (SNDRV_PCM_INFO_MMAP |
1335 SNDRV_PCM_INFO_MMAP_VALID |
1336 SNDRV_PCM_INFO_INTERLEAVED |
1337 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1338 /*SNDRV_PCM_INFO_PAUSE |*/
1339 SNDRV_PCM_INFO_RESUME),
1340 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1341 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1342 .rate_min = 4000,
1343 .rate_max = 48000,
1344 .channels_min = 1,
1345 .channels_max = 2,
1346 .buffer_bytes_max = 65536,
1347 .period_bytes_min = 256,
1348 .period_bytes_max = 65536,
1349 .periods_min = 1,
1350 .periods_max = 1024,
1351 .fifo_size = 0,
1352};
1353
1354static snd_pcm_hardware_t snd_es1968_capture = {
1355 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1356 SNDRV_PCM_INFO_MMAP |
1357 SNDRV_PCM_INFO_MMAP_VALID |
1358 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1359 /*SNDRV_PCM_INFO_PAUSE |*/
1360 SNDRV_PCM_INFO_RESUME),
1361 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1362 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1363 .rate_min = 4000,
1364 .rate_max = 48000,
1365 .channels_min = 1,
1366 .channels_max = 2,
1367 .buffer_bytes_max = 65536,
1368 .period_bytes_min = 256,
1369 .period_bytes_max = 65536,
1370 .periods_min = 1,
1371 .periods_max = 1024,
1372 .fifo_size = 0,
1373};
1374
1375/* *************************
1376 * DMA memory management *
1377 *************************/
1378
1379/* Because the Maestro can only take addresses relative to the PCM base address
1380 register :( */
1381
1382static int calc_available_memory_size(es1968_t *chip)
1383{
1384 struct list_head *p;
1385 int max_size = 0;
1386
1387 down(&chip->memory_mutex);
1388 list_for_each(p, &chip->buf_list) {
1389 esm_memory_t *buf = list_entry(p, esm_memory_t, list);
1390 if (buf->empty && buf->buf.bytes > max_size)
1391 max_size = buf->buf.bytes;
1392 }
1393 up(&chip->memory_mutex);
1394 if (max_size >= 128*1024)
1395 max_size = 127*1024;
1396 return max_size;
1397}
1398
1399/* allocate a new memory chunk with the specified size */
1400static esm_memory_t *snd_es1968_new_memory(es1968_t *chip, int size)
1401{
1402 esm_memory_t *buf;
1403 struct list_head *p;
1404
1405 size = ((size + ESM_MEM_ALIGN - 1) / ESM_MEM_ALIGN) * ESM_MEM_ALIGN;
1406 down(&chip->memory_mutex);
1407 list_for_each(p, &chip->buf_list) {
1408 buf = list_entry(p, esm_memory_t, list);
1409 if (buf->empty && buf->buf.bytes >= size)
1410 goto __found;
1411 }
1412 up(&chip->memory_mutex);
1413 return NULL;
1414
1415__found:
1416 if (buf->buf.bytes > size) {
1417 esm_memory_t *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1418 if (chunk == NULL) {
1419 up(&chip->memory_mutex);
1420 return NULL;
1421 }
1422 chunk->buf = buf->buf;
1423 chunk->buf.bytes -= size;
1424 chunk->buf.area += size;
1425 chunk->buf.addr += size;
1426 chunk->empty = 1;
1427 buf->buf.bytes = size;
1428 list_add(&chunk->list, &buf->list);
1429 }
1430 buf->empty = 0;
1431 up(&chip->memory_mutex);
1432 return buf;
1433}
1434
1435/* free a memory chunk */
1436static void snd_es1968_free_memory(es1968_t *chip, esm_memory_t *buf)
1437{
1438 esm_memory_t *chunk;
1439
1440 down(&chip->memory_mutex);
1441 buf->empty = 1;
1442 if (buf->list.prev != &chip->buf_list) {
1443 chunk = list_entry(buf->list.prev, esm_memory_t, list);
1444 if (chunk->empty) {
1445 chunk->buf.bytes += buf->buf.bytes;
1446 list_del(&buf->list);
1447 kfree(buf);
1448 buf = chunk;
1449 }
1450 }
1451 if (buf->list.next != &chip->buf_list) {
1452 chunk = list_entry(buf->list.next, esm_memory_t, list);
1453 if (chunk->empty) {
1454 buf->buf.bytes += chunk->buf.bytes;
1455 list_del(&chunk->list);
1456 kfree(chunk);
1457 }
1458 }
1459 up(&chip->memory_mutex);
1460}
1461
1462static void snd_es1968_free_dmabuf(es1968_t *chip)
1463{
1464 struct list_head *p;
1465
1466 if (! chip->dma.area)
1467 return;
1468 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1469 while ((p = chip->buf_list.next) != &chip->buf_list) {
1470 esm_memory_t *chunk = list_entry(p, esm_memory_t, list);
1471 list_del(p);
1472 kfree(chunk);
1473 }
1474}
1475
1476static int __devinit
1477snd_es1968_init_dmabuf(es1968_t *chip)
1478{
1479 int err;
1480 esm_memory_t *chunk;
1481
1482 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1483 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1484 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1485 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1486 snd_dma_pci_data(chip->pci),
1487 chip->total_bufsize, &chip->dma);
1488 if (err < 0 || ! chip->dma.area) {
1489 snd_printk("es1968: can't allocate dma pages for size %d\n",
1490 chip->total_bufsize);
1491 return -ENOMEM;
1492 }
1493 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1494 snd_dma_free_pages(&chip->dma);
1495 snd_printk("es1968: DMA buffer beyond 256MB.\n");
1496 return -ENOMEM;
1497 }
1498 }
1499
1500 INIT_LIST_HEAD(&chip->buf_list);
1501 /* allocate an empty chunk */
1502 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1503 if (chunk == NULL) {
1504 snd_es1968_free_dmabuf(chip);
1505 return -ENOMEM;
1506 }
1507 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1508 chunk->buf = chip->dma;
1509 chunk->buf.area += ESM_MEM_ALIGN;
1510 chunk->buf.addr += ESM_MEM_ALIGN;
1511 chunk->buf.bytes -= ESM_MEM_ALIGN;
1512 chunk->empty = 1;
1513 list_add(&chunk->list, &chip->buf_list);
1514
1515 return 0;
1516}
1517
1518/* setup the dma_areas */
1519/* buffer is extracted from the pre-allocated memory chunk */
1520static int snd_es1968_hw_params(snd_pcm_substream_t *substream,
1521 snd_pcm_hw_params_t *hw_params)
1522{
1523 es1968_t *chip = snd_pcm_substream_chip(substream);
1524 snd_pcm_runtime_t *runtime = substream->runtime;
1525 esschan_t *chan = runtime->private_data;
1526 int size = params_buffer_bytes(hw_params);
1527
1528 if (chan->memory) {
1529 if (chan->memory->buf.bytes >= size) {
1530 runtime->dma_bytes = size;
1531 return 0;
1532 }
1533 snd_es1968_free_memory(chip, chan->memory);
1534 }
1535 chan->memory = snd_es1968_new_memory(chip, size);
1536 if (chan->memory == NULL) {
1537 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1538 return -ENOMEM;
1539 }
1540 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1541 return 1; /* area was changed */
1542}
1543
1544/* remove dma areas if allocated */
1545static int snd_es1968_hw_free(snd_pcm_substream_t * substream)
1546{
1547 es1968_t *chip = snd_pcm_substream_chip(substream);
1548 snd_pcm_runtime_t *runtime = substream->runtime;
1549 esschan_t *chan;
1550
1551 if (runtime->private_data == NULL)
1552 return 0;
1553 chan = runtime->private_data;
1554 if (chan->memory) {
1555 snd_es1968_free_memory(chip, chan->memory);
1556 chan->memory = NULL;
1557 }
1558 return 0;
1559}
1560
1561
1562/*
1563 * allocate APU pair
1564 */
1565static int snd_es1968_alloc_apu_pair(es1968_t *chip, int type)
1566{
1567 int apu;
1568
1569 for (apu = 0; apu < NR_APUS; apu += 2) {
1570 if (chip->apu[apu] == ESM_APU_FREE &&
1571 chip->apu[apu + 1] == ESM_APU_FREE) {
1572 chip->apu[apu] = chip->apu[apu + 1] = type;
1573 return apu;
1574 }
1575 }
1576 return -EBUSY;
1577}
1578
1579/*
1580 * release APU pair
1581 */
1582static void snd_es1968_free_apu_pair(es1968_t *chip, int apu)
1583{
1584 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1585}
1586
1587
1588/******************
1589 * PCM open/close *
1590 ******************/
1591
1592static int snd_es1968_playback_open(snd_pcm_substream_t *substream)
1593{
1594 es1968_t *chip = snd_pcm_substream_chip(substream);
1595 snd_pcm_runtime_t *runtime = substream->runtime;
1596 esschan_t *es;
1597 int apu1;
1598
1599 /* search 2 APUs */
1600 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1601 if (apu1 < 0)
1602 return apu1;
1603
1604 es = kcalloc(1, sizeof(*es), GFP_KERNEL);
1605 if (!es) {
1606 snd_es1968_free_apu_pair(chip, apu1);
1607 return -ENOMEM;
1608 }
1609
1610 es->apu[0] = apu1;
1611 es->apu[1] = apu1 + 1;
1612 es->apu_mode[0] = 0;
1613 es->apu_mode[1] = 0;
1614 es->running = 0;
1615 es->substream = substream;
1616 es->mode = ESM_MODE_PLAY;
1617
1618 runtime->private_data = es;
1619 runtime->hw = snd_es1968_playback;
1620 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1621 calc_available_memory_size(chip);
1622#if 0
1623 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1624 1024);
1625#endif
1626 spin_lock_irq(&chip->substream_lock);
1627 list_add(&es->list, &chip->substream_list);
1628 spin_unlock_irq(&chip->substream_lock);
1629
1630 return 0;
1631}
1632
1633static int snd_es1968_capture_open(snd_pcm_substream_t *substream)
1634{
1635 snd_pcm_runtime_t *runtime = substream->runtime;
1636 es1968_t *chip = snd_pcm_substream_chip(substream);
1637 esschan_t *es;
1638 int apu1, apu2;
1639
1640 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1641 if (apu1 < 0)
1642 return apu1;
1643 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1644 if (apu2 < 0) {
1645 snd_es1968_free_apu_pair(chip, apu1);
1646 return apu2;
1647 }
1648
1649 es = kcalloc(1, sizeof(*es), GFP_KERNEL);
1650 if (!es) {
1651 snd_es1968_free_apu_pair(chip, apu1);
1652 snd_es1968_free_apu_pair(chip, apu2);
1653 return -ENOMEM;
1654 }
1655
1656 es->apu[0] = apu1;
1657 es->apu[1] = apu1 + 1;
1658 es->apu[2] = apu2;
1659 es->apu[3] = apu2 + 1;
1660 es->apu_mode[0] = 0;
1661 es->apu_mode[1] = 0;
1662 es->apu_mode[2] = 0;
1663 es->apu_mode[3] = 0;
1664 es->running = 0;
1665 es->substream = substream;
1666 es->mode = ESM_MODE_CAPTURE;
1667
1668 /* get mixbuffer */
1669 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1670 snd_es1968_free_apu_pair(chip, apu1);
1671 snd_es1968_free_apu_pair(chip, apu2);
1672 kfree(es);
1673 return -ENOMEM;
1674 }
1675 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1676
1677 runtime->private_data = es;
1678 runtime->hw = snd_es1968_capture;
1679 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1680 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1681#if 0
1682 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1683 1024);
1684#endif
1685 spin_lock_irq(&chip->substream_lock);
1686 list_add(&es->list, &chip->substream_list);
1687 spin_unlock_irq(&chip->substream_lock);
1688
1689 return 0;
1690}
1691
1692static int snd_es1968_playback_close(snd_pcm_substream_t * substream)
1693{
1694 es1968_t *chip = snd_pcm_substream_chip(substream);
1695 esschan_t *es;
1696
1697 if (substream->runtime->private_data == NULL)
1698 return 0;
1699 es = substream->runtime->private_data;
1700 spin_lock_irq(&chip->substream_lock);
1701 list_del(&es->list);
1702 spin_unlock_irq(&chip->substream_lock);
1703 snd_es1968_free_apu_pair(chip, es->apu[0]);
1704 kfree(es);
1705
1706 return 0;
1707}
1708
1709static int snd_es1968_capture_close(snd_pcm_substream_t * substream)
1710{
1711 es1968_t *chip = snd_pcm_substream_chip(substream);
1712 esschan_t *es;
1713
1714 if (substream->runtime->private_data == NULL)
1715 return 0;
1716 es = substream->runtime->private_data;
1717 spin_lock_irq(&chip->substream_lock);
1718 list_del(&es->list);
1719 spin_unlock_irq(&chip->substream_lock);
1720 snd_es1968_free_memory(chip, es->mixbuf);
1721 snd_es1968_free_apu_pair(chip, es->apu[0]);
1722 snd_es1968_free_apu_pair(chip, es->apu[2]);
1723 kfree(es);
1724
1725 return 0;
1726}
1727
1728static snd_pcm_ops_t snd_es1968_playback_ops = {
1729 .open = snd_es1968_playback_open,
1730 .close = snd_es1968_playback_close,
1731 .ioctl = snd_pcm_lib_ioctl,
1732 .hw_params = snd_es1968_hw_params,
1733 .hw_free = snd_es1968_hw_free,
1734 .prepare = snd_es1968_pcm_prepare,
1735 .trigger = snd_es1968_pcm_trigger,
1736 .pointer = snd_es1968_pcm_pointer,
1737};
1738
1739static snd_pcm_ops_t snd_es1968_capture_ops = {
1740 .open = snd_es1968_capture_open,
1741 .close = snd_es1968_capture_close,
1742 .ioctl = snd_pcm_lib_ioctl,
1743 .hw_params = snd_es1968_hw_params,
1744 .hw_free = snd_es1968_hw_free,
1745 .prepare = snd_es1968_pcm_prepare,
1746 .trigger = snd_es1968_pcm_trigger,
1747 .pointer = snd_es1968_pcm_pointer,
1748};
1749
1750
1751/*
1752 * measure clock
1753 */
1754#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1755
1756static void __devinit es1968_measure_clock(es1968_t *chip)
1757{
1758 int i, apu;
1759 unsigned int pa, offset, t;
1760 esm_memory_t *memory;
1761 struct timeval start_time, stop_time;
1762
1763 if (chip->clock == 0)
1764 chip->clock = 48000; /* default clock value */
1765
1766 /* search 2 APUs (although one apu is enough) */
1767 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1768 snd_printk("Hmm, cannot find empty APU pair!?\n");
1769 return;
1770 }
1771 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1772 snd_printk("cannot allocate dma buffer - using default clock %d\n", chip->clock);
1773 snd_es1968_free_apu_pair(chip, apu);
1774 return;
1775 }
1776
1777 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1778
1779 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1780
1781 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1782 pa |= 0x00400000; /* System RAM (Bit 22) */
1783
1784 /* initialize apu */
1785 for (i = 0; i < 16; i++)
1786 apu_set_register(chip, apu, i, 0x0000);
1787
1788 apu_set_register(chip, apu, 0, 0x400f);
1789 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1790 apu_set_register(chip, apu, 5, pa & 0xffff);
1791 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1792 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1793 apu_set_register(chip, apu, 8, 0x0000);
1794 apu_set_register(chip, apu, 9, 0xD000);
1795 apu_set_register(chip, apu, 10, 0x8F08);
1796 apu_set_register(chip, apu, 11, 0x0000);
1797 spin_lock_irq(&chip->reg_lock);
1798 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1799 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1800 spin_unlock_irq(&chip->reg_lock);
1801
1802 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1803
1804 chip->in_measurement = 1;
1805 chip->measure_apu = apu;
1806 spin_lock_irq(&chip->reg_lock);
1807 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1808 __apu_set_register(chip, apu, 5, pa & 0xffff);
1809 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1810 do_gettimeofday(&start_time);
1811 spin_unlock_irq(&chip->reg_lock);
1812 set_current_state(TASK_UNINTERRUPTIBLE);
1813 schedule_timeout(HZ / 20); /* 50 msec */
1814 spin_lock_irq(&chip->reg_lock);
1815 offset = __apu_get_register(chip, apu, 5);
1816 do_gettimeofday(&stop_time);
1817 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1818 snd_es1968_bob_dec(chip);
1819 chip->in_measurement = 0;
1820 spin_unlock_irq(&chip->reg_lock);
1821
1822 /* check the current position */
1823 offset -= (pa & 0xffff);
1824 offset &= 0xfffe;
1825 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1826
1827 t = stop_time.tv_sec - start_time.tv_sec;
1828 t *= 1000000;
1829 if (stop_time.tv_usec < start_time.tv_usec)
1830 t -= start_time.tv_usec - stop_time.tv_usec;
1831 else
1832 t += stop_time.tv_usec - start_time.tv_usec;
1833 if (t == 0) {
1834 snd_printk("?? calculation error..\n");
1835 } else {
1836 offset *= 1000;
1837 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1838 if (offset < 47500 || offset > 48500) {
1839 if (offset >= 40000 && offset <= 50000)
1840 chip->clock = (chip->clock * offset) / 48000;
1841 }
1842 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1843 }
1844 snd_es1968_free_memory(chip, memory);
1845 snd_es1968_free_apu_pair(chip, apu);
1846}
1847
1848
1849/*
1850 */
1851
1852static void snd_es1968_pcm_free(snd_pcm_t *pcm)
1853{
1854 es1968_t *esm = pcm->private_data;
1855 snd_es1968_free_dmabuf(esm);
1856 esm->pcm = NULL;
1857}
1858
1859static int __devinit
1860snd_es1968_pcm(es1968_t *chip, int device)
1861{
1862 snd_pcm_t *pcm;
1863 int err;
1864
1865 /* get DMA buffer */
1866 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1867 return err;
1868
1869 /* set PCMBAR */
1870 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1871 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1872 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1873 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1874
1875 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1876 chip->playback_streams,
1877 chip->capture_streams, &pcm)) < 0)
1878 return err;
1879
1880 pcm->private_data = chip;
1881 pcm->private_free = snd_es1968_pcm_free;
1882
1883 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1884 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1885
1886 pcm->info_flags = 0;
1887
1888 strcpy(pcm->name, "ESS Maestro");
1889
1890 chip->pcm = pcm;
1891
1892 return 0;
1893}
1894
1895/*
1896 * update pointer
1897 */
1898static void snd_es1968_update_pcm(es1968_t *chip, esschan_t *es)
1899{
1900 unsigned int hwptr;
1901 unsigned int diff;
1902 snd_pcm_substream_t *subs = es->substream;
1903
1904 if (subs == NULL || !es->running)
1905 return;
1906
1907 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1908 hwptr %= es->dma_size;
1909
1910 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1911
1912 es->hwptr = hwptr;
1913 es->count += diff;
1914
1915 if (es->count > es->frag_size) {
1916 spin_unlock(&chip->substream_lock);
1917 snd_pcm_period_elapsed(subs);
1918 spin_lock(&chip->substream_lock);
1919 es->count %= es->frag_size;
1920 }
1921}
1922
1923/*
1924 */
1925static void es1968_update_hw_volume(unsigned long private_data)
1926{
1927 es1968_t *chip = (es1968_t *) private_data;
1928 int x, val;
1929 unsigned long flags;
1930
1931 /* Figure out which volume control button was pushed,
1932 based on differences from the default register
1933 values. */
1934 x = inb(chip->io_port + 0x1c);
1935 /* Reset the volume control registers. */
1936 outb(0x88, chip->io_port + 0x1c);
1937 outb(0x88, chip->io_port + 0x1d);
1938 outb(0x88, chip->io_port + 0x1e);
1939 outb(0x88, chip->io_port + 0x1f);
1940
1941 if (chip->in_suspend)
1942 return;
1943
1944 if (! chip->master_switch || ! chip->master_volume)
1945 return;
1946
1947 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1948 spin_lock_irqsave(&chip->ac97_lock, flags);
1949 val = chip->ac97->regs[AC97_MASTER];
1950 if (x & 1) {
1951 /* mute */
1952 val ^= 0x8000;
1953 chip->ac97->regs[AC97_MASTER] = val;
1954 outw(val, chip->io_port + ESM_AC97_DATA);
1955 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1956 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1957 &chip->master_switch->id);
1958 } else {
1959 val &= 0x7fff;
1960 if (((x>>1) & 7) > 4) {
1961 /* volume up */
1962 if ((val & 0xff) > 0)
1963 val--;
1964 if ((val & 0xff00) > 0)
1965 val -= 0x0100;
1966 } else {
1967 /* volume down */
1968 if ((val & 0xff) < 0x1f)
1969 val++;
1970 if ((val & 0xff00) < 0x1f00)
1971 val += 0x0100;
1972 }
1973 chip->ac97->regs[AC97_MASTER] = val;
1974 outw(val, chip->io_port + ESM_AC97_DATA);
1975 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1976 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1977 &chip->master_volume->id);
1978 }
1979 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1980}
1981
1982/*
1983 * interrupt handler
1984 */
1985static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1986{
1987 es1968_t *chip = dev_id;
1988 u32 event;
1989
1990 if (!(event = inb(chip->io_port + 0x1A)))
1991 return IRQ_NONE;
1992
1993 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1994
1995 if (event & ESM_HWVOL_IRQ)
1996 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1997
1998 /* else ack 'em all, i imagine */
1999 outb(0xFF, chip->io_port + 0x1A);
2000
2001 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
2002 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
2003 }
2004
2005 if (event & ESM_SOUND_IRQ) {
2006 struct list_head *p;
2007 spin_lock(&chip->substream_lock);
2008 list_for_each(p, &chip->substream_list) {
2009 esschan_t *es = list_entry(p, esschan_t, list);
2010 if (es->running)
2011 snd_es1968_update_pcm(chip, es);
2012 }
2013 spin_unlock(&chip->substream_lock);
2014 if (chip->in_measurement) {
2015 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
2016 if (curp < chip->measure_lastpos)
2017 chip->measure_count++;
2018 chip->measure_lastpos = curp;
2019 }
2020 }
2021
2022 return IRQ_HANDLED;
2023}
2024
2025/*
2026 * Mixer stuff
2027 */
2028
2029static int __devinit
2030snd_es1968_mixer(es1968_t *chip)
2031{
2032 ac97_bus_t *pbus;
2033 ac97_template_t ac97;
2034 snd_ctl_elem_id_t id;
2035 int err;
2036 static ac97_bus_ops_t ops = {
2037 .write = snd_es1968_ac97_write,
2038 .read = snd_es1968_ac97_read,
2039 };
2040
2041 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2042 return err;
2043 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2044
2045 memset(&ac97, 0, sizeof(ac97));
2046 ac97.private_data = chip;
2047 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2048 return err;
2049
2050 /* attach master switch / volumes for h/w volume control */
2051 memset(&id, 0, sizeof(id));
2052 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2053 strcpy(id.name, "Master Playback Switch");
2054 chip->master_switch = snd_ctl_find_id(chip->card, &id);
2055 memset(&id, 0, sizeof(id));
2056 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2057 strcpy(id.name, "Master Playback Volume");
2058 chip->master_volume = snd_ctl_find_id(chip->card, &id);
2059
2060 return 0;
2061}
2062
2063/*
2064 * reset ac97 codec
2065 */
2066
2067static void snd_es1968_ac97_reset(es1968_t *chip)
2068{
2069 unsigned long ioaddr = chip->io_port;
2070
2071 unsigned short save_ringbus_a;
2072 unsigned short save_68;
2073 unsigned short w;
2074 unsigned int vend;
2075
2076 /* save configuration */
2077 save_ringbus_a = inw(ioaddr + 0x36);
2078
2079 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2080 /* set command/status address i/o to 1st codec */
2081 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2082 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2083
2084 /* disable ac link */
2085 outw(0x0000, ioaddr + 0x36);
2086 save_68 = inw(ioaddr + 0x68);
2087 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2088 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2089 if (w & 1)
2090 save_68 |= 0x10;
2091 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2092 outw(0x0001, ioaddr + 0x68); /* gpio write */
2093 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2094 udelay(20);
2095 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2096 big_mdelay(20);
2097
2098 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2099 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2100 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2101 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2102
2103 /* now the second codec */
2104 /* disable ac link */
2105 outw(0x0000, ioaddr + 0x36);
2106 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2107 save_68 = inw(ioaddr + 0x68);
2108 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2109 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2110 udelay(20);
2111 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2112 big_mdelay(500);
2113 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2114 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2115 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2116
2117#if 0 /* the loop here needs to be much better if we want it.. */
2118 snd_printk("trying software reset\n");
2119 /* try and do a software reset */
2120 outb(0x80 | 0x7c, ioaddr + 0x30);
2121 for (w = 0;; w++) {
2122 if ((inw(ioaddr + 0x30) & 1) == 0) {
2123 if (inb(ioaddr + 0x32) != 0)
2124 break;
2125
2126 outb(0x80 | 0x7d, ioaddr + 0x30);
2127 if (((inw(ioaddr + 0x30) & 1) == 0)
2128 && (inb(ioaddr + 0x32) != 0))
2129 break;
2130 outb(0x80 | 0x7f, ioaddr + 0x30);
2131 if (((inw(ioaddr + 0x30) & 1) == 0)
2132 && (inb(ioaddr + 0x32) != 0))
2133 break;
2134 }
2135
2136 if (w > 10000) {
2137 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2138 big_mdelay(500); /* oh my.. */
2139 outb(inb(ioaddr + 0x37) & ~0x08,
2140 ioaddr + 0x37);
2141 udelay(1);
2142 outw(0x80, ioaddr + 0x30);
2143 for (w = 0; w < 10000; w++) {
2144 if ((inw(ioaddr + 0x30) & 1) == 0)
2145 break;
2146 }
2147 }
2148 }
2149#endif
2150 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2151 /* turn on external amp? */
2152 outw(0xf9ff, ioaddr + 0x64);
2153 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2154 outw(0x0209, ioaddr + 0x60);
2155 }
2156
2157 /* restore.. */
2158 outw(save_ringbus_a, ioaddr + 0x36);
2159
2160 /* Turn on the 978 docking chip.
2161 First frob the "master output enable" bit,
2162 then set most of the playback volume control registers to max. */
2163 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2164 outb(0xff, ioaddr+0xc3);
2165 outb(0xff, ioaddr+0xc4);
2166 outb(0xff, ioaddr+0xc6);
2167 outb(0xff, ioaddr+0xc8);
2168 outb(0x3f, ioaddr+0xcf);
2169 outb(0x3f, ioaddr+0xd0);
2170}
2171
2172static void snd_es1968_reset(es1968_t *chip)
2173{
2174 /* Reset */
2175 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2176 chip->io_port + ESM_PORT_HOST_IRQ);
2177 udelay(10);
2178 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2179 udelay(10);
2180}
2181
2182/*
2183 * power management
2184 */
2185static void snd_es1968_set_acpi(es1968_t *chip, int state)
2186{
2187 u16 active_mask = acpi_state_mask[state];
2188
2189 pci_set_power_state(chip->pci, state);
2190 /* make sure the units we care about are on
2191 XXX we might want to do this before state flipping? */
2192 pci_write_config_word(chip->pci, 0x54, ~ active_mask);
2193 pci_write_config_word(chip->pci, 0x56, ~ active_mask);
2194}
2195
2196
2197/*
2198 * initialize maestro chip
2199 */
2200static void snd_es1968_chip_init(es1968_t *chip)
2201{
2202 struct pci_dev *pci = chip->pci;
2203 int i;
2204 unsigned long iobase = chip->io_port;
2205 u16 w;
2206 u32 n;
2207
2208 /* We used to muck around with pci config space that
2209 * we had no business messing with. We don't know enough
2210 * about the machine to know which DMA mode is appropriate,
2211 * etc. We were guessing wrong on some machines and making
2212 * them unhappy. We now trust in the BIOS to do things right,
2213 * which almost certainly means a new host of problems will
2214 * arise with broken BIOS implementations. screw 'em.
2215 * We're already intolerant of machines that don't assign
2216 * IRQs.
2217 */
2218
2219 /* do config work at full power */
2220 snd_es1968_set_acpi(chip, ACPI_D0);
2221
2222 /* Config Reg A */
2223 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2224
2225 /* Use TDMA for now. TDMA works on all boards, so while its
2226 * not the most efficient its the simplest. */
2227 w &= ~DMA_CLEAR; /* Clear DMA bits */
2228 w |= DMA_TDMA; /* TDMA on */
2229 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2230 w &= ~SAFEGUARD; /* Safeguard off */
2231 w |= POST_WRITE; /* Posted write */
2232 w |= ISA_TIMING; /* ISA timing on */
2233 /* XXX huh? claims to be reserved.. */
2234 w &= ~SWAP_LR; /* swap left/right
2235 seems to only have effect on SB
2236 Emulation */
2237 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2238
2239 pci_write_config_word(pci, ESM_CONFIG_A, w);
2240
2241 /* Config Reg B */
2242
2243 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2244
2245 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2246 /* XXX how do we know which to use? */
2247 w &= ~(1 << 14); /* External clock */
2248
2249 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2250 w |= HWV_CONFB; /* HWV on */
2251 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2252 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2253 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2254 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2255 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2256 w &= ~(1 << 1); /* reserved, always write 0 */
2257 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2258
2259 pci_write_config_word(pci, ESM_CONFIG_B, w);
2260
2261 /* DDMA off */
2262
2263 pci_read_config_word(pci, ESM_DDMA, &w);
2264 w &= ~(1 << 0);
2265 pci_write_config_word(pci, ESM_DDMA, w);
2266
2267 /*
2268 * Legacy mode
2269 */
2270
2271 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2272
2273 w &= ~ESS_ENABLE_AUDIO; /* Disable Legacy Audio */
2274 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2275 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2276
2277 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2278
2279 /* Set up 978 docking control chip. */
2280 pci_read_config_word(pci, 0x58, &w);
2281 w|=1<<2; /* Enable 978. */
2282 w|=1<<3; /* Turn on 978 hardware volume control. */
2283 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2284 pci_write_config_word(pci, 0x58, w);
2285
2286 /* Sound Reset */
2287
2288 snd_es1968_reset(chip);
2289
2290 /*
2291 * Ring Bus Setup
2292 */
2293
2294 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2295 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2296 udelay(20);
2297 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2298 udelay(20);
2299
2300 /*
2301 * Reset the CODEC
2302 */
2303
2304 snd_es1968_ac97_reset(chip);
2305
2306 /* Ring Bus Control B */
2307
2308 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2309 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2310 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2311 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2312
2313 /* Set hardware volume control registers to midpoints.
2314 We can tell which button was pushed based on how they change. */
2315 outb(0x88, iobase+0x1c);
2316 outb(0x88, iobase+0x1d);
2317 outb(0x88, iobase+0x1e);
2318 outb(0x88, iobase+0x1f);
2319
2320 /* it appears some maestros (dell 7500) only work if these are set,
2321 regardless of wether we use the assp or not. */
2322
2323 outb(0, iobase + ASSP_CONTROL_B);
2324 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2325 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2326
2327 /*
2328 * set up wavecache
2329 */
2330 for (i = 0; i < 16; i++) {
2331 /* Write 0 into the buffer area 0x1E0->1EF */
2332 outw(0x01E0 + i, iobase + WC_INDEX);
2333 outw(0x0000, iobase + WC_DATA);
2334
2335 /* The 1.10 test program seem to write 0 into the buffer area
2336 * 0x1D0-0x1DF too.*/
2337 outw(0x01D0 + i, iobase + WC_INDEX);
2338 outw(0x0000, iobase + WC_DATA);
2339 }
2340 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2341 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2342 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2343 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2344 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2345 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2346 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2347 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2348
2349
2350 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2351 /* Now back to the DirectSound stuff */
2352 /* audio serial configuration.. ? */
2353 maestro_write(chip, 0x08, 0xB004);
2354 maestro_write(chip, 0x09, 0x001B);
2355 maestro_write(chip, 0x0A, 0x8000);
2356 maestro_write(chip, 0x0B, 0x3F37);
2357 maestro_write(chip, 0x0C, 0x0098);
2358
2359 /* parallel in, has something to do with recording :) */
2360 maestro_write(chip, 0x0C,
2361 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2362 /* parallel out */
2363 maestro_write(chip, 0x0C,
2364 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2365
2366 maestro_write(chip, 0x0D, 0x7632);
2367
2368 /* Wave cache control on - test off, sg off,
2369 enable, enable extra chans 1Mb */
2370
2371 w = inw(iobase + WC_CONTROL);
2372
2373 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2374 w |= 0xA000; /* reserved... I don't know */
2375 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2376 Seems to crash the Computer if enabled... */
2377 w |= 0x0100; /* Wave Cache Operation Enabled */
2378 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2379 w &= ~0x0060; /* Clear Wavtable Size */
2380 w |= 0x0020; /* Wavetable Size : 1MB */
2381 /* Bit 4 is reserved */
2382 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2383 /* Bit 1 is reserved */
2384 w &= ~0x0001; /* Test Mode off */
2385
2386 outw(w, iobase + WC_CONTROL);
2387
2388 /* Now clear the APU control ram */
2389 for (i = 0; i < NR_APUS; i++) {
2390 for (w = 0; w < NR_APU_REGS; w++)
2391 apu_set_register(chip, i, w, 0);
2392
2393 }
2394}
2395
2396/* Enable IRQ's */
2397static void snd_es1968_start_irq(es1968_t *chip)
2398{
2399 unsigned short w;
2400 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2401 if (chip->rmidi)
2402 w |= ESM_HIRQ_MPU401;
2403 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2404}
2405
2406#ifdef CONFIG_PM
2407/*
2408 * PM support
2409 */
2410static int es1968_suspend(snd_card_t *card, pm_message_t state)
2411{
2412 es1968_t *chip = card->pm_private_data;
2413
2414 if (! chip->do_pm)
2415 return 0;
2416
2417 chip->in_suspend = 1;
2418 snd_pcm_suspend_all(chip->pcm);
2419 snd_ac97_suspend(chip->ac97);
2420 snd_es1968_bob_stop(chip);
2421 snd_es1968_set_acpi(chip, ACPI_D3);
2422 pci_disable_device(chip->pci);
2423 return 0;
2424}
2425
2426static int es1968_resume(snd_card_t *card)
2427{
2428 es1968_t *chip = card->pm_private_data;
2429 struct list_head *p;
2430
2431 if (! chip->do_pm)
2432 return 0;
2433
2434 /* restore all our config */
2435 pci_enable_device(chip->pci);
2436 pci_set_master(chip->pci);
2437 snd_es1968_chip_init(chip);
2438
2439 /* need to restore the base pointers.. */
2440 if (chip->dma.addr) {
2441 /* set PCMBAR */
2442 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2443 }
2444
2445 snd_es1968_start_irq(chip);
2446
2447 /* restore ac97 state */
2448 snd_ac97_resume(chip->ac97);
2449
2450 list_for_each(p, &chip->substream_list) {
2451 esschan_t *es = list_entry(p, esschan_t, list);
2452 switch (es->mode) {
2453 case ESM_MODE_PLAY:
2454 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2455 break;
2456 case ESM_MODE_CAPTURE:
2457 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2458 break;
2459 }
2460 }
2461
2462 /* start timer again */
2463 if (chip->bobclient)
2464 snd_es1968_bob_start(chip);
2465
2466 chip->in_suspend = 0;
2467 return 0;
2468}
2469#endif /* CONFIG_PM */
2470
2471#ifdef SUPPORT_JOYSTICK
2472#define JOYSTICK_ADDR 0x200
2473static int __devinit snd_es1968_create_gameport(es1968_t *chip, int dev)
2474{
2475 struct gameport *gp;
2476 struct resource *r;
2477 u16 val;
2478
2479 if (!joystick[dev])
2480 return -ENODEV;
2481
2482 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2483 if (!r)
2484 return -EBUSY;
2485
2486 chip->gameport = gp = gameport_allocate_port();
2487 if (!gp) {
2488 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2489 release_resource(r);
2490 kfree_nocheck(r);
2491 return -ENOMEM;
2492 }
2493
2494 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2495 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2496
2497 gameport_set_name(gp, "ES1968 Gameport");
2498 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2499 gameport_set_dev_parent(gp, &chip->pci->dev);
2500 gp->io = JOYSTICK_ADDR;
2501 gameport_set_port_data(gp, r);
2502
2503 gameport_register_port(gp);
2504
2505 return 0;
2506}
2507
2508static void snd_es1968_free_gameport(es1968_t *chip)
2509{
2510 if (chip->gameport) {
2511 struct resource *r = gameport_get_port_data(chip->gameport);
2512
2513 gameport_unregister_port(chip->gameport);
2514 chip->gameport = NULL;
2515
2516 release_resource(r);
2517 kfree_nocheck(r);
2518 }
2519}
2520#else
2521static inline int snd_es1968_create_gameport(es1968_t *chip, int dev) { return -ENOSYS; }
2522static inline void snd_es1968_free_gameport(es1968_t *chip) { }
2523#endif
2524
2525static int snd_es1968_free(es1968_t *chip)
2526{
2527 if (chip->io_port) {
2528 synchronize_irq(chip->irq);
2529 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2530 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2531 }
2532
2533 if (chip->irq >= 0)
2534 free_irq(chip->irq, (void *)chip);
2535 snd_es1968_free_gameport(chip);
2536 snd_es1968_set_acpi(chip, ACPI_D3);
2537 chip->master_switch = NULL;
2538 chip->master_volume = NULL;
2539 pci_release_regions(chip->pci);
2540 pci_disable_device(chip->pci);
2541 kfree(chip);
2542 return 0;
2543}
2544
2545static int snd_es1968_dev_free(snd_device_t *device)
2546{
2547 es1968_t *chip = device->device_data;
2548 return snd_es1968_free(chip);
2549}
2550
2551struct ess_device_list {
2552 unsigned short type; /* chip type */
2553 unsigned short vendor; /* subsystem vendor id */
2554};
2555
2556static struct ess_device_list pm_whitelist[] __devinitdata = {
2557 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2558 { TYPE_MAESTRO2E, 0x1028 },
2559 { TYPE_MAESTRO2E, 0x103c },
2560 { TYPE_MAESTRO2E, 0x1179 },
2561 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2562};
2563
2564static struct ess_device_list mpu_blacklist[] __devinitdata = {
2565 { TYPE_MAESTRO2, 0x125d },
2566};
2567
2568static int __devinit snd_es1968_create(snd_card_t * card,
2569 struct pci_dev *pci,
2570 int total_bufsize,
2571 int play_streams,
2572 int capt_streams,
2573 int chip_type,
2574 int do_pm,
2575 es1968_t **chip_ret)
2576{
2577 static snd_device_ops_t ops = {
2578 .dev_free = snd_es1968_dev_free,
2579 };
2580 es1968_t *chip;
2581 int i, err;
2582
2583 *chip_ret = NULL;
2584
2585 /* enable PCI device */
2586 if ((err = pci_enable_device(pci)) < 0)
2587 return err;
2588 /* check, if we can restrict PCI DMA transfers to 28 bits */
2589 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 ||
2590 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) {
2591 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
2592 pci_disable_device(pci);
2593 return -ENXIO;
2594 }
2595
2596 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2597 if (! chip) {
2598 pci_disable_device(pci);
2599 return -ENOMEM;
2600 }
2601
2602 /* Set Vars */
2603 chip->type = chip_type;
2604 spin_lock_init(&chip->reg_lock);
2605 spin_lock_init(&chip->substream_lock);
2606 INIT_LIST_HEAD(&chip->buf_list);
2607 INIT_LIST_HEAD(&chip->substream_list);
2608 spin_lock_init(&chip->ac97_lock);
2609 init_MUTEX(&chip->memory_mutex);
2610 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2611 chip->card = card;
2612 chip->pci = pci;
2613 chip->irq = -1;
2614 chip->total_bufsize = total_bufsize; /* in bytes */
2615 chip->playback_streams = play_streams;
2616 chip->capture_streams = capt_streams;
2617
2618 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2619 kfree(chip);
2620 pci_disable_device(pci);
2621 return err;
2622 }
2623 chip->io_port = pci_resource_start(pci, 0);
2624 if (request_irq(pci->irq, snd_es1968_interrupt, SA_INTERRUPT|SA_SHIRQ,
2625 "ESS Maestro", (void*)chip)) {
2626 snd_printk("unable to grab IRQ %d\n", pci->irq);
2627 snd_es1968_free(chip);
2628 return -EBUSY;
2629 }
2630 chip->irq = pci->irq;
2631
2632 /* Clear Maestro_map */
2633 for (i = 0; i < 32; i++)
2634 chip->maestro_map[i] = 0;
2635
2636 /* Clear Apu Map */
2637 for (i = 0; i < NR_APUS; i++)
2638 chip->apu[i] = ESM_APU_FREE;
2639
2640 /* just to be sure */
2641 pci_set_master(pci);
2642
2643 if (do_pm > 1) {
2644 /* disable power-management if not on the whitelist */
2645 unsigned short vend;
2646 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2647 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2648 if (chip->type == pm_whitelist[i].type &&
2649 vend == pm_whitelist[i].vendor) {
2650 do_pm = 1;
2651 break;
2652 }
2653 }
2654 if (do_pm > 1) {
2655 /* not matched; disabling pm */
2656 printk(KERN_INFO "es1968: not attempting power management.\n");
2657 do_pm = 0;
2658 }
2659 }
2660 chip->do_pm = do_pm;
2661
2662 snd_es1968_chip_init(chip);
2663
2664 if (chip->do_pm)
2665 snd_card_set_pm_callback(card, es1968_suspend, es1968_resume, chip);
2666
2667 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2668 snd_es1968_free(chip);
2669 return err;
2670 }
2671
2672 snd_card_set_dev(card, &pci->dev);
2673
2674 *chip_ret = chip;
2675
2676 return 0;
2677}
2678
2679
2680/*
2681 */
2682static int __devinit snd_es1968_probe(struct pci_dev *pci,
2683 const struct pci_device_id *pci_id)
2684{
2685 static int dev;
2686 snd_card_t *card;
2687 es1968_t *chip;
2688 unsigned int i;
2689 int err;
2690
2691 if (dev >= SNDRV_CARDS)
2692 return -ENODEV;
2693 if (!enable[dev]) {
2694 dev++;
2695 return -ENOENT;
2696 }
2697
2698 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2699 if (!card)
2700 return -ENOMEM;
2701
2702 if (total_bufsize[dev] < 128)
2703 total_bufsize[dev] = 128;
2704 if (total_bufsize[dev] > 4096)
2705 total_bufsize[dev] = 4096;
2706 if ((err = snd_es1968_create(card, pci,
2707 total_bufsize[dev] * 1024, /* in bytes */
2708 pcm_substreams_p[dev],
2709 pcm_substreams_c[dev],
2710 pci_id->driver_data,
2711 use_pm[dev],
2712 &chip)) < 0) {
2713 snd_card_free(card);
2714 return err;
2715 }
2716
2717 switch (chip->type) {
2718 case TYPE_MAESTRO2E:
2719 strcpy(card->driver, "ES1978");
2720 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2721 break;
2722 case TYPE_MAESTRO2:
2723 strcpy(card->driver, "ES1968");
2724 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2725 break;
2726 case TYPE_MAESTRO:
2727 strcpy(card->driver, "ESM1");
2728 strcpy(card->shortname, "ESS Maestro 1");
2729 break;
2730 }
2731
2732 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2733 snd_card_free(card);
2734 return err;
2735 }
2736
2737 if ((err = snd_es1968_mixer(chip)) < 0) {
2738 snd_card_free(card);
2739 return err;
2740 }
2741
2742 if (enable_mpu[dev] == 2) {
2743 /* check the black list */
2744 unsigned short vend;
2745 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2746 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2747 if (chip->type == mpu_blacklist[i].type &&
2748 vend == mpu_blacklist[i].vendor) {
2749 enable_mpu[dev] = 0;
2750 break;
2751 }
2752 }
2753 }
2754 if (enable_mpu[dev]) {
2755 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2756 chip->io_port + ESM_MPU401_PORT, 1,
2757 chip->irq, 0, &chip->rmidi)) < 0) {
2758 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2759 }
2760 }
2761
2762 snd_es1968_create_gameport(chip, dev);
2763
2764 snd_es1968_start_irq(chip);
2765
2766 chip->clock = clock[dev];
2767 if (! chip->clock)
2768 es1968_measure_clock(chip);
2769
2770 sprintf(card->longname, "%s at 0x%lx, irq %i",
2771 card->shortname, chip->io_port, chip->irq);
2772
2773 if ((err = snd_card_register(card)) < 0) {
2774 snd_card_free(card);
2775 return err;
2776 }
2777 pci_set_drvdata(pci, card);
2778 dev++;
2779 return 0;
2780}
2781
2782static void __devexit snd_es1968_remove(struct pci_dev *pci)
2783{
2784 snd_card_free(pci_get_drvdata(pci));
2785 pci_set_drvdata(pci, NULL);
2786}
2787
2788static struct pci_driver driver = {
2789 .name = "ES1968 (ESS Maestro)",
2790 .id_table = snd_es1968_ids,
2791 .probe = snd_es1968_probe,
2792 .remove = __devexit_p(snd_es1968_remove),
2793 SND_PCI_PM_CALLBACKS
2794};
2795
2796static int __init alsa_card_es1968_init(void)
2797{
2798 return pci_module_init(&driver);
2799}
2800
2801static void __exit alsa_card_es1968_exit(void)
2802{
2803 pci_unregister_driver(&driver);
2804}
2805
2806module_init(alsa_card_es1968_init)
2807module_exit(alsa_card_es1968_exit)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 00:09:55 -0500