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-rw-r--r--sound/pci/ctxfi/cthw20k1.c2230
1 files changed, 2230 insertions, 0 deletions
diff --git a/sound/pci/ctxfi/cthw20k1.c b/sound/pci/ctxfi/cthw20k1.c
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index 000000000000..53572d92ef5d
--- /dev/null
+++ b/sound/pci/ctxfi/cthw20k1.c
@@ -0,0 +1,2230 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k1.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k1.
12 *
13 * @Author Liu Chun
14 * @Date Jun 24 2008
15 *
16 */
17
18#include "cthw20k1.h"
19#include "ct20k1reg.h"
20#include <linux/types.h>
21#include <linux/slab.h>
22#include <linux/pci.h>
23#include <linux/io.h>
24#include <linux/string.h>
25#include <linux/spinlock.h>
26#include <linux/kernel.h>
27#include <linux/interrupt.h>
28
29#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bits */
30
31struct hw20k1 {
32 struct hw hw;
33 spinlock_t reg_20k1_lock;
34 spinlock_t reg_pci_lock;
35};
36
37static u32 hw_read_20kx(struct hw *hw, u32 reg);
38static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
39static u32 hw_read_pci(struct hw *hw, u32 reg);
40static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
41
42/*
43 * Type definition block.
44 * The layout of control structures can be directly applied on 20k2 chip.
45 */
46
47/*
48 * SRC control block definitions.
49 */
50
51/* SRC resource control block */
52#define SRCCTL_STATE 0x00000007
53#define SRCCTL_BM 0x00000008
54#define SRCCTL_RSR 0x00000030
55#define SRCCTL_SF 0x000001C0
56#define SRCCTL_WR 0x00000200
57#define SRCCTL_PM 0x00000400
58#define SRCCTL_ROM 0x00001800
59#define SRCCTL_VO 0x00002000
60#define SRCCTL_ST 0x00004000
61#define SRCCTL_IE 0x00008000
62#define SRCCTL_ILSZ 0x000F0000
63#define SRCCTL_BP 0x00100000
64
65#define SRCCCR_CISZ 0x000007FF
66#define SRCCCR_CWA 0x001FF800
67#define SRCCCR_D 0x00200000
68#define SRCCCR_RS 0x01C00000
69#define SRCCCR_NAL 0x3E000000
70#define SRCCCR_RA 0xC0000000
71
72#define SRCCA_CA 0x03FFFFFF
73#define SRCCA_RS 0x1C000000
74#define SRCCA_NAL 0xE0000000
75
76#define SRCSA_SA 0x03FFFFFF
77
78#define SRCLA_LA 0x03FFFFFF
79
80/* Mixer Parameter Ring ram Low and Hight register.
81 * Fixed-point value in 8.24 format for parameter channel */
82#define MPRLH_PITCH 0xFFFFFFFF
83
84/* SRC resource register dirty flags */
85union src_dirty {
86 struct {
87 u16 ctl:1;
88 u16 ccr:1;
89 u16 sa:1;
90 u16 la:1;
91 u16 ca:1;
92 u16 mpr:1;
93 u16 czbfs:1; /* Clear Z-Buffers */
94 u16 rsv:9;
95 } bf;
96 u16 data;
97};
98
99struct src_rsc_ctrl_blk {
100 unsigned int ctl;
101 unsigned int ccr;
102 unsigned int ca;
103 unsigned int sa;
104 unsigned int la;
105 unsigned int mpr;
106 union src_dirty dirty;
107};
108
109/* SRC manager control block */
110union src_mgr_dirty {
111 struct {
112 u16 enb0:1;
113 u16 enb1:1;
114 u16 enb2:1;
115 u16 enb3:1;
116 u16 enb4:1;
117 u16 enb5:1;
118 u16 enb6:1;
119 u16 enb7:1;
120 u16 enbsa:1;
121 u16 rsv:7;
122 } bf;
123 u16 data;
124};
125
126struct src_mgr_ctrl_blk {
127 unsigned int enbsa;
128 unsigned int enb[8];
129 union src_mgr_dirty dirty;
130};
131
132/* SRCIMP manager control block */
133#define SRCAIM_ARC 0x00000FFF
134#define SRCAIM_NXT 0x00FF0000
135#define SRCAIM_SRC 0xFF000000
136
137struct srcimap {
138 unsigned int srcaim;
139 unsigned int idx;
140};
141
142/* SRCIMP manager register dirty flags */
143union srcimp_mgr_dirty {
144 struct {
145 u16 srcimap:1;
146 u16 rsv:15;
147 } bf;
148 u16 data;
149};
150
151struct srcimp_mgr_ctrl_blk {
152 struct srcimap srcimap;
153 union srcimp_mgr_dirty dirty;
154};
155
156/*
157 * Function implementation block.
158 */
159
160static int src_get_rsc_ctrl_blk(void **rblk)
161{
162 struct src_rsc_ctrl_blk *blk;
163
164 *rblk = NULL;
165 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
166 if (NULL == blk)
167 return -ENOMEM;
168
169 *rblk = blk;
170
171 return 0;
172}
173
174static int src_put_rsc_ctrl_blk(void *blk)
175{
176 kfree((struct src_rsc_ctrl_blk *)blk);
177
178 return 0;
179}
180
181static int src_set_state(void *blk, unsigned int state)
182{
183 struct src_rsc_ctrl_blk *ctl = blk;
184
185 set_field(&ctl->ctl, SRCCTL_STATE, state);
186 ctl->dirty.bf.ctl = 1;
187 return 0;
188}
189
190static int src_set_bm(void *blk, unsigned int bm)
191{
192 struct src_rsc_ctrl_blk *ctl = blk;
193
194 set_field(&ctl->ctl, SRCCTL_BM, bm);
195 ctl->dirty.bf.ctl = 1;
196 return 0;
197}
198
199static int src_set_rsr(void *blk, unsigned int rsr)
200{
201 struct src_rsc_ctrl_blk *ctl = blk;
202
203 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
204 ctl->dirty.bf.ctl = 1;
205 return 0;
206}
207
208static int src_set_sf(void *blk, unsigned int sf)
209{
210 struct src_rsc_ctrl_blk *ctl = blk;
211
212 set_field(&ctl->ctl, SRCCTL_SF, sf);
213 ctl->dirty.bf.ctl = 1;
214 return 0;
215}
216
217static int src_set_wr(void *blk, unsigned int wr)
218{
219 struct src_rsc_ctrl_blk *ctl = blk;
220
221 set_field(&ctl->ctl, SRCCTL_WR, wr);
222 ctl->dirty.bf.ctl = 1;
223 return 0;
224}
225
226static int src_set_pm(void *blk, unsigned int pm)
227{
228 struct src_rsc_ctrl_blk *ctl = blk;
229
230 set_field(&ctl->ctl, SRCCTL_PM, pm);
231 ctl->dirty.bf.ctl = 1;
232 return 0;
233}
234
235static int src_set_rom(void *blk, unsigned int rom)
236{
237 struct src_rsc_ctrl_blk *ctl = blk;
238
239 set_field(&ctl->ctl, SRCCTL_ROM, rom);
240 ctl->dirty.bf.ctl = 1;
241 return 0;
242}
243
244static int src_set_vo(void *blk, unsigned int vo)
245{
246 struct src_rsc_ctrl_blk *ctl = blk;
247
248 set_field(&ctl->ctl, SRCCTL_VO, vo);
249 ctl->dirty.bf.ctl = 1;
250 return 0;
251}
252
253static int src_set_st(void *blk, unsigned int st)
254{
255 struct src_rsc_ctrl_blk *ctl = blk;
256
257 set_field(&ctl->ctl, SRCCTL_ST, st);
258 ctl->dirty.bf.ctl = 1;
259 return 0;
260}
261
262static int src_set_ie(void *blk, unsigned int ie)
263{
264 struct src_rsc_ctrl_blk *ctl = blk;
265
266 set_field(&ctl->ctl, SRCCTL_IE, ie);
267 ctl->dirty.bf.ctl = 1;
268 return 0;
269}
270
271static int src_set_ilsz(void *blk, unsigned int ilsz)
272{
273 struct src_rsc_ctrl_blk *ctl = blk;
274
275 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
276 ctl->dirty.bf.ctl = 1;
277 return 0;
278}
279
280static int src_set_bp(void *blk, unsigned int bp)
281{
282 struct src_rsc_ctrl_blk *ctl = blk;
283
284 set_field(&ctl->ctl, SRCCTL_BP, bp);
285 ctl->dirty.bf.ctl = 1;
286 return 0;
287}
288
289static int src_set_cisz(void *blk, unsigned int cisz)
290{
291 struct src_rsc_ctrl_blk *ctl = blk;
292
293 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
294 ctl->dirty.bf.ccr = 1;
295 return 0;
296}
297
298static int src_set_ca(void *blk, unsigned int ca)
299{
300 struct src_rsc_ctrl_blk *ctl = blk;
301
302 set_field(&ctl->ca, SRCCA_CA, ca);
303 ctl->dirty.bf.ca = 1;
304 return 0;
305}
306
307static int src_set_sa(void *blk, unsigned int sa)
308{
309 struct src_rsc_ctrl_blk *ctl = blk;
310
311 set_field(&ctl->sa, SRCSA_SA, sa);
312 ctl->dirty.bf.sa = 1;
313 return 0;
314}
315
316static int src_set_la(void *blk, unsigned int la)
317{
318 struct src_rsc_ctrl_blk *ctl = blk;
319
320 set_field(&ctl->la, SRCLA_LA, la);
321 ctl->dirty.bf.la = 1;
322 return 0;
323}
324
325static int src_set_pitch(void *blk, unsigned int pitch)
326{
327 struct src_rsc_ctrl_blk *ctl = blk;
328
329 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
330 ctl->dirty.bf.mpr = 1;
331 return 0;
332}
333
334static int src_set_clear_zbufs(void *blk, unsigned int clear)
335{
336 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
337 return 0;
338}
339
340static int src_set_dirty(void *blk, unsigned int flags)
341{
342 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
343 return 0;
344}
345
346static int src_set_dirty_all(void *blk)
347{
348 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
349 return 0;
350}
351
352#define AR_SLOT_SIZE 4096
353#define AR_SLOT_BLOCK_SIZE 16
354#define AR_PTS_PITCH 6
355#define AR_PARAM_SRC_OFFSET 0x60
356
357static unsigned int src_param_pitch_mixer(unsigned int src_idx)
358{
359 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
360 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
361
362}
363
364static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
365{
366 struct src_rsc_ctrl_blk *ctl = blk;
367 int i = 0;
368
369 if (ctl->dirty.bf.czbfs) {
370 /* Clear Z-Buffer registers */
371 for (i = 0; i < 8; i++)
372 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
373
374 for (i = 0; i < 4; i++)
375 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
376
377 for (i = 0; i < 8; i++)
378 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
379
380 ctl->dirty.bf.czbfs = 0;
381 }
382 if (ctl->dirty.bf.mpr) {
383 /* Take the parameter mixer resource in the same group as that
384 * the idx src is in for simplicity. Unlike src, all conjugate
385 * parameter mixer resources must be programmed for
386 * corresponding conjugate src resources. */
387 unsigned int pm_idx = src_param_pitch_mixer(idx);
388 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
389 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
390 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
391 ctl->dirty.bf.mpr = 0;
392 }
393 if (ctl->dirty.bf.sa) {
394 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
395 ctl->dirty.bf.sa = 0;
396 }
397 if (ctl->dirty.bf.la) {
398 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
399 ctl->dirty.bf.la = 0;
400 }
401 if (ctl->dirty.bf.ca) {
402 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
403 ctl->dirty.bf.ca = 0;
404 }
405
406 /* Write srccf register */
407 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
408
409 if (ctl->dirty.bf.ccr) {
410 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
411 ctl->dirty.bf.ccr = 0;
412 }
413 if (ctl->dirty.bf.ctl) {
414 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
415 ctl->dirty.bf.ctl = 0;
416 }
417
418 return 0;
419}
420
421static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
422{
423 struct src_rsc_ctrl_blk *ctl = blk;
424
425 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
426 ctl->dirty.bf.ca = 0;
427
428 return get_field(ctl->ca, SRCCA_CA);
429}
430
431static unsigned int src_get_dirty(void *blk)
432{
433 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
434}
435
436static unsigned int src_dirty_conj_mask(void)
437{
438 return 0x20;
439}
440
441static int src_mgr_enbs_src(void *blk, unsigned int idx)
442{
443 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
444 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
445 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
446 return 0;
447}
448
449static int src_mgr_enb_src(void *blk, unsigned int idx)
450{
451 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
452 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
453 return 0;
454}
455
456static int src_mgr_dsb_src(void *blk, unsigned int idx)
457{
458 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
459 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
460 return 0;
461}
462
463static int src_mgr_commit_write(struct hw *hw, void *blk)
464{
465 struct src_mgr_ctrl_blk *ctl = blk;
466 int i = 0;
467 unsigned int ret = 0;
468
469 if (ctl->dirty.bf.enbsa) {
470 do {
471 ret = hw_read_20kx(hw, SRCENBSTAT);
472 } while (ret & 0x1);
473 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
474 ctl->dirty.bf.enbsa = 0;
475 }
476 for (i = 0; i < 8; i++) {
477 if ((ctl->dirty.data & (0x1 << i))) {
478 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
479 ctl->dirty.data &= ~(0x1 << i);
480 }
481 }
482
483 return 0;
484}
485
486static int src_mgr_get_ctrl_blk(void **rblk)
487{
488 struct src_mgr_ctrl_blk *blk;
489
490 *rblk = NULL;
491 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
492 if (NULL == blk)
493 return -ENOMEM;
494
495 *rblk = blk;
496
497 return 0;
498}
499
500static int src_mgr_put_ctrl_blk(void *blk)
501{
502 kfree((struct src_mgr_ctrl_blk *)blk);
503
504 return 0;
505}
506
507static int srcimp_mgr_get_ctrl_blk(void **rblk)
508{
509 struct srcimp_mgr_ctrl_blk *blk;
510
511 *rblk = NULL;
512 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
513 if (NULL == blk)
514 return -ENOMEM;
515
516 *rblk = blk;
517
518 return 0;
519}
520
521static int srcimp_mgr_put_ctrl_blk(void *blk)
522{
523 kfree((struct srcimp_mgr_ctrl_blk *)blk);
524
525 return 0;
526}
527
528static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
529{
530 struct srcimp_mgr_ctrl_blk *ctl = blk;
531
532 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
533 ctl->dirty.bf.srcimap = 1;
534 return 0;
535}
536
537static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
538{
539 struct srcimp_mgr_ctrl_blk *ctl = blk;
540
541 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
542 ctl->dirty.bf.srcimap = 1;
543 return 0;
544}
545
546static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
547{
548 struct srcimp_mgr_ctrl_blk *ctl = blk;
549
550 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
551 ctl->dirty.bf.srcimap = 1;
552 return 0;
553}
554
555static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
556{
557 struct srcimp_mgr_ctrl_blk *ctl = blk;
558
559 ctl->srcimap.idx = addr;
560 ctl->dirty.bf.srcimap = 1;
561 return 0;
562}
563
564static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
565{
566 struct srcimp_mgr_ctrl_blk *ctl = blk;
567
568 if (ctl->dirty.bf.srcimap) {
569 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
570 ctl->srcimap.srcaim);
571 ctl->dirty.bf.srcimap = 0;
572 }
573
574 return 0;
575}
576
577/*
578 * AMIXER control block definitions.
579 */
580
581#define AMOPLO_M 0x00000003
582#define AMOPLO_X 0x0003FFF0
583#define AMOPLO_Y 0xFFFC0000
584
585#define AMOPHI_SADR 0x000000FF
586#define AMOPHI_SE 0x80000000
587
588/* AMIXER resource register dirty flags */
589union amixer_dirty {
590 struct {
591 u16 amoplo:1;
592 u16 amophi:1;
593 u16 rsv:14;
594 } bf;
595 u16 data;
596};
597
598/* AMIXER resource control block */
599struct amixer_rsc_ctrl_blk {
600 unsigned int amoplo;
601 unsigned int amophi;
602 union amixer_dirty dirty;
603};
604
605static int amixer_set_mode(void *blk, unsigned int mode)
606{
607 struct amixer_rsc_ctrl_blk *ctl = blk;
608
609 set_field(&ctl->amoplo, AMOPLO_M, mode);
610 ctl->dirty.bf.amoplo = 1;
611 return 0;
612}
613
614static int amixer_set_iv(void *blk, unsigned int iv)
615{
616 /* 20k1 amixer does not have this field */
617 return 0;
618}
619
620static int amixer_set_x(void *blk, unsigned int x)
621{
622 struct amixer_rsc_ctrl_blk *ctl = blk;
623
624 set_field(&ctl->amoplo, AMOPLO_X, x);
625 ctl->dirty.bf.amoplo = 1;
626 return 0;
627}
628
629static int amixer_set_y(void *blk, unsigned int y)
630{
631 struct amixer_rsc_ctrl_blk *ctl = blk;
632
633 set_field(&ctl->amoplo, AMOPLO_Y, y);
634 ctl->dirty.bf.amoplo = 1;
635 return 0;
636}
637
638static int amixer_set_sadr(void *blk, unsigned int sadr)
639{
640 struct amixer_rsc_ctrl_blk *ctl = blk;
641
642 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
643 ctl->dirty.bf.amophi = 1;
644 return 0;
645}
646
647static int amixer_set_se(void *blk, unsigned int se)
648{
649 struct amixer_rsc_ctrl_blk *ctl = blk;
650
651 set_field(&ctl->amophi, AMOPHI_SE, se);
652 ctl->dirty.bf.amophi = 1;
653 return 0;
654}
655
656static int amixer_set_dirty(void *blk, unsigned int flags)
657{
658 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
659 return 0;
660}
661
662static int amixer_set_dirty_all(void *blk)
663{
664 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
665 return 0;
666}
667
668static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
669{
670 struct amixer_rsc_ctrl_blk *ctl = blk;
671
672 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
673 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
674 ctl->dirty.bf.amoplo = 0;
675 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
676 ctl->dirty.bf.amophi = 0;
677 }
678
679 return 0;
680}
681
682static int amixer_get_y(void *blk)
683{
684 struct amixer_rsc_ctrl_blk *ctl = blk;
685
686 return get_field(ctl->amoplo, AMOPLO_Y);
687}
688
689static unsigned int amixer_get_dirty(void *blk)
690{
691 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
692}
693
694static int amixer_rsc_get_ctrl_blk(void **rblk)
695{
696 struct amixer_rsc_ctrl_blk *blk;
697
698 *rblk = NULL;
699 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
700 if (NULL == blk)
701 return -ENOMEM;
702
703 *rblk = blk;
704
705 return 0;
706}
707
708static int amixer_rsc_put_ctrl_blk(void *blk)
709{
710 kfree((struct amixer_rsc_ctrl_blk *)blk);
711
712 return 0;
713}
714
715static int amixer_mgr_get_ctrl_blk(void **rblk)
716{
717 /*amixer_mgr_ctrl_blk_t *blk;*/
718
719 *rblk = NULL;
720 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
721 if (NULL == blk)
722 return -ENOMEM;
723
724 *rblk = blk;*/
725
726 return 0;
727}
728
729static int amixer_mgr_put_ctrl_blk(void *blk)
730{
731 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
732
733 return 0;
734}
735
736/*
737 * DAIO control block definitions.
738 */
739
740/* Receiver Sample Rate Tracker Control register */
741#define SRTCTL_SRCR 0x000000FF
742#define SRTCTL_SRCL 0x0000FF00
743#define SRTCTL_RSR 0x00030000
744#define SRTCTL_DRAT 0x000C0000
745#define SRTCTL_RLE 0x10000000
746#define SRTCTL_RLP 0x20000000
747#define SRTCTL_EC 0x40000000
748#define SRTCTL_ET 0x80000000
749
750/* DAIO Receiver register dirty flags */
751union dai_dirty {
752 struct {
753 u16 srtctl:1;
754 u16 rsv:15;
755 } bf;
756 u16 data;
757};
758
759/* DAIO Receiver control block */
760struct dai_ctrl_blk {
761 unsigned int srtctl;
762 union dai_dirty dirty;
763};
764
765/* S/PDIF Transmitter register dirty flags */
766union dao_dirty {
767 struct {
768 u16 spos:1;
769 u16 rsv:15;
770 } bf;
771 u16 data;
772};
773
774/* S/PDIF Transmitter control block */
775struct dao_ctrl_blk {
776 unsigned int spos; /* S/PDIF Output Channel Status Register */
777 union dao_dirty dirty;
778};
779
780/* Audio Input Mapper RAM */
781#define AIM_ARC 0x00000FFF
782#define AIM_NXT 0x007F0000
783
784struct daoimap {
785 unsigned int aim;
786 unsigned int idx;
787};
788
789/* I2S Transmitter/Receiver Control register */
790#define I2SCTL_EA 0x00000004
791#define I2SCTL_EI 0x00000010
792
793/* S/PDIF Transmitter Control register */
794#define SPOCTL_OE 0x00000001
795#define SPOCTL_OS 0x0000000E
796#define SPOCTL_RIV 0x00000010
797#define SPOCTL_LIV 0x00000020
798#define SPOCTL_SR 0x000000C0
799
800/* S/PDIF Receiver Control register */
801#define SPICTL_EN 0x00000001
802#define SPICTL_I24 0x00000002
803#define SPICTL_IB 0x00000004
804#define SPICTL_SM 0x00000008
805#define SPICTL_VM 0x00000010
806
807/* DAIO manager register dirty flags */
808union daio_mgr_dirty {
809 struct {
810 u32 i2soctl:4;
811 u32 i2sictl:4;
812 u32 spoctl:4;
813 u32 spictl:4;
814 u32 daoimap:1;
815 u32 rsv:15;
816 } bf;
817 u32 data;
818};
819
820/* DAIO manager control block */
821struct daio_mgr_ctrl_blk {
822 unsigned int i2sctl;
823 unsigned int spoctl;
824 unsigned int spictl;
825 struct daoimap daoimap;
826 union daio_mgr_dirty dirty;
827};
828
829static int dai_srt_set_srcr(void *blk, unsigned int src)
830{
831 struct dai_ctrl_blk *ctl = blk;
832
833 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
834 ctl->dirty.bf.srtctl = 1;
835 return 0;
836}
837
838static int dai_srt_set_srcl(void *blk, unsigned int src)
839{
840 struct dai_ctrl_blk *ctl = blk;
841
842 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
843 ctl->dirty.bf.srtctl = 1;
844 return 0;
845}
846
847static int dai_srt_set_rsr(void *blk, unsigned int rsr)
848{
849 struct dai_ctrl_blk *ctl = blk;
850
851 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
852 ctl->dirty.bf.srtctl = 1;
853 return 0;
854}
855
856static int dai_srt_set_drat(void *blk, unsigned int drat)
857{
858 struct dai_ctrl_blk *ctl = blk;
859
860 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
861 ctl->dirty.bf.srtctl = 1;
862 return 0;
863}
864
865static int dai_srt_set_ec(void *blk, unsigned int ec)
866{
867 struct dai_ctrl_blk *ctl = blk;
868
869 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
870 ctl->dirty.bf.srtctl = 1;
871 return 0;
872}
873
874static int dai_srt_set_et(void *blk, unsigned int et)
875{
876 struct dai_ctrl_blk *ctl = blk;
877
878 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
879 ctl->dirty.bf.srtctl = 1;
880 return 0;
881}
882
883static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
884{
885 struct dai_ctrl_blk *ctl = blk;
886
887 if (ctl->dirty.bf.srtctl) {
888 if (idx < 4) {
889 /* S/PDIF SRTs */
890 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
891 } else {
892 /* I2S SRT */
893 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
894 }
895 ctl->dirty.bf.srtctl = 0;
896 }
897
898 return 0;
899}
900
901static int dai_get_ctrl_blk(void **rblk)
902{
903 struct dai_ctrl_blk *blk;
904
905 *rblk = NULL;
906 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
907 if (NULL == blk)
908 return -ENOMEM;
909
910 *rblk = blk;
911
912 return 0;
913}
914
915static int dai_put_ctrl_blk(void *blk)
916{
917 kfree((struct dai_ctrl_blk *)blk);
918
919 return 0;
920}
921
922static int dao_set_spos(void *blk, unsigned int spos)
923{
924 ((struct dao_ctrl_blk *)blk)->spos = spos;
925 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
926 return 0;
927}
928
929static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
930{
931 struct dao_ctrl_blk *ctl = blk;
932
933 if (ctl->dirty.bf.spos) {
934 if (idx < 4) {
935 /* S/PDIF SPOSx */
936 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
937 }
938 ctl->dirty.bf.spos = 0;
939 }
940
941 return 0;
942}
943
944static int dao_get_spos(void *blk, unsigned int *spos)
945{
946 *spos = ((struct dao_ctrl_blk *)blk)->spos;
947 return 0;
948}
949
950static int dao_get_ctrl_blk(void **rblk)
951{
952 struct dao_ctrl_blk *blk;
953
954 *rblk = NULL;
955 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
956 if (NULL == blk)
957 return -ENOMEM;
958
959 *rblk = blk;
960
961 return 0;
962}
963
964static int dao_put_ctrl_blk(void *blk)
965{
966 kfree((struct dao_ctrl_blk *)blk);
967
968 return 0;
969}
970
971static int daio_mgr_enb_dai(void *blk, unsigned int idx)
972{
973 struct daio_mgr_ctrl_blk *ctl = blk;
974
975 if (idx < 4) {
976 /* S/PDIF input */
977 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
978 ctl->dirty.bf.spictl |= (0x1 << idx);
979 } else {
980 /* I2S input */
981 idx %= 4;
982 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
983 ctl->dirty.bf.i2sictl |= (0x1 << idx);
984 }
985 return 0;
986}
987
988static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
989{
990 struct daio_mgr_ctrl_blk *ctl = blk;
991
992 if (idx < 4) {
993 /* S/PDIF input */
994 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
995 ctl->dirty.bf.spictl |= (0x1 << idx);
996 } else {
997 /* I2S input */
998 idx %= 4;
999 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
1000 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1001 }
1002 return 0;
1003}
1004
1005static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1006{
1007 struct daio_mgr_ctrl_blk *ctl = blk;
1008
1009 if (idx < 4) {
1010 /* S/PDIF output */
1011 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1012 ctl->dirty.bf.spoctl |= (0x1 << idx);
1013 } else {
1014 /* I2S output */
1015 idx %= 4;
1016 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1017 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1018 }
1019 return 0;
1020}
1021
1022static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1023{
1024 struct daio_mgr_ctrl_blk *ctl = blk;
1025
1026 if (idx < 4) {
1027 /* S/PDIF output */
1028 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1029 ctl->dirty.bf.spoctl |= (0x1 << idx);
1030 } else {
1031 /* I2S output */
1032 idx %= 4;
1033 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1034 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1035 }
1036 return 0;
1037}
1038
1039static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1040{
1041 struct daio_mgr_ctrl_blk *ctl = blk;
1042
1043 if (idx < 4) {
1044 /* S/PDIF output */
1045 switch ((conf & 0x7)) {
1046 case 0:
1047 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1048 break; /* CDIF */
1049 case 1:
1050 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1051 break;
1052 case 2:
1053 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1054 break;
1055 case 4:
1056 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1057 break;
1058 default:
1059 break;
1060 }
1061 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1062 (conf >> 4) & 0x1); /* Non-audio */
1063 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1064 (conf >> 4) & 0x1); /* Non-audio */
1065 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1066 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1067
1068 ctl->dirty.bf.spoctl |= (0x1 << idx);
1069 } else {
1070 /* I2S output */
1071 /*idx %= 4; */
1072 }
1073 return 0;
1074}
1075
1076static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1077{
1078 struct daio_mgr_ctrl_blk *ctl = blk;
1079
1080 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1081 ctl->dirty.bf.daoimap = 1;
1082 return 0;
1083}
1084
1085static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1086{
1087 struct daio_mgr_ctrl_blk *ctl = blk;
1088
1089 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1090 ctl->dirty.bf.daoimap = 1;
1091 return 0;
1092}
1093
1094static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1095{
1096 struct daio_mgr_ctrl_blk *ctl = blk;
1097
1098 ctl->daoimap.idx = addr;
1099 ctl->dirty.bf.daoimap = 1;
1100 return 0;
1101}
1102
1103static int daio_mgr_commit_write(struct hw *hw, void *blk)
1104{
1105 struct daio_mgr_ctrl_blk *ctl = blk;
1106 int i = 0;
1107
1108 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1109 for (i = 0; i < 4; i++) {
1110 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1111 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1112
1113 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1114 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1115 }
1116 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1117 mdelay(1);
1118 }
1119 if (ctl->dirty.bf.spoctl) {
1120 for (i = 0; i < 4; i++) {
1121 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1122 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1123 }
1124 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1125 mdelay(1);
1126 }
1127 if (ctl->dirty.bf.spictl) {
1128 for (i = 0; i < 4; i++) {
1129 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1130 ctl->dirty.bf.spictl &= ~(0x1 << i);
1131 }
1132 hw_write_20kx(hw, SPICTL, ctl->spictl);
1133 mdelay(1);
1134 }
1135 if (ctl->dirty.bf.daoimap) {
1136 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1137 ctl->daoimap.aim);
1138 ctl->dirty.bf.daoimap = 0;
1139 }
1140
1141 return 0;
1142}
1143
1144static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1145{
1146 struct daio_mgr_ctrl_blk *blk;
1147
1148 *rblk = NULL;
1149 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1150 if (NULL == blk)
1151 return -ENOMEM;
1152
1153 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1154 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1155 blk->spictl = hw_read_20kx(hw, SPICTL);
1156
1157 *rblk = blk;
1158
1159 return 0;
1160}
1161
1162static int daio_mgr_put_ctrl_blk(void *blk)
1163{
1164 kfree((struct daio_mgr_ctrl_blk *)blk);
1165
1166 return 0;
1167}
1168
1169/* Card hardware initialization block */
1170struct dac_conf {
1171 unsigned int msr; /* master sample rate in rsrs */
1172};
1173
1174struct adc_conf {
1175 unsigned int msr; /* master sample rate in rsrs */
1176 unsigned char input; /* the input source of ADC */
1177 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1178};
1179
1180struct daio_conf {
1181 unsigned int msr; /* master sample rate in rsrs */
1182};
1183
1184struct trn_conf {
1185 unsigned long vm_pgt_phys;
1186};
1187
1188static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1189{
1190 u32 i2sorg = 0;
1191 u32 spdorg = 0;
1192
1193 /* Read I2S CTL. Keep original value. */
1194 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1195 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1196 /* Program I2S with proper master sample rate and enable
1197 * the correct I2S channel. */
1198 i2sorg &= 0xfffffffc;
1199
1200 /* Enable S/PDIF-out-A in fixed 24-bit data
1201 * format and default to 48kHz. */
1202 /* Disable all before doing any changes. */
1203 hw_write_20kx(hw, SPOCTL, 0x0);
1204 spdorg = 0x05;
1205
1206 switch (info->msr) {
1207 case 1:
1208 i2sorg |= 1;
1209 spdorg |= (0x0 << 6);
1210 break;
1211 case 2:
1212 i2sorg |= 2;
1213 spdorg |= (0x1 << 6);
1214 break;
1215 case 4:
1216 i2sorg |= 3;
1217 spdorg |= (0x2 << 6);
1218 break;
1219 default:
1220 i2sorg |= 1;
1221 break;
1222 }
1223
1224 hw_write_20kx(hw, I2SCTL, i2sorg);
1225 hw_write_20kx(hw, SPOCTL, spdorg);
1226
1227 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1228 /* Disable all before doing any changes. */
1229 hw_write_20kx(hw, SPICTL, 0x0);
1230 mdelay(1);
1231 spdorg = 0x0a0a0a0a;
1232 hw_write_20kx(hw, SPICTL, spdorg);
1233 mdelay(1);
1234
1235 return 0;
1236}
1237
1238/* TRANSPORT operations */
1239static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1240{
1241 u32 trnctl = 0;
1242 unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1243
1244 /* Set up device page table */
1245 if ((~0UL) == info->vm_pgt_phys) {
1246 printk(KERN_ERR "Wrong device page table page address!\n");
1247 return -1;
1248 }
1249
1250 trnctl = 0x13; /* 32-bit, 4k-size page */
1251#if BITS_PER_LONG == 64
1252 ptp_phys_low = info->vm_pgt_phys & ((1UL<<32)-1);
1253 ptp_phys_high = (info->vm_pgt_phys>>32) & ((1UL<<32)-1);
1254 trnctl |= (1<<2);
1255#elif BITS_PER_LONG == 32
1256 ptp_phys_low = info->vm_pgt_phys & (~0UL);
1257 ptp_phys_high = 0;
1258#else
1259# error "Unknown BITS_PER_LONG!"
1260#endif
1261#if PAGE_SIZE == 8192
1262 trnctl |= (1<<5);
1263#endif
1264 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1265 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1266 hw_write_20kx(hw, TRNCTL, trnctl);
1267 hw_write_20kx(hw, TRNIS, 0x200c01); /* realy needed? */
1268
1269 return 0;
1270}
1271
1272/* Card initialization */
1273#define GCTL_EAC 0x00000001
1274#define GCTL_EAI 0x00000002
1275#define GCTL_BEP 0x00000004
1276#define GCTL_BES 0x00000008
1277#define GCTL_DSP 0x00000010
1278#define GCTL_DBP 0x00000020
1279#define GCTL_ABP 0x00000040
1280#define GCTL_TBP 0x00000080
1281#define GCTL_SBP 0x00000100
1282#define GCTL_FBP 0x00000200
1283#define GCTL_XA 0x00000400
1284#define GCTL_ET 0x00000800
1285#define GCTL_PR 0x00001000
1286#define GCTL_MRL 0x00002000
1287#define GCTL_SDE 0x00004000
1288#define GCTL_SDI 0x00008000
1289#define GCTL_SM 0x00010000
1290#define GCTL_SR 0x00020000
1291#define GCTL_SD 0x00040000
1292#define GCTL_SE 0x00080000
1293#define GCTL_AID 0x00100000
1294
1295static int hw_pll_init(struct hw *hw, unsigned int rsr)
1296{
1297 unsigned int pllctl;
1298 int i = 0;
1299
1300 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1301 for (i = 0; i < 3; i++) {
1302 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1303 break;
1304
1305 hw_write_20kx(hw, PLLCTL, pllctl);
1306 mdelay(40);
1307 }
1308 if (i >= 3) {
1309 printk(KERN_ALERT "PLL initialization failed!!!\n");
1310 return -EBUSY;
1311 }
1312
1313 return 0;
1314}
1315
1316static int hw_auto_init(struct hw *hw)
1317{
1318 unsigned int gctl;
1319 int i;
1320
1321 gctl = hw_read_20kx(hw, GCTL);
1322 set_field(&gctl, GCTL_EAI, 0);
1323 hw_write_20kx(hw, GCTL, gctl);
1324 set_field(&gctl, GCTL_EAI, 1);
1325 hw_write_20kx(hw, GCTL, gctl);
1326 mdelay(10);
1327 for (i = 0; i < 400000; i++) {
1328 gctl = hw_read_20kx(hw, GCTL);
1329 if (get_field(gctl, GCTL_AID))
1330 break;
1331 }
1332 if (!get_field(gctl, GCTL_AID)) {
1333 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1334 return -EBUSY;
1335 }
1336
1337 return 0;
1338}
1339
1340static int i2c_unlock(struct hw *hw)
1341{
1342 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1343 return 0;
1344
1345 hw_write_pci(hw, 0xcc, 0x8c);
1346 hw_write_pci(hw, 0xcc, 0x0e);
1347 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1348 return 0;
1349
1350 hw_write_pci(hw, 0xcc, 0xee);
1351 hw_write_pci(hw, 0xcc, 0xaa);
1352 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1353 return 0;
1354
1355 return -1;
1356}
1357
1358static void i2c_lock(struct hw *hw)
1359{
1360 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1361 hw_write_pci(hw, 0xcc, 0x00);
1362}
1363
1364static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1365{
1366 unsigned int ret = 0;
1367
1368 do {
1369 ret = hw_read_pci(hw, 0xEC);
1370 } while (!(ret & 0x800000));
1371 hw_write_pci(hw, 0xE0, device);
1372 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1373}
1374
1375/* DAC operations */
1376
1377static int hw_reset_dac(struct hw *hw)
1378{
1379 u32 i = 0;
1380 u16 gpioorg = 0;
1381 unsigned int ret = 0;
1382
1383 if (i2c_unlock(hw))
1384 return -1;
1385
1386 do {
1387 ret = hw_read_pci(hw, 0xEC);
1388 } while (!(ret & 0x800000));
1389 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1390
1391 /* To be effective, need to reset the DAC twice. */
1392 for (i = 0; i < 2; i++) {
1393 /* set gpio */
1394 mdelay(100);
1395 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1396 gpioorg &= 0xfffd;
1397 hw_write_20kx(hw, GPIO, gpioorg);
1398 mdelay(1);
1399 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1400 }
1401
1402 i2c_write(hw, 0x00180080, 0x01, 0x80);
1403 i2c_write(hw, 0x00180080, 0x02, 0x10);
1404
1405 i2c_lock(hw);
1406
1407 return 0;
1408}
1409
1410static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1411{
1412 u32 data = 0;
1413 u16 gpioorg = 0;
1414 u16 subsys_id = 0;
1415 unsigned int ret = 0;
1416
1417 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1418 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1419 /* SB055x, unmute outputs */
1420 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1421 gpioorg &= 0xffbf; /* set GPIO6 to low */
1422 gpioorg |= 2; /* set GPIO1 to high */
1423 hw_write_20kx(hw, GPIO, gpioorg);
1424 return 0;
1425 }
1426
1427 /* mute outputs */
1428 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1429 gpioorg &= 0xffbf;
1430 hw_write_20kx(hw, GPIO, gpioorg);
1431
1432 hw_reset_dac(hw);
1433
1434 if (i2c_unlock(hw))
1435 return -1;
1436
1437 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1438 do {
1439 ret = hw_read_pci(hw, 0xEC);
1440 } while (!(ret & 0x800000));
1441
1442 switch (info->msr) {
1443 case 1:
1444 data = 0x24;
1445 break;
1446 case 2:
1447 data = 0x25;
1448 break;
1449 case 4:
1450 data = 0x26;
1451 break;
1452 default:
1453 data = 0x24;
1454 break;
1455 }
1456
1457 i2c_write(hw, 0x00180080, 0x06, data);
1458 i2c_write(hw, 0x00180080, 0x09, data);
1459 i2c_write(hw, 0x00180080, 0x0c, data);
1460 i2c_write(hw, 0x00180080, 0x0f, data);
1461
1462 i2c_lock(hw);
1463
1464 /* unmute outputs */
1465 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1466 gpioorg = gpioorg | 0x40;
1467 hw_write_20kx(hw, GPIO, gpioorg);
1468
1469 return 0;
1470}
1471
1472/* ADC operations */
1473
1474static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1475{
1476 u32 data = 0;
1477 return data;
1478}
1479
1480static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1481{
1482 u32 data = 0;
1483
1484 data = hw_read_20kx(hw, GPIO);
1485 switch (type) {
1486 case ADC_MICIN:
1487 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1488 break;
1489 case ADC_LINEIN:
1490 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1491 break;
1492 case ADC_NONE: /* Digital I/O */
1493 data = (!(data & (0x1<<8)));
1494 break;
1495 default:
1496 data = 0;
1497 }
1498 return data;
1499}
1500
1501static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1502{
1503 u32 data = 0;
1504
1505 data = hw_read_20kx(hw, GPIO);
1506 switch (type) {
1507 case ADC_MICIN:
1508 data = (data & (0x1 << 7)) ? 1 : 0;
1509 break;
1510 case ADC_LINEIN:
1511 data = (data & (0x1 << 7)) ? 0 : 1;
1512 break;
1513 default:
1514 data = 0;
1515 }
1516 return data;
1517}
1518
1519static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1520{
1521 u16 subsys_id = 0;
1522
1523 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1524 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1525 /* SB055x cards */
1526 return is_adc_input_selected_SB055x(hw, type);
1527 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
1528 /* SB073x cards */
1529 return is_adc_input_selected_hendrix(hw, type);
1530 } else if ((subsys_id & 0xf000) == 0x6000) {
1531 /* Vista compatible cards */
1532 return is_adc_input_selected_hendrix(hw, type);
1533 } else {
1534 return is_adc_input_selected_SBx(hw, type);
1535 }
1536}
1537
1538static int
1539adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1540{
1541 u32 data = 0;
1542
1543 /*
1544 * check and set the following GPIO bits accordingly
1545 * ADC_Gain = GPIO2
1546 * DRM_off = GPIO3
1547 * Mic_Pwr_on = GPIO7
1548 * Digital_IO_Sel = GPIO8
1549 * Mic_Sw = GPIO9
1550 * Aux/MicLine_Sw = GPIO12
1551 */
1552 data = hw_read_20kx(hw, GPIO);
1553 data &= 0xec73;
1554 switch (type) {
1555 case ADC_MICIN:
1556 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1557 data |= boost ? (0x1<<2) : 0;
1558 break;
1559 case ADC_LINEIN:
1560 data |= (0x1<<8);
1561 break;
1562 case ADC_AUX:
1563 data |= (0x1<<8) | (0x1<<12);
1564 break;
1565 case ADC_NONE:
1566 data |= (0x1<<12); /* set to digital */
1567 break;
1568 default:
1569 return -1;
1570 }
1571
1572 hw_write_20kx(hw, GPIO, data);
1573
1574 return 0;
1575}
1576
1577
1578static int
1579adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1580{
1581 u32 data = 0;
1582 u32 i2c_data = 0;
1583 unsigned int ret = 0;
1584
1585 if (i2c_unlock(hw))
1586 return -1;
1587
1588 do {
1589 ret = hw_read_pci(hw, 0xEC);
1590 } while (!(ret & 0x800000)); /* i2c ready poll */
1591 /* set i2c access mode as Direct Control */
1592 hw_write_pci(hw, 0xEC, 0x05);
1593
1594 data = hw_read_20kx(hw, GPIO);
1595 switch (type) {
1596 case ADC_MICIN:
1597 data |= ((0x1 << 7) | (0x1 << 8));
1598 i2c_data = 0x1; /* Mic-in */
1599 break;
1600 case ADC_LINEIN:
1601 data &= ~(0x1 << 7);
1602 data |= (0x1 << 8);
1603 i2c_data = 0x2; /* Line-in */
1604 break;
1605 case ADC_NONE:
1606 data &= ~(0x1 << 8);
1607 i2c_data = 0x0; /* set to Digital */
1608 break;
1609 default:
1610 i2c_lock(hw);
1611 return -1;
1612 }
1613 hw_write_20kx(hw, GPIO, data);
1614 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1615 if (boost) {
1616 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1617 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1618 } else {
1619 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1620 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1621 }
1622
1623 i2c_lock(hw);
1624
1625 return 0;
1626}
1627
1628static int
1629adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1630{
1631 u32 data = 0;
1632 u32 i2c_data = 0;
1633 unsigned int ret = 0;
1634
1635 if (i2c_unlock(hw))
1636 return -1;
1637
1638 do {
1639 ret = hw_read_pci(hw, 0xEC);
1640 } while (!(ret & 0x800000)); /* i2c ready poll */
1641 /* set i2c access mode as Direct Control */
1642 hw_write_pci(hw, 0xEC, 0x05);
1643
1644 data = hw_read_20kx(hw, GPIO);
1645 switch (type) {
1646 case ADC_MICIN:
1647 data |= (0x1 << 7);
1648 i2c_data = 0x1; /* Mic-in */
1649 break;
1650 case ADC_LINEIN:
1651 data &= ~(0x1 << 7);
1652 i2c_data = 0x2; /* Line-in */
1653 break;
1654 default:
1655 i2c_lock(hw);
1656 return -1;
1657 }
1658 hw_write_20kx(hw, GPIO, data);
1659 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1660 if (boost) {
1661 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1662 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1663 } else {
1664 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1665 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1666 }
1667
1668 i2c_lock(hw);
1669
1670 return 0;
1671}
1672
1673static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1674{
1675 u16 subsys_id = 0;
1676
1677 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1678 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1679 /* SB055x cards */
1680 return adc_input_select_SB055x(hw, type, (ADC_MICIN == type));
1681 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
1682 /* SB073x cards */
1683 return adc_input_select_hendrix(hw, type, (ADC_MICIN == type));
1684 } else if ((subsys_id & 0xf000) == 0x6000) {
1685 /* Vista compatible cards */
1686 return adc_input_select_hendrix(hw, type, (ADC_MICIN == type));
1687 } else {
1688 return adc_input_select_SBx(hw, type, (ADC_MICIN == type));
1689 }
1690}
1691
1692static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1693{
1694 return adc_input_select_SB055x(hw, input, mic20db);
1695}
1696
1697static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1698{
1699 u16 gpioorg;
1700 u16 input_source;
1701 u32 adcdata = 0;
1702 unsigned int ret = 0;
1703
1704 input_source = 0x100; /* default to analog */
1705 switch (input) {
1706 case ADC_MICIN:
1707 adcdata = 0x1;
1708 input_source = 0x180; /* set GPIO7 to select Mic */
1709 break;
1710 case ADC_LINEIN:
1711 adcdata = 0x2;
1712 break;
1713 case ADC_VIDEO:
1714 adcdata = 0x4;
1715 break;
1716 case ADC_AUX:
1717 adcdata = 0x8;
1718 break;
1719 case ADC_NONE:
1720 adcdata = 0x0;
1721 input_source = 0x0; /* set to Digital */
1722 break;
1723 default:
1724 break;
1725 }
1726
1727 if (i2c_unlock(hw))
1728 return -1;
1729
1730 do {
1731 ret = hw_read_pci(hw, 0xEC);
1732 } while (!(ret & 0x800000)); /* i2c ready poll */
1733 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1734
1735 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1736 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1737 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1738 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1739
1740 if (mic20db) {
1741 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1742 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1743 } else {
1744 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1745 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1746 }
1747
1748 if (!(hw_read_20kx(hw, ID0) & 0x100))
1749 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1750
1751 i2c_lock(hw);
1752
1753 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1754 gpioorg &= 0xfe7f;
1755 gpioorg |= input_source;
1756 hw_write_20kx(hw, GPIO, gpioorg);
1757
1758 return 0;
1759}
1760
1761static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1762{
1763 int err = 0;
1764 u16 subsys_id = 0;
1765
1766 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1767 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
1768 /* Sb055x card */
1769 err = adc_init_SB055x(hw, info->input, info->mic20db);
1770 } else {
1771 err = adc_init_SBx(hw, info->input, info->mic20db);
1772 }
1773
1774 return err;
1775}
1776
1777static int hw_have_digit_io_switch(struct hw *hw)
1778{
1779 u16 subsys_id = 0;
1780
1781 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
1782 /* SB073x and Vista compatible cards have no digit IO switch */
1783 return !((subsys_id == 0x0029) || (subsys_id == 0x0031)
1784 || ((subsys_id & 0xf000) == 0x6000));
1785}
1786
1787#define UAA_CFG_PWRSTATUS 0x44
1788#define UAA_CFG_SPACE_FLAG 0xA0
1789#define UAA_CORE_CHANGE 0x3FFC
1790static int uaa_to_xfi(struct pci_dev *pci)
1791{
1792 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1793 unsigned int cmd, irq, cl_size, l_timer, pwr;
1794 unsigned int CTLA, CTLZ, CTLL, CTLX, CTL_, CTLF, CTLi;
1795 unsigned int is_uaa = 0;
1796 unsigned int data[4] = {0};
1797 unsigned int io_base;
1798 void *mem_base;
1799 int i = 0;
1800
1801 /* By default, Hendrix card UAA Bar0 should be using memory... */
1802 io_base = pci_resource_start(pci, 0);
1803 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1804 if (NULL == mem_base)
1805 return -ENOENT;
1806
1807 CTLX = ___constant_swab32(*((unsigned int *)"CTLX"));
1808 CTL_ = ___constant_swab32(*((unsigned int *)"CTL-"));
1809 CTLF = ___constant_swab32(*((unsigned int *)"CTLF"));
1810 CTLi = ___constant_swab32(*((unsigned int *)"CTLi"));
1811 CTLA = ___constant_swab32(*((unsigned int *)"CTLA"));
1812 CTLZ = ___constant_swab32(*((unsigned int *)"CTLZ"));
1813 CTLL = ___constant_swab32(*((unsigned int *)"CTLL"));
1814
1815 /* Read current mode from Mode Change Register */
1816 for (i = 0; i < 4; i++)
1817 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1818
1819 /* Determine current mode... */
1820 if (data[0] == CTLA) {
1821 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1822 && data[3] == CTLA) || (data[1] == CTLA
1823 && data[2] == CTLZ && data[3] == CTLL));
1824 } else if (data[0] == CTLZ) {
1825 is_uaa = (data[1] == CTLL
1826 && data[2] == CTLA && data[3] == CTLA);
1827 } else if (data[0] == CTLL) {
1828 is_uaa = (data[1] == CTLA
1829 && data[2] == CTLA && data[3] == CTLZ);
1830 } else {
1831 is_uaa = 0;
1832 }
1833
1834 if (!is_uaa) {
1835 /* Not in UAA mode currently. Return directly. */
1836 iounmap(mem_base);
1837 return 0;
1838 }
1839
1840 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1843 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1844 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1845 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1846 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1847 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1848 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1849 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1850 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1851
1852 /* Set up X-Fi core PCI configuration space. */
1853 /* Switch to X-Fi config space with BAR0 exposed. */
1854 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1855 /* Copy UAA's BAR5 into X-Fi BAR0 */
1856 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1857 /* Switch to X-Fi config space without BAR0 exposed. */
1858 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1859 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1861 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1863 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1864 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1865 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1866 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1867 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1868
1869 /* Switch to X-Fi mode */
1870 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1871 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1872 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1873 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1874
1875 iounmap(mem_base);
1876
1877 return 0;
1878}
1879
1880static int hw_card_start(struct hw *hw)
1881{
1882 int err = 0;
1883 struct pci_dev *pci = hw->pci;
1884 u16 subsys_id = 0;
1885 unsigned int dma_mask = 0;
1886
1887 err = pci_enable_device(pci);
1888 if (err < 0)
1889 return err;
1890
1891 /* Set DMA transfer mask */
1892 dma_mask = CT_XFI_DMA_MASK;
1893 if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1894 pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1895 printk(KERN_ERR "architecture does not support PCI "
1896 "busmaster DMA with mask 0x%x\n", dma_mask);
1897 err = -ENXIO;
1898 goto error1;
1899 }
1900
1901 err = pci_request_regions(pci, "XFi");
1902 if (err < 0)
1903 goto error1;
1904
1905 /* Switch to X-Fi mode from UAA mode if neeeded */
1906 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &subsys_id);
1907 if ((0x5 == pci->device) && (0x6000 == (subsys_id & 0x6000))) {
1908 err = uaa_to_xfi(pci);
1909 if (err)
1910 goto error2;
1911
1912 hw->io_base = pci_resource_start(pci, 5);
1913 } else {
1914 hw->io_base = pci_resource_start(pci, 0);
1915 }
1916
1917 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1918 atc->chip_details->nm_card, hw))) {
1919 goto error2;
1920 }
1921 hw->irq = pci->irq;
1922 */
1923
1924 pci_set_master(pci);
1925
1926 return 0;
1927
1928error2:
1929 pci_release_regions(pci);
1930 hw->io_base = 0;
1931error1:
1932 pci_disable_device(pci);
1933 return err;
1934}
1935
1936static int hw_card_stop(struct hw *hw)
1937{
1938 /* TODO: Disable interrupt and so on... */
1939 return 0;
1940}
1941
1942static int hw_card_shutdown(struct hw *hw)
1943{
1944 if (hw->irq >= 0)
1945 free_irq(hw->irq, hw);
1946
1947 hw->irq = -1;
1948
1949 if (NULL != ((void *)hw->mem_base))
1950 iounmap((void *)hw->mem_base);
1951
1952 hw->mem_base = (unsigned long)NULL;
1953
1954 if (hw->io_base)
1955 pci_release_regions(hw->pci);
1956
1957 hw->io_base = 0;
1958
1959 pci_disable_device(hw->pci);
1960
1961 return 0;
1962}
1963
1964static int hw_card_init(struct hw *hw, struct card_conf *info)
1965{
1966 int err;
1967 unsigned int gctl;
1968 u16 subsys_id = 0;
1969 u32 data = 0;
1970 struct dac_conf dac_info = {0};
1971 struct adc_conf adc_info = {0};
1972 struct daio_conf daio_info = {0};
1973 struct trn_conf trn_info = {0};
1974
1975 /* Get PCI io port base address and do Hendrix switch if needed. */
1976 if (!hw->io_base) {
1977 err = hw_card_start(hw);
1978 if (err)
1979 return err;
1980 }
1981
1982 /* PLL init */
1983 err = hw_pll_init(hw, info->rsr);
1984 if (err < 0)
1985 return err;
1986
1987 /* kick off auto-init */
1988 err = hw_auto_init(hw);
1989 if (err < 0)
1990 return err;
1991
1992 /* Enable audio ring */
1993 gctl = hw_read_20kx(hw, GCTL);
1994 set_field(&gctl, GCTL_EAC, 1);
1995 set_field(&gctl, GCTL_DBP, 1);
1996 set_field(&gctl, GCTL_TBP, 1);
1997 set_field(&gctl, GCTL_FBP, 1);
1998 set_field(&gctl, GCTL_ET, 1);
1999 hw_write_20kx(hw, GCTL, gctl);
2000 mdelay(10);
2001
2002 /* Reset all global pending interrupts */
2003 hw_write_20kx(hw, GIE, 0);
2004 /* Reset all SRC pending interrupts */
2005 hw_write_20kx(hw, SRCIP, 0);
2006 mdelay(30);
2007
2008 pci_read_config_word(hw->pci, PCI_SUBSYSTEM_ID, &subsys_id);
2009 /* Detect the card ID and configure GPIO accordingly. */
2010 if ((subsys_id == 0x0022) || (subsys_id == 0x002F)) {
2011 /* SB055x cards */
2012 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2013 } else if ((subsys_id == 0x0029) || (subsys_id == 0x0031)) {
2014 /* SB073x cards */
2015 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2016 } else if ((subsys_id & 0xf000) == 0x6000) {
2017 /* Vista compatible cards */
2018 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2019 } else {
2020 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2021 }
2022
2023 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2024 err = hw_trn_init(hw, &trn_info);
2025 if (err < 0)
2026 return err;
2027
2028 daio_info.msr = info->msr;
2029 err = hw_daio_init(hw, &daio_info);
2030 if (err < 0)
2031 return err;
2032
2033 dac_info.msr = info->msr;
2034 err = hw_dac_init(hw, &dac_info);
2035 if (err < 0)
2036 return err;
2037
2038 adc_info.msr = info->msr;
2039 adc_info.input = ADC_LINEIN;
2040 adc_info.mic20db = 0;
2041 err = hw_adc_init(hw, &adc_info);
2042 if (err < 0)
2043 return err;
2044
2045 data = hw_read_20kx(hw, SRCMCTL);
2046 data |= 0x1; /* Enables input from the audio ring */
2047 hw_write_20kx(hw, SRCMCTL, data);
2048
2049 return 0;
2050}
2051
2052static u32 hw_read_20kx(struct hw *hw, u32 reg)
2053{
2054 u32 value;
2055 unsigned long flags;
2056
2057 spin_lock_irqsave(
2058 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2059 outl(reg, hw->io_base + 0x0);
2060 value = inl(hw->io_base + 0x4);
2061 spin_unlock_irqrestore(
2062 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2063
2064 return value;
2065}
2066
2067static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2068{
2069 unsigned long flags;
2070
2071 spin_lock_irqsave(
2072 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2073 outl(reg, hw->io_base + 0x0);
2074 outl(data, hw->io_base + 0x4);
2075 spin_unlock_irqrestore(
2076 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2077
2078}
2079
2080static u32 hw_read_pci(struct hw *hw, u32 reg)
2081{
2082 u32 value;
2083 unsigned long flags;
2084
2085 spin_lock_irqsave(
2086 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2087 outl(reg, hw->io_base + 0x10);
2088 value = inl(hw->io_base + 0x14);
2089 spin_unlock_irqrestore(
2090 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2091
2092 return value;
2093}
2094
2095static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2096{
2097 unsigned long flags;
2098
2099 spin_lock_irqsave(
2100 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2101 outl(reg, hw->io_base + 0x10);
2102 outl(data, hw->io_base + 0x14);
2103 spin_unlock_irqrestore(
2104 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2105}
2106
2107int create_20k1_hw_obj(struct hw **rhw)
2108{
2109 struct hw *hw;
2110 struct hw20k1 *hw20k1;
2111
2112 *rhw = NULL;
2113 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2114 if (NULL == hw20k1)
2115 return -ENOMEM;
2116
2117 spin_lock_init(&hw20k1->reg_20k1_lock);
2118 spin_lock_init(&hw20k1->reg_pci_lock);
2119
2120 hw = &hw20k1->hw;
2121
2122 hw->io_base = 0;
2123 hw->mem_base = (unsigned long)NULL;
2124 hw->irq = -1;
2125
2126 hw->card_init = hw_card_init;
2127 hw->card_stop = hw_card_stop;
2128 hw->pll_init = hw_pll_init;
2129 hw->is_adc_source_selected = hw_is_adc_input_selected;
2130 hw->select_adc_source = hw_adc_input_select;
2131 hw->have_digit_io_switch = hw_have_digit_io_switch;
2132
2133 hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2134 hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2135 hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2136 hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2137 hw->src_set_state = src_set_state;
2138 hw->src_set_bm = src_set_bm;
2139 hw->src_set_rsr = src_set_rsr;
2140 hw->src_set_sf = src_set_sf;
2141 hw->src_set_wr = src_set_wr;
2142 hw->src_set_pm = src_set_pm;
2143 hw->src_set_rom = src_set_rom;
2144 hw->src_set_vo = src_set_vo;
2145 hw->src_set_st = src_set_st;
2146 hw->src_set_ie = src_set_ie;
2147 hw->src_set_ilsz = src_set_ilsz;
2148 hw->src_set_bp = src_set_bp;
2149 hw->src_set_cisz = src_set_cisz;
2150 hw->src_set_ca = src_set_ca;
2151 hw->src_set_sa = src_set_sa;
2152 hw->src_set_la = src_set_la;
2153 hw->src_set_pitch = src_set_pitch;
2154 hw->src_set_dirty = src_set_dirty;
2155 hw->src_set_clear_zbufs = src_set_clear_zbufs;
2156 hw->src_set_dirty_all = src_set_dirty_all;
2157 hw->src_commit_write = src_commit_write;
2158 hw->src_get_ca = src_get_ca;
2159 hw->src_get_dirty = src_get_dirty;
2160 hw->src_dirty_conj_mask = src_dirty_conj_mask;
2161 hw->src_mgr_enbs_src = src_mgr_enbs_src;
2162 hw->src_mgr_enb_src = src_mgr_enb_src;
2163 hw->src_mgr_dsb_src = src_mgr_dsb_src;
2164 hw->src_mgr_commit_write = src_mgr_commit_write;
2165
2166 hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2167 hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2168 hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2169 hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2170 hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2171 hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2172 hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2173
2174 hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2175 hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2176 hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2177 hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2178 hw->amixer_set_mode = amixer_set_mode;
2179 hw->amixer_set_iv = amixer_set_iv;
2180 hw->amixer_set_x = amixer_set_x;
2181 hw->amixer_set_y = amixer_set_y;
2182 hw->amixer_set_sadr = amixer_set_sadr;
2183 hw->amixer_set_se = amixer_set_se;
2184 hw->amixer_set_dirty = amixer_set_dirty;
2185 hw->amixer_set_dirty_all = amixer_set_dirty_all;
2186 hw->amixer_commit_write = amixer_commit_write;
2187 hw->amixer_get_y = amixer_get_y;
2188 hw->amixer_get_dirty = amixer_get_dirty;
2189
2190 hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2191 hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2192 hw->dai_srt_set_srco = dai_srt_set_srcr;
2193 hw->dai_srt_set_srcm = dai_srt_set_srcl;
2194 hw->dai_srt_set_rsr = dai_srt_set_rsr;
2195 hw->dai_srt_set_drat = dai_srt_set_drat;
2196 hw->dai_srt_set_ec = dai_srt_set_ec;
2197 hw->dai_srt_set_et = dai_srt_set_et;
2198 hw->dai_commit_write = dai_commit_write;
2199
2200 hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2201 hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2202 hw->dao_set_spos = dao_set_spos;
2203 hw->dao_commit_write = dao_commit_write;
2204 hw->dao_get_spos = dao_get_spos;
2205
2206 hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2207 hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2208 hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2209 hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2210 hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2211 hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2212 hw->daio_mgr_dao_init = daio_mgr_dao_init;
2213 hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2214 hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2215 hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2216 hw->daio_mgr_commit_write = daio_mgr_commit_write;
2217
2218 *rhw = hw;
2219
2220 return 0;
2221}
2222
2223int destroy_20k1_hw_obj(struct hw *hw)
2224{
2225 if (hw->io_base)
2226 hw_card_shutdown(hw);
2227
2228 kfree(container_of(hw, struct hw20k1, hw));
2229 return 0;
2230}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 20:19:09 -0500