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-rw-r--r--sound/pci/cs4281.c2136
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diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c
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1/*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/moduleparam.h>
31#include <sound/core.h>
32#include <sound/control.h>
33#include <sound/pcm.h>
34#include <sound/rawmidi.h>
35#include <sound/ac97_codec.h>
36#include <sound/opl3.h>
37#include <sound/initval.h>
38
39
40MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41MODULE_DESCRIPTION("Cirrus Logic CS4281");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
47static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
48static int dual_codec[SNDRV_CARDS]; /* dual codec */
49
50module_param_array(index, int, NULL, 0444);
51MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52module_param_array(id, charp, NULL, 0444);
53MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54module_param_array(enable, bool, NULL, 0444);
55MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56module_param_array(dual_codec, bool, NULL, 0444);
57MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
59/*
60 *
61 */
62
63#ifndef PCI_VENDOR_ID_CIRRUS
64#define PCI_VENDOR_ID_CIRRUS 0x1013
65#endif
66#ifndef PCI_DEVICE_ID_CIRRUS_4281
67#define PCI_DEVICE_ID_CIRRUS_4281 0x6005
68#endif
69
70/*
71 * Direct registers
72 */
73
74#define CS4281_BA0_SIZE 0x1000
75#define CS4281_BA1_SIZE 0x10000
76
77/*
78 * BA0 registers
79 */
80#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
81#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
82#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
83#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
84#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
85#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
86#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
87#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
88#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
89#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
90#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
91#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
92#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
93
94#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
95#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
96#define BA0_HICR_IEV (1<<0) /* INTENA Value */
97#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
98
99#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
100 /* Use same contants as for BA0_HISR */
101
102#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
103
104#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
105#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
106#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
107#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
108
109#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
110#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
111#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
112#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
113#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
114#define BA0_HDSR_RQ (1<<7) /* Pending Request */
115
116#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
117#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
118#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
119#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
120#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
121#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
122#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
123#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
124#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
125#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
126#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
127#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
128#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
129#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
130#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
131#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
132#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
133#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
134#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
135#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
136#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
137#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
138#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
139#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
140
141#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
142#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
143#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
144#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
145#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
146#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
147#define BA0_DMR_USIGN (1<<19) /* Unsigned */
148#define BA0_DMR_BEND (1<<18) /* Big Endian */
149#define BA0_DMR_MONO (1<<17) /* Mono */
150#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
151#define BA0_DMR_TYPE_DEMAND (0<<6)
152#define BA0_DMR_TYPE_SINGLE (1<<6)
153#define BA0_DMR_TYPE_BLOCK (2<<6)
154#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
155#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
156#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
157#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
158#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
159#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
160
161#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
162#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
163#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
164
165#define BA0_FCR0 0x0180 /* FIFO Control 0 */
166#define BA0_FCR1 0x0184 /* FIFO Control 1 */
167#define BA0_FCR2 0x0188 /* FIFO Control 2 */
168#define BA0_FCR3 0x018c /* FIFO Control 3 */
169
170#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
171#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
172#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
173#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
174#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
175#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
176#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
177
178#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
179#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
180#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
181#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
182
183#define BA0_FCHS 0x020c /* FIFO Channel Status */
184#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
185#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
186#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
187#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
188#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
189#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
190#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
191#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
192
193#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
194#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
195#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
196#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
197
198#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
199#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
200#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
201#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
202#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
203#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
204#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
205#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
206
207#define BA0_PMCS 0x0344 /* Power Management Control/Status */
208#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
209#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
210#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
211
212#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
213#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
214#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
215#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
216#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
217#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
218#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
219#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
220#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
221#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
222
223#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
224#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
225#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
226#define BA0_TMS 0x03f8 /* Test Register */
227#define BA0_SSVID 0x03fc /* Subsystem ID register */
228
229#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
230#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
231#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
232#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
233#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
234#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
235#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
236
237#define BA0_FRR 0x0410 /* Feature Reporting Register */
238#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
239
240#define BA0_SERMC 0x0420 /* Serial Port Master Control */
241#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
242#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
243#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
244#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
245#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
246#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
247#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
248#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
249#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
250#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
251#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
252#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
253
254#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
255#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
256#define BA0_SERC1_AC97 (1<<1)
257#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
258
259#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
260#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
261#define BA0_SERC2_AC97 (1<<1)
262#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
263
264#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
265
266#define BA0_ACCTL 0x0460 /* AC'97 Control */
267#define BA0_ACCTL_TC (1<<6) /* Target Codec */
268#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
269#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
270#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
271#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
272
273#define BA0_ACSTS 0x0464 /* AC'97 Status */
274#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
275#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
276
277#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
278#define BA0_ACOSV_SLV(x) (1<<((x)-3))
279
280#define BA0_ACCAD 0x046c /* AC'97 Command Address */
281#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
282
283#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
284#define BA0_ACISV_SLV(x) (1<<((x)-3))
285
286#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
287#define BA0_ACSDA 0x047c /* AC'97 Status Data */
288#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
289#define BA0_JSCTL 0x0484 /* Joystick control */
290#define BA0_JSC1 0x0488 /* Joystick control */
291#define BA0_JSC2 0x048c /* Joystick control */
292#define BA0_JSIO 0x04a0
293
294#define BA0_MIDCR 0x0490 /* MIDI Control */
295#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
296#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
297#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
298#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
299#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
300#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
301
302#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
303
304#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
305#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
306#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
307#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
308#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
309
310#define BA0_MIDWP 0x0498 /* MIDI Write */
311#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
312
313#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
314#define BA0_AODSD1_NDS(x) (1<<((x)-3))
315
316#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
317#define BA0_AODSD2_NDS(x) (1<<((x)-3))
318
319#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
320#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
321#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
322#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
323#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
324#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
325#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
326#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
327#define BA0_FMDP 0x0734 /* FM Data Port */
328#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
329#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
330
331#define BA0_SSPM 0x0740 /* Sound System Power Management */
332#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
333#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
334#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
335#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
336#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
337#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
338
339#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
340#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
341
342#define BA0_SSCR 0x074c /* Sound System Control Register */
343#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
344#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
345#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
346#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
347#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
348#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
349#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
350#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
351#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
352
353#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
354#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
355#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
356#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
357#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
358#define BA0_PASR 0x0768 /* playback sample rate */
359#define BA0_CASR 0x076C /* capture sample rate */
360
361/* Source Slot Numbers - Playback */
362#define SRCSLOT_LEFT_PCM_PLAYBACK 0
363#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
364#define SRCSLOT_PHONE_LINE_1_DAC 2
365#define SRCSLOT_CENTER_PCM_PLAYBACK 3
366#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
367#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
368#define SRCSLOT_LFE_PCM_PLAYBACK 6
369#define SRCSLOT_PHONE_LINE_2_DAC 7
370#define SRCSLOT_HEADSET_DAC 8
371#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
372#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
373
374/* Source Slot Numbers - Capture */
375#define SRCSLOT_LEFT_PCM_RECORD 10
376#define SRCSLOT_RIGHT_PCM_RECORD 11
377#define SRCSLOT_PHONE_LINE_1_ADC 12
378#define SRCSLOT_MIC_ADC 13
379#define SRCSLOT_PHONE_LINE_2_ADC 17
380#define SRCSLOT_HEADSET_ADC 18
381#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
382#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
383#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
384#define SRCSLOT_SECONDARY_MIC_ADC 23
385#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
386#define SRCSLOT_SECONDARY_HEADSET_ADC 28
387
388/* Source Slot Numbers - Others */
389#define SRCSLOT_POWER_DOWN 31
390
391/* MIDI modes */
392#define CS4281_MODE_OUTPUT (1<<0)
393#define CS4281_MODE_INPUT (1<<1)
394
395/* joystick bits */
396/* Bits for JSPT */
397#define JSPT_CAX 0x00000001
398#define JSPT_CAY 0x00000002
399#define JSPT_CBX 0x00000004
400#define JSPT_CBY 0x00000008
401#define JSPT_BA1 0x00000010
402#define JSPT_BA2 0x00000020
403#define JSPT_BB1 0x00000040
404#define JSPT_BB2 0x00000080
405
406/* Bits for JSCTL */
407#define JSCTL_SP_MASK 0x00000003
408#define JSCTL_SP_SLOW 0x00000000
409#define JSCTL_SP_MEDIUM_SLOW 0x00000001
410#define JSCTL_SP_MEDIUM_FAST 0x00000002
411#define JSCTL_SP_FAST 0x00000003
412#define JSCTL_ARE 0x00000004
413
414/* Data register pairs masks */
415#define JSC1_Y1V_MASK 0x0000FFFF
416#define JSC1_X1V_MASK 0xFFFF0000
417#define JSC1_Y1V_SHIFT 0
418#define JSC1_X1V_SHIFT 16
419#define JSC2_Y2V_MASK 0x0000FFFF
420#define JSC2_X2V_MASK 0xFFFF0000
421#define JSC2_Y2V_SHIFT 0
422#define JSC2_X2V_SHIFT 16
423
424/* JS GPIO */
425#define JSIO_DAX 0x00000001
426#define JSIO_DAY 0x00000002
427#define JSIO_DBX 0x00000004
428#define JSIO_DBY 0x00000008
429#define JSIO_AXOE 0x00000010
430#define JSIO_AYOE 0x00000020
431#define JSIO_BXOE 0x00000040
432#define JSIO_BYOE 0x00000080
433
434/*
435 *
436 */
437
438typedef struct snd_cs4281 cs4281_t;
439typedef struct snd_cs4281_dma cs4281_dma_t;
440
441struct snd_cs4281_dma {
442 snd_pcm_substream_t *substream;
443 unsigned int regDBA; /* offset to DBA register */
444 unsigned int regDCA; /* offset to DCA register */
445 unsigned int regDBC; /* offset to DBC register */
446 unsigned int regDCC; /* offset to DCC register */
447 unsigned int regDMR; /* offset to DMR register */
448 unsigned int regDCR; /* offset to DCR register */
449 unsigned int regHDSR; /* offset to HDSR register */
450 unsigned int regFCR; /* offset to FCR register */
451 unsigned int regFSIC; /* offset to FSIC register */
452 unsigned int valDMR; /* DMA mode */
453 unsigned int valDCR; /* DMA command */
454 unsigned int valFCR; /* FIFO control */
455 unsigned int fifo_offset; /* FIFO offset within BA1 */
456 unsigned char left_slot; /* FIFO left slot */
457 unsigned char right_slot; /* FIFO right slot */
458 int frag; /* period number */
459};
460
461#define SUSPEND_REGISTERS 20
462
463struct snd_cs4281 {
464 int irq;
465
466 void __iomem *ba0; /* virtual (accessible) address */
467 void __iomem *ba1; /* virtual (accessible) address */
468 unsigned long ba0_addr;
469 unsigned long ba1_addr;
470
471 int dual_codec;
472
473 ac97_bus_t *ac97_bus;
474 ac97_t *ac97;
475 ac97_t *ac97_secondary;
476
477 struct pci_dev *pci;
478 snd_card_t *card;
479 snd_pcm_t *pcm;
480 snd_rawmidi_t *rmidi;
481 snd_rawmidi_substream_t *midi_input;
482 snd_rawmidi_substream_t *midi_output;
483
484 cs4281_dma_t dma[4];
485
486 unsigned char src_left_play_slot;
487 unsigned char src_right_play_slot;
488 unsigned char src_left_rec_slot;
489 unsigned char src_right_rec_slot;
490
491 unsigned int spurious_dhtc_irq;
492 unsigned int spurious_dtc_irq;
493
494 spinlock_t reg_lock;
495 unsigned int midcr;
496 unsigned int uartm;
497
498 struct gameport *gameport;
499
500#ifdef CONFIG_PM
501 u32 suspend_regs[SUSPEND_REGISTERS];
502#endif
503
504};
505
506static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
507
508static struct pci_device_id snd_cs4281_ids[] = {
509 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
510 { 0, }
511};
512
513MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
514
515/*
516 * constants
517 */
518
519#define CS4281_FIFO_SIZE 32
520
521/*
522 * common I/O routines
523 */
524
525static void snd_cs4281_delay(unsigned int delay)
526{
527 if (delay > 999) {
528 unsigned long end_time;
529 delay = (delay * HZ) / 1000000;
530 if (delay < 1)
531 delay = 1;
532 end_time = jiffies + delay;
533 do {
534 set_current_state(TASK_UNINTERRUPTIBLE);
535 schedule_timeout(1);
536 } while (time_after_eq(end_time, jiffies));
537 } else {
538 udelay(delay);
539 }
540}
541
542inline static void snd_cs4281_delay_long(void)
543{
544 set_current_state(TASK_UNINTERRUPTIBLE);
545 schedule_timeout(1);
546}
547
548static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
549{
550 writel(val, chip->ba0 + offset);
551}
552
553static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
554{
555 return readl(chip->ba0 + offset);
556}
557
558static void snd_cs4281_ac97_write(ac97_t *ac97,
559 unsigned short reg, unsigned short val)
560{
561 /*
562 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
563 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
564 * 3. Write ACCTL = Control Register = 460h for initiating the write
565 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
566 * 5. if DCV not cleared, break and return error
567 */
568 cs4281_t *chip = ac97->private_data;
569 int count;
570
571 /*
572 * Setup the AC97 control registers on the CS461x to send the
573 * appropriate command to the AC97 to perform the read.
574 * ACCAD = Command Address Register = 46Ch
575 * ACCDA = Command Data Register = 470h
576 * ACCTL = Control Register = 460h
577 * set DCV - will clear when process completed
578 * reset CRW - Write command
579 * set VFRM - valid frame enabled
580 * set ESYN - ASYNC generation enabled
581 * set RSTN - ARST# inactive, AC97 codec not reset
582 */
583 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
584 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
585 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
586 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
587 for (count = 0; count < 2000; count++) {
588 /*
589 * First, we want to wait for a short time.
590 */
591 udelay(10);
592 /*
593 * Now, check to see if the write has completed.
594 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
595 */
596 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
597 return;
598 }
599 }
600 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
601}
602
603static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
604 unsigned short reg)
605{
606 cs4281_t *chip = ac97->private_data;
607 int count;
608 unsigned short result;
609 // FIXME: volatile is necessary in the following due to a bug of
610 // some gcc versions
611 volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
612
613 /*
614 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
615 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
616 * 3. Write ACCTL = Control Register = 460h for initiating the write
617 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
618 * 5. if DCV not cleared, break and return error
619 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
620 */
621
622 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
623
624 /*
625 * Setup the AC97 control registers on the CS461x to send the
626 * appropriate command to the AC97 to perform the read.
627 * ACCAD = Command Address Register = 46Ch
628 * ACCDA = Command Data Register = 470h
629 * ACCTL = Control Register = 460h
630 * set DCV - will clear when process completed
631 * set CRW - Read command
632 * set VFRM - valid frame enabled
633 * set ESYN - ASYNC generation enabled
634 * set RSTN - ARST# inactive, AC97 codec not reset
635 */
636
637 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
638 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
639 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
640 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
641 (ac97_num ? BA0_ACCTL_TC : 0));
642
643
644 /*
645 * Wait for the read to occur.
646 */
647 for (count = 0; count < 500; count++) {
648 /*
649 * First, we want to wait for a short time.
650 */
651 udelay(10);
652 /*
653 * Now, check to see if the read has completed.
654 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
655 */
656 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
657 goto __ok1;
658 }
659
660 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
661 result = 0xffff;
662 goto __end;
663
664 __ok1:
665 /*
666 * Wait for the valid status bit to go active.
667 */
668 for (count = 0; count < 100; count++) {
669 /*
670 * Read the AC97 status register.
671 * ACSTS = Status Register = 464h
672 * VSTS - Valid Status
673 */
674 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
675 goto __ok2;
676 udelay(10);
677 }
678
679 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
680 result = 0xffff;
681 goto __end;
682
683 __ok2:
684 /*
685 * Read the data returned from the AC97 register.
686 * ACSDA = Status Data Register = 474h
687 */
688 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
689
690 __end:
691 return result;
692}
693
694/*
695 * PCM part
696 */
697
698static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
699{
700 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
701 cs4281_t *chip = snd_pcm_substream_chip(substream);
702
703 spin_lock(&chip->reg_lock);
704 switch (cmd) {
705 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
706 dma->valDCR |= BA0_DCR_MSK;
707 dma->valFCR |= BA0_FCR_FEN;
708 break;
709 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
710 dma->valDCR &= ~BA0_DCR_MSK;
711 dma->valFCR &= ~BA0_FCR_FEN;
712 break;
713 case SNDRV_PCM_TRIGGER_START:
714 case SNDRV_PCM_TRIGGER_RESUME:
715 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
716 dma->valDMR |= BA0_DMR_DMA;
717 dma->valDCR &= ~BA0_DCR_MSK;
718 dma->valFCR |= BA0_FCR_FEN;
719 break;
720 case SNDRV_PCM_TRIGGER_STOP:
721 case SNDRV_PCM_TRIGGER_SUSPEND:
722 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
723 dma->valDCR |= BA0_DCR_MSK;
724 dma->valFCR &= ~BA0_FCR_FEN;
725 /* Leave wave playback FIFO enabled for FM */
726 if (dma->regFCR != BA0_FCR0)
727 dma->valFCR &= ~BA0_FCR_FEN;
728 break;
729 default:
730 spin_unlock(&chip->reg_lock);
731 return -EINVAL;
732 }
733 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
734 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
735 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
736 spin_unlock(&chip->reg_lock);
737 return 0;
738}
739
740static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
741{
742 unsigned int val = ~0;
743
744 if (real_rate)
745 *real_rate = rate;
746 /* special "hardcoded" rates */
747 switch (rate) {
748 case 8000: return 5;
749 case 11025: return 4;
750 case 16000: return 3;
751 case 22050: return 2;
752 case 44100: return 1;
753 case 48000: return 0;
754 default:
755 goto __variable;
756 }
757 __variable:
758 val = 1536000 / rate;
759 if (real_rate)
760 *real_rate = 1536000 / val;
761 return val;
762}
763
764static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
765{
766 int rec_mono;
767
768 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
769 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
770 if (runtime->channels == 1)
771 dma->valDMR |= BA0_DMR_MONO;
772 if (snd_pcm_format_unsigned(runtime->format) > 0)
773 dma->valDMR |= BA0_DMR_USIGN;
774 if (snd_pcm_format_big_endian(runtime->format) > 0)
775 dma->valDMR |= BA0_DMR_BEND;
776 switch (snd_pcm_format_width(runtime->format)) {
777 case 8: dma->valDMR |= BA0_DMR_SIZE8;
778 if (runtime->channels == 1)
779 dma->valDMR |= BA0_DMR_SWAPC;
780 break;
781 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
782 }
783 dma->frag = 0; /* for workaround */
784 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
785 if (runtime->buffer_size != runtime->period_size)
786 dma->valDCR |= BA0_DCR_HTCIE;
787 /* Initialize DMA */
788 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
789 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
790 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
791 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
792 (chip->src_right_play_slot << 8) |
793 (chip->src_left_rec_slot << 16) |
794 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
795 if (!src)
796 goto __skip_src;
797 if (!capture) {
798 if (dma->left_slot == chip->src_left_play_slot) {
799 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
800 snd_assert(dma->right_slot == chip->src_right_play_slot, );
801 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
802 }
803 } else {
804 if (dma->left_slot == chip->src_left_rec_slot) {
805 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
806 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
807 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
808 }
809 }
810 __skip_src:
811 /* Deactivate wave playback FIFO before changing slot assignments */
812 if (dma->regFCR == BA0_FCR0)
813 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
814 /* Initialize FIFO */
815 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
816 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
817 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
818 BA0_FCR_OF(dma->fifo_offset);
819 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
820 /* Activate FIFO again for FM playback */
821 if (dma->regFCR == BA0_FCR0)
822 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
823 /* Clear FIFO Status and Interrupt Control Register */
824 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
825}
826
827static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
828 snd_pcm_hw_params_t * hw_params)
829{
830 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
831}
832
833static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
834{
835 return snd_pcm_lib_free_pages(substream);
836}
837
838static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
839{
840 snd_pcm_runtime_t *runtime = substream->runtime;
841 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
842 cs4281_t *chip = snd_pcm_substream_chip(substream);
843
844 spin_lock_irq(&chip->reg_lock);
845 snd_cs4281_mode(chip, dma, runtime, 0, 1);
846 spin_unlock_irq(&chip->reg_lock);
847 return 0;
848}
849
850static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
851{
852 snd_pcm_runtime_t *runtime = substream->runtime;
853 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
854 cs4281_t *chip = snd_pcm_substream_chip(substream);
855
856 spin_lock_irq(&chip->reg_lock);
857 snd_cs4281_mode(chip, dma, runtime, 1, 1);
858 spin_unlock_irq(&chip->reg_lock);
859 return 0;
860}
861
862static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
863{
864 snd_pcm_runtime_t *runtime = substream->runtime;
865 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
866 cs4281_t *chip = snd_pcm_substream_chip(substream);
867
868 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
869 return runtime->buffer_size -
870 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
871}
872
873static snd_pcm_hardware_t snd_cs4281_playback =
874{
875 .info = (SNDRV_PCM_INFO_MMAP |
876 SNDRV_PCM_INFO_INTERLEAVED |
877 SNDRV_PCM_INFO_MMAP_VALID |
878 SNDRV_PCM_INFO_PAUSE |
879 SNDRV_PCM_INFO_RESUME |
880 SNDRV_PCM_INFO_SYNC_START),
881 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
882 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
883 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
884 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
885 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
886 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
887 .rate_min = 4000,
888 .rate_max = 48000,
889 .channels_min = 1,
890 .channels_max = 2,
891 .buffer_bytes_max = (512*1024),
892 .period_bytes_min = 64,
893 .period_bytes_max = (512*1024),
894 .periods_min = 1,
895 .periods_max = 2,
896 .fifo_size = CS4281_FIFO_SIZE,
897};
898
899static snd_pcm_hardware_t snd_cs4281_capture =
900{
901 .info = (SNDRV_PCM_INFO_MMAP |
902 SNDRV_PCM_INFO_INTERLEAVED |
903 SNDRV_PCM_INFO_MMAP_VALID |
904 SNDRV_PCM_INFO_PAUSE |
905 SNDRV_PCM_INFO_RESUME |
906 SNDRV_PCM_INFO_SYNC_START),
907 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
908 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
909 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
910 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
911 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
912 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
913 .rate_min = 4000,
914 .rate_max = 48000,
915 .channels_min = 1,
916 .channels_max = 2,
917 .buffer_bytes_max = (512*1024),
918 .period_bytes_min = 64,
919 .period_bytes_max = (512*1024),
920 .periods_min = 1,
921 .periods_max = 2,
922 .fifo_size = CS4281_FIFO_SIZE,
923};
924
925static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
926{
927 cs4281_t *chip = snd_pcm_substream_chip(substream);
928 snd_pcm_runtime_t *runtime = substream->runtime;
929 cs4281_dma_t *dma;
930
931 dma = &chip->dma[0];
932 dma->substream = substream;
933 dma->left_slot = 0;
934 dma->right_slot = 1;
935 runtime->private_data = dma;
936 runtime->hw = snd_cs4281_playback;
937 snd_pcm_set_sync(substream);
938 /* should be detected from the AC'97 layer, but it seems
939 that although CS4297A rev B reports 18-bit ADC resolution,
940 samples are 20-bit */
941 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
942 return 0;
943}
944
945static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
946{
947 cs4281_t *chip = snd_pcm_substream_chip(substream);
948 snd_pcm_runtime_t *runtime = substream->runtime;
949 cs4281_dma_t *dma;
950
951 dma = &chip->dma[1];
952 dma->substream = substream;
953 dma->left_slot = 10;
954 dma->right_slot = 11;
955 runtime->private_data = dma;
956 runtime->hw = snd_cs4281_capture;
957 snd_pcm_set_sync(substream);
958 /* should be detected from the AC'97 layer, but it seems
959 that although CS4297A rev B reports 18-bit ADC resolution,
960 samples are 20-bit */
961 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
962 return 0;
963}
964
965static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
966{
967 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
968
969 dma->substream = NULL;
970 return 0;
971}
972
973static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
974{
975 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
976
977 dma->substream = NULL;
978 return 0;
979}
980
981static snd_pcm_ops_t snd_cs4281_playback_ops = {
982 .open = snd_cs4281_playback_open,
983 .close = snd_cs4281_playback_close,
984 .ioctl = snd_pcm_lib_ioctl,
985 .hw_params = snd_cs4281_hw_params,
986 .hw_free = snd_cs4281_hw_free,
987 .prepare = snd_cs4281_playback_prepare,
988 .trigger = snd_cs4281_trigger,
989 .pointer = snd_cs4281_pointer,
990};
991
992static snd_pcm_ops_t snd_cs4281_capture_ops = {
993 .open = snd_cs4281_capture_open,
994 .close = snd_cs4281_capture_close,
995 .ioctl = snd_pcm_lib_ioctl,
996 .hw_params = snd_cs4281_hw_params,
997 .hw_free = snd_cs4281_hw_free,
998 .prepare = snd_cs4281_capture_prepare,
999 .trigger = snd_cs4281_trigger,
1000 .pointer = snd_cs4281_pointer,
1001};
1002
1003static void snd_cs4281_pcm_free(snd_pcm_t *pcm)
1004{
1005 cs4281_t *chip = pcm->private_data;
1006 chip->pcm = NULL;
1007 snd_pcm_lib_preallocate_free_for_all(pcm);
1008}
1009
1010static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
1011{
1012 snd_pcm_t *pcm;
1013 int err;
1014
1015 if (rpcm)
1016 *rpcm = NULL;
1017 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
1018 if (err < 0)
1019 return err;
1020
1021 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
1022 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
1023
1024 pcm->private_data = chip;
1025 pcm->private_free = snd_cs4281_pcm_free;
1026 pcm->info_flags = 0;
1027 strcpy(pcm->name, "CS4281");
1028 chip->pcm = pcm;
1029
1030 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1031 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
1032
1033 if (rpcm)
1034 *rpcm = pcm;
1035 return 0;
1036}
1037
1038/*
1039 * Mixer section
1040 */
1041
1042#define CS_VOL_MASK 0x1f
1043
1044static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1045{
1046 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1047 uinfo->count = 2;
1048 uinfo->value.integer.min = 0;
1049 uinfo->value.integer.max = CS_VOL_MASK;
1050 return 0;
1051}
1052
1053static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1054{
1055 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1056 int regL = (kcontrol->private_value >> 16) & 0xffff;
1057 int regR = kcontrol->private_value & 0xffff;
1058 int volL, volR;
1059
1060 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1061 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1062
1063 ucontrol->value.integer.value[0] = volL;
1064 ucontrol->value.integer.value[1] = volR;
1065 return 0;
1066}
1067
1068static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1069{
1070 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1071 int change = 0;
1072 int regL = (kcontrol->private_value >> 16) & 0xffff;
1073 int regR = kcontrol->private_value & 0xffff;
1074 int volL, volR;
1075
1076 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1077 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1078
1079 if (ucontrol->value.integer.value[0] != volL) {
1080 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1081 snd_cs4281_pokeBA0(chip, regL, volL);
1082 change = 1;
1083 }
1084 if (ucontrol->value.integer.value[0] != volL) {
1085 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1086 snd_cs4281_pokeBA0(chip, regR, volR);
1087 change = 1;
1088 }
1089 return change;
1090}
1091
1092static snd_kcontrol_new_t snd_cs4281_fm_vol =
1093{
1094 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1095 .name = "Synth Playback Volume",
1096 .info = snd_cs4281_info_volume,
1097 .get = snd_cs4281_get_volume,
1098 .put = snd_cs4281_put_volume,
1099 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1100};
1101
1102static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1103{
1104 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1105 .name = "PCM Stream Playback Volume",
1106 .info = snd_cs4281_info_volume,
1107 .get = snd_cs4281_get_volume,
1108 .put = snd_cs4281_put_volume,
1109 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1110};
1111
1112static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1113{
1114 cs4281_t *chip = bus->private_data;
1115 chip->ac97_bus = NULL;
1116}
1117
1118static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1119{
1120 cs4281_t *chip = ac97->private_data;
1121 if (ac97->num)
1122 chip->ac97_secondary = NULL;
1123 else
1124 chip->ac97 = NULL;
1125}
1126
1127static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1128{
1129 snd_card_t *card = chip->card;
1130 ac97_template_t ac97;
1131 int err;
1132 static ac97_bus_ops_t ops = {
1133 .write = snd_cs4281_ac97_write,
1134 .read = snd_cs4281_ac97_read,
1135 };
1136
1137 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1138 return err;
1139 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1140
1141 memset(&ac97, 0, sizeof(ac97));
1142 ac97.private_data = chip;
1143 ac97.private_free = snd_cs4281_mixer_free_ac97;
1144 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1145 return err;
1146 if (chip->dual_codec) {
1147 ac97.num = 1;
1148 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1149 return err;
1150 }
1151 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1152 return err;
1153 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1154 return err;
1155 return 0;
1156}
1157
1158
1159/*
1160 * proc interface
1161 */
1162
1163static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1164 snd_info_buffer_t * buffer)
1165{
1166 cs4281_t *chip = entry->private_data;
1167
1168 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1169 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1170 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1171}
1172
1173static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1174 struct file *file, char __user *buf,
1175 unsigned long count, unsigned long pos)
1176{
1177 long size;
1178 cs4281_t *chip = entry->private_data;
1179
1180 size = count;
1181 if (pos + size > CS4281_BA0_SIZE)
1182 size = (long)CS4281_BA0_SIZE - pos;
1183 if (size > 0) {
1184 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1185 return -EFAULT;
1186 }
1187 return size;
1188}
1189
1190static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1191 struct file *file, char __user *buf,
1192 unsigned long count, unsigned long pos)
1193{
1194 long size;
1195 cs4281_t *chip = entry->private_data;
1196
1197 size = count;
1198 if (pos + size > CS4281_BA1_SIZE)
1199 size = (long)CS4281_BA1_SIZE - pos;
1200 if (size > 0) {
1201 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1202 return -EFAULT;
1203 }
1204 return size;
1205}
1206
1207static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1208 .read = snd_cs4281_BA0_read,
1209};
1210
1211static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1212 .read = snd_cs4281_BA1_read,
1213};
1214
1215static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1216{
1217 snd_info_entry_t *entry;
1218
1219 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1220 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1221 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1222 entry->content = SNDRV_INFO_CONTENT_DATA;
1223 entry->private_data = chip;
1224 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1225 entry->size = CS4281_BA0_SIZE;
1226 }
1227 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1228 entry->content = SNDRV_INFO_CONTENT_DATA;
1229 entry->private_data = chip;
1230 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1231 entry->size = CS4281_BA1_SIZE;
1232 }
1233}
1234
1235/*
1236 * joystick support
1237 */
1238
1239#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1240
1241static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1242{
1243 cs4281_t *chip = gameport_get_port_data(gameport);
1244
1245 snd_assert(chip, return);
1246 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1247}
1248
1249static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1250{
1251 cs4281_t *chip = gameport_get_port_data(gameport);
1252
1253 snd_assert(chip, return 0);
1254 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1255}
1256
1257#ifdef COOKED_MODE
1258static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1259{
1260 cs4281_t *chip = gameport_get_port_data(gameport);
1261 unsigned js1, js2, jst;
1262
1263 snd_assert(chip, return 0);
1264
1265 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1266 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1267 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1268
1269 *buttons = (~jst >> 4) & 0x0F;
1270
1271 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1272 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1273 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1274 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1275
1276 for (jst = 0; jst < 4; ++jst)
1277 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1278 return 0;
1279}
1280#else
1281#define snd_cs4281_gameport_cooked_read NULL
1282#endif
1283
1284static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1285{
1286 switch (mode) {
1287#ifdef COOKED_MODE
1288 case GAMEPORT_MODE_COOKED:
1289 return 0;
1290#endif
1291 case GAMEPORT_MODE_RAW:
1292 return 0;
1293 default:
1294 return -1;
1295 }
1296 return 0;
1297}
1298
1299static int __devinit snd_cs4281_create_gameport(cs4281_t *chip)
1300{
1301 struct gameport *gp;
1302
1303 chip->gameport = gp = gameport_allocate_port();
1304 if (!gp) {
1305 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1306 return -ENOMEM;
1307 }
1308
1309 gameport_set_name(gp, "CS4281 Gameport");
1310 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1311 gameport_set_dev_parent(gp, &chip->pci->dev);
1312 gp->open = snd_cs4281_gameport_open;
1313 gp->read = snd_cs4281_gameport_read;
1314 gp->trigger = snd_cs4281_gameport_trigger;
1315 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1316 gameport_set_port_data(gp, chip);
1317
1318 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1319 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1320
1321 gameport_register_port(gp);
1322
1323 return 0;
1324}
1325
1326static void snd_cs4281_free_gameport(cs4281_t *chip)
1327{
1328 if (chip->gameport) {
1329 gameport_unregister_port(chip->gameport);
1330 chip->gameport = NULL;
1331 }
1332}
1333#else
1334static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; }
1335static inline void snd_cs4281_free_gameport(cs4281_t *chip) { }
1336#endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1337
1338
1339/*
1340
1341 */
1342
1343static int snd_cs4281_free(cs4281_t *chip)
1344{
1345 snd_cs4281_free_gameport(chip);
1346
1347 if (chip->irq >= 0)
1348 synchronize_irq(chip->irq);
1349
1350 /* Mask interrupts */
1351 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1352 /* Stop the DLL Clock logic. */
1353 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1354 /* Sound System Power Management - Turn Everything OFF */
1355 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1356 /* PCI interface - D3 state */
1357 pci_set_power_state(chip->pci, 3);
1358
1359 if (chip->irq >= 0)
1360 free_irq(chip->irq, (void *)chip);
1361 if (chip->ba0)
1362 iounmap(chip->ba0);
1363 if (chip->ba1)
1364 iounmap(chip->ba1);
1365 pci_release_regions(chip->pci);
1366 pci_disable_device(chip->pci);
1367
1368 kfree(chip);
1369 return 0;
1370}
1371
1372static int snd_cs4281_dev_free(snd_device_t *device)
1373{
1374 cs4281_t *chip = device->device_data;
1375 return snd_cs4281_free(chip);
1376}
1377
1378static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1379#ifdef CONFIG_PM
1380static int cs4281_suspend(snd_card_t *card, pm_message_t state);
1381static int cs4281_resume(snd_card_t *card);
1382#endif
1383
1384static int __devinit snd_cs4281_create(snd_card_t * card,
1385 struct pci_dev *pci,
1386 cs4281_t ** rchip,
1387 int dual_codec)
1388{
1389 cs4281_t *chip;
1390 unsigned int tmp;
1391 int err;
1392 static snd_device_ops_t ops = {
1393 .dev_free = snd_cs4281_dev_free,
1394 };
1395
1396 *rchip = NULL;
1397 if ((err = pci_enable_device(pci)) < 0)
1398 return err;
1399 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1400 if (chip == NULL) {
1401 pci_disable_device(pci);
1402 return -ENOMEM;
1403 }
1404 spin_lock_init(&chip->reg_lock);
1405 chip->card = card;
1406 chip->pci = pci;
1407 chip->irq = -1;
1408 pci_set_master(pci);
1409 if (dual_codec < 0 || dual_codec > 3) {
1410 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1411 dual_codec = 0;
1412 }
1413 chip->dual_codec = dual_codec;
1414
1415 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1416 kfree(chip);
1417 pci_disable_device(pci);
1418 return err;
1419 }
1420 chip->ba0_addr = pci_resource_start(pci, 0);
1421 chip->ba1_addr = pci_resource_start(pci, 1);
1422
1423 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1424 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1425 snd_cs4281_free(chip);
1426 return -ENOMEM;
1427 }
1428 chip->irq = pci->irq;
1429
1430 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1431 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1432 if (!chip->ba0 || !chip->ba1) {
1433 snd_cs4281_free(chip);
1434 return -ENOMEM;
1435 }
1436
1437 tmp = snd_cs4281_chip_init(chip);
1438 if (tmp) {
1439 snd_cs4281_free(chip);
1440 return tmp;
1441 }
1442
1443 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1444 snd_cs4281_free(chip);
1445 return err;
1446 }
1447
1448 snd_cs4281_proc_init(chip);
1449
1450 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1451
1452 snd_card_set_dev(card, &pci->dev);
1453
1454 *rchip = chip;
1455 return 0;
1456}
1457
1458static int snd_cs4281_chip_init(cs4281_t *chip)
1459{
1460 unsigned int tmp;
1461 int timeout;
1462 int retry_count = 2;
1463
1464 __retry:
1465 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1466 if (tmp != BA0_CFLR_DEFAULT) {
1467 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1468 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1469 if (tmp != BA0_CFLR_DEFAULT) {
1470 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1471 return -EIO;
1472 }
1473 }
1474
1475 /* Set the 'Configuration Write Protect' register
1476 * to 4281h. Allows vendor-defined configuration
1477 * space between 0e4h and 0ffh to be written. */
1478 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1479
1480 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1481 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1482 return -EIO;
1483 }
1484 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1485 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1486 return -EIO;
1487 }
1488
1489 /* Sound System Power Management */
1490 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1491 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1492 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1493
1494 /* Serial Port Power Management */
1495 /* Blast the clock control register to zero so that the
1496 * PLL starts out in a known state, and blast the master serial
1497 * port control register to zero so that the serial ports also
1498 * start out in a known state. */
1499 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1500 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1501
1502 /* Make ESYN go to zero to turn off
1503 * the Sync pulse on the AC97 link. */
1504 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1505 udelay(50);
1506
1507 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1508 * spec) and then drive it high. This is done for non AC97 modes since
1509 * there might be logic external to the CS4281 that uses the ARST# line
1510 * for a reset. */
1511 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1512 udelay(50);
1513 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1514 snd_cs4281_delay(50000);
1515
1516 if (chip->dual_codec)
1517 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1518
1519 /*
1520 * Set the serial port timing configuration.
1521 */
1522 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1523 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1524 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1525
1526 /*
1527 * Start the DLL Clock logic.
1528 */
1529 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1530 snd_cs4281_delay(50000);
1531 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1532
1533 /*
1534 * Wait for the DLL ready signal from the clock logic.
1535 */
1536 timeout = HZ;
1537 do {
1538 /*
1539 * Read the AC97 status register to see if we've seen a CODEC
1540 * signal from the AC97 codec.
1541 */
1542 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1543 goto __ok0;
1544 snd_cs4281_delay_long();
1545 } while (timeout-- > 0);
1546
1547 snd_printk(KERN_ERR "DLLRDY not seen\n");
1548 return -EIO;
1549
1550 __ok0:
1551
1552 /*
1553 * The first thing we do here is to enable sync generation. As soon
1554 * as we start receiving bit clock, we'll start producing the SYNC
1555 * signal.
1556 */
1557 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1558
1559 /*
1560 * Wait for the codec ready signal from the AC97 codec.
1561 */
1562 timeout = HZ;
1563 do {
1564 /*
1565 * Read the AC97 status register to see if we've seen a CODEC
1566 * signal from the AC97 codec.
1567 */
1568 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1569 goto __ok1;
1570 snd_cs4281_delay_long();
1571 } while (timeout-- > 0);
1572
1573 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1574 return -EIO;
1575
1576 __ok1:
1577 if (chip->dual_codec) {
1578 timeout = HZ;
1579 do {
1580 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1581 goto __codec2_ok;
1582 snd_cs4281_delay_long();
1583 } while (timeout-- > 0);
1584 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1585 chip->dual_codec = 0;
1586 __codec2_ok: ;
1587 }
1588
1589 /*
1590 * Assert the valid frame signal so that we can start sending commands
1591 * to the AC97 codec.
1592 */
1593
1594 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1595
1596 /*
1597 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1598 * the codec is pumping ADC data across the AC-link.
1599 */
1600
1601 timeout = HZ;
1602 do {
1603 /*
1604 * Read the input slot valid register and see if input slots 3
1605 * 4 are valid yet.
1606 */
1607 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1608 goto __ok2;
1609 snd_cs4281_delay_long();
1610 } while (timeout-- > 0);
1611
1612 if (--retry_count > 0)
1613 goto __retry;
1614 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1615 return -EIO;
1616
1617 __ok2:
1618
1619 /*
1620 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1621 * commense the transfer of digital audio data to the AC97 codec.
1622 */
1623 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1624
1625 /*
1626 * Initialize DMA structures
1627 */
1628 for (tmp = 0; tmp < 4; tmp++) {
1629 cs4281_dma_t *dma = &chip->dma[tmp];
1630 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1631 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1632 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1633 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1634 dma->regDMR = BA0_DMR0 + (tmp * 8);
1635 dma->regDCR = BA0_DCR0 + (tmp * 8);
1636 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1637 dma->regFCR = BA0_FCR0 + (tmp * 4);
1638 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1639 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1640 snd_cs4281_pokeBA0(chip, dma->regFCR,
1641 BA0_FCR_LS(31) |
1642 BA0_FCR_RS(31) |
1643 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1644 BA0_FCR_OF(dma->fifo_offset));
1645 }
1646
1647 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1648 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1649 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1650 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1651
1652 /* Activate wave playback FIFO for FM playback */
1653 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1654 BA0_FCR_RS(1) |
1655 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1656 BA0_FCR_OF(chip->dma[0].fifo_offset);
1657 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1658 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1659 (chip->src_right_play_slot << 8) |
1660 (chip->src_left_rec_slot << 16) |
1661 (chip->src_right_rec_slot << 24));
1662
1663 /* Initialize digital volume */
1664 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1665 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1666
1667 /* Enable IRQs */
1668 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1669 /* Unmask interrupts */
1670 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1671 BA0_HISR_MIDI |
1672 BA0_HISR_DMAI |
1673 BA0_HISR_DMA(0) |
1674 BA0_HISR_DMA(1) |
1675 BA0_HISR_DMA(2) |
1676 BA0_HISR_DMA(3)));
1677 synchronize_irq(chip->irq);
1678
1679 return 0;
1680}
1681
1682/*
1683 * MIDI section
1684 */
1685
1686static void snd_cs4281_midi_reset(cs4281_t *chip)
1687{
1688 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1689 udelay(100);
1690 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1691}
1692
1693static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1694{
1695 cs4281_t *chip = substream->rmidi->private_data;
1696
1697 spin_lock_irq(&chip->reg_lock);
1698 chip->midcr |= BA0_MIDCR_RXE;
1699 chip->midi_input = substream;
1700 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1701 snd_cs4281_midi_reset(chip);
1702 } else {
1703 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1704 }
1705 spin_unlock_irq(&chip->reg_lock);
1706 return 0;
1707}
1708
1709static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1710{
1711 cs4281_t *chip = substream->rmidi->private_data;
1712
1713 spin_lock_irq(&chip->reg_lock);
1714 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1715 chip->midi_input = NULL;
1716 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1717 snd_cs4281_midi_reset(chip);
1718 } else {
1719 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1720 }
1721 chip->uartm &= ~CS4281_MODE_INPUT;
1722 spin_unlock_irq(&chip->reg_lock);
1723 return 0;
1724}
1725
1726static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1727{
1728 cs4281_t *chip = substream->rmidi->private_data;
1729
1730 spin_lock_irq(&chip->reg_lock);
1731 chip->uartm |= CS4281_MODE_OUTPUT;
1732 chip->midcr |= BA0_MIDCR_TXE;
1733 chip->midi_output = substream;
1734 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1735 snd_cs4281_midi_reset(chip);
1736 } else {
1737 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1738 }
1739 spin_unlock_irq(&chip->reg_lock);
1740 return 0;
1741}
1742
1743static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1744{
1745 cs4281_t *chip = substream->rmidi->private_data;
1746
1747 spin_lock_irq(&chip->reg_lock);
1748 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1749 chip->midi_output = NULL;
1750 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1751 snd_cs4281_midi_reset(chip);
1752 } else {
1753 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1754 }
1755 chip->uartm &= ~CS4281_MODE_OUTPUT;
1756 spin_unlock_irq(&chip->reg_lock);
1757 return 0;
1758}
1759
1760static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1761{
1762 unsigned long flags;
1763 cs4281_t *chip = substream->rmidi->private_data;
1764
1765 spin_lock_irqsave(&chip->reg_lock, flags);
1766 if (up) {
1767 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1768 chip->midcr |= BA0_MIDCR_RIE;
1769 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1770 }
1771 } else {
1772 if (chip->midcr & BA0_MIDCR_RIE) {
1773 chip->midcr &= ~BA0_MIDCR_RIE;
1774 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1775 }
1776 }
1777 spin_unlock_irqrestore(&chip->reg_lock, flags);
1778}
1779
1780static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1781{
1782 unsigned long flags;
1783 cs4281_t *chip = substream->rmidi->private_data;
1784 unsigned char byte;
1785
1786 spin_lock_irqsave(&chip->reg_lock, flags);
1787 if (up) {
1788 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1789 chip->midcr |= BA0_MIDCR_TIE;
1790 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1791 while ((chip->midcr & BA0_MIDCR_TIE) &&
1792 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1793 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1794 chip->midcr &= ~BA0_MIDCR_TIE;
1795 } else {
1796 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1797 }
1798 }
1799 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1800 }
1801 } else {
1802 if (chip->midcr & BA0_MIDCR_TIE) {
1803 chip->midcr &= ~BA0_MIDCR_TIE;
1804 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1805 }
1806 }
1807 spin_unlock_irqrestore(&chip->reg_lock, flags);
1808}
1809
1810static snd_rawmidi_ops_t snd_cs4281_midi_output =
1811{
1812 .open = snd_cs4281_midi_output_open,
1813 .close = snd_cs4281_midi_output_close,
1814 .trigger = snd_cs4281_midi_output_trigger,
1815};
1816
1817static snd_rawmidi_ops_t snd_cs4281_midi_input =
1818{
1819 .open = snd_cs4281_midi_input_open,
1820 .close = snd_cs4281_midi_input_close,
1821 .trigger = snd_cs4281_midi_input_trigger,
1822};
1823
1824static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1825{
1826 snd_rawmidi_t *rmidi;
1827 int err;
1828
1829 if (rrawmidi)
1830 *rrawmidi = NULL;
1831 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1832 return err;
1833 strcpy(rmidi->name, "CS4281");
1834 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1835 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1836 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1837 rmidi->private_data = chip;
1838 chip->rmidi = rmidi;
1839 if (rrawmidi)
1840 *rrawmidi = rmidi;
1841 return 0;
1842}
1843
1844/*
1845 * Interrupt handler
1846 */
1847
1848static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1849{
1850 cs4281_t *chip = dev_id;
1851 unsigned int status, dma, val;
1852 cs4281_dma_t *cdma;
1853
1854 if (chip == NULL)
1855 return IRQ_NONE;
1856 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1857 if ((status & 0x7fffffff) == 0) {
1858 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1859 return IRQ_NONE;
1860 }
1861
1862 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1863 for (dma = 0; dma < 4; dma++)
1864 if (status & BA0_HISR_DMA(dma)) {
1865 cdma = &chip->dma[dma];
1866 spin_lock(&chip->reg_lock);
1867 /* ack DMA IRQ */
1868 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1869 /* workaround, sometimes CS4281 acknowledges */
1870 /* end or middle transfer position twice */
1871 cdma->frag++;
1872 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1873 cdma->frag--;
1874 chip->spurious_dhtc_irq++;
1875 spin_unlock(&chip->reg_lock);
1876 continue;
1877 }
1878 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1879 cdma->frag--;
1880 chip->spurious_dtc_irq++;
1881 spin_unlock(&chip->reg_lock);
1882 continue;
1883 }
1884 spin_unlock(&chip->reg_lock);
1885 snd_pcm_period_elapsed(cdma->substream);
1886 }
1887 }
1888
1889 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1890 unsigned char c;
1891
1892 spin_lock(&chip->reg_lock);
1893 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1894 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1895 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1896 continue;
1897 snd_rawmidi_receive(chip->midi_input, &c, 1);
1898 }
1899 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1900 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1901 break;
1902 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1903 chip->midcr &= ~BA0_MIDCR_TIE;
1904 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1905 break;
1906 }
1907 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1908 }
1909 spin_unlock(&chip->reg_lock);
1910 }
1911
1912 /* EOI to the PCI part... reenables interrupts */
1913 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1914
1915 return IRQ_HANDLED;
1916}
1917
1918
1919/*
1920 * OPL3 command
1921 */
1922static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
1923{
1924 unsigned long flags;
1925 cs4281_t *chip = opl3->private_data;
1926 void __iomem *port;
1927
1928 if (cmd & OPL3_RIGHT)
1929 port = chip->ba0 + BA0_B1AP; /* right port */
1930 else
1931 port = chip->ba0 + BA0_B0AP; /* left port */
1932
1933 spin_lock_irqsave(&opl3->reg_lock, flags);
1934
1935 writel((unsigned int)cmd, port);
1936 udelay(10);
1937
1938 writel((unsigned int)val, port + 4);
1939 udelay(30);
1940
1941 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1942}
1943
1944static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1945 const struct pci_device_id *pci_id)
1946{
1947 static int dev;
1948 snd_card_t *card;
1949 cs4281_t *chip;
1950 opl3_t *opl3;
1951 int err;
1952
1953 if (dev >= SNDRV_CARDS)
1954 return -ENODEV;
1955 if (!enable[dev]) {
1956 dev++;
1957 return -ENOENT;
1958 }
1959
1960 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1961 if (card == NULL)
1962 return -ENOMEM;
1963
1964 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1965 snd_card_free(card);
1966 return err;
1967 }
1968
1969 if ((err = snd_cs4281_mixer(chip)) < 0) {
1970 snd_card_free(card);
1971 return err;
1972 }
1973 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1974 snd_card_free(card);
1975 return err;
1976 }
1977 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1978 snd_card_free(card);
1979 return err;
1980 }
1981 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1982 snd_card_free(card);
1983 return err;
1984 }
1985 opl3->private_data = chip;
1986 opl3->command = snd_cs4281_opl3_command;
1987 snd_opl3_init(opl3);
1988 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1989 snd_card_free(card);
1990 return err;
1991 }
1992 snd_cs4281_create_gameport(chip);
1993 strcpy(card->driver, "CS4281");
1994 strcpy(card->shortname, "Cirrus Logic CS4281");
1995 sprintf(card->longname, "%s at 0x%lx, irq %d",
1996 card->shortname,
1997 chip->ba0_addr,
1998 chip->irq);
1999
2000 if ((err = snd_card_register(card)) < 0) {
2001 snd_card_free(card);
2002 return err;
2003 }
2004
2005 pci_set_drvdata(pci, card);
2006 dev++;
2007 return 0;
2008}
2009
2010static void __devexit snd_cs4281_remove(struct pci_dev *pci)
2011{
2012 snd_card_free(pci_get_drvdata(pci));
2013 pci_set_drvdata(pci, NULL);
2014}
2015
2016/*
2017 * Power Management
2018 */
2019#ifdef CONFIG_PM
2020
2021static int saved_regs[SUSPEND_REGISTERS] = {
2022 BA0_JSCTL,
2023 BA0_GPIOR,
2024 BA0_SSCR,
2025 BA0_MIDCR,
2026 BA0_SRCSA,
2027 BA0_PASR,
2028 BA0_CASR,
2029 BA0_DACSR,
2030 BA0_ADCSR,
2031 BA0_FMLVC,
2032 BA0_FMRVC,
2033 BA0_PPLVC,
2034 BA0_PPRVC,
2035};
2036
2037#define CLKCR1_CKRA 0x00010000L
2038
2039static int cs4281_suspend(snd_card_t *card, pm_message_t state)
2040{
2041 cs4281_t *chip = card->pm_private_data;
2042 u32 ulCLK;
2043 unsigned int i;
2044
2045 snd_pcm_suspend_all(chip->pcm);
2046
2047 if (chip->ac97)
2048 snd_ac97_suspend(chip->ac97);
2049 if (chip->ac97_secondary)
2050 snd_ac97_suspend(chip->ac97_secondary);
2051
2052 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2053 ulCLK |= CLKCR1_CKRA;
2054 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2055
2056 /* Disable interrupts. */
2057 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2058
2059 /* remember the status registers */
2060 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2061 if (saved_regs[i])
2062 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2063
2064 /* Turn off the serial ports. */
2065 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2066
2067 /* Power off FM, Joystick, AC link, */
2068 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2069
2070 /* DLL off. */
2071 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2072
2073 /* AC link off. */
2074 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2075
2076 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2077 ulCLK &= ~CLKCR1_CKRA;
2078 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2079
2080 pci_disable_device(chip->pci);
2081 return 0;
2082}
2083
2084static int cs4281_resume(snd_card_t *card)
2085{
2086 cs4281_t *chip = card->pm_private_data;
2087 unsigned int i;
2088 u32 ulCLK;
2089
2090 pci_enable_device(chip->pci);
2091 pci_set_master(chip->pci);
2092
2093 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2094 ulCLK |= CLKCR1_CKRA;
2095 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2096
2097 snd_cs4281_chip_init(chip);
2098
2099 /* restore the status registers */
2100 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2101 if (saved_regs[i])
2102 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2103
2104 if (chip->ac97)
2105 snd_ac97_resume(chip->ac97);
2106 if (chip->ac97_secondary)
2107 snd_ac97_resume(chip->ac97_secondary);
2108
2109 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2110 ulCLK &= ~CLKCR1_CKRA;
2111 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2112
2113 return 0;
2114}
2115#endif /* CONFIG_PM */
2116
2117static struct pci_driver driver = {
2118 .name = "CS4281",
2119 .id_table = snd_cs4281_ids,
2120 .probe = snd_cs4281_probe,
2121 .remove = __devexit_p(snd_cs4281_remove),
2122 SND_PCI_PM_CALLBACKS
2123};
2124
2125static int __init alsa_card_cs4281_init(void)
2126{
2127 return pci_module_init(&driver);
2128}
2129
2130static void __exit alsa_card_cs4281_exit(void)
2131{
2132 pci_unregister_driver(&driver);
2133}
2134
2135module_init(alsa_card_cs4281_init)
2136module_exit(alsa_card_cs4281_exit)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 00:49:17 -0500