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-rw-r--r--sound/pci/cmipci.c537
1 files changed, 353 insertions, 184 deletions
diff --git a/sound/pci/cmipci.c b/sound/pci/cmipci.c
index 7d3c5ee0005c..6832649879ce 100644
--- a/sound/pci/cmipci.c
+++ b/sound/pci/cmipci.c
@@ -95,30 +95,34 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
95#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ 95#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96 96
97#define CM_REG_FUNCTRL1 0x04 97#define CM_REG_FUNCTRL1 0x04
98#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ 98#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99#define CM_ASFC_SHIFT 13 99#define CM_DSFC_SHIFT 13
100#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ 100#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101#define CM_DSFC_SHIFT 10 101#define CM_ASFC_SHIFT 10
102#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 102#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 103#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ 104#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 105#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 106#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107#define CM_BREQ 0x00000010 /* bus master enabled */ 107#define CM_BREQ 0x00000010 /* bus master enabled */
108#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 108#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109#define CM_UART_EN 0x00000004 /* UART */ 109#define CM_UART_EN 0x00000004 /* legacy UART */
110#define CM_JYSTK_EN 0x00000002 /* joy stick */ 110#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111#define CM_ZVPORT 0x00000001 /* ZVPORT */
111 112
112#define CM_REG_CHFORMAT 0x08 113#define CM_REG_CHFORMAT 0x08
113 114
114#define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 115#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
115#define CM_CHB3D 0x20000000 /* 4 channels */ 117#define CM_CHB3D 0x20000000 /* 4 channels */
116 118
117#define CM_CHIP_MASK1 0x1f000000 119#define CM_CHIP_MASK1 0x1f000000
118#define CM_CHIP_037 0x01000000 120#define CM_CHIP_037 0x01000000
119 121#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
120#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 122#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
121#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 124#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
122#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 126#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
123/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 127/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
124 128
@@ -128,35 +132,45 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
128#define CM_ADCBITLEN_14 0x00008000 132#define CM_ADCBITLEN_14 0x00008000
129#define CM_ADCBITLEN_13 0x0000C000 133#define CM_ADCBITLEN_13 0x0000C000
130 134
131#define CM_ADCDACLEN_MASK 0x00003000 135#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
132#define CM_ADCDACLEN_060 0x00000000 136#define CM_ADCDACLEN_060 0x00000000
133#define CM_ADCDACLEN_066 0x00001000 137#define CM_ADCDACLEN_066 0x00001000
134#define CM_ADCDACLEN_130 0x00002000 138#define CM_ADCDACLEN_130 0x00002000
135#define CM_ADCDACLEN_280 0x00003000 139#define CM_ADCDACLEN_280 0x00003000
136 140
141#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142#define CM_ADCDLEN_ORIGINAL 0x00000000
143#define CM_ADCDLEN_EXTRA 0x00001000
144#define CM_ADCDLEN_24K 0x00002000
145#define CM_ADCDLEN_WEIGHT 0x00003000
146
137#define CM_CH1_SRATE_176K 0x00000800 147#define CM_CH1_SRATE_176K 0x00000800
148#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
138#define CM_CH1_SRATE_88K 0x00000400 149#define CM_CH1_SRATE_88K 0x00000400
139#define CM_CH0_SRATE_176K 0x00000200 150#define CM_CH0_SRATE_176K 0x00000200
151#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
140#define CM_CH0_SRATE_88K 0x00000100 152#define CM_CH0_SRATE_88K 0x00000100
141 153
142#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 154#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
155#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
156#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
157#define CM_SPDLOCKED 0x00000010
143 158
144#define CM_CH1FMT_MASK 0x0000000C 159#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
145#define CM_CH1FMT_SHIFT 2 160#define CM_CH1FMT_SHIFT 2
146#define CM_CH0FMT_MASK 0x00000003 161#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
147#define CM_CH0FMT_SHIFT 0 162#define CM_CH0FMT_SHIFT 0
148 163
149#define CM_REG_INT_HLDCLR 0x0C 164#define CM_REG_INT_HLDCLR 0x0C
150#define CM_CHIP_MASK2 0xff000000 165#define CM_CHIP_MASK2 0xff000000
166#define CM_CHIP_8768 0x20000000
167#define CM_CHIP_055 0x08000000
151#define CM_CHIP_039 0x04000000 168#define CM_CHIP_039 0x04000000
152#define CM_CHIP_039_6CH 0x01000000 169#define CM_CHIP_039_6CH 0x01000000
153#define CM_CHIP_055 0x08000000 170#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
154#define CM_CHIP_8768 0x20000000
155#define CM_TDMA_INT_EN 0x00040000 171#define CM_TDMA_INT_EN 0x00040000
156#define CM_CH1_INT_EN 0x00020000 172#define CM_CH1_INT_EN 0x00020000
157#define CM_CH0_INT_EN 0x00010000 173#define CM_CH0_INT_EN 0x00010000
158#define CM_INT_HOLD 0x00000002
159#define CM_INT_CLEAR 0x00000001
160 174
161#define CM_REG_INT_STATUS 0x10 175#define CM_REG_INT_STATUS 0x10
162#define CM_INTR 0x80000000 176#define CM_INTR 0x80000000
@@ -175,12 +189,13 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
175#define CM_CHINT0 0x00000001 189#define CM_CHINT0 0x00000001
176 190
177#define CM_REG_LEGACY_CTRL 0x14 191#define CM_REG_LEGACY_CTRL 0x14
178#define CM_NXCHG 0x80000000 /* h/w multi channels? */ 192#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
179#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 193#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
180#define CM_VMPU_330 0x00000000 194#define CM_VMPU_330 0x00000000
181#define CM_VMPU_320 0x20000000 195#define CM_VMPU_320 0x20000000
182#define CM_VMPU_310 0x40000000 196#define CM_VMPU_310 0x40000000
183#define CM_VMPU_300 0x60000000 197#define CM_VMPU_300 0x60000000
198#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
184#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 199#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
185#define CM_VSBSEL_220 0x00000000 200#define CM_VSBSEL_220 0x00000000
186#define CM_VSBSEL_240 0x04000000 201#define CM_VSBSEL_240 0x04000000
@@ -191,44 +206,74 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
191#define CM_FMSEL_3C8 0x01000000 206#define CM_FMSEL_3C8 0x01000000
192#define CM_FMSEL_3E0 0x02000000 207#define CM_FMSEL_3E0 0x02000000
193#define CM_FMSEL_3E8 0x03000000 208#define CM_FMSEL_3E8 0x03000000
194#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ 209#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
195#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ 210#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
196#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 211#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
197#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 212#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
213#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
214#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
215#define CM_C_EECS 0x00040000
216#define CM_C_EEDI46 0x00020000
217#define CM_C_EECK46 0x00010000
198#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 218#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
199#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ 219#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
220#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
221#define CM_EXBASEN 0x00001000 /* external bass input enable */
200 222
201#define CM_REG_MISC_CTRL 0x18 223#define CM_REG_MISC_CTRL 0x18
202#define CM_PWD 0x80000000 224#define CM_PWD 0x80000000 /* power down */
203#define CM_RESET 0x40000000 225#define CM_RESET 0x40000000
204#define CM_SFIL_MASK 0x30000000 226#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
205#define CM_TXVX 0x08000000 227#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
206#define CM_N4SPK3D 0x04000000 /* 4ch output */ 228#define CM_TXVX 0x08000000 /* model 037? */
229#define CM_N4SPK3D 0x04000000 /* copy front to rear */
207#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 230#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
208#define CM_SPDIF48K 0x01000000 /* write */ 231#define CM_SPDIF48K 0x01000000 /* write */
209#define CM_SPATUS48K 0x01000000 /* read */ 232#define CM_SPATUS48K 0x01000000 /* read */
210#define CM_ENDBDAC 0x00800000 /* enable dual dac */ 233#define CM_ENDBDAC 0x00800000 /* enable double dac */
211#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 234#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
212#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 235#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
213#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ 236#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
214#define CM_FM_EN 0x00080000 /* enalbe FM */ 237#define CM_FM_EN 0x00080000 /* enable legacy FM */
215#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 238#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
216#define CM_VIDWPDSB 0x00010000 239#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
240#define CM_VIDWPDSB 0x00010000 /* model 037? */
217#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 241#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
218#define CM_MASK_EN 0x00004000 242#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
219#define CM_VIDWPPRT 0x00002000 243#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
220#define CM_SFILENB 0x00001000 244#define CM_VIDWPPRT 0x00002000 /* model 037? */
221#define CM_MMODE_MASK 0x00000E00 245#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
246#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
222#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 247#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
223#define CM_ENCENTER 0x00000080 248#define CM_ENCENTER 0x00000080
224#define CM_FLINKON 0x00000040 249#define CM_FLINKON 0x00000080 /* force modem link detection on, model 037 */
225#define CM_FLINKOFF 0x00000020 250#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
226#define CM_MIDSMP 0x00000010 251#define CM_FLINKOFF 0x00000040 /* force modem link detection off, model 037 */
227#define CM_UPDDMA_MASK 0x0000000C 252#define CM_UNKNOWN_18_5 0x00000020 /* ? */
228#define CM_TWAIT_MASK 0x00000003 253#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255#define CM_UPDDMA_2048 0x00000000
256#define CM_UPDDMA_1024 0x00000004
257#define CM_UPDDMA_512 0x00000008
258#define CM_UPDDMA_256 0x0000000C
259#define CM_TWAIT_MASK 0x00000003 /* model 037 */
260#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
262
263#define CM_REG_TDMA_POSITION 0x1C
264#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
229 266
230 /* byte */ 267 /* byte */
231#define CM_REG_MIXER0 0x20 268#define CM_REG_MIXER0 0x20
269#define CM_REG_SBVR 0x20 /* write: sb16 version */
270#define CM_REG_DEV 0x20 /* read: hardware device version */
271
272#define CM_REG_MIXER21 0x21
273#define CM_UNKNOWN_21_MASK 0x78 /* ? */
274#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275#define CM_PROINV 0x02 /* SBPro left/right channel switching */
276#define CM_X_SB16 0x01 /* SB16 compatible */
232 277
233#define CM_REG_SB16_DATA 0x22 278#define CM_REG_SB16_DATA 0x22
234#define CM_REG_SB16_ADDR 0x23 279#define CM_REG_SB16_ADDR 0x23
@@ -243,8 +288,8 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
243#define CM_FMMUTE_SHIFT 7 288#define CM_FMMUTE_SHIFT 7
244#define CM_WSMUTE 0x40 /* mute PCM */ 289#define CM_WSMUTE 0x40 /* mute PCM */
245#define CM_WSMUTE_SHIFT 6 290#define CM_WSMUTE_SHIFT 6
246#define CM_SPK4 0x20 /* lin-in -> rear line out */ 291#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
247#define CM_SPK4_SHIFT 5 292#define CM_REAR2LIN_SHIFT 5
248#define CM_REAR2FRONT 0x10 /* exchange rear/front */ 293#define CM_REAR2FRONT 0x10 /* exchange rear/front */
249#define CM_REAR2FRONT_SHIFT 4 294#define CM_REAR2FRONT_SHIFT 4
250#define CM_WAVEINL 0x08 /* digital wave rec. left chan */ 295#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
@@ -276,12 +321,13 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
276#define CM_VAUXR_MASK 0x0f 321#define CM_VAUXR_MASK 0x0f
277 322
278#define CM_REG_MISC 0x27 323#define CM_REG_MISC 0x27
324#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
279#define CM_XGPO1 0x20 325#define CM_XGPO1 0x20
280// #define CM_XGPBIO 0x04 326// #define CM_XGPBIO 0x04
281#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ 327#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
282#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 328#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
283#define CM_SPDVALID 0x02 /* spdif input valid check */ 329#define CM_SPDVALID 0x02 /* spdif input valid check */
284#define CM_DMAUTO 0x01 330#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
285 331
286#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ 332#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
287/* 333/*
@@ -322,18 +368,20 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
322/* 368/*
323 * extended registers 369 * extended registers
324 */ 370 */
325#define CM_REG_CH0_FRAME1 0x80 /* base address */ 371#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
326#define CM_REG_CH0_FRAME2 0x84 372#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
327#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 373#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
328#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 374#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375
329#define CM_REG_EXT_MISC 0x90 376#define CM_REG_EXT_MISC 0x90
330#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ 377#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
331#define CM_CHB3D8C 0x20 /* 7.1 channels support */ 378#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
332#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ 379#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
333#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ 380#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
334#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ 381#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
335#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ 382#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
336#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ 383#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
337 385
338/* 386/*
339 * size of i/o region 387 * size of i/o region
@@ -383,15 +431,14 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
383 431
384struct cmipci_pcm { 432struct cmipci_pcm {
385 struct snd_pcm_substream *substream; 433 struct snd_pcm_substream *substream;
386 int running; /* dac/adc running? */ 434 u8 running; /* dac/adc running? */
435 u8 fmt; /* format bits */
436 u8 is_dac;
437 u8 needs_silencing;
387 unsigned int dma_size; /* in frames */ 438 unsigned int dma_size; /* in frames */
388 unsigned int period_size; /* in frames */ 439 unsigned int shift;
440 unsigned int ch; /* channel (0/1) */
389 unsigned int offset; /* physical address of the buffer */ 441 unsigned int offset; /* physical address of the buffer */
390 unsigned int fmt; /* format bits */
391 int ch; /* channel (0/1) */
392 unsigned int is_dac; /* is dac? */
393 int bytes_per_frame;
394 int shift;
395}; 442};
396 443
397/* mixer elements toggled/resumed during ac3 playback */ 444/* mixer elements toggled/resumed during ac3 playback */
@@ -424,7 +471,6 @@ struct cmipci {
424 471
425 int chip_version; 472 int chip_version;
426 int max_channels; 473 int max_channels;
427 unsigned int has_dual_dac: 1;
428 unsigned int can_ac3_sw: 1; 474 unsigned int can_ac3_sw: 1;
429 unsigned int can_ac3_hw: 1; 475 unsigned int can_ac3_hw: 1;
430 unsigned int can_multi_ch: 1; 476 unsigned int can_multi_ch: 1;
@@ -557,6 +603,9 @@ static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 4
557static unsigned int snd_cmipci_rate_freq(unsigned int rate) 603static unsigned int snd_cmipci_rate_freq(unsigned int rate)
558{ 604{
559 unsigned int i; 605 unsigned int i;
606
607 if (rate > 48000)
608 rate /= 2;
560 for (i = 0; i < ARRAY_SIZE(rates); i++) { 609 for (i = 0; i < ARRAY_SIZE(rates); i++) {
561 if (rates[i] == rate) 610 if (rates[i] == rate)
562 return i; 611 return i;
@@ -671,19 +720,19 @@ static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
671/* 720/*
672 */ 721 */
673 722
674static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; 723static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
675static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { 724static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
676 .count = 3, 725 .count = 3,
677 .list = hw_channels, 726 .list = hw_channels,
678 .mask = 0, 727 .mask = 0,
679}; 728};
680static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { 729static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
681 .count = 5, 730 .count = 4,
682 .list = hw_channels, 731 .list = hw_channels,
683 .mask = 0, 732 .mask = 0,
684}; 733};
685static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { 734static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
686 .count = 6, 735 .count = 5,
687 .list = hw_channels, 736 .list = hw_channels,
688 .mask = 0, 737 .mask = 0,
689}; 738};
@@ -691,48 +740,37 @@ static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
691static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) 740static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
692{ 741{
693 if (channels > 2) { 742 if (channels > 2) {
694 if (! cm->can_multi_ch) 743 if (!cm->can_multi_ch || !rec->ch)
695 return -EINVAL; 744 return -EINVAL;
696 if (rec->fmt != 0x03) /* stereo 16bit only */ 745 if (rec->fmt != 0x03) /* stereo 16bit only */
697 return -EINVAL; 746 return -EINVAL;
747 }
698 748
749 if (cm->can_multi_ch) {
699 spin_lock_irq(&cm->reg_lock); 750 spin_lock_irq(&cm->reg_lock);
700 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 751 if (channels > 2) {
701 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 752 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
702 if (channels > 4) { 753 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
703 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
704 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
705 } else { 754 } else {
706 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 755 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
707 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
708 } 757 }
709 if (channels >= 6) { 758 if (channels == 8)
759 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
760 else
761 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
762 if (channels == 6) {
763 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
710 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 764 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
711 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
712 } else { 765 } else {
713 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
714 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
715 }
716 if (cm->chip_version == 68) {
717 if (channels == 8) {
718 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
719 } else {
720 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
721 }
722 }
723 spin_unlock_irq(&cm->reg_lock);
724
725 } else {
726 if (cm->can_multi_ch) {
727 spin_lock_irq(&cm->reg_lock);
728 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
729 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
730 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 766 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
731 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 767 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
732 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
733 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
734 spin_unlock_irq(&cm->reg_lock);
735 } 768 }
769 if (channels == 4)
770 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
771 else
772 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
773 spin_unlock_irq(&cm->reg_lock);
736 } 774 }
737 return 0; 775 return 0;
738} 776}
@@ -746,6 +784,7 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
746 struct snd_pcm_substream *substream) 784 struct snd_pcm_substream *substream)
747{ 785{
748 unsigned int reg, freq, val; 786 unsigned int reg, freq, val;
787 unsigned int period_size;
749 struct snd_pcm_runtime *runtime = substream->runtime; 788 struct snd_pcm_runtime *runtime = substream->runtime;
750 789
751 rec->fmt = 0; 790 rec->fmt = 0;
@@ -765,11 +804,11 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
765 rec->offset = runtime->dma_addr; 804 rec->offset = runtime->dma_addr;
766 /* buffer and period sizes in frame */ 805 /* buffer and period sizes in frame */
767 rec->dma_size = runtime->buffer_size << rec->shift; 806 rec->dma_size = runtime->buffer_size << rec->shift;
768 rec->period_size = runtime->period_size << rec->shift; 807 period_size = runtime->period_size << rec->shift;
769 if (runtime->channels > 2) { 808 if (runtime->channels > 2) {
770 /* multi-channels */ 809 /* multi-channels */
771 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 810 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
772 rec->period_size = (rec->period_size * runtime->channels) / 2; 811 period_size = (period_size * runtime->channels) / 2;
773 } 812 }
774 813
775 spin_lock_irq(&cm->reg_lock); 814 spin_lock_irq(&cm->reg_lock);
@@ -780,7 +819,7 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
780 /* program sample counts */ 819 /* program sample counts */
781 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 820 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
782 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 821 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
783 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); 822 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
784 823
785 /* set adc/dac flag */ 824 /* set adc/dac flag */
786 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 825 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
@@ -795,11 +834,11 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
795 freq = snd_cmipci_rate_freq(runtime->rate); 834 freq = snd_cmipci_rate_freq(runtime->rate);
796 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 835 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
797 if (rec->ch) { 836 if (rec->ch) {
798 val &= ~CM_ASFC_MASK;
799 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
800 } else {
801 val &= ~CM_DSFC_MASK; 837 val &= ~CM_DSFC_MASK;
802 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 838 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
839 } else {
840 val &= ~CM_ASFC_MASK;
841 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
803 } 842 }
804 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 843 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
805 //snd_printd("cmipci: functrl1 = %08x\n", val); 844 //snd_printd("cmipci: functrl1 = %08x\n", val);
@@ -813,6 +852,16 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
813 val &= ~CM_CH0FMT_MASK; 852 val &= ~CM_CH0FMT_MASK;
814 val |= rec->fmt << CM_CH0FMT_SHIFT; 853 val |= rec->fmt << CM_CH0FMT_SHIFT;
815 } 854 }
855 if (cm->chip_version == 68) {
856 if (runtime->rate == 88200)
857 val |= CM_CH0_SRATE_88K << (rec->ch * 2);
858 else
859 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
860 if (runtime->rate == 96000)
861 val |= CM_CH0_SRATE_96K << (rec->ch * 2);
862 else
863 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
864 }
816 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 865 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
817 //snd_printd("cmipci: chformat = %08x\n", val); 866 //snd_printd("cmipci: chformat = %08x\n", val);
818 867
@@ -826,7 +875,7 @@ static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
826 * PCM trigger/stop 875 * PCM trigger/stop
827 */ 876 */
828static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, 877static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
829 struct snd_pcm_substream *substream, int cmd) 878 int cmd)
830{ 879{
831 unsigned int inthld, chen, reset, pause; 880 unsigned int inthld, chen, reset, pause;
832 int result = 0; 881 int result = 0;
@@ -855,6 +904,7 @@ static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
855 cm->ctrl &= ~chen; 904 cm->ctrl &= ~chen;
856 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 905 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
857 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
907 rec->needs_silencing = rec->is_dac;
858 break; 908 break;
859 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 909 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
860 case SNDRV_PCM_TRIGGER_SUSPEND: 910 case SNDRV_PCM_TRIGGER_SUSPEND:
@@ -906,7 +956,7 @@ static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
906 int cmd) 956 int cmd)
907{ 957{
908 struct cmipci *cm = snd_pcm_substream_chip(substream); 958 struct cmipci *cm = snd_pcm_substream_chip(substream);
909 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); 959 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
910} 960}
911 961
912static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) 962static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
@@ -925,7 +975,7 @@ static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
925 int cmd) 975 int cmd)
926{ 976{
927 struct cmipci *cm = snd_pcm_substream_chip(substream); 977 struct cmipci *cm = snd_pcm_substream_chip(substream);
928 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); 978 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
929} 979}
930 980
931static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) 981static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
@@ -1199,15 +1249,19 @@ static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *sub
1199 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1249 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1200 setup_ac3(cm, subs, do_ac3, rate); 1250 setup_ac3(cm, subs, do_ac3, rate);
1201 1251
1202 if (rate == 48000) 1252 if (rate == 48000 || rate == 96000)
1203 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1253 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1204 else 1254 else
1205 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1255 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1206 1256 if (rate > 48000)
1257 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1258 else
1259 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1207 } else { 1260 } else {
1208 /* they are controlled via "IEC958 Output Switch" */ 1261 /* they are controlled via "IEC958 Output Switch" */
1209 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1262 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1210 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1263 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1264 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1211 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1265 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1212 setup_ac3(cm, subs, 0, 0); 1266 setup_ac3(cm, subs, 0, 0);
1213 } 1267 }
@@ -1227,7 +1281,7 @@ static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1227 int rate = substream->runtime->rate; 1281 int rate = substream->runtime->rate;
1228 int err, do_spdif, do_ac3 = 0; 1282 int err, do_spdif, do_ac3 = 0;
1229 1283
1230 do_spdif = ((rate == 44100 || rate == 48000) && 1284 do_spdif = (rate >= 44100 &&
1231 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1285 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1232 substream->runtime->channels == 2); 1286 substream->runtime->channels == 2);
1233 if (do_spdif && cm->can_ac3_hw) 1287 if (do_spdif && cm->can_ac3_hw)
@@ -1252,11 +1306,75 @@ static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream
1252 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1306 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1253} 1307}
1254 1308
1309/*
1310 * Apparently, the samples last played on channel A stay in some buffer, even
1311 * after the channel is reset, and get added to the data for the rear DACs when
1312 * playing a multichannel stream on channel B. This is likely to generate
1313 * wraparounds and thus distortions.
1314 * To avoid this, we play at least one zero sample after the actual stream has
1315 * stopped.
1316 */
1317static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1318{
1319 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1320 unsigned int reg, val;
1321
1322 if (rec->needs_silencing && runtime && runtime->dma_area) {
1323 /* set up a small silence buffer */
1324 memset(runtime->dma_area, 0, PAGE_SIZE);
1325 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1326 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1327 snd_cmipci_write(cm, reg, val);
1328
1329 /* configure for 16 bits, 2 channels, 8 kHz */
1330 if (runtime->channels > 2)
1331 set_dac_channels(cm, rec, 2);
1332 spin_lock_irq(&cm->reg_lock);
1333 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1334 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1335 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1336 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1337 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1338 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1339 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1340 if (cm->chip_version == 68) {
1341 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
1342 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
1343 }
1344 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1345
1346 /* start stream (we don't need interrupts) */
1347 cm->ctrl |= CM_CHEN0 << rec->ch;
1348 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1349 spin_unlock_irq(&cm->reg_lock);
1350
1351 msleep(1);
1352
1353 /* stop and reset stream */
1354 spin_lock_irq(&cm->reg_lock);
1355 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1356 val = CM_RST_CH0 << rec->ch;
1357 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1358 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1359 spin_unlock_irq(&cm->reg_lock);
1360
1361 rec->needs_silencing = 0;
1362 }
1363}
1364
1255static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) 1365static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1256{ 1366{
1257 struct cmipci *cm = snd_pcm_substream_chip(substream); 1367 struct cmipci *cm = snd_pcm_substream_chip(substream);
1258 setup_spdif_playback(cm, substream, 0, 0); 1368 setup_spdif_playback(cm, substream, 0, 0);
1259 restore_mixer_state(cm); 1369 restore_mixer_state(cm);
1370 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1371 return snd_cmipci_hw_free(substream);
1372}
1373
1374static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1375{
1376 struct cmipci *cm = snd_pcm_substream_chip(substream);
1377 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1260 return snd_cmipci_hw_free(substream); 1378 return snd_cmipci_hw_free(substream);
1261} 1379}
1262 1380
@@ -1515,7 +1633,11 @@ static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1515 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1633 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1516 return err; 1634 return err;
1517 runtime->hw = snd_cmipci_playback; 1635 runtime->hw = snd_cmipci_playback;
1518 runtime->hw.channels_max = cm->max_channels; 1636 if (cm->chip_version == 68) {
1637 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1638 SNDRV_PCM_RATE_96000;
1639 runtime->hw.rate_max = 96000;
1640 }
1519 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1641 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1520 cm->dig_pcm_status = cm->dig_status; 1642 cm->dig_pcm_status = cm->dig_status;
1521 return 0; 1643 return 0;
@@ -1558,9 +1680,14 @@ static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1558 else if (cm->max_channels == 8) 1680 else if (cm->max_channels == 8)
1559 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1681 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1560 } 1682 }
1561 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1562 } 1683 }
1563 mutex_unlock(&cm->open_mutex); 1684 mutex_unlock(&cm->open_mutex);
1685 if (cm->chip_version == 68) {
1686 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1687 SNDRV_PCM_RATE_96000;
1688 runtime->hw.rate_max = 96000;
1689 }
1690 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1564 return 0; 1691 return 0;
1565} 1692}
1566 1693
@@ -1574,8 +1701,15 @@ static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1574 return err; 1701 return err;
1575 if (cm->can_ac3_hw) { 1702 if (cm->can_ac3_hw) {
1576 runtime->hw = snd_cmipci_playback_spdif; 1703 runtime->hw = snd_cmipci_playback_spdif;
1577 if (cm->chip_version >= 37) 1704 if (cm->chip_version >= 37) {
1578 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1705 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1706 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1707 }
1708 if (cm->chip_version == 68) {
1709 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1710 SNDRV_PCM_RATE_96000;
1711 runtime->hw.rate_max = 96000;
1712 }
1579 } else { 1713 } else {
1580 runtime->hw = snd_cmipci_playback_iec958_subframe; 1714 runtime->hw = snd_cmipci_playback_iec958_subframe;
1581 } 1715 }
@@ -1668,7 +1802,7 @@ static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1668 .close = snd_cmipci_playback2_close, 1802 .close = snd_cmipci_playback2_close,
1669 .ioctl = snd_pcm_lib_ioctl, 1803 .ioctl = snd_pcm_lib_ioctl,
1670 .hw_params = snd_cmipci_playback2_hw_params, 1804 .hw_params = snd_cmipci_playback2_hw_params,
1671 .hw_free = snd_cmipci_hw_free, 1805 .hw_free = snd_cmipci_playback2_hw_free,
1672 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1806 .prepare = snd_cmipci_capture_prepare, /* channel B */
1673 .trigger = snd_cmipci_capture_trigger, /* channel B */ 1807 .trigger = snd_cmipci_capture_trigger, /* channel B */
1674 .pointer = snd_cmipci_capture_pointer, /* channel B */ 1808 .pointer = snd_cmipci_capture_pointer, /* channel B */
@@ -2139,15 +2273,7 @@ struct cmipci_switch_args {
2139 */ 2273 */
2140}; 2274};
2141 2275
2142static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol, 2276#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2143 struct snd_ctl_elem_info *uinfo)
2144{
2145 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2146 uinfo->count = 1;
2147 uinfo->value.integer.min = 0;
2148 uinfo->value.integer.max = 1;
2149 return 0;
2150}
2151 2277
2152static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2278static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2153 struct snd_ctl_elem_value *ucontrol, 2279 struct snd_ctl_elem_value *ucontrol,
@@ -2260,8 +2386,8 @@ DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* rever
2260DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); 2386DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2261#endif 2387#endif
2262DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2388DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2263// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); 2389// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2264// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); 2390// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2265// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2391// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2266DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2392DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2267 2393
@@ -2331,11 +2457,11 @@ static inline unsigned int get_line_in_mode(struct cmipci *cm)
2331 unsigned int val; 2457 unsigned int val;
2332 if (cm->chip_version >= 39) { 2458 if (cm->chip_version >= 39) {
2333 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2459 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2334 if (val & CM_LINE_AS_BASS) 2460 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2335 return 2; 2461 return 2;
2336 } 2462 }
2337 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2463 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2338 if (val & CM_SPK4) 2464 if (val & CM_REAR2LIN)
2339 return 1; 2465 return 1;
2340 return 0; 2466 return 0;
2341} 2467}
@@ -2359,13 +2485,13 @@ static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2359 2485
2360 spin_lock_irq(&cm->reg_lock); 2486 spin_lock_irq(&cm->reg_lock);
2361 if (ucontrol->value.enumerated.item[0] == 2) 2487 if (ucontrol->value.enumerated.item[0] == 2)
2362 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2488 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2363 else 2489 else
2364 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2490 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2365 if (ucontrol->value.enumerated.item[0] == 1) 2491 if (ucontrol->value.enumerated.item[0] == 1)
2366 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2492 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2367 else 2493 else
2368 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2494 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2369 spin_unlock_irq(&cm->reg_lock); 2495 spin_unlock_irq(&cm->reg_lock);
2370 return change; 2496 return change;
2371} 2497}
@@ -2583,19 +2709,18 @@ static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2583 struct snd_info_buffer *buffer) 2709 struct snd_info_buffer *buffer)
2584{ 2710{
2585 struct cmipci *cm = entry->private_data; 2711 struct cmipci *cm = entry->private_data;
2586 int i; 2712 int i, v;
2587 2713
2588 snd_iprintf(buffer, "%s\n\n", cm->card->longname); 2714 snd_iprintf(buffer, "%s\n", cm->card->longname);
2589 for (i = 0; i < 0x40; i++) { 2715 for (i = 0; i < 0x94; i++) {
2590 int v = inb(cm->iobase + i); 2716 if (i == 0x28)
2717 i = 0x90;
2718 v = inb(cm->iobase + i);
2591 if (i % 4 == 0) 2719 if (i % 4 == 0)
2592 snd_iprintf(buffer, "%02x: ", i); 2720 snd_iprintf(buffer, "\n%02x:", i);
2593 snd_iprintf(buffer, "%02x", v); 2721 snd_iprintf(buffer, " %02x", v);
2594 if (i % 4 == 3)
2595 snd_iprintf(buffer, "\n");
2596 else
2597 snd_iprintf(buffer, " ");
2598 } 2722 }
2723 snd_iprintf(buffer, "\n");
2599} 2724}
2600 2725
2601static void __devinit snd_cmipci_proc_init(struct cmipci *cm) 2726static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
@@ -2633,46 +2758,40 @@ static void __devinit query_chip(struct cmipci *cm)
2633 if (! detect) { 2758 if (! detect) {
2634 /* check reg 08h, bit 24-28 */ 2759 /* check reg 08h, bit 24-28 */
2635 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2760 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2636 if (! detect) { 2761 switch (detect) {
2762 case 0:
2637 cm->chip_version = 33; 2763 cm->chip_version = 33;
2638 cm->max_channels = 2;
2639 if (cm->do_soft_ac3) 2764 if (cm->do_soft_ac3)
2640 cm->can_ac3_sw = 1; 2765 cm->can_ac3_sw = 1;
2641 else 2766 else
2642 cm->can_ac3_hw = 1; 2767 cm->can_ac3_hw = 1;
2643 cm->has_dual_dac = 1; 2768 break;
2644 } else { 2769 case CM_CHIP_037:
2645 cm->chip_version = 37; 2770 cm->chip_version = 37;
2646 cm->max_channels = 2;
2647 cm->can_ac3_hw = 1; 2771 cm->can_ac3_hw = 1;
2648 cm->has_dual_dac = 1; 2772 break;
2773 default:
2774 cm->chip_version = 39;
2775 cm->can_ac3_hw = 1;
2776 break;
2649 } 2777 }
2778 cm->max_channels = 2;
2650 } else { 2779 } else {
2651 /* check reg 0Ch, bit 26 */ 2780 if (detect & CM_CHIP_039) {
2652 if (detect & CM_CHIP_8768) {
2653 cm->chip_version = 68;
2654 cm->max_channels = 8;
2655 cm->can_ac3_hw = 1;
2656 cm->has_dual_dac = 1;
2657 cm->can_multi_ch = 1;
2658 } else if (detect & CM_CHIP_055) {
2659 cm->chip_version = 55;
2660 cm->max_channels = 6;
2661 cm->can_ac3_hw = 1;
2662 cm->has_dual_dac = 1;
2663 cm->can_multi_ch = 1;
2664 } else if (detect & CM_CHIP_039) {
2665 cm->chip_version = 39; 2781 cm->chip_version = 39;
2666 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2782 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2667 cm->max_channels = 6; 2783 cm->max_channels = 6;
2668 else 2784 else
2669 cm->max_channels = 4; 2785 cm->max_channels = 4;
2670 cm->can_ac3_hw = 1; 2786 } else if (detect & CM_CHIP_8768) {
2671 cm->has_dual_dac = 1; 2787 cm->chip_version = 68;
2672 cm->can_multi_ch = 1; 2788 cm->max_channels = 8;
2673 } else { 2789 } else {
2674 printk(KERN_ERR "chip %x version not supported\n", detect); 2790 cm->chip_version = 55;
2791 cm->max_channels = 6;
2675 } 2792 }
2793 cm->can_ac3_hw = 1;
2794 cm->can_multi_ch = 1;
2676 } 2795 }
2677} 2796}
2678 2797
@@ -2782,10 +2901,14 @@ static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2782 if (!fm_port) 2901 if (!fm_port)
2783 goto disable_fm; 2902 goto disable_fm;
2784 2903
2785 /* first try FM regs in PCI port range */ 2904 if (cm->chip_version >= 39) {
2786 iosynth = cm->iobase + CM_REG_FM_PCI; 2905 /* first try FM regs in PCI port range */
2787 err = snd_opl3_create(cm->card, iosynth, iosynth + 2, 2906 iosynth = cm->iobase + CM_REG_FM_PCI;
2788 OPL3_HW_OPL3, 1, &opl3); 2907 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2908 OPL3_HW_OPL3, 1, &opl3);
2909 } else {
2910 err = -EIO;
2911 }
2789 if (err < 0) { 2912 if (err < 0) {
2790 /* then try legacy ports */ 2913 /* then try legacy ports */
2791 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2914 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
@@ -2829,9 +2952,10 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2829 static struct snd_device_ops ops = { 2952 static struct snd_device_ops ops = {
2830 .dev_free = snd_cmipci_dev_free, 2953 .dev_free = snd_cmipci_dev_free,
2831 }; 2954 };
2832 unsigned int val = 0; 2955 unsigned int val;
2833 long iomidi; 2956 long iomidi;
2834 int integrated_midi; 2957 int integrated_midi = 0;
2958 char modelstr[16];
2835 int pcm_index, pcm_spdif_index; 2959 int pcm_index, pcm_spdif_index;
2836 static struct pci_device_id intel_82437vx[] = { 2960 static struct pci_device_id intel_82437vx[] = {
2837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 2961 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
@@ -2904,6 +3028,8 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2904#endif 3028#endif
2905 3029
2906 /* initialize codec registers */ 3030 /* initialize codec registers */
3031 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3032 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
2907 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 3033 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2908 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3034 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2909 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3035 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
@@ -2917,6 +3043,10 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2917#else 3043#else
2918 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 3044 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2919#endif 3045#endif
3046 if (cm->chip_version) {
3047 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3048 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3049 }
2920 /* Set Bus Master Request */ 3050 /* Set Bus Master Request */
2921 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 3051 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2922 3052
@@ -2931,15 +3061,55 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2931 break; 3061 break;
2932 } 3062 }
2933 3063
3064 if (cm->chip_version < 68) {
3065 val = pci->device < 0x110 ? 8338 : 8738;
3066 } else {
3067 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3068 case 0:
3069 val = 8769;
3070 break;
3071 case 2:
3072 val = 8762;
3073 break;
3074 default:
3075 switch ((pci->subsystem_vendor << 16) |
3076 pci->subsystem_device) {
3077 case 0x13f69761:
3078 case 0x584d3741:
3079 case 0x584d3751:
3080 case 0x584d3761:
3081 case 0x584d3771:
3082 case 0x72848384:
3083 val = 8770;
3084 break;
3085 default:
3086 val = 8768;
3087 break;
3088 }
3089 }
3090 }
3091 sprintf(card->shortname, "C-Media CMI%d", val);
3092 if (cm->chip_version < 68)
3093 sprintf(modelstr, " (model %d)", cm->chip_version);
3094 else
3095 modelstr[0] = '\0';
3096 sprintf(card->longname, "%s%s at %#lx, irq %i",
3097 card->shortname, modelstr, cm->iobase, cm->irq);
3098
2934 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 3099 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2935 snd_cmipci_free(cm); 3100 snd_cmipci_free(cm);
2936 return err; 3101 return err;
2937 } 3102 }
2938 3103
2939 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff; 3104 if (cm->chip_version >= 39) {
2940 if (integrated_midi && mpu_port[dev] == 1) 3105 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
2941 iomidi = cm->iobase + CM_REG_MPU_PCI; 3106 if (val != 0x00 && val != 0xff) {
2942 else { 3107 iomidi = cm->iobase + CM_REG_MPU_PCI;
3108 integrated_midi = 1;
3109 }
3110 }
3111 if (!integrated_midi) {
3112 val = 0;
2943 iomidi = mpu_port[dev]; 3113 iomidi = mpu_port[dev];
2944 switch (iomidi) { 3114 switch (iomidi) {
2945 case 0x320: val = CM_VMPU_320; break; 3115 case 0x320: val = CM_VMPU_320; break;
@@ -2953,11 +3123,21 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2953 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 3123 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2954 /* enable UART */ 3124 /* enable UART */
2955 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 3125 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3126 if (inb(iomidi + 1) == 0xff) {
3127 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3128 " at %#lx\n", iomidi);
3129 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3130 CM_UART_EN);
3131 iomidi = 0;
3132 }
2956 } 3133 }
2957 } 3134 }
2958 3135
2959 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0) 3136 if (cm->chip_version < 68) {
2960 return err; 3137 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3138 if (err < 0)
3139 return err;
3140 }
2961 3141
2962 /* reset mixer */ 3142 /* reset mixer */
2963 snd_cmipci_mixer_write(cm, 0, 0); 3143 snd_cmipci_mixer_write(cm, 0, 0);
@@ -2969,11 +3149,9 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
2969 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 3149 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2970 return err; 3150 return err;
2971 pcm_index++; 3151 pcm_index++;
2972 if (cm->has_dual_dac) { 3152 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2973 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 3153 return err;
2974 return err; 3154 pcm_index++;
2975 pcm_index++;
2976 }
2977 if (cm->can_ac3_hw || cm->can_ac3_sw) { 3155 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2978 pcm_spdif_index = pcm_index; 3156 pcm_spdif_index = pcm_index;
2979 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 3157 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
@@ -3057,15 +3235,6 @@ static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3057 } 3235 }
3058 card->private_data = cm; 3236 card->private_data = cm;
3059 3237
3060 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3061 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3062 card->shortname,
3063 cm->chip_version,
3064 cm->iobase,
3065 cm->irq);
3066
3067 //snd_printd("%s is detected\n", card->longname);
3068
3069 if ((err = snd_card_register(card)) < 0) { 3238 if ((err = snd_card_register(card)) < 0) {
3070 snd_card_free(card); 3239 snd_card_free(card);
3071 return err; 3240 return err;
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-02 14:47:03 -0400