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-rw-r--r--sound/pci/ca0106/ca0106.h47
1 files changed, 45 insertions, 2 deletions
diff --git a/sound/pci/ca0106/ca0106.h b/sound/pci/ca0106/ca0106.h
index a0420bc63f0b..7ad03c6afd42 100644
--- a/sound/pci/ca0106/ca0106.h
+++ b/sound/pci/ca0106/ca0106.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk> 2 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
3 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit 3 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
4 * Version: 0.0.21 4 * Version: 0.0.22
5 * 5 *
6 * FEATURES currently supported: 6 * FEATURES currently supported:
7 * See ca0106_main.c for features. 7 * See ca0106_main.c for features.
@@ -47,6 +47,8 @@
47 * Added GPIO info for SB Live 24bit. 47 * Added GPIO info for SB Live 24bit.
48 * 0.0.21 48 * 0.0.21
49 * Implement support for Line-in capture on SB Live 24bit. 49 * Implement support for Line-in capture on SB Live 24bit.
50 * 0.0.22
51 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
50 * 52 *
51 * 53 *
52 * This code was initally based on code from ALSA's emu10k1x.c which is: 54 * This code was initally based on code from ALSA's emu10k1x.c which is:
@@ -552,6 +554,44 @@
552#define CONTROL_CENTER_LFE_CHANNEL 1 554#define CONTROL_CENTER_LFE_CHANNEL 1
553#define CONTROL_UNKNOWN_CHANNEL 2 555#define CONTROL_UNKNOWN_CHANNEL 2
554 556
557
558/* Based on WM8768 Datasheet Rev 4.2 page 32 */
559#define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */
560#define SPI_REG_SHIFT 9 /* followed by 9 bits of data */
561
562/* They really do label the bit for the 4th channel "4" and not "3" */
563#define SPI_DMUTE0_REG 9
564#define SPI_DMUTE1_REG 9
565#define SPI_DMUTE2_REG 9
566#define SPI_DMUTE4_REG 15
567#define SPI_DMUTE0_BIT 3
568#define SPI_DMUTE1_BIT 4
569#define SPI_DMUTE2_BIT 5
570#define SPI_DMUTE4_BIT 2
571
572#define SPI_PHASE0_REG 3
573#define SPI_PHASE1_REG 3
574#define SPI_PHASE2_REG 3
575#define SPI_PHASE4_REG 15
576#define SPI_PHASE0_BIT 6
577#define SPI_PHASE1_BIT 7
578#define SPI_PHASE2_BIT 8
579#define SPI_PHASE4_BIT 3
580
581#define SPI_PDWN_REG 2 /* power down all DACs */
582#define SPI_PDWN_BIT 2
583#define SPI_DACD0_REG 10 /* power down individual DACs */
584#define SPI_DACD1_REG 10
585#define SPI_DACD2_REG 10
586#define SPI_DACD4_REG 15
587#define SPI_DACD0_BIT 1
588#define SPI_DACD1_BIT 2
589#define SPI_DACD2_BIT 3
590#define SPI_DACD4_BIT 1
591
592#define SPI_PWRDNALL_REG 10 /* power down everything */
593#define SPI_PWRDNALL_BIT 4
594
555#include "ca_midi.h" 595#include "ca_midi.h"
556 596
557struct snd_ca0106; 597struct snd_ca0106;
@@ -611,6 +651,8 @@ struct snd_ca0106 {
611 651
612 struct snd_ca_midi midi; 652 struct snd_ca_midi midi;
613 struct snd_ca_midi midi2; 653 struct snd_ca_midi midi2;
654
655 u16 spi_dac_reg[16];
614}; 656};
615 657
616int snd_ca0106_mixer(struct snd_ca0106 *emu); 658int snd_ca0106_mixer(struct snd_ca0106 *emu);
@@ -627,4 +669,5 @@ void snd_ca0106_ptr_write(struct snd_ca0106 *emu,
627 669
628int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value); 670int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value);
629 671
630 672int snd_ca0106_spi_write(struct snd_ca0106 * emu,
673 unsigned int data);