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path: root/sound/pci/ca0106/ca0106.h
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Diffstat (limited to 'sound/pci/ca0106/ca0106.h')
-rw-r--r--sound/pci/ca0106/ca0106.h79
1 files changed, 65 insertions, 14 deletions
diff --git a/sound/pci/ca0106/ca0106.h b/sound/pci/ca0106/ca0106.h
index 47d923821403..75da1746e758 100644
--- a/sound/pci/ca0106/ca0106.h
+++ b/sound/pci/ca0106/ca0106.h
@@ -559,38 +559,89 @@
559#define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */ 559#define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */
560#define SPI_REG_SHIFT 9 /* followed by 9 bits of data */ 560#define SPI_REG_SHIFT 9 /* followed by 9 bits of data */
561 561
562#define SPI_LDA1_REG 0 /* digital attenuation */
563#define SPI_RDA1_REG 1
564#define SPI_LDA2_REG 4
565#define SPI_RDA2_REG 5
566#define SPI_LDA3_REG 6
567#define SPI_RDA3_REG 7
568#define SPI_LDA4_REG 13
569#define SPI_RDA4_REG 14
570#define SPI_MASTDA_REG 8
571
572#define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */
573#define SPI_DA_BIT_0dB 0xff /* 0 dB */
574#define SPI_DA_BIT_infdB 0x00 /* inf dB attenuation (mute) */
575
576#define SPI_PL_REG 2
577#define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */
578#define SPI_PL_BIT_L_L (1<<5) /* left channel = left */
579#define SPI_PL_BIT_L_R (2<<5) /* left channel = right */
580#define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */
581#define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */
582#define SPI_PL_BIT_R_L (1<<7) /* right channel = left */
583#define SPI_PL_BIT_R_R (2<<7) /* right channel = right */
584#define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */
585#define SPI_IZD_REG 2
586#define SPI_IZD_BIT (1<<4) /* infinite zero detect */
587
588#define SPI_FMT_REG 3
589#define SPI_FMT_BIT_RJ (0<<0) /* right justified mode */
590#define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */
591#define SPI_FMT_BIT_I2S (2<<0) /* I2S mode */
592#define SPI_FMT_BIT_DSP (3<<0) /* DSP Modes A or B */
593#define SPI_LRP_REG 3
594#define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */
595#define SPI_BCP_REG 3
596#define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */
597#define SPI_IWL_REG 3
598#define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */
599#define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */
600#define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */
601#define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */
602
603#define SPI_MS_REG 10
604#define SPI_MS_BIT (1<<5) /* master mode */
605#define SPI_RATE_REG 10 /* only applies in master mode */
606#define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */
607#define SPI_RATE_BIT_192 (1<<6)
608#define SPI_RATE_BIT_256 (2<<6)
609#define SPI_RATE_BIT_384 (3<<6)
610#define SPI_RATE_BIT_512 (4<<6)
611#define SPI_RATE_BIT_768 (5<<6)
612
562/* They really do label the bit for the 4th channel "4" and not "3" */ 613/* They really do label the bit for the 4th channel "4" and not "3" */
563#define SPI_DMUTE0_REG 9 614#define SPI_DMUTE0_REG 9
564#define SPI_DMUTE1_REG 9 615#define SPI_DMUTE1_REG 9
565#define SPI_DMUTE2_REG 9 616#define SPI_DMUTE2_REG 9
566#define SPI_DMUTE4_REG 15 617#define SPI_DMUTE4_REG 15
567#define SPI_DMUTE0_BIT 3 618#define SPI_DMUTE0_BIT (1<<3)
568#define SPI_DMUTE1_BIT 4 619#define SPI_DMUTE1_BIT (1<<4)
569#define SPI_DMUTE2_BIT 5 620#define SPI_DMUTE2_BIT (1<<5)
570#define SPI_DMUTE4_BIT 2 621#define SPI_DMUTE4_BIT (1<<2)
571 622
572#define SPI_PHASE0_REG 3 623#define SPI_PHASE0_REG 3
573#define SPI_PHASE1_REG 3 624#define SPI_PHASE1_REG 3
574#define SPI_PHASE2_REG 3 625#define SPI_PHASE2_REG 3
575#define SPI_PHASE4_REG 15 626#define SPI_PHASE4_REG 15
576#define SPI_PHASE0_BIT 6 627#define SPI_PHASE0_BIT (1<<6)
577#define SPI_PHASE1_BIT 7 628#define SPI_PHASE1_BIT (1<<7)
578#define SPI_PHASE2_BIT 8 629#define SPI_PHASE2_BIT (1<<8)
579#define SPI_PHASE4_BIT 3 630#define SPI_PHASE4_BIT (1<<3)
580 631
581#define SPI_PDWN_REG 2 /* power down all DACs */ 632#define SPI_PDWN_REG 2 /* power down all DACs */
582#define SPI_PDWN_BIT 2 633#define SPI_PDWN_BIT (1<<2)
583#define SPI_DACD0_REG 10 /* power down individual DACs */ 634#define SPI_DACD0_REG 10 /* power down individual DACs */
584#define SPI_DACD1_REG 10 635#define SPI_DACD1_REG 10
585#define SPI_DACD2_REG 10 636#define SPI_DACD2_REG 10
586#define SPI_DACD4_REG 15 637#define SPI_DACD4_REG 15
587#define SPI_DACD0_BIT 1 638#define SPI_DACD0_BIT (1<<1)
588#define SPI_DACD1_BIT 2 639#define SPI_DACD1_BIT (1<<2)
589#define SPI_DACD2_BIT 3 640#define SPI_DACD2_BIT (1<<3)
590#define SPI_DACD4_BIT 0 /* datasheet error says it's 1 */ 641#define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */
591 642
592#define SPI_PWRDNALL_REG 10 /* power down everything */ 643#define SPI_PWRDNALL_REG 10 /* power down everything */
593#define SPI_PWRDNALL_BIT 4 644#define SPI_PWRDNALL_BIT (1<<4)
594 645
595#include "ca_midi.h" 646#include "ca_midi.h"
596 647