1 files changed, 72 insertions, 63 deletions
diff --git a/sound/pci/azt3328.h b/sound/pci/azt3328.h
index 7e0e79180977..f489bdaf6d40 100644
--- a/sound/pci/azt3328.h
+++ b/sound/pci/azt3328.h
@@ -1,19 +1,17 @@
-#ifndef __SOUND_AZF3328_H
+#ifndef __SOUND_AZT3328_H
-#define __SOUND_AZF3328_H
+#define __SOUND_AZT3328_H
-/* type argument to use for the I/O functions */
+/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */
-#define WORD_VALUE      0x1000
-#define DWORD_VALUE     0x2000
-#define BYTE_VALUE      0x4000
 /*** main I/O area port indices ***/
 /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
-/* the driver initialisation suggests a layout of 3 main areas:
+/* the driver initialisation suggests a layout of 4 main areas:
- * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe DirectX
+ * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??).
- * timer ???). and probably another area from 0x60 to 0x6f
+ * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
- * (IRQ management, power management etc. ???). */
+ * power management etc.???). */
-/* playback area */
-#define IDX_IO_PLAY_FLAGS       0x00
+/** playback area **/
+#define IDX_IO_PLAY_FLAGS       0x00 /* PU:0x0000 */
     /* able to reactivate output after output muting due to 8/16bit
      * output change, just like 0x0002.
      * 0x0001 is the only bit that's able to start the DMA counter */
@@ -29,7 +27,7 @@
  #define DMA_EPILOGUE_SOMETHING        0x0010
  #define DMA_SOMETHING_ELSE            0x0020 /* ??? */
  #define SOMETHING_UNMODIFIABLE        0xffc0 /* unused ? not modifiable */
-#define IDX_IO_PLAY_IRQMASK     0x02
+#define IDX_IO_PLAY_IRQTYPE     0x02 /* PU:0x0001 */
  /* write back to flags in case flags are set, in order to ACK IRQ in handler
   * (bit 1 of port 0x64 indicates interrupt for one of these three types)
   * sometimes in this case it just writes 0xffff to globally ACK all IRQs
@@ -41,36 +39,39 @@
  #define IRQMASK_SOME_STATUS_1         0x0008 /* \ related bits */
  #define IRQMASK_SOME_STATUS_2         0x0010 /* / (checked together in loop) */
  #define IRQMASK_UNMODIFIABLE          0xffe0 /* unused ? not modifiable */
-#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area */
+#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */
-#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area */
+#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */
-#define IDX_IO_PLAY_DMA_LEN_1   0x0c /* length of 1st DMA play area */
+#define IDX_IO_PLAY_DMA_LEN_1   0x0c /* length of 1st DMA play area, PU:0x0000 */
-#define IDX_IO_PLAY_DMA_LEN_2   0x0e /* length of 2nd DMA play area */
+#define IDX_IO_PLAY_DMA_LEN_2   0x0e /* length of 2nd DMA play area, PU:0x0000 */
-#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position  */
+#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
-#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area */
+#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */
-#define IDX_IO_PLAY_SOUNDFORMAT 0x16
+#define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */
  /* all unspecified bits can't be modified */
  #define SOUNDFORMAT_FREQUENCY_MASK    0x000f
+  #define SOUNDFORMAT_XTAL1             0x00
+  #define SOUNDFORMAT_XTAL2             0x01
    /* all _SUSPECTED_ values are not used by Windows drivers, so we don't
     * have any hard facts, only rough measurements */
-    #define SOUNDFORMAT_FREQ_SUSPECTED_4000     0x0c
+    #define SOUNDFORMAT_FREQ_SUSPECTED_4000     0x0c | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_SUSPECTED_4800     0x0a
+    #define SOUNDFORMAT_FREQ_SUSPECTED_4800     0x0a | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_5510               0x0d
+    #define SOUNDFORMAT_FREQ_5510               0x0c | SOUNDFORMAT_XTAL2
-    #define SOUNDFORMAT_FREQ_6620               0x0b
+    #define SOUNDFORMAT_FREQ_6620               0x0a | SOUNDFORMAT_XTAL2
-    #define SOUNDFORMAT_FREQ_8000               0x00 /* also 0x0e ? */
+    #define SOUNDFORMAT_FREQ_8000               0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
-    #define SOUNDFORMAT_FREQ_9600               0x08
+    #define SOUNDFORMAT_FREQ_9600               0x08 | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_SUSPECTED_12000    0x09
+    #define SOUNDFORMAT_FREQ_11025              0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
-    #define SOUNDFORMAT_FREQ_11025              0x01 /* also 0x0f ? */
+    #define SOUNDFORMAT_FREQ_SUSPECTED_13240    0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
-    #define SOUNDFORMAT_FREQ_16000              0x02
+    #define SOUNDFORMAT_FREQ_16000              0x02 | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_22050              0x03
+    #define SOUNDFORMAT_FREQ_22050              0x02 | SOUNDFORMAT_XTAL2
-    #define SOUNDFORMAT_FREQ_32000              0x04
+    #define SOUNDFORMAT_FREQ_32000              0x04 | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_44100              0x05
+    #define SOUNDFORMAT_FREQ_44100              0x04 | SOUNDFORMAT_XTAL2
-    #define SOUNDFORMAT_FREQ_48000              0x06
+    #define SOUNDFORMAT_FREQ_48000              0x06 | SOUNDFORMAT_XTAL1
-    #define SOUNDFORMAT_FREQ_SUSPECTED_64000    0x07
+    #define SOUNDFORMAT_FREQ_SUSPECTED_66200    0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
  #define SOUNDFORMAT_FLAG_16BIT        0x0010
  #define SOUNDFORMAT_FLAG_2CHANNELS    0x0020
-/* recording area (see also: playback bit flag definitions) */
-#define IDX_IO_REC_FLAGS        0x20 /* ?? */
+/** recording area (see also: playback bit flag definitions) **/
-#define IDX_IO_REC_IRQMASK      0x22 /* ?? */
+#define IDX_IO_REC_FLAGS        0x20 /* ??, PU:0x0000 */
+#define IDX_IO_REC_IRQTYPE      0x22 /* ??, PU:0x0000 */
  #define IRQ_REC_SOMETHING             0x0001 /* something & ACK */
  #define IRQ_FINISHED_RECBUF_1         0x0002 /* 1st dmabuf finished & ACK */
  #define IRQ_FINISHED_RECBUF_2         0x0004 /* 2nd dmabuf finished & ACK */
@@ -78,39 +79,47 @@
   * but OTOH they are most likely at port 0x22 instead */
  #define IRQMASK_SOME_STATUS_1         0x0008 /* \ related bits */
  #define IRQMASK_SOME_STATUS_2         0x0010 /* / (checked together in loop) */
-#define IDX_IO_REC_DMA_START_1  0x24
+#define IDX_IO_REC_DMA_START_1  0x24 /* PU:0x00000000 */
-#define IDX_IO_REC_DMA_START_2  0x28
+#define IDX_IO_REC_DMA_START_2  0x28 /* PU:0x00000000 */
-#define IDX_IO_REC_DMA_LEN_1    0x2c
+#define IDX_IO_REC_DMA_LEN_1    0x2c /* PU:0x0000 */
-#define IDX_IO_REC_DMA_LEN_2    0x2e
+#define IDX_IO_REC_DMA_LEN_2    0x2e /* PU:0x0000 */
-#define IDX_IO_REC_DMA_CURRPOS  0x30
+#define IDX_IO_REC_DMA_CURRPOS  0x30 /* PU:0x00000000 */
-#define IDX_IO_REC_DMA_CURROFS  0x34
+#define IDX_IO_REC_DMA_CURROFS  0x34 /* PU:0x00000000 */
-#define IDX_IO_REC_SOUNDFORMAT  0x36
+#define IDX_IO_REC_SOUNDFORMAT  0x36 /* PU:0x0000 */
-/* some third area ? (after playback and recording) */
-#define IDX_IO_SOMETHING_FLAGS  0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init */
+/** hmm, what is this I/O area for? MPU401?? (after playback, recording, ???, timer) **/
+#define IDX_IO_SOMETHING_FLAGS  0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */
 /* general */
-#define IDX_IO_60H              0x60 /* writing 0xffff returns 0xffff */
+#define IDX_IO_42H              0x42 /* PU:0x0001 */
-#define IDX_IO_62H              0x62 /* writing to WORD 0x0062 can hang the box ! --> responsible for IRQ management as a whole ?? */
-#define IDX_IO_IRQ63H           0x63 /* FIXME !! */
+/** DirectX timer, main interrupt area (FIXME: and something else?) **/ 
-  #define IO_IRQ63H_SOMETHING           0x04 /* being set in IRQ handler in case port 0x00 had 0x0020 set upon IRQ handler */
+#define IDX_IO_TIMER_VALUE      0x60 /* found this timer area by pure luck :-) */
+  #define TIMER_VALUE_MASK              0x000fffffUL /* timer countdown value; triggers IRQ when timer is finished */
+  #define TIMER_ENABLE_COUNTDOWN        0x01000000UL /* activate the timer countdown */
+  #define TIMER_ENABLE_IRQ              0x02000000UL /* trigger timer IRQ on zero transition */
+  #define TIMER_ACK_IRQ                 0x04000000UL /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) had 0x0020 set upon IRQ handler */
 #define IDX_IO_IRQSTATUS        0x64
  #define IRQ_PLAYBACK                  0x0001
  #define IRQ_RECORDING                 0x0002
  #define IRQ_MPU401                    0x0010
-  #define IRQ_SOMEIRQ                   0x0020 /* ???? */
+  #define IRQ_TIMER                     0x0020 /* DirectX timer */
-  #define IRQ_WHO_KNOWS_UNUSED          0x00e0 /* probably unused */
+  #define IRQ_UNKNOWN1                  0x0040 /* probably unused */
+  #define IRQ_UNKNOWN2                  0x0080 /* probably unused */
 #define IDX_IO_66H              0x66    /* writing 0xffff returns 0x0000 */
-#define IDX_IO_SOME_VALUE       0x68    /* this is always set to 0x3ff, and writable; maybe some buffer limit, but I couldn't find out more */
+#define IDX_IO_SOME_VALUE       0x68    /* this is set to e.g. 0x3ff or 0x300, and writable; maybe some buffer limit, but I couldn't find out more, PU:0x00ff */
-#define IDX_IO_6AH              0x6A    /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback !!! maybe power management ?? */
+#define IDX_IO_6AH              0x6A    /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback!!! maybe power management?? */
-#define IDX_IO_6CH              0x6C    /* this WORD can have all its bits activated ? */
+#define IDX_IO_6CH              0x6C
 #define IDX_IO_6EH              0x6E    /* writing 0xffff returns 0x83fe */
 /* further I/O indices not saved/restored, so probably not used */
 /*** I/O 2 area port indices ***/
 /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ 
 #define IDX_IO2_LEGACY_ADDR     0x04
-  #define LEGACY_SOMETHING              0x01 /* OPL3 ?? */
+  #define LEGACY_SOMETHING              0x01 /* OPL3?? */
  #define LEGACY_JOY                    0x08
 /*** mixer I/O area port indices ***/
 /* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
 * generally spoken: AC97 register index = AZF3328 mixer reg index + 2
@@ -148,18 +157,18 @@
  /* unlisted bits are unmodifiable */
  #define MIXER_ADVCTL1_3DWIDTH_MASK    0x000e
  #define MIXER_ADVCTL1_HIFI3D_MASK     0x0300
-#define IDX_MIXER_ADVCTL2       0x20 /* resembles AC97_GENERAL_PURPOSE reg ! */
+#define IDX_MIXER_ADVCTL2       0x20 /* resembles AC97_GENERAL_PURPOSE reg! */
  /* unlisted bits are unmodifiable */
-  #define MIXER_ADVCTL2_BIT7            0x0080 /* WaveOut 3D Bypass ? mutes WaveOut at LineOut */
+  #define MIXER_ADVCTL2_BIT7            0x0080 /* WaveOut 3D Bypass? mutes WaveOut at LineOut */
-  #define MIXER_ADVCTL2_BIT8            0x0100 /* is this Modem Out Select ? */
+  #define MIXER_ADVCTL2_BIT8            0x0100 /* is this Modem Out Select? */
-  #define MIXER_ADVCTL2_BIT9            0x0200 /* Mono Select Source ? */
+  #define MIXER_ADVCTL2_BIT9            0x0200 /* Mono Select Source? */
-  #define MIXER_ADVCTL2_BIT13           0x2000 /* 3D enable ? */
+  #define MIXER_ADVCTL2_BIT13           0x2000 /* 3D enable? */
  #define MIXER_ADVCTL2_BIT15           0x8000 /* unknown */
  
-#define IDX_MIXER_SOMETHING30H  0x30 /* used, but unknown ??? */
+#define IDX_MIXER_SOMETHING30H  0x30 /* used, but unknown??? */
 /* driver internal flags */
 #define SET_CHAN_LEFT   1
 #define SET_CHAN_RIGHT  2
-#endif /* __SOUND_AZF3328_H  */
+#endif /* __SOUND_AZT3328_H  */

diff --git a/sound/pci/azt3328.h b/sound/pci/azt3328.h index 7e0e79180977..f489bdaf6d40 100644 --- a/sound/pci/azt3328.h +++ b/sound/pci/azt3328.h
@@ -1,19 +1,17 @@
1	#ifndef __SOUND_AZF3328_H	1	#ifndef __SOUND_AZT3328_H
2	#define __SOUND_AZF3328_H	2	#define __SOUND_AZT3328_H
3		3
4	/* type argument to use for the I/O functions */	4	/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */
5	#define WORD_VALUE 0x1000
6	#define DWORD_VALUE 0x2000
7	#define BYTE_VALUE 0x4000
8		5
9	/* main I/O area port indices */	6	/* main I/O area port indices */
10	/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */	7	/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
11	/* the driver initialisation suggests a layout of 3 main areas:	8	/* the driver initialisation suggests a layout of 4 main areas:
12	* from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe DirectX	9	* from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??).
13	* timer ???). and probably another area from 0x60 to 0x6f	10	* And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
14	* (IRQ management, power management etc. ???). */	11	* power management etc.???). */
15	/* playback area */	12
16	#define IDX_IO_PLAY_FLAGS 0x00	13	/ playback area /
		14	#define IDX_IO_PLAY_FLAGS 0x00 /* PU:0x0000 */
17	/* able to reactivate output after output muting due to 8/16bit	15	/* able to reactivate output after output muting due to 8/16bit
18	* output change, just like 0x0002.	16	* output change, just like 0x0002.
19	* 0x0001 is the only bit that's able to start the DMA counter */	17	* 0x0001 is the only bit that's able to start the DMA counter */
@@ -29,7 +27,7 @@
29	#define DMA_EPILOGUE_SOMETHING 0x0010	27	#define DMA_EPILOGUE_SOMETHING 0x0010
30	#define DMA_SOMETHING_ELSE 0x0020 /* ??? */	28	#define DMA_SOMETHING_ELSE 0x0020 /* ??? */
31	#define SOMETHING_UNMODIFIABLE 0xffc0 /* unused ? not modifiable */	29	#define SOMETHING_UNMODIFIABLE 0xffc0 /* unused ? not modifiable */
32	#define IDX_IO_PLAY_IRQMASK 0x02	30	#define IDX_IO_PLAY_IRQTYPE 0x02 /* PU:0x0001 */
33	/* write back to flags in case flags are set, in order to ACK IRQ in handler	31	/* write back to flags in case flags are set, in order to ACK IRQ in handler
34	* (bit 1 of port 0x64 indicates interrupt for one of these three types)	32	* (bit 1 of port 0x64 indicates interrupt for one of these three types)
35	* sometimes in this case it just writes 0xffff to globally ACK all IRQs	33	* sometimes in this case it just writes 0xffff to globally ACK all IRQs
@@ -41,36 +39,39 @@
41	#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */	39	#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
42	#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */	40	#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
43	#define IRQMASK_UNMODIFIABLE 0xffe0 /* unused ? not modifiable */	41	#define IRQMASK_UNMODIFIABLE 0xffe0 /* unused ? not modifiable */
44	#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area */	42	#define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */
45	#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area */	43	#define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */
46	#define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area */	44	#define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area, PU:0x0000 */
47	#define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area */	45	#define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area, PU:0x0000 */
48	#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position */	46	#define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
49	#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area */	47	#define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */
50	#define IDX_IO_PLAY_SOUNDFORMAT 0x16	48	#define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */
51	/* all unspecified bits can't be modified */	49	/* all unspecified bits can't be modified */
52	#define SOUNDFORMAT_FREQUENCY_MASK 0x000f	50	#define SOUNDFORMAT_FREQUENCY_MASK 0x000f
		51	#define SOUNDFORMAT_XTAL1 0x00
		52	#define SOUNDFORMAT_XTAL2 0x01
53	/* all _SUSPECTED_ values are not used by Windows drivers, so we don't	53	/* all _SUSPECTED_ values are not used by Windows drivers, so we don't
54	* have any hard facts, only rough measurements */	54	* have any hard facts, only rough measurements */
55	#define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c	55	#define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c \| SOUNDFORMAT_XTAL1
56	#define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a	56	#define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a \| SOUNDFORMAT_XTAL1
57	#define SOUNDFORMAT_FREQ_5510 0x0d	57	#define SOUNDFORMAT_FREQ_5510 0x0c \| SOUNDFORMAT_XTAL2
58	#define SOUNDFORMAT_FREQ_6620 0x0b	58	#define SOUNDFORMAT_FREQ_6620 0x0a \| SOUNDFORMAT_XTAL2
59	#define SOUNDFORMAT_FREQ_8000 0x00 /* also 0x0e ? */	59	#define SOUNDFORMAT_FREQ_8000 0x00 \| SOUNDFORMAT_XTAL1 /* also 0x0e \| SOUNDFORMAT_XTAL1? */
60	#define SOUNDFORMAT_FREQ_9600 0x08	60	#define SOUNDFORMAT_FREQ_9600 0x08 \| SOUNDFORMAT_XTAL1
61	#define SOUNDFORMAT_FREQ_SUSPECTED_12000 0x09	61	#define SOUNDFORMAT_FREQ_11025 0x00 \| SOUNDFORMAT_XTAL2 /* also 0x0e \| SOUNDFORMAT_XTAL2? */
62	#define SOUNDFORMAT_FREQ_11025 0x01 /* also 0x0f ? */	62	#define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 \| SOUNDFORMAT_XTAL2 /* seems to be 6620 2 /
63	#define SOUNDFORMAT_FREQ_16000 0x02	63	#define SOUNDFORMAT_FREQ_16000 0x02 \| SOUNDFORMAT_XTAL1
64	#define SOUNDFORMAT_FREQ_22050 0x03	64	#define SOUNDFORMAT_FREQ_22050 0x02 \| SOUNDFORMAT_XTAL2
65	#define SOUNDFORMAT_FREQ_32000 0x04	65	#define SOUNDFORMAT_FREQ_32000 0x04 \| SOUNDFORMAT_XTAL1
66	#define SOUNDFORMAT_FREQ_44100 0x05	66	#define SOUNDFORMAT_FREQ_44100 0x04 \| SOUNDFORMAT_XTAL2
67	#define SOUNDFORMAT_FREQ_48000 0x06	67	#define SOUNDFORMAT_FREQ_48000 0x06 \| SOUNDFORMAT_XTAL1
68	#define SOUNDFORMAT_FREQ_SUSPECTED_64000 0x07	68	#define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 \| SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
69	#define SOUNDFORMAT_FLAG_16BIT 0x0010	69	#define SOUNDFORMAT_FLAG_16BIT 0x0010
70	#define SOUNDFORMAT_FLAG_2CHANNELS 0x0020	70	#define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
71	/* recording area (see also: playback bit flag definitions) */	71
72	#define IDX_IO_REC_FLAGS 0x20 /* ?? */	72	/ recording area (see also: playback bit flag definitions) /
73	#define IDX_IO_REC_IRQMASK 0x22 /* ?? */	73	#define IDX_IO_REC_FLAGS 0x20 /* ??, PU:0x0000 */
		74	#define IDX_IO_REC_IRQTYPE 0x22 /* ??, PU:0x0000 */
74	#define IRQ_REC_SOMETHING 0x0001 /* something & ACK */	75	#define IRQ_REC_SOMETHING 0x0001 /* something & ACK */
75	#define IRQ_FINISHED_RECBUF_1 0x0002 /* 1st dmabuf finished & ACK */	76	#define IRQ_FINISHED_RECBUF_1 0x0002 /* 1st dmabuf finished & ACK */
76	#define IRQ_FINISHED_RECBUF_2 0x0004 /* 2nd dmabuf finished & ACK */	77	#define IRQ_FINISHED_RECBUF_2 0x0004 /* 2nd dmabuf finished & ACK */
@@ -78,39 +79,47 @@
78	* but OTOH they are most likely at port 0x22 instead */	79	* but OTOH they are most likely at port 0x22 instead */
79	#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */	80	#define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
80	#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */	81	#define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
81	#define IDX_IO_REC_DMA_START_1 0x24	82	#define IDX_IO_REC_DMA_START_1 0x24 /* PU:0x00000000 */
82	#define IDX_IO_REC_DMA_START_2 0x28	83	#define IDX_IO_REC_DMA_START_2 0x28 /* PU:0x00000000 */
83	#define IDX_IO_REC_DMA_LEN_1 0x2c	84	#define IDX_IO_REC_DMA_LEN_1 0x2c /* PU:0x0000 */
84	#define IDX_IO_REC_DMA_LEN_2 0x2e	85	#define IDX_IO_REC_DMA_LEN_2 0x2e /* PU:0x0000 */
85	#define IDX_IO_REC_DMA_CURRPOS 0x30	86	#define IDX_IO_REC_DMA_CURRPOS 0x30 /* PU:0x00000000 */
86	#define IDX_IO_REC_DMA_CURROFS 0x34	87	#define IDX_IO_REC_DMA_CURROFS 0x34 /* PU:0x00000000 */
87	#define IDX_IO_REC_SOUNDFORMAT 0x36	88	#define IDX_IO_REC_SOUNDFORMAT 0x36 /* PU:0x0000 */
88	/* some third area ? (after playback and recording) */	89
89	#define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init */	90	/ hmm, what is this I/O area for? MPU401?? (after playback, recording, ???, timer) /
		91	#define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */
90	/* general */	92	/* general */
91	#define IDX_IO_60H 0x60 /* writing 0xffff returns 0xffff */	93	#define IDX_IO_42H 0x42 /* PU:0x0001 */
92	#define IDX_IO_62H 0x62 /* writing to WORD 0x0062 can hang the box ! --> responsible for IRQ management as a whole ?? */	94
93	#define IDX_IO_IRQ63H 0x63 /* FIXME !! */	95	/ DirectX timer, main interrupt area (FIXME: and something else?) /
94	#define IO_IRQ63H_SOMETHING 0x04 /* being set in IRQ handler in case port 0x00 had 0x0020 set upon IRQ handler */	96	#define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
		97	#define TIMER_VALUE_MASK 0x000fffffUL /* timer countdown value; triggers IRQ when timer is finished */
		98	#define TIMER_ENABLE_COUNTDOWN 0x01000000UL /* activate the timer countdown */
		99	#define TIMER_ENABLE_IRQ 0x02000000UL /* trigger timer IRQ on zero transition */
		100	#define TIMER_ACK_IRQ 0x04000000UL /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) had 0x0020 set upon IRQ handler */
95	#define IDX_IO_IRQSTATUS 0x64	101	#define IDX_IO_IRQSTATUS 0x64
96	#define IRQ_PLAYBACK 0x0001	102	#define IRQ_PLAYBACK 0x0001
97	#define IRQ_RECORDING 0x0002	103	#define IRQ_RECORDING 0x0002
98	#define IRQ_MPU401 0x0010	104	#define IRQ_MPU401 0x0010
99	#define IRQ_SOMEIRQ 0x0020 /* ???? */	105	#define IRQ_TIMER 0x0020 /* DirectX timer */
100	#define IRQ_WHO_KNOWS_UNUSED 0x00e0 /* probably unused */	106	#define IRQ_UNKNOWN1 0x0040 /* probably unused */
		107	#define IRQ_UNKNOWN2 0x0080 /* probably unused */
101	#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */	108	#define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
102	#define IDX_IO_SOME_VALUE 0x68 /* this is always set to 0x3ff, and writable; maybe some buffer limit, but I couldn't find out more */	109	#define IDX_IO_SOME_VALUE 0x68 /* this is set to e.g. 0x3ff or 0x300, and writable; maybe some buffer limit, but I couldn't find out more, PU:0x00ff */
103	#define IDX_IO_6AH 0x6A /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback !!! maybe power management ?? */	110	#define IDX_IO_6AH 0x6A /* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback!!! maybe power management?? */
104	#define IDX_IO_6CH 0x6C /* this WORD can have all its bits activated ? */	111	#define IDX_IO_6CH 0x6C
105	#define IDX_IO_6EH 0x6E /* writing 0xffff returns 0x83fe */	112	#define IDX_IO_6EH 0x6E /* writing 0xffff returns 0x83fe */
106	/* further I/O indices not saved/restored, so probably not used */	113	/* further I/O indices not saved/restored, so probably not used */
107		114
		115
108	/* I/O 2 area port indices */	116	/* I/O 2 area port indices */
109	/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */	117	/* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
110	#define IDX_IO2_LEGACY_ADDR 0x04	118	#define IDX_IO2_LEGACY_ADDR 0x04
111	#define LEGACY_SOMETHING 0x01 /* OPL3 ?? */	119	#define LEGACY_SOMETHING 0x01 /* OPL3?? */
112	#define LEGACY_JOY 0x08	120	#define LEGACY_JOY 0x08
113		121
		122
114	/* mixer I/O area port indices */	123	/* mixer I/O area port indices */
115	/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)	124	/* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
116	* generally spoken: AC97 register index = AZF3328 mixer reg index + 2	125	* generally spoken: AC97 register index = AZF3328 mixer reg index + 2
@@ -148,18 +157,18 @@
148	/* unlisted bits are unmodifiable */	157	/* unlisted bits are unmodifiable */
149	#define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e	158	#define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e
150	#define MIXER_ADVCTL1_HIFI3D_MASK 0x0300	159	#define MIXER_ADVCTL1_HIFI3D_MASK 0x0300
151	#define IDX_MIXER_ADVCTL2 0x20 /* resembles AC97_GENERAL_PURPOSE reg ! */	160	#define IDX_MIXER_ADVCTL2 0x20 /* resembles AC97_GENERAL_PURPOSE reg! */
152	/* unlisted bits are unmodifiable */	161	/* unlisted bits are unmodifiable */
153	#define MIXER_ADVCTL2_BIT7 0x0080 /* WaveOut 3D Bypass ? mutes WaveOut at LineOut */	162	#define MIXER_ADVCTL2_BIT7 0x0080 /* WaveOut 3D Bypass? mutes WaveOut at LineOut */
154	#define MIXER_ADVCTL2_BIT8 0x0100 /* is this Modem Out Select ? */	163	#define MIXER_ADVCTL2_BIT8 0x0100 /* is this Modem Out Select? */
155	#define MIXER_ADVCTL2_BIT9 0x0200 /* Mono Select Source ? */	164	#define MIXER_ADVCTL2_BIT9 0x0200 /* Mono Select Source? */
156	#define MIXER_ADVCTL2_BIT13 0x2000 /* 3D enable ? */	165	#define MIXER_ADVCTL2_BIT13 0x2000 /* 3D enable? */
157	#define MIXER_ADVCTL2_BIT15 0x8000 /* unknown */	166	#define MIXER_ADVCTL2_BIT15 0x8000 /* unknown */
158		167
159	#define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown ??? */	168	#define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */
160		169
161	/* driver internal flags */	170	/* driver internal flags */
162	#define SET_CHAN_LEFT 1	171	#define SET_CHAN_LEFT 1
163	#define SET_CHAN_RIGHT 2	172	#define SET_CHAN_RIGHT 2
164		173
165	#endif /* __SOUND_AZF3328_H */	174	#endif /* __SOUND_AZT3328_H */