diff options
Diffstat (limited to 'sound/pci/au88x0/au8820.h')
-rw-r--r-- | sound/pci/au88x0/au8820.h | 209 |
1 files changed, 209 insertions, 0 deletions
diff --git a/sound/pci/au88x0/au8820.h b/sound/pci/au88x0/au8820.h new file mode 100644 index 000000000000..be8022e78714 --- /dev/null +++ b/sound/pci/au88x0/au8820.h | |||
@@ -0,0 +1,209 @@ | |||
1 | /* | ||
2 | Aureal Vortex Soundcard driver. | ||
3 | |||
4 | IO addr collected from asp4core.vxd: | ||
5 | function address | ||
6 | 0005D5A0 13004 | ||
7 | 00080674 14004 | ||
8 | 00080AFF 12818 | ||
9 | |||
10 | */ | ||
11 | |||
12 | #define CHIP_AU8820 | ||
13 | |||
14 | #define CARD_NAME "Aureal Vortex 3D Sound Processor" | ||
15 | #define CARD_NAME_SHORT "au8820" | ||
16 | |||
17 | /* Number of ADB and WT channels */ | ||
18 | #define NR_ADB 0x10 | ||
19 | #define NR_WT 0x20 | ||
20 | #define NR_SRC 0x10 | ||
21 | #define NR_A3D 0x00 | ||
22 | #define NR_MIXIN 0x10 | ||
23 | #define NR_MIXOUT 0x10 | ||
24 | |||
25 | |||
26 | /* ADBDMA */ | ||
27 | #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */ | ||
28 | #define POS_MASK 0x00000fff | ||
29 | #define POS_SHIFT 0x0 | ||
30 | #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ | ||
31 | #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ | ||
32 | #define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */ | ||
33 | #define OFFSET_MASK 0x00000fff | ||
34 | #define OFFSET_SHIFT 0x0 | ||
35 | #define IE_MASK 0x00001000 /* interrupt enable. */ | ||
36 | #define IE_SHIFT 0xc | ||
37 | #define DIR_MASK 0x00002000 /* Direction. */ | ||
38 | #define DIR_SHIFT 0xd | ||
39 | #define FMT_MASK 0x0003c000 | ||
40 | #define FMT_SHIFT 0xe | ||
41 | // The masks and shift also work for the wtdma, if not specified otherwise. | ||
42 | #define VORTEX_ADBDMA_BUFCFG0 0x10400 | ||
43 | #define VORTEX_ADBDMA_BUFCFG1 0x10404 | ||
44 | #define VORTEX_ADBDMA_BUFBASE 0x10200 | ||
45 | #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ | ||
46 | #define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */ | ||
47 | |||
48 | /* ADB */ | ||
49 | #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ | ||
50 | #define VORTEX_ADB_RTBASE 0x10800 | ||
51 | #define VORTEX_ADB_RTBASE_COUNT 103 | ||
52 | #define VORTEX_ADB_CHNBASE 0x1099c | ||
53 | #define VORTEX_ADB_CHNBASE_COUNT 22 | ||
54 | #define ROUTE_MASK 0x3fff | ||
55 | #define ADB_MASK 0x7f | ||
56 | #define ADB_SHIFT 0x7 | ||
57 | //#define ADB_MIX_MASK 0xf | ||
58 | /* ADB address */ | ||
59 | #define OFFSET_ADBDMA 0x00 | ||
60 | #define OFFSET_SRCOUT 0x10 /* on channel 0x11 */ | ||
61 | #define OFFSET_SRCIN 0x10 /* on channel < 0x11 */ | ||
62 | #define OFFSET_MIXOUT 0x20 /* source */ | ||
63 | #define OFFSET_MIXIN 0x30 /* sink */ | ||
64 | #define OFFSET_CODECIN 0x48 /* ADB source */ | ||
65 | #define OFFSET_CODECOUT 0x58 /* ADB sink/target */ | ||
66 | #define OFFSET_SPORTOUT 0x60 /* sink */ | ||
67 | #define OFFSET_SPORTIN 0x50 /* source */ | ||
68 | #define OFFSET_EFXOUT 0x50 /* sink */ | ||
69 | #define OFFSET_EFXIN 0x40 /* source */ | ||
70 | #define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */ | ||
71 | #define OFFSET_A3DIN 0x00 | ||
72 | #define OFFSET_WTOUT 0x58 /* */ | ||
73 | |||
74 | /* ADB route translate helper */ | ||
75 | #define ADB_DMA(x) (x + OFFSET_ADBDMA) | ||
76 | #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) | ||
77 | #define ADB_SRCIN(x) (x + OFFSET_SRCIN) | ||
78 | #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) | ||
79 | #define ADB_MIXIN(x) (x + OFFSET_MIXIN) | ||
80 | #define ADB_CODECIN(x) (x + OFFSET_CODECIN) | ||
81 | #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) | ||
82 | #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) | ||
83 | #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */ | ||
84 | #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ | ||
85 | #define ADB_A3DIN(x) (x + OFFSET_A3DIN) | ||
86 | #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT) | ||
87 | |||
88 | /* WTDMA */ | ||
89 | #define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ | ||
90 | #define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ | ||
91 | #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT) | ||
92 | #define WT_SUBBUF_SHIFT 0x15 | ||
93 | #define VORTEX_WTDMA_BUFBASE 0x10000 | ||
94 | #define VORTEX_WTDMA_BUFCFG0 0x10300 | ||
95 | #define VORTEX_WTDMA_BUFCFG1 0x10304 | ||
96 | #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ | ||
97 | |||
98 | #define VORTEX_WT_BASE 0x9000 | ||
99 | |||
100 | /* MIXER */ | ||
101 | #define VORTEX_MIXER_SR 0x9f00 | ||
102 | #define VORTEX_MIXER_CLIP 0x9f80 | ||
103 | #define VORTEX_MIXER_CHNBASE 0x9e40 | ||
104 | #define VORTEX_MIXER_RTBASE 0x9e00 | ||
105 | #define MIXER_RTBASE_SIZE 0x26 | ||
106 | #define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */ | ||
107 | #define VORTEX_MIX_SMP 0x9c00 | ||
108 | |||
109 | /* MIX */ | ||
110 | #define VORTEX_MIX_INVOL_A 0x9000 /* in? */ | ||
111 | #define VORTEX_MIX_INVOL_B 0x8000 /* out? */ | ||
112 | #define VORTEX_MIX_VOL_A 0x9800 | ||
113 | #define VORTEX_MIX_VOL_B 0x8800 | ||
114 | |||
115 | #define VOL_MIN 0x80 /* Input volume when muted. */ | ||
116 | #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ | ||
117 | |||
118 | //#define MIX_OUTL 0xe | ||
119 | //#define MIX_OUTR 0xf | ||
120 | //#define MIX_INL 0xe | ||
121 | //#define MIX_INR 0xf | ||
122 | #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */ | ||
123 | #define MIX_DEFOGAIN 0x08 | ||
124 | |||
125 | /* SRC */ | ||
126 | #define VORTEX_SRCBLOCK_SR 0xccc0 | ||
127 | #define VORTEX_SRC_CHNBASE 0xcc40 | ||
128 | #define VORTEX_SRC_RTBASE 0xcc00 | ||
129 | #define VORTEX_SRC_SOURCE 0xccc4 | ||
130 | #define VORTEX_SRC_SOURCESIZE 0xccc8 | ||
131 | #define VORTEX_SRC_U0 0xce00 | ||
132 | #define VORTEX_SRC_DRIFT0 0xce80 | ||
133 | #define VORTEX_SRC_DRIFT1 0xcec0 | ||
134 | #define VORTEX_SRC_U1 0xcf00 | ||
135 | #define VORTEX_SRC_DRIFT2 0xcf40 | ||
136 | #define VORTEX_SRC_U2 0xcf80 | ||
137 | #define VORTEX_SRC_DATA 0xc800 | ||
138 | #define VORTEX_SRC_DATA0 0xc000 | ||
139 | #define VORTEX_SRC_CONVRATIO 0xce40 | ||
140 | //#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ | ||
141 | //#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ | ||
142 | |||
143 | /* FIFO */ | ||
144 | #define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ | ||
145 | #define VORTEX_FIFO_WTCTRL 0xf840 | ||
146 | #define FIFO_RDONLY 0x00000001 | ||
147 | #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ | ||
148 | #define FIFO_VALID 0x00000010 | ||
149 | #define FIFO_EMPTY 0x00000020 | ||
150 | #define FIFO_U0 0x00001000 /* Unknown. */ | ||
151 | #define FIFO_U1 0x00010000 | ||
152 | #define FIFO_SIZE_BITS 5 | ||
153 | #define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20 | ||
154 | #define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */ | ||
155 | #define VORTEX_FIFO_ADBDATA 0xe000 | ||
156 | #define VORTEX_FIFO_WTDATA 0xe800 | ||
157 | |||
158 | /* CODEC */ | ||
159 | #define VORTEX_CODEC_CTRL 0x11984 | ||
160 | #define VORTEX_CODEC_EN 0x11990 | ||
161 | #define EN_CODEC 0x00000300 | ||
162 | #define EN_SPORT 0x00030000 | ||
163 | #define EN_SPDIF 0x000c0000 | ||
164 | #define VORTEX_CODEC_CHN 0x11880 | ||
165 | #define VORTEX_CODEC_WRITE 0x00800000 | ||
166 | #define VORTEX_CODEC_ADDSHIFT 16 | ||
167 | #define VORTEX_CODEC_ADDMASK 0x7f0000 /* 0x000f0000 */ | ||
168 | #define VORTEX_CODEC_DATSHIFT 0 | ||
169 | #define VORTEX_CODEC_DATMASK 0xffff | ||
170 | #define VORTEX_CODEC_IO 0x11988 | ||
171 | |||
172 | #define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */ | ||
173 | #define VORTEX_SPDIF_CFG0 0x119D0 | ||
174 | #define VORTEX_SPDIF_CFG1 0x119D4 | ||
175 | #define VORTEX_SPDIF_SMPRATE 0x11994 | ||
176 | |||
177 | /* Sample timer */ | ||
178 | #define VORTEX_SMP_TIME 0x11998 | ||
179 | |||
180 | /* IRQ */ | ||
181 | #define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */ | ||
182 | #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */ | ||
183 | |||
184 | #define VORTEX_STAT 0x12808 /* ?? */ | ||
185 | |||
186 | #define VORTEX_CTRL 0x1280c | ||
187 | #define CTRL_MIDI_EN 0x00000001 | ||
188 | #define CTRL_MIDI_PORT 0x00000060 | ||
189 | #define CTRL_GAME_EN 0x00000008 | ||
190 | #define CTRL_GAME_PORT 0x00000e00 | ||
191 | #define CTRL_IRQ_ENABLE 0x4000 | ||
192 | |||
193 | /* write: Timer period config / read: TIMER IRQ ack. */ | ||
194 | #define VORTEX_IRQ_STAT 0x1199c | ||
195 | |||
196 | /* DMA */ | ||
197 | #define VORTEX_DMA_BUFFER 0x10200 | ||
198 | #define VORTEX_ENGINE_CTRL 0x1060c | ||
199 | #define ENGINE_INIT 0x0L | ||
200 | |||
201 | /* MIDI *//* GAME. */ | ||
202 | #define VORTEX_MIDI_DATA 0x11000 | ||
203 | #define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */ | ||
204 | #define VORTEX_GAME_LEGACY 0x11008 | ||
205 | #define VORTEX_CTRL2 0x1100c | ||
206 | #define CTRL2_GAME_ADCMODE 0x40 | ||
207 | #define VORTEX_GAME_AXIS 0x11010 | ||
208 | #define AXIS_SIZE 4 | ||
209 | #define AXIS_RANGE 0x1fff | ||