aboutsummaryrefslogtreecommitdiffstats
path: root/sound/oss/sonicvibes.c
diff options
context:
space:
mode:
Diffstat (limited to 'sound/oss/sonicvibes.c')
-rw-r--r--sound/oss/sonicvibes.c2792
1 files changed, 0 insertions, 2792 deletions
diff --git a/sound/oss/sonicvibes.c b/sound/oss/sonicvibes.c
deleted file mode 100644
index 8ea532d40198..000000000000
--- a/sound/oss/sonicvibes.c
+++ /dev/null
@@ -1,2792 +0,0 @@
1/*****************************************************************************/
2
3/*
4 * sonicvibes.c -- S3 Sonic Vibes audio driver.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to David C. Niemi
23 *
24 *
25 * Module command line parameters:
26 * none so far
27 *
28 *
29 * Supported devices:
30 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
31 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
32 * /dev/midi simple MIDI UART interface, no ioctl
33 *
34 * The card has both an FM and a Wavetable synth, but I have to figure
35 * out first how to drive them...
36 *
37 * Revision history
38 * 06.05.1998 0.1 Initial release
39 * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
40 * First stab at a simple midi interface (no bells&whistles)
41 * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
42 * set_dac_rate in the FMODE_WRITE case in sv_open
43 * Fix hwptr out of bounds (now mpg123 works)
44 * 14.05.1998 0.4 Don't allow excessive interrupt rates
45 * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
46 * 03.08.1998 0.6 Do not include modversions.h
47 * Now mixer behaviour can basically be selected between
48 * "OSS documented" and "OSS actual" behaviour
49 * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
50 * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
51 * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
52 * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
53 * hopefully killed the egcs section type conflict
54 * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
55 * reported by Johan Maes <joma@telindus.be>
56 * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
57 * read/write cannot be executed
58 * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
59 * lockups of the sound chip and revive it. This is basically
60 * an ugly hack, but at least applications using this driver
61 * won't hang forever. I don't know why these lockups happen,
62 * it might well be the motherboard chipset (an early 486 PCI
63 * board with ALI chipset), since every busmastering 100MB
64 * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
65 * exhibit similar behaviour (they work for a couple of packets
66 * and then lock up and can be revived by ifconfig down/up).
67 * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
68 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
69 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
70 * Note: dmaio hack might still be wrong on archs other than i386
71 * 15.06.1999 0.15 Fix bad allocation bug.
72 * Thanks to Deti Fliegl <fliegl@in.tum.de>
73 * 28.06.1999 0.16 Add pci_set_master
74 * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
75 * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
76 * 12.08.1999 0.18 module_init/__setup fixes
77 * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
78 * 31.08.1999 0.20 add spin_lock_init
79 * use new resource allocation to allocate DDMA IO space
80 * replaced current->state = x with set_current_state(x)
81 * 03.09.1999 0.21 change read semantics for MIDI to match
82 * OSS more closely; remove possible wakeup race
83 * 28.10.1999 0.22 More waitqueue races fixed
84 * 01.12.1999 0.23 New argument to allocate_resource
85 * 07.12.1999 0.24 More allocate_resource semantics change
86 * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
87 * Tim Janik's BSE (Bedevilled Sound Engine) found this
88 * use Martin Mares' pci_assign_resource
89 * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
90 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
91 * 12.12.2000 0.28 More dma buffer initializations, patch from
92 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
93 * 31.01.2001 0.29 Register/Unregister gameport
94 * Fix SETTRIGGER non OSS API conformity
95 * 18.05.2001 0.30 PCI probing and error values cleaned up by Marcus
96 * Meissner <mm@caldera.de>
97 * 03.01.2003 0.31 open_mode fixes from Georg Acher <acher@in.tum.de>
98 *
99 */
100
101/*****************************************************************************/
102
103#include <linux/module.h>
104#include <linux/string.h>
105#include <linux/ioport.h>
106#include <linux/interrupt.h>
107#include <linux/wait.h>
108#include <linux/mm.h>
109#include <linux/delay.h>
110#include <linux/sound.h>
111#include <linux/slab.h>
112#include <linux/soundcard.h>
113#include <linux/pci.h>
114#include <linux/init.h>
115#include <linux/poll.h>
116#include <linux/spinlock.h>
117#include <linux/smp_lock.h>
118#include <linux/gameport.h>
119#include <linux/dma-mapping.h>
120#include <linux/mutex.h>
121
122
123#include <asm/io.h>
124#include <asm/uaccess.h>
125
126#include "dm.h"
127
128#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
129#define SUPPORT_JOYSTICK 1
130#endif
131
132/* --------------------------------------------------------------------- */
133
134#undef OSS_DOCUMENTED_MIXER_SEMANTICS
135
136/* --------------------------------------------------------------------- */
137
138#ifndef PCI_VENDOR_ID_S3
139#define PCI_VENDOR_ID_S3 0x5333
140#endif
141#ifndef PCI_DEVICE_ID_S3_SONICVIBES
142#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
143#endif
144
145#define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
146
147#define SV_EXTENT_SB 0x10
148#define SV_EXTENT_ENH 0x10
149#define SV_EXTENT_SYNTH 0x4
150#define SV_EXTENT_MIDI 0x4
151#define SV_EXTENT_GAME 0x8
152#define SV_EXTENT_DMA 0x10
153
154/*
155 * we are not a bridge and thus use a resource for DDMA that is used for bridges but
156 * left empty for normal devices
157 */
158#define RESOURCE_SB 0
159#define RESOURCE_ENH 1
160#define RESOURCE_SYNTH 2
161#define RESOURCE_MIDI 3
162#define RESOURCE_GAME 4
163#define RESOURCE_DDMA 7
164
165#define SV_MIDI_DATA 0
166#define SV_MIDI_COMMAND 1
167#define SV_MIDI_STATUS 1
168
169#define SV_DMA_ADDR0 0
170#define SV_DMA_ADDR1 1
171#define SV_DMA_ADDR2 2
172#define SV_DMA_ADDR3 3
173#define SV_DMA_COUNT0 4
174#define SV_DMA_COUNT1 5
175#define SV_DMA_COUNT2 6
176#define SV_DMA_MODE 0xb
177#define SV_DMA_RESET 0xd
178#define SV_DMA_MASK 0xf
179
180/*
181 * DONT reset the DMA controllers unless you understand
182 * the reset semantics. Assuming reset semantics as in
183 * the 8237 does not work.
184 */
185
186#define DMA_MODE_AUTOINIT 0x10
187#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
188#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
189
190#define SV_CODEC_CONTROL 0
191#define SV_CODEC_INTMASK 1
192#define SV_CODEC_STATUS 2
193#define SV_CODEC_IADDR 4
194#define SV_CODEC_IDATA 5
195
196#define SV_CCTRL_RESET 0x80
197#define SV_CCTRL_INTADRIVE 0x20
198#define SV_CCTRL_WAVETABLE 0x08
199#define SV_CCTRL_REVERB 0x04
200#define SV_CCTRL_ENHANCED 0x01
201
202#define SV_CINTMASK_DMAA 0x01
203#define SV_CINTMASK_DMAC 0x04
204#define SV_CINTMASK_SPECIAL 0x08
205#define SV_CINTMASK_UPDOWN 0x40
206#define SV_CINTMASK_MIDI 0x80
207
208#define SV_CSTAT_DMAA 0x01
209#define SV_CSTAT_DMAC 0x04
210#define SV_CSTAT_SPECIAL 0x08
211#define SV_CSTAT_UPDOWN 0x40
212#define SV_CSTAT_MIDI 0x80
213
214#define SV_CIADDR_TRD 0x80
215#define SV_CIADDR_MCE 0x40
216
217/* codec indirect registers */
218#define SV_CIMIX_ADCINL 0x00
219#define SV_CIMIX_ADCINR 0x01
220#define SV_CIMIX_AUX1INL 0x02
221#define SV_CIMIX_AUX1INR 0x03
222#define SV_CIMIX_CDINL 0x04
223#define SV_CIMIX_CDINR 0x05
224#define SV_CIMIX_LINEINL 0x06
225#define SV_CIMIX_LINEINR 0x07
226#define SV_CIMIX_MICIN 0x08
227#define SV_CIMIX_SYNTHINL 0x0A
228#define SV_CIMIX_SYNTHINR 0x0B
229#define SV_CIMIX_AUX2INL 0x0C
230#define SV_CIMIX_AUX2INR 0x0D
231#define SV_CIMIX_ANALOGINL 0x0E
232#define SV_CIMIX_ANALOGINR 0x0F
233#define SV_CIMIX_PCMINL 0x10
234#define SV_CIMIX_PCMINR 0x11
235
236#define SV_CIGAMECONTROL 0x09
237#define SV_CIDATAFMT 0x12
238#define SV_CIENABLE 0x13
239#define SV_CIUPDOWN 0x14
240#define SV_CIREVISION 0x15
241#define SV_CIADCOUTPUT 0x16
242#define SV_CIDMAABASECOUNT1 0x18
243#define SV_CIDMAABASECOUNT0 0x19
244#define SV_CIDMACBASECOUNT1 0x1c
245#define SV_CIDMACBASECOUNT0 0x1d
246#define SV_CIPCMSR0 0x1e
247#define SV_CIPCMSR1 0x1f
248#define SV_CISYNTHSR0 0x20
249#define SV_CISYNTHSR1 0x21
250#define SV_CIADCCLKSOURCE 0x22
251#define SV_CIADCALTSR 0x23
252#define SV_CIADCPLLM 0x24
253#define SV_CIADCPLLN 0x25
254#define SV_CISYNTHPLLM 0x26
255#define SV_CISYNTHPLLN 0x27
256#define SV_CIUARTCONTROL 0x2a
257#define SV_CIDRIVECONTROL 0x2b
258#define SV_CISRSSPACE 0x2c
259#define SV_CISRSCENTER 0x2d
260#define SV_CIWAVETABLESRC 0x2e
261#define SV_CIANALOGPWRDOWN 0x30
262#define SV_CIDIGITALPWRDOWN 0x31
263
264
265#define SV_CIMIX_ADCSRC_CD 0x20
266#define SV_CIMIX_ADCSRC_DAC 0x40
267#define SV_CIMIX_ADCSRC_AUX2 0x60
268#define SV_CIMIX_ADCSRC_LINE 0x80
269#define SV_CIMIX_ADCSRC_AUX1 0xa0
270#define SV_CIMIX_ADCSRC_MIC 0xc0
271#define SV_CIMIX_ADCSRC_MIXOUT 0xe0
272#define SV_CIMIX_ADCSRC_MASK 0xe0
273
274#define SV_CFMT_STEREO 0x01
275#define SV_CFMT_16BIT 0x02
276#define SV_CFMT_MASK 0x03
277#define SV_CFMT_ASHIFT 0
278#define SV_CFMT_CSHIFT 4
279
280static const unsigned sample_size[] = { 1, 2, 2, 4 };
281static const unsigned sample_shift[] = { 0, 1, 1, 2 };
282
283#define SV_CENABLE_PPE 0x4
284#define SV_CENABLE_RE 0x2
285#define SV_CENABLE_PE 0x1
286
287
288/* MIDI buffer sizes */
289
290#define MIDIINBUF 256
291#define MIDIOUTBUF 256
292
293#define FMODE_MIDI_SHIFT 2
294#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
295#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
296
297#define FMODE_DMFM 0x10
298
299/* --------------------------------------------------------------------- */
300
301struct sv_state {
302 /* magic */
303 unsigned int magic;
304
305 /* list of sonicvibes devices */
306 struct list_head devs;
307
308 /* the corresponding pci_dev structure */
309 struct pci_dev *dev;
310
311 /* soundcore stuff */
312 int dev_audio;
313 int dev_mixer;
314 int dev_midi;
315 int dev_dmfm;
316
317 /* hardware resources */
318 unsigned long iosb, ioenh, iosynth, iomidi; /* long for SPARC */
319 unsigned int iodmaa, iodmac, irq;
320
321 /* mixer stuff */
322 struct {
323 unsigned int modcnt;
324#ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
325 unsigned short vol[13];
326#endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
327 } mix;
328
329 /* wave stuff */
330 unsigned int rateadc, ratedac;
331 unsigned char fmt, enable;
332
333 spinlock_t lock;
334 struct mutex open_mutex;
335 mode_t open_mode;
336 wait_queue_head_t open_wait;
337
338 struct dmabuf {
339 void *rawbuf;
340 dma_addr_t dmaaddr;
341 unsigned buforder;
342 unsigned numfrag;
343 unsigned fragshift;
344 unsigned hwptr, swptr;
345 unsigned total_bytes;
346 int count;
347 unsigned error; /* over/underrun */
348 wait_queue_head_t wait;
349 /* redundant, but makes calculations easier */
350 unsigned fragsize;
351 unsigned dmasize;
352 unsigned fragsamples;
353 /* OSS stuff */
354 unsigned mapped:1;
355 unsigned ready:1;
356 unsigned endcleared:1;
357 unsigned enabled:1;
358 unsigned ossfragshift;
359 int ossmaxfrags;
360 unsigned subdivision;
361 } dma_dac, dma_adc;
362
363 /* midi stuff */
364 struct {
365 unsigned ird, iwr, icnt;
366 unsigned ord, owr, ocnt;
367 wait_queue_head_t iwait;
368 wait_queue_head_t owait;
369 struct timer_list timer;
370 unsigned char ibuf[MIDIINBUF];
371 unsigned char obuf[MIDIOUTBUF];
372 } midi;
373
374#if SUPPORT_JOYSTICK
375 struct gameport *gameport;
376#endif
377};
378
379/* --------------------------------------------------------------------- */
380
381static LIST_HEAD(devs);
382static unsigned long wavetable_mem;
383
384/* --------------------------------------------------------------------- */
385
386static inline unsigned ld2(unsigned int x)
387{
388 unsigned r = 0;
389
390 if (x >= 0x10000) {
391 x >>= 16;
392 r += 16;
393 }
394 if (x >= 0x100) {
395 x >>= 8;
396 r += 8;
397 }
398 if (x >= 0x10) {
399 x >>= 4;
400 r += 4;
401 }
402 if (x >= 4) {
403 x >>= 2;
404 r += 2;
405 }
406 if (x >= 2)
407 r++;
408 return r;
409}
410
411/* --------------------------------------------------------------------- */
412
413/*
414 * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
415 */
416
417#undef DMABYTEIO
418
419static void set_dmaa(struct sv_state *s, unsigned int addr, unsigned int count)
420{
421#ifdef DMABYTEIO
422 unsigned io = s->iodmaa, u;
423
424 count--;
425 for (u = 4; u > 0; u--, addr >>= 8, io++)
426 outb(addr & 0xff, io);
427 for (u = 3; u > 0; u--, count >>= 8, io++)
428 outb(count & 0xff, io);
429#else /* DMABYTEIO */
430 count--;
431 outl(addr, s->iodmaa + SV_DMA_ADDR0);
432 outl(count, s->iodmaa + SV_DMA_COUNT0);
433#endif /* DMABYTEIO */
434 outb(0x18, s->iodmaa + SV_DMA_MODE);
435}
436
437static void set_dmac(struct sv_state *s, unsigned int addr, unsigned int count)
438{
439#ifdef DMABYTEIO
440 unsigned io = s->iodmac, u;
441
442 count >>= 1;
443 count--;
444 for (u = 4; u > 0; u--, addr >>= 8, io++)
445 outb(addr & 0xff, io);
446 for (u = 3; u > 0; u--, count >>= 8, io++)
447 outb(count & 0xff, io);
448#else /* DMABYTEIO */
449 count >>= 1;
450 count--;
451 outl(addr, s->iodmac + SV_DMA_ADDR0);
452 outl(count, s->iodmac + SV_DMA_COUNT0);
453#endif /* DMABYTEIO */
454 outb(0x14, s->iodmac + SV_DMA_MODE);
455}
456
457static inline unsigned get_dmaa(struct sv_state *s)
458{
459#ifdef DMABYTEIO
460 unsigned io = s->iodmaa+6, v = 0, u;
461
462 for (u = 3; u > 0; u--, io--) {
463 v <<= 8;
464 v |= inb(io);
465 }
466 return v + 1;
467#else /* DMABYTEIO */
468 return (inl(s->iodmaa + SV_DMA_COUNT0) & 0xffffff) + 1;
469#endif /* DMABYTEIO */
470}
471
472static inline unsigned get_dmac(struct sv_state *s)
473{
474#ifdef DMABYTEIO
475 unsigned io = s->iodmac+6, v = 0, u;
476
477 for (u = 3; u > 0; u--, io--) {
478 v <<= 8;
479 v |= inb(io);
480 }
481 return (v + 1) << 1;
482#else /* DMABYTEIO */
483 return ((inl(s->iodmac + SV_DMA_COUNT0) & 0xffffff) + 1) << 1;
484#endif /* DMABYTEIO */
485}
486
487static void wrindir(struct sv_state *s, unsigned char idx, unsigned char data)
488{
489 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
490 udelay(10);
491 outb(data, s->ioenh + SV_CODEC_IDATA);
492 udelay(10);
493}
494
495static unsigned char rdindir(struct sv_state *s, unsigned char idx)
496{
497 unsigned char v;
498
499 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
500 udelay(10);
501 v = inb(s->ioenh + SV_CODEC_IDATA);
502 udelay(10);
503 return v;
504}
505
506static void set_fmt(struct sv_state *s, unsigned char mask, unsigned char data)
507{
508 unsigned long flags;
509
510 spin_lock_irqsave(&s->lock, flags);
511 outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
512 if (mask) {
513 s->fmt = inb(s->ioenh + SV_CODEC_IDATA);
514 udelay(10);
515 }
516 s->fmt = (s->fmt & mask) | data;
517 outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
518 udelay(10);
519 outb(0, s->ioenh + SV_CODEC_IADDR);
520 spin_unlock_irqrestore(&s->lock, flags);
521 udelay(10);
522}
523
524static void frobindir(struct sv_state *s, unsigned char idx, unsigned char mask, unsigned char data)
525{
526 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
527 udelay(10);
528 outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
529 udelay(10);
530}
531
532#define REFFREQUENCY 24576000
533#define ADCMULT 512
534#define FULLRATE 48000
535
536static unsigned setpll(struct sv_state *s, unsigned char reg, unsigned rate)
537{
538 unsigned long flags;
539 unsigned char r, m=0, n=0;
540 unsigned xm, xn, xr, xd, metric = ~0U;
541 /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
542
543 if (rate < 625000/ADCMULT)
544 rate = 625000/ADCMULT;
545 if (rate > 150000000/ADCMULT)
546 rate = 150000000/ADCMULT;
547 /* slight violation of specs, needed for continuous sampling rates */
548 for (r = 0; rate < 75000000/ADCMULT; r += 0x20, rate <<= 1);
549 for (xn = 3; xn < 35; xn++)
550 for (xm = 3; xm < 130; xm++) {
551 xr = REFFREQUENCY/ADCMULT * xm / xn;
552 xd = abs((signed)(xr - rate));
553 if (xd < metric) {
554 metric = xd;
555 m = xm - 2;
556 n = xn - 2;
557 }
558 }
559 reg &= 0x3f;
560 spin_lock_irqsave(&s->lock, flags);
561 outb(reg, s->ioenh + SV_CODEC_IADDR);
562 udelay(10);
563 outb(m, s->ioenh + SV_CODEC_IDATA);
564 udelay(10);
565 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
566 udelay(10);
567 outb(r | n, s->ioenh + SV_CODEC_IDATA);
568 spin_unlock_irqrestore(&s->lock, flags);
569 udelay(10);
570 return (REFFREQUENCY/ADCMULT * (m + 2) / (n + 2)) >> ((r >> 5) & 7);
571}
572
573#if 0
574
575static unsigned getpll(struct sv_state *s, unsigned char reg)
576{
577 unsigned long flags;
578 unsigned char m, n;
579
580 reg &= 0x3f;
581 spin_lock_irqsave(&s->lock, flags);
582 outb(reg, s->ioenh + SV_CODEC_IADDR);
583 udelay(10);
584 m = inb(s->ioenh + SV_CODEC_IDATA);
585 udelay(10);
586 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
587 udelay(10);
588 n = inb(s->ioenh + SV_CODEC_IDATA);
589 spin_unlock_irqrestore(&s->lock, flags);
590 udelay(10);
591 return (REFFREQUENCY/ADCMULT * (m + 2) / ((n & 0x1f) + 2)) >> ((n >> 5) & 7);
592}
593
594#endif
595
596static void set_dac_rate(struct sv_state *s, unsigned rate)
597{
598 unsigned div;
599 unsigned long flags;
600
601 if (rate > 48000)
602 rate = 48000;
603 if (rate < 4000)
604 rate = 4000;
605 div = (rate * 65536 + FULLRATE/2) / FULLRATE;
606 if (div > 65535)
607 div = 65535;
608 spin_lock_irqsave(&s->lock, flags);
609 wrindir(s, SV_CIPCMSR1, div >> 8);
610 wrindir(s, SV_CIPCMSR0, div);
611 spin_unlock_irqrestore(&s->lock, flags);
612 s->ratedac = (div * FULLRATE + 32768) / 65536;
613}
614
615static void set_adc_rate(struct sv_state *s, unsigned rate)
616{
617 unsigned long flags;
618 unsigned rate1, rate2, div;
619
620 if (rate > 48000)
621 rate = 48000;
622 if (rate < 4000)
623 rate = 4000;
624 rate1 = setpll(s, SV_CIADCPLLM, rate);
625 div = (48000 + rate/2) / rate;
626 if (div > 8)
627 div = 8;
628 rate2 = (48000 + div/2) / div;
629 spin_lock_irqsave(&s->lock, flags);
630 wrindir(s, SV_CIADCALTSR, (div-1) << 4);
631 if (abs((signed)(rate-rate2)) <= abs((signed)(rate-rate1))) {
632 wrindir(s, SV_CIADCCLKSOURCE, 0x10);
633 s->rateadc = rate2;
634 } else {
635 wrindir(s, SV_CIADCCLKSOURCE, 0x00);
636 s->rateadc = rate1;
637 }
638 spin_unlock_irqrestore(&s->lock, flags);
639}
640
641/* --------------------------------------------------------------------- */
642
643static inline void stop_adc(struct sv_state *s)
644{
645 unsigned long flags;
646
647 spin_lock_irqsave(&s->lock, flags);
648 s->enable &= ~SV_CENABLE_RE;
649 wrindir(s, SV_CIENABLE, s->enable);
650 spin_unlock_irqrestore(&s->lock, flags);
651}
652
653static inline void stop_dac(struct sv_state *s)
654{
655 unsigned long flags;
656
657 spin_lock_irqsave(&s->lock, flags);
658 s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
659 wrindir(s, SV_CIENABLE, s->enable);
660 spin_unlock_irqrestore(&s->lock, flags);
661}
662
663static void start_dac(struct sv_state *s)
664{
665 unsigned long flags;
666
667 spin_lock_irqsave(&s->lock, flags);
668 if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
669 s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
670 wrindir(s, SV_CIENABLE, s->enable);
671 }
672 spin_unlock_irqrestore(&s->lock, flags);
673}
674
675static void start_adc(struct sv_state *s)
676{
677 unsigned long flags;
678
679 spin_lock_irqsave(&s->lock, flags);
680 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
681 && s->dma_adc.ready) {
682 s->enable |= SV_CENABLE_RE;
683 wrindir(s, SV_CIENABLE, s->enable);
684 }
685 spin_unlock_irqrestore(&s->lock, flags);
686}
687
688/* --------------------------------------------------------------------- */
689
690#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
691#define DMABUF_MINORDER 1
692
693static void dealloc_dmabuf(struct sv_state *s, struct dmabuf *db)
694{
695 struct page *page, *pend;
696
697 if (db->rawbuf) {
698 /* undo marking the pages as reserved */
699 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
700 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
701 ClearPageReserved(page);
702 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
703 }
704 db->rawbuf = NULL;
705 db->mapped = db->ready = 0;
706}
707
708
709/* DMAA is used for playback, DMAC is used for recording */
710
711static int prog_dmabuf(struct sv_state *s, unsigned rec)
712{
713 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
714 unsigned rate = rec ? s->rateadc : s->ratedac;
715 int order;
716 unsigned bytepersec;
717 unsigned bufs;
718 struct page *page, *pend;
719 unsigned char fmt;
720 unsigned long flags;
721
722 spin_lock_irqsave(&s->lock, flags);
723 fmt = s->fmt;
724 if (rec) {
725 s->enable &= ~SV_CENABLE_RE;
726 fmt >>= SV_CFMT_CSHIFT;
727 } else {
728 s->enable &= ~SV_CENABLE_PE;
729 fmt >>= SV_CFMT_ASHIFT;
730 }
731 wrindir(s, SV_CIENABLE, s->enable);
732 spin_unlock_irqrestore(&s->lock, flags);
733 fmt &= SV_CFMT_MASK;
734 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
735 if (!db->rawbuf) {
736 db->ready = db->mapped = 0;
737 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
738 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
739 break;
740 if (!db->rawbuf)
741 return -ENOMEM;
742 db->buforder = order;
743 if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
744 printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
745 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
746 if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
747 printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
748 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
749 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
750 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
751 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
752 SetPageReserved(page);
753 }
754 bytepersec = rate << sample_shift[fmt];
755 bufs = PAGE_SIZE << db->buforder;
756 if (db->ossfragshift) {
757 if ((1000 << db->ossfragshift) < bytepersec)
758 db->fragshift = ld2(bytepersec/1000);
759 else
760 db->fragshift = db->ossfragshift;
761 } else {
762 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
763 if (db->fragshift < 3)
764 db->fragshift = 3;
765 }
766 db->numfrag = bufs >> db->fragshift;
767 while (db->numfrag < 4 && db->fragshift > 3) {
768 db->fragshift--;
769 db->numfrag = bufs >> db->fragshift;
770 }
771 db->fragsize = 1 << db->fragshift;
772 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
773 db->numfrag = db->ossmaxfrags;
774 db->fragsamples = db->fragsize >> sample_shift[fmt];
775 db->dmasize = db->numfrag << db->fragshift;
776 memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
777 spin_lock_irqsave(&s->lock, flags);
778 if (rec) {
779 set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
780 /* program enhanced mode registers */
781 wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >> 8);
782 wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
783 } else {
784 set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
785 /* program enhanced mode registers */
786 wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >> 8);
787 wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
788 }
789 spin_unlock_irqrestore(&s->lock, flags);
790 db->enabled = 1;
791 db->ready = 1;
792 return 0;
793}
794
795static inline void clear_advance(struct sv_state *s)
796{
797 unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ? 0 : 0x80;
798 unsigned char *buf = s->dma_dac.rawbuf;
799 unsigned bsize = s->dma_dac.dmasize;
800 unsigned bptr = s->dma_dac.swptr;
801 unsigned len = s->dma_dac.fragsize;
802
803 if (bptr + len > bsize) {
804 unsigned x = bsize - bptr;
805 memset(buf + bptr, c, x);
806 bptr = 0;
807 len -= x;
808 }
809 memset(buf + bptr, c, len);
810}
811
812/* call with spinlock held! */
813static void sv_update_ptr(struct sv_state *s)
814{
815 unsigned hwptr;
816 int diff;
817
818 /* update ADC pointer */
819 if (s->dma_adc.ready) {
820 hwptr = (s->dma_adc.dmasize - get_dmac(s)) % s->dma_adc.dmasize;
821 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
822 s->dma_adc.hwptr = hwptr;
823 s->dma_adc.total_bytes += diff;
824 s->dma_adc.count += diff;
825 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
826 wake_up(&s->dma_adc.wait);
827 if (!s->dma_adc.mapped) {
828 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
829 s->enable &= ~SV_CENABLE_RE;
830 wrindir(s, SV_CIENABLE, s->enable);
831 s->dma_adc.error++;
832 }
833 }
834 }
835 /* update DAC pointer */
836 if (s->dma_dac.ready) {
837 hwptr = (s->dma_dac.dmasize - get_dmaa(s)) % s->dma_dac.dmasize;
838 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
839 s->dma_dac.hwptr = hwptr;
840 s->dma_dac.total_bytes += diff;
841 if (s->dma_dac.mapped) {
842 s->dma_dac.count += diff;
843 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
844 wake_up(&s->dma_dac.wait);
845 } else {
846 s->dma_dac.count -= diff;
847 if (s->dma_dac.count <= 0) {
848 s->enable &= ~SV_CENABLE_PE;
849 wrindir(s, SV_CIENABLE, s->enable);
850 s->dma_dac.error++;
851 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
852 clear_advance(s);
853 s->dma_dac.endcleared = 1;
854 }
855 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
856 wake_up(&s->dma_dac.wait);
857 }
858 }
859}
860
861/* hold spinlock for the following! */
862static void sv_handle_midi(struct sv_state *s)
863{
864 unsigned char ch;
865 int wake;
866
867 wake = 0;
868 while (!(inb(s->iomidi+1) & 0x80)) {
869 ch = inb(s->iomidi);
870 if (s->midi.icnt < MIDIINBUF) {
871 s->midi.ibuf[s->midi.iwr] = ch;
872 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
873 s->midi.icnt++;
874 }
875 wake = 1;
876 }
877 if (wake)
878 wake_up(&s->midi.iwait);
879 wake = 0;
880 while (!(inb(s->iomidi+1) & 0x40) && s->midi.ocnt > 0) {
881 outb(s->midi.obuf[s->midi.ord], s->iomidi);
882 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
883 s->midi.ocnt--;
884 if (s->midi.ocnt < MIDIOUTBUF-16)
885 wake = 1;
886 }
887 if (wake)
888 wake_up(&s->midi.owait);
889}
890
891static irqreturn_t sv_interrupt(int irq, void *dev_id, struct pt_regs *regs)
892{
893 struct sv_state *s = (struct sv_state *)dev_id;
894 unsigned int intsrc;
895
896 /* fastpath out, to ease interrupt sharing */
897 intsrc = inb(s->ioenh + SV_CODEC_STATUS);
898 if (!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
899 return IRQ_NONE;
900 spin_lock(&s->lock);
901 sv_update_ptr(s);
902 sv_handle_midi(s);
903 spin_unlock(&s->lock);
904 return IRQ_HANDLED;
905}
906
907static void sv_midi_timer(unsigned long data)
908{
909 struct sv_state *s = (struct sv_state *)data;
910 unsigned long flags;
911
912 spin_lock_irqsave(&s->lock, flags);
913 sv_handle_midi(s);
914 spin_unlock_irqrestore(&s->lock, flags);
915 s->midi.timer.expires = jiffies+1;
916 add_timer(&s->midi.timer);
917}
918
919/* --------------------------------------------------------------------- */
920
921static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
922
923#define VALIDATE_STATE(s) \
924({ \
925 if (!(s) || (s)->magic != SV_MAGIC) { \
926 printk(invalid_magic); \
927 return -ENXIO; \
928 } \
929})
930
931/* --------------------------------------------------------------------- */
932
933#define MT_4 1
934#define MT_5MUTE 2
935#define MT_4MUTEMONO 3
936#define MT_6MUTE 4
937
938static const struct {
939 unsigned left:5;
940 unsigned right:5;
941 unsigned type:3;
942 unsigned rec:3;
943} mixtable[SOUND_MIXER_NRDEVICES] = {
944 [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4, 0 },
945 [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE, 5 },
946 [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE, 1 },
947 [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE, 4 },
948 [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO, 6 },
949 [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE, 2 },
950 [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE, 3 },
951 [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE, 7 },
952 [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE, 0 }
953};
954
955#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
956
957static int return_mixval(struct sv_state *s, unsigned i, int *arg)
958{
959 unsigned long flags;
960 unsigned char l, r, rl, rr;
961
962 spin_lock_irqsave(&s->lock, flags);
963 l = rdindir(s, mixtable[i].left);
964 r = rdindir(s, mixtable[i].right);
965 spin_unlock_irqrestore(&s->lock, flags);
966 switch (mixtable[i].type) {
967 case MT_4:
968 r &= 0xf;
969 l &= 0xf;
970 rl = 10 + 6 * (l & 15);
971 rr = 10 + 6 * (r & 15);
972 break;
973
974 case MT_4MUTEMONO:
975 rl = 55 - 3 * (l & 15);
976 if (r & 0x10)
977 rl += 45;
978 rr = rl;
979 r = l;
980 break;
981
982 case MT_5MUTE:
983 default:
984 rl = 100 - 3 * (l & 31);
985 rr = 100 - 3 * (r & 31);
986 break;
987
988 case MT_6MUTE:
989 rl = 100 - 3 * (l & 63) / 2;
990 rr = 100 - 3 * (r & 63) / 2;
991 break;
992 }
993 if (l & 0x80)
994 rl = 0;
995 if (r & 0x80)
996 rr = 0;
997 return put_user((rr << 8) | rl, arg);
998}
999
1000#else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1001
1002static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1003{
1004 [SOUND_MIXER_RECLEV] = 1,
1005 [SOUND_MIXER_LINE1] = 2,
1006 [SOUND_MIXER_CD] = 3,
1007 [SOUND_MIXER_LINE] = 4,
1008 [SOUND_MIXER_MIC] = 5,
1009 [SOUND_MIXER_SYNTH] = 6,
1010 [SOUND_MIXER_LINE2] = 7,
1011 [SOUND_MIXER_VOLUME] = 8,
1012 [SOUND_MIXER_PCM] = 9
1013};
1014
1015#endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1016
1017static unsigned mixer_recmask(struct sv_state *s)
1018{
1019 unsigned long flags;
1020 int i, j;
1021
1022 spin_lock_irqsave(&s->lock, flags);
1023 j = rdindir(s, SV_CIMIX_ADCINL) >> 5;
1024 spin_unlock_irqrestore(&s->lock, flags);
1025 j &= 7;
1026 for (i = 0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
1027 return 1 << i;
1028}
1029
1030static int mixer_ioctl(struct sv_state *s, unsigned int cmd, unsigned long arg)
1031{
1032 unsigned long flags;
1033 int i, val;
1034 unsigned char l, r, rl, rr;
1035 int __user *p = (int __user *)arg;
1036
1037 VALIDATE_STATE(s);
1038 if (cmd == SOUND_MIXER_INFO) {
1039 mixer_info info;
1040 memset(&info, 0, sizeof(info));
1041 strlcpy(info.id, "SonicVibes", sizeof(info.id));
1042 strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
1043 info.modify_counter = s->mix.modcnt;
1044 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
1045 return -EFAULT;
1046 return 0;
1047 }
1048 if (cmd == SOUND_OLD_MIXER_INFO) {
1049 _old_mixer_info info;
1050 memset(&info, 0, sizeof(info));
1051 strlcpy(info.id, "SonicVibes", sizeof(info.id));
1052 strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
1053 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
1054 return -EFAULT;
1055 return 0;
1056 }
1057 if (cmd == OSS_GETVERSION)
1058 return put_user(SOUND_VERSION, p);
1059 if (cmd == SOUND_MIXER_PRIVATE1) { /* SRS settings */
1060 if (get_user(val, p))
1061 return -EFAULT;
1062 spin_lock_irqsave(&s->lock, flags);
1063 if (val & 1) {
1064 if (val & 2) {
1065 l = 4 - ((val >> 2) & 7);
1066 if (l & ~3)
1067 l = 4;
1068 r = 4 - ((val >> 5) & 7);
1069 if (r & ~3)
1070 r = 4;
1071 wrindir(s, SV_CISRSSPACE, l);
1072 wrindir(s, SV_CISRSCENTER, r);
1073 } else
1074 wrindir(s, SV_CISRSSPACE, 0x80);
1075 }
1076 l = rdindir(s, SV_CISRSSPACE);
1077 r = rdindir(s, SV_CISRSCENTER);
1078 spin_unlock_irqrestore(&s->lock, flags);
1079 if (l & 0x80)
1080 return put_user(0, p);
1081 return put_user(((4 - (l & 7)) << 2) | ((4 - (r & 7)) << 5) | 2, p);
1082 }
1083 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1084 return -EINVAL;
1085 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1086 switch (_IOC_NR(cmd)) {
1087 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1088 return put_user(mixer_recmask(s), p);
1089
1090 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
1091 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1092 if (mixtable[i].type)
1093 val |= 1 << i;
1094 return put_user(val, p);
1095
1096 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1097 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1098 if (mixtable[i].rec)
1099 val |= 1 << i;
1100 return put_user(val, p);
1101
1102 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1103 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1104 if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1105 val |= 1 << i;
1106 return put_user(val, p);
1107
1108 case SOUND_MIXER_CAPS:
1109 return put_user(SOUND_CAP_EXCL_INPUT, p);
1110
1111 default:
1112 i = _IOC_NR(cmd);
1113 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1114 return -EINVAL;
1115#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1116 return return_mixval(s, i, p);
1117#else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1118 if (!volidx[i])
1119 return -EINVAL;
1120 return put_user(s->mix.vol[volidx[i]-1], p);
1121#endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1122 }
1123 }
1124 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1125 return -EINVAL;
1126 s->mix.modcnt++;
1127 switch (_IOC_NR(cmd)) {
1128 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1129 if (get_user(val, p))
1130 return -EFAULT;
1131 i = hweight32(val);
1132 if (i == 0)
1133 return 0; /*val = mixer_recmask(s);*/
1134 else if (i > 1)
1135 val &= ~mixer_recmask(s);
1136 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1137 if (!(val & (1 << i)))
1138 continue;
1139 if (mixtable[i].rec)
1140 break;
1141 }
1142 if (i == SOUND_MIXER_NRDEVICES)
1143 return 0;
1144 spin_lock_irqsave(&s->lock, flags);
1145 frobindir(s, SV_CIMIX_ADCINL, 0x1f, mixtable[i].rec << 5);
1146 frobindir(s, SV_CIMIX_ADCINR, 0x1f, mixtable[i].rec << 5);
1147 spin_unlock_irqrestore(&s->lock, flags);
1148 return 0;
1149
1150 default:
1151 i = _IOC_NR(cmd);
1152 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1153 return -EINVAL;
1154 if (get_user(val, p))
1155 return -EFAULT;
1156 l = val & 0xff;
1157 r = (val >> 8) & 0xff;
1158 if (mixtable[i].type == MT_4MUTEMONO)
1159 l = (r + l) / 2;
1160 if (l > 100)
1161 l = 100;
1162 if (r > 100)
1163 r = 100;
1164 spin_lock_irqsave(&s->lock, flags);
1165 switch (mixtable[i].type) {
1166 case MT_4:
1167 if (l >= 10)
1168 l -= 10;
1169 if (r >= 10)
1170 r -= 10;
1171 frobindir(s, mixtable[i].left, 0xf0, l / 6);
1172 frobindir(s, mixtable[i].right, 0xf0, l / 6);
1173 break;
1174
1175 case MT_4MUTEMONO:
1176 rr = 0;
1177 if (l < 10)
1178 rl = 0x80;
1179 else {
1180 if (l >= 55) {
1181 rr = 0x10;
1182 l -= 45;
1183 }
1184 rl = (55 - l) / 3;
1185 }
1186 wrindir(s, mixtable[i].left, rl);
1187 frobindir(s, mixtable[i].right, ~0x10, rr);
1188 break;
1189
1190 case MT_5MUTE:
1191 if (l < 7)
1192 rl = 0x80;
1193 else
1194 rl = (100 - l) / 3;
1195 if (r < 7)
1196 rr = 0x80;
1197 else
1198 rr = (100 - r) / 3;
1199 wrindir(s, mixtable[i].left, rl);
1200 wrindir(s, mixtable[i].right, rr);
1201 break;
1202
1203 case MT_6MUTE:
1204 if (l < 6)
1205 rl = 0x80;
1206 else
1207 rl = (100 - l) * 2 / 3;
1208 if (r < 6)
1209 rr = 0x80;
1210 else
1211 rr = (100 - r) * 2 / 3;
1212 wrindir(s, mixtable[i].left, rl);
1213 wrindir(s, mixtable[i].right, rr);
1214 break;
1215 }
1216 spin_unlock_irqrestore(&s->lock, flags);
1217#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1218 return return_mixval(s, i, p);
1219#else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1220 if (!volidx[i])
1221 return -EINVAL;
1222 s->mix.vol[volidx[i]-1] = val;
1223 return put_user(s->mix.vol[volidx[i]-1], p);
1224#endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1225 }
1226}
1227
1228/* --------------------------------------------------------------------- */
1229
1230static int sv_open_mixdev(struct inode *inode, struct file *file)
1231{
1232 int minor = iminor(inode);
1233 struct list_head *list;
1234 struct sv_state *s;
1235
1236 for (list = devs.next; ; list = list->next) {
1237 if (list == &devs)
1238 return -ENODEV;
1239 s = list_entry(list, struct sv_state, devs);
1240 if (s->dev_mixer == minor)
1241 break;
1242 }
1243 VALIDATE_STATE(s);
1244 file->private_data = s;
1245 return nonseekable_open(inode, file);
1246}
1247
1248static int sv_release_mixdev(struct inode *inode, struct file *file)
1249{
1250 struct sv_state *s = (struct sv_state *)file->private_data;
1251
1252 VALIDATE_STATE(s);
1253 return 0;
1254}
1255
1256static int sv_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1257{
1258 return mixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
1259}
1260
1261static /*const*/ struct file_operations sv_mixer_fops = {
1262 .owner = THIS_MODULE,
1263 .llseek = no_llseek,
1264 .ioctl = sv_ioctl_mixdev,
1265 .open = sv_open_mixdev,
1266 .release = sv_release_mixdev,
1267};
1268
1269/* --------------------------------------------------------------------- */
1270
1271static int drain_dac(struct sv_state *s, int nonblock)
1272{
1273 DECLARE_WAITQUEUE(wait, current);
1274 unsigned long flags;
1275 int count, tmo;
1276
1277 if (s->dma_dac.mapped || !s->dma_dac.ready)
1278 return 0;
1279 add_wait_queue(&s->dma_dac.wait, &wait);
1280 for (;;) {
1281 __set_current_state(TASK_INTERRUPTIBLE);
1282 spin_lock_irqsave(&s->lock, flags);
1283 count = s->dma_dac.count;
1284 spin_unlock_irqrestore(&s->lock, flags);
1285 if (count <= 0)
1286 break;
1287 if (signal_pending(current))
1288 break;
1289 if (nonblock) {
1290 remove_wait_queue(&s->dma_dac.wait, &wait);
1291 set_current_state(TASK_RUNNING);
1292 return -EBUSY;
1293 }
1294 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
1295 tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
1296 if (!schedule_timeout(tmo + 1))
1297 printk(KERN_DEBUG "sv: dma timed out??\n");
1298 }
1299 remove_wait_queue(&s->dma_dac.wait, &wait);
1300 set_current_state(TASK_RUNNING);
1301 if (signal_pending(current))
1302 return -ERESTARTSYS;
1303 return 0;
1304}
1305
1306/* --------------------------------------------------------------------- */
1307
1308static ssize_t sv_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1309{
1310 struct sv_state *s = (struct sv_state *)file->private_data;
1311 DECLARE_WAITQUEUE(wait, current);
1312 ssize_t ret;
1313 unsigned long flags;
1314 unsigned swptr;
1315 int cnt;
1316
1317 VALIDATE_STATE(s);
1318 if (s->dma_adc.mapped)
1319 return -ENXIO;
1320 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1321 return ret;
1322 if (!access_ok(VERIFY_WRITE, buffer, count))
1323 return -EFAULT;
1324 ret = 0;
1325#if 0
1326 spin_lock_irqsave(&s->lock, flags);
1327 sv_update_ptr(s);
1328 spin_unlock_irqrestore(&s->lock, flags);
1329#endif
1330 add_wait_queue(&s->dma_adc.wait, &wait);
1331 while (count > 0) {
1332 spin_lock_irqsave(&s->lock, flags);
1333 swptr = s->dma_adc.swptr;
1334 cnt = s->dma_adc.dmasize-swptr;
1335 if (s->dma_adc.count < cnt)
1336 cnt = s->dma_adc.count;
1337 if (cnt <= 0)
1338 __set_current_state(TASK_INTERRUPTIBLE);
1339 spin_unlock_irqrestore(&s->lock, flags);
1340 if (cnt > count)
1341 cnt = count;
1342 if (cnt <= 0) {
1343 if (s->dma_adc.enabled)
1344 start_adc(s);
1345 if (file->f_flags & O_NONBLOCK) {
1346 if (!ret)
1347 ret = -EAGAIN;
1348 break;
1349 }
1350 if (!schedule_timeout(HZ)) {
1351 printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1352 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1353 s->dma_adc.hwptr, s->dma_adc.swptr);
1354 stop_adc(s);
1355 spin_lock_irqsave(&s->lock, flags);
1356 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1357 /* program enhanced mode registers */
1358 wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
1359 wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
1360 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1361 spin_unlock_irqrestore(&s->lock, flags);
1362 }
1363 if (signal_pending(current)) {
1364 if (!ret)
1365 ret = -ERESTARTSYS;
1366 break;
1367 }
1368 continue;
1369 }
1370 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1371 if (!ret)
1372 ret = -EFAULT;
1373 break;
1374 }
1375 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1376 spin_lock_irqsave(&s->lock, flags);
1377 s->dma_adc.swptr = swptr;
1378 s->dma_adc.count -= cnt;
1379 spin_unlock_irqrestore(&s->lock, flags);
1380 count -= cnt;
1381 buffer += cnt;
1382 ret += cnt;
1383 if (s->dma_adc.enabled)
1384 start_adc(s);
1385 }
1386 remove_wait_queue(&s->dma_adc.wait, &wait);
1387 set_current_state(TASK_RUNNING);
1388 return ret;
1389}
1390
1391static ssize_t sv_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1392{
1393 struct sv_state *s = (struct sv_state *)file->private_data;
1394 DECLARE_WAITQUEUE(wait, current);
1395 ssize_t ret;
1396 unsigned long flags;
1397 unsigned swptr;
1398 int cnt;
1399
1400 VALIDATE_STATE(s);
1401 if (s->dma_dac.mapped)
1402 return -ENXIO;
1403 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1404 return ret;
1405 if (!access_ok(VERIFY_READ, buffer, count))
1406 return -EFAULT;
1407 ret = 0;
1408#if 0
1409 spin_lock_irqsave(&s->lock, flags);
1410 sv_update_ptr(s);
1411 spin_unlock_irqrestore(&s->lock, flags);
1412#endif
1413 add_wait_queue(&s->dma_dac.wait, &wait);
1414 while (count > 0) {
1415 spin_lock_irqsave(&s->lock, flags);
1416 if (s->dma_dac.count < 0) {
1417 s->dma_dac.count = 0;
1418 s->dma_dac.swptr = s->dma_dac.hwptr;
1419 }
1420 swptr = s->dma_dac.swptr;
1421 cnt = s->dma_dac.dmasize-swptr;
1422 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1423 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1424 if (cnt <= 0)
1425 __set_current_state(TASK_INTERRUPTIBLE);
1426 spin_unlock_irqrestore(&s->lock, flags);
1427 if (cnt > count)
1428 cnt = count;
1429 if (cnt <= 0) {
1430 if (s->dma_dac.enabled)
1431 start_dac(s);
1432 if (file->f_flags & O_NONBLOCK) {
1433 if (!ret)
1434 ret = -EAGAIN;
1435 break;
1436 }
1437 if (!schedule_timeout(HZ)) {
1438 printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1439 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1440 s->dma_dac.hwptr, s->dma_dac.swptr);
1441 stop_dac(s);
1442 spin_lock_irqsave(&s->lock, flags);
1443 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1444 /* program enhanced mode registers */
1445 wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
1446 wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
1447 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1448 spin_unlock_irqrestore(&s->lock, flags);
1449 }
1450 if (signal_pending(current)) {
1451 if (!ret)
1452 ret = -ERESTARTSYS;
1453 break;
1454 }
1455 continue;
1456 }
1457 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1458 if (!ret)
1459 ret = -EFAULT;
1460 break;
1461 }
1462 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1463 spin_lock_irqsave(&s->lock, flags);
1464 s->dma_dac.swptr = swptr;
1465 s->dma_dac.count += cnt;
1466 s->dma_dac.endcleared = 0;
1467 spin_unlock_irqrestore(&s->lock, flags);
1468 count -= cnt;
1469 buffer += cnt;
1470 ret += cnt;
1471 if (s->dma_dac.enabled)
1472 start_dac(s);
1473 }
1474 remove_wait_queue(&s->dma_dac.wait, &wait);
1475 set_current_state(TASK_RUNNING);
1476 return ret;
1477}
1478
1479/* No kernel lock - we have our own spinlock */
1480static unsigned int sv_poll(struct file *file, struct poll_table_struct *wait)
1481{
1482 struct sv_state *s = (struct sv_state *)file->private_data;
1483 unsigned long flags;
1484 unsigned int mask = 0;
1485
1486 VALIDATE_STATE(s);
1487 if (file->f_mode & FMODE_WRITE) {
1488 if (!s->dma_dac.ready && prog_dmabuf(s, 1))
1489 return 0;
1490 poll_wait(file, &s->dma_dac.wait, wait);
1491 }
1492 if (file->f_mode & FMODE_READ) {
1493 if (!s->dma_adc.ready && prog_dmabuf(s, 0))
1494 return 0;
1495 poll_wait(file, &s->dma_adc.wait, wait);
1496 }
1497 spin_lock_irqsave(&s->lock, flags);
1498 sv_update_ptr(s);
1499 if (file->f_mode & FMODE_READ) {
1500 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1501 mask |= POLLIN | POLLRDNORM;
1502 }
1503 if (file->f_mode & FMODE_WRITE) {
1504 if (s->dma_dac.mapped) {
1505 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1506 mask |= POLLOUT | POLLWRNORM;
1507 } else {
1508 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1509 mask |= POLLOUT | POLLWRNORM;
1510 }
1511 }
1512 spin_unlock_irqrestore(&s->lock, flags);
1513 return mask;
1514}
1515
1516static int sv_mmap(struct file *file, struct vm_area_struct *vma)
1517{
1518 struct sv_state *s = (struct sv_state *)file->private_data;
1519 struct dmabuf *db;
1520 int ret = -EINVAL;
1521 unsigned long size;
1522
1523 VALIDATE_STATE(s);
1524 lock_kernel();
1525 if (vma->vm_flags & VM_WRITE) {
1526 if ((ret = prog_dmabuf(s, 1)) != 0)
1527 goto out;
1528 db = &s->dma_dac;
1529 } else if (vma->vm_flags & VM_READ) {
1530 if ((ret = prog_dmabuf(s, 0)) != 0)
1531 goto out;
1532 db = &s->dma_adc;
1533 } else
1534 goto out;
1535 ret = -EINVAL;
1536 if (vma->vm_pgoff != 0)
1537 goto out;
1538 size = vma->vm_end - vma->vm_start;
1539 if (size > (PAGE_SIZE << db->buforder))
1540 goto out;
1541 ret = -EAGAIN;
1542 if (remap_pfn_range(vma, vma->vm_start,
1543 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1544 size, vma->vm_page_prot))
1545 goto out;
1546 db->mapped = 1;
1547 ret = 0;
1548out:
1549 unlock_kernel();
1550 return ret;
1551}
1552
1553static int sv_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1554{
1555 struct sv_state *s = (struct sv_state *)file->private_data;
1556 unsigned long flags;
1557 audio_buf_info abinfo;
1558 count_info cinfo;
1559 int count;
1560 int val, mapped, ret;
1561 unsigned char fmtm, fmtd;
1562 void __user *argp = (void __user *)arg;
1563 int __user *p = argp;
1564
1565 VALIDATE_STATE(s);
1566 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1567 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1568 switch (cmd) {
1569 case OSS_GETVERSION:
1570 return put_user(SOUND_VERSION, p);
1571
1572 case SNDCTL_DSP_SYNC:
1573 if (file->f_mode & FMODE_WRITE)
1574 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1575 return 0;
1576
1577 case SNDCTL_DSP_SETDUPLEX:
1578 return 0;
1579
1580 case SNDCTL_DSP_GETCAPS:
1581 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1582
1583 case SNDCTL_DSP_RESET:
1584 if (file->f_mode & FMODE_WRITE) {
1585 stop_dac(s);
1586 synchronize_irq(s->irq);
1587 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1588 }
1589 if (file->f_mode & FMODE_READ) {
1590 stop_adc(s);
1591 synchronize_irq(s->irq);
1592 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1593 }
1594 return 0;
1595
1596 case SNDCTL_DSP_SPEED:
1597 if (get_user(val, p))
1598 return -EFAULT;
1599 if (val >= 0) {
1600 if (file->f_mode & FMODE_READ) {
1601 stop_adc(s);
1602 s->dma_adc.ready = 0;
1603 set_adc_rate(s, val);
1604 }
1605 if (file->f_mode & FMODE_WRITE) {
1606 stop_dac(s);
1607 s->dma_dac.ready = 0;
1608 set_dac_rate(s, val);
1609 }
1610 }
1611 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1612
1613 case SNDCTL_DSP_STEREO:
1614 if (get_user(val, p))
1615 return -EFAULT;
1616 fmtd = 0;
1617 fmtm = ~0;
1618 if (file->f_mode & FMODE_READ) {
1619 stop_adc(s);
1620 s->dma_adc.ready = 0;
1621 if (val)
1622 fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1623 else
1624 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1625 }
1626 if (file->f_mode & FMODE_WRITE) {
1627 stop_dac(s);
1628 s->dma_dac.ready = 0;
1629 if (val)
1630 fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1631 else
1632 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1633 }
1634 set_fmt(s, fmtm, fmtd);
1635 return 0;
1636
1637 case SNDCTL_DSP_CHANNELS:
1638 if (get_user(val, p))
1639 return -EFAULT;
1640 if (val != 0) {
1641 fmtd = 0;
1642 fmtm = ~0;
1643 if (file->f_mode & FMODE_READ) {
1644 stop_adc(s);
1645 s->dma_adc.ready = 0;
1646 if (val >= 2)
1647 fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1648 else
1649 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1650 }
1651 if (file->f_mode & FMODE_WRITE) {
1652 stop_dac(s);
1653 s->dma_dac.ready = 0;
1654 if (val >= 2)
1655 fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1656 else
1657 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1658 }
1659 set_fmt(s, fmtm, fmtd);
1660 }
1661 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1662 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
1663
1664 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1665 return put_user(AFMT_S16_LE|AFMT_U8, p);
1666
1667 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1668 if (get_user(val, p))
1669 return -EFAULT;
1670 if (val != AFMT_QUERY) {
1671 fmtd = 0;
1672 fmtm = ~0;
1673 if (file->f_mode & FMODE_READ) {
1674 stop_adc(s);
1675 s->dma_adc.ready = 0;
1676 if (val == AFMT_S16_LE)
1677 fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1678 else
1679 fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
1680 }
1681 if (file->f_mode & FMODE_WRITE) {
1682 stop_dac(s);
1683 s->dma_dac.ready = 0;
1684 if (val == AFMT_S16_LE)
1685 fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1686 else
1687 fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
1688 }
1689 set_fmt(s, fmtm, fmtd);
1690 }
1691 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1692 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, p);
1693
1694 case SNDCTL_DSP_POST:
1695 return 0;
1696
1697 case SNDCTL_DSP_GETTRIGGER:
1698 val = 0;
1699 if (file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
1700 val |= PCM_ENABLE_INPUT;
1701 if (file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
1702 val |= PCM_ENABLE_OUTPUT;
1703 return put_user(val, p);
1704
1705 case SNDCTL_DSP_SETTRIGGER:
1706 if (get_user(val, p))
1707 return -EFAULT;
1708 if (file->f_mode & FMODE_READ) {
1709 if (val & PCM_ENABLE_INPUT) {
1710 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1711 return ret;
1712 s->dma_adc.enabled = 1;
1713 start_adc(s);
1714 } else {
1715 s->dma_adc.enabled = 0;
1716 stop_adc(s);
1717 }
1718 }
1719 if (file->f_mode & FMODE_WRITE) {
1720 if (val & PCM_ENABLE_OUTPUT) {
1721 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1722 return ret;
1723 s->dma_dac.enabled = 1;
1724 start_dac(s);
1725 } else {
1726 s->dma_dac.enabled = 0;
1727 stop_dac(s);
1728 }
1729 }
1730 return 0;
1731
1732 case SNDCTL_DSP_GETOSPACE:
1733 if (!(file->f_mode & FMODE_WRITE))
1734 return -EINVAL;
1735 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1736 return val;
1737 spin_lock_irqsave(&s->lock, flags);
1738 sv_update_ptr(s);
1739 abinfo.fragsize = s->dma_dac.fragsize;
1740 count = s->dma_dac.count;
1741 if (count < 0)
1742 count = 0;
1743 abinfo.bytes = s->dma_dac.dmasize - count;
1744 abinfo.fragstotal = s->dma_dac.numfrag;
1745 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1746 spin_unlock_irqrestore(&s->lock, flags);
1747 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1748
1749 case SNDCTL_DSP_GETISPACE:
1750 if (!(file->f_mode & FMODE_READ))
1751 return -EINVAL;
1752 if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
1753 return val;
1754 spin_lock_irqsave(&s->lock, flags);
1755 sv_update_ptr(s);
1756 abinfo.fragsize = s->dma_adc.fragsize;
1757 count = s->dma_adc.count;
1758 if (count < 0)
1759 count = 0;
1760 abinfo.bytes = count;
1761 abinfo.fragstotal = s->dma_adc.numfrag;
1762 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1763 spin_unlock_irqrestore(&s->lock, flags);
1764 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1765
1766 case SNDCTL_DSP_NONBLOCK:
1767 file->f_flags |= O_NONBLOCK;
1768 return 0;
1769
1770 case SNDCTL_DSP_GETODELAY:
1771 if (!(file->f_mode & FMODE_WRITE))
1772 return -EINVAL;
1773 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1774 return val;
1775 spin_lock_irqsave(&s->lock, flags);
1776 sv_update_ptr(s);
1777 count = s->dma_dac.count;
1778 spin_unlock_irqrestore(&s->lock, flags);
1779 if (count < 0)
1780 count = 0;
1781 return put_user(count, p);
1782
1783 case SNDCTL_DSP_GETIPTR:
1784 if (!(file->f_mode & FMODE_READ))
1785 return -EINVAL;
1786 if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
1787 return val;
1788 spin_lock_irqsave(&s->lock, flags);
1789 sv_update_ptr(s);
1790 cinfo.bytes = s->dma_adc.total_bytes;
1791 count = s->dma_adc.count;
1792 if (count < 0)
1793 count = 0;
1794 cinfo.blocks = count >> s->dma_adc.fragshift;
1795 cinfo.ptr = s->dma_adc.hwptr;
1796 if (s->dma_adc.mapped)
1797 s->dma_adc.count &= s->dma_adc.fragsize-1;
1798 spin_unlock_irqrestore(&s->lock, flags);
1799 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1800 return -EFAULT;
1801 return 0;
1802
1803 case SNDCTL_DSP_GETOPTR:
1804 if (!(file->f_mode & FMODE_WRITE))
1805 return -EINVAL;
1806 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1807 return val;
1808 spin_lock_irqsave(&s->lock, flags);
1809 sv_update_ptr(s);
1810 cinfo.bytes = s->dma_dac.total_bytes;
1811 count = s->dma_dac.count;
1812 if (count < 0)
1813 count = 0;
1814 cinfo.blocks = count >> s->dma_dac.fragshift;
1815 cinfo.ptr = s->dma_dac.hwptr;
1816 if (s->dma_dac.mapped)
1817 s->dma_dac.count &= s->dma_dac.fragsize-1;
1818 spin_unlock_irqrestore(&s->lock, flags);
1819 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1820 return -EFAULT;
1821 return 0;
1822
1823 case SNDCTL_DSP_GETBLKSIZE:
1824 if (file->f_mode & FMODE_WRITE) {
1825 if ((val = prog_dmabuf(s, 0)))
1826 return val;
1827 return put_user(s->dma_dac.fragsize, p);
1828 }
1829 if ((val = prog_dmabuf(s, 1)))
1830 return val;
1831 return put_user(s->dma_adc.fragsize, p);
1832
1833 case SNDCTL_DSP_SETFRAGMENT:
1834 if (get_user(val, p))
1835 return -EFAULT;
1836 if (file->f_mode & FMODE_READ) {
1837 s->dma_adc.ossfragshift = val & 0xffff;
1838 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1839 if (s->dma_adc.ossfragshift < 4)
1840 s->dma_adc.ossfragshift = 4;
1841 if (s->dma_adc.ossfragshift > 15)
1842 s->dma_adc.ossfragshift = 15;
1843 if (s->dma_adc.ossmaxfrags < 4)
1844 s->dma_adc.ossmaxfrags = 4;
1845 }
1846 if (file->f_mode & FMODE_WRITE) {
1847 s->dma_dac.ossfragshift = val & 0xffff;
1848 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1849 if (s->dma_dac.ossfragshift < 4)
1850 s->dma_dac.ossfragshift = 4;
1851 if (s->dma_dac.ossfragshift > 15)
1852 s->dma_dac.ossfragshift = 15;
1853 if (s->dma_dac.ossmaxfrags < 4)
1854 s->dma_dac.ossmaxfrags = 4;
1855 }
1856 return 0;
1857
1858 case SNDCTL_DSP_SUBDIVIDE:
1859 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1860 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1861 return -EINVAL;
1862 if (get_user(val, p))
1863 return -EFAULT;
1864 if (val != 1 && val != 2 && val != 4)
1865 return -EINVAL;
1866 if (file->f_mode & FMODE_READ)
1867 s->dma_adc.subdivision = val;
1868 if (file->f_mode & FMODE_WRITE)
1869 s->dma_dac.subdivision = val;
1870 return 0;
1871
1872 case SOUND_PCM_READ_RATE:
1873 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1874
1875 case SOUND_PCM_READ_CHANNELS:
1876 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1877 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
1878
1879 case SOUND_PCM_READ_BITS:
1880 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1881 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? 16 : 8, p);
1882
1883 case SOUND_PCM_WRITE_FILTER:
1884 case SNDCTL_DSP_SETSYNCRO:
1885 case SOUND_PCM_READ_FILTER:
1886 return -EINVAL;
1887
1888 }
1889 return mixer_ioctl(s, cmd, arg);
1890}
1891
1892static int sv_open(struct inode *inode, struct file *file)
1893{
1894 int minor = iminor(inode);
1895 DECLARE_WAITQUEUE(wait, current);
1896 unsigned char fmtm = ~0, fmts = 0;
1897 struct list_head *list;
1898 struct sv_state *s;
1899
1900 for (list = devs.next; ; list = list->next) {
1901 if (list == &devs)
1902 return -ENODEV;
1903 s = list_entry(list, struct sv_state, devs);
1904 if (!((s->dev_audio ^ minor) & ~0xf))
1905 break;
1906 }
1907 VALIDATE_STATE(s);
1908 file->private_data = s;
1909 /* wait for device to become free */
1910 mutex_lock(&s->open_mutex);
1911 while (s->open_mode & file->f_mode) {
1912 if (file->f_flags & O_NONBLOCK) {
1913 mutex_unlock(&s->open_mutex);
1914 return -EBUSY;
1915 }
1916 add_wait_queue(&s->open_wait, &wait);
1917 __set_current_state(TASK_INTERRUPTIBLE);
1918 mutex_unlock(&s->open_mutex);
1919 schedule();
1920 remove_wait_queue(&s->open_wait, &wait);
1921 set_current_state(TASK_RUNNING);
1922 if (signal_pending(current))
1923 return -ERESTARTSYS;
1924 mutex_lock(&s->open_mutex);
1925 }
1926 if (file->f_mode & FMODE_READ) {
1927 fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
1928 if ((minor & 0xf) == SND_DEV_DSP16)
1929 fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1930 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1931 s->dma_adc.enabled = 1;
1932 set_adc_rate(s, 8000);
1933 }
1934 if (file->f_mode & FMODE_WRITE) {
1935 fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
1936 if ((minor & 0xf) == SND_DEV_DSP16)
1937 fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1938 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1939 s->dma_dac.enabled = 1;
1940 set_dac_rate(s, 8000);
1941 }
1942 set_fmt(s, fmtm, fmts);
1943 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1944 mutex_unlock(&s->open_mutex);
1945 return nonseekable_open(inode, file);
1946}
1947
1948static int sv_release(struct inode *inode, struct file *file)
1949{
1950 struct sv_state *s = (struct sv_state *)file->private_data;
1951
1952 VALIDATE_STATE(s);
1953 lock_kernel();
1954 if (file->f_mode & FMODE_WRITE)
1955 drain_dac(s, file->f_flags & O_NONBLOCK);
1956 mutex_lock(&s->open_mutex);
1957 if (file->f_mode & FMODE_WRITE) {
1958 stop_dac(s);
1959 dealloc_dmabuf(s, &s->dma_dac);
1960 }
1961 if (file->f_mode & FMODE_READ) {
1962 stop_adc(s);
1963 dealloc_dmabuf(s, &s->dma_adc);
1964 }
1965 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
1966 wake_up(&s->open_wait);
1967 mutex_unlock(&s->open_mutex);
1968 unlock_kernel();
1969 return 0;
1970}
1971
1972static /*const*/ struct file_operations sv_audio_fops = {
1973 .owner = THIS_MODULE,
1974 .llseek = no_llseek,
1975 .read = sv_read,
1976 .write = sv_write,
1977 .poll = sv_poll,
1978 .ioctl = sv_ioctl,
1979 .mmap = sv_mmap,
1980 .open = sv_open,
1981 .release = sv_release,
1982};
1983
1984/* --------------------------------------------------------------------- */
1985
1986static ssize_t sv_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1987{
1988 struct sv_state *s = (struct sv_state *)file->private_data;
1989 DECLARE_WAITQUEUE(wait, current);
1990 ssize_t ret;
1991 unsigned long flags;
1992 unsigned ptr;
1993 int cnt;
1994
1995 VALIDATE_STATE(s);
1996 if (!access_ok(VERIFY_WRITE, buffer, count))
1997 return -EFAULT;
1998 if (count == 0)
1999 return 0;
2000 ret = 0;
2001 add_wait_queue(&s->midi.iwait, &wait);
2002 while (count > 0) {
2003 spin_lock_irqsave(&s->lock, flags);
2004 ptr = s->midi.ird;
2005 cnt = MIDIINBUF - ptr;
2006 if (s->midi.icnt < cnt)
2007 cnt = s->midi.icnt;
2008 if (cnt <= 0)
2009 __set_current_state(TASK_INTERRUPTIBLE);
2010 spin_unlock_irqrestore(&s->lock, flags);
2011 if (cnt > count)
2012 cnt = count;
2013 if (cnt <= 0) {
2014 if (file->f_flags & O_NONBLOCK) {
2015 if (!ret)
2016 ret = -EAGAIN;
2017 break;
2018 }
2019 schedule();
2020 if (signal_pending(current)) {
2021 if (!ret)
2022 ret = -ERESTARTSYS;
2023 break;
2024 }
2025 continue;
2026 }
2027 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2028 if (!ret)
2029 ret = -EFAULT;
2030 break;
2031 }
2032 ptr = (ptr + cnt) % MIDIINBUF;
2033 spin_lock_irqsave(&s->lock, flags);
2034 s->midi.ird = ptr;
2035 s->midi.icnt -= cnt;
2036 spin_unlock_irqrestore(&s->lock, flags);
2037 count -= cnt;
2038 buffer += cnt;
2039 ret += cnt;
2040 break;
2041 }
2042 __set_current_state(TASK_RUNNING);
2043 remove_wait_queue(&s->midi.iwait, &wait);
2044 return ret;
2045}
2046
2047static ssize_t sv_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2048{
2049 struct sv_state *s = (struct sv_state *)file->private_data;
2050 DECLARE_WAITQUEUE(wait, current);
2051 ssize_t ret;
2052 unsigned long flags;
2053 unsigned ptr;
2054 int cnt;
2055
2056 VALIDATE_STATE(s);
2057 if (!access_ok(VERIFY_READ, buffer, count))
2058 return -EFAULT;
2059 if (count == 0)
2060 return 0;
2061 ret = 0;
2062 add_wait_queue(&s->midi.owait, &wait);
2063 while (count > 0) {
2064 spin_lock_irqsave(&s->lock, flags);
2065 ptr = s->midi.owr;
2066 cnt = MIDIOUTBUF - ptr;
2067 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2068 cnt = MIDIOUTBUF - s->midi.ocnt;
2069 if (cnt <= 0) {
2070 __set_current_state(TASK_INTERRUPTIBLE);
2071 sv_handle_midi(s);
2072 }
2073 spin_unlock_irqrestore(&s->lock, flags);
2074 if (cnt > count)
2075 cnt = count;
2076 if (cnt <= 0) {
2077 if (file->f_flags & O_NONBLOCK) {
2078 if (!ret)
2079 ret = -EAGAIN;
2080 break;
2081 }
2082 schedule();
2083 if (signal_pending(current)) {
2084 if (!ret)
2085 ret = -ERESTARTSYS;
2086 break;
2087 }
2088 continue;
2089 }
2090 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2091 if (!ret)
2092 ret = -EFAULT;
2093 break;
2094 }
2095 ptr = (ptr + cnt) % MIDIOUTBUF;
2096 spin_lock_irqsave(&s->lock, flags);
2097 s->midi.owr = ptr;
2098 s->midi.ocnt += cnt;
2099 spin_unlock_irqrestore(&s->lock, flags);
2100 count -= cnt;
2101 buffer += cnt;
2102 ret += cnt;
2103 spin_lock_irqsave(&s->lock, flags);
2104 sv_handle_midi(s);
2105 spin_unlock_irqrestore(&s->lock, flags);
2106 }
2107 __set_current_state(TASK_RUNNING);
2108 remove_wait_queue(&s->midi.owait, &wait);
2109 return ret;
2110}
2111
2112/* No kernel lock - we have our own spinlock */
2113static unsigned int sv_midi_poll(struct file *file, struct poll_table_struct *wait)
2114{
2115 struct sv_state *s = (struct sv_state *)file->private_data;
2116 unsigned long flags;
2117 unsigned int mask = 0;
2118
2119 VALIDATE_STATE(s);
2120 if (file->f_mode & FMODE_WRITE)
2121 poll_wait(file, &s->midi.owait, wait);
2122 if (file->f_mode & FMODE_READ)
2123 poll_wait(file, &s->midi.iwait, wait);
2124 spin_lock_irqsave(&s->lock, flags);
2125 if (file->f_mode & FMODE_READ) {
2126 if (s->midi.icnt > 0)
2127 mask |= POLLIN | POLLRDNORM;
2128 }
2129 if (file->f_mode & FMODE_WRITE) {
2130 if (s->midi.ocnt < MIDIOUTBUF)
2131 mask |= POLLOUT | POLLWRNORM;
2132 }
2133 spin_unlock_irqrestore(&s->lock, flags);
2134 return mask;
2135}
2136
2137static int sv_midi_open(struct inode *inode, struct file *file)
2138{
2139 int minor = iminor(inode);
2140 DECLARE_WAITQUEUE(wait, current);
2141 unsigned long flags;
2142 struct list_head *list;
2143 struct sv_state *s;
2144
2145 for (list = devs.next; ; list = list->next) {
2146 if (list == &devs)
2147 return -ENODEV;
2148 s = list_entry(list, struct sv_state, devs);
2149 if (s->dev_midi == minor)
2150 break;
2151 }
2152 VALIDATE_STATE(s);
2153 file->private_data = s;
2154 /* wait for device to become free */
2155 mutex_lock(&s->open_mutex);
2156 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2157 if (file->f_flags & O_NONBLOCK) {
2158 mutex_unlock(&s->open_mutex);
2159 return -EBUSY;
2160 }
2161 add_wait_queue(&s->open_wait, &wait);
2162 __set_current_state(TASK_INTERRUPTIBLE);
2163 mutex_unlock(&s->open_mutex);
2164 schedule();
2165 remove_wait_queue(&s->open_wait, &wait);
2166 set_current_state(TASK_RUNNING);
2167 if (signal_pending(current))
2168 return -ERESTARTSYS;
2169 mutex_lock(&s->open_mutex);
2170 }
2171 spin_lock_irqsave(&s->lock, flags);
2172 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2173 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2174 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2175 //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
2176 outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2177 wrindir(s, SV_CIUARTCONTROL, 5); /* output MIDI data to external and internal synth */
2178 wrindir(s, SV_CIWAVETABLESRC, 1); /* Wavetable in PC RAM */
2179 outb(0xff, s->iomidi+1); /* reset command */
2180 outb(0x3f, s->iomidi+1); /* uart command */
2181 if (!(inb(s->iomidi+1) & 0x80))
2182 inb(s->iomidi);
2183 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2184 init_timer(&s->midi.timer);
2185 s->midi.timer.expires = jiffies+1;
2186 s->midi.timer.data = (unsigned long)s;
2187 s->midi.timer.function = sv_midi_timer;
2188 add_timer(&s->midi.timer);
2189 }
2190 if (file->f_mode & FMODE_READ) {
2191 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2192 }
2193 if (file->f_mode & FMODE_WRITE) {
2194 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2195 }
2196 spin_unlock_irqrestore(&s->lock, flags);
2197 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2198 mutex_unlock(&s->open_mutex);
2199 return nonseekable_open(inode, file);
2200}
2201
2202static int sv_midi_release(struct inode *inode, struct file *file)
2203{
2204 struct sv_state *s = (struct sv_state *)file->private_data;
2205 DECLARE_WAITQUEUE(wait, current);
2206 unsigned long flags;
2207 unsigned count, tmo;
2208
2209 VALIDATE_STATE(s);
2210
2211 lock_kernel();
2212 if (file->f_mode & FMODE_WRITE) {
2213 add_wait_queue(&s->midi.owait, &wait);
2214 for (;;) {
2215 __set_current_state(TASK_INTERRUPTIBLE);
2216 spin_lock_irqsave(&s->lock, flags);
2217 count = s->midi.ocnt;
2218 spin_unlock_irqrestore(&s->lock, flags);
2219 if (count <= 0)
2220 break;
2221 if (signal_pending(current))
2222 break;
2223 if (file->f_flags & O_NONBLOCK) {
2224 remove_wait_queue(&s->midi.owait, &wait);
2225 set_current_state(TASK_RUNNING);
2226 unlock_kernel();
2227 return -EBUSY;
2228 }
2229 tmo = (count * HZ) / 3100;
2230 if (!schedule_timeout(tmo ? : 1) && tmo)
2231 printk(KERN_DEBUG "sv: midi timed out??\n");
2232 }
2233 remove_wait_queue(&s->midi.owait, &wait);
2234 set_current_state(TASK_RUNNING);
2235 }
2236 mutex_lock(&s->open_mutex);
2237 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2238 spin_lock_irqsave(&s->lock, flags);
2239 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2240 outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2241 del_timer(&s->midi.timer);
2242 }
2243 spin_unlock_irqrestore(&s->lock, flags);
2244 wake_up(&s->open_wait);
2245 mutex_unlock(&s->open_mutex);
2246 unlock_kernel();
2247 return 0;
2248}
2249
2250static /*const*/ struct file_operations sv_midi_fops = {
2251 .owner = THIS_MODULE,
2252 .llseek = no_llseek,
2253 .read = sv_midi_read,
2254 .write = sv_midi_write,
2255 .poll = sv_midi_poll,
2256 .open = sv_midi_open,
2257 .release = sv_midi_release,
2258};
2259
2260/* --------------------------------------------------------------------- */
2261
2262static int sv_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2263{
2264 static const unsigned char op_offset[18] = {
2265 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2266 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2267 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2268 };
2269 struct sv_state *s = (struct sv_state *)file->private_data;
2270 struct dm_fm_voice v;
2271 struct dm_fm_note n;
2272 struct dm_fm_params p;
2273 unsigned int io;
2274 unsigned int regb;
2275
2276 switch (cmd) {
2277 case FM_IOCTL_RESET:
2278 for (regb = 0xb0; regb < 0xb9; regb++) {
2279 outb(regb, s->iosynth);
2280 outb(0, s->iosynth+1);
2281 outb(regb, s->iosynth+2);
2282 outb(0, s->iosynth+3);
2283 }
2284 return 0;
2285
2286 case FM_IOCTL_PLAY_NOTE:
2287 if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
2288 return -EFAULT;
2289 if (n.voice >= 18)
2290 return -EINVAL;
2291 if (n.voice >= 9) {
2292 regb = n.voice - 9;
2293 io = s->iosynth+2;
2294 } else {
2295 regb = n.voice;
2296 io = s->iosynth;
2297 }
2298 outb(0xa0 + regb, io);
2299 outb(n.fnum & 0xff, io+1);
2300 outb(0xb0 + regb, io);
2301 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2302 return 0;
2303
2304 case FM_IOCTL_SET_VOICE:
2305 if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
2306 return -EFAULT;
2307 if (v.voice >= 18)
2308 return -EINVAL;
2309 regb = op_offset[v.voice];
2310 io = s->iosynth + ((v.op & 1) << 1);
2311 outb(0x20 + regb, io);
2312 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2313 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2314 outb(0x40 + regb, io);
2315 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2316 outb(0x60 + regb, io);
2317 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2318 outb(0x80 + regb, io);
2319 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2320 outb(0xe0 + regb, io);
2321 outb(v.waveform & 0x7, io+1);
2322 if (n.voice >= 9) {
2323 regb = n.voice - 9;
2324 io = s->iosynth+2;
2325 } else {
2326 regb = n.voice;
2327 io = s->iosynth;
2328 }
2329 outb(0xc0 + regb, io);
2330 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2331 (v.connection & 1), io+1);
2332 return 0;
2333
2334 case FM_IOCTL_SET_PARAMS:
2335 if (copy_from_user(&p, (void *__user )arg, sizeof(p)))
2336 return -EFAULT;
2337 outb(0x08, s->iosynth);
2338 outb((p.kbd_split & 1) << 6, s->iosynth+1);
2339 outb(0xbd, s->iosynth);
2340 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2341 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->iosynth+1);
2342 return 0;
2343
2344 case FM_IOCTL_SET_OPL:
2345 outb(4, s->iosynth+2);
2346 outb(arg, s->iosynth+3);
2347 return 0;
2348
2349 case FM_IOCTL_SET_MODE:
2350 outb(5, s->iosynth+2);
2351 outb(arg & 1, s->iosynth+3);
2352 return 0;
2353
2354 default:
2355 return -EINVAL;
2356 }
2357}
2358
2359static int sv_dmfm_open(struct inode *inode, struct file *file)
2360{
2361 int minor = iminor(inode);
2362 DECLARE_WAITQUEUE(wait, current);
2363 struct list_head *list;
2364 struct sv_state *s;
2365
2366 for (list = devs.next; ; list = list->next) {
2367 if (list == &devs)
2368 return -ENODEV;
2369 s = list_entry(list, struct sv_state, devs);
2370 if (s->dev_dmfm == minor)
2371 break;
2372 }
2373 VALIDATE_STATE(s);
2374 file->private_data = s;
2375 /* wait for device to become free */
2376 mutex_lock(&s->open_mutex);
2377 while (s->open_mode & FMODE_DMFM) {
2378 if (file->f_flags & O_NONBLOCK) {
2379 mutex_unlock(&s->open_mutex);
2380 return -EBUSY;
2381 }
2382 add_wait_queue(&s->open_wait, &wait);
2383 __set_current_state(TASK_INTERRUPTIBLE);
2384 mutex_unlock(&s->open_mutex);
2385 schedule();
2386 remove_wait_queue(&s->open_wait, &wait);
2387 set_current_state(TASK_RUNNING);
2388 if (signal_pending(current))
2389 return -ERESTARTSYS;
2390 mutex_lock(&s->open_mutex);
2391 }
2392 /* init the stuff */
2393 outb(1, s->iosynth);
2394 outb(0x20, s->iosynth+1); /* enable waveforms */
2395 outb(4, s->iosynth+2);
2396 outb(0, s->iosynth+3); /* no 4op enabled */
2397 outb(5, s->iosynth+2);
2398 outb(1, s->iosynth+3); /* enable OPL3 */
2399 s->open_mode |= FMODE_DMFM;
2400 mutex_unlock(&s->open_mutex);
2401 return nonseekable_open(inode, file);
2402}
2403
2404static int sv_dmfm_release(struct inode *inode, struct file *file)
2405{
2406 struct sv_state *s = (struct sv_state *)file->private_data;
2407 unsigned int regb;
2408
2409 VALIDATE_STATE(s);
2410 lock_kernel();
2411 mutex_lock(&s->open_mutex);
2412 s->open_mode &= ~FMODE_DMFM;
2413 for (regb = 0xb0; regb < 0xb9; regb++) {
2414 outb(regb, s->iosynth);
2415 outb(0, s->iosynth+1);
2416 outb(regb, s->iosynth+2);
2417 outb(0, s->iosynth+3);
2418 }
2419 wake_up(&s->open_wait);
2420 mutex_unlock(&s->open_mutex);
2421 unlock_kernel();
2422 return 0;
2423}
2424
2425static /*const*/ struct file_operations sv_dmfm_fops = {
2426 .owner = THIS_MODULE,
2427 .llseek = no_llseek,
2428 .ioctl = sv_dmfm_ioctl,
2429 .open = sv_dmfm_open,
2430 .release = sv_dmfm_release,
2431};
2432
2433/* --------------------------------------------------------------------- */
2434
2435/* maximum number of devices; only used for command line params */
2436#define NR_DEVICE 5
2437
2438static int reverb[NR_DEVICE];
2439
2440#if 0
2441static int wavetable[NR_DEVICE];
2442#endif
2443
2444static unsigned int devindex;
2445
2446module_param_array(reverb, bool, NULL, 0);
2447MODULE_PARM_DESC(reverb, "if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
2448#if 0
2449MODULE_PARM(wavetable, "1-" __MODULE_STRING(NR_DEVICE) "i");
2450MODULE_PARM_DESC(wavetable, "if 1 the wavetable synth is enabled");
2451#endif
2452
2453MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2454MODULE_DESCRIPTION("S3 SonicVibes Driver");
2455MODULE_LICENSE("GPL");
2456
2457
2458/* --------------------------------------------------------------------- */
2459
2460static struct initvol {
2461 int mixch;
2462 int vol;
2463} initvol[] __devinitdata = {
2464 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2465 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2466 { SOUND_MIXER_WRITE_CD, 0x4040 },
2467 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2468 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2469 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2470 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2471 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2472 { SOUND_MIXER_WRITE_PCM, 0x4040 }
2473};
2474
2475#define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
2476 (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
2477
2478#ifdef SUPPORT_JOYSTICK
2479static int __devinit sv_register_gameport(struct sv_state *s, int io_port)
2480{
2481 struct gameport *gp;
2482
2483 if (!request_region(io_port, SV_EXTENT_GAME, "S3 SonicVibes Gameport")) {
2484 printk(KERN_ERR "sv: gameport io ports are in use\n");
2485 return -EBUSY;
2486 }
2487
2488 s->gameport = gp = gameport_allocate_port();
2489 if (!gp) {
2490 printk(KERN_ERR "sv: can not allocate memory for gameport\n");
2491 release_region(io_port, SV_EXTENT_GAME);
2492 return -ENOMEM;
2493 }
2494
2495 gameport_set_name(gp, "S3 SonicVibes Gameport");
2496 gameport_set_phys(gp, "isa%04x/gameport0", io_port);
2497 gp->dev.parent = &s->dev->dev;
2498 gp->io = io_port;
2499
2500 gameport_register_port(gp);
2501
2502 return 0;
2503}
2504
2505static inline void sv_unregister_gameport(struct sv_state *s)
2506{
2507 if (s->gameport) {
2508 int gpio = s->gameport->io;
2509 gameport_unregister_port(s->gameport);
2510 release_region(gpio, SV_EXTENT_GAME);
2511 }
2512}
2513#else
2514static inline int sv_register_gameport(struct sv_state *s, int io_port) { return -ENOSYS; }
2515static inline void sv_unregister_gameport(struct sv_state *s) { }
2516#endif /* SUPPORT_JOYSTICK */
2517
2518static int __devinit sv_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2519{
2520 static char __devinitdata sv_ddma_name[] = "S3 Inc. SonicVibes DDMA Controller";
2521 struct sv_state *s;
2522 mm_segment_t fs;
2523 int i, val, ret;
2524 int gpio;
2525 char *ddmaname;
2526 unsigned ddmanamelen;
2527
2528 if ((ret=pci_enable_device(pcidev)))
2529 return ret;
2530
2531 if (!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
2532 !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
2533 !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
2534 !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
2535 !RSRCISIOREGION(pcidev, RESOURCE_GAME))
2536 return -ENODEV;
2537 if (pcidev->irq == 0)
2538 return -ENODEV;
2539 if (pci_set_dma_mask(pcidev, DMA_24BIT_MASK)) {
2540 printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
2541 return -ENODEV;
2542 }
2543 /* try to allocate a DDMA resource if not already available */
2544 if (!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
2545 pcidev->resource[RESOURCE_DDMA].start = 0;
2546 pcidev->resource[RESOURCE_DDMA].end = 2*SV_EXTENT_DMA-1;
2547 pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
2548 ddmanamelen = strlen(sv_ddma_name)+1;
2549 if (!(ddmaname = kmalloc(ddmanamelen, GFP_KERNEL)))
2550 return -1;
2551 memcpy(ddmaname, sv_ddma_name, ddmanamelen);
2552 pcidev->resource[RESOURCE_DDMA].name = ddmaname;
2553 if (pci_assign_resource(pcidev, RESOURCE_DDMA)) {
2554 pcidev->resource[RESOURCE_DDMA].name = NULL;
2555 kfree(ddmaname);
2556 printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
2557 return -EBUSY;
2558 }
2559 }
2560 if (!(s = kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
2561 printk(KERN_WARNING "sv: out of memory\n");
2562 return -ENOMEM;
2563 }
2564 memset(s, 0, sizeof(struct sv_state));
2565 init_waitqueue_head(&s->dma_adc.wait);
2566 init_waitqueue_head(&s->dma_dac.wait);
2567 init_waitqueue_head(&s->open_wait);
2568 init_waitqueue_head(&s->midi.iwait);
2569 init_waitqueue_head(&s->midi.owait);
2570 mutex_init(&s->open_mutex);
2571 spin_lock_init(&s->lock);
2572 s->magic = SV_MAGIC;
2573 s->dev = pcidev;
2574 s->iosb = pci_resource_start(pcidev, RESOURCE_SB);
2575 s->ioenh = pci_resource_start(pcidev, RESOURCE_ENH);
2576 s->iosynth = pci_resource_start(pcidev, RESOURCE_SYNTH);
2577 s->iomidi = pci_resource_start(pcidev, RESOURCE_MIDI);
2578 s->iodmaa = pci_resource_start(pcidev, RESOURCE_DDMA);
2579 s->iodmac = pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
2580 gpio = pci_resource_start(pcidev, RESOURCE_GAME);
2581 pci_write_config_dword(pcidev, 0x40, s->iodmaa | 9); /* enable and use extended mode */
2582 pci_write_config_dword(pcidev, 0x48, s->iodmac | 9); /* enable */
2583 printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#x %#x %#x\n",
2584 s->iosb, s->ioenh, s->iosynth, s->iomidi, gpio, s->iodmaa, s->iodmac);
2585 s->irq = pcidev->irq;
2586
2587 /* hack */
2588 pci_write_config_dword(pcidev, 0x60, wavetable_mem >> 12); /* wavetable base address */
2589
2590 ret = -EBUSY;
2591 if (!request_region(s->ioenh, SV_EXTENT_ENH, "S3 SonicVibes PCM")) {
2592 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
2593 goto err_region5;
2594 }
2595 if (!request_region(s->iodmaa, SV_EXTENT_DMA, "S3 SonicVibes DMAA")) {
2596 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
2597 goto err_region4;
2598 }
2599 if (!request_region(s->iodmac, SV_EXTENT_DMA, "S3 SonicVibes DMAC")) {
2600 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
2601 goto err_region3;
2602 }
2603 if (!request_region(s->iomidi, SV_EXTENT_MIDI, "S3 SonicVibes Midi")) {
2604 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
2605 goto err_region2;
2606 }
2607 if (!request_region(s->iosynth, SV_EXTENT_SYNTH, "S3 SonicVibes Synth")) {
2608 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
2609 goto err_region1;
2610 }
2611
2612 /* initialize codec registers */
2613 outb(0x80, s->ioenh + SV_CODEC_CONTROL); /* assert reset */
2614 udelay(50);
2615 outb(0x00, s->ioenh + SV_CODEC_CONTROL); /* deassert reset */
2616 udelay(50);
2617 outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
2618 | (reverb[devindex] ? SV_CCTRL_REVERB : 0), s->ioenh + SV_CODEC_CONTROL);
2619 inb(s->ioenh + SV_CODEC_STATUS); /* clear ints */
2620 wrindir(s, SV_CIDRIVECONTROL, 0); /* drive current 16mA */
2621 wrindir(s, SV_CIENABLE, s->enable = 0); /* disable DMAA and DMAC */
2622 outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
2623 /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
2624 /* outb(0xff, s->iodmac + SV_DMA_RESET); */
2625 inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
2626 wrindir(s, SV_CIADCCLKSOURCE, 0); /* use pll as ADC clock source */
2627 wrindir(s, SV_CIANALOGPWRDOWN, 0); /* power up the analog parts of the device */
2628 wrindir(s, SV_CIDIGITALPWRDOWN, 0); /* power up the digital parts of the device */
2629 setpll(s, SV_CIADCPLLM, 8000);
2630 wrindir(s, SV_CISRSSPACE, 0x80); /* SRS off */
2631 wrindir(s, SV_CIPCMSR0, (8000 * 65536 / FULLRATE) & 0xff);
2632 wrindir(s, SV_CIPCMSR1, ((8000 * 65536 / FULLRATE) >> 8) & 0xff);
2633 wrindir(s, SV_CIADCOUTPUT, 0);
2634 /* request irq */
2635 if ((ret=request_irq(s->irq,sv_interrupt,IRQF_SHARED,"S3 SonicVibes",s))) {
2636 printk(KERN_ERR "sv: irq %u in use\n", s->irq);
2637 goto err_irq;
2638 }
2639 printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
2640 s->ioenh, s->irq, s->iodmaa, s->iodmac, rdindir(s, SV_CIREVISION));
2641 /* register devices */
2642 if ((s->dev_audio = register_sound_dsp(&sv_audio_fops, -1)) < 0) {
2643 ret = s->dev_audio;
2644 goto err_dev1;
2645 }
2646 if ((s->dev_mixer = register_sound_mixer(&sv_mixer_fops, -1)) < 0) {
2647 ret = s->dev_mixer;
2648 goto err_dev2;
2649 }
2650 if ((s->dev_midi = register_sound_midi(&sv_midi_fops, -1)) < 0) {
2651 ret = s->dev_midi;
2652 goto err_dev3;
2653 }
2654 if ((s->dev_dmfm = register_sound_special(&sv_dmfm_fops, 15 /* ?? */)) < 0) {
2655 ret = s->dev_dmfm;
2656 goto err_dev4;
2657 }
2658 pci_set_master(pcidev); /* enable bus mastering */
2659 /* initialize the chips */
2660 fs = get_fs();
2661 set_fs(KERNEL_DS);
2662 val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
2663 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2664 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2665 val = initvol[i].vol;
2666 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2667 }
2668 set_fs(fs);
2669 /* register gameport */
2670 sv_register_gameport(s, gpio);
2671 /* store it in the driver field */
2672 pci_set_drvdata(pcidev, s);
2673 /* put it into driver list */
2674 list_add_tail(&s->devs, &devs);
2675 /* increment devindex */
2676 if (devindex < NR_DEVICE-1)
2677 devindex++;
2678 return 0;
2679
2680 err_dev4:
2681 unregister_sound_midi(s->dev_midi);
2682 err_dev3:
2683 unregister_sound_mixer(s->dev_mixer);
2684 err_dev2:
2685 unregister_sound_dsp(s->dev_audio);
2686 err_dev1:
2687 printk(KERN_ERR "sv: cannot register misc device\n");
2688 free_irq(s->irq, s);
2689 err_irq:
2690 release_region(s->iosynth, SV_EXTENT_SYNTH);
2691 err_region1:
2692 release_region(s->iomidi, SV_EXTENT_MIDI);
2693 err_region2:
2694 release_region(s->iodmac, SV_EXTENT_DMA);
2695 err_region3:
2696 release_region(s->iodmaa, SV_EXTENT_DMA);
2697 err_region4:
2698 release_region(s->ioenh, SV_EXTENT_ENH);
2699 err_region5:
2700 kfree(s);
2701 return ret;
2702}
2703
2704static void __devexit sv_remove(struct pci_dev *dev)
2705{
2706 struct sv_state *s = pci_get_drvdata(dev);
2707
2708 if (!s)
2709 return;
2710 list_del(&s->devs);
2711 outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
2712 synchronize_irq(s->irq);
2713 inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
2714 wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
2715 /*outb(0, s->iodmaa + SV_DMA_RESET);*/
2716 /*outb(0, s->iodmac + SV_DMA_RESET);*/
2717 free_irq(s->irq, s);
2718 sv_unregister_gameport(s);
2719 release_region(s->iodmac, SV_EXTENT_DMA);
2720 release_region(s->iodmaa, SV_EXTENT_DMA);
2721 release_region(s->ioenh, SV_EXTENT_ENH);
2722 release_region(s->iomidi, SV_EXTENT_MIDI);
2723 release_region(s->iosynth, SV_EXTENT_SYNTH);
2724 unregister_sound_dsp(s->dev_audio);
2725 unregister_sound_mixer(s->dev_mixer);
2726 unregister_sound_midi(s->dev_midi);
2727 unregister_sound_special(s->dev_dmfm);
2728 kfree(s);
2729 pci_set_drvdata(dev, NULL);
2730}
2731
2732static struct pci_device_id id_table[] = {
2733 { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2734 { 0, }
2735};
2736
2737MODULE_DEVICE_TABLE(pci, id_table);
2738
2739static struct pci_driver sv_driver = {
2740 .name = "sonicvibes",
2741 .id_table = id_table,
2742 .probe = sv_probe,
2743 .remove = __devexit_p(sv_remove),
2744};
2745
2746static int __init init_sonicvibes(void)
2747{
2748 printk(KERN_INFO "sv: version v0.31 time " __TIME__ " " __DATE__ "\n");
2749#if 0
2750 if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
2751 printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
2752#endif
2753 return pci_register_driver(&sv_driver);
2754}
2755
2756static void __exit cleanup_sonicvibes(void)
2757{
2758 printk(KERN_INFO "sv: unloading\n");
2759 pci_unregister_driver(&sv_driver);
2760 if (wavetable_mem)
2761 free_pages(wavetable_mem, 20-PAGE_SHIFT);
2762}
2763
2764module_init(init_sonicvibes);
2765module_exit(cleanup_sonicvibes);
2766
2767/* --------------------------------------------------------------------- */
2768
2769#ifndef MODULE
2770
2771/* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
2772
2773static int __init sonicvibes_setup(char *str)
2774{
2775 static unsigned __initdata nr_dev = 0;
2776
2777 if (nr_dev >= NR_DEVICE)
2778 return 0;
2779#if 0
2780 if (get_option(&str, &reverb[nr_dev]) == 2)
2781 (void)get_option(&str, &wavetable[nr_dev]);
2782#else
2783 (void)get_option(&str, &reverb[nr_dev]);
2784#endif
2785
2786 nr_dev++;
2787 return 1;
2788}
2789
2790__setup("sonicvibes=", sonicvibes_setup);
2791
2792#endif /* MODULE */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 00:17:50 -0500