diff options
Diffstat (limited to 'sound/oss/ad1889.h')
| -rw-r--r-- | sound/oss/ad1889.h | 101 |
1 files changed, 51 insertions, 50 deletions
diff --git a/sound/oss/ad1889.h b/sound/oss/ad1889.h index 861b3213f30b..09913765967a 100644 --- a/sound/oss/ad1889.h +++ b/sound/oss/ad1889.h | |||
| @@ -1,57 +1,58 @@ | |||
| 1 | #ifndef _AD1889_H_ | 1 | #ifndef _AD1889_H_ |
| 2 | #define _AD1889_H_ | 2 | #define _AD1889_H_ |
| 3 | 3 | ||
| 4 | #define AD_DSWSMC 0x00 /* DMA input wave/syn mixer control */ | 4 | #define AD_DS_WSMC 0x00 /* DMA input wave/syn mixer control */ |
| 5 | #define AD_DSRAMC 0x02 /* DMA output resamp/ADC mixer control */ | 5 | #define AD_DS_RAMC 0x02 /* DMA output resamp/ADC mixer control */ |
| 6 | #define AD_DSWADA 0x04 /* DMA input wave attenuation */ | 6 | #define AD_DS_WADA 0x04 /* DMA input wave attenuation */ |
| 7 | #define AD_DSSYDA 0x06 /* DMA input syn attentuation */ | 7 | #define AD_DS_SYDA 0x06 /* DMA input syn attentuation */ |
| 8 | #define AD_DSWAS 0x08 /* wave input sample rate */ | 8 | #define AD_DS_WAS 0x08 /* wave input sample rate */ |
| 9 | #define AD_DSRES 0x0a /* resampler output sample rate */ | 9 | #define AD_DS_RES 0x0a /* resampler output sample rate */ |
| 10 | #define AD_DSCCS 0x0c /* chip control/status */ | 10 | #define AD_DS_CCS 0x0c /* chip control/status */ |
| 11 | 11 | ||
| 12 | #define AD_DMARESBA 0x40 /* RES base addr */ | 12 | #define AD_DMA_RESBA 0x40 /* RES base addr */ |
| 13 | #define AD_DMARESCA 0x44 /* RES current addr */ | 13 | #define AD_DMA_RESCA 0x44 /* RES current addr */ |
| 14 | #define AD_DMARESBC 0x48 /* RES base cnt */ | 14 | #define AD_DMA_RESBC 0x48 /* RES base cnt */ |
| 15 | #define AD_DMARESCC 0x4c /* RES current count */ | 15 | #define AD_DMA_RESCC 0x4c /* RES current count */ |
| 16 | #define AD_DMAADCBA 0x50 /* ADC */ | 16 | #define AD_DMA_ADCBA 0x50 /* ADC */ |
| 17 | #define AD_DMAADCCA 0x54 | 17 | #define AD_DMA_ADCCA 0x54 |
| 18 | #define AD_DMAADCBC 0x58 | 18 | #define AD_DMA_ADCBC 0x58 |
| 19 | #define AD_DMAADCCC 0x5c | 19 | #define AD_DMA_ADCCC 0x5c |
| 20 | #define AD_DMASYNBA 0x60 /* SYN */ | 20 | #define AD_DMA_SYNBA 0x60 /* SYN */ |
| 21 | #define AD_DMASYNCA 0x64 | 21 | #define AD_DMA_SYNCA 0x64 |
| 22 | #define AD_DMASYNBC 0x68 | 22 | #define AD_DMA_SYNBC 0x68 |
| 23 | #define AD_DMASYNCC 0x6c | 23 | #define AD_DMA_SYNCC 0x6c |
| 24 | #define AD_DMAWAVBA 0x70 /* WAV */ | 24 | #define AD_DMA_WAVBA 0x70 /* WAV */ |
| 25 | #define AD_DMAWAVCA 0x74 | 25 | #define AD_DMA_WAVCA 0x74 |
| 26 | #define AD_DMAWAVBC 0x78 | 26 | #define AD_DMA_WAVBC 0x78 |
| 27 | #define AD_DMAWAVCC 0x7c | 27 | #define AD_DMA_WAVCC 0x7c |
| 28 | #define AD_DMARESICC 0x80 /* RES interrupt current count */ | 28 | #define AD_DMA_RESICC 0x80 /* RES interrupt current count */ |
| 29 | #define AD_DMARESIBC 0x84 /* RES interrupt base count */ | 29 | #define AD_DMA_RESIBC 0x84 /* RES interrupt base count */ |
| 30 | #define AD_DMAADCICC 0x88 /* ADC interrupt current count */ | 30 | #define AD_DMA_ADCICC 0x88 /* ADC interrupt current count */ |
| 31 | #define AD_DMAADCIBC 0x8c /* ADC interrupt base count */ | 31 | #define AD_DMA_ADCIBC 0x8c /* ADC interrupt base count */ |
| 32 | #define AD_DMASYNICC 0x90 /* SYN interrupt current count */ | 32 | #define AD_DMA_SYNICC 0x90 /* SYN interrupt current count */ |
| 33 | #define AD_DMASYNIBC 0x94 /* SYN interrupt base count */ | 33 | #define AD_DMA_SYNIBC 0x94 /* SYN interrupt base count */ |
| 34 | #define AD_DMAWAVICC 0x98 /* WAV interrupt current count */ | 34 | #define AD_DMA_WAVICC 0x98 /* WAV interrupt current count */ |
| 35 | #define AD_DMAWAVIBC 0x9c /* WAV interrupt base count */ | 35 | #define AD_DMA_WAVIBC 0x9c /* WAV interrupt base count */ |
| 36 | #define AD_DMARESCTRL 0xa0 /* RES PCI control/status */ | 36 | #define AD_DMA_RESCTRL 0xa0 /* RES PCI control/status */ |
| 37 | #define AD_DMAADCCTRL 0xa8 /* ADC PCI control/status */ | 37 | #define AD_DMA_ADCCTRL 0xa8 /* ADC PCI control/status */ |
| 38 | #define AD_DMASYNCTRL 0xb0 /* SYN PCI control/status */ | 38 | #define AD_DMA_SYNCTRL 0xb0 /* SYN PCI control/status */ |
| 39 | #define AD_DMAWAVCTRL 0xb8 /* WAV PCI control/status */ | 39 | #define AD_DMA_WAVCTRL 0xb8 /* WAV PCI control/status */ |
| 40 | #define AD_DMADISR 0xc0 /* PCI DMA intr status */ | 40 | #define AD_DMA_DISR 0xc0 /* PCI DMA intr status */ |
| 41 | #define AD_DMACHSS 0xc4 /* PCI DMA channel stop status */ | 41 | #define AD_DMA_CHSS 0xc4 /* PCI DMA channel stop status */ |
| 42 | 42 | ||
| 43 | #define AD_GPIOIPC 0xc8 /* IO port ctrl */ | 43 | #define AD_GPIO_IPC 0xc8 /* IO port ctrl */ |
| 44 | #define AD_GPIOOP 0xca /* IO output status */ | 44 | #define AD_GPIO_OP 0xca /* IO output status */ |
| 45 | #define AD_GPIOIP 0xcc /* IO input status */ | 45 | #define AD_GPIO_IP 0xcc /* IO input status */ |
| 46 | 46 | ||
| 47 | /* AC97 registers, 0x100 - 0x17f; see ac97.h */ | 47 | /* AC97 registers, 0x100 - 0x17f; see ac97.h */ |
| 48 | #define AD_ACIC 0x180 /* AC Link interface ctrl */ | 48 | #define AD_AC97_BASE 0x100 /* ac97 base register */ |
| 49 | #define AD_AC97_ACIC 0x180 /* AC Link interface ctrl */ | ||
| 49 | 50 | ||
| 50 | /* OPL3; BAR1 */ | 51 | /* OPL3; BAR1 */ |
| 51 | #define AD_OPLM0AS 0x00 /* Music0 address/status */ | 52 | #define AD_OPL_M0AS 0x00 /* Music0 address/status */ |
| 52 | #define AD_OPLM0DATA 0x01 /* Music0 data */ | 53 | #define AD_OPL_M0DATA 0x01 /* Music0 data */ |
| 53 | #define AD_OPLM1A 0x02 /* Music1 address */ | 54 | #define AD_OPL_M1A 0x02 /* Music1 address */ |
| 54 | #define AD_OPLM1DATA 0x03 /* Music1 data */ | 55 | #define AD_OPL_M1DATA 0x03 /* Music1 data */ |
| 55 | /* 0x04-0x0f reserved */ | 56 | /* 0x04-0x0f reserved */ |
| 56 | 57 | ||
| 57 | /* MIDI; BAR2 */ | 58 | /* MIDI; BAR2 */ |
| @@ -59,9 +60,9 @@ | |||
| 59 | #define AD_MISC 0x01 /* MIDI status/cmd */ | 60 | #define AD_MISC 0x01 /* MIDI status/cmd */ |
| 60 | /* 0x02-0xff reserved */ | 61 | /* 0x02-0xff reserved */ |
| 61 | 62 | ||
| 62 | #define AD_DSIOMEMSIZE 512 | 63 | #define AD_DS_IOMEMSIZE 512 |
| 63 | #define AD_OPLMEMSIZE 16 | 64 | #define AD_OPL_MEMSIZE 16 |
| 64 | #define AD_MIDIMEMSIZE 16 | 65 | #define AD_MIDI_MEMSIZE 16 |
| 65 | 66 | ||
| 66 | #define AD_WAV_STATE 0 | 67 | #define AD_WAV_STATE 0 |
| 67 | #define AD_ADC_STATE 1 | 68 | #define AD_ADC_STATE 1 |