litmus-rt.git - The LITMUS^RT kernel.

diff options

Diffstat (limited to 'net/unix/af_unix.c')

-rw-r--r--

1 files changed, 3 insertions, 25 deletions


diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index c478fc8db776..c420eba4876b 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c
@@ -770,33 +770,12 @@ static int unix_bind(struct socket sock, struct sockaddr uaddr, int addr_len)
770	err = path_lookup(sunaddr->sun_path, LOOKUP_PARENT, &nd);	770	err = path_lookup(sunaddr->sun_path, LOOKUP_PARENT, &nd);
771	if (err)	771	if (err)
772	goto out_mknod_parent;	772	goto out_mknod_parent;
773	/*	773
774	* Yucky last component or no last component at all?	774	dentry = lookup_create(&nd, 0);
775	* (foo/., foo/.., /////)
776	*/
777	err = -EEXIST;
778	if (nd.last_type != LAST_NORM)
779	goto out_mknod;
780	/*
781	* Lock the directory.
782	*/
783	down(&nd.dentry->d_inode->i_sem);
784	/*
785	* Do the final lookup.
786	*/
787	dentry = lookup_hash(&nd.last, nd.dentry);
788	err = PTR_ERR(dentry);	775	err = PTR_ERR(dentry);
789	if (IS_ERR(dentry))	776	if (IS_ERR(dentry))
790	goto out_mknod_unlock;	777	goto out_mknod_unlock;
791	err = -ENOENT;	778
792	/*
793	* Special case - lookup gave negative, but... we had foo/bar/
794	* From the vfs_mknod() POV we just have a negative dentry -
795	* all is fine. Let's be bastards - you had / on the end, you've
796	* been asking for (non-existent) directory. -ENOENT for you.
797	*/
798	if (nd.last.name[nd.last.len] && !dentry->d_inode)
799	goto out_mknod_dput;
800	/*	779	/*
801	* All right, let's create it.	780	* All right, let's create it.
802	*/	781	*/
@@ -845,7 +824,6 @@ out_mknod_dput:
845	dput(dentry);	824	dput(dentry);
846	out_mknod_unlock:	825	out_mknod_unlock:
847	up(&nd.dentry->d_inode->i_sem);	826	up(&nd.dentry->d_inode->i_sem);
848	out_mknod:
849	path_release(&nd);	827	path_release(&nd);
850	out_mknod_parent:	828	out_mknod_parent:
851	if (err==-EEXIST)	829	if (err==-EEXIST)

/* * ARMv5 [xscale] Performance counter handling code. * * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com> * * Based on the previous xscale OProfile code. * * There are two variants of the xscale PMU that we support: * - xscale1pmu: 2 event counters and a cycle counter * - xscale2pmu: 4 event counters and a cycle counter * The two variants share event definitions, but have different * PMU structures. */ #ifdef CONFIG_CPU_XSCALE enum xscale_perf_types { XSCALE_PERFCTR_ICACHE_MISS = 0x00, XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01, XSCALE_PERFCTR_DATA_STALL = 0x02, XSCALE_PERFCTR_ITLB_MISS = 0x03, XSCALE_PERFCTR_DTLB_MISS = 0x04, XSCALE_PERFCTR_BRANCH = 0x05, XSCALE_PERFCTR_BRANCH_MISS = 0x06, XSCALE_PERFCTR_INSTRUCTION = 0x07, XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08, XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09, XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A, XSCALE_PERFCTR_DCACHE_MISS = 0x0B, XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C, XSCALE_PERFCTR_PC_CHANGED = 0x0D, XSCALE_PERFCTR_BCU_REQUEST = 0x10, XSCALE_PERFCTR_BCU_FULL = 0x11, XSCALE_PERFCTR_BCU_DRAIN = 0x12, XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14, XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15, XSCALE_PERFCTR_RMW = 0x16, /* XSCALE_PERFCTR_CCNT is not hardware defined */ XSCALE_PERFCTR_CCNT = 0xFE, XSCALE_PERFCTR_UNUSED = 0xFF, }; enum xscale_counters { XSCALE_CYCLE_COUNTER = 1, XSCALE_COUNTER0, XSCALE_COUNTER1, XSCALE_COUNTER2, XSCALE_COUNTER3, }; static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, }; static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [C(L1D)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(L1I)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(LL)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(DTLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(ITLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(BPU)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, [C(NODE)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, }; #define XSCALE_PMU_ENABLE 0x001 #define XSCALE_PMN_RESET 0x002 #define XSCALE_CCNT_RESET 0x004 #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET) #define XSCALE_PMU_CNT64 0x008 #define XSCALE1_OVERFLOWED_MASK 0x700 #define XSCALE1_CCOUNT_OVERFLOW 0x400 #define XSCALE1_COUNT0_OVERFLOW 0x100 #define XSCALE1_COUNT1_OVERFLOW 0x200 #define XSCALE1_CCOUNT_INT_EN 0x040 #define XSCALE1_COUNT0_INT_EN 0x010 #define XSCALE1_COUNT1_INT_EN 0x020 #define XSCALE1_COUNT0_EVT_SHFT 12 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT) #define XSCALE1_COUNT1_EVT_SHFT 20 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT) static inline u32 xscale1pmu_read_pmnc(void) { u32 val; asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); return val; } static inline void xscale1pmu_write_pmnc(u32 val) { /* upper 4bits and 7, 11 are write-as-0 */ val &= 0xffff77f; asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); } static inline int xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, enum xscale_counters counter) { int ret = 0; switch (counter) { case XSCALE_CYCLE_COUNTER: ret = pmnc & XSCALE1_CCOUNT_OVERFLOW; break; case XSCALE_COUNTER0: ret = pmnc & XSCALE1_COUNT0_OVERFLOW; break; case XSCALE_COUNTER1: ret = pmnc & XSCALE1_COUNT1_OVERFLOW; break; default: WARN_ONCE(1, "invalid counter number (%d)\n", counter); } return ret; } static irqreturn_t xscale1pmu_handle_irq(int irq_num, void *dev) { unsigned long pmnc; struct perf_sample_data data; struct cpu_hw_events *cpuc; struct pt_regs *regs; int idx; /* * NOTE: there's an A stepping erratum that states if an overflow * bit already exists and another occurs, the previous * Overflow bit gets cleared. There's no workaround. * Fixed in B stepping or later. */ pmnc = xscale1pmu_read_pmnc(); /* * Write the value back to clear the overflow flags. Overflow * flags remain in pmnc for use below. We also disable the PMU * while we process the interrupt. */ xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); if (!(pmnc & XSCALE1_OVERFLOWED_MASK)) return IRQ_NONE; regs = get_irq_regs(); perf_sample_data_init(&data, 0); cpuc = &__get_cpu_var(cpu_hw_events); for (idx = 0; idx <= armpmu->num_events; ++idx) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc; if (!test_bit(idx, cpuc->active_mask)) continue; if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) continue; hwc = &event->hw; armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; if (perf_event_overflow(event, &data, regs)) armpmu->disable(hwc, idx); } irq_work_run(); /* * Re-enable the PMU. */ pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE; xscale1pmu_write_pmnc(pmnc); return IRQ_HANDLED; } static void xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) { unsigned long val, mask, evt, flags; switch (idx) { case XSCALE_CYCLE_COUNTER: mask = 0; evt = XSCALE1_CCOUNT_INT_EN; break; case XSCALE_COUNTER0: mask = XSCALE1_COUNT0_EVT_MASK; evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | XSCALE1_COUNT0_INT_EN; break; case XSCALE_COUNTER1: mask = XSCALE1_COUNT1_EVT_MASK; evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | XSCALE1_COUNT1_INT_EN; break; default: WARN_ONCE(1, "invalid counter number (%d)\n", idx); return; } raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val &= ~mask; val |= evt; xscale1pmu_write_pmnc(val); raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) { unsigned long val, mask, evt, flags; switch (idx) { case XSCALE_CYCLE_COUNTER: mask = XSCALE1_CCOUNT_INT_EN; evt = 0; break; case XSCALE_COUNTER0: mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT; break; case XSCALE_COUNTER1: mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT; break; default: WARN_ONCE(1, "invalid counter number (%d)\n", idx); return; } raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val &= ~mask; val |= evt; xscale1pmu_write_pmnc(val); raw_spin_unlock_irqrestore(&pmu_lock, flags); } static int xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *event) { if (XSCALE_PERFCTR_CCNT == event->config_base) { if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) return -EAGAIN; return XSCALE_CYCLE_COUNTER; } else { if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) return XSCALE_COUNTER1; if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) return XSCALE_COUNTER0; return -EAGAIN; } } static void xscale1pmu_start(void) { unsigned long flags, val; raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc();


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