litmus-rt.git - The LITMUS^RT kernel.

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The LITMUS^RT kernel.

Bjoern Brandenburg

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/*
 * Pinctrl data for the NVIDIA Tegra186 pinmux
 *
 * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/tegra-pmc.h>

#include "pinctrl-tegra.h"

/*
 * Most pins affected by the pinmux can also be GPIOs. Define these first.
 * These must match how the GPIO driver names/numbers its pins.
 */
#define _GPIO(offset)				(offset)

#define TEGRA_PIN_PEX_L0_RST_N_PA0                    _GPIO(0)
#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1                    _GPIO(1)
#define TEGRA_PIN_PEX_WAKE_N_PA2                    _GPIO(2)
#define TEGRA_PIN_PEX_L1_RST_N_PA3                    _GPIO(3)
#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4                    _GPIO(4)
#define TEGRA_PIN_PEX_L2_RST_N_PA5                    _GPIO(5)
#define TEGRA_PIN_PEX_L2_CLKREQ_N_PA6                    _GPIO(6)
#define TEGRA_PIN_UART4_TX_PB0                    _GPIO(8)
#define TEGRA_PIN_UART4_RX_PB1                    _GPIO(9)
#define TEGRA_PIN_UART4_RTS_PB2                    _GPIO(10)
#define TEGRA_PIN_UART4_CTS_PB3                    _GPIO(11)
#define TEGRA_PIN_GPIO_WAN1_PB4                    _GPIO(12)
#define TEGRA_PIN_GPIO_WAN2_PB5                    _GPIO(13)
#define TEGRA_PIN_GPIO_WAN3_PB6                    _GPIO(14)
#define TEGRA_PIN_GPIO_WAN4_PC0                    _GPIO(16)
#define TEGRA_PIN_DAP2_SCLK_PC1                    _GPIO(17)
#define TEGRA_PIN_DAP2_DOUT_PC2                    _GPIO(18)
#define TEGRA_PIN_DAP2_DIN_PC3                    _GPIO(19)
#define TEGRA_PIN_DAP2_FS_PC4                    _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SCL_PC5                    _GPIO(21)
#define TEGRA_PIN_GEN1_I2C_SDA_PC6                    _GPIO(22)
#define TEGRA_PIN_SDMMC1_CLK_PD0                    _GPIO(24)
#define TEGRA_PIN_SDMMC1_CMD_PD1                    _GPIO(25)
#define TEGRA_PIN_SDMMC1_DAT0_PD2                    _GPIO(26)
#define TEGRA_PIN_SDMMC1_DAT1_PD3                    _GPIO(27)
#define TEGRA_PIN_SDMMC1_DAT2_PD4                    _GPIO(28)
#define TEGRA_PIN_SDMMC1_DAT3_PD5                    _GPIO(29)
#define TEGRA_PIN_EQOS_TXC_PE0                    _GPIO(32)
#define TEGRA_PIN_EQOS_TD0_PE1                    _GPIO(33)
#define TEGRA_PIN_EQOS_TD1_PE2                    _GPIO(34)
#define TEGRA_PIN_EQOS_TD2_PE3                    _GPIO(35)
#define TEGRA_PIN_EQOS_TD3_PE4                    _GPIO(36)
#define TEGRA_PIN_EQOS_TX_CTL_PE5                    _GPIO(37)
#define TEGRA_PIN_EQOS_RD0_PE6                    _GPIO(38)
#define TEGRA_PIN_EQOS_RD1_PE7                    _GPIO(39)
#define TEGRA_PIN_EQOS_RD2_PF0                    _GPIO(40)
#define TEGRA_PIN_EQOS_RD3_PF1                    _GPIO(41)
#define TEGRA_PIN_EQOS_RX_CTL_PF2                    _GPIO(42)
#define TEGRA_PIN_EQOS_RXC_PF3                    _GPIO(43)
#define TEGRA_PIN_EQOS_MDIO_PF4                    _GPIO(44)
#define TEGRA_PIN_EQOS_MDC_PF5                    _GPIO(45)
#define TEGRA_PIN_SDMMC3_CLK_PG0                    _GPIO(48)
#define TEGRA_PIN_SDMMC3_CMD_PG1                    _GPIO(49)
#define TEGRA_PIN_SDMMC3_DAT0_PG2                    _GPIO(50)
#define TEGRA_PIN_SDMMC3_DAT1_PG3                    _GPIO(51)
#define TEGRA_PIN_SDMMC3_DAT2_PG4                    _GPIO(52)
#define TEGRA_PIN_SDMMC3_DAT3_PG5                    _GPIO(53)
#define TEGRA_PIN_GPIO_WAN5_PH0                    _GPIO(56)
#define TEGRA_PIN_GPIO_WAN6_PH1                    _GPIO(57)
#define TEGRA_PIN_GPIO_WAN7_PH2                    _GPIO(58)
#define TEGRA_PIN_GPIO_WAN8_PH3                    _GPIO(59)
#define TEGRA_PIN_BCPU_PWR_REQ_PH4                    _GPIO(60)
#define TEGRA_PIN_MCPU_PWR_REQ_PH5                    _GPIO(61)
#define TEGRA_PIN_GPU_PWR_REQ_PH6                    _GPIO(62)
#define TEGRA_PIN_GPIO_PQ0_PI0                    _GPIO(64)
#define TEGRA_PIN_GPIO_PQ1_PI1                    _GPIO(65)
#define TEGRA_PIN_GPIO_PQ2_PI2                    _GPIO(66)
#define TEGRA_PIN_GPIO_PQ3_PI3                    _GPIO(67)
#define TEGRA_PIN_GPIO_PQ4_PI4                    _GPIO(68)
#define TEGRA_PIN_GPIO_PQ5_PI5                    _GPIO(69)
#define TEGRA_PIN_GPIO_PQ6_PI6                    _GPIO(70)
#define TEGRA_PIN_GPIO_PQ7_PI7                    _GPIO(71)
#define TEGRA_PIN_DAP1_SCLK_PJ0                    _GPIO(72)
#define TEGRA_PIN_DAP1_DOUT_PJ1                    _GPIO(73)
#define TEGRA_PIN_DAP1_DIN_PJ2                    _GPIO(74)
#define TEGRA_PIN_DAP1_FS_PJ3                    _GPIO(75)
#define TEGRA_PIN_AUD_MCLK_PJ4                    _GPIO(76)
#define TEGRA_PIN_GPIO_AUD0_PJ5                    _GPIO(77)
#define TEGRA_PIN_GPIO_AUD1_PJ6                    _GPIO(78)
#define TEGRA_PIN_GPIO_AUD2_PJ7                    _GPIO(79)
#define TEGRA_PIN_GPIO_AUD3_PK0                    _GPIO(80)
#define TEGRA_PIN_GEN7_I2C_SCL_PL0                    _GPIO(88)
#define TEGRA_PIN_GEN7_I2C_SDA_PL1                    _GPIO(89)
#define TEGRA_PIN_GEN9_I2C_SCL_PL2                    _GPIO(90)
#define TEGRA_PIN_GEN9_I2C_SDA_PL3                    _GPIO(91)
#define TEGRA_PIN_USB_VBUS_EN0_PL4                    _GPIO(92)
#define TEGRA_PIN_USB_VBUS_EN1_PL5                    _GPIO(93)
#define TEGRA_PIN_GP_PWM6_PL6                    _GPIO(94)
#define TEGRA_PIN_GP_PWM7_PL7                    _GPIO(95)
#define TEGRA_PIN_DMIC1_DAT_PM0                    _GPIO(96)
#define TEGRA_PIN_DMIC1_CLK_PM1                    _GPIO(97)
#define TEGRA_PIN_DMIC2_DAT_PM2                    _GPIO(98)
#define TEGRA_PIN_DMIC2_CLK_PM3                    _GPIO(99)
#define TEGRA_PIN_DMIC4_DAT_PM4                    _GPIO(100)
#define TEGRA_PIN_DMIC4_CLK_PM5                    _GPIO(101)
#define TEGRA_PIN_GPIO_CAM1_PN0                    _GPIO(104)
#define TEGRA_PIN_GPIO_CAM2_PN1                    _GPIO(105)
#define TEGRA_PIN_GPIO_CAM3_PN2                    _GPIO(106)
#define TEGRA_PIN_GPIO_CAM4_PN3                    _GPIO(107)
#define TEGRA_PIN_GPIO_CAM5_PN4                    _GPIO(108)
#define TEGRA_PIN_GPIO_CAM6_PN5                    _GPIO(109)
#define TEGRA_PIN_GPIO_CAM7_PN6                    _GPIO(110)
#define TEGRA_PIN_EXTPERIPH1_CLK_PO0                    _GPIO(112)
#define TEGRA_PIN_EXTPERIPH2_CLK_PO1                    _GPIO(113)
#define TEGRA_PIN_CAM_I2C_SCL_PO2                    _GPIO(114)
#define TEGRA_PIN_CAM_I2C_SDA_PO3                    _GPIO(115)
#define TEGRA_PIN_DP_AUX_CH0_HPD_PP0                    _GPIO(120)
#define TEGRA_PIN_DP_AUX_CH1_HPD_PP1                    _GPIO(121)
#define TEGRA_PIN_HDMI_CEC_PP2                    _GPIO(122)
#define TEGRA_PIN_GPIO_EDP0_PP3                    _GPIO(123)
#define TEGRA_PIN_GPIO_EDP1_PP4                    _GPIO(124)
#define TEGRA_PIN_GPIO_EDP2_PP5                    _GPIO(125)
#define TEGRA_PIN_GPIO_EDP3_PP6                    _GPIO(126)
#define TEGRA_PIN_DIRECTDC1_CLK_PQ0                    _GPIO(128)
#define TEGRA_PIN_DIRECTDC1_IN_PQ1                    _GPIO(129)
#define TEGRA_PIN_DIRECTDC1_OUT0_PQ2                    _GPIO(130)
#define TEGRA_PIN_DIRECTDC1_OUT1_PQ3                    _GPIO(131)
#define TEGRA_PIN_DIRECTDC1_OUT2_PQ4                    _GPIO(132)
#define TEGRA_PIN_DIRECTDC1_OUT3_PQ5                    _GPIO(133)
#define TEGRA_PIN_QSPI_SCK_PR0                    _GPIO(136)
#define TEGRA_PIN_QSPI_IO0_PR1                    _GPIO(137)
#define TEGRA_PIN_QSPI_IO1_PR2                    _GPIO(138)
#define TEGRA_PIN_QSPI_IO2_PR3                    _GPIO(139)
#define TEGRA_PIN_QSPI_IO3_PR4                    _GPIO(140)
#define TEGRA_PIN_QSPI_CS_N_PR5                    _GPIO(141)
#define TEGRA_PIN_PWR_I2C_SCL_PS0                    _GPIO(144)
#define TEGRA_PIN_PWR_I2C_SDA_PS1                    _GPIO(145)
#define TEGRA_PIN_BATT_OC_PS2                    _GPIO(146)
#define TEGRA_PIN_SAFE_STATE_PS3                    _GPIO(147)
#define TEGRA_PIN_VCOMP_ALERT_PS4                    _GPIO(148)
#define TEGRA_PIN_UART1_TX_PT0                    _GPIO(152)
#define TEGRA_PIN_UART1_RX_PT1                    _GPIO(153)
#define TEGRA_PIN_UART1_RTS_PT2                    _GPIO(154)
#define TEGRA_PIN_UART1_CTS_PT3                    _GPIO(155)
#define TEGRA_PIN_GPIO_DIS0_PU0                    _GPIO(160)
#define TEGRA_PIN_GPIO_DIS1_PU1                    _GPIO(161)
#define TEGRA_PIN_GPIO_DIS2_PU2                    _GPIO(162)
#define TEGRA_PIN_GPIO_DIS3_PU3                    _GPIO(163)
#define TEGRA_PIN_GPIO_DIS4_PU4                    _GPIO(164)
#define TEGRA_PIN_GPIO_DIS5_PU5                    _GPIO(165)
#define TEGRA_PIN_GPIO_SEN0_PV0                    _GPIO(168)
#define TEGRA_PIN_GPIO_SEN1_PV1                    _GPIO(169)
#define TEGRA_PIN_GPIO_SEN2_PV2                    _GPIO(170)
#define TEGRA_PIN_GPIO_SEN3_PV3                    _GPIO(171)
#define TEGRA_PIN_GPIO_SEN4_PV4                    _GPIO(172)
#define TEGRA_PIN_GPIO_SEN5_PV5                    _GPIO(173)
#define TEGRA_PIN_GPIO_SEN6_PV6                    _GPIO(174)
#define TEGRA_PIN_GPIO_SEN7_PV7                    _GPIO(175)
#define TEGRA_PIN_GEN8_I2C_SCL_PW0                    _GPIO(176)
#define TEGRA_PIN_GEN8_I2C_SDA_PW1                    _GPIO(177)
#define TEGRA_PIN_UART3_TX_PW2                    _GPIO(178)
#define TEGRA_PIN_UART3_RX_PW3                    _GPIO(179)
#define TEGRA_PIN_UART3_RTS_PW4                    _GPIO(180)
#define TEGRA_PIN_UART3_CTS_PW5                    _GPIO(181)
#define TEGRA_PIN_UART7_TX_PW6                    _GPIO(182)
#define TEGRA_PIN_UART7_RX_PW7                    _GPIO(183)
#define TEGRA_PIN_UART2_TX_PX0                    _GPIO(184)
#define TEGRA_PIN_UART2_RX_PX1                    _GPIO(185)
#define TEGRA_PIN_UART2_RTS_PX2                    _GPIO(186)
#define TEGRA_PIN_UART2_CTS_PX3                    _GPIO(187)
#define TEGRA_PIN_UART5_TX_PX4                    _GPIO(188)
#define TEGRA_PIN_UART5_RX_PX5                    _GPIO(189)
#define TEGRA_PIN_UART5_RTS_PX6                    _GPIO(190)
#define TEGRA_PIN_UART5_CTS_PX7                    _GPIO(191)
#define TEGRA_PIN_GPIO_MDM1_PY0                    _GPIO(192)
#define TEGRA_PIN_GPIO_MDM2_PY1                    _GPIO(193)
#define TEGRA_PIN_GPIO_MDM3_PY2                    _GPIO(194)
#define TEGRA_PIN_GPIO_MDM4_PY3                    _GPIO(195)
#define TEGRA_PIN_GPIO_MDM5_PY4                    _GPIO(196)
#define TEGRA_PIN_GPIO_MDM6_PY5                    _GPIO(197)
#define TEGRA_PIN_GPIO_MDM7_PY6                    _GPIO(198)
#define TEGRA_PIN_CAN1_DOUT_PZ0                    _GPIO(200)
#define TEGRA_PIN_CAN1_DIN_PZ1                    _GPIO(201)
#define TEGRA_PIN_CAN0_DOUT_PZ2                    _GPIO(202)
#define TEGRA_PIN_CAN0_DIN_PZ3                    _GPIO(203)
#define TEGRA_PIN_CAN_GPIO0_PAA0                    _GPIO(208)
#define TEGRA_PIN_CAN_GPIO1_PAA1                    _GPIO(209)
#define TEGRA_PIN_CAN_GPIO2_PAA2                    _GPIO(210)
#define TEGRA_PIN_CAN_GPIO3_PAA3                    _GPIO(211)
#define TEGRA_PIN_CAN_GPIO4_PAA4                    _GPIO(212)
#define TEGRA_PIN_CAN_GPIO5_PAA5                    _GPIO(213)
#define TEGRA_PIN_CAN_GPIO6_PAA6                    _GPIO(214)
#define TEGRA_PIN_CAN_GPIO7_PAA7                    _GPIO(215)
#define TEGRA_PIN_UFS0_REF_CLK_PBB0                    _GPIO(216)
#define TEGRA_PIN_UFS0_RST_PBB1                    _GPIO(217)
#define TEGRA_PIN_DAP4_SCLK_PCC0                    _GPIO(224)
#define TEGRA_PIN_DAP4_DOUT_PCC1                    _GPIO(225)
#define TEGRA_PIN_DAP4_DIN_PCC2                    _GPIO(226)
#define TEGRA_PIN_DAP4_FS_PCC3                    _GPIO(227)
#define TEGRA_PIN_GPIO_SEN8_PEE0                    _GPIO(240)
#define TEGRA_PIN_GPIO_SEN9_PEE1                    _GPIO(241)
#define TEGRA_PIN_TOUCH_CLK_PEE2                    _GPIO(242)
#define TEGRA_PIN_POWER_ON_PFF0                    _GPIO(248)
#define TEGRA_PIN_GPIO_SW1_PFF1                    _GPIO(249)
#define TEGRA_PIN_GPIO_SW2_PFF2                    _GPIO(250)
#define TEGRA_PIN_GPIO_SW3_PFF3                    _GPIO(251)
#define TEGRA_PIN_GPIO_SW4_PFF4                    _GPIO(252)

/* All non-GPIO pins follow */
#define NUM_GPIOS	(TEGRA_PIN_GPIO_SW4_PFF4 + 1)
#define _PIN(offset)	(NUM_GPIOS + (offset))

/* Non-GPIO pins */
#define TEGRA_PIN_DIRECTDC_COMP 		_PIN(0)
#define TEGRA_PIN_SDMMC1_COMP		_PIN(1)
#define TEGRA_PIN_EQOS_COMP			_PIN(2)
#define TEGRA_PIN_SDMMC3_COMP		_PIN(3)
#define TEGRA_PIN_QSPI_COMP			_PIN(4)
#define TEGRA_PIN_SHUTDOWN			_PIN(5)
#define TEGRA_PIN_PMU_INT				_PIN(6)
#define TEGRA_PIN_SOC_PWR_REQ			_PIN(7)
#define TEGRA_PIN_CLK_32K_IN			_PIN(8)

#define DRV_BANK	0
#define MUX_BANK	1

static const struct pinctrl_pin_desc  tegra186_pins[] = {
	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N_PA0"),
	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N_PA1"),
	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N_PA2"),
	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N_PA3"),
	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N_PA4"),
	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PA5, "PEX_L2_RST_N_PA5"),
	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PA6, "PEX_L2_CLKREQ_N_PA6"),
	PINCTRL_PIN(TEGRA_PIN_UART4_TX_PB0, "UART4_TX_PB0"),
	PINCTRL_PIN(TEGRA_PIN_UART4_RX_PB1, "UART4_RX_PB1"),
	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PB2, "UART4_RTS_PB2"),
	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PB3, "UART4_CTS_PB3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN1_PB4, "GPIO_WAN1_PB4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN2_PB5, "GPIO_WAN2_PB5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN3_PB6, "GPIO_WAN3_PB6"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN4_PC0, "GPIO_WAN4_PC0"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PC1, "DAP2_SCLK_PC1"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PC2, "DAP2_DOUT_PC2"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PC3, "DAP2_DIN_PC3"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PC4, "DAP2_FS_PC4"),
	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC5, "GEN1_I2C_SCL_PC5"),
	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC6, "GEN1_I2C_SDA_PC6"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PD0, "SDMMC1_CLK_PD0"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PD1, "SDMMC1_CMD_PD1"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PD2, "SDMMC1_DAT0_PD2"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PD3, "SDMMC1_DAT1_PD3"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PD4, "SDMMC1_DAT2_PD4"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PD5, "SDMMC1_DAT3_PD5"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_MDIO_PF4, "EQOS_MDIO_PF4"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_MDC_PF5, "EQOS_MDC_PF5"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PG0, "SDMMC3_CLK_PG0"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PG1, "SDMMC3_CMD_PG1"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PG2, "SDMMC3_DAT0_PG2"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PG3, "SDMMC3_DAT1_PG3"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PG4, "SDMMC3_DAT2_PG4"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PG5, "SDMMC3_DAT3_PG5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN5_PH0, "GPIO_WAN5_PH0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN6_PH1, "GPIO_WAN6_PH1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN7_PH2, "GPIO_WAN7_PH2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_WAN8_PH3, "GPIO_WAN8_PH3"),
	PINCTRL_PIN(TEGRA_PIN_BCPU_PWR_REQ_PH4, "BCPU_PWR_REQ_PH4"),
	PINCTRL_PIN(TEGRA_PIN_MCPU_PWR_REQ_PH5, "MCPU_PWR_REQ_PH5"),
	PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH6, "GPU_PWR_REQ_PH6"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ0_PI0, "GPIO_PQ0_PI0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ1_PI1, "GPIO_PQ1_PI1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ2_PI2, "GPIO_PQ2_PI2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ3_PI3, "GPIO_PQ3_PI3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ4_PI4, "GPIO_PQ4_PI4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ5_PI5, "GPIO_PQ5_PI5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ6_PI6, "GPIO_PQ6_PI6"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_PQ7_PI7, "GPIO_PQ7_PI7"),
	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PJ0, "DAP1_SCLK_PJ0"),
	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PJ1, "DAP1_DOUT_PJ1"),
	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PJ2, "DAP1_DIN_PJ2"),
	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PJ3, "DAP1_FS_PJ3"),
	PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PJ4, "AUD_MCLK_PJ4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_AUD0_PJ5, "GPIO_AUD0_PJ5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_AUD1_PJ6, "GPIO_AUD1_PJ6"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_AUD2_PJ7, "GPIO_AUD2_PJ7"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_AUD3_PK0, "GPIO_AUD3_PK0"),
	PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PL0, "GEN7_I2C_SCL_PL0"),
	PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PL1, "GEN7_I2C_SDA_PL1"),
	PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PL2, "GEN9_I2C_SCL_PL2"),
	PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PL3, "GEN9_I2C_SDA_PL3"),
	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PL4, "USB_VBUS_EN0_PL4"),
	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PL5, "USB_VBUS_EN1_PL5"),
	PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PL6, "GP_PWM6_PL6"),
	PINCTRL_PIN(TEGRA_PIN_GP_PWM7_PL7, "GP_PWM7_PL7"),
	PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PM0, "DMIC1_DAT_PM0"),
	PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PM1, "DMIC1_CLK_PM1"),
	PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PM2, "DMIC2_DAT_PM2"),
	PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PM3, "DMIC2_CLK_PM3"),
	PINCTRL_PIN(TEGRA_PIN_DMIC4_DAT_PM4, "DMIC4_DAT_PM4"),
	PINCTRL_PIN(TEGRA_PIN_DMIC4_CLK_PM5, "DMIC4_CLK_PM5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM1_PN0, "GPIO_CAM1_PN0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM2_PN1, "GPIO_CAM2_PN1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM3_PN2, "GPIO_CAM3_PN2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM4_PN3, "GPIO_CAM4_PN3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM5_PN4, "GPIO_CAM5_PN4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM6_PN5, "GPIO_CAM6_PN5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_CAM7_PN6, "GPIO_CAM7_PN6"),
	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PO0, "EXTPERIPH1_CLK_PO0"),
	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PO1, "EXTPERIPH2_CLK_PO1"),
	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PO2, "CAM_I2C_SCL_PO2"),
	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PO3, "CAM_I2C_SDA_PO3"),
	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PP0, "DP_AUX_CH0_HPD_PP0"),
	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PP1, "DP_AUX_CH1_HPD_PP1"),
	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PP2, "HDMI_CEC_PP2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_EDP0_PP3, "GPIO_EDP0_PP3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_EDP1_PP4, "GPIO_EDP1_PP4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_EDP2_PP5, "GPIO_EDP2_PP5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_EDP3_PP6, "GPIO_EDP3_PP6"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PQ0, "DIRECTDC1_CLK_PQ0"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PQ1, "DIRECTDC1_IN_PQ1"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PQ2, "DIRECTDC1_OUT0_PQ2"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PQ3, "DIRECTDC1_OUT1_PQ3"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PQ4, "DIRECTDC1_OUT2_PQ4"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PQ5, "DIRECTDC1_OUT3_PQ5"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PR0, "QSPI_SCK_PR0"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PR1, "QSPI_IO0_PR1"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PR2, "QSPI_IO1_PR2"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PR3, "QSPI_IO2_PR3"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PR4, "QSPI_IO3_PR4"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PR5, "QSPI_CS_N_PR5"),
	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PS0, "PWR_I2C_SCL_PS0"),
	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PS1, "PWR_I2C_SDA_PS1"),
	PINCTRL_PIN(TEGRA_PIN_BATT_OC_PS2, "BATT_OC_PS2"),
	PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PS3, "SAFE_STATE_PS3"),
	PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PS4, "VCOMP_ALERT_PS4"),
	PINCTRL_PIN(TEGRA_PIN_UART1_TX_PT0, "UART1_TX_PT0"),
	PINCTRL_PIN(TEGRA_PIN_UART1_RX_PT1, "UART1_RX_PT1"),
	PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PT2, "UART1_RTS_PT2"),
	PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PT3, "UART1_CTS_PT3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS0_PU0, "GPIO_DIS0_PU0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS1_PU1, "GPIO_DIS1_PU1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS2_PU2, "GPIO_DIS2_PU2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS3_PU3, "GPIO_DIS3_PU3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS4_PU4, "GPIO_DIS4_PU4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_DIS5_PU5, "GPIO_DIS5_PU5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN0_PV0, "GPIO_SEN0_PV0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN1_PV1, "GPIO_SEN1_PV1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN2_PV2, "GPIO_SEN2_PV2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN3_PV3, "GPIO_SEN3_PV3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN4_PV4, "GPIO_SEN4_PV4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN5_PV5, "GPIO_SEN5_PV5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN6_PV6, "GPIO_SEN6_PV6"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN7_PV7, "GPIO_SEN7_PV7"),
	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PW0, "GEN8_I2C_SCL_PW0"),
	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PW1, "GEN8_I2C_SDA_PW1"),
	PINCTRL_PIN(TEGRA_PIN_UART3_TX_PW2, "UART3_TX_PW2"),
	PINCTRL_PIN(TEGRA_PIN_UART3_RX_PW3, "UART3_RX_PW3"),
	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PW4, "UART3_RTS_PW4"),
	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PW5, "UART3_CTS_PW5"),
	PINCTRL_PIN(TEGRA_PIN_UART7_TX_PW6, "UART7_TX_PW6"),
	PINCTRL_PIN(TEGRA_PIN_UART7_RX_PW7, "UART7_RX_PW7"),
	PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX0, "UART2_TX_PX0"),
	PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX1, "UART2_RX_PX1"),
	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX2, "UART2_RTS_PX2"),
	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX3, "UART2_CTS_PX3"),
	PINCTRL_PIN(TEGRA_PIN_UART5_TX_PX4, "UART5_TX_PX4"),
	PINCTRL_PIN(TEGRA_PIN_UART5_RX_PX5, "UART5_RX_PX5"),
	PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PX6, "UART5_RTS_PX6"),
	PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PX7, "UART5_CTS_PX7"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM1_PY0, "GPIO_MDM1_PY0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM2_PY1, "GPIO_MDM2_PY1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM3_PY2, "GPIO_MDM3_PY2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM4_PY3, "GPIO_MDM4_PY3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM5_PY4, "GPIO_MDM5_PY4"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM6_PY5, "GPIO_MDM6_PY5"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_MDM7_PY6, "GPIO_MDM7_PY6"),
	PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PZ0, "CAN1_DOUT_PZ0"),
	PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PZ1, "CAN1_DIN_PZ1"),
	PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PZ2, "CAN0_DOUT_PZ2"),
	PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PZ3, "CAN0_DIN_PZ3"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO0_PAA0, "CAN_GPIO0_PAA0"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO1_PAA1, "CAN_GPIO1_PAA1"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO2_PAA2, "CAN_GPIO2_PAA2"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO3_PAA3, "CAN_GPIO3_PAA3"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO4_PAA4, "CAN_GPIO4_PAA4"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO5_PAA5, "CAN_GPIO5_PAA5"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO6_PAA6, "CAN_GPIO6_PAA6"),
	PINCTRL_PIN(TEGRA_PIN_CAN_GPIO7_PAA7, "CAN_GPIO7_PAA7"),
	PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PBB0, "UFS0_REF_CLK_PBB0"),
	PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PBB1, "UFS0_RST_PBB1"),
	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PCC0, "DAP4_SCLK_PCC0"),
	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PCC1, "DAP4_DOUT_PCC1"),
	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PCC2, "DAP4_DIN_PCC2"),
	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PCC3, "DAP4_FS_PCC3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN8_PEE0, "GPIO_SEN8_PEE0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SEN9_PEE1, "GPIO_SEN9_PEE1"),
	PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PEE2, "TOUCH_CLK_PEE2"),
	PINCTRL_PIN(TEGRA_PIN_POWER_ON_PFF0, "POWER_ON_PFF0"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SW1_PFF1, "GPIO_SW1_PFF1"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SW2_PFF2, "GPIO_SW2_PFF2"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SW3_PFF3, "GPIO_SW3_PFF3"),
	PINCTRL_PIN(TEGRA_PIN_GPIO_SW4_PFF4, "GPIO_SW4_PFF4"),
	PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP,	"SDMMC1_COMP"),
	PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
	PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
	PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
	PINCTRL_PIN(TEGRA_PIN_PMU_INT, "PMU_INT"),
	PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),

};

static const unsigned pex_l0_rst_n_pa0_pins[] = {
	TEGRA_PIN_PEX_L0_RST_N_PA0,
};

static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
	TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
};

static const unsigned pex_wake_n_pa2_pins[] = {
	TEGRA_PIN_PEX_WAKE_N_PA2,
};

static const unsigned pex_l1_rst_n_pa3_pins[] = {
	TEGRA_PIN_PEX_L1_RST_N_PA3,
};

static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
	TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
};

static const unsigned pex_l2_rst_n_pa5_pins[] = {
	TEGRA_PIN_PEX_L2_RST_N_PA5,
};

static const unsigned pex_l2_clkreq_n_pa6_pins[] = {
	TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
};

static const unsigned uart4_tx_pb0_pins[] = {
	TEGRA_PIN_UART4_TX_PB0,
};

static const unsigned uart4_rx_pb1_pins[] = {
	TEGRA_PIN_UART4_RX_PB1,
};

static const unsigned uart4_rts_pb2_pins[] = {
	TEGRA_PIN_UART4_RTS_PB2,
};

static const unsigned uart4_cts_pb3_pins[] = {
	TEGRA_PIN_UART4_CTS_PB3,
};

static const unsigned gpio_wan1_pb4_pins[] = {
	TEGRA_PIN_GPIO_WAN1_PB4,
};

static const unsigned gpio_wan2_pb5_pins[] = {
	TEGRA_PIN_GPIO_WAN2_PB5,
};

static const unsigned gpio_wan3_pb6_pins[] = {
	TEGRA_PIN_GPIO_WAN3_PB6,
};

static const unsigned gpio_wan4_pc0_pins[] = {
	TEGRA_PIN_GPIO_WAN4_PC0,
};

static const unsigned dap2_sclk_pc1_pins[] = {
	TEGRA_PIN_DAP2_SCLK_PC1,
};

static const unsigned dap2_dout_pc2_pins[] = {
	TEGRA_PIN_DAP2_DOUT_PC2,
};

static const unsigned dap2_din_pc3_pins[] = {
	TEGRA_PIN_DAP2_DIN_PC3,
};

static const unsigned dap2_fs_pc4_pins[] = {
	TEGRA_PIN_DAP2_FS_PC4,
};

static const unsigned gen1_i2c_scl_pc5_pins[] = {
	TEGRA_PIN_GEN1_I2C_SCL_PC5,
};

static const unsigned gen1_i2c_sda_pc6_pins[] = {
	TEGRA_PIN_GEN1_I2C_SDA_PC6,
};

static const unsigned sdmmc1_clk_pd0_pins[] = {
	TEGRA_PIN_SDMMC1_CLK_PD0,
};

static const unsigned sdmmc1_cmd_pd1_pins[] = {
	TEGRA_PIN_SDMMC1_CMD_PD1,
};

static const unsigned sdmmc1_comp_pins[] = {
	TEGRA_PIN_SDMMC1_COMP,
};

static const unsigned sdmmc1_dat0_pd2_pins[] = {
	TEGRA_PIN_SDMMC1_DAT0_PD2,
};

static const unsigned sdmmc1_dat1_pd3_pins[] = {
	TEGRA_PIN_SDMMC1_DAT1_PD3,
};

static const unsigned sdmmc1_dat2_pd4_pins[] = {
	TEGRA_PIN_SDMMC1_DAT2_PD4,
};

static const unsigned sdmmc1_dat3_pd5_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PD5,
};

static const unsigned eqos_txc_pe0_pins[] = {
	TEGRA_PIN_EQOS_TXC_PE0,
};

static const unsigned eqos_td0_pe1_pins[] = {
	TEGRA_PIN_EQOS_TD0_PE1,
};

static const unsigned eqos_td1_pe2_pins[] = {
	TEGRA_PIN_EQOS_TD1_PE2,
};

static const unsigned eqos_td2_pe3_pins[] = {
	TEGRA_PIN_EQOS_TD2_PE3,
};

static const unsigned eqos_td3_pe4_pins[] = {
	TEGRA_PIN_EQOS_TD3_PE4,
};

static const unsigned eqos_tx_ctl_pe5_pins[] = {
	TEGRA_PIN_EQOS_TX_CTL_PE5,
};

static const unsigned eqos_rd0_pe6_pins[] = {
	TEGRA_PIN_EQOS_RD0_PE6,
};

static const unsigned eqos_rd1_pe7_pins[] = {
	TEGRA_PIN_EQOS_RD1_PE7,
};

static const unsigned eqos_rd2_pf0_pins[] = {
	TEGRA_PIN_EQOS_RD2_PF0,
};

static const unsigned eqos_rd3_pf1_pins[] = {
	TEGRA_PIN_EQOS_RD3_PF1,
};

static const unsigned eqos_rx_ctl_pf2_pins[] = {
	TEGRA_PIN_EQOS_RX_CTL_PF2,
};

static const unsigned eqos_rxc_pf3_pins[] = {
	TEGRA_PIN_EQOS_RXC_PF3,
};

static const unsigned eqos_mdio_pf4_pins[] = {
	TEGRA_PIN_EQOS_MDIO_PF4,
};

static const unsigned eqos_mdc_pf5_pins[] = {
	TEGRA_PIN_EQOS_MDC_PF5,
};

static const unsigned eqos_comp_pins[] = {
	TEGRA_PIN_EQOS_COMP,
};

static const unsigned sdmmc4_clk_pcc4_pins[] = {};

static const unsigned sdmmc4_cmd_pt7_pins[] = {};

static const unsigned sdmmc4_dqs_pins[] = {};

static const unsigned sdmmc4_dat7_pins[] = {};

static const unsigned sdmmc4_dat6_pins[] = {};

static const unsigned sdmmc4_dat5_pins[] = {};

static const unsigned sdmmc4_dat4_pins[] = {};

static const unsigned sdmmc4_dat3_pins[] = {};

static const unsigned sdmmc4_dat2_pins[] = {};

static const unsigned sdmmc4_dat1_pins[] = {};

static const unsigned sdmmc4_dat0_pins[] = {};

static const unsigned sdmmc3_clk_pg0_pins[] = {
	TEGRA_PIN_SDMMC3_CLK_PG0,
};

static const unsigned sdmmc3_cmd_pg1_pins[] = {
	TEGRA_PIN_SDMMC3_CMD_PG1,
};

static const unsigned sdmmc3_dat0_pg2_pins[] = {
	TEGRA_PIN_SDMMC3_DAT0_PG2,
};

static const unsigned sdmmc3_comp_pins[] = {
	TEGRA_PIN_SDMMC3_COMP,
};

static const unsigned sdmmc3_dat1_pg3_pins[] = {
	TEGRA_PIN_SDMMC3_DAT1_PG3,
};

static const unsigned sdmmc3_dat2_pg4_pins[] = {
	TEGRA_PIN_SDMMC3_DAT2_PG4,
};

static const unsigned sdmmc3_dat3_pg5_pins[] = {
	TEGRA_PIN_SDMMC3_DAT3_PG5,
};

static const unsigned gpio_wan5_ph0_pins[] = {
	TEGRA_PIN_GPIO_WAN5_PH0,
};

static const unsigned gpio_wan6_ph1_pins[] = {
	TEGRA_PIN_GPIO_WAN6_PH1,
};

static const unsigned gpio_wan7_ph2_pins[] = {
	TEGRA_PIN_GPIO_WAN7_PH2,
};

static const unsigned gpio_wan8_ph3_pins[] = {
	TEGRA_PIN_GPIO_WAN8_PH3,
};

static const unsigned bcpu_pwr_req_ph4_pins[] = {
	TEGRA_PIN_BCPU_PWR_REQ_PH4,
};

static const unsigned mcpu_pwr_req_ph5_pins[] = {
	TEGRA_PIN_MCPU_PWR_REQ_PH5,
};

static const unsigned gpu_pwr_req_ph6_pins[] = {
	TEGRA_PIN_GPU_PWR_REQ_PH6,
};

static const unsigned gpio_pq0_pi0_pins[] = {
	TEGRA_PIN_GPIO_PQ0_PI0,
};

static const unsigned gpio_pq1_pi1_pins[] = {
	TEGRA_PIN_GPIO_PQ1_PI1,
};

static const unsigned gpio_pq2_pi2_pins[] = {
	TEGRA_PIN_GPIO_PQ2_PI2,
};

static const unsigned gpio_pq3_pi3_pins[] = {
	TEGRA_PIN_GPIO_PQ3_PI3,
};

static const unsigned gpio_pq4_pi4_pins[] = {
	TEGRA_PIN_GPIO_PQ4_PI4,
};

static const unsigned gpio_pq5_pi5_pins[] = {
	TEGRA_PIN_GPIO_PQ5_PI5,
};

static const unsigned gpio_pq6_pi6_pins[] = {
	TEGRA_PIN_GPIO_PQ6_PI6,
};

static const unsigned gpio_pq7_pi7_pins[] = {
	TEGRA_PIN_GPIO_PQ7_PI7,
};

static const unsigned dap1_sclk_pj0_pins[] = {
	TEGRA_PIN_DAP1_SCLK_PJ0,
};

static const unsigned dap1_dout_pj1_pins[] = {
	TEGRA_PIN_DAP1_DOUT_PJ1,
};

static const unsigned dap1_din_pj2_pins[] = {
	TEGRA_PIN_DAP1_DIN_PJ2,
};

static const unsigned dap1_fs_pj3_pins[] = {
	TEGRA_PIN_DAP1_FS_PJ3,
};

static const unsigned aud_mclk_pj4_pins[] = {
	TEGRA_PIN_AUD_MCLK_PJ4,
};

static const unsigned gpio_aud0_pj5_pins[] = {
	TEGRA_PIN_GPIO_AUD0_PJ5,
};

static const unsigned gpio_aud1_pj6_pins[] = {
	TEGRA_PIN_GPIO_AUD1_PJ6,
};

static const unsigned gpio_aud2_pj7_pins[] = {
	TEGRA_PIN_GPIO_AUD2_PJ7,
};

static const unsigned gpio_aud3_pk0_pins[] = {
	TEGRA_PIN_GPIO_AUD3_PK0,
};

static const unsigned gen7_i2c_scl_pl0_pins[] = {
	TEGRA_PIN_GEN7_I2C_SCL_PL0,
};

static const unsigned gen7_i2c_sda_pl1_pins[] = {
	TEGRA_PIN_GEN7_I2C_SDA_PL1,
};

static const unsigned gen9_i2c_scl_pl2_pins[] = {
	TEGRA_PIN_GEN9_I2C_SCL_PL2,
};

static const unsigned gen9_i2c_sda_pl3_pins[] = {
	TEGRA_PIN_GEN9_I2C_SDA_PL3,
};

static const unsigned usb_vbus_en0_pl4_pins[] = {
	TEGRA_PIN_USB_VBUS_EN0_PL4,
};

static const unsigned usb_vbus_en1_pl5_pins[] = {
	TEGRA_PIN_USB_VBUS_EN1_PL5,
};

static const unsigned gp_pwm6_pl6_pins[] = {
	TEGRA_PIN_GP_PWM6_PL6,
};

static const unsigned gp_pwm7_pl7_pins[] = {
	TEGRA_PIN_GP_PWM7_PL7,
};

static const unsigned dmic1_dat_pm0_pins[] = {
	TEGRA_PIN_DMIC1_DAT_PM0,
};

static const unsigned dmic1_clk_pm1_pins[] = {
	TEGRA_PIN_DMIC1_CLK_PM1,
};

static const unsigned dmic2_dat_pm2_pins[] = {
	TEGRA_PIN_DMIC2_DAT_PM2,
};

static const unsigned dmic2_clk_pm3_pins[] = {
	TEGRA_PIN_DMIC2_CLK_PM3,
};

static const unsigned dmic4_dat_pm4_pins[] = {
	TEGRA_PIN_DMIC4_DAT_PM4,
};

static const unsigned dmic4_clk_pm5_pins[] = {
	TEGRA_PIN_DMIC4_CLK_PM5,
};

static const unsigned gpio_cam1_pn0_pins[] = {
	TEGRA_PIN_GPIO_CAM1_PN0,
};

static const unsigned gpio_cam2_pn1_pins[] = {
	TEGRA_PIN_GPIO_CAM2_PN1,
};

static const unsigned gpio_cam3_pn2_pins[] = {
	TEGRA_PIN_GPIO_CAM3_PN2,
};

static const unsigned gpio_cam4_pn3_pins[] = {
	TEGRA_PIN_GPIO_CAM4_PN3,
};

static const unsigned gpio_cam5_pn4_pins[] = {
	TEGRA_PIN_GPIO_CAM5_PN4,
};

static const unsigned gpio_cam6_pn5_pins[] = {
	TEGRA_PIN_GPIO_CAM6_PN5,
};

static const unsigned gpio_cam7_pn6_pins[] = {
	TEGRA_PIN_GPIO_CAM7_PN6,
};

static const unsigned extperiph1_clk_po0_pins[] = {
	TEGRA_PIN_EXTPERIPH1_CLK_PO0,
};

static const unsigned extperiph2_clk_po1_pins[] = {
	TEGRA_PIN_EXTPERIPH2_CLK_PO1,
};

static const unsigned cam_i2c_scl_po2_pins[] = {
	TEGRA_PIN_CAM_I2C_SCL_PO2,
};

static const unsigned cam_i2c_sda_po3_pins[] = {
	TEGRA_PIN_CAM_I2C_SDA_PO3,
};

static const unsigned dp_aux_ch0_hpd_pp0_pins[] = {
	TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
};

static const unsigned dp_aux_ch1_hpd_pp1_pins[] = {
	TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
};

static const unsigned hdmi_cec_pp2_pins[] = {
	TEGRA_PIN_HDMI_CEC_PP2,
};

static const unsigned gpio_edp0_pp3_pins[] = {
	TEGRA_PIN_GPIO_EDP0_PP3,
};

static const unsigned gpio_edp1_pp4_pins[] = {
	TEGRA_PIN_GPIO_EDP1_PP4,
};

static const unsigned gpio_edp2_pp5_pins[] = {
	TEGRA_PIN_GPIO_EDP2_PP5,
};

static const unsigned gpio_edp3_pp6_pins[] = {
	TEGRA_PIN_GPIO_EDP3_PP6,
};

static const unsigned directdc1_clk_pq0_pins[] = {
	TEGRA_PIN_DIRECTDC1_CLK_PQ0,
};

static const unsigned directdc_comp_pins[] = {
	TEGRA_PIN_DIRECTDC_COMP,
};

static const unsigned directdc1_in_pq1_pins[] = {
	TEGRA_PIN_DIRECTDC1_IN_PQ1,
};

static const unsigned directdc1_out0_pq2_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
};

static const unsigned directdc1_out1_pq3_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
};

static const unsigned directdc1_out2_pq4_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
};

static const unsigned directdc1_out3_pq5_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
};

static const unsigned qspi_sck_pr0_pins[] = {
	TEGRA_PIN_QSPI_SCK_PR0,
};

static const unsigned qspi_io0_pr1_pins[] = {
	TEGRA_PIN_QSPI_IO0_PR1,
};

static const unsigned qspi_io1_pr2_pins[] = {
	TEGRA_PIN_QSPI_IO1_PR2,
};

static const unsigned qspi_io2_pr3_pins[] = {
	TEGRA_PIN_QSPI_IO2_PR3,
};

static const unsigned qspi_io3_pr4_pins[] = {
	TEGRA_PIN_QSPI_IO3_PR4,
};

static const unsigned qspi_cs_n_pr5_pins[] = {
	TEGRA_PIN_QSPI_CS_N_PR5,
};

static const unsigned qspi_comp_pins[] = {
	TEGRA_PIN_QSPI_COMP,
};

static const unsigned pwr_i2c_scl_ps0_pins[] = {
	TEGRA_PIN_PWR_I2C_SCL_PS0,
};

static const unsigned pwr_i2c_sda_ps1_pins[] = {
	TEGRA_PIN_PWR_I2C_SDA_PS1,
};

static const unsigned batt_oc_ps2_pins[] = {
	TEGRA_PIN_BATT_OC_PS2,
};

static const unsigned safe_state_ps3_pins[] = {
	TEGRA_PIN_SAFE_STATE_PS3,
};

static const unsigned vcomp_alert_ps4_pins[] = {
	TEGRA_PIN_VCOMP_ALERT_PS4,
};

static const unsigned soc_pwr_req_pins[] = {
	TEGRA_PIN_SOC_PWR_REQ,
};

static const unsigned uart1_tx_pt0_pins[] = {
	TEGRA_PIN_UART1_TX_PT0,
};

static const unsigned uart1_rx_pt1_pins[] = {
	TEGRA_PIN_UART1_RX_PT1,
};

static const unsigned uart1_rts_pt2_pins[] = {
	TEGRA_PIN_UART1_RTS_PT2,
};

static const unsigned uart1_cts_pt3_pins[] = {
	TEGRA_PIN_UART1_CTS_PT3,
};

static const unsigned gpio_dis0_pu0_pins[] = {
	TEGRA_PIN_GPIO_DIS0_PU0,
};

static const unsigned gpio_dis1_pu1_pins[] = {
	TEGRA_PIN_GPIO_DIS1_PU1,
};

static const unsigned gpio_dis2_pu2_pins[] = {
	TEGRA_PIN_GPIO_DIS2_PU2,
};

static const unsigned gpio_dis3_pu3_pins[] = {
	TEGRA_PIN_GPIO_DIS3_PU3,
};

static const unsigned gpio_dis4_pu4_pins[] = {
	TEGRA_PIN_GPIO_DIS4_PU4,
};

static const unsigned gpio_dis5_pu5_pins[] = {
	TEGRA_PIN_GPIO_DIS5_PU5,
};

static const unsigned gpio_sen0_pv0_pins[] = {
	TEGRA_PIN_GPIO_SEN0_PV0,
};

static const unsigned gpio_sen1_pv1_pins[] = {
	TEGRA_PIN_GPIO_SEN1_PV1,
};

static const unsigned gpio_sen2_pv2_pins[] = {
	TEGRA_PIN_GPIO_SEN2_PV2,
};

static const unsigned gpio_sen3_pv3_pins[] = {
	TEGRA_PIN_GPIO_SEN3_PV3,
};

static const unsigned gpio_sen4_pv4_pins[] = {
	TEGRA_PIN_GPIO_SEN4_PV4,
};

static const unsigned gpio_sen5_pv5_pins[] = {
	TEGRA_PIN_GPIO_SEN5_PV5,
};

static const unsigned gpio_sen6_pv6_pins[] = {
	TEGRA_PIN_GPIO_SEN6_PV6,
};

static const unsigned gpio_sen7_pv7_pins[] = {
	TEGRA_PIN_GPIO_SEN7_PV7,
};

static const unsigned gen8_i2c_scl_pw0_pins[] = {
	TEGRA_PIN_GEN8_I2C_SCL_PW0,
};

static const unsigned gen8_i2c_sda_pw1_pins[] = {
	TEGRA_PIN_GEN8_I2C_SDA_PW1,
};

static const unsigned uart3_tx_pw2_pins[] = {
	TEGRA_PIN_UART3_TX_PW2,
};

static const unsigned uart3_rx_pw3_pins[] = {
	TEGRA_PIN_UART3_RX_PW3,
};

static const unsigned uart3_rts_pw4_pins[] = {
	TEGRA_PIN_UART3_RTS_PW4,
};

static const unsigned uart3_cts_pw5_pins[] = {
	TEGRA_PIN_UART3_CTS_PW5,
};

static const unsigned uart7_tx_pw6_pins[] = {
	TEGRA_PIN_UART7_TX_PW6,
};

static const unsigned uart7_rx_pw7_pins[] = {
	TEGRA_PIN_UART7_RX_PW7,
};

static const unsigned uart2_tx_px0_pins[] = {
	TEGRA_PIN_UART2_TX_PX0,
};

static const unsigned uart2_rx_px1_pins[] = {
	TEGRA_PIN_UART2_RX_PX1,
};

static const unsigned uart2_rts_px2_pins[] = {
	TEGRA_PIN_UART2_RTS_PX2,
};

static const unsigned uart2_cts_px3_pins[] = {
	TEGRA_PIN_UART2_CTS_PX3,
};

static const unsigned uart5_tx_px4_pins[] = {
	TEGRA_PIN_UART5_TX_PX4,
};

static const unsigned uart5_rx_px5_pins[] = {
	TEGRA_PIN_UART5_RX_PX5,
};

static const unsigned uart5_rts_px6_pins[] = {
	TEGRA_PIN_UART5_RTS_PX6,
};

static const unsigned uart5_cts_px7_pins[] = {
	TEGRA_PIN_UART5_CTS_PX7,
};

static const unsigned gpio_mdm1_py0_pins[] = {
	TEGRA_PIN_GPIO_MDM1_PY0,
};

static const unsigned gpio_mdm2_py1_pins[] = {
	TEGRA_PIN_GPIO_MDM2_PY1,
};

static const unsigned gpio_mdm3_py2_pins[] = {
	TEGRA_PIN_GPIO_MDM3_PY2,
};

static const unsigned gpio_mdm4_py3_pins[] = {
	TEGRA_PIN_GPIO_MDM4_PY3,
};

static const unsigned gpio_mdm5_py4_pins[] = {
	TEGRA_PIN_GPIO_MDM5_PY4,
};

static const unsigned gpio_mdm6_py5_pins[] = {
	TEGRA_PIN_GPIO_MDM6_PY5,
};

static const unsigned gpio_mdm7_py6_pins[] = {
	TEGRA_PIN_GPIO_MDM7_PY6,
};

static const unsigned can1_dout_pz0_pins[] = {
	TEGRA_PIN_CAN1_DOUT_PZ0,
};

static const unsigned can1_din_pz1_pins[] = {
	TEGRA_PIN_CAN1_DIN_PZ1,
};

static const unsigned can0_dout_pz2_pins[] = {
	TEGRA_PIN_CAN0_DOUT_PZ2,
};

static const unsigned can0_din_pz3_pins[] = {
	TEGRA_PIN_CAN0_DIN_PZ3,
};

static const unsigned can_gpio0_paa0_pins[] = {
	TEGRA_PIN_CAN_GPIO0_PAA0,
};

static const unsigned can_gpio1_paa1_pins[] = {
	TEGRA_PIN_CAN_GPIO1_PAA1,
};

static const unsigned can_gpio2_paa2_pins[] = {
	TEGRA_PIN_CAN_GPIO2_PAA2,
};

static const unsigned can_gpio3_paa3_pins[] = {
	TEGRA_PIN_CAN_GPIO3_PAA3,
};

static const unsigned can_gpio4_paa4_pins[] = {
	TEGRA_PIN_CAN_GPIO4_PAA4,
};

static const unsigned can_gpio5_paa5_pins[] = {
	TEGRA_PIN_CAN_GPIO5_PAA5,
};

static const unsigned can_gpio6_paa6_pins[] = {
	TEGRA_PIN_CAN_GPIO6_PAA6,
};

static const unsigned can_gpio7_paa7_pins[] = {
	TEGRA_PIN_CAN_GPIO7_PAA7,
};

static const unsigned ufs0_ref_clk_pbb0_pins[] = {
	TEGRA_PIN_UFS0_REF_CLK_PBB0,
};

static const unsigned ufs0_rst_pbb1_pins[] = {
	TEGRA_PIN_UFS0_RST_PBB1,
};

static const unsigned dap4_sclk_pcc0_pins[] = {
	TEGRA_PIN_DAP4_SCLK_PCC0,
};

static const unsigned dap4_dout_pcc1_pins[] = {
	TEGRA_PIN_DAP4_DOUT_PCC1,
};

static const unsigned dap4_din_pcc2_pins[] = {
	TEGRA_PIN_DAP4_DIN_PCC2,
};

static const unsigned dap4_fs_pcc3_pins[] = {
	TEGRA_PIN_DAP4_FS_PCC3,
};

static const unsigned gpio_sen8_pee0_pins[] = {
	TEGRA_PIN_GPIO_SEN8_PEE0,
};

static const unsigned gpio_sen9_pee1_pins[] = {
	TEGRA_PIN_GPIO_SEN9_PEE1,
};


static const unsigned touch_clk_pee2_pins[] = {
	TEGRA_PIN_TOUCH_CLK_PEE2,
};

static const unsigned power_on_pff0_pins[] = {
	TEGRA_PIN_POWER_ON_PFF0,
};

static const unsigned gpio_sw1_pff1_pins[] = {
	TEGRA_PIN_GPIO_SW1_PFF1,
};

static const unsigned gpio_sw2_pff2_pins[] = {
	TEGRA_PIN_GPIO_SW2_PFF2,
};

static const unsigned gpio_sw3_pff3_pins[] = {
	TEGRA_PIN_GPIO_SW3_PFF3,
};

static const unsigned gpio_sw4_pff4_pins[] = {
	TEGRA_PIN_GPIO_SW4_PFF4,
};

static const unsigned clk_32k_in_pins[] = {
	TEGRA_PIN_CLK_32K_IN,
};

static const unsigned shutdown_pins[] = {
	TEGRA_PIN_SHUTDOWN,
};

static const unsigned pmu_int_pins[] = {
	TEGRA_PIN_PMU_INT,
};

static const unsigned drive_ufs0_rst_pins[] = {
	TEGRA_PIN_UFS0_RST_PBB1,
};

static const unsigned drive_ufs0_ref_clk_pins[] = {
	TEGRA_PIN_UFS0_REF_CLK_PBB0,
};

static const unsigned drive_gpio_wan8_pins[] = {
	TEGRA_PIN_GPIO_WAN8_PH3,
};

static const unsigned drive_gpio_wan7_pins[] = {
	TEGRA_PIN_GPIO_WAN7_PH2,
};

static const unsigned drive_gpio_wan6_pins[] = {
	TEGRA_PIN_GPIO_WAN6_PH1,
};

static const unsigned drive_gpio_wan5_pins[] = {
	TEGRA_PIN_GPIO_WAN5_PH0,
};

static const unsigned drive_uart2_tx_pins[] = {
	TEGRA_PIN_UART2_TX_PX0,
};

static const unsigned drive_uart2_rx_pins[] = {
	TEGRA_PIN_UART2_RX_PX1,
};

static const unsigned drive_uart2_rts_pins[] = {
	TEGRA_PIN_UART2_RTS_PX2,
};

static const unsigned drive_uart2_cts_pins[] = {
	TEGRA_PIN_UART2_CTS_PX3,
};

static const unsigned drive_uart5_rx_pins[] = {
	TEGRA_PIN_UART5_RX_PX5,
};

static const unsigned drive_uart5_tx_pins[] = {
	TEGRA_PIN_UART5_TX_PX4,
};

static const unsigned drive_uart5_rts_pins[] = {
	TEGRA_PIN_UART5_RTS_PX6,
};

static const unsigned drive_uart5_cts_pins[] = {
	TEGRA_PIN_UART5_CTS_PX7,
};

static const unsigned drive_gpio_mdm1_pins[] = {
	TEGRA_PIN_GPIO_MDM1_PY0,
};

static const unsigned drive_gpio_mdm2_pins[] = {
	TEGRA_PIN_GPIO_MDM2_PY1,
};

static const unsigned drive_gpio_mdm3_pins[] = {
	TEGRA_PIN_GPIO_MDM3_PY2,
};

static const unsigned drive_gpio_mdm4_pins[] = {
	TEGRA_PIN_GPIO_MDM4_PY3,
};

static const unsigned drive_gpio_mdm5_pins[] = {
	TEGRA_PIN_GPIO_MDM5_PY4,
};

static const unsigned drive_gpio_mdm6_pins[] = {
	TEGRA_PIN_GPIO_MDM6_PY5,
};

static const unsigned drive_gpio_mdm7_pins[] = {
	TEGRA_PIN_GPIO_MDM7_PY6,
};

static const unsigned drive_bcpu_pwr_req_pins[] = {
	TEGRA_PIN_BCPU_PWR_REQ_PH4,
};

static const unsigned drive_mcpu_pwr_req_pins[] = {
	TEGRA_PIN_MCPU_PWR_REQ_PH5,
};

static const unsigned drive_gpu_pwr_req_pins[] = {
	TEGRA_PIN_GPU_PWR_REQ_PH6,
};

static const unsigned drive_gen7_i2c_scl_pins[] = {
	TEGRA_PIN_GEN7_I2C_SCL_PL0,
};

static const unsigned drive_gen7_i2c_sda_pins[] = {
	TEGRA_PIN_GEN7_I2C_SDA_PL1,
};

static const unsigned drive_gen9_i2c_sda_pins[] = {
	TEGRA_PIN_GEN9_I2C_SDA_PL3,
};

static const unsigned drive_gen9_i2c_scl_pins[] = {
	TEGRA_PIN_GEN9_I2C_SCL_PL2,
};

static const unsigned drive_usb_vbus_en0_pins[] = {
	TEGRA_PIN_USB_VBUS_EN0_PL4,
};

static const unsigned drive_usb_vbus_en1_pins[] = {
	TEGRA_PIN_USB_VBUS_EN1_PL5,
};

static const unsigned drive_gp_pwm7_pins[] = {
	TEGRA_PIN_GP_PWM7_PL7,
};

static const unsigned drive_gp_pwm6_pins[] = {
	TEGRA_PIN_GP_PWM6_PL6,
};

static const unsigned drive_gpio_sw1_pins[] = {
	TEGRA_PIN_GPIO_SW1_PFF1,
};

static const unsigned drive_gpio_sw2_pins[] = {
	TEGRA_PIN_GPIO_SW2_PFF2,
};

static const unsigned drive_gpio_sw3_pins[] = {
	TEGRA_PIN_GPIO_SW3_PFF3,
};

static const unsigned drive_gpio_sw4_pins[] = {
	TEGRA_PIN_GPIO_SW4_PFF4,
};

static const unsigned drive_shutdown_pins[] = {
	TEGRA_PIN_SHUTDOWN,
};

static const unsigned drive_pmu_int_pins[] = {
};

static const unsigned drive_safe_state_pins[] = {
	TEGRA_PIN_SAFE_STATE_PS3,
};

static const unsigned drive_vcomp_alert_pins[] = {
	TEGRA_PIN_VCOMP_ALERT_PS4,
};

static const unsigned drive_soc_pwr_req_pins[] = {
	TEGRA_PIN_SOC_PWR_REQ,
};

static const unsigned drive_batt_oc_pins[] = {
	TEGRA_PIN_BATT_OC_PS2,
};

static const unsigned drive_clk_32k_in_pins[] = {
	TEGRA_PIN_CLK_32K_IN,
};

static const unsigned drive_power_on_pins[] = {
	TEGRA_PIN_POWER_ON_PFF0,
};

static const unsigned drive_pwr_i2c_scl_pins[] = {
	TEGRA_PIN_PWR_I2C_SCL_PS0,
};

static const unsigned drive_pwr_i2c_sda_pins[] = {
	TEGRA_PIN_PWR_I2C_SDA_PS1,
};

static const unsigned drive_gpio_dis0_pins[] = {
	TEGRA_PIN_GPIO_DIS0_PU0,
};

static const unsigned drive_gpio_dis1_pins[] = {
	TEGRA_PIN_GPIO_DIS1_PU1,
};

static const unsigned drive_gpio_dis2_pins[] = {
	TEGRA_PIN_GPIO_DIS2_PU2,
};

static const unsigned drive_gpio_dis3_pins[] = {
	TEGRA_PIN_GPIO_DIS3_PU3,
};

static const unsigned drive_gpio_dis4_pins[] = {
	TEGRA_PIN_GPIO_DIS4_PU4,
};

static const unsigned drive_gpio_dis5_pins[] = {
	TEGRA_PIN_GPIO_DIS5_PU5,
};

static const unsigned drive_qspi_io3_pins[] = {
	TEGRA_PIN_QSPI_IO3_PR4,
};

static const unsigned drive_qspi_io2_pins[] = {
	TEGRA_PIN_QSPI_IO2_PR3,
};

static const unsigned drive_qspi_io1_pins[] = {
	TEGRA_PIN_QSPI_IO1_PR2,
};

static const unsigned drive_qspi_io0_pins[] = {
	TEGRA_PIN_QSPI_IO0_PR1,
};

static const unsigned drive_qspi_sck_pins[] = {
	TEGRA_PIN_QSPI_SCK_PR0,
};

static const unsigned drive_qspi_cs_n_pins[] = {
	TEGRA_PIN_QSPI_CS_N_PR5,
};

static const unsigned drive_sdmmc3_dat3_pins[] = {
	TEGRA_PIN_SDMMC3_DAT3_PG5,
};

static const unsigned drive_sdmmc3_dat2_pins[] = {
	TEGRA_PIN_SDMMC3_DAT2_PG4,
};

static const unsigned drive_sdmmc3_dat1_pins[] = {
	TEGRA_PIN_SDMMC3_DAT1_PG3,
};

static const unsigned drive_sdmmc3_dat0_pins[] = {
	TEGRA_PIN_SDMMC3_DAT0_PG2,
};

static const unsigned drive_sdmmc3_cmd_pins[] = {
	TEGRA_PIN_SDMMC3_CMD_PG1,
};

static const unsigned drive_sdmmc3_clk_pins[] = {
	TEGRA_PIN_SDMMC3_CLK_PG0,
};

static const unsigned drive_eqos_td3_pins[] = {
	TEGRA_PIN_EQOS_TD3_PE4,
};

static const unsigned drive_eqos_td2_pins[] = {
	TEGRA_PIN_EQOS_TD2_PE3,
};

static const unsigned drive_eqos_td1_pins[] = {
	TEGRA_PIN_EQOS_TD1_PE2,
};

static const unsigned drive_eqos_td0_pins[] = {
	TEGRA_PIN_EQOS_TD0_PE1,
};

static const unsigned drive_eqos_rd3_pins[] = {
	TEGRA_PIN_EQOS_RD3_PF1,
};

static const unsigned drive_eqos_rd2_pins[] = {
	TEGRA_PIN_EQOS_RD2_PF0,
};

static const unsigned drive_eqos_rd1_pins[] = {
	TEGRA_PIN_EQOS_RD1_PE7,
};

static const unsigned drive_eqos_mdio_pins[] = {
	TEGRA_PIN_EQOS_MDIO_PF4,
};

static const unsigned drive_eqos_rd0_pins[] = {
	TEGRA_PIN_EQOS_RD0_PE6,
};

static const unsigned drive_eqos_mdc_pins[] = {
	TEGRA_PIN_EQOS_MDC_PF5,
};

static const unsigned drive_eqos_txc_pins[] = {
	TEGRA_PIN_EQOS_TXC_PE0,
};

static const unsigned drive_eqos_rxc_pins[] = {
	TEGRA_PIN_EQOS_RXC_PF3,
};

static const unsigned drive_eqos_tx_ctl_pins[] = {
	TEGRA_PIN_EQOS_TX_CTL_PE5,
};

static const unsigned drive_eqos_rx_ctl_pins[] = {
	TEGRA_PIN_EQOS_RX_CTL_PF2,
};

static const unsigned drive_sdmmc1_clk_pins[] = {
	TEGRA_PIN_SDMMC1_CLK_PD0,
};

static const unsigned drive_sdmmc1_cmd_pins[] = {
	TEGRA_PIN_SDMMC1_CMD_PD1,
};

static const unsigned drive_sdmmc1_dat3_pins[] = {
	TEGRA_PIN_SDMMC1_DAT3_PD5,
};

static const unsigned drive_sdmmc1_dat2_pins[] = {
	TEGRA_PIN_SDMMC1_DAT2_PD4,
};

static const unsigned drive_sdmmc1_dat1_pins[] = {
	TEGRA_PIN_SDMMC1_DAT1_PD3,
};

static const unsigned drive_sdmmc1_dat0_pins[] = {
	TEGRA_PIN_SDMMC1_DAT0_PD2,
};

static const unsigned drive_pex_l2_clkreq_n_pins[] = {
	TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
};

static const unsigned drive_pex_wake_n_pins[] = {
	TEGRA_PIN_PEX_WAKE_N_PA2,
};

static const unsigned drive_pex_l1_clkreq_n_pins[] = {
	TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
};

static const unsigned drive_pex_l1_rst_n_pins[] = {
	TEGRA_PIN_PEX_L1_RST_N_PA3,
};

static const unsigned drive_pex_l0_clkreq_n_pins[] = {
	TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
};

static const unsigned drive_pex_l0_rst_n_pins[] = {
	TEGRA_PIN_PEX_L0_RST_N_PA0,
};

static const unsigned drive_pex_l2_rst_n_pins[] = {
	TEGRA_PIN_PEX_L2_RST_N_PA5,
};

static const unsigned drive_gpio_edp2_pins[] = {
	TEGRA_PIN_GPIO_EDP2_PP5,
};

static const unsigned drive_gpio_edp3_pins[] = {
	TEGRA_PIN_GPIO_EDP3_PP6,
};

static const unsigned drive_gpio_edp0_pins[] = {
	TEGRA_PIN_GPIO_EDP0_PP3,
};

static const unsigned drive_gpio_edp1_pins[] = {
	TEGRA_PIN_GPIO_EDP1_PP4,
};

static const unsigned drive_dp_aux_ch0_hpd_pins[] = {
	TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
};

static const unsigned drive_dp_aux_ch1_hpd_pins[] = {
	TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
};

static const unsigned drive_hdmi_cec_pins[] = {
	TEGRA_PIN_HDMI_CEC_PP2,
};

static const unsigned drive_gpio_pq0_pins[] = {
	TEGRA_PIN_GPIO_PQ0_PI0,
};

static const unsigned drive_gpio_pq1_pins[] = {
	TEGRA_PIN_GPIO_PQ1_PI1,
};

static const unsigned drive_gpio_pq2_pins[] = {
	TEGRA_PIN_GPIO_PQ2_PI2,
};

static const unsigned drive_gpio_pq3_pins[] = {
	TEGRA_PIN_GPIO_PQ3_PI3,
};

static const unsigned drive_gpio_pq4_pins[] = {
	TEGRA_PIN_GPIO_PQ4_PI4,
};

static const unsigned drive_gpio_pq5_pins[] = {
	TEGRA_PIN_GPIO_PQ5_PI5,
};

static const unsigned drive_gpio_pq6_pins[] = {
	TEGRA_PIN_GPIO_PQ6_PI6,
};

static const unsigned drive_gpio_pq7_pins[] = {
	TEGRA_PIN_GPIO_PQ7_PI7,
};

static const unsigned drive_dap2_din_pins[] = {
	TEGRA_PIN_DAP2_DIN_PC3,
};

static const unsigned drive_dap2_dout_pins[] = {
	TEGRA_PIN_DAP2_DOUT_PC2,
};

static const unsigned drive_dap2_fs_pins[] = {
	TEGRA_PIN_DAP2_FS_PC4,
};

static const unsigned drive_dap2_sclk_pins[] = {
	TEGRA_PIN_DAP2_SCLK_PC1,
};

static const unsigned drive_uart4_cts_pins[] = {
	TEGRA_PIN_UART4_CTS_PB3,
};

static const unsigned drive_uart4_rts_pins[] = {
	TEGRA_PIN_UART4_RTS_PB2,
};

static const unsigned drive_uart4_rx_pins[] = {
	TEGRA_PIN_UART4_RX_PB1,
};

static const unsigned drive_uart4_tx_pins[] = {
	TEGRA_PIN_UART4_TX_PB0,
};

static const unsigned drive_gpio_wan4_pins[] = {
	TEGRA_PIN_GPIO_WAN4_PC0,
};

static const unsigned drive_gpio_wan3_pins[] = {
	TEGRA_PIN_GPIO_WAN3_PB6,
};

static const unsigned drive_gpio_wan2_pins[] = {
	TEGRA_PIN_GPIO_WAN2_PB5,
};

static const unsigned drive_gpio_wan1_pins[] = {
	TEGRA_PIN_GPIO_WAN1_PB4,
};

static const unsigned drive_gen1_i2c_scl_pins[] = {
	TEGRA_PIN_GEN1_I2C_SCL_PC5,
};

static const unsigned drive_gen1_i2c_sda_pins[] = {
	TEGRA_PIN_GEN1_I2C_SDA_PC6,
};

static const unsigned drive_extperiph2_clk_pins[] = {
	TEGRA_PIN_EXTPERIPH1_CLK_PO0,
};

static const unsigned drive_extperiph1_clk_pins[] = {
	TEGRA_PIN_EXTPERIPH2_CLK_PO1,
};

static const unsigned drive_cam_i2c_sda_pins[] = {
	TEGRA_PIN_CAM_I2C_SDA_PO3,
};

static const unsigned drive_cam_i2c_scl_pins[] = {
	TEGRA_PIN_CAM_I2C_SCL_PO2,
};

static const unsigned drive_gpio_cam1_pins[] = {
	TEGRA_PIN_GPIO_CAM1_PN0,
};

static const unsigned drive_gpio_cam2_pins[] = {
	TEGRA_PIN_GPIO_CAM2_PN1,
};

static const unsigned drive_gpio_cam3_pins[] = {
	TEGRA_PIN_GPIO_CAM3_PN2,
};

static const unsigned drive_gpio_cam4_pins[] = {
	TEGRA_PIN_GPIO_CAM4_PN3,
};

static const unsigned drive_gpio_cam5_pins[] = {
	TEGRA_PIN_GPIO_CAM5_PN4,
};

static const unsigned drive_gpio_cam6_pins[] = {
	TEGRA_PIN_GPIO_CAM6_PN5,
};

static const unsigned drive_gpio_cam7_pins[] = {
	TEGRA_PIN_GPIO_CAM7_PN6,
};

static const unsigned drive_dmic1_clk_pins[] = {
	TEGRA_PIN_DMIC1_CLK_PM1,
};

static const unsigned drive_dmic1_dat_pins[] = {
	TEGRA_PIN_DMIC1_DAT_PM0,
};

static const unsigned drive_dmic2_dat_pins[] = {
	TEGRA_PIN_DMIC2_DAT_PM2,
};

static const unsigned drive_dmic2_clk_pins[] = {
	TEGRA_PIN_DMIC2_CLK_PM3,
};

static const unsigned drive_dmic4_dat_pins[] = {
	TEGRA_PIN_DMIC4_DAT_PM4,
};

static const unsigned drive_dmic4_clk_pins[] = {
	TEGRA_PIN_DMIC4_CLK_PM5,
};

static const unsigned drive_dap4_fs_pins[] = {
	TEGRA_PIN_DAP4_FS_PCC3,
};

static const unsigned drive_dap4_din_pins[] = {
	TEGRA_PIN_DAP4_DIN_PCC2,
};

static const unsigned drive_dap4_dout_pins[] = {
	TEGRA_PIN_DAP4_DOUT_PCC1,
};

static const unsigned drive_dap4_sclk_pins[] = {
	TEGRA_PIN_DAP4_SCLK_PCC0,
};

static const unsigned drive_gpio_aud3_pins[] = {
	TEGRA_PIN_GPIO_AUD3_PK0,
};

static const unsigned drive_gpio_aud2_pins[] = {
	TEGRA_PIN_GPIO_AUD2_PJ7,
};

static const unsigned drive_gpio_aud1_pins[] = {
	TEGRA_PIN_GPIO_AUD1_PJ6,
};

static const unsigned drive_gpio_aud0_pins[] = {
	TEGRA_PIN_GPIO_AUD0_PJ5,
};

static const unsigned drive_aud_mclk_pins[] = {
	TEGRA_PIN_AUD_MCLK_PJ4,
};

static const unsigned drive_dap1_fs_pins[] = {
	TEGRA_PIN_DAP1_FS_PJ3,
};

static const unsigned drive_dap1_din_pins[] = {
	TEGRA_PIN_DAP1_DIN_PJ2,
};

static const unsigned drive_dap1_dout_pins[] = {
	TEGRA_PIN_DAP1_DOUT_PJ1,
};

static const unsigned drive_dap1_sclk_pins[] = {
	TEGRA_PIN_DAP1_SCLK_PJ0,
};

static const unsigned drive_touch_clk_pins[] = {
	TEGRA_PIN_TOUCH_CLK_PEE2,
};

static const unsigned drive_uart3_cts_pins[] = {
	TEGRA_PIN_UART3_CTS_PW5,
};

static const unsigned drive_uart3_rts_pins[] = {
	TEGRA_PIN_UART3_RTS_PW4,
};

static const unsigned drive_uart3_rx_pins[] = {
	TEGRA_PIN_UART3_RX_PW3,
};

static const unsigned drive_uart3_tx_pins[] = {
	TEGRA_PIN_UART3_TX_PW2,
};

static const unsigned drive_gen8_i2c_sda_pins[] = {
	TEGRA_PIN_GEN8_I2C_SDA_PW1,
};

static const unsigned drive_gen8_i2c_scl_pins[] = {
	TEGRA_PIN_GEN8_I2C_SCL_PW0,
};

static const unsigned drive_uart7_rx_pins[] = {
	TEGRA_PIN_UART7_RX_PW7,
};

static const unsigned drive_uart7_tx_pins[] = {
	TEGRA_PIN_UART7_TX_PW6,
};

static const unsigned drive_gpio_sen0_pins[] = {
	TEGRA_PIN_GPIO_SEN0_PV0,
};

static const unsigned drive_gpio_sen1_pins[] = {
	TEGRA_PIN_GPIO_SEN1_PV1,
};

static const unsigned drive_gpio_sen2_pins[] = {
	TEGRA_PIN_GPIO_SEN2_PV2,
};

static const unsigned drive_gpio_sen3_pins[] = {
	TEGRA_PIN_GPIO_SEN3_PV3,
};

static const unsigned drive_gpio_sen4_pins[] = {
	TEGRA_PIN_GPIO_SEN4_PV4,
};

static const unsigned drive_gpio_sen5_pins[] = {
	TEGRA_PIN_GPIO_SEN5_PV5,
};

static const unsigned drive_gpio_sen6_pins[] = {
	TEGRA_PIN_GPIO_SEN6_PV6,
};

static const unsigned drive_gpio_sen7_pins[] = {
	TEGRA_PIN_GPIO_SEN7_PV7,
};

static const unsigned drive_gpio_sen8_pins[] = {
	TEGRA_PIN_GPIO_SEN8_PEE0,
};

static const unsigned drive_gpio_sen9_pins[] = {
	TEGRA_PIN_GPIO_SEN9_PEE1,
};

static const unsigned drive_can_gpio7_pins[] = {
	TEGRA_PIN_CAN_GPIO7_PAA7,
};

static const unsigned drive_can1_dout_pins[] = {
	TEGRA_PIN_CAN1_DOUT_PZ0,
};

static const unsigned drive_can1_din_pins[] = {
	TEGRA_PIN_CAN1_DIN_PZ1,
};

static const unsigned drive_can0_dout_pins[] = {
	TEGRA_PIN_CAN0_DOUT_PZ2,
};

static const unsigned drive_can0_din_pins[] = {
	TEGRA_PIN_CAN0_DIN_PZ3,
};

static const unsigned drive_can_gpio0_pins[] = {
	TEGRA_PIN_CAN_GPIO0_PAA0,
};

static const unsigned drive_can_gpio1_pins[] = {
	TEGRA_PIN_CAN_GPIO1_PAA1,
};

static const unsigned drive_can_gpio2_pins[] = {
	TEGRA_PIN_CAN_GPIO2_PAA2,
};

static const unsigned drive_can_gpio3_pins[] = {
	TEGRA_PIN_CAN_GPIO3_PAA3,
};

static const unsigned drive_can_gpio4_pins[] = {
	TEGRA_PIN_CAN_GPIO4_PAA4,
};

static const unsigned drive_can_gpio5_pins[] = {
	TEGRA_PIN_CAN_GPIO5_PAA5,
};

static const unsigned drive_can_gpio6_pins[] = {
	TEGRA_PIN_CAN_GPIO6_PAA6,
};

static const unsigned drive_uart1_cts_pins[] = {
	TEGRA_PIN_UART1_CTS_PT3,
};

static const unsigned drive_uart1_rts_pins[] = {
	TEGRA_PIN_UART1_RTS_PT2,
};

static const unsigned drive_uart1_rx_pins[] = {
	TEGRA_PIN_UART1_RX_PT1,
};

static const unsigned drive_uart1_tx_pins[] = {
	TEGRA_PIN_UART1_TX_PT0,
};

static const unsigned drive_directdc1_out3_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
};

static const unsigned drive_directdc1_out2_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
};

static const unsigned drive_directdc1_out1_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
};

static const unsigned drive_directdc1_out0_pins[] = {
	TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
};

static const unsigned drive_directdc1_clk_pins[] = {
	TEGRA_PIN_DIRECTDC1_CLK_PQ0,
};

static const unsigned drive_directdc1_in_pins[] = {
	TEGRA_PIN_DIRECTDC1_IN_PQ1,
};

enum tegra_mux_dt {
	TEGRA_MUX_RSVD0,
	TEGRA_MUX_RSVD1,
	TEGRA_MUX_RSVD2,
	TEGRA_MUX_RSVD3,
	TEGRA_MUX_TOUCH,
	TEGRA_MUX_UARTC,
	TEGRA_MUX_I2C8,
	TEGRA_MUX_UARTG,
	TEGRA_MUX_SPI2,
	TEGRA_MUX_GP,
	TEGRA_MUX_DCA,
	TEGRA_MUX_WDT,
	TEGRA_MUX_I2C2,
	TEGRA_MUX_CAN1,
	TEGRA_MUX_CAN0,
	TEGRA_MUX_DMIC3,
	TEGRA_MUX_DMIC5,
	TEGRA_MUX_GPIO,
	TEGRA_MUX_DSPK1,
	TEGRA_MUX_DSPK0,
	TEGRA_MUX_SPDIF,
	TEGRA_MUX_AUD,
	TEGRA_MUX_I2S1,
	TEGRA_MUX_DMIC1,
	TEGRA_MUX_DMIC2,
	TEGRA_MUX_I2S3,
	TEGRA_MUX_DMIC4,
	TEGRA_MUX_I2S4,
	TEGRA_MUX_EXTPERIPH2,
	TEGRA_MUX_EXTPERIPH1,
	TEGRA_MUX_I2C3,
	TEGRA_MUX_VGP1,
	TEGRA_MUX_VGP2,
	TEGRA_MUX_VGP3,
	TEGRA_MUX_VGP4,
	TEGRA_MUX_VGP5,
	TEGRA_MUX_VGP6,
	TEGRA_MUX_EXTPERIPH3,
	TEGRA_MUX_EXTPERIPH4,
	TEGRA_MUX_SPI4,
	TEGRA_MUX_I2S2,
	TEGRA_MUX_UARTD,
	TEGRA_MUX_I2C1,
	TEGRA_MUX_UARTA,
	TEGRA_MUX_DIRECTDC1,
	TEGRA_MUX_DIRECTDC,
	TEGRA_MUX_IQC0,
	TEGRA_MUX_IQC1,
	TEGRA_MUX_I2S6,
	TEGRA_MUX_DTV,
	TEGRA_MUX_UARTF,
	TEGRA_MUX_SDMMC3,
	TEGRA_MUX_SDMMC1,
	TEGRA_MUX_DP,
	TEGRA_MUX_HDMI,
	TEGRA_MUX_PE2,
	TEGRA_MUX_SATA,
	TEGRA_MUX_PE,
	TEGRA_MUX_PE1,
	TEGRA_MUX_PE0,
	TEGRA_MUX_SOC,
	TEGRA_MUX_EQOS,
	TEGRA_MUX_SDMMC2,
	TEGRA_MUX_QSPI,
	TEGRA_MUX_SCE,
	TEGRA_MUX_I2C5,
	TEGRA_MUX_DISPLAYA,
	TEGRA_MUX_DISPLAYB,
	TEGRA_MUX_DCC,
	TEGRA_MUX_SPI1,
	TEGRA_MUX_UARTB,
	TEGRA_MUX_UARTE,
	TEGRA_MUX_SPI3,
	TEGRA_MUX_NV,
	TEGRA_MUX_CCLA,
	TEGRA_MUX_I2C7,
	TEGRA_MUX_I2C9,
	TEGRA_MUX_I2S5,
	TEGRA_MUX_USB,
	TEGRA_MUX_UFS0,
};

static const char * const rsvd0_groups[] = {
	"gpio_sen0_pv0",
	"gpio_sen5_pv5",
	"gpio_sen6_pv6",
	"gpio_sen7_pv7",
	"gpio_sen8_pee0",
	"gpio_sen9_pee1",
	"can_gpio7_paa7",
	"can_gpio0_paa0",
	"can_gpio1_paa1",
	"can_gpio3_paa3",
	"can_gpio4_paa4",
	"can_gpio5_paa5",
	"can_gpio6_paa6",
	"gpio_aud3_pk0",
	"gpio_aud2_pj7",
	"gpio_aud1_pj6",
	"gpio_aud0_pj5",
	"gpio_cam7_pn6",
	"gpio_wan4_pc0",
	"gpio_wan3_pb6",
	"gpio_wan2_pb5",
	"gpio_wan1_pb4",
	"gpio_pq0_pi0",
	"gpio_pq1_pi1",
	"gpio_pq2_pi2",
	"gpio_pq3_pi3",
	"gpio_pq4_pi4",
	"gpio_pq5_pi5",
	"gpio_pq6_pi6",
	"gpio_pq7_pi7",
	"gpio_edp2_pp5",
	"gpio_edp3_pp6",
	"gpio_edp0_pp3",
	"gpio_edp1_pp4",
	"sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_dqs",
	"sdmmc4_dat7",
	"sdmmc4_dat6",
	"sdmmc4_dat5",
	"sdmmc4_dat4",
	"sdmmc4_dat3",
	"sdmmc4_dat2",
	"sdmmc4_dat1",
	"sdmmc4_dat0",
	"gpio_sw1_pff1",
	"gpio_sw2_pff2",
	"gpio_sw3_pff3",
	"gpio_sw4_pff4",
	"shutdown",
	"power_on_pff0",
	"gpio_dis0_pu0",
	"gpio_dis1_pu1",
	"gpio_dis2_pu2",
	"gpio_dis3_pu3",
	"gpio_dis4_pu4",
	"gpio_dis5_pu5",
	"gpio_wan8_ph3",
	"gpio_wan7_ph2",
	"gpio_wan6_ph1",
	"gpio_wan5_ph0",
	"gpio_mdm1_py0",
	"gpio_mdm2_py1",
	"gpio_mdm3_py2",
	"gpio_mdm4_py3",
	"gpio_mdm5_py4",
	"gpio_mdm7_py6",
	"bcpu_pwr_req_ph4",
	"mcpu_pwr_req_ph5",
	"gpu_pwr_req_ph6",
};

static const char * const rsvd1_groups[] = {
	"touch_clk_pee2",
	"uart3_cts_pw5",
	"uart3_rts_pw4",
	"uart3_rx_pw3",
	"uart3_tx_pw2",
	"gen8_i2c_sda_pw1",
	"gen8_i2c_scl_pw0",
	"uart7_rx_pw7",
	"uart7_tx_pw6",
	"gpio_sen0_pv0",
	"gpio_sen1_pv1",
	"gpio_sen2_pv2",
	"gpio_sen3_pv3",
	"gpio_sen4_pv4",
	"gpio_sen5_pv5",
	"can1_dout_pz0",
	"can1_din_pz1",
	"can0_dout_pz2",
	"can0_din_pz3",
	"can_gpio2_paa2",
	"can_gpio3_paa3",
	"can_gpio4_paa4",
	"can_gpio5_paa5",
	"can_gpio6_paa6",
	"gpio_aud1_pj6",
	"gpio_aud0_pj5",
	"aud_mclk_pj4",
	"dap1_fs_pj3",
	"dap1_din_pj2",
	"dap1_dout_pj1",
	"dap1_sclk_pj0",
	"dap4_fs_pcc3",
	"dap4_din_pcc2",
	"dap4_dout_pcc1",
	"dap4_sclk_pcc0",
	"extperiph2_clk_po1",
	"extperiph1_clk_po0",
	"cam_i2c_sda_po3",
	"cam_i2c_scl_po2",
	"gpio_cam1_pn0",
	"dap2_din_pc3",
	"dap2_dout_pc2",
	"dap2_fs_pc4",
	"dap2_sclk_pc1",
	"uart4_cts_pb3",
	"uart4_rts_pb2",
	"uart4_rx_pb1",
	"uart4_tx_pb0",
	"gpio_wan4_pc0",
	"gpio_wan3_pb6",
	"gpio_wan2_pb5",
	"gpio_wan1_pb4",
	"gen1_i2c_scl_pc5",
	"gen1_i2c_sda_pc6",
	"uart1_cts_pt3",
	"uart1_rts_pt2",
	"uart1_rx_pt1",
	"uart1_tx_pt0",
	"directdc1_out3_pq5",
	"directdc1_out2_pq4",
	"directdc1_out1_pq3",
	"directdc1_out0_pq2",
	"directdc1_in_pq1",
	"directdc1_clk_pq0",
	"dp_aux_ch0_hpd_pp0",
	"dp_aux_ch1_hpd_pp1",
	"hdmi_cec_pp2",
	"pex_wake_n_pa2",
	"pex_l1_clkreq_n_pa4",
	"pex_l1_rst_n_pa3",
	"pex_l0_clkreq_n_pa1",
	"pex_l0_rst_n_pa0",
	"sdmmc1_clk_pd0",
	"sdmmc1_cmd_pd1",
	"sdmmc1_dat3_pd5",
	"sdmmc1_dat2_pd4",
	"sdmmc1_dat1_pd3",
	"sdmmc1_dat0_pd2",
	"eqos_mdc_pf5",
	"sdmmc3_dat3_pg5",
	"sdmmc3_dat2_pg4",
	"sdmmc3_dat1_pg3",
	"sdmmc3_dat0_pg2",
	"sdmmc3_comp",
	"sdmmc3_cmd_pg1",
	"sdmmc3_clk_pg0",
	"sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_dqs",
	"sdmmc4_dat7",
	"sdmmc4_dat6",
	"sdmmc4_dat5",
	"sdmmc4_dat4",
	"sdmmc4_dat3",
	"sdmmc4_dat2",
	"sdmmc4_dat1",
	"sdmmc4_dat0",
	"qspi_io3_pr4",
	"qspi_io2_pr3",
	"qspi_io1_pr2",
	"qspi_io0_pr1",
	"qspi_sck_pr0",
	"qspi_cs_n_pr5",
	"qspi_comp",
	"gpio_sw1_pff1",
	"gpio_sw2_pff2",
	"gpio_sw3_pff3",
	"gpio_sw4_pff4",
	"shutdown",
	"safe_state_ps3",
	"vcomp_alert_ps4",
	"batt_oc_ps2",
	"power_on_pff0",
	"pwr_i2c_scl_ps0",
	"pwr_i2c_sda_ps1",
	"gpio_dis1_pu1",
	"gpio_dis3_pu3",
	"gpio_wan8_ph3",
	"gpio_wan7_ph2",
	"gpio_wan6_ph1",
	"gpio_wan5_ph0",
	"uart2_tx_px0",
	"uart2_rx_px1",
	"uart2_rts_px2",
	"uart2_cts_px3",
	"gpio_mdm1_py0",
	"gpio_mdm2_py1",
	"gpio_mdm3_py2",
	"gpio_mdm6_py5",
	"gpio_mdm7_py6",
	"bcpu_pwr_req_ph4",
	"mcpu_pwr_req_ph5",
	"gpu_pwr_req_ph6",
	"usb_vbus_en0_pl4",
	"usb_vbus_en1_pl5",
	"gp_pwm7_pl7",
	"gp_pwm6_pl6",
	"ufs0_rst_pbb1",
	"ufs0_ref_clk_pbb0",
};

static const char * const rsvd2_groups[] = {
	"touch_clk_pee2",
	"uart3_cts_pw5",
	"uart3_rts_pw4",
	"uart3_rx_pw3",
	"uart3_tx_pw2",
	"gen8_i2c_sda_pw1",
	"gen8_i2c_scl_pw0",
	"uart7_rx_pw7",
	"uart7_tx_pw6",
	"gpio_sen0_pv0",
	"gpio_sen1_pv1",
	"gpio_sen2_pv2",
	"gpio_sen3_pv3",
	"gpio_sen4_pv4",
	"gpio_sen5_pv5",
	"gpio_sen6_pv6",
	"gpio_sen7_pv7",
	"gpio_sen8_pee0",
	"gpio_sen9_pee1",
	"can_gpio7_paa7",
	"can1_dout_pz0",
	"can1_din_pz1",
	"can0_dout_pz2",
	"can0_din_pz3",
	"can_gpio2_paa2",
	"can_gpio3_paa3",
	"can_gpio4_paa4",
	"can_gpio5_paa5",
	"can_gpio6_paa6",
	"gpio_aud1_pj6",
	"gpio_aud0_pj5",
	"aud_mclk_pj4",
	"dap1_fs_pj3",
	"dap1_din_pj2",
	"dap1_dout_pj1",
	"dap1_sclk_pj0",
	"dmic1_clk_pm1",
	"dmic1_dat_pm0",
	"dmic2_dat_pm2",
	"dmic2_clk_pm3",
	"dmic4_dat_pm4",
	"dmic4_clk_pm5",
	"dap4_fs_pcc3",
	"dap4_din_pcc2",
	"dap4_dout_pcc1",
	"dap4_sclk_pcc0",
	"extperiph2_clk_po1",
	"extperiph1_clk_po0",
	"cam_i2c_sda_po3",
	"cam_i2c_scl_po2",
	"gpio_cam1_pn0",
	"gpio_cam2_pn1",
	"gpio_cam3_pn2",
	"gpio_cam4_pn3",
	"gpio_cam5_pn4",
	"gpio_cam6_pn5",
	"gpio_cam7_pn6",
	"dap2_din_pc3",
	"dap2_dout_pc2",
	"dap2_fs_pc4",
	"dap2_sclk_pc1",
	"uart4_cts_pb3",
	"uart4_rts_pb2",
	"uart4_rx_pb1",
	"uart4_tx_pb0",
	"gpio_wan4_pc0",
	"gpio_wan3_pb6",
	"gpio_wan2_pb5",
	"gpio_wan1_pb4",
	"gen1_i2c_scl_pc5",
	"gen1_i2c_sda_pc6",
	"uart1_cts_pt3",
	"uart1_rts_pt2",
	"uart1_rx_pt1",
	"uart1_tx_pt0",
	"directdc1_out3_pq5",
	"directdc1_out2_pq4",
	"directdc1_out1_pq3",
	"directdc1_out0_pq2",
	"directdc1_in_pq1",
	"directdc1_clk_pq0",
	"dp_aux_ch0_hpd_pp0",
	"dp_aux_ch1_hpd_pp1",
	"hdmi_cec_pp2",
	"pex_wake_n_pa2",
	"pex_l1_clkreq_n_pa4",
	"pex_l1_rst_n_pa3",
	"pex_l0_clkreq_n_pa1",
	"pex_l0_rst_n_pa0",
	"sdmmc1_clk_pd0",
	"sdmmc1_cmd_pd1",
	"sdmmc1_dat3_pd5",
	"sdmmc1_dat2_pd4",
	"sdmmc1_dat1_pd3",
	"sdmmc1_dat0_pd2",
	"eqos_td3_pe4",
	"eqos_td2_pe3",
	"eqos_td1_pe2",
	"eqos_td0_pe1",
	"eqos_rd3_pf1",
	"eqos_rd2_pf0",
	"eqos_rd1_pe7",
	"eqos_mdio_pf4",
	"eqos_rd0_pe6",
	"eqos_mdc_pf5",
	"eqos_comp",
	"eqos_txc_pe0",
	"eqos_rxc_pf3",
	"eqos_tx_ctl_pe5",
	"eqos_rx_ctl_pf2",
	"sdmmc3_dat3_pg5",
	"sdmmc3_dat2_pg4",
	"sdmmc3_dat1_pg3",
	"sdmmc3_dat0_pg2",
	"sdmmc3_comp",
	"sdmmc3_cmd_pg1",
	"sdmmc3_clk_pg0",
	"sdmmc4_clk_pcc4",
	"sdmmc4_cmd_pt7",
	"sdmmc4_dqs",
	"sdmmc4_dat7",
	"sdmmc4_dat6",
	"sdmmc4_dat5",
	"sdmmc4_dat4",
	"sdmmc4_dat3",
	"sdmmc4_dat2",
	"sdmmc4_dat1",
	"sdmmc4_dat0",
	"qspi_io3_pr4",
	"qspi_io2_pr3",
	"qspi_io1_pr2",
	"qspi_io0_pr1",
	"qspi_sck_pr0",
	"qspi_cs_n_pr5",
	"qspi_comp",
	"gpio_sw1_pff1",
	"gpio_sw2_pff2",
	"gpio_sw3_pff3",
	"gpio_sw4_pff4",
	"shutdown",
	"safe_state_ps3",
	"vcomp_alert_ps4",
	"batt_oc_ps2",
	"power_on_pff0",
	"pwr_i2c_scl_ps0",
	"pwr_i2c_sda_ps1",
	"gpio_dis0_pu0",
	"gpio_dis2_pu2",
	"gpio_dis4_pu4",
	"uart2_tx_px0",
	"uart2_rx_px1",
	"uart2_rts_px2",
	"uart2_cts_px3",
	"uart5_rts_px6",
	"uart5_cts_px7",
	"gpio_mdm1_py0",
	"gpio_mdm2_py1",
	"gpio_mdm3_py2",
	"gpio_mdm5_py4",
	"gpio_mdm6_py5",
	"gpio_mdm7_py6",
	"bcpu_pwr_req_ph4",
	"mcpu_pwr_req_ph5",
	"gpu_pwr_req_ph6",
	"gen7_i2c_scl_pl0",
	"gen7_i2c_sda_pl1",
	"gen9_i2c_sda_pl3",
	"gen9_i2c_scl_pl2",
	"usb_vbus_en0_pl4",
	"usb_vbus_en1_pl5",
	"gp_pwm7_pl7",
	"gp_pwm6_pl6",
	"ufs0_rst_pbb1",
	"ufs0_ref_clk_pbb0",
};

static const char * const rsvd3_groups[] = {
	"touch_clk_pee2",
	"uart3_cts_pw5",
	"uart3_rts_pw4",
	"uart3_rx_pw3",
	"uart3_tx_pw2",
	"gen8_i2c_sda_pw1",
	"gen8_i2c_scl_pw0",
	"uart7_rx_pw7",
	"uart7_tx_pw6",
	"gpio_sen0_pv0",
	"gpio_sen1_pv1",
	"gpio_sen2_pv2",
	"gpio_sen3_pv3",
	"gpio_sen4_pv4",
	"gpio_sen5_pv5",
	"gpio_sen6_pv6",
	"gpio_sen7_pv7",
	"gpio_sen8_pee0",
	"gpio_sen9_pee1",
	"can_gpio7_paa7",
	"can1_dout_pz0",
	"can1_din_pz1",
	"can0_dout_pz2",
	"can0_din_pz3",
	"can_gpio0_paa0",
	"can_gpio1_paa1",
	"can_gpio2_paa2",
	"can_gpio3_paa3",
	"can_gpio4_paa4",
	"can_gpio5_paa5",
	"can_gpio6_paa6",
	"gpio_aud3_pk0",
	"gpio_aud2_pj7",
	"gpio_aud1_pj6",
	"gpio_aud0_pj5",
	"aud_mclk_pj4",
	"dap1_fs_pj3",
	"dap1_din_pj2",
	"dap1_dout_pj1",
	"dap1_sclk_pj0",
	"dmic1_clk_pm1",
	"dmic1_dat_pm0",
	"dmic2_dat_pm2",
	"dmic2_clk_pm3",
	"dmic4_dat_pm4",
	"dmic4_clk_pm5",
	"dap4_fs_pcc3",
	"dap4_din_pcc2",
	"dap4_dout_pcc1",
	"dap4_sclk_pcc0",
	"extperiph2_clk_po1",
	"extperiph1_clk_po0",
	"cam_i2c_sda_po3",
	"cam_i2c_scl_po2",
	"gpio_cam1_pn0",
	"gpio_cam2_pn1",
	"gpio_cam3_pn2",
	"gpio_cam4_pn3",
	"gpio_cam5_pn4",
	"gpio_cam6_pn5",
	"gpio_cam7_pn6",
	"dap2_din_pc3",
	"dap2_dout_pc2",
	"dap2_fs_pc4",
	"dap2_sclk_pc1",
	"uart4_cts_pb3",
	"uart4_rts_pb2",
	"uart4_rx_pb1",
	"uart4_tx_pb0",
	"gpio_wan4_pc0",
	"gpio_wan3_pb6",
	"gpio_wan2_pb5",
	"gpio_wan1_pb4",
	"gen1_i2c_scl_pc5",
	"gen1_i2c_sda_pc6",
	"uart1_cts_pt3",
	"uart1_rts_pt2",
	"uart1_rx_pt1",
	"uart1_tx_pt0",
	"directdc1_out3_pq5",
	"directdc1_out2_pq4",
	"directdc1_out1_pq3",
	"directdc1_out0_pq2",
	"directdc1_in_pq1",
	"directdc1_clk_pq0",
	"gpio_pq0_pi0",
	"gpio_pq1_pi1",
	"gpio_pq2_pi2",
	"gpio_pq3_pi3",
	"gpio_pq4_pi4",
	"gpio_pq5_pi5",
	"gpio_pq6_pi6",
	"gpio_pq7_pi7",
	"gpio_edp2_pp5",
	"gpio_edp3_pp6",
	"gpio_edp0_pp3",
	"gpio_edp1_pp4",
	"dp_aux_ch0_hpd_pp0",
	"dp_aux_ch1_hpd_pp1",
	"hdmi_cec_pp2",
	"pex_l2_clkreq_n",
	"pex_wake_n_pa2",
	"pex_l1_clkreq_n_pa4",
	"pex_l1_rst_n_pa3",
	"pex_l0_clkreq_n_pa1",
	"pex_l0_rst_n_pa0",
	"pex_l2_rst_n_pa5",
	"sdmmc1_clk_pd0",
	"sdmmc1_cmd_pd1",
	"sdmmc1_dat3_pd5",
	"sdmmc1_dat2_pd4",
	"sdmmc1_dat1_pd3",
	"sdmmc1_dat0_pd2",
	"eqos_td3_pe4",
	"eqos_td2_pe3",
	"eqos_td1_pe2",
	"eqos_td0_pe1",
	"eqos_rd3_pf1",
	"eqos_rd2_pf0",
	"eqos_rd1_pe7",
	"eqos_mdio_pf4",
	"eqos_rd0_pe6",
	"eqos_mdc_pf5",
	"eqos_comp",
	"eqos_txc_pe0",
	"eqos_rxc_pf3",
	"eqos_tx_ctl_pe5",
	"eqos_rx_ctl_pf2",
	"sdmmc3_dat3_pg5",
	"sdmmc3_dat2_pg4",


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