1560 files changed, 82275 insertions, 23310 deletions

diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h
index 2b41e47b7d80..427cff1a3f83 100644
--- a/include/acpi/acconfig.h
+++ b/include/acpi/acconfig.h
@@ -44,7 +44,6 @@
 #ifndef _ACCONFIG_H
 #define _ACCONFIG_H
 
-
 /******************************************************************************
  *
  * Configuration options
@@ -64,7 +63,7 @@
 
 /* Version string */
 
-#define ACPI_CA_VERSION                 0x20050309
+#define ACPI_CA_VERSION                 0x20050902
 
 /*
  * OS name, used for the _OS object.  The _OS object is essentially obsolete,
@@ -78,11 +77,10 @@
 
 /* Maximum objects in the various object caches */
 
-#define ACPI_MAX_STATE_CACHE_DEPTH      64          /* State objects */
-#define ACPI_MAX_PARSE_CACHE_DEPTH      96          /* Parse tree objects */
-#define ACPI_MAX_EXTPARSE_CACHE_DEPTH   64          /* Parse tree objects */
-#define ACPI_MAX_OBJECT_CACHE_DEPTH     64          /* Interpreter operand objects */
-#define ACPI_MAX_WALK_CACHE_DEPTH       4           /* Objects for parse tree walks */
+#define ACPI_MAX_STATE_CACHE_DEPTH      96      /* State objects */
+#define ACPI_MAX_PARSE_CACHE_DEPTH      96      /* Parse tree objects */
+#define ACPI_MAX_EXTPARSE_CACHE_DEPTH   96      /* Parse tree objects */
+#define ACPI_MAX_OBJECT_CACHE_DEPTH     96      /* Interpreter operand objects */
 
 /*
  * Should the subystem abort the loading of an ACPI table if the
@@ -90,7 +88,6 @@
  */
 #define ACPI_CHECKSUM_ABORT             FALSE
 
-
 /******************************************************************************
  *
  * Subsystem Constants
@@ -104,7 +101,7 @@
 /* String size constants */
 
 #define ACPI_MAX_STRING_LENGTH          512
-#define ACPI_PATHNAME_MAX               256         /* A full namespace pathname */
+#define ACPI_PATHNAME_MAX               256     /* A full namespace pathname */
 
 /* Maximum count for a semaphore object */
 
@@ -118,7 +115,6 @@
 
 #define ACPI_SYSMEM_REGION_WINDOW_SIZE  4096
 
-
 /******************************************************************************
  *
  * ACPI Specification constants (Do not change unless the specification changes)
@@ -130,9 +126,8 @@
 #define ACPI_MAX_GPE_BLOCKS             2
 #define ACPI_GPE_REGISTER_WIDTH         8
 
-/*
- * Method info (in WALK_STATE), containing local variables and argumetns
- */
+/* Method info (in WALK_STATE), containing local variables and argumetns */
+
 #define ACPI_METHOD_NUM_LOCALS          8
 #define ACPI_METHOD_MAX_LOCAL           7
 
@@ -157,15 +152,15 @@
 /* Names within the namespace are 4 bytes long */
 
 #define ACPI_NAME_SIZE                  4
-#define ACPI_PATH_SEGMENT_LENGTH        5           /* 4 chars for name + 1 char for separator */
+#define ACPI_PATH_SEGMENT_LENGTH        5       /* 4 chars for name + 1 char for separator */
 #define ACPI_PATH_SEPARATOR             '.'
 
 /* Constants used in searching for the RSDP in low memory */
 
-#define ACPI_EBDA_PTR_LOCATION          0x0000040E     /* Physical Address */
+#define ACPI_EBDA_PTR_LOCATION          0x0000040E      /* Physical Address */
 #define ACPI_EBDA_PTR_LENGTH            2
 #define ACPI_EBDA_WINDOW_SIZE           1024
-#define ACPI_HI_RSDP_WINDOW_BASE        0x000E0000     /* Physical Address */
+#define ACPI_HI_RSDP_WINDOW_BASE        0x000E0000      /* Physical Address */
 #define ACPI_HI_RSDP_WINDOW_SIZE        0x00020000
 #define ACPI_RSDP_SCAN_STEP             16
 
@@ -200,18 +195,15 @@
 
 #define ACPI_NUM_OSI_STRINGS            10
 
-
 /******************************************************************************
  *
  * ACPI AML Debugger
  *
  *****************************************************************************/
 
-#define ACPI_DEBUGGER_MAX_ARGS          8  /* Must be max method args + 1 */
+#define ACPI_DEBUGGER_MAX_ARGS          8       /* Must be max method args + 1 */
 
 #define ACPI_DEBUGGER_COMMAND_PROMPT    '-'
 #define ACPI_DEBUGGER_EXECUTE_PROMPT    '%'
 
-
-#endif /* _ACCONFIG_H */
-
+#endif                          /* _ACCONFIG_H */
diff --git a/include/acpi/acdebug.h b/include/acpi/acdebug.h
index 223b2a506e49..70ce3b4d006e 100644
--- a/include/acpi/acdebug.h
+++ b/include/acpi/acdebug.h
@@ -44,429 +44,174 @@
 #ifndef __ACDEBUG_H__
 #define __ACDEBUG_H__
 
-
 #define ACPI_DEBUG_BUFFER_SIZE  4196
 
-struct command_info
-{
-        char                            *name;          /* Command Name */
-        u8                              min_args;       /* Minimum arguments required */
+struct command_info {
+        char *name;             /* Command Name */
+        u8 min_args;            /* Minimum arguments required */
 };
 
-
-struct argument_info
-{
-        char                            *name;          /* Argument Name */
+struct argument_info {
+        char *name;             /* Argument Name */
 };
 
-
 #define PARAM_LIST(pl)                  pl
-
 #define DBTEST_OUTPUT_LEVEL(lvl)        if (acpi_gbl_db_opt_verbose)
-
 #define VERBOSE_PRINT(fp)               DBTEST_OUTPUT_LEVEL(lvl) {\
                           acpi_os_printf PARAM_LIST(fp);}
 
 #define EX_NO_SINGLE_STEP               1
 #define EX_SINGLE_STEP                  2
 
-
-/* Prototypes */
-
-
 /*
  * dbxface - external debugger interfaces
  */
+acpi_status acpi_db_initialize(void);
 
-acpi_status
-acpi_db_initialize (
-        void);
-
-void
-acpi_db_terminate (
-        void);
+void acpi_db_terminate(void);
 
 acpi_status
-acpi_db_single_step (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        u32                             op_type);
-
-acpi_status
-acpi_db_start_command (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
-
-void
-acpi_db_method_end (
-        struct acpi_walk_state          *walk_state);
-
+acpi_db_single_step(struct acpi_walk_state *walk_state,
+                    union acpi_parse_object *op, u32 op_type);
 
 /*
  * dbcmds - debug commands and output routines
  */
+acpi_status acpi_db_disassemble_method(char *name);
 
-acpi_status
-acpi_db_disassemble_method (
-        char                            *name);
+void acpi_db_display_table_info(char *table_arg);
 
-void
-acpi_db_display_table_info (
-        char                            *table_arg);
+void acpi_db_unload_acpi_table(char *table_arg, char *instance_arg);
 
 void
-acpi_db_unload_acpi_table (
-        char                            *table_arg,
-        char                            *instance_arg);
+acpi_db_set_method_breakpoint(char *location,
+                              struct acpi_walk_state *walk_state,
+                              union acpi_parse_object *op);
 
-void
-acpi_db_set_method_breakpoint (
-        char                            *location,
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+void acpi_db_set_method_call_breakpoint(union acpi_parse_object *op);
 
-void
-acpi_db_set_method_call_breakpoint (
-        union acpi_parse_object         *op);
+void acpi_db_get_bus_info(void);
 
-void
-acpi_db_disassemble_aml (
-        char                            *statements,
-        union acpi_parse_object         *op);
-
-void
-acpi_db_dump_namespace (
-        char                            *start_arg,
-        char                            *depth_arg);
-
-void
-acpi_db_dump_namespace_by_owner (
-        char                            *owner_arg,
-        char                            *depth_arg);
-
-void
-acpi_db_send_notify (
-        char                            *name,
-        u32                             value);
+void acpi_db_disassemble_aml(char *statements, union acpi_parse_object *op);
 
-void
-acpi_db_set_method_data (
-        char                            *type_arg,
-        char                            *index_arg,
-        char                            *value_arg);
+void acpi_db_dump_namespace(char *start_arg, char *depth_arg);
 
-acpi_status
-acpi_db_display_objects (
-        char                            *obj_type_arg,
-        char                            *display_count_arg);
+void acpi_db_dump_namespace_by_owner(char *owner_arg, char *depth_arg);
 
-acpi_status
-acpi_db_find_name_in_namespace (
-        char                            *name_arg);
+void acpi_db_send_notify(char *name, u32 value);
 
-void
-acpi_db_set_scope (
-        char                            *name);
+void acpi_db_set_method_data(char *type_arg, char *index_arg, char *value_arg);
 
 acpi_status
-acpi_db_sleep (
-        char                            *object_arg);
+acpi_db_display_objects(char *obj_type_arg, char *display_count_arg);
 
-void
-acpi_db_find_references (
-        char                            *object_arg);
-
-void
-acpi_db_display_locks (void);
+acpi_status acpi_db_find_name_in_namespace(char *name_arg);
 
+void acpi_db_set_scope(char *name);
 
-void
-acpi_db_display_resources (
-        char                            *object_arg);
+acpi_status acpi_db_sleep(char *object_arg);
 
-void
-acpi_db_display_gpes (void);
+void acpi_db_find_references(char *object_arg);
 
-void
-acpi_db_check_integrity (
-        void);
+void acpi_db_display_locks(void);
 
-acpi_status
-acpi_db_integrity_walk (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
+void acpi_db_display_resources(char *object_arg);
 
-acpi_status
-acpi_db_walk_and_match_name (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
+void acpi_db_display_gpes(void);
 
-acpi_status
-acpi_db_walk_for_references (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
+void acpi_db_check_integrity(void);
 
-acpi_status
-acpi_db_walk_for_specific_objects (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
-
-void
-acpi_db_generate_gpe (
-        char                            *gpe_arg,
-        char                            *block_arg);
+void acpi_db_generate_gpe(char *gpe_arg, char *block_arg);
 
 /*
  * dbdisply - debug display commands
  */
+void acpi_db_display_method_info(union acpi_parse_object *op);
 
-void
-acpi_db_display_method_info (
-        union acpi_parse_object         *op);
+void acpi_db_decode_and_display_object(char *target, char *output_type);
 
 void
-acpi_db_decode_and_display_object (
-        char                            *target,
-        char                            *output_type);
+acpi_db_display_result_object(union acpi_operand_object *obj_desc,
+                              struct acpi_walk_state *walk_state);
 
-void
-acpi_db_display_result_object (
-        union acpi_operand_object       *obj_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_db_display_all_methods(char *display_count_arg);
 
-acpi_status
-acpi_db_display_all_methods (
-        char                            *display_count_arg);
+void acpi_db_display_arguments(void);
 
-void
-acpi_db_display_arguments (
-        void);
+void acpi_db_display_locals(void);
 
-void
-acpi_db_display_locals (
-        void);
+void acpi_db_display_results(void);
 
-void
-acpi_db_display_results (
-        void);
-
-void
-acpi_db_display_calling_tree (
-        void);
+void acpi_db_display_calling_tree(void);
 
-void
-acpi_db_display_object_type (
-        char                            *object_arg);
-
-void
-acpi_db_display_argument_object (
-        union acpi_operand_object       *obj_desc,
-        struct acpi_walk_state          *walk_state);
+void acpi_db_display_object_type(char *object_arg);
 
 void
-acpi_db_dump_parser_descriptor (
-        union acpi_parse_object         *op);
-
-void *
-acpi_db_get_pointer (
-        void                            *target);
-
+acpi_db_display_argument_object(union acpi_operand_object *obj_desc,
+                                struct acpi_walk_state *walk_state);
 
 /*
  * dbexec - debugger control method execution
  */
+void acpi_db_execute(char *name, char **args, u32 flags);
 
 void
-acpi_db_execute (
-        char                            *name,
-        char                            **args,
-        u32                             flags);
-
-void
-acpi_db_create_execution_threads (
-        char                            *num_threads_arg,
-        char                            *num_loops_arg,
-        char                            *method_name_arg);
-
-acpi_status
-acpi_db_execute_method (
-        struct acpi_db_method_info      *info,
-        struct acpi_buffer              *return_obj);
-
-void
-acpi_db_execute_setup (
-        struct acpi_db_method_info      *info);
-
-u32
-acpi_db_get_outstanding_allocations (
-        void);
-
-void ACPI_SYSTEM_XFACE
-acpi_db_method_thread (
-        void                            *context);
-
-acpi_status
-acpi_db_execution_walk (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
-
+acpi_db_create_execution_threads(char *num_threads_arg,
+                                 char *num_loops_arg, char *method_name_arg);
 
 /*
  * dbfileio - Debugger file I/O commands
  */
-
 acpi_object_type
-acpi_db_match_argument (
-        char                            *user_argument,
-        struct argument_info            *arguments);
+acpi_db_match_argument(char *user_argument, struct argument_info *arguments);
 
-acpi_status
-ae_local_load_table (
-        struct acpi_table_header        *table_ptr);
+void acpi_db_close_debug_file(void);
 
-void
-acpi_db_close_debug_file (
-        void);
+void acpi_db_open_debug_file(char *name);
 
-void
-acpi_db_open_debug_file (
-        char                            *name);
+acpi_status acpi_db_load_acpi_table(char *filename);
 
 acpi_status
-acpi_db_load_acpi_table (
-        char                            *filename);
+acpi_db_get_table_from_file(char *filename, struct acpi_table_header **table);
 
 acpi_status
-acpi_db_get_table_from_file (
-        char                            *filename,
-        struct acpi_table_header        **table);
-
-acpi_status
-acpi_db_read_table_from_file (
-        char                            *filename,
-        struct acpi_table_header        **table);
+acpi_db_read_table_from_file(char *filename, struct acpi_table_header **table);
 
 /*
  * dbhistry - debugger HISTORY command
  */
+void acpi_db_add_to_history(char *command_line);
 
-void
-acpi_db_add_to_history (
-        char                            *command_line);
-
-void
-acpi_db_display_history (void);
-
-char *
-acpi_db_get_from_history (
-        char                            *command_num_arg);
+void acpi_db_display_history(void);
 
+char *acpi_db_get_from_history(char *command_num_arg);
 
 /*
  * dbinput - user front-end to the AML debugger
  */
-
 acpi_status
-acpi_db_command_dispatch (
-        char                            *input_buffer,
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
-
-void ACPI_SYSTEM_XFACE
-acpi_db_execute_thread (
-        void                            *context);
-
-void
-acpi_db_display_help (
-        char                            *help_type);
-
-char *
-acpi_db_get_next_token (
-        char                            *string,
-        char                            **next);
-
-u32
-acpi_db_get_line (
-        char                            *input_buffer);
-
-u32
-acpi_db_match_command (
-        char                            *user_command);
-
-void
-acpi_db_single_thread (
-        void);
+acpi_db_command_dispatch(char *input_buffer,
+                         struct acpi_walk_state *walk_state,
+                         union acpi_parse_object *op);
 
+void ACPI_SYSTEM_XFACE acpi_db_execute_thread(void *context);
 
 /*
  * dbstats - Generation and display of ACPI table statistics
  */
+void acpi_db_generate_statistics(union acpi_parse_object *root, u8 is_method);
 
-void
-acpi_db_generate_statistics (
-        union acpi_parse_object         *root,
-        u8                              is_method);
-
-
-acpi_status
-acpi_db_display_statistics (
-        char                            *type_arg);
-
-acpi_status
-acpi_db_classify_one_object (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
-
-void
-acpi_db_count_namespace_objects (
-        void);
-
-void
-acpi_db_enumerate_object (
-        union acpi_operand_object       *obj_desc);
-
+acpi_status acpi_db_display_statistics(char *type_arg);
 
 /*
  * dbutils - AML debugger utilities
  */
+void acpi_db_set_output_destination(u32 where);
 
-void
-acpi_db_set_output_destination (
-        u32                             where);
-
-void
-acpi_db_dump_buffer (
-        u32                             address);
-
-void
-acpi_db_dump_object (
-        union acpi_object               *obj_desc,
-        u32                             level);
-
-void
-acpi_db_prep_namestring (
-        char                            *name);
-
-
-acpi_status
-acpi_db_second_pass_parse (
-        union acpi_parse_object         *root);
+void acpi_db_dump_external_object(union acpi_object *obj_desc, u32 level);
 
-struct acpi_namespace_node *
-acpi_db_local_ns_lookup (
-        char                            *name);
+void acpi_db_prep_namestring(char *name);
 
+struct acpi_namespace_node *acpi_db_local_ns_lookup(char *name);
 
-#endif  /* __ACDEBUG_H__ */
+#endif                          /* __ACDEBUG_H__ */
diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h
index 26d907eae6fe..3d96dcb1bb4b 100644
--- a/include/acpi/acdisasm.h
+++ b/include/acpi/acdisasm.h
@@ -46,383 +46,219 @@
 
 #include "amlresrc.h"
 
-
 #define BLOCK_NONE              0
 #define BLOCK_PAREN             1
 #define BLOCK_BRACE             2
 #define BLOCK_COMMA_LIST        4
 
-struct acpi_external_list
-{
-        char                                *path;
-        struct acpi_external_list           *next;
+struct acpi_external_list {
+        char *path;
+        struct acpi_external_list *next;
 };
 
-extern struct acpi_external_list        *acpi_gbl_external_list;
-extern const char                       *acpi_gbl_io_decode[2];
-extern const char                       *acpi_gbl_word_decode[4];
-extern const char                       *acpi_gbl_consume_decode[2];
-extern const char                       *acpi_gbl_min_decode[2];
-extern const char                       *acpi_gbl_max_decode[2];
-extern const char                       *acpi_gbl_DECdecode[2];
-extern const char                       *acpi_gbl_RNGdecode[4];
-extern const char                       *acpi_gbl_MEMdecode[4];
-extern const char                       *acpi_gbl_RWdecode[2];
-extern const char                       *acpi_gbl_irq_decode[2];
-extern const char                       *acpi_gbl_HEdecode[2];
-extern const char                       *acpi_gbl_LLdecode[2];
-extern const char                       *acpi_gbl_SHRdecode[2];
-extern const char                       *acpi_gbl_TYPdecode[4];
-extern const char                       *acpi_gbl_BMdecode[2];
-extern const char                       *acpi_gbl_SIZdecode[4];
-extern const char                       *acpi_gbl_TTPdecode[2];
-extern const char                       *acpi_gbl_MTPdecode[4];
-extern const char                       *acpi_gbl_TRSdecode[2];
-
-
-extern const char                       *acpi_gbl_lock_rule[ACPI_NUM_LOCK_RULES];
-extern const char                       *acpi_gbl_access_types[ACPI_NUM_ACCESS_TYPES];
-extern const char                       *acpi_gbl_update_rules[ACPI_NUM_UPDATE_RULES];
-extern const char                       *acpi_gbl_match_ops[ACPI_NUM_MATCH_OPS];
-
-
-struct acpi_op_walk_info
-{
-        u32                             level;
-        u32                             bit_offset;
+extern struct acpi_external_list *acpi_gbl_external_list;
+extern const char *acpi_gbl_io_decode[2];
+extern const char *acpi_gbl_word_decode[4];
+extern const char *acpi_gbl_consume_decode[2];
+extern const char *acpi_gbl_min_decode[2];
+extern const char *acpi_gbl_max_decode[2];
+extern const char *acpi_gbl_DECdecode[2];
+extern const char *acpi_gbl_RNGdecode[4];
+extern const char *acpi_gbl_MEMdecode[4];
+extern const char *acpi_gbl_RWdecode[2];
+extern const char *acpi_gbl_irq_decode[2];
+extern const char *acpi_gbl_HEdecode[2];
+extern const char *acpi_gbl_LLdecode[2];
+extern const char *acpi_gbl_SHRdecode[2];
+extern const char *acpi_gbl_TYPdecode[4];
+extern const char *acpi_gbl_BMdecode[2];
+extern const char *acpi_gbl_SIZdecode[4];
+extern const char *acpi_gbl_TTPdecode[2];
+extern const char *acpi_gbl_MTPdecode[4];
+extern const char *acpi_gbl_TRSdecode[2];
+
+extern const char *acpi_gbl_lock_rule[ACPI_NUM_LOCK_RULES];
+extern const char *acpi_gbl_access_types[ACPI_NUM_ACCESS_TYPES];
+extern const char *acpi_gbl_update_rules[ACPI_NUM_UPDATE_RULES];
+extern const char *acpi_gbl_match_ops[ACPI_NUM_MATCH_OPS];
+
+struct acpi_op_walk_info {
+        u32 level;
+        u32 bit_offset;
+        struct acpi_walk_state *walk_state;
 };
 
 typedef
-acpi_status (*asl_walk_callback) (
-        union acpi_parse_object             *op,
-        u32                                 level,
-        void                                *context);
-
+acpi_status(*asl_walk_callback) (union acpi_parse_object * op,
+                                 u32 level, void *context);
 
 /*
  * dmwalk
  */
-
 void
-acpi_dm_walk_parse_tree (
-        union acpi_parse_object         *op,
-        asl_walk_callback               descending_callback,
-        asl_walk_callback               ascending_callback,
-        void                            *context);
-
-acpi_status
-acpi_dm_descending_op (
-        union acpi_parse_object         *op,
-        u32                             level,
-        void                            *context);
-
-acpi_status
-acpi_dm_ascending_op (
-        union acpi_parse_object         *op,
-        u32                             level,
-        void                            *context);
-
+acpi_dm_disassemble(struct acpi_walk_state *walk_state,
+                    union acpi_parse_object *origin, u32 num_opcodes);
 
 /*
  * dmopcode
  */
-
 void
-acpi_dm_validate_name (
-        char                            *name,
-        union acpi_parse_object         *op);
+acpi_dm_disassemble_one_op(struct acpi_walk_state *walk_state,
+                           struct acpi_op_walk_info *info,
+                           union acpi_parse_object *op);
 
-u32
-acpi_dm_dump_name (
-        char                            *name);
+void acpi_dm_decode_internal_object(union acpi_operand_object *obj_desc);
 
-void
-acpi_dm_unicode (
-        union acpi_parse_object         *op);
+u32 acpi_dm_list_type(union acpi_parse_object *op);
 
-void
-acpi_dm_disassemble (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *origin,
-        u32                             num_opcodes);
+void acpi_dm_method_flags(union acpi_parse_object *op);
 
-void
-acpi_dm_namestring (
-        char                            *name);
+void acpi_dm_field_flags(union acpi_parse_object *op);
 
-void
-acpi_dm_display_path (
-        union acpi_parse_object         *op);
+void acpi_dm_address_space(u8 space_id);
 
-void
-acpi_dm_disassemble_one_op (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_op_walk_info        *info,
-        union acpi_parse_object         *op);
+void acpi_dm_region_flags(union acpi_parse_object *op);
 
-void
-acpi_dm_decode_internal_object (
-        union acpi_operand_object       *obj_desc);
+void acpi_dm_match_op(union acpi_parse_object *op);
 
-u32
-acpi_dm_block_type (
-        union acpi_parse_object         *op);
+u8 acpi_dm_comma_if_list_member(union acpi_parse_object *op);
 
-u32
-acpi_dm_list_type (
-        union acpi_parse_object         *op);
-
-acpi_status
-acpi_ps_display_object_pathname (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
-
-void
-acpi_dm_method_flags (
-        union acpi_parse_object         *op);
-
-void
-acpi_dm_field_flags (
-        union acpi_parse_object         *op);
-
-void
-acpi_dm_address_space (
-        u8                              space_id);
-
-void
-acpi_dm_region_flags (
-        union acpi_parse_object         *op);
-
-void
-acpi_dm_match_op (
-        union acpi_parse_object         *op);
-
-void
-acpi_dm_match_keyword (
-        union acpi_parse_object         *op);
+void acpi_dm_comma_if_field_member(union acpi_parse_object *op);
 
-u8
-acpi_dm_comma_if_list_member (
-        union acpi_parse_object         *op);
+/*
+ * dmnames
+ */
+u32 acpi_dm_dump_name(char *name);
 
-void
-acpi_dm_comma_if_field_member (
-        union acpi_parse_object         *op);
+acpi_status
+acpi_ps_display_object_pathname(struct acpi_walk_state *walk_state,
+                                union acpi_parse_object *op);
 
+void acpi_dm_namestring(char *name);
 
 /*
  * dmobject
  */
-
 void
-acpi_dm_decode_node (
-        struct acpi_namespace_node      *node);
+acpi_dm_display_internal_object(union acpi_operand_object *obj_desc,
+                                struct acpi_walk_state *walk_state);
 
-void
-acpi_dm_display_internal_object (
-        union acpi_operand_object       *obj_desc,
-        struct acpi_walk_state          *walk_state);
+void acpi_dm_display_arguments(struct acpi_walk_state *walk_state);
 
-void
-acpi_dm_display_arguments (
-        struct acpi_walk_state          *walk_state);
+void acpi_dm_display_locals(struct acpi_walk_state *walk_state);
 
 void
-acpi_dm_display_locals (
-        struct acpi_walk_state          *walk_state);
-
-void
-acpi_dm_dump_method_info (
-        acpi_status                     status,
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
-
+acpi_dm_dump_method_info(acpi_status status,
+                         struct acpi_walk_state *walk_state,
+                         union acpi_parse_object *op);
 
 /*
  * dmbuffer
  */
+void acpi_dm_disasm_byte_list(u32 level, u8 * byte_data, u32 byte_count);
 
 void
-acpi_is_eisa_id (
-        union acpi_parse_object         *op);
+acpi_dm_byte_list(struct acpi_op_walk_info *info, union acpi_parse_object *op);
 
-void
-acpi_dm_eisa_id (
-        u32                             encoded_id);
+void acpi_dm_is_eisa_id(union acpi_parse_object *op);
 
-u8
-acpi_dm_is_unicode_buffer (
-        union acpi_parse_object         *op);
+void acpi_dm_eisa_id(u32 encoded_id);
 
-u8
-acpi_dm_is_string_buffer (
-        union acpi_parse_object         *op);
+u8 acpi_dm_is_unicode_buffer(union acpi_parse_object *op);
 
+u8 acpi_dm_is_string_buffer(union acpi_parse_object *op);
 
 /*
  * dmresrc
  */
-
 void
-acpi_dm_disasm_byte_list (
-        u32                             level,
-        u8                              *byte_data,
-        u32                             byte_count);
+acpi_dm_resource_descriptor(struct acpi_op_walk_info *info,
+                            u8 * byte_data, u32 byte_count);
 
-void
-acpi_dm_byte_list (
-        struct acpi_op_walk_info        *info,
-        union acpi_parse_object         *op);
+u8 acpi_dm_is_resource_descriptor(union acpi_parse_object *op);
 
-void
-acpi_dm_resource_descriptor (
-        struct acpi_op_walk_info        *info,
-        u8                              *byte_data,
-        u32                             byte_count);
+void acpi_dm_indent(u32 level);
 
-u8
-acpi_dm_is_resource_descriptor (
-        union acpi_parse_object         *op);
+void acpi_dm_bit_list(u16 mask);
 
-void
-acpi_dm_indent (
-        u32                             level);
-
-void
-acpi_dm_bit_list (
-        u16                             mask);
-
-void
-acpi_dm_decode_attribute (
-        u8                              attribute);
+void acpi_dm_decode_attribute(u8 attribute);
 
 /*
  * dmresrcl
  */
-
-void
-acpi_dm_io_flags (
-                u8                          flags);
-
 void
-acpi_dm_memory_flags (
-        u8                              flags,
-        u8                              specific_flags);
+acpi_dm_word_descriptor(struct asl_word_address_desc *resource,
+                        u32 length, u32 level);
 
 void
-acpi_dm_word_descriptor (
-        struct asl_word_address_desc    *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_dword_descriptor(struct asl_dword_address_desc *resource,
+                         u32 length, u32 level);
 
 void
-acpi_dm_dword_descriptor (
-        struct asl_dword_address_desc   *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_extended_descriptor(struct asl_extended_address_desc *resource,
+                            u32 length, u32 level);
 
 void
-acpi_dm_extended_descriptor (
-        struct asl_extended_address_desc   *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_qword_descriptor(struct asl_qword_address_desc *resource,
+                         u32 length, u32 level);
 
 void
-acpi_dm_qword_descriptor (
-        struct asl_qword_address_desc   *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_memory24_descriptor(struct asl_memory_24_desc *resource,
+                            u32 length, u32 level);
 
 void
-acpi_dm_memory24_descriptor (
-        struct asl_memory_24_desc       *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_memory32_descriptor(struct asl_memory_32_desc *resource,
+                            u32 length, u32 level);
 
 void
-acpi_dm_memory32_descriptor (
-        struct asl_memory_32_desc       *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_fixed_mem32_descriptor(struct asl_fixed_memory_32_desc *resource,
+                               u32 length, u32 level);
 
 void
-acpi_dm_fixed_mem32_descriptor (
-        struct asl_fixed_memory_32_desc *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_generic_register_descriptor(struct asl_general_register_desc *resource,
+                                    u32 length, u32 level);
 
 void
-acpi_dm_generic_register_descriptor (
-        struct asl_general_register_desc *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_interrupt_descriptor(struct asl_extended_xrupt_desc *resource,
+                             u32 length, u32 level);
 
 void
-acpi_dm_interrupt_descriptor (
-        struct asl_extended_xrupt_desc *resource,
-        u32                             length,
-        u32                             level);
-
-void
-acpi_dm_vendor_large_descriptor (
-        struct asl_large_vendor_desc    *resource,
-        u32                             length,
-        u32                             level);
-
+acpi_dm_vendor_large_descriptor(struct asl_large_vendor_desc *resource,
+                                u32 length, u32 level);
 
 /*
  * dmresrcs
  */
-
 void
-acpi_dm_irq_descriptor (
-        struct asl_irq_format_desc      *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_irq_descriptor(struct asl_irq_format_desc *resource,
+                       u32 length, u32 level);
 
 void
-acpi_dm_dma_descriptor (
-        struct asl_dma_format_desc      *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_dma_descriptor(struct asl_dma_format_desc *resource,
+                       u32 length, u32 level);
 
 void
-acpi_dm_io_descriptor (
-        struct asl_io_port_desc         *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_io_descriptor(struct asl_io_port_desc *resource, u32 length, u32 level);
 
 void
-acpi_dm_fixed_io_descriptor (
-        struct asl_fixed_io_port_desc   *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_fixed_io_descriptor(struct asl_fixed_io_port_desc *resource,
+                            u32 length, u32 level);
 
 void
-acpi_dm_start_dependent_descriptor (
-        struct asl_start_dependent_desc *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_start_dependent_descriptor(struct asl_start_dependent_desc *resource,
+                                   u32 length, u32 level);
 
 void
-acpi_dm_end_dependent_descriptor (
-        struct asl_start_dependent_desc *resource,
-        u32                             length,
-        u32                             level);
+acpi_dm_end_dependent_descriptor(struct asl_start_dependent_desc *resource,
+                                 u32 length, u32 level);
 
 void
-acpi_dm_vendor_small_descriptor (
-        struct asl_small_vendor_desc    *resource,
-        u32                             length,
-        u32                             level);
-
+acpi_dm_vendor_small_descriptor(struct asl_small_vendor_desc *resource,
+                                u32 length, u32 level);
 
 /*
  * dmutils
  */
+void acpi_dm_add_to_external_list(char *path);
 
-void
-acpi_dm_add_to_external_list (
-        char                            *path);
-
-#endif  /* __ACDISASM_H__ */
+#endif                          /* __ACDISASM_H__ */
diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h
index 237d63433581..065f24a77cfc 100644
--- a/include/acpi/acdispat.h
+++ b/include/acpi/acdispat.h
@@ -41,492 +41,304 @@
  * POSSIBILITY OF SUCH DAMAGES.
  */
 
-
 #ifndef _ACDISPAT_H_
 #define _ACDISPAT_H_
 
-
 #define NAMEOF_LOCAL_NTE    "__L0"
 #define NAMEOF_ARG_NTE      "__A0"
 
-
-/* Common interfaces */
-
-acpi_status
-acpi_ds_obj_stack_push (
-        void                            *object,
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ds_obj_stack_pop (
-        u32                             pop_count,
-        struct acpi_walk_state          *walk_state);
-
-#ifdef ACPI_FUTURE_USAGE
-void *
-acpi_ds_obj_stack_get_value (
-        u32                             index,
-        struct acpi_walk_state          *walk_state);
-#endif
-
-acpi_status
-acpi_ds_obj_stack_pop_object (
-        union acpi_operand_object       **object,
-        struct acpi_walk_state          *walk_state);
-
-
-/* dsopcode - support for late evaluation */
-
-acpi_status
-acpi_ds_execute_arguments (
-        struct acpi_namespace_node      *node,
-        struct acpi_namespace_node      *scope_node,
-        u32                             aml_length,
-        u8                              *aml_start);
-
-acpi_status
-acpi_ds_get_buffer_field_arguments (
-        union acpi_operand_object       *obj_desc);
-
-acpi_status
-acpi_ds_get_region_arguments (
-        union acpi_operand_object       *rgn_desc);
-
-acpi_status
-acpi_ds_get_buffer_arguments (
-        union acpi_operand_object       *obj_desc);
-
-acpi_status
-acpi_ds_get_package_arguments (
-        union acpi_operand_object       *obj_desc);
-
+/*
+ * dsopcode - support for late evaluation
+ */
 acpi_status
-acpi_ds_init_buffer_field (
-        u16                             aml_opcode,
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       *buffer_desc,
-        union acpi_operand_object       *offset_desc,
-        union acpi_operand_object       *length_desc,
-        union acpi_operand_object       *result_desc);
+acpi_ds_get_buffer_field_arguments(union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ds_eval_buffer_field_operands (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+acpi_status acpi_ds_get_region_arguments(union acpi_operand_object *rgn_desc);
 
-acpi_status
-acpi_ds_eval_region_operands (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+acpi_status acpi_ds_get_buffer_arguments(union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ds_eval_data_object_operands (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        union acpi_operand_object       *obj_desc);
+acpi_status acpi_ds_get_package_arguments(union acpi_operand_object *obj_desc);
 
 acpi_status
-acpi_ds_initialize_region (
-        acpi_handle                     obj_handle);
-
-
-/* dsctrl - Parser/Interpreter interface, control stack routines */
-
+acpi_ds_eval_buffer_field_operands(struct acpi_walk_state *walk_state,
+                                   union acpi_parse_object *op);
 
 acpi_status
-acpi_ds_exec_begin_control_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+acpi_ds_eval_region_operands(struct acpi_walk_state *walk_state,
+                             union acpi_parse_object *op);
 
 acpi_status
-acpi_ds_exec_end_control_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
-
+acpi_ds_eval_data_object_operands(struct acpi_walk_state *walk_state,
+                                  union acpi_parse_object *op,
+                                  union acpi_operand_object *obj_desc);
 
-/* dsexec - Parser/Interpreter interface, method execution callbacks */
-
-
-acpi_status
-acpi_ds_get_predicate_value (
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       *result_obj);
+acpi_status acpi_ds_initialize_region(acpi_handle obj_handle);
 
+/*
+ * dsctrl - Parser/Interpreter interface, control stack routines
+ */
 acpi_status
-acpi_ds_exec_begin_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         **out_op);
+acpi_ds_exec_begin_control_op(struct acpi_walk_state *walk_state,
+                              union acpi_parse_object *op);
 
 acpi_status
-acpi_ds_exec_end_op (
-        struct acpi_walk_state          *state);
-
-
-/* dsfield - Parser/Interpreter interface for AML fields */
+acpi_ds_exec_end_control_op(struct acpi_walk_state *walk_state,
+                            union acpi_parse_object *op);
 
+/*
+ * dsexec - Parser/Interpreter interface, method execution callbacks
+ */
 acpi_status
-acpi_ds_get_field_names (
-        struct acpi_create_field_info   *info,
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *arg);
+acpi_ds_get_predicate_value(struct acpi_walk_state *walk_state,
+                            union acpi_operand_object *result_obj);
 
 acpi_status
-acpi_ds_create_field (
-        union acpi_parse_object         *op,
-        struct acpi_namespace_node      *region_node,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_exec_begin_op(struct acpi_walk_state *walk_state,
+                      union acpi_parse_object **out_op);
 
-acpi_status
-acpi_ds_create_bank_field (
-        union acpi_parse_object         *op,
-        struct acpi_namespace_node      *region_node,
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *state);
 
+/*
+ * dsfield - Parser/Interpreter interface for AML fields
+ */
 acpi_status
-acpi_ds_create_index_field (
-        union acpi_parse_object         *op,
-        struct acpi_namespace_node      *region_node,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_create_field(union acpi_parse_object *op,
+                     struct acpi_namespace_node *region_node,
+                     struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_create_buffer_field (
-        union acpi_parse_object         *op,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_create_bank_field(union acpi_parse_object *op,
+                          struct acpi_namespace_node *region_node,
+                          struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_init_field_objects (
-        union acpi_parse_object         *op,
-        struct acpi_walk_state          *walk_state);
-
-
-/* dsload - Parser/Interpreter interface, namespace load callbacks */
+acpi_ds_create_index_field(union acpi_parse_object *op,
+                           struct acpi_namespace_node *region_node,
+                           struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_load1_begin_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         **out_op);
+acpi_ds_create_buffer_field(union acpi_parse_object *op,
+                            struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_load1_end_op (
-        struct acpi_walk_state          *walk_state);
+acpi_ds_init_field_objects(union acpi_parse_object *op,
+                           struct acpi_walk_state *walk_state);
 
+/*
+ * dsload - Parser/Interpreter interface, namespace load callbacks
+ */
 acpi_status
-acpi_ds_load2_begin_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         **out_op);
+acpi_ds_load1_begin_op(struct acpi_walk_state *walk_state,
+                       union acpi_parse_object **out_op);
 
-acpi_status
-acpi_ds_load2_end_op (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ds_load1_end_op(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_init_callbacks (
-        struct acpi_walk_state          *walk_state,
-        u32                             pass_number);
-
-
-/* dsmthdat - method data (locals/args) */
+acpi_ds_load2_begin_op(struct acpi_walk_state *walk_state,
+                       union acpi_parse_object **out_op);
 
+acpi_status acpi_ds_load2_end_op(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_store_object_to_local (
-        u16                             opcode,
-        u32                             index,
-        union acpi_operand_object       *src_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_init_callbacks(struct acpi_walk_state *walk_state, u32 pass_number);
 
+/*
+ * dsmthdat - method data (locals/args)
+ */
 acpi_status
-acpi_ds_method_data_get_entry (
-        u16                             opcode,
-        u32                             index,
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       ***node);
-
-void
-acpi_ds_method_data_delete_all (
-        struct acpi_walk_state          *walk_state);
-
-u8
-acpi_ds_is_method_value (
-        union acpi_operand_object       *obj_desc);
-
-#ifdef ACPI_FUTURE_USAGE
-acpi_object_type
-acpi_ds_method_data_get_type (
-        u16                             opcode,
-        u32                             index,
-        struct acpi_walk_state          *walk_state);
-#endif
+acpi_ds_store_object_to_local(u16 opcode,
+                              u32 index,
+                              union acpi_operand_object *src_desc,
+                              struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_method_data_get_value (
-        u16                             opcode,
-        u32                             index,
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       **dest_desc);
+acpi_ds_method_data_get_entry(u16 opcode,
+                              u32 index,
+                              struct acpi_walk_state *walk_state,
+                              union acpi_operand_object ***node);
 
-void
-acpi_ds_method_data_delete_value (
-        u16                             opcode,
-        u32                             index,
-        struct acpi_walk_state          *walk_state);
+void acpi_ds_method_data_delete_all(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ds_method_data_init_args (
-        union acpi_operand_object       **params,
-        u32                             max_param_count,
-        struct acpi_walk_state          *walk_state);
+u8 acpi_ds_is_method_value(union acpi_operand_object *obj_desc);
 
 acpi_status
-acpi_ds_method_data_get_node (
-        u16                             opcode,
-        u32                             index,
-        struct acpi_walk_state          *walk_state,
-        struct acpi_namespace_node      **node);
-
-void
-acpi_ds_method_data_init (
-        struct acpi_walk_state          *walk_state);
+acpi_ds_method_data_get_value(u16 opcode,
+                              u32 index,
+                              struct acpi_walk_state *walk_state,
+                              union acpi_operand_object **dest_desc);
 
 acpi_status
-acpi_ds_method_data_set_value (
-        u16                             opcode,
-        u32                             index,
-        union acpi_operand_object       *object,
-        struct acpi_walk_state          *walk_state);
-
-
-/* dsmethod - Parser/Interpreter interface - control method parsing */
+acpi_ds_method_data_init_args(union acpi_operand_object **params,
+                              u32 max_param_count,
+                              struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_parse_method (
-        acpi_handle                     obj_handle);
+acpi_ds_method_data_get_node(u16 opcode,
+                             u32 index,
+                             struct acpi_walk_state *walk_state,
+                             struct acpi_namespace_node **node);
 
-acpi_status
-acpi_ds_call_control_method (
-        struct acpi_thread_state        *thread,
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+void acpi_ds_method_data_init(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ds_restart_control_method (
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       *return_desc);
+/*
+ * dsmethod - Parser/Interpreter interface - control method parsing
+ */
+acpi_status acpi_ds_parse_method(struct acpi_namespace_node *node);
 
 acpi_status
-acpi_ds_terminate_control_method (
-        struct acpi_walk_state          *walk_state);
+acpi_ds_call_control_method(struct acpi_thread_state *thread,
+                            struct acpi_walk_state *walk_state,
+                            union acpi_parse_object *op);
 
 acpi_status
-acpi_ds_begin_method_execution (
-        struct acpi_namespace_node      *method_node,
-        union acpi_operand_object       *obj_desc,
-        struct acpi_namespace_node      *calling_method_node);
+acpi_ds_restart_control_method(struct acpi_walk_state *walk_state,
+                               union acpi_operand_object *return_desc);
 
-
-/* dsobj - Parser/Interpreter interface - object initialization and conversion */
-
-acpi_status
-acpi_ds_init_one_object (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+void acpi_ds_terminate_control_method(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_initialize_objects (
-        struct acpi_table_desc          *table_desc,
-        struct acpi_namespace_node      *start_node);
+acpi_ds_begin_method_execution(struct acpi_namespace_node *method_node,
+                               union acpi_operand_object *obj_desc,
+                               struct acpi_namespace_node *calling_method_node);
 
+/*
+ * dsinit
+ */
 acpi_status
-acpi_ds_build_internal_buffer_obj (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        u32                             buffer_length,
-        union acpi_operand_object       **obj_desc_ptr);
+acpi_ds_initialize_objects(struct acpi_table_desc *table_desc,
+                           struct acpi_namespace_node *start_node);
 
+/*
+ * dsobject - Parser/Interpreter interface - object initialization and conversion
+ */
 acpi_status
-acpi_ds_build_internal_package_obj (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        u32                             package_length,
-        union acpi_operand_object       **obj_desc);
+acpi_ds_build_internal_buffer_obj(struct acpi_walk_state *walk_state,
+                                  union acpi_parse_object *op,
+                                  u32 buffer_length,
+                                  union acpi_operand_object **obj_desc_ptr);
 
 acpi_status
-acpi_ds_build_internal_object (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        union acpi_operand_object       **obj_desc_ptr);
+acpi_ds_build_internal_package_obj(struct acpi_walk_state *walk_state,
+                                   union acpi_parse_object *op,
+                                   u32 package_length,
+                                   union acpi_operand_object **obj_desc);
 
 acpi_status
-acpi_ds_init_object_from_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        u16                             opcode,
-        union acpi_operand_object       **obj_desc);
+acpi_ds_init_object_from_op(struct acpi_walk_state *walk_state,
+                            union acpi_parse_object *op,
+                            u16 opcode, union acpi_operand_object **obj_desc);
 
 acpi_status
-acpi_ds_create_node (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_namespace_node      *node,
-        union acpi_parse_object         *op);
-
-
-/* dsutils - Parser/Interpreter interface utility routines */
+acpi_ds_create_node(struct acpi_walk_state *walk_state,
+                    struct acpi_namespace_node *node,
+                    union acpi_parse_object *op);
 
-void
-acpi_ds_clear_implicit_return (
-        struct acpi_walk_state          *walk_state);
+/*
+ * dsutils - Parser/Interpreter interface utility routines
+ */
+void acpi_ds_clear_implicit_return(struct acpi_walk_state *walk_state);
 
 u8
-acpi_ds_do_implicit_return (
-        union acpi_operand_object       *return_desc,
-        struct acpi_walk_state          *walk_state,
-        u8                              add_reference);
+acpi_ds_do_implicit_return(union acpi_operand_object *return_desc,
+                           struct acpi_walk_state *walk_state,
+                           u8 add_reference);
 
 u8
-acpi_ds_is_result_used (
-        union acpi_parse_object         *op,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_is_result_used(union acpi_parse_object *op,
+                       struct acpi_walk_state *walk_state);
 
 void
-acpi_ds_delete_result_if_not_used (
-        union acpi_parse_object         *op,
-        union acpi_operand_object       *result_obj,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_delete_result_if_not_used(union acpi_parse_object *op,
+                                  union acpi_operand_object *result_obj,
+                                  struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_create_operand (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *arg,
-        u32                             args_remaining);
+acpi_ds_create_operand(struct acpi_walk_state *walk_state,
+                       union acpi_parse_object *arg, u32 args_remaining);
 
 acpi_status
-acpi_ds_create_operands (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *first_arg);
+acpi_ds_create_operands(struct acpi_walk_state *walk_state,
+                        union acpi_parse_object *first_arg);
 
-acpi_status
-acpi_ds_resolve_operands (
-        struct acpi_walk_state          *walk_state);
-
-void
-acpi_ds_clear_operands (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ds_resolve_operands(struct acpi_walk_state *walk_state);
 
+void acpi_ds_clear_operands(struct acpi_walk_state *walk_state);
 
 /*
  * dswscope - Scope Stack manipulation
  */
-
 acpi_status
-acpi_ds_scope_stack_push (
-        struct acpi_namespace_node      *node,
-        acpi_object_type                type,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_scope_stack_push(struct acpi_namespace_node *node,
+                         acpi_object_type type,
+                         struct acpi_walk_state *walk_state);
 
+acpi_status acpi_ds_scope_stack_pop(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ds_scope_stack_pop (
-        struct acpi_walk_state          *walk_state);
-
-void
-acpi_ds_scope_stack_clear (
-        struct acpi_walk_state          *walk_state);
-
+void acpi_ds_scope_stack_clear(struct acpi_walk_state *walk_state);
 
-/* dswstate - parser WALK_STATE management routines */
-
-struct acpi_walk_state *
-acpi_ds_create_walk_state (
-        acpi_owner_id                   owner_id,
-        union acpi_parse_object         *origin,
-        union acpi_operand_object       *mth_desc,
-        struct acpi_thread_state        *thread);
+/*
+ * dswstate - parser WALK_STATE management routines
+ */
+acpi_status
+acpi_ds_obj_stack_push(void *object, struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_init_aml_walk (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        struct acpi_namespace_node      *method_node,
-        u8                              *aml_start,
-        u32                             aml_length,
-        struct acpi_parameter_info      *info,
-        u32                             pass_number);
+acpi_ds_obj_stack_pop(u32 pop_count, struct acpi_walk_state *walk_state);
+
+struct acpi_walk_state *acpi_ds_create_walk_state(acpi_owner_id owner_id,
+                                                  union acpi_parse_object
+                                                  *origin,
+                                                  union acpi_operand_object
+                                                  *mth_desc,
+                                                  struct acpi_thread_state
+                                                  *thread);
 
-#ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_ds_obj_stack_delete_all (
-        struct acpi_walk_state          *walk_state);
-#endif
+acpi_ds_init_aml_walk(struct acpi_walk_state *walk_state,
+                      union acpi_parse_object *op,
+                      struct acpi_namespace_node *method_node,
+                      u8 * aml_start,
+                      u32 aml_length,
+                      struct acpi_parameter_info *info, u8 pass_number);
 
 acpi_status
-acpi_ds_obj_stack_pop_and_delete (
-        u32                             pop_count,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_obj_stack_pop_and_delete(u32 pop_count,
+                                 struct acpi_walk_state *walk_state);
 
-void
-acpi_ds_delete_walk_state (
-        struct acpi_walk_state          *walk_state);
+void acpi_ds_delete_walk_state(struct acpi_walk_state *walk_state);
 
-struct acpi_walk_state *
-acpi_ds_pop_walk_state (
-        struct acpi_thread_state        *thread);
+struct acpi_walk_state *acpi_ds_pop_walk_state(struct acpi_thread_state
+                                               *thread);
 
 void
-acpi_ds_push_walk_state (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_thread_state        *thread);
+acpi_ds_push_walk_state(struct acpi_walk_state *walk_state,
+                        struct acpi_thread_state *thread);
 
-acpi_status
-acpi_ds_result_stack_pop (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ds_result_stack_pop(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ds_result_stack_push (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ds_result_stack_push(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ds_result_stack_clear (
-        struct acpi_walk_state          *walk_state);
-
-struct acpi_walk_state *
-acpi_ds_get_current_walk_state (
-        struct acpi_thread_state        *thread);
+acpi_status acpi_ds_result_stack_clear(struct acpi_walk_state *walk_state);
 
-#ifdef ACPI_ENABLE_OBJECT_CACHE
-void
-acpi_ds_delete_walk_state_cache (
-        void);
-#endif
+struct acpi_walk_state *acpi_ds_get_current_walk_state(struct acpi_thread_state
+                                                       *thread);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_ds_result_insert (
-        void                            *object,
-        u32                             index,
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ds_result_remove (
-        union acpi_operand_object       **object,
-        u32                             index,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_result_remove(union acpi_operand_object **object,
+                      u32 index, struct acpi_walk_state *walk_state);
 #endif
 
 acpi_status
-acpi_ds_result_pop (
-        union acpi_operand_object       **object,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_result_pop(union acpi_operand_object **object,
+                   struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_result_push (
-        union acpi_operand_object       *object,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_result_push(union acpi_operand_object *object,
+                    struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_result_pop_from_bottom (
-        union acpi_operand_object       **object,
-        struct acpi_walk_state          *walk_state);
+acpi_ds_result_pop_from_bottom(union acpi_operand_object **object,
+                               struct acpi_walk_state *walk_state);
 
-#endif /* _ACDISPAT_H_ */
+#endif                          /* _ACDISPAT_H_ */
diff --git a/include/acpi/acevents.h b/include/acpi/acevents.h
index 2dec083ba1cd..bfa54600ecd9 100644
--- a/include/acpi/acevents.h
+++ b/include/acpi/acevents.h
@@ -44,277 +44,167 @@
 #ifndef __ACEVENTS_H__
 #define __ACEVENTS_H__
 
-
-acpi_status
-acpi_ev_initialize_events (
-        void);
-
-acpi_status
-acpi_ev_install_xrupt_handlers (
-        void);
-
-
 /*
- * Evfixed - Fixed event handling
+ * evevent
  */
+acpi_status acpi_ev_initialize_events(void);
 
-acpi_status
-acpi_ev_fixed_event_initialize (
-        void);
-
-u32
-acpi_ev_fixed_event_detect (
-        void);
-
-u32
-acpi_ev_fixed_event_dispatch (
-        u32                             event);
+acpi_status acpi_ev_install_xrupt_handlers(void);
 
+u32 acpi_ev_fixed_event_detect(void);
 
 /*
- * Evmisc
+ * evmisc
  */
+u8 acpi_ev_is_notify_object(struct acpi_namespace_node *node);
 
-u8
-acpi_ev_is_notify_object (
-        struct acpi_namespace_node      *node);
+acpi_status acpi_ev_acquire_global_lock(u16 timeout);
 
-acpi_status
-acpi_ev_acquire_global_lock(
-        u16                             timeout);
-
-acpi_status
-acpi_ev_release_global_lock(
-        void);
+acpi_status acpi_ev_release_global_lock(void);
 
-acpi_status
-acpi_ev_init_global_lock_handler (
-        void);
+acpi_status acpi_ev_init_global_lock_handler(void);
 
-u32
-acpi_ev_get_gpe_number_index (
-        u32                             gpe_number);
+u32 acpi_ev_get_gpe_number_index(u32 gpe_number);
 
 acpi_status
-acpi_ev_queue_notify_request (
-        struct acpi_namespace_node      *node,
-        u32                             notify_value);
-
-void ACPI_SYSTEM_XFACE
-acpi_ev_notify_dispatch (
-        void                            *context);
-
+acpi_ev_queue_notify_request(struct acpi_namespace_node *node,
+                             u32 notify_value);
 
 /*
- * Evgpe - GPE handling and dispatch
+ * evgpe - GPE handling and dispatch
  */
-
 acpi_status
-acpi_ev_walk_gpe_list (
-        ACPI_GPE_CALLBACK       gpe_walk_callback,
-        u32                             flags);
-
-u8
-acpi_ev_valid_gpe_event (
-        struct acpi_gpe_event_info      *gpe_event_info);
+acpi_ev_update_gpe_enable_masks(struct acpi_gpe_event_info *gpe_event_info,
+                                u8 type);
 
 acpi_status
-acpi_ev_update_gpe_enable_masks (
-        struct acpi_gpe_event_info      *gpe_event_info,
-        u8                              type);
+acpi_ev_enable_gpe(struct acpi_gpe_event_info *gpe_event_info,
+                   u8 write_to_hardware);
 
-acpi_status
-acpi_ev_enable_gpe (
-        struct acpi_gpe_event_info      *gpe_event_info,
-        u8                              write_to_hardware);
+acpi_status acpi_ev_disable_gpe(struct acpi_gpe_event_info *gpe_event_info);
 
-acpi_status
-acpi_ev_disable_gpe (
-        struct acpi_gpe_event_info      *gpe_event_info);
+struct acpi_gpe_event_info *acpi_ev_get_gpe_event_info(acpi_handle gpe_device,
+                                                       u32 gpe_number);
 
-struct acpi_gpe_event_info *
-acpi_ev_get_gpe_event_info (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number);
+/*
+ * evgpeblk
+ */
+u8 acpi_ev_valid_gpe_event(struct acpi_gpe_event_info *gpe_event_info);
 
-acpi_status
-acpi_ev_gpe_initialize (
-        void);
+acpi_status acpi_ev_walk_gpe_list(ACPI_GPE_CALLBACK gpe_walk_callback);
 
 acpi_status
-acpi_ev_create_gpe_block (
-        struct acpi_namespace_node      *gpe_device,
-        struct acpi_generic_address     *gpe_block_address,
-        u32                             register_count,
-        u8                              gpe_block_base_number,
-        u32                             interrupt_level,
-        struct acpi_gpe_block_info      **return_gpe_block);
+acpi_ev_delete_gpe_handlers(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
+                            struct acpi_gpe_block_info *gpe_block);
 
 acpi_status
-acpi_ev_delete_gpe_block (
-        struct acpi_gpe_block_info      *gpe_block);
+acpi_ev_create_gpe_block(struct acpi_namespace_node *gpe_device,
+                         struct acpi_generic_address *gpe_block_address,
+                         u32 register_count,
+                         u8 gpe_block_base_number,
+                         u32 interrupt_number,
+                         struct acpi_gpe_block_info **return_gpe_block);
 
-acpi_status
-acpi_ev_delete_gpe_handlers (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
+acpi_status acpi_ev_delete_gpe_block(struct acpi_gpe_block_info *gpe_block);
 
 u32
-acpi_ev_gpe_dispatch (
-        struct acpi_gpe_event_info      *gpe_event_info,
-        u32                             gpe_number);
+acpi_ev_gpe_dispatch(struct acpi_gpe_event_info *gpe_event_info,
+                     u32 gpe_number);
 
-u32
-acpi_ev_gpe_detect (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_list);
+u32 acpi_ev_gpe_detect(struct acpi_gpe_xrupt_info *gpe_xrupt_list);
 
 acpi_status
-acpi_ev_set_gpe_type (
-        struct acpi_gpe_event_info      *gpe_event_info,
-        u8                              type);
+acpi_ev_set_gpe_type(struct acpi_gpe_event_info *gpe_event_info, u8 type);
 
 acpi_status
-acpi_ev_check_for_wake_only_gpe (
-        struct acpi_gpe_event_info      *gpe_event_info);
+acpi_ev_check_for_wake_only_gpe(struct acpi_gpe_event_info *gpe_event_info);
+
+acpi_status acpi_ev_gpe_initialize(void);
 
 /*
- * Evregion - Address Space handling
+ * evregion - Address Space handling
  */
+acpi_status acpi_ev_install_region_handlers(void);
 
-acpi_status
-acpi_ev_install_region_handlers (
-        void);
-
-acpi_status
-acpi_ev_initialize_op_regions (
-        void);
-
-acpi_status
-acpi_ev_address_space_dispatch (
-        union acpi_operand_object      *region_obj,
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        void                            *value);
+acpi_status acpi_ev_initialize_op_regions(void);
 
 acpi_status
-acpi_ev_install_handler (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
+                               u32 function,
+                               acpi_physical_address address,
+                               u32 bit_width, void *value);
 
 acpi_status
-acpi_ev_attach_region (
-        union acpi_operand_object       *handler_obj,
-        union acpi_operand_object       *region_obj,
-        u8                              acpi_ns_is_locked);
+acpi_ev_attach_region(union acpi_operand_object *handler_obj,
+                      union acpi_operand_object *region_obj,
+                      u8 acpi_ns_is_locked);
 
 void
-acpi_ev_detach_region (
-        union acpi_operand_object      *region_obj,
-        u8                              acpi_ns_is_locked);
+acpi_ev_detach_region(union acpi_operand_object *region_obj,
+                      u8 acpi_ns_is_locked);
 
 acpi_status
-acpi_ev_install_space_handler (
-        struct acpi_namespace_node      *node,
-        acpi_adr_space_type             space_id,
-        acpi_adr_space_handler          handler,
-        acpi_adr_space_setup            setup,
-        void                            *context);
+acpi_ev_install_space_handler(struct acpi_namespace_node *node,
+                              acpi_adr_space_type space_id,
+                              acpi_adr_space_handler handler,
+                              acpi_adr_space_setup setup, void *context);
 
 acpi_status
-acpi_ev_execute_reg_methods (
-        struct acpi_namespace_node      *node,
-        acpi_adr_space_type             space_id);
+acpi_ev_execute_reg_methods(struct acpi_namespace_node *node,
+                            acpi_adr_space_type space_id);
 
 acpi_status
-acpi_ev_execute_reg_method (
-        union acpi_operand_object      *region_obj,
-        u32                             function);
-
-acpi_status
-acpi_ev_reg_run (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+acpi_ev_execute_reg_method(union acpi_operand_object *region_obj, u32 function);
 
 /*
- * Evregini - Region initialization and setup
+ * evregini - Region initialization and setup
  */
-
 acpi_status
-acpi_ev_system_memory_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_system_memory_region_setup(acpi_handle handle,
+                                   u32 function,
+                                   void *handler_context,
+                                   void **region_context);
 
 acpi_status
-acpi_ev_io_space_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_io_space_region_setup(acpi_handle handle,
+                              u32 function,
+                              void *handler_context, void **region_context);
 
 acpi_status
-acpi_ev_pci_config_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_pci_config_region_setup(acpi_handle handle,
+                                u32 function,
+                                void *handler_context, void **region_context);
 
 acpi_status
-acpi_ev_cmos_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_cmos_region_setup(acpi_handle handle,
+                          u32 function,
+                          void *handler_context, void **region_context);
 
 acpi_status
-acpi_ev_pci_bar_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_pci_bar_region_setup(acpi_handle handle,
+                             u32 function,
+                             void *handler_context, void **region_context);
 
 acpi_status
-acpi_ev_default_region_setup (
-        acpi_handle                     handle,
-        u32                             function,
-        void                            *handler_context,
-        void                            **region_context);
+acpi_ev_default_region_setup(acpi_handle handle,
+                             u32 function,
+                             void *handler_context, void **region_context);
 
 acpi_status
-acpi_ev_initialize_region (
-        union acpi_operand_object       *region_obj,
-        u8                              acpi_ns_locked);
-
+acpi_ev_initialize_region(union acpi_operand_object *region_obj,
+                          u8 acpi_ns_locked);
 
 /*
- * Evsci - SCI (System Control Interrupt) handling/dispatch
+ * evsci - SCI (System Control Interrupt) handling/dispatch
  */
+u32 ACPI_SYSTEM_XFACE acpi_ev_gpe_xrupt_handler(void *context);
 
-u32 ACPI_SYSTEM_XFACE
-acpi_ev_gpe_xrupt_handler (
-        void                            *context);
-
-u32
-acpi_ev_install_sci_handler (
-        void);
+u32 acpi_ev_install_sci_handler(void);
 
-acpi_status
-acpi_ev_remove_sci_handler (
-        void);
+acpi_status acpi_ev_remove_sci_handler(void);
 
-u32
-acpi_ev_initialize_sCI (
-        u32                             program_sCI);
-
-void
-acpi_ev_terminate (
-        void);
+u32 acpi_ev_initialize_sCI(u32 program_sCI);
 
+void acpi_ev_terminate(void);
 
-#endif  /* __ACEVENTS_H__  */
+#endif                          /* __ACEVENTS_H__  */
diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h
index 53f8b50fac1a..4f005eb65928 100644
--- a/include/acpi/acexcep.h
+++ b/include/acpi/acexcep.h
@@ -44,11 +44,9 @@
 #ifndef __ACEXCEP_H__
 #define __ACEXCEP_H__
 
-
 /*
  * Exceptions returned by external ACPI interfaces
  */
-
 #define AE_CODE_ENVIRONMENTAL           0x0000
 #define AE_CODE_PROGRAMMER              0x1000
 #define AE_CODE_ACPI_TABLES             0x2000
@@ -56,11 +54,9 @@
 #define AE_CODE_CONTROL                 0x4000
 #define AE_CODE_MASK                    0xF000
 
-
 #define ACPI_SUCCESS(a)                 (!(a))
 #define ACPI_FAILURE(a)                 (a)
 
-
 #define AE_OK                           (acpi_status) 0x0000
 
 /*
@@ -96,8 +92,9 @@
 #define AE_ABORT_METHOD                 (acpi_status) (0x001C | AE_CODE_ENVIRONMENTAL)
 #define AE_SAME_HANDLER                 (acpi_status) (0x001D | AE_CODE_ENVIRONMENTAL)
 #define AE_WAKE_ONLY_GPE                (acpi_status) (0x001E | AE_CODE_ENVIRONMENTAL)
+#define AE_OWNER_ID_LIMIT               (acpi_status) (0x001F | AE_CODE_ENVIRONMENTAL)
 
-#define AE_CODE_ENV_MAX                 0x001E
+#define AE_CODE_ENV_MAX                 0x001F
 
 /*
  * Programmer exceptions
@@ -114,7 +111,6 @@
 
 #define AE_CODE_PGM_MAX                 0x0009
 
-
 /*
  * Acpi table exceptions
  */
@@ -127,7 +123,6 @@
 
 #define AE_CODE_TBL_MAX                 0x0006
 
-
 /*
  * AML exceptions.  These are caused by problems with
  * the actual AML byte stream
@@ -185,15 +180,13 @@
 
 #define AE_CODE_CTRL_MAX                0x000B
 
-
 #ifdef DEFINE_ACPI_GLOBALS
 
 /*
  * String versions of the exception codes above
  * These strings must match the corresponding defines exactly
  */
-char const   *acpi_gbl_exception_names_env[] =
-{
+char const *acpi_gbl_exception_names_env[] = {
         "AE_OK",
         "AE_ERROR",
         "AE_NO_ACPI_TABLES",
@@ -224,11 +217,11 @@ char const   *acpi_gbl_exception_names_env[] =
         "AE_LOGICAL_ADDRESS",
         "AE_ABORT_METHOD",
         "AE_SAME_HANDLER",
-        "AE_WAKE_ONLY_GPE"
+        "AE_WAKE_ONLY_GPE",
+        "AE_OWNER_ID_LIMIT"
 };
 
-char const   *acpi_gbl_exception_names_pgm[] =
-{
+char const *acpi_gbl_exception_names_pgm[] = {
         "AE_BAD_PARAMETER",
         "AE_BAD_CHARACTER",
         "AE_BAD_PATHNAME",
@@ -240,8 +233,7 @@ char const   *acpi_gbl_exception_names_pgm[] =
         "AE_BAD_DECIMAL_CONSTANT"
 };
 
-char const   *acpi_gbl_exception_names_tbl[] =
-{
+char const *acpi_gbl_exception_names_tbl[] = {
         "AE_BAD_SIGNATURE",
         "AE_BAD_HEADER",
         "AE_BAD_CHECKSUM",
@@ -250,8 +242,7 @@ char const   *acpi_gbl_exception_names_tbl[] =
         "AE_INVALID_TABLE_LENGTH"
 };
 
-char const   *acpi_gbl_exception_names_aml[] =
-{
+char const *acpi_gbl_exception_names_aml[] = {
         "AE_AML_ERROR",
         "AE_AML_PARSE",
         "AE_AML_BAD_OPCODE",
@@ -287,8 +278,7 @@ char const   *acpi_gbl_exception_names_aml[] =
         "AE_AML_BAD_RESOURCE_LENGTH"
 };
 
-char const   *acpi_gbl_exception_names_ctrl[] =
-{
+char const *acpi_gbl_exception_names_ctrl[] = {
         "AE_CTRL_RETURN_VALUE",
         "AE_CTRL_PENDING",
         "AE_CTRL_TERMINATE",
@@ -302,7 +292,6 @@ char const   *acpi_gbl_exception_names_ctrl[] =
         "AE_CTRL_SKIP"
 };
 
-#endif /* ACPI GLOBALS */
-
+#endif                          /* ACPI GLOBALS */
 
-#endif /* __ACEXCEP_H__ */
+#endif                          /* __ACEXCEP_H__ */
diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h
index c7f387a972cb..e9c2790139ec 100644
--- a/include/acpi/acglobal.h
+++ b/include/acpi/acglobal.h
@@ -44,7 +44,6 @@
 #ifndef __ACGLOBAL_H__
 #define __ACGLOBAL_H__
 
-
 /*
  * Ensure that the globals are actually defined and initialized only once.
  *
@@ -63,9 +62,8 @@
  * Keep local copies of these FADT-based registers.  NOTE: These globals
  * are first in this file for alignment reasons on 64-bit systems.
  */
-ACPI_EXTERN struct acpi_generic_address         acpi_gbl_xpm1a_enable;
-ACPI_EXTERN struct acpi_generic_address         acpi_gbl_xpm1b_enable;
-
+ACPI_EXTERN struct acpi_generic_address acpi_gbl_xpm1a_enable;
+ACPI_EXTERN struct acpi_generic_address acpi_gbl_xpm1b_enable;
 
 /*****************************************************************************
  *
@@ -75,13 +73,12 @@ ACPI_EXTERN struct acpi_generic_address         acpi_gbl_xpm1b_enable;
 
 /* Runtime configuration of debug print levels */
 
-extern      u32                                 acpi_dbg_level;
-extern      u32                                 acpi_dbg_layer;
+extern u32 acpi_dbg_level;
+extern u32 acpi_dbg_layer;
 
 /* Procedure nesting level for debug output */
 
-extern      u32                                 acpi_gbl_nesting_level;
-
+extern u32 acpi_gbl_nesting_level;
 
 /*****************************************************************************
  *
@@ -98,7 +95,7 @@ extern      u32                                 acpi_gbl_nesting_level;
  * 3) Allow access to uninitialized locals/args (auto-init to integer 0)
  * 4) Allow ANY object type to be a source operand for the Store() operator
  */
-ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_enable_interpreter_slack, FALSE);
+ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_enable_interpreter_slack, FALSE);
 
 /*
  * Automatically serialize ALL control methods? Default is FALSE, meaning
@@ -106,22 +103,21 @@ ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_enable_interpreter_slack, FALSE)
  * Only change this if the ASL code is poorly written and cannot handle
  * reentrancy even though methods are marked "not_serialized".
  */
-ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_all_methods_serialized, FALSE);
+ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_all_methods_serialized, FALSE);
 
 /*
  * Create the predefined _OSI method in the namespace? Default is TRUE
  * because ACPI CA is fully compatible with other ACPI implementations.
  * Changing this will revert ACPI CA (and machine ASL) to pre-OSI behavior.
  */
-ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_create_osi_method, TRUE);
+ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_create_osi_method, TRUE);
 
 /*
  * Disable wakeup GPEs during runtime? Default is TRUE because WAKE and
  * RUNTIME GPEs should never be shared, and WAKE GPEs should typically only
  * be enabled just before going to sleep.
  */
-ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_leave_wake_gpes_disabled, TRUE);
-
+ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_leave_wake_gpes_disabled, TRUE);
 
 /*****************************************************************************
  *
@@ -137,42 +133,46 @@ ACPI_EXTERN u8       ACPI_INIT_GLOBAL (acpi_gbl_leave_wake_gpes_disabled, TRUE);
  * These tables are single-table only; meaning that there can be at most one
  * of each in the system.  Each global points to the actual table.
  */
-ACPI_EXTERN u32                                 acpi_gbl_table_flags;
-ACPI_EXTERN u32                                 acpi_gbl_rsdt_table_count;
-ACPI_EXTERN struct rsdp_descriptor             *acpi_gbl_RSDP;
-ACPI_EXTERN XSDT_DESCRIPTOR            *acpi_gbl_XSDT;
-ACPI_EXTERN FADT_DESCRIPTOR            *acpi_gbl_FADT;
-ACPI_EXTERN struct acpi_table_header           *acpi_gbl_DSDT;
-ACPI_EXTERN FACS_DESCRIPTOR            *acpi_gbl_FACS;
-ACPI_EXTERN struct acpi_common_facs             acpi_gbl_common_fACS;
+ACPI_EXTERN u32 acpi_gbl_table_flags;
+ACPI_EXTERN u32 acpi_gbl_rsdt_table_count;
+ACPI_EXTERN struct rsdp_descriptor *acpi_gbl_RSDP;
+ACPI_EXTERN XSDT_DESCRIPTOR *acpi_gbl_XSDT;
+ACPI_EXTERN FADT_DESCRIPTOR *acpi_gbl_FADT;
+ACPI_EXTERN struct acpi_table_header *acpi_gbl_DSDT;
+ACPI_EXTERN FACS_DESCRIPTOR *acpi_gbl_FACS;
+ACPI_EXTERN struct acpi_common_facs acpi_gbl_common_fACS;
 /*
- * Since there may be multiple SSDTs and PSDTS, a single pointer is not
+ * Since there may be multiple SSDTs and PSDTs, a single pointer is not
  * sufficient; Therefore, there isn't one!
  */
 
+/* The root table can be either an RSDT or an XSDT */
+
+ACPI_EXTERN u8 acpi_gbl_root_table_type;
+#define     ACPI_TABLE_TYPE_RSDT        'R'
+#define     ACPI_TABLE_TYPE_XSDT        'X'
 
 /*
- * Handle both ACPI 1.0 and ACPI 2.0 Integer widths
- * If we are running a method that exists in a 32-bit ACPI table.
- * Use only 32 bits of the Integer for conversion.
+ * Handle both ACPI 1.0 and ACPI 2.0 Integer widths:
+ * If we are executing a method that exists in a 32-bit ACPI table,
+ * use only the lower 32 bits of the (internal) 64-bit Integer.
  */
-ACPI_EXTERN u8                                  acpi_gbl_integer_bit_width;
-ACPI_EXTERN u8                                  acpi_gbl_integer_byte_width;
-ACPI_EXTERN u8                                  acpi_gbl_integer_nybble_width;
+ACPI_EXTERN u8 acpi_gbl_integer_bit_width;
+ACPI_EXTERN u8 acpi_gbl_integer_byte_width;
+ACPI_EXTERN u8 acpi_gbl_integer_nybble_width;
 
 /*
  * ACPI Table info arrays
  */
-extern      struct acpi_table_list              acpi_gbl_table_lists[NUM_ACPI_TABLE_TYPES];
-extern      struct acpi_table_support           acpi_gbl_table_data[NUM_ACPI_TABLE_TYPES];
+extern struct acpi_table_list acpi_gbl_table_lists[NUM_ACPI_TABLE_TYPES];
+extern struct acpi_table_support acpi_gbl_table_data[NUM_ACPI_TABLE_TYPES];
 
 /*
  * Predefined mutex objects.  This array contains the
  * actual OS mutex handles, indexed by the local ACPI_MUTEX_HANDLEs.
  * (The table maps local handles to the real OS handles)
  */
-ACPI_EXTERN struct acpi_mutex_info              acpi_gbl_mutex_info[NUM_MUTEX];
-
+ACPI_EXTERN struct acpi_mutex_info acpi_gbl_mutex_info[NUM_MUTEX];
 
 /*****************************************************************************
  *
@@ -180,41 +180,56 @@ ACPI_EXTERN struct acpi_mutex_info              acpi_gbl_mutex_info[NUM_MUTEX];
  *
  ****************************************************************************/
 
+#ifdef ACPI_DBG_TRACK_ALLOCATIONS
+
+/* Lists for tracking memory allocations */
 
-ACPI_EXTERN struct acpi_memory_list             acpi_gbl_memory_lists[ACPI_NUM_MEM_LISTS];
-ACPI_EXTERN struct acpi_object_notify_handler   acpi_gbl_device_notify;
-ACPI_EXTERN struct acpi_object_notify_handler   acpi_gbl_system_notify;
-ACPI_EXTERN acpi_exception_handler              acpi_gbl_exception_handler;
-ACPI_EXTERN acpi_init_handler                   acpi_gbl_init_handler;
-ACPI_EXTERN struct acpi_walk_state             *acpi_gbl_breakpoint_walk;
-ACPI_EXTERN acpi_handle                         acpi_gbl_global_lock_semaphore;
-
-ACPI_EXTERN u32                                 acpi_gbl_global_lock_thread_count;
-ACPI_EXTERN u32                                 acpi_gbl_original_mode;
-ACPI_EXTERN u32                                 acpi_gbl_rsdp_original_location;
-ACPI_EXTERN u32                                 acpi_gbl_ns_lookup_count;
-ACPI_EXTERN u32                                 acpi_gbl_ps_find_count;
-ACPI_EXTERN u16                                 acpi_gbl_pm1_enable_register_save;
-ACPI_EXTERN u16                                 acpi_gbl_next_table_owner_id;
-ACPI_EXTERN u16                                 acpi_gbl_next_method_owner_id;
-ACPI_EXTERN u16                                 acpi_gbl_global_lock_handle;
-ACPI_EXTERN u8                                  acpi_gbl_debugger_configuration;
-ACPI_EXTERN u8                                  acpi_gbl_global_lock_acquired;
-ACPI_EXTERN u8                                  acpi_gbl_step_to_next_call;
-ACPI_EXTERN u8                                  acpi_gbl_acpi_hardware_present;
-ACPI_EXTERN u8                                  acpi_gbl_global_lock_present;
-ACPI_EXTERN u8                                  acpi_gbl_events_initialized;
-ACPI_EXTERN u8                                  acpi_gbl_system_awake_and_running;
-
-extern u8                                       acpi_gbl_shutdown;
-extern u32                                      acpi_gbl_startup_flags;
-extern const u8                                 acpi_gbl_decode_to8bit[8];
-extern const char                              *acpi_gbl_sleep_state_names[ACPI_S_STATE_COUNT];
-extern const char                              *acpi_gbl_highest_dstate_names[4];
-extern const struct acpi_opcode_info            acpi_gbl_aml_op_info[AML_NUM_OPCODES];
-extern const char                              *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS];
-extern const char                              *acpi_gbl_valid_osi_strings[ACPI_NUM_OSI_STRINGS];
+ACPI_EXTERN struct acpi_memory_list *acpi_gbl_global_list;
+ACPI_EXTERN struct acpi_memory_list *acpi_gbl_ns_node_list;
+#endif
 
+/* Object caches */
+
+ACPI_EXTERN acpi_cache_t *acpi_gbl_state_cache;
+ACPI_EXTERN acpi_cache_t *acpi_gbl_ps_node_cache;
+ACPI_EXTERN acpi_cache_t *acpi_gbl_ps_node_ext_cache;
+ACPI_EXTERN acpi_cache_t *acpi_gbl_operand_cache;
+
+/* Global handlers */
+
+ACPI_EXTERN struct acpi_object_notify_handler acpi_gbl_device_notify;
+ACPI_EXTERN struct acpi_object_notify_handler acpi_gbl_system_notify;
+ACPI_EXTERN acpi_exception_handler acpi_gbl_exception_handler;
+ACPI_EXTERN acpi_init_handler acpi_gbl_init_handler;
+ACPI_EXTERN struct acpi_walk_state *acpi_gbl_breakpoint_walk;
+ACPI_EXTERN acpi_handle acpi_gbl_global_lock_semaphore;
+
+/* Misc */
+
+ACPI_EXTERN u32 acpi_gbl_global_lock_thread_count;
+ACPI_EXTERN u32 acpi_gbl_original_mode;
+ACPI_EXTERN u32 acpi_gbl_rsdp_original_location;
+ACPI_EXTERN u32 acpi_gbl_ns_lookup_count;
+ACPI_EXTERN u32 acpi_gbl_ps_find_count;
+ACPI_EXTERN u32 acpi_gbl_owner_id_mask;
+ACPI_EXTERN u16 acpi_gbl_pm1_enable_register_save;
+ACPI_EXTERN u16 acpi_gbl_global_lock_handle;
+ACPI_EXTERN u8 acpi_gbl_debugger_configuration;
+ACPI_EXTERN u8 acpi_gbl_global_lock_acquired;
+ACPI_EXTERN u8 acpi_gbl_step_to_next_call;
+ACPI_EXTERN u8 acpi_gbl_acpi_hardware_present;
+ACPI_EXTERN u8 acpi_gbl_global_lock_present;
+ACPI_EXTERN u8 acpi_gbl_events_initialized;
+ACPI_EXTERN u8 acpi_gbl_system_awake_and_running;
+
+extern u8 acpi_gbl_shutdown;
+extern u32 acpi_gbl_startup_flags;
+extern const u8 acpi_gbl_decode_to8bit[8];
+extern const char *acpi_gbl_sleep_state_names[ACPI_S_STATE_COUNT];
+extern const char *acpi_gbl_highest_dstate_names[4];
+extern const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES];
+extern const char *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS];
+extern const char *acpi_gbl_valid_osi_strings[ACPI_NUM_OSI_STRINGS];
 
 /*****************************************************************************
  *
@@ -230,20 +245,21 @@ extern const char                              *acpi_gbl_valid_osi_strings[ACPI_
 #define NUM_PREDEFINED_NAMES            9
 #endif
 
-ACPI_EXTERN struct acpi_namespace_node          acpi_gbl_root_node_struct;
-ACPI_EXTERN struct acpi_namespace_node         *acpi_gbl_root_node;
-ACPI_EXTERN struct acpi_namespace_node         *acpi_gbl_fadt_gpe_device;
+ACPI_EXTERN struct acpi_namespace_node acpi_gbl_root_node_struct;
+ACPI_EXTERN struct acpi_namespace_node *acpi_gbl_root_node;
+ACPI_EXTERN struct acpi_namespace_node *acpi_gbl_fadt_gpe_device;
 
-extern const u8                                 acpi_gbl_ns_properties[NUM_NS_TYPES];
-extern const struct acpi_predefined_names       acpi_gbl_pre_defined_names [NUM_PREDEFINED_NAMES];
+extern const u8 acpi_gbl_ns_properties[NUM_NS_TYPES];
+extern const struct acpi_predefined_names
+    acpi_gbl_pre_defined_names[NUM_PREDEFINED_NAMES];
 
 #ifdef ACPI_DEBUG_OUTPUT
-ACPI_EXTERN u32                                 acpi_gbl_current_node_count;
-ACPI_EXTERN u32                                 acpi_gbl_current_node_size;
-ACPI_EXTERN u32                                 acpi_gbl_max_concurrent_node_count;
-ACPI_EXTERN acpi_size                           acpi_gbl_entry_stack_pointer;
-ACPI_EXTERN acpi_size                           acpi_gbl_lowest_stack_pointer;
-ACPI_EXTERN u32                                 acpi_gbl_deepest_nesting;
+ACPI_EXTERN u32 acpi_gbl_current_node_count;
+ACPI_EXTERN u32 acpi_gbl_current_node_size;
+ACPI_EXTERN u32 acpi_gbl_max_concurrent_node_count;
+ACPI_EXTERN acpi_size acpi_gbl_entry_stack_pointer;
+ACPI_EXTERN acpi_size acpi_gbl_lowest_stack_pointer;
+ACPI_EXTERN u32 acpi_gbl_deepest_nesting;
 #endif
 
 /*****************************************************************************
@@ -252,13 +268,11 @@ ACPI_EXTERN u32                                 acpi_gbl_deepest_nesting;
  *
  ****************************************************************************/
 
-
-ACPI_EXTERN struct acpi_thread_state           *acpi_gbl_current_walk_list;
+ACPI_EXTERN struct acpi_thread_state *acpi_gbl_current_walk_list;
 
 /* Control method single step flag */
 
-ACPI_EXTERN u8                                  acpi_gbl_cm_single_step;
-
+ACPI_EXTERN u8 acpi_gbl_cm_single_step;
 
 /*****************************************************************************
  *
@@ -266,7 +280,7 @@ ACPI_EXTERN u8                                  acpi_gbl_cm_single_step;
  *
  ****************************************************************************/
 
-ACPI_EXTERN union acpi_parse_object            *acpi_gbl_parsed_namespace_root;
+ACPI_EXTERN union acpi_parse_object *acpi_gbl_parsed_namespace_root;
 
 /*****************************************************************************
  *
@@ -274,10 +288,10 @@ ACPI_EXTERN union acpi_parse_object            *acpi_gbl_parsed_namespace_root;
  *
  ****************************************************************************/
 
-extern      struct acpi_bit_register_info       acpi_gbl_bit_register_info[ACPI_NUM_BITREG];
-ACPI_EXTERN u8                                  acpi_gbl_sleep_type_a;
-ACPI_EXTERN u8                                  acpi_gbl_sleep_type_b;
-
+extern struct acpi_bit_register_info
+    acpi_gbl_bit_register_info[ACPI_NUM_BITREG];
+ACPI_EXTERN u8 acpi_gbl_sleep_type_a;
+ACPI_EXTERN u8 acpi_gbl_sleep_type_b;
 
 /*****************************************************************************
  *
@@ -285,12 +299,14 @@ ACPI_EXTERN u8                                  acpi_gbl_sleep_type_b;
  *
  ****************************************************************************/
 
-extern      struct acpi_fixed_event_info        acpi_gbl_fixed_event_info[ACPI_NUM_FIXED_EVENTS];
-ACPI_EXTERN struct acpi_fixed_event_handler     acpi_gbl_fixed_event_handlers[ACPI_NUM_FIXED_EVENTS];
-ACPI_EXTERN struct acpi_gpe_xrupt_info         *acpi_gbl_gpe_xrupt_list_head;
-ACPI_EXTERN struct acpi_gpe_block_info         *acpi_gbl_gpe_fadt_blocks[ACPI_MAX_GPE_BLOCKS];
-ACPI_EXTERN acpi_handle                         acpi_gbl_gpe_lock;
-
+extern struct acpi_fixed_event_info
+    acpi_gbl_fixed_event_info[ACPI_NUM_FIXED_EVENTS];
+ACPI_EXTERN struct acpi_fixed_event_handler
+    acpi_gbl_fixed_event_handlers[ACPI_NUM_FIXED_EVENTS];
+ACPI_EXTERN struct acpi_gpe_xrupt_info *acpi_gbl_gpe_xrupt_list_head;
+ACPI_EXTERN struct acpi_gpe_block_info
+    *acpi_gbl_gpe_fadt_blocks[ACPI_MAX_GPE_BLOCKS];
+ACPI_EXTERN acpi_handle acpi_gbl_gpe_lock;
 
 /*****************************************************************************
  *
@@ -298,60 +314,55 @@ ACPI_EXTERN acpi_handle                         acpi_gbl_gpe_lock;
  *
  ****************************************************************************/
 
-
-ACPI_EXTERN u8                                  acpi_gbl_db_output_flags;
+ACPI_EXTERN u8 acpi_gbl_db_output_flags;
 
 #ifdef ACPI_DISASSEMBLER
 
-ACPI_EXTERN u8                                  acpi_gbl_db_opt_disasm;
-ACPI_EXTERN u8                                  acpi_gbl_db_opt_verbose;
+ACPI_EXTERN u8 acpi_gbl_db_opt_disasm;
+ACPI_EXTERN u8 acpi_gbl_db_opt_verbose;
 #endif
 
-
 #ifdef ACPI_DEBUGGER
 
-extern      u8                                  acpi_gbl_method_executing;
-extern      u8                                  acpi_gbl_abort_method;
-extern      u8                                  acpi_gbl_db_terminate_threads;
-
-ACPI_EXTERN int                                 optind;
-ACPI_EXTERN char                               *optarg;
-
-ACPI_EXTERN u8                                  acpi_gbl_db_opt_tables;
-ACPI_EXTERN u8                                  acpi_gbl_db_opt_stats;
-ACPI_EXTERN u8                                  acpi_gbl_db_opt_ini_methods;
-
-
-ACPI_EXTERN char                               *acpi_gbl_db_args[ACPI_DEBUGGER_MAX_ARGS];
-ACPI_EXTERN char                                acpi_gbl_db_line_buf[80];
-ACPI_EXTERN char                                acpi_gbl_db_parsed_buf[80];
-ACPI_EXTERN char                                acpi_gbl_db_scope_buf[40];
-ACPI_EXTERN char                                acpi_gbl_db_debug_filename[40];
-ACPI_EXTERN u8                                  acpi_gbl_db_output_to_file;
-ACPI_EXTERN char                               *acpi_gbl_db_buffer;
-ACPI_EXTERN char                               *acpi_gbl_db_filename;
-ACPI_EXTERN u32                                 acpi_gbl_db_debug_level;
-ACPI_EXTERN u32                                 acpi_gbl_db_console_debug_level;
-ACPI_EXTERN struct acpi_table_header           *acpi_gbl_db_table_ptr;
-ACPI_EXTERN struct acpi_namespace_node         *acpi_gbl_db_scope_node;
+extern u8 acpi_gbl_method_executing;
+extern u8 acpi_gbl_abort_method;
+extern u8 acpi_gbl_db_terminate_threads;
+
+ACPI_EXTERN int optind;
+ACPI_EXTERN char *optarg;
+
+ACPI_EXTERN u8 acpi_gbl_db_opt_tables;
+ACPI_EXTERN u8 acpi_gbl_db_opt_stats;
+ACPI_EXTERN u8 acpi_gbl_db_opt_ini_methods;
+
+ACPI_EXTERN char *acpi_gbl_db_args[ACPI_DEBUGGER_MAX_ARGS];
+ACPI_EXTERN char acpi_gbl_db_line_buf[80];
+ACPI_EXTERN char acpi_gbl_db_parsed_buf[80];
+ACPI_EXTERN char acpi_gbl_db_scope_buf[40];
+ACPI_EXTERN char acpi_gbl_db_debug_filename[40];
+ACPI_EXTERN u8 acpi_gbl_db_output_to_file;
+ACPI_EXTERN char *acpi_gbl_db_buffer;
+ACPI_EXTERN char *acpi_gbl_db_filename;
+ACPI_EXTERN u32 acpi_gbl_db_debug_level;
+ACPI_EXTERN u32 acpi_gbl_db_console_debug_level;
+ACPI_EXTERN struct acpi_table_header *acpi_gbl_db_table_ptr;
+ACPI_EXTERN struct acpi_namespace_node *acpi_gbl_db_scope_node;
 
 /*
  * Statistic globals
  */
-ACPI_EXTERN u16                                 acpi_gbl_obj_type_count[ACPI_TYPE_NS_NODE_MAX+1];
-ACPI_EXTERN u16                                 acpi_gbl_node_type_count[ACPI_TYPE_NS_NODE_MAX+1];
-ACPI_EXTERN u16                                 acpi_gbl_obj_type_count_misc;
-ACPI_EXTERN u16                                 acpi_gbl_node_type_count_misc;
-ACPI_EXTERN u32                                 acpi_gbl_num_nodes;
-ACPI_EXTERN u32                                 acpi_gbl_num_objects;
-
-
-ACPI_EXTERN u32                                 acpi_gbl_size_of_parse_tree;
-ACPI_EXTERN u32                                 acpi_gbl_size_of_method_trees;
-ACPI_EXTERN u32                                 acpi_gbl_size_of_node_entries;
-ACPI_EXTERN u32                                 acpi_gbl_size_of_acpi_objects;
+ACPI_EXTERN u16 acpi_gbl_obj_type_count[ACPI_TYPE_NS_NODE_MAX + 1];
+ACPI_EXTERN u16 acpi_gbl_node_type_count[ACPI_TYPE_NS_NODE_MAX + 1];
+ACPI_EXTERN u16 acpi_gbl_obj_type_count_misc;
+ACPI_EXTERN u16 acpi_gbl_node_type_count_misc;
+ACPI_EXTERN u32 acpi_gbl_num_nodes;
+ACPI_EXTERN u32 acpi_gbl_num_objects;
 
-#endif /* ACPI_DEBUGGER */
+ACPI_EXTERN u32 acpi_gbl_size_of_parse_tree;
+ACPI_EXTERN u32 acpi_gbl_size_of_method_trees;
+ACPI_EXTERN u32 acpi_gbl_size_of_node_entries;
+ACPI_EXTERN u32 acpi_gbl_size_of_acpi_objects;
 
+#endif                          /* ACPI_DEBUGGER */
 
-#endif /* __ACGLOBAL_H__ */
+#endif                          /* __ACGLOBAL_H__ */
diff --git a/include/acpi/achware.h b/include/acpi/achware.h
index 28ad1398c159..3644d7248e7e 100644
--- a/include/acpi/achware.h
+++ b/include/acpi/achware.h
@@ -44,139 +44,90 @@
 #ifndef __ACHWARE_H__
 #define __ACHWARE_H__
 
-
 /* PM Timer ticks per second (HZ) */
-#define PM_TIMER_FREQUENCY  3579545
-
-
-/* Prototypes */
 
+#define PM_TIMER_FREQUENCY  3579545
 
-acpi_status
-acpi_hw_initialize (
-        void);
-
-acpi_status
-acpi_hw_shutdown (
-        void);
-
-acpi_status
-acpi_hw_initialize_system_info (
-        void);
+/* Values for the _SST reserved method */
 
-acpi_status
-acpi_hw_set_mode (
-        u32                             mode);
+#define ACPI_SST_INDICATOR_OFF  0
+#define ACPI_SST_WORKING        1
+#define ACPI_SST_WAKING         2
+#define ACPI_SST_SLEEPING       3
+#define ACPI_SST_SLEEP_CONTEXT  4
 
-u32
-acpi_hw_get_mode (
-        void);
+/* Prototypes */
 
-u32
-acpi_hw_get_mode_capabilities (
-        void);
+/*
+ * hwacpi - high level functions
+ */
+acpi_status acpi_hw_initialize(void);
 
-/* Register I/O Prototypes */
+acpi_status acpi_hw_set_mode(u32 mode);
 
-struct acpi_bit_register_info *
-acpi_hw_get_bit_register_info (
-        u32                             register_id);
+u32 acpi_hw_get_mode(void);
 
-acpi_status
-acpi_hw_register_read (
-        u8                              use_lock,
-        u32                             register_id,
-        u32                             *return_value);
+/*
+ * hwregs - ACPI Register I/O
+ */
+struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id);
 
 acpi_status
-acpi_hw_register_write (
-        u8                              use_lock,
-        u32                             register_id,
-        u32                             value);
+acpi_hw_register_read(u8 use_lock, u32 register_id, u32 * return_value);
 
-acpi_status
-acpi_hw_low_level_read (
-        u32                             width,
-        u32                             *value,
-        struct acpi_generic_address     *reg);
+acpi_status acpi_hw_register_write(u8 use_lock, u32 register_id, u32 value);
 
 acpi_status
-acpi_hw_low_level_write (
-        u32                             width,
-        u32                             value,
-        struct acpi_generic_address     *reg);
+acpi_hw_low_level_read(u32 width,
+                       u32 * value, struct acpi_generic_address *reg);
 
 acpi_status
-acpi_hw_clear_acpi_status (
-        u32                             flags);
-
+acpi_hw_low_level_write(u32 width, u32 value, struct acpi_generic_address *reg);
 
-/* GPE support */
+acpi_status acpi_hw_clear_acpi_status(u32 flags);
 
+/*
+ * hwgpe - GPE support
+ */
 acpi_status
-acpi_hw_write_gpe_enable_reg (
-        struct acpi_gpe_event_info      *gpe_event_info);
+acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info *gpe_event_info);
 
 acpi_status
-acpi_hw_disable_gpe_block (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
+acpi_hw_disable_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
+                          struct acpi_gpe_block_info *gpe_block);
 
-acpi_status
-acpi_hw_clear_gpe (
-        struct acpi_gpe_event_info      *gpe_event_info);
+acpi_status acpi_hw_clear_gpe(struct acpi_gpe_event_info *gpe_event_info);
 
 acpi_status
-acpi_hw_clear_gpe_block (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
+acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
+                        struct acpi_gpe_block_info *gpe_block);
 
-#ifdef ACPI_FUTURE_USAGE
+#ifdef  ACPI_FUTURE_USAGE
 acpi_status
-acpi_hw_get_gpe_status (
-        struct acpi_gpe_event_info      *gpe_event_info,
-        acpi_event_status               *event_status);
-#endif
+acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
+                       acpi_event_status * event_status);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-acpi_status
-acpi_hw_disable_all_gpes (
-        u32                             flags);
+acpi_status acpi_hw_disable_all_gpes(void);
 
-acpi_status
-acpi_hw_enable_all_runtime_gpes (
-        u32                             flags);
+acpi_status acpi_hw_enable_all_runtime_gpes(void);
 
-acpi_status
-acpi_hw_enable_all_wakeup_gpes (
-        u32                             flags);
+acpi_status acpi_hw_enable_all_wakeup_gpes(void);
 
 acpi_status
-acpi_hw_enable_runtime_gpe_block (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
+acpi_hw_enable_runtime_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
+                                 struct acpi_gpe_block_info *gpe_block);
 
-acpi_status
-acpi_hw_enable_wakeup_gpe_block (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
-
-
-/* ACPI Timer prototypes */
-
-#ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_get_timer_resolution (
-        u32                             *resolution);
+#ifdef  ACPI_FUTURE_USAGE
+/*
+ * hwtimer - ACPI Timer prototypes
+ */
+acpi_status acpi_get_timer_resolution(u32 * resolution);
 
-acpi_status
-acpi_get_timer (
-        u32                             *ticks);
+acpi_status acpi_get_timer(u32 * ticks);
 
 acpi_status
-acpi_get_timer_duration (
-        u32                             start_ticks,
-        u32                             end_ticks,
-        u32                             *time_elapsed);
-#endif  /*  ACPI_FUTURE_USAGE  */
+acpi_get_timer_duration(u32 start_ticks, u32 end_ticks, u32 * time_elapsed);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-#endif /* __ACHWARE_H__ */
+#endif                          /* __ACHWARE_H__ */
diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h
index c5301f5ffaf4..2c9c1a1d1b7f 100644
--- a/include/acpi/acinterp.h
+++ b/include/acpi/acinterp.h
@@ -44,57 +44,22 @@
 #ifndef __ACINTERP_H__
 #define __ACINTERP_H__
 
-
 #define ACPI_WALK_OPERANDS       (&(walk_state->operands [walk_state->num_operands -1]))
 
-
-acpi_status
-acpi_ex_resolve_operands (
-        u16                             opcode,
-        union acpi_operand_object       **stack_ptr,
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ex_check_object_type (
-        acpi_object_type                type_needed,
-        acpi_object_type                this_type,
-        void                            *object);
-
-/*
- * exxface - External interpreter interfaces
- */
-
-acpi_status
-acpi_ex_load_table (
-        acpi_table_type                 table_id);
-
-acpi_status
-acpi_ex_execute_method (
-        struct acpi_namespace_node      *method_node,
-        union acpi_operand_object       **params,
-        union acpi_operand_object       **return_obj_desc);
-
-
 /*
  * exconvrt - object conversion
  */
-
 acpi_status
-acpi_ex_convert_to_integer (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **result_desc,
-        u32                             flags);
+acpi_ex_convert_to_integer(union acpi_operand_object *obj_desc,
+                           union acpi_operand_object **result_desc, u32 flags);
 
 acpi_status
-acpi_ex_convert_to_buffer (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **result_desc);
+acpi_ex_convert_to_buffer(union acpi_operand_object *obj_desc,
+                          union acpi_operand_object **result_desc);
 
 acpi_status
-acpi_ex_convert_to_string (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **result_desc,
-        u32                             type);
+acpi_ex_convert_to_string(union acpi_operand_object *obj_desc,
+                          union acpi_operand_object **result_desc, u32 type);
 
 /* Types for ->String conversion */
 
@@ -104,662 +69,412 @@ acpi_ex_convert_to_string (
 #define ACPI_EXPLICIT_CONVERT_DECIMAL   0x00000003
 
 acpi_status
-acpi_ex_convert_to_target_type (
-        acpi_object_type                destination_type,
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       **result_desc,
-        struct acpi_walk_state          *walk_state);
-
-u32
-acpi_ex_convert_to_ascii (
-        acpi_integer                    integer,
-        u16                             base,
-        u8                              *string,
-        u8                              max_length);
+acpi_ex_convert_to_target_type(acpi_object_type destination_type,
+                               union acpi_operand_object *source_desc,
+                               union acpi_operand_object **result_desc,
+                               struct acpi_walk_state *walk_state);
 
 /*
  * exfield - ACPI AML (p-code) execution - field manipulation
  */
-
-acpi_status
-acpi_ex_common_buffer_setup (
-        union acpi_operand_object       *obj_desc,
-        u32                             buffer_length,
-        u32                             *datum_count);
-
-acpi_status
-acpi_ex_extract_from_field (
-        union acpi_operand_object       *obj_desc,
-        void                            *buffer,
-        u32                             buffer_length);
-
-acpi_status
-acpi_ex_insert_into_field (
-        union acpi_operand_object       *obj_desc,
-        void                            *buffer,
-        u32                             buffer_length);
-
 acpi_status
-acpi_ex_setup_region (
-        union acpi_operand_object       *obj_desc,
-        u32                             field_datum_byte_offset);
+acpi_ex_common_buffer_setup(union acpi_operand_object *obj_desc,
+                            u32 buffer_length, u32 * datum_count);
 
 acpi_status
-acpi_ex_access_region (
-        union acpi_operand_object       *obj_desc,
-        u32                             field_datum_byte_offset,
-        acpi_integer                    *value,
-        u32                             read_write);
-
-u8
-acpi_ex_register_overflow (
-        union acpi_operand_object       *obj_desc,
-        acpi_integer                    value);
-
-acpi_status
-acpi_ex_field_datum_io (
-        union acpi_operand_object       *obj_desc,
-        u32                             field_datum_byte_offset,
-        acpi_integer                    *value,
-        u32                             read_write);
-
-acpi_status
-acpi_ex_write_with_update_rule (
-        union acpi_operand_object       *obj_desc,
-        acpi_integer                    mask,
-        acpi_integer                    field_value,
-        u32                             field_datum_byte_offset);
+acpi_ex_write_with_update_rule(union acpi_operand_object *obj_desc,
+                               acpi_integer mask,
+                               acpi_integer field_value,
+                               u32 field_datum_byte_offset);
 
 void
-acpi_ex_get_buffer_datum(
-        acpi_integer                    *datum,
-        void                            *buffer,
-        u32                             buffer_length,
-        u32                             byte_granularity,
-        u32                             buffer_offset);
+acpi_ex_get_buffer_datum(acpi_integer * datum,
+                         void *buffer,
+                         u32 buffer_length,
+                         u32 byte_granularity, u32 buffer_offset);
 
 void
-acpi_ex_set_buffer_datum (
-        acpi_integer                    merged_datum,
-        void                            *buffer,
-        u32                             buffer_length,
-        u32                             byte_granularity,
-        u32                             buffer_offset);
+acpi_ex_set_buffer_datum(acpi_integer merged_datum,
+                         void *buffer,
+                         u32 buffer_length,
+                         u32 byte_granularity, u32 buffer_offset);
 
 acpi_status
-acpi_ex_read_data_from_field (
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **ret_buffer_desc);
+acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state,
+                             union acpi_operand_object *obj_desc,
+                             union acpi_operand_object **ret_buffer_desc);
 
 acpi_status
-acpi_ex_write_data_to_field (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **result_desc);
+acpi_ex_write_data_to_field(union acpi_operand_object *source_desc,
+                            union acpi_operand_object *obj_desc,
+                            union acpi_operand_object **result_desc);
 
 /*
- * exmisc - ACPI AML (p-code) execution - specific opcodes
+ * exfldio - low level field I/O
  */
-
-acpi_status
-acpi_ex_opcode_3A_0T_0R (
-        struct acpi_walk_state          *walk_state);
-
 acpi_status
-acpi_ex_opcode_3A_1T_1R (
-        struct acpi_walk_state          *walk_state);
+acpi_ex_extract_from_field(union acpi_operand_object *obj_desc,
+                           void *buffer, u32 buffer_length);
 
 acpi_status
-acpi_ex_opcode_6A_0T_1R (
-        struct acpi_walk_state          *walk_state);
-
-u8
-acpi_ex_do_match (
-        u32                             match_op,
-        union acpi_operand_object       *package_obj,
-        union acpi_operand_object       *match_obj);
+acpi_ex_insert_into_field(union acpi_operand_object *obj_desc,
+                          void *buffer, u32 buffer_length);
 
 acpi_status
-acpi_ex_get_object_reference (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       **return_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_access_region(union acpi_operand_object *obj_desc,
+                      u32 field_datum_byte_offset,
+                      acpi_integer * value, u32 read_write);
 
+/*
+ * exmisc - misc support routines
+ */
 acpi_status
-acpi_ex_resolve_multiple (
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       *operand,
-        acpi_object_type                *return_type,
-        union acpi_operand_object       **return_desc);
+acpi_ex_get_object_reference(union acpi_operand_object *obj_desc,
+                             union acpi_operand_object **return_desc,
+                             struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_concat_template (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       *obj_desc2,
-        union acpi_operand_object       **actual_return_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_concat_template(union acpi_operand_object *obj_desc,
+                        union acpi_operand_object *obj_desc2,
+                        union acpi_operand_object **actual_return_desc,
+                        struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_do_concatenate (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       *obj_desc2,
-        union acpi_operand_object       **actual_return_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_do_concatenate(union acpi_operand_object *obj_desc,
+                       union acpi_operand_object *obj_desc2,
+                       union acpi_operand_object **actual_return_desc,
+                       struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_do_logical_numeric_op (
-        u16                             opcode,
-        acpi_integer                    integer0,
-        acpi_integer                    integer1,
-        u8                              *logical_result);
+acpi_ex_do_logical_numeric_op(u16 opcode,
+                              acpi_integer integer0,
+                              acpi_integer integer1, u8 * logical_result);
 
 acpi_status
-acpi_ex_do_logical_op (
-        u16                             opcode,
-        union acpi_operand_object       *operand0,
-        union acpi_operand_object       *operand1,
-        u8                              *logical_result);
+acpi_ex_do_logical_op(u16 opcode,
+                      union acpi_operand_object *operand0,
+                      union acpi_operand_object *operand1, u8 * logical_result);
 
 acpi_integer
-acpi_ex_do_math_op (
-        u16                             opcode,
-        acpi_integer                    operand0,
-        acpi_integer                    operand1);
+acpi_ex_do_math_op(u16 opcode, acpi_integer operand0, acpi_integer operand1);
 
-acpi_status
-acpi_ex_create_mutex (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_mutex(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_create_processor (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_processor(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_create_power_resource (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_power_resource(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_create_region (
-        u8                              *aml_start,
-        u32                             aml_length,
-        u8                              region_space,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_create_region(u8 * aml_start,
+                      u32 aml_length,
+                      u8 region_space, struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_create_table_region (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_table_region(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_create_event (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_event(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_create_alias (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_create_alias(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_create_method (
-        u8                              *aml_start,
-        u32                             aml_length,
-        struct acpi_walk_state          *walk_state);
-
+acpi_ex_create_method(u8 * aml_start,
+                      u32 aml_length, struct acpi_walk_state *walk_state);
 
 /*
  * exconfig - dynamic table load/unload
  */
-
-acpi_status
-acpi_ex_add_table (
-        struct acpi_table_header        *table,
-        struct acpi_namespace_node      *parent_node,
-        union acpi_operand_object       **ddb_handle);
-
-acpi_status
-acpi_ex_load_op (
-        union acpi_operand_object       *obj_desc,
-        union acpi_operand_object       *target,
-        struct acpi_walk_state          *walk_state);
-
 acpi_status
-acpi_ex_load_table_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_operand_object       **return_desc);
+acpi_ex_load_op(union acpi_operand_object *obj_desc,
+                union acpi_operand_object *target,
+                struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_unload_table (
-        union acpi_operand_object       *ddb_handle);
+acpi_ex_load_table_op(struct acpi_walk_state *walk_state,
+                      union acpi_operand_object **return_desc);
 
+acpi_status acpi_ex_unload_table(union acpi_operand_object *ddb_handle);
 
 /*
  * exmutex - mutex support
  */
-
 acpi_status
-acpi_ex_acquire_mutex (
-        union acpi_operand_object       *time_desc,
-        union acpi_operand_object       *obj_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_acquire_mutex(union acpi_operand_object *time_desc,
+                      union acpi_operand_object *obj_desc,
+                      struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_release_mutex (
-        union acpi_operand_object       *obj_desc,
-        struct acpi_walk_state          *walk_state);
-
-void
-acpi_ex_release_all_mutexes (
-        struct acpi_thread_state        *thread);
+acpi_ex_release_mutex(union acpi_operand_object *obj_desc,
+                      struct acpi_walk_state *walk_state);
 
-void
-acpi_ex_unlink_mutex (
-        union acpi_operand_object       *obj_desc);
+void acpi_ex_release_all_mutexes(struct acpi_thread_state *thread);
 
-void
-acpi_ex_link_mutex (
-        union acpi_operand_object       *obj_desc,
-        struct acpi_thread_state        *thread);
+void acpi_ex_unlink_mutex(union acpi_operand_object *obj_desc);
 
 /*
- * exprep - ACPI AML (p-code) execution - prep utilities
+ * exprep - ACPI AML execution - prep utilities
  */
-
 acpi_status
-acpi_ex_prep_common_field_object (
-        union acpi_operand_object       *obj_desc,
-        u8                              field_flags,
-        u8                              field_attribute,
-        u32                             field_bit_position,
-        u32                             field_bit_length);
+acpi_ex_prep_common_field_object(union acpi_operand_object *obj_desc,
+                                 u8 field_flags,
+                                 u8 field_attribute,
+                                 u32 field_bit_position, u32 field_bit_length);
 
-acpi_status
-acpi_ex_prep_field_value (
-        struct acpi_create_field_info   *info);
+acpi_status acpi_ex_prep_field_value(struct acpi_create_field_info *info);
 
 /*
  * exsystem - Interface to OS services
  */
-
 acpi_status
-acpi_ex_system_do_notify_op (
-        union acpi_operand_object       *value,
-        union acpi_operand_object       *obj_desc);
+acpi_ex_system_do_notify_op(union acpi_operand_object *value,
+                            union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ex_system_do_suspend(
-        acpi_integer                    time);
+acpi_status acpi_ex_system_do_suspend(acpi_integer time);
 
-acpi_status
-acpi_ex_system_do_stall (
-        u32                             time);
+acpi_status acpi_ex_system_do_stall(u32 time);
 
 acpi_status
-acpi_ex_system_acquire_mutex(
-        union acpi_operand_object       *time,
-        union acpi_operand_object       *obj_desc);
+acpi_ex_system_acquire_mutex(union acpi_operand_object *time,
+                             union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ex_system_release_mutex(
-        union acpi_operand_object       *obj_desc);
+acpi_status acpi_ex_system_release_mutex(union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ex_system_signal_event(
-        union acpi_operand_object       *obj_desc);
+acpi_status acpi_ex_system_signal_event(union acpi_operand_object *obj_desc);
 
 acpi_status
-acpi_ex_system_wait_event(
-        union acpi_operand_object       *time,
-        union acpi_operand_object       *obj_desc);
+acpi_ex_system_wait_event(union acpi_operand_object *time,
+                          union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ex_system_reset_event(
-        union acpi_operand_object       *obj_desc);
-
-acpi_status
-acpi_ex_system_wait_semaphore (
-        acpi_handle                     semaphore,
-        u16                             timeout);
+acpi_status acpi_ex_system_reset_event(union acpi_operand_object *obj_desc);
 
+acpi_status acpi_ex_system_wait_semaphore(acpi_handle semaphore, u16 timeout);
 
 /*
- * exmonadic - ACPI AML (p-code) execution, monadic operators
+ * exoparg1 - ACPI AML execution, 1 operand
  */
+acpi_status acpi_ex_opcode_0A_0T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_0A_0T_1R (
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ex_opcode_1A_0T_0R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_1A_0T_0R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_1A_0T_1R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_1A_0T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_1A_1T_1R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_1A_1T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_1A_1T_0R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_1A_1T_0R(struct acpi_walk_state *walk_state);
 
 /*
- * exdyadic - ACPI AML (p-code) execution, dyadic operators
+ * exoparg2 - ACPI AML execution, 2 operands
  */
+acpi_status acpi_ex_opcode_2A_0T_0R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_2A_0T_0R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_2A_0T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_2A_0T_1R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_2A_1T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_2A_1T_1R (
-        struct acpi_walk_state          *walk_state);
+acpi_status acpi_ex_opcode_2A_2T_1R(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ex_opcode_2A_2T_1R (
-        struct acpi_walk_state          *walk_state);
+/*
+ * exoparg3 - ACPI AML execution, 3 operands
+ */
+acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state);
 
+acpi_status acpi_ex_opcode_3A_1T_1R(struct acpi_walk_state *walk_state);
 
 /*
- * exresolv  - Object resolution and get value functions
+ * exoparg6 - ACPI AML execution, 6 operands
  */
+acpi_status acpi_ex_opcode_6A_0T_1R(struct acpi_walk_state *walk_state);
 
+/*
+ * exresolv - Object resolution and get value functions
+ */
 acpi_status
-acpi_ex_resolve_to_value (
-        union acpi_operand_object       **stack_ptr,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_resolve_to_value(union acpi_operand_object **stack_ptr,
+                         struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_resolve_node_to_value (
-        struct acpi_namespace_node      **stack_ptr,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_resolve_multiple(struct acpi_walk_state *walk_state,
+                         union acpi_operand_object *operand,
+                         acpi_object_type * return_type,
+                         union acpi_operand_object **return_desc);
 
+/*
+ * exresnte - resolve namespace node
+ */
 acpi_status
-acpi_ex_resolve_object_to_value (
-        union acpi_operand_object       **stack_ptr,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_resolve_node_to_value(struct acpi_namespace_node **stack_ptr,
+                              struct acpi_walk_state *walk_state);
 
+/*
+ * exresop - resolve operand to value
+ */
+acpi_status
+acpi_ex_resolve_operands(u16 opcode,
+                         union acpi_operand_object **stack_ptr,
+                         struct acpi_walk_state *walk_state);
 
 /*
  * exdump - Interpreter debug output routines
  */
+void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth);
 
 void
-acpi_ex_dump_operand (
-        union acpi_operand_object       *obj_desc,
-        u32                             depth);
-
-void
-acpi_ex_dump_operands (
-        union acpi_operand_object       **operands,
-        acpi_interpreter_mode           interpreter_mode,
-        char                            *ident,
-        u32                             num_levels,
-        char                            *note,
-        char                            *module_name,
-        u32                             line_number);
-
-#ifdef ACPI_FUTURE_USAGE
-void
-acpi_ex_dump_object_descriptor (
-        union acpi_operand_object       *object,
-        u32                             flags);
+acpi_ex_dump_operands(union acpi_operand_object **operands,
+                      acpi_interpreter_mode interpreter_mode,
+                      char *ident,
+                      u32 num_levels,
+                      char *note, char *module_name, u32 line_number);
 
+#ifdef  ACPI_FUTURE_USAGE
 void
-acpi_ex_dump_node (
-        struct acpi_namespace_node      *node,
-        u32                             flags);
+acpi_ex_dump_object_descriptor(union acpi_operand_object *object, u32 flags);
 
-void
-acpi_ex_out_string (
-        char                            *title,
-        char                            *value);
-
-void
-acpi_ex_out_pointer (
-        char                            *title,
-        void                            *value);
-
-void
-acpi_ex_out_integer (
-        char                            *title,
-        u32                             value);
-
-void
-acpi_ex_out_address (
-        char                            *title,
-        acpi_physical_address           value);
-#endif  /*  ACPI_FUTURE_USAGE  */
+void acpi_ex_dump_node(struct acpi_namespace_node *node, u32 flags);
+#endif                          /* ACPI_FUTURE_USAGE */
 
 /*
- * exnames - interpreter/scanner name load/execute
+ * exnames - AML namestring support
  */
-
-char *
-acpi_ex_allocate_name_string (
-        u32                             prefix_count,
-        u32                             num_name_segs);
-
-u32
-acpi_ex_good_char (
-        u32                             character);
-
-acpi_status
-acpi_ex_name_segment (
-        u8                              **in_aml_address,
-        char                            *name_string);
-
-acpi_status
-acpi_ex_get_name_string (
-        acpi_object_type                data_type,
-        u8                              *in_aml_address,
-        char                            **out_name_string,
-        u32                             *out_name_length);
-
 acpi_status
-acpi_ex_do_name (
-        acpi_object_type                data_type,
-        acpi_interpreter_mode           load_exec_mode);
-
+acpi_ex_get_name_string(acpi_object_type data_type,
+                        u8 * in_aml_address,
+                        char **out_name_string, u32 * out_name_length);
 
 /*
  * exstore - Object store support
  */
-
-acpi_status
-acpi_ex_store (
-        union acpi_operand_object       *val_desc,
-        union acpi_operand_object       *dest_desc,
-        struct acpi_walk_state          *walk_state);
-
 acpi_status
-acpi_ex_store_object_to_index (
-        union acpi_operand_object       *val_desc,
-        union acpi_operand_object       *dest_desc,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_store(union acpi_operand_object *val_desc,
+              union acpi_operand_object *dest_desc,
+              struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_store_object_to_node (
-        union acpi_operand_object       *source_desc,
-        struct acpi_namespace_node      *node,
-        struct acpi_walk_state          *walk_state,
-        u8                              implicit_conversion);
+acpi_ex_store_object_to_node(union acpi_operand_object *source_desc,
+                             struct acpi_namespace_node *node,
+                             struct acpi_walk_state *walk_state,
+                             u8 implicit_conversion);
 
 #define ACPI_IMPLICIT_CONVERSION        TRUE
 #define ACPI_NO_IMPLICIT_CONVERSION     FALSE
 
 /*
- * exstoren
+ * exstoren - resolve/store object
  */
-
 acpi_status
-acpi_ex_resolve_object (
-        union acpi_operand_object       **source_desc_ptr,
-        acpi_object_type                target_type,
-        struct acpi_walk_state          *walk_state);
+acpi_ex_resolve_object(union acpi_operand_object **source_desc_ptr,
+                       acpi_object_type target_type,
+                       struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ex_store_object_to_object (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *dest_desc,
-        union acpi_operand_object       **new_desc,
-        struct acpi_walk_state          *walk_state);
-
+acpi_ex_store_object_to_object(union acpi_operand_object *source_desc,
+                               union acpi_operand_object *dest_desc,
+                               union acpi_operand_object **new_desc,
+                               struct acpi_walk_state *walk_state);
 
 /*
- * excopy - object copy
+ * exstorob - store object - buffer/string
  */
-
 acpi_status
-acpi_ex_store_buffer_to_buffer (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *target_desc);
+acpi_ex_store_buffer_to_buffer(union acpi_operand_object *source_desc,
+                               union acpi_operand_object *target_desc);
 
 acpi_status
-acpi_ex_store_string_to_string (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *target_desc);
+acpi_ex_store_string_to_string(union acpi_operand_object *source_desc,
+                               union acpi_operand_object *target_desc);
 
+/*
+ * excopy - object copy
+ */
 acpi_status
-acpi_ex_copy_integer_to_index_field (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *target_desc);
+acpi_ex_copy_integer_to_index_field(union acpi_operand_object *source_desc,
+                                    union acpi_operand_object *target_desc);
 
 acpi_status
-acpi_ex_copy_integer_to_bank_field (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *target_desc);
+acpi_ex_copy_integer_to_bank_field(union acpi_operand_object *source_desc,
+                                   union acpi_operand_object *target_desc);
 
 acpi_status
-acpi_ex_copy_data_to_named_field (
-        union acpi_operand_object       *source_desc,
-        struct acpi_namespace_node      *node);
+acpi_ex_copy_data_to_named_field(union acpi_operand_object *source_desc,
+                                 struct acpi_namespace_node *node);
 
 acpi_status
-acpi_ex_copy_integer_to_buffer_field (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *target_desc);
+acpi_ex_copy_integer_to_buffer_field(union acpi_operand_object *source_desc,
+                                     union acpi_operand_object *target_desc);
 
 /*
  * exutils - interpreter/scanner utilities
  */
+acpi_status acpi_ex_enter_interpreter(void);
 
-acpi_status
-acpi_ex_enter_interpreter (
-        void);
-
-void
-acpi_ex_exit_interpreter (
-        void);
-
-void
-acpi_ex_truncate_for32bit_table (
-        union acpi_operand_object       *obj_desc);
+void acpi_ex_exit_interpreter(void);
 
-u8
-acpi_ex_acquire_global_lock (
-        u32                             rule);
+void acpi_ex_truncate_for32bit_table(union acpi_operand_object *obj_desc);
 
-void
-acpi_ex_release_global_lock (
-        u8                              locked);
+u8 acpi_ex_acquire_global_lock(u32 rule);
 
-u32
-acpi_ex_digits_needed (
-        acpi_integer                    value,
-        u32                             base);
+void acpi_ex_release_global_lock(u8 locked);
 
-void
-acpi_ex_eisa_id_to_string (
-        u32                             numeric_id,
-        char                            *out_string);
-
-void
-acpi_ex_unsigned_integer_to_string (
-        acpi_integer                    value,
-        char                            *out_string);
+void acpi_ex_eisa_id_to_string(u32 numeric_id, char *out_string);
 
+void acpi_ex_unsigned_integer_to_string(acpi_integer value, char *out_string);
 
 /*
  * exregion - default op_region handlers
  */
-
 acpi_status
-acpi_ex_system_memory_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_system_memory_space_handler(u32 function,
+                                    acpi_physical_address address,
+                                    u32 bit_width,
+                                    acpi_integer * value,
+                                    void *handler_context,
+                                    void *region_context);
 
 acpi_status
-acpi_ex_system_io_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_system_io_space_handler(u32 function,
+                                acpi_physical_address address,
+                                u32 bit_width,
+                                acpi_integer * value,
+                                void *handler_context, void *region_context);
 
 acpi_status
-acpi_ex_pci_config_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_pci_config_space_handler(u32 function,
+                                 acpi_physical_address address,
+                                 u32 bit_width,
+                                 acpi_integer * value,
+                                 void *handler_context, void *region_context);
 
 acpi_status
-acpi_ex_cmos_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_cmos_space_handler(u32 function,
+                           acpi_physical_address address,
+                           u32 bit_width,
+                           acpi_integer * value,
+                           void *handler_context, void *region_context);
 
 acpi_status
-acpi_ex_pci_bar_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_pci_bar_space_handler(u32 function,
+                              acpi_physical_address address,
+                              u32 bit_width,
+                              acpi_integer * value,
+                              void *handler_context, void *region_context);
 
 acpi_status
-acpi_ex_embedded_controller_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_embedded_controller_space_handler(u32 function,
+                                          acpi_physical_address address,
+                                          u32 bit_width,
+                                          acpi_integer * value,
+                                          void *handler_context,
+                                          void *region_context);
 
 acpi_status
-acpi_ex_sm_bus_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
-
+acpi_ex_sm_bus_space_handler(u32 function,
+                             acpi_physical_address address,
+                             u32 bit_width,
+                             acpi_integer * value,
+                             void *handler_context, void *region_context);
 
 acpi_status
-acpi_ex_data_table_space_handler (
-        u32                             function,
-        acpi_physical_address           address,
-        u32                             bit_width,
-        acpi_integer                    *value,
-        void                            *handler_context,
-        void                            *region_context);
+acpi_ex_data_table_space_handler(u32 function,
+                                 acpi_physical_address address,
+                                 u32 bit_width,
+                                 acpi_integer * value,
+                                 void *handler_context, void *region_context);
 
-#endif /* __INTERP_H__ */
+#endif                          /* __INTERP_H__ */
diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h
index 01d3b4bc0c85..9fba0fddda90 100644
--- a/include/acpi/aclocal.h
+++ b/include/acpi/aclocal.h
@@ -44,17 +44,20 @@
 #ifndef __ACLOCAL_H__
 #define __ACLOCAL_H__
 
+#define ACPI_WAIT_FOREVER               0xFFFF  /* u16, as per ACPI spec */
 
-#define ACPI_WAIT_FOREVER               0xFFFF  /* u16, as per ACPI spec */
-
-typedef void *                                  acpi_mutex;
-typedef u32                                     acpi_mutex_handle;
-
+typedef void *acpi_mutex;
+typedef u32 acpi_mutex_handle;
 
 /* Total number of aml opcodes defined */
 
 #define AML_NUM_OPCODES                 0x7F
 
+/* Forward declarations */
+
+struct acpi_walk_state;
+struct acpi_obj_mutex;
+union acpi_parse_object;
 
 /*****************************************************************************
  *
@@ -62,7 +65,6 @@ typedef u32                                     acpi_mutex_handle;
  *
  ****************************************************************************/
 
-
 /*
  * Predefined handles for the mutex objects used within the subsystem
  * All mutex objects are automatically created by acpi_ut_mutex_initialize.
@@ -72,7 +74,6 @@ typedef u32                                     acpi_mutex_handle;
  *
  * NOTE: any changes here must be reflected in the acpi_gbl_mutex_names table also!
  */
-
 #define ACPI_MTX_EXECUTE                0
 #define ACPI_MTX_INTERPRETER            1
 #define ACPI_MTX_PARSER                 2
@@ -90,14 +91,12 @@ typedef u32                                     acpi_mutex_handle;
 #define MAX_MUTEX                       12
 #define NUM_MUTEX                       MAX_MUTEX+1
 
-
 #if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DEBUGGER)
 #ifdef DEFINE_ACPI_GLOBALS
 
 /* Names for the mutexes used in the subsystem */
 
-static char                         *acpi_gbl_mutex_names[] =
-{
+static char *acpi_gbl_mutex_names[] = {
         "ACPI_MTX_Execute",
         "ACPI_MTX_Interpreter",
         "ACPI_MTX_Parser",
@@ -116,34 +115,28 @@ static char                         *acpi_gbl_mutex_names[] =
 #endif
 #endif
 
+/* Owner IDs are used to track namespace nodes for selective deletion */
 
-/* Table for the global mutexes */
+typedef u8 acpi_owner_id;
+#define ACPI_OWNER_ID_MAX               0xFF
 
-struct acpi_mutex_info
-{
-        acpi_mutex                          mutex;
-        u32                                 use_count;
-        u32                                 owner_id;
-};
+/* This Thread ID means that the mutex is not in use (unlocked) */
 
-/* This owner ID means that the mutex is not in use (unlocked) */
+#define ACPI_MUTEX_NOT_ACQUIRED         (u32) -1
 
-#define ACPI_MUTEX_NOT_ACQUIRED         (u32) (-1)
+/* Table for the global mutexes */
 
+struct acpi_mutex_info {
+        acpi_mutex mutex;
+        u32 use_count;
+        u32 thread_id;
+};
 
 /* Lock flag parameter for various interfaces */
 
 #define ACPI_MTX_DO_NOT_LOCK            0
 #define ACPI_MTX_LOCK                   1
 
-
-typedef u16                                     acpi_owner_id;
-#define ACPI_OWNER_TYPE_TABLE           0x0
-#define ACPI_OWNER_TYPE_METHOD          0x1
-#define ACPI_FIRST_METHOD_ID            0x0001
-#define ACPI_FIRST_TABLE_ID             0xF000
-
-
 /* Field access granularities */
 
 #define ACPI_FIELD_BYTE_GRANULARITY     1
@@ -157,18 +150,14 @@ typedef u16                                     acpi_owner_id;
  *
  ****************************************************************************/
 
-
 /* Operational modes of the AML interpreter/scanner */
 
-typedef enum
-{
-        ACPI_IMODE_LOAD_PASS1               = 0x01,
-        ACPI_IMODE_LOAD_PASS2               = 0x02,
-        ACPI_IMODE_EXECUTE                  = 0x0E
-
+typedef enum {
+        ACPI_IMODE_LOAD_PASS1 = 0x01,
+        ACPI_IMODE_LOAD_PASS2 = 0x02,
+        ACPI_IMODE_EXECUTE = 0x0E
 } acpi_interpreter_mode;
 
-
 /*
  * The Node describes a named object that appears in the AML
  * An acpi_node is used to store Nodes.
@@ -176,35 +165,37 @@ typedef enum
  * data_type is used to differentiate between internal descriptors, and MUST
  * be the first byte in this structure.
  */
-
-union acpi_name_union
-{
-        u32                                 integer;
-        char                                ascii[4];
-};
-
-struct acpi_namespace_node
-{
-        u8                                  descriptor;     /* Used to differentiate object descriptor types */
-        u8                                  type;           /* Type associated with this name */
-        u16                                 owner_id;
-        union acpi_name_union               name;           /* ACPI Name, always 4 chars per ACPI spec */
-        union acpi_operand_object           *object;        /* Pointer to attached ACPI object (optional) */
-        struct acpi_namespace_node          *child;         /* First child */
-        struct acpi_namespace_node          *peer;          /* Next peer*/
-        u16                                 reference_count; /* Current count of references and children */
-        u8                                  flags;
+union acpi_name_union {
+        u32 integer;
+        char ascii[4];
+};
+
+struct acpi_namespace_node {
+        u8 descriptor;          /* Used to differentiate object descriptor types */
+        u8 type;                /* Type associated with this name */
+        u16 reference_count;    /* Current count of references and children */
+        union acpi_name_union name;     /* ACPI Name, always 4 chars per ACPI spec */
+        union acpi_operand_object *object;      /* Pointer to attached ACPI object (optional) */
+        struct acpi_namespace_node *child;      /* First child */
+        struct acpi_namespace_node *peer;       /* Next peer */
+        u8 owner_id;            /* Who created this node */
+        u8 flags;
+
+        /* Fields used by the ASL compiler only */
+
+#ifdef ACPI_ASL_COMPILER
+        u32 value;
+        union acpi_parse_object *op;
+#endif
 };
 
-
 #define ACPI_ENTRY_NOT_FOUND            NULL
 
-
 /* Node flags */
 
 #define ANOBJ_RESERVED                  0x01
 #define ANOBJ_END_OF_PEER_LIST          0x02
-#define ANOBJ_DATA_WIDTH_32             0x04     /* Parent table is 64-bits */
+#define ANOBJ_DATA_WIDTH_32             0x04    /* Parent table is 64-bits */
 #define ANOBJ_METHOD_ARG                0x08
 #define ANOBJ_METHOD_LOCAL              0x10
 #define ANOBJ_METHOD_NO_RETVAL          0x20
@@ -214,91 +205,77 @@ struct acpi_namespace_node
 /*
  * ACPI Table Descriptor.  One per ACPI table
  */
-struct acpi_table_desc
-{
-        struct acpi_table_desc          *prev;
-        struct acpi_table_desc          *next;
-        struct acpi_table_desc          *installed_desc;
-        struct acpi_table_header        *pointer;
-        u8                              *aml_start;
-        u64                             physical_address;
-        u32                             aml_length;
-        acpi_size                       length;
-        acpi_owner_id                   table_id;
-        u8                              type;
-        u8                              allocation;
-        u8                              loaded_into_namespace;
+struct acpi_table_desc {
+        struct acpi_table_desc *prev;
+        struct acpi_table_desc *next;
+        struct acpi_table_desc *installed_desc;
+        struct acpi_table_header *pointer;
+        u8 *aml_start;
+        u64 physical_address;
+        u32 aml_length;
+        acpi_size length;
+        acpi_owner_id owner_id;
+        u8 type;
+        u8 allocation;
+        u8 loaded_into_namespace;
 };
 
-struct acpi_table_list
-{
-        struct acpi_table_desc          *next;
-        u32                             count;
+struct acpi_table_list {
+        struct acpi_table_desc *next;
+        u32 count;
 };
 
-
-struct acpi_find_context
-{
-        char                            *search_for;
-        acpi_handle                     *list;
-        u32                             *count;
+struct acpi_find_context {
+        char *search_for;
+        acpi_handle *list;
+        u32 *count;
 };
 
-
-struct acpi_ns_search_data
-{
-        struct acpi_namespace_node      *node;
+struct acpi_ns_search_data {
+        struct acpi_namespace_node *node;
 };
 
-
 /*
  * Predefined Namespace items
  */
-struct acpi_predefined_names
-{
-        char                            *name;
-        u8                              type;
-        char                            *val;
+struct acpi_predefined_names {
+        char *name;
+        u8 type;
+        char *val;
 };
 
-
 /* Object types used during package copies */
 
-
 #define ACPI_COPY_TYPE_SIMPLE           0
 #define ACPI_COPY_TYPE_PACKAGE          1
 
 /* Info structure used to convert external<->internal namestrings */
 
-struct acpi_namestring_info
-{
-        char                            *external_name;
-        char                            *next_external_char;
-        char                            *internal_name;
-        u32                             length;
-        u32                             num_segments;
-        u32                             num_carats;
-        u8                              fully_qualified;
+struct acpi_namestring_info {
+        char *external_name;
+        char *next_external_char;
+        char *internal_name;
+        u32 length;
+        u32 num_segments;
+        u32 num_carats;
+        u8 fully_qualified;
 };
 
-
 /* Field creation info */
 
-struct acpi_create_field_info
-{
-        struct acpi_namespace_node      *region_node;
-        struct acpi_namespace_node      *field_node;
-        struct acpi_namespace_node      *register_node;
-        struct acpi_namespace_node      *data_register_node;
-        u32                             bank_value;
-        u32                             field_bit_position;
-        u32                             field_bit_length;
-        u8                              field_flags;
-        u8                              attribute;
-        u8                              field_type;
+struct acpi_create_field_info {
+        struct acpi_namespace_node *region_node;
+        struct acpi_namespace_node *field_node;
+        struct acpi_namespace_node *register_node;
+        struct acpi_namespace_node *data_register_node;
+        u32 bank_value;
+        u32 field_bit_position;
+        u32 field_bit_length;
+        u8 field_flags;
+        u8 attribute;
+        u8 field_type;
 };
 
-
 /*****************************************************************************
  *
  * Event typedefs and structs
@@ -307,128 +284,107 @@ struct acpi_create_field_info
 
 /* Dispatch info for each GPE -- either a method or handler, cannot be both */
 
-struct acpi_handler_info
-{
-        acpi_event_handler                      address;        /* Address of handler, if any */
-        void                                    *context;       /* Context to be passed to handler */
-        struct acpi_namespace_node              *method_node;   /* Method node for this GPE level (saved) */
+struct acpi_handler_info {
+        acpi_event_handler address;     /* Address of handler, if any */
+        void *context;          /* Context to be passed to handler */
+        struct acpi_namespace_node *method_node;        /* Method node for this GPE level (saved) */
 };
 
-union acpi_gpe_dispatch_info
-{
-        struct acpi_namespace_node              *method_node;   /* Method node for this GPE level */
-        struct acpi_handler_info                *handler;
+union acpi_gpe_dispatch_info {
+        struct acpi_namespace_node *method_node;        /* Method node for this GPE level */
+        struct acpi_handler_info *handler;
 };
 
 /*
  * Information about a GPE, one per each GPE in an array.
  * NOTE: Important to keep this struct as small as possible.
  */
-struct acpi_gpe_event_info
-{
-        union acpi_gpe_dispatch_info    dispatch;       /* Either Method or Handler */
-        struct acpi_gpe_register_info           *register_info; /* Backpointer to register info */
-        u8                                      flags;          /* Misc info about this GPE */
-        u8                                      register_bit;   /* This GPE bit within the register */
+struct acpi_gpe_event_info {
+        union acpi_gpe_dispatch_info dispatch;  /* Either Method or Handler */
+        struct acpi_gpe_register_info *register_info;   /* Backpointer to register info */
+        u8 flags;               /* Misc info about this GPE */
+        u8 register_bit;        /* This GPE bit within the register */
 };
 
 /* Information about a GPE register pair, one per each status/enable pair in an array */
 
-struct acpi_gpe_register_info
-{
-        struct acpi_generic_address             status_address; /* Address of status reg */
-        struct acpi_generic_address             enable_address; /* Address of enable reg */
-        u8                                      enable_for_wake; /* GPEs to keep enabled when sleeping */
-        u8                                      enable_for_run; /* GPEs to keep enabled when running */
-        u8                                      base_gpe_number; /* Base GPE number for this register */
+struct acpi_gpe_register_info {
+        struct acpi_generic_address status_address;     /* Address of status reg */
+        struct acpi_generic_address enable_address;     /* Address of enable reg */
+        u8 enable_for_wake;     /* GPEs to keep enabled when sleeping */
+        u8 enable_for_run;      /* GPEs to keep enabled when running */
+        u8 base_gpe_number;     /* Base GPE number for this register */
 };
 
 /*
  * Information about a GPE register block, one per each installed block --
  * GPE0, GPE1, and one per each installed GPE Block Device.
  */
-struct acpi_gpe_block_info
-{
-        struct acpi_namespace_node              *node;
-        struct acpi_gpe_block_info              *previous;
-        struct acpi_gpe_block_info              *next;
-        struct acpi_gpe_xrupt_info              *xrupt_block;   /* Backpointer to interrupt block */
-        struct acpi_gpe_register_info           *register_info; /* One per GPE register pair */
-        struct acpi_gpe_event_info              *event_info;    /* One for each GPE */
-        struct acpi_generic_address             block_address;  /* Base address of the block */
-        u32                                     register_count; /* Number of register pairs in block */
-        u8                                      block_base_number;/* Base GPE number for this block */
+struct acpi_gpe_block_info {
+        struct acpi_namespace_node *node;
+        struct acpi_gpe_block_info *previous;
+        struct acpi_gpe_block_info *next;
+        struct acpi_gpe_xrupt_info *xrupt_block;        /* Backpointer to interrupt block */
+        struct acpi_gpe_register_info *register_info;   /* One per GPE register pair */
+        struct acpi_gpe_event_info *event_info; /* One for each GPE */
+        struct acpi_generic_address block_address;      /* Base address of the block */
+        u32 register_count;     /* Number of register pairs in block */
+        u8 block_base_number;   /* Base GPE number for this block */
 };
 
 /* Information about GPE interrupt handlers, one per each interrupt level used for GPEs */
 
-struct acpi_gpe_xrupt_info
-{
-        struct acpi_gpe_xrupt_info              *previous;
-        struct acpi_gpe_xrupt_info              *next;
-        struct acpi_gpe_block_info              *gpe_block_list_head; /* List of GPE blocks for this xrupt */
-        u32                                     interrupt_level;    /* System interrupt level */
+struct acpi_gpe_xrupt_info {
+        struct acpi_gpe_xrupt_info *previous;
+        struct acpi_gpe_xrupt_info *next;
+        struct acpi_gpe_block_info *gpe_block_list_head;        /* List of GPE blocks for this xrupt */
+        u32 interrupt_number;   /* System interrupt number */
 };
 
-
-struct acpi_gpe_walk_info
-{
-        struct acpi_namespace_node              *gpe_device;
-        struct acpi_gpe_block_info              *gpe_block;
+struct acpi_gpe_walk_info {
+        struct acpi_namespace_node *gpe_device;
+        struct acpi_gpe_block_info *gpe_block;
 };
 
-
-typedef acpi_status (*ACPI_GPE_CALLBACK) (
-        struct acpi_gpe_xrupt_info      *gpe_xrupt_info,
-        struct acpi_gpe_block_info      *gpe_block);
-
+typedef acpi_status(*ACPI_GPE_CALLBACK) (struct acpi_gpe_xrupt_info *
+                                         gpe_xrupt_info,
+                                         struct acpi_gpe_block_info *
+                                         gpe_block);
 
 /* Information about each particular fixed event */
 
-struct acpi_fixed_event_handler
-{
-        acpi_event_handler              handler;        /* Address of handler. */
-        void                            *context;       /* Context to be passed to handler */
+struct acpi_fixed_event_handler {
+        acpi_event_handler handler;     /* Address of handler. */
+        void *context;          /* Context to be passed to handler */
 };
 
-struct acpi_fixed_event_info
-{
-        u8                              status_register_id;
-        u8                              enable_register_id;
-        u16                             status_bit_mask;
-        u16                             enable_bit_mask;
+struct acpi_fixed_event_info {
+        u8 status_register_id;
+        u8 enable_register_id;
+        u16 status_bit_mask;
+        u16 enable_bit_mask;
 };
 
 /* Information used during field processing */
 
-struct acpi_field_info
-{
-        u8                              skip_field;
-        u8                              field_flag;
-        u32                             pkg_length;
+struct acpi_field_info {
+        u8 skip_field;
+        u8 field_flag;
+        u32 pkg_length;
 };
 
-
 /*****************************************************************************
  *
  * Generic "state" object for stacks
  *
  ****************************************************************************/
 
-
 #define ACPI_CONTROL_NORMAL                  0xC0
 #define ACPI_CONTROL_CONDITIONAL_EXECUTING   0xC1
 #define ACPI_CONTROL_PREDICATE_EXECUTING     0xC2
 #define ACPI_CONTROL_PREDICATE_FALSE         0xC3
 #define ACPI_CONTROL_PREDICATE_TRUE          0xC4
 
-
-/* Forward declarations */
-struct acpi_walk_state        ;
-struct acpi_obj_mutex;
-union acpi_parse_object        ;
-
-
 #define ACPI_STATE_COMMON                  /* Two 32-bit fields and a pointer */\
         u8                                  data_type;          /* To differentiate various internal objs */\
         u8                                  flags;      \
@@ -437,147 +393,112 @@ union acpi_parse_object        ;
         u16                                 reserved;   \
         void                                *next;      \
 
-struct acpi_common_state
-{
-        ACPI_STATE_COMMON
-};
-
+struct acpi_common_state {
+ACPI_STATE_COMMON};
 
 /*
  * Update state - used to traverse complex objects such as packages
  */
-struct acpi_update_state
-{
-        ACPI_STATE_COMMON
-        union acpi_operand_object           *object;
+struct acpi_update_state {
+        ACPI_STATE_COMMON union acpi_operand_object *object;
 };
 
-
 /*
  * Pkg state - used to traverse nested package structures
  */
-struct acpi_pkg_state
-{
-        ACPI_STATE_COMMON
-        union acpi_operand_object           *source_object;
-        union acpi_operand_object           *dest_object;
-        struct acpi_walk_state              *walk_state;
-        void                                *this_target_obj;
-        u32                                 num_packages;
-        u16                                 index;
+struct acpi_pkg_state {
+        ACPI_STATE_COMMON union acpi_operand_object *source_object;
+        union acpi_operand_object *dest_object;
+        struct acpi_walk_state *walk_state;
+        void *this_target_obj;
+        u32 num_packages;
+        u16 index;
 };
 
-
 /*
  * Control state - one per if/else and while constructs.
  * Allows nesting of these constructs
  */
-struct acpi_control_state
-{
-        ACPI_STATE_COMMON
-        union acpi_parse_object             *predicate_op;
-        u8                                  *aml_predicate_start;   /* Start of if/while predicate */
-        u8                                  *package_end;           /* End of if/while block */
-        u16                                 opcode;
+struct acpi_control_state {
+        ACPI_STATE_COMMON union acpi_parse_object *predicate_op;
+        u8 *aml_predicate_start;        /* Start of if/while predicate */
+        u8 *package_end;        /* End of if/while block */
+        u16 opcode;
 };
 
-
 /*
  * Scope state - current scope during namespace lookups
  */
-struct acpi_scope_state
-{
-        ACPI_STATE_COMMON
-        struct acpi_namespace_node          *node;
+struct acpi_scope_state {
+        ACPI_STATE_COMMON struct acpi_namespace_node *node;
 };
 
-
-struct acpi_pscope_state
-{
-        ACPI_STATE_COMMON
-        union acpi_parse_object             *op;                    /* Current op being parsed */
-        u8                                  *arg_end;               /* Current argument end */
-        u8                                  *pkg_end;               /* Current package end */
-        u32                                 arg_list;               /* Next argument to parse */
-        u32                                 arg_count;              /* Number of fixed arguments */
+struct acpi_pscope_state {
+        ACPI_STATE_COMMON union acpi_parse_object *op;  /* Current op being parsed */
+        u8 *arg_end;            /* Current argument end */
+        u8 *pkg_end;            /* Current package end */
+        u32 arg_list;           /* Next argument to parse */
+        u32 arg_count;          /* Number of fixed arguments */
 };
 
-
 /*
  * Thread state - one per thread across multiple walk states.  Multiple walk
  * states are created when there are nested control methods executing.
  */
-struct acpi_thread_state
-{
-        ACPI_STATE_COMMON
-        struct acpi_walk_state              *walk_state_list;       /* Head of list of walk_states for this thread */
-        union acpi_operand_object           *acquired_mutex_list;   /* List of all currently acquired mutexes */
-        u32                                 thread_id;              /* Running thread ID */
-        u8                                  current_sync_level;     /* Mutex Sync (nested acquire) level */
+struct acpi_thread_state {
+        ACPI_STATE_COMMON struct acpi_walk_state *walk_state_list;      /* Head of list of walk_states for this thread */
+        union acpi_operand_object *acquired_mutex_list; /* List of all currently acquired mutexes */
+        u32 thread_id;          /* Running thread ID */
+        u8 current_sync_level;  /* Mutex Sync (nested acquire) level */
 };
 
-
 /*
  * Result values - used to accumulate the results of nested
  * AML arguments
  */
-struct acpi_result_values
-{
+struct acpi_result_values {
         ACPI_STATE_COMMON
-        union acpi_operand_object           *obj_desc [ACPI_OBJ_NUM_OPERANDS];
-        u8                                  num_results;
-        u8                                  last_insert;
+            union acpi_operand_object *obj_desc[ACPI_OBJ_NUM_OPERANDS];
+        u8 num_results;
+        u8 last_insert;
 };
 
-
 typedef
-acpi_status (*acpi_parse_downwards) (
-        struct acpi_walk_state              *walk_state,
-        union acpi_parse_object             **out_op);
-
-typedef
-acpi_status (*acpi_parse_upwards) (
-        struct acpi_walk_state              *walk_state);
+acpi_status(*acpi_parse_downwards) (struct acpi_walk_state * walk_state,
+                                    union acpi_parse_object ** out_op);
 
+typedef acpi_status(*acpi_parse_upwards) (struct acpi_walk_state * walk_state);
 
 /*
  * Notify info - used to pass info to the deferred notify
  * handler/dispatcher.
  */
-struct acpi_notify_info
-{
-        ACPI_STATE_COMMON
-        struct acpi_namespace_node          *node;
-        union acpi_operand_object           *handler_obj;
+struct acpi_notify_info {
+        ACPI_STATE_COMMON struct acpi_namespace_node *node;
+        union acpi_operand_object *handler_obj;
 };
 
-
 /* Generic state is union of structs above */
 
-union acpi_generic_state
-{
-        struct acpi_common_state            common;
-        struct acpi_control_state           control;
-        struct acpi_update_state            update;
-        struct acpi_scope_state             scope;
-        struct acpi_pscope_state            parse_scope;
-        struct acpi_pkg_state               pkg;
-        struct acpi_thread_state            thread;
-        struct acpi_result_values           results;
-        struct acpi_notify_info             notify;
+union acpi_generic_state {
+        struct acpi_common_state common;
+        struct acpi_control_state control;
+        struct acpi_update_state update;
+        struct acpi_scope_state scope;
+        struct acpi_pscope_state parse_scope;
+        struct acpi_pkg_state pkg;
+        struct acpi_thread_state thread;
+        struct acpi_result_values results;
+        struct acpi_notify_info notify;
 };
 
-
 /*****************************************************************************
  *
  * Interpreter typedefs and structs
  *
  ****************************************************************************/
 
-typedef
-acpi_status (*ACPI_EXECUTE_OP) (
-        struct acpi_walk_state              *walk_state);
-
+typedef acpi_status(*ACPI_EXECUTE_OP) (struct acpi_walk_state * walk_state);
 
 /*****************************************************************************
  *
@@ -588,32 +509,28 @@ acpi_status (*ACPI_EXECUTE_OP) (
 /*
  * AML opcode, name, and argument layout
  */
-struct acpi_opcode_info
-{
+struct acpi_opcode_info {
 #if defined(ACPI_DISASSEMBLER) || defined(ACPI_DEBUG_OUTPUT)
-        char                                *name;          /* Opcode name (disassembler/debug only) */
+        char *name;             /* Opcode name (disassembler/debug only) */
 #endif
-        u32                                 parse_args;     /* Grammar/Parse time arguments */
-        u32                                 runtime_args;   /* Interpret time arguments */
-        u32                                 flags;          /* Misc flags */
-        u8                                  object_type;    /* Corresponding internal object type */
-        u8                                  class;          /* Opcode class */
-        u8                                  type;           /* Opcode type */
+        u32 parse_args;         /* Grammar/Parse time arguments */
+        u32 runtime_args;       /* Interpret time arguments */
+        u32 flags;              /* Misc flags */
+        u8 object_type;         /* Corresponding internal object type */
+        u8 class;               /* Opcode class */
+        u8 type;                /* Opcode type */
 };
 
-
-union acpi_parse_value
-{
-        acpi_integer                        integer;        /* Integer constant (Up to 64 bits) */
-        struct uint64_struct                integer64;      /* Structure overlay for 2 32-bit Dwords */
-        u32                                 size;           /* bytelist or field size */
-        char                                *string;        /* NULL terminated string */
-        u8                                  *buffer;        /* buffer or string */
-        char                                *name;          /* NULL terminated string */
-        union acpi_parse_object             *arg;           /* arguments and contained ops */
+union acpi_parse_value {
+        acpi_integer integer;   /* Integer constant (Up to 64 bits) */
+        struct uint64_struct integer64; /* Structure overlay for 2 32-bit Dwords */
+        u32 size;               /* bytelist or field size */
+        char *string;           /* NULL terminated string */
+        u8 *buffer;             /* buffer or string */
+        char *name;             /* NULL terminated string */
+        union acpi_parse_object *arg;   /* arguments and contained ops */
 };
 
-
 #define ACPI_PARSE_COMMON \
         u8                                  data_type;      /* To differentiate various internal objs */\
         u8                                  flags;          /* Type of Op */\
@@ -640,85 +557,72 @@ union acpi_parse_value
 /*
  * generic operation (for example:  If, While, Store)
  */
-struct acpi_parse_obj_common
-{
-        ACPI_PARSE_COMMON
-};
-
+struct acpi_parse_obj_common {
+ACPI_PARSE_COMMON};
 
 /*
  * Extended Op for named ops (Scope, Method, etc.), deferred ops (Methods and op_regions),
  * and bytelists.
  */
-struct acpi_parse_obj_named
-{
-        ACPI_PARSE_COMMON
-        u8                                  *path;
-        u8                                  *data;          /* AML body or bytelist data */
-        u32                                 length;         /* AML length */
-        u32                                 name;           /* 4-byte name or zero if no name */
+struct acpi_parse_obj_named {
+        ACPI_PARSE_COMMON u8 * path;
+        u8 *data;               /* AML body or bytelist data */
+        u32 length;             /* AML length */
+        u32 name;               /* 4-byte name or zero if no name */
 };
 
-
 /* The parse node is the fundamental element of the parse tree */
 
-struct acpi_parse_obj_asl
-{
-        ACPI_PARSE_COMMON
-        union acpi_parse_object             *child;
-        union acpi_parse_object             *parent_method;
-        char                                *filename;
-        char                                *external_name;
-        char                                *namepath;
-        char                                name_seg[4];
-        u32                                 extra_value;
-        u32                                 column;
-        u32                                 line_number;
-        u32                                 logical_line_number;
-        u32                                 logical_byte_offset;
-        u32                                 end_line;
-        u32                                 end_logical_line;
-        u32                                 acpi_btype;
-        u32                                 aml_length;
-        u32                                 aml_subtree_length;
-        u32                                 final_aml_length;
-        u32                                 final_aml_offset;
-        u32                                 compile_flags;
-        u16                                 parse_opcode;
-        u8                                  aml_opcode_length;
-        u8                                  aml_pkg_len_bytes;
-        u8                                  extra;
-        char                                parse_op_name[12];
-};
-
-
-union acpi_parse_object
-{
-        struct acpi_parse_obj_common        common;
-        struct acpi_parse_obj_named         named;
-        struct acpi_parse_obj_asl           asl;
+struct acpi_parse_obj_asl {
+        ACPI_PARSE_COMMON union acpi_parse_object *child;
+        union acpi_parse_object *parent_method;
+        char *filename;
+        char *external_name;
+        char *namepath;
+        char name_seg[4];
+        u32 extra_value;
+        u32 column;
+        u32 line_number;
+        u32 logical_line_number;
+        u32 logical_byte_offset;
+        u32 end_line;
+        u32 end_logical_line;
+        u32 acpi_btype;
+        u32 aml_length;
+        u32 aml_subtree_length;
+        u32 final_aml_length;
+        u32 final_aml_offset;
+        u32 compile_flags;
+        u16 parse_opcode;
+        u8 aml_opcode_length;
+        u8 aml_pkg_len_bytes;
+        u8 extra;
+        char parse_op_name[12];
+};
+
+union acpi_parse_object {
+        struct acpi_parse_obj_common common;
+        struct acpi_parse_obj_named named;
+        struct acpi_parse_obj_asl asl;
 };
 
-
 /*
  * Parse state - one state per parser invocation and each control
  * method.
  */
-struct acpi_parse_state
-{
-        u32                                 aml_size;
-        u8                                  *aml_start;     /* First AML byte */
-        u8                                  *aml;           /* Next AML byte */
-        u8                                  *aml_end;       /* (last + 1) AML byte */
-        u8                                  *pkg_start;     /* Current package begin */
-        u8                                  *pkg_end;       /* Current package end */
-        union acpi_parse_object             *start_op;      /* Root of parse tree */
-        struct acpi_namespace_node          *start_node;
-        union acpi_generic_state            *scope;         /* Current scope */
-        union acpi_parse_object             *start_scope;
+struct acpi_parse_state {
+        u32 aml_size;
+        u8 *aml_start;          /* First AML byte */
+        u8 *aml;                /* Next AML byte */
+        u8 *aml_end;            /* (last + 1) AML byte */
+        u8 *pkg_start;          /* Current package begin */
+        u8 *pkg_end;            /* Current package end */
+        union acpi_parse_object *start_op;      /* Root of parse tree */
+        struct acpi_namespace_node *start_node;
+        union acpi_generic_state *scope;        /* Current scope */
+        union acpi_parse_object *start_scope;
 };
 
-
 /* Parse object flags */
 
 #define ACPI_PARSEOP_GENERIC                    0x01
@@ -734,7 +638,6 @@ struct acpi_parse_state
 #define ACPI_PARSEOP_EMPTY_TERMLIST             0x04
 #define ACPI_PARSEOP_SPECIAL                    0x10
 
-
 /*****************************************************************************
  *
  * Hardware (ACPI registers) and PNP
@@ -742,15 +645,14 @@ struct acpi_parse_state
  ****************************************************************************/
 
 #define PCI_ROOT_HID_STRING         "PNP0A03"
+#define PCI_EXPRESS_ROOT_HID_STRING "PNP0A08"
 
-struct acpi_bit_register_info
-{
-        u8                                  parent_register;
-        u8                                  bit_position;
-        u16                                 access_bit_mask;
+struct acpi_bit_register_info {
+        u8 parent_register;
+        u8 bit_position;
+        u16 access_bit_mask;
 };
 
-
 /*
  * Register IDs
  * These are the full ACPI registers
@@ -765,7 +667,6 @@ struct acpi_bit_register_info
 #define ACPI_REGISTER_PROCESSOR_BLOCK           0x08
 #define ACPI_REGISTER_SMI_COMMAND_BLOCK         0x09
 
-
 /* Masks used to access the bit_registers */
 
 #define ACPI_BITMASK_TIMER_STATUS               0x0001
@@ -774,7 +675,7 @@ struct acpi_bit_register_info
 #define ACPI_BITMASK_POWER_BUTTON_STATUS        0x0100
 #define ACPI_BITMASK_SLEEP_BUTTON_STATUS        0x0200
 #define ACPI_BITMASK_RT_CLOCK_STATUS            0x0400
-#define ACPI_BITMASK_PCIEXP_WAKE_STATUS         0x4000    /* ACPI 3.0 */
+#define ACPI_BITMASK_PCIEXP_WAKE_STATUS         0x4000  /* ACPI 3.0 */
 #define ACPI_BITMASK_WAKE_STATUS                0x8000
 
 #define ACPI_BITMASK_ALL_FIXED_STATUS           (ACPI_BITMASK_TIMER_STATUS          | \
@@ -790,7 +691,7 @@ struct acpi_bit_register_info
 #define ACPI_BITMASK_POWER_BUTTON_ENABLE        0x0100
 #define ACPI_BITMASK_SLEEP_BUTTON_ENABLE        0x0200
 #define ACPI_BITMASK_RT_CLOCK_ENABLE            0x0400
-#define ACPI_BITMASK_PCIEXP_WAKE_DISABLE        0x4000    /* ACPI 3.0 */
+#define ACPI_BITMASK_PCIEXP_WAKE_DISABLE        0x4000  /* ACPI 3.0 */
 
 #define ACPI_BITMASK_SCI_ENABLE                 0x0001
 #define ACPI_BITMASK_BUS_MASTER_RLD             0x0002
@@ -800,7 +701,6 @@ struct acpi_bit_register_info
 
 #define ACPI_BITMASK_ARB_DISABLE                0x0001
 
-
 /* Raw bit position of each bit_register */
 
 #define ACPI_BITPOSITION_TIMER_STATUS           0x00
@@ -809,7 +709,7 @@ struct acpi_bit_register_info
 #define ACPI_BITPOSITION_POWER_BUTTON_STATUS    0x08
 #define ACPI_BITPOSITION_SLEEP_BUTTON_STATUS    0x09
 #define ACPI_BITPOSITION_RT_CLOCK_STATUS        0x0A
-#define ACPI_BITPOSITION_PCIEXP_WAKE_STATUS     0x0E    /* ACPI 3.0 */
+#define ACPI_BITPOSITION_PCIEXP_WAKE_STATUS     0x0E    /* ACPI 3.0 */
 #define ACPI_BITPOSITION_WAKE_STATUS            0x0F
 
 #define ACPI_BITPOSITION_TIMER_ENABLE           0x00
@@ -817,7 +717,7 @@ struct acpi_bit_register_info
 #define ACPI_BITPOSITION_POWER_BUTTON_ENABLE    0x08
 #define ACPI_BITPOSITION_SLEEP_BUTTON_ENABLE    0x09
 #define ACPI_BITPOSITION_RT_CLOCK_ENABLE        0x0A
-#define ACPI_BITPOSITION_PCIEXP_WAKE_DISABLE    0x0E    /* ACPI 3.0 */
+#define ACPI_BITPOSITION_PCIEXP_WAKE_DISABLE    0x0E    /* ACPI 3.0 */
 
 #define ACPI_BITPOSITION_SCI_ENABLE             0x00
 #define ACPI_BITPOSITION_BUS_MASTER_RLD         0x01
@@ -827,14 +727,12 @@ struct acpi_bit_register_info
 
 #define ACPI_BITPOSITION_ARB_DISABLE            0x00
 
-
 /*****************************************************************************
  *
  * Resource descriptors
  *
  ****************************************************************************/
 
-
 /* resource_type values */
 
 #define ACPI_RESOURCE_TYPE_MEMORY_RANGE         0
@@ -847,8 +745,7 @@ struct acpi_bit_register_info
 #define ACPI_RDESC_TYPE_SMALL                   0x00
 
 #define ACPI_RDESC_TYPE_MASK                    0x80
-#define ACPI_RDESC_SMALL_MASK                   0x78 /* Only bits 6:3 contain the type */
-
+#define ACPI_RDESC_SMALL_MASK                   0x78    /* Only bits 6:3 contain the type */
 
 /*
  * Small resource descriptor types
@@ -877,7 +774,6 @@ struct acpi_bit_register_info
 #define ACPI_RDESC_TYPE_QWORD_ADDRESS_SPACE     0x8A
 #define ACPI_RDESC_TYPE_EXTENDED_ADDRESS_SPACE  0x8B
 
-
 /*****************************************************************************
  *
  * Miscellaneous
@@ -886,49 +782,36 @@ struct acpi_bit_register_info
 
 #define ACPI_ASCII_ZERO                      0x30
 
-
 /*****************************************************************************
  *
  * Debugger
  *
  ****************************************************************************/
 
-struct acpi_db_method_info
-{
-        acpi_handle                     thread_gate;
-        char                            *name;
-        char                            **args;
-        u32                             flags;
-        u32                             num_loops;
-        char                            pathname[128];
+struct acpi_db_method_info {
+        acpi_handle thread_gate;
+        char *name;
+        char **args;
+        u32 flags;
+        u32 num_loops;
+        char pathname[128];
 };
 
-struct acpi_integrity_info
-{
-        u32                         nodes;
-        u32                         objects;
+struct acpi_integrity_info {
+        u32 nodes;
+        u32 objects;
 };
 
-
 #define ACPI_DB_REDIRECTABLE_OUTPUT  0x01
 #define ACPI_DB_CONSOLE_OUTPUT       0x02
 #define ACPI_DB_DUPLICATE_OUTPUT     0x03
 
-
 /*****************************************************************************
  *
  * Debug
  *
  ****************************************************************************/
 
-struct acpi_debug_print_info
-{
-        u32                             component_id;
-        char                            *proc_name;
-        char                            *module_name;
-};
-
-
 /* Entry for a memory allocation (debug only) */
 
 #define ACPI_MEM_MALLOC                      0
@@ -944,51 +827,36 @@ struct acpi_debug_print_info
         char                                module[ACPI_MAX_MODULE_NAME]; \
         u8                                  alloc_type;
 
-struct acpi_debug_mem_header
-{
-        ACPI_COMMON_DEBUG_MEM_HEADER
-};
+struct acpi_debug_mem_header {
+ACPI_COMMON_DEBUG_MEM_HEADER};
 
-struct acpi_debug_mem_block
-{
-        ACPI_COMMON_DEBUG_MEM_HEADER
-        u64                                 user_space;
+struct acpi_debug_mem_block {
+        ACPI_COMMON_DEBUG_MEM_HEADER u64 user_space;
 };
 
-
 #define ACPI_MEM_LIST_GLOBAL            0
 #define ACPI_MEM_LIST_NSNODE            1
+#define ACPI_MEM_LIST_MAX               1
+#define ACPI_NUM_MEM_LISTS              2
 
-#define ACPI_MEM_LIST_FIRST_CACHE_LIST  2
-#define ACPI_MEM_LIST_STATE             2
-#define ACPI_MEM_LIST_PSNODE            3
-#define ACPI_MEM_LIST_PSNODE_EXT        4
-#define ACPI_MEM_LIST_OPERAND           5
-#define ACPI_MEM_LIST_WALK              6
-#define ACPI_MEM_LIST_MAX               6
-#define ACPI_NUM_MEM_LISTS              7
-
-
-struct acpi_memory_list
-{
-        void                                *list_head;
-        u16                                 link_offset;
-        u16                                 max_cache_depth;
-        u16                                 cache_depth;
-        u16                                 object_size;
+struct acpi_memory_list {
+        char *list_name;
+        void *list_head;
+        u16 object_size;
+        u16 max_depth;
+        u16 current_depth;
+        u16 link_offset;
 
 #ifdef ACPI_DBG_TRACK_ALLOCATIONS
 
         /* Statistics for debug memory tracking only */
 
-        u32                                 total_allocated;
-        u32                                 total_freed;
-        u32                                 current_total_size;
-        u32                                 cache_requests;
-        u32                                 cache_hits;
-        char                                *list_name;
+        u32 total_allocated;
+        u32 total_freed;
+        u32 current_total_size;
+        u32 requests;
+        u32 hits;
 #endif
 };
 
-
-#endif /* __ACLOCAL_H__ */
+#endif                          /* __ACLOCAL_H__ */
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index fcaced16b16f..702cc4e57f5f 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -44,7 +44,6 @@
 #ifndef __ACMACROS_H__
 #define __ACMACROS_H__
 
-
 /*
  * Data manipulation macros
  */
@@ -57,7 +56,6 @@
 #define ACPI_CLEAR_BIT(target,bit)      ((target) &= ~(bit))
 #define ACPI_MIN(a,b)                   (((a)<(b))?(a):(b))
 
-
 #if ACPI_MACHINE_WIDTH == 16
 
 /*
@@ -168,7 +166,7 @@
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
 
 #define ACPI_MOVE_32_TO_32(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[3];\
                                                                           ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[2];\
@@ -183,9 +181,9 @@
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
+#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
 
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)    /* Truncate to 32 */
+#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s) /* Truncate to 32 */
 
 #define ACPI_MOVE_64_TO_64(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[7];\
                                                                                  ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[6];\
@@ -219,14 +217,14 @@
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
 #define ACPI_MOVE_32_TO_32(d,s)         *(u32 *)(void *)(d) = *(u32 *)(void *)(s)
 #define ACPI_MOVE_32_TO_64(d,s)         ACPI_MOVE_32_TO_32(d,s)
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)    /* Truncate to 32 */
+#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
+#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s) /* Truncate to 32 */
 #define ACPI_MOVE_64_TO_64(d,s)         ACPI_MOVE_32_TO_32(d,s)
 
 #else
@@ -238,14 +236,14 @@
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
 #define ACPI_MOVE_32_TO_32(d,s)         *(u32 *)(void *)(d) = *(u32 *)(void *)(s)
 #define ACPI_MOVE_32_TO_64(d,s)         *(u64 *)(void *)(d) = *(u32 *)(void *)(s)
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)    /* Truncate to 32 */
+#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
+#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s) /* Truncate to 32 */
 #define ACPI_MOVE_64_TO_64(d,s)         *(u64 *)(void *)(d) = *(u64 *)(void *)(s)
 #endif
 
@@ -266,7 +264,7 @@
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
 
 #define ACPI_MOVE_32_TO_32(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
                                                                                  ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[1];\
@@ -277,8 +275,8 @@
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)    /* Truncate to 16 */
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)    /* Truncate to 32 */
+#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s) /* Truncate to 16 */
+#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s) /* Truncate to 32 */
 #define ACPI_MOVE_64_TO_64(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
                                                                                  ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[1];\
                                                                                  ((  u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[2];\
@@ -305,7 +303,6 @@
 #error unknown ACPI_MACHINE_WIDTH
 #endif
 
-
 /*
  * Fast power-of-two math macros for non-optimized compilers
  */
@@ -329,7 +326,6 @@
 #define ACPI_MUL_16(a)                  _ACPI_MUL(a,4)
 #define ACPI_MOD_16(a)                  _ACPI_MOD(a,16)
 
-
 /*
  * Rounding macros (Power of two boundaries only)
  */
@@ -344,7 +340,6 @@
 #define ACPI_ROUND_UP_to_64_bITS(a)          ACPI_ROUND_UP(a,8)
 #define ACPI_ROUND_UP_TO_NATIVE_WORD(a)      ACPI_ROUND_UP(a,ALIGNED_ADDRESS_BOUNDARY)
 
-
 #define ACPI_ROUND_BITS_UP_TO_BYTES(a)       ACPI_DIV_8((a) + 7)
 #define ACPI_ROUND_BITS_DOWN_TO_BYTES(a)     ACPI_DIV_8((a))
 
@@ -365,7 +360,6 @@
 
 #define ACPI_IS_OCTAL_DIGIT(d)               (((char)(d) >= '0') && ((char)(d) <= '7'))
 
-
 /* Bitfields within ACPI registers */
 
 #define ACPI_REGISTER_PREPARE_BITS(val, pos, mask)      ((val << pos) & mask)
@@ -381,7 +375,6 @@
 #define ACPI_GET_DESCRIPTOR_TYPE(d)     (((union acpi_descriptor *)(void *)(d))->descriptor_id)
 #define ACPI_SET_DESCRIPTOR_TYPE(d,t)   (((union acpi_descriptor *)(void *)(d))->descriptor_id = t)
 
-
 /* Macro to test the object type */
 
 #define ACPI_GET_OBJECT_TYPE(d)         (((union acpi_operand_object *)(void *)(d))->common.type)
@@ -430,28 +423,28 @@
 #define GET_CURRENT_ARG_TYPE(list)      (list & ((u32) 0x1F))
 #define INCREMENT_ARG_LIST(list)        (list >>= ((u32) ARG_TYPE_WIDTH))
 
-
 /*
  * Reporting macros that are never compiled out
  */
 #define ACPI_PARAM_LIST(pl)                 pl
 
 /*
- * Error reporting.  These versions add callers module and line#.  Since
- * _THIS_MODULE gets compiled out when ACPI_DEBUG_OUTPUT isn't defined, only
- * use it in debug mode.
+ * Error reporting.  These versions add callers module and line#.
+ *
+ * Since _acpi_module_name gets compiled out when ACPI_DEBUG_OUTPUT
+ * isn't defined, only use it in debug mode.
  */
 #ifdef ACPI_DEBUG_OUTPUT
 
-#define ACPI_REPORT_INFO(fp)                {acpi_ut_report_info(_THIS_MODULE,__LINE__,_COMPONENT); \
+#define ACPI_REPORT_INFO(fp)                {acpi_ut_report_info(_acpi_module_name,__LINE__,_COMPONENT); \
                                                                                                 acpi_os_printf ACPI_PARAM_LIST(fp);}
-#define ACPI_REPORT_ERROR(fp)               {acpi_ut_report_error(_THIS_MODULE,__LINE__,_COMPONENT); \
+#define ACPI_REPORT_ERROR(fp)               {acpi_ut_report_error(_acpi_module_name,__LINE__,_COMPONENT); \
                                                                                                 acpi_os_printf ACPI_PARAM_LIST(fp);}
-#define ACPI_REPORT_WARNING(fp)             {acpi_ut_report_warning(_THIS_MODULE,__LINE__,_COMPONENT); \
+#define ACPI_REPORT_WARNING(fp)             {acpi_ut_report_warning(_acpi_module_name,__LINE__,_COMPONENT); \
                                                                                                 acpi_os_printf ACPI_PARAM_LIST(fp);}
-#define ACPI_REPORT_NSERROR(s,e)            acpi_ns_report_error(_THIS_MODULE,__LINE__,_COMPONENT, s, e);
+#define ACPI_REPORT_NSERROR(s,e)            acpi_ns_report_error(_acpi_module_name,__LINE__,_COMPONENT, s, e);
 
-#define ACPI_REPORT_METHOD_ERROR(s,n,p,e)   acpi_ns_report_method_error(_THIS_MODULE,__LINE__,_COMPONENT, s, n, p, e);
+#define ACPI_REPORT_METHOD_ERROR(s,n,p,e)   acpi_ns_report_method_error(_acpi_module_name,__LINE__,_COMPONENT, s, n, p, e);
 
 #else
 
@@ -480,36 +473,58 @@
  * Debug macros that are conditionally compiled
  */
 #ifdef ACPI_DEBUG_OUTPUT
+#define ACPI_MODULE_NAME(name)          static char ACPI_UNUSED_VAR *_acpi_module_name = name;
 
-#define ACPI_MODULE_NAME(name)               static char ACPI_UNUSED_VAR *_THIS_MODULE = name;
+/*
+ * Common parameters used for debug output functions:
+ * line number, function name, module(file) name, component ID
+ */
+#define ACPI_DEBUG_PARAMETERS           __LINE__, ACPI_GET_FUNCTION_NAME, _acpi_module_name, _COMPONENT
+
+/*
+ * Function entry tracing
+ */
 
 /*
- * Function entry tracing.
- * The first parameter should be the procedure name as a quoted string.  This is declared
- * as a local string ("_proc_name) so that it can be also used by the function exit macros below.
+ * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
+ * define it now. This is the case where there the compiler does not support
+ * a __FUNCTION__ macro or equivalent. We save the function name on the
+ * local stack.
  */
-#define ACPI_FUNCTION_NAME(a)               struct acpi_debug_print_info _debug_info; \
-                                                                                                _debug_info.component_id = _COMPONENT; \
-                                                                                                _debug_info.proc_name  = a; \
-                                                                                                _debug_info.module_name = _THIS_MODULE;
-
-#define ACPI_FUNCTION_TRACE(a)              ACPI_FUNCTION_NAME(a) \
-                                                                                                acpi_ut_trace(__LINE__,&_debug_info)
-#define ACPI_FUNCTION_TRACE_PTR(a,b)        ACPI_FUNCTION_NAME(a) \
-                                                                                                acpi_ut_trace_ptr(__LINE__,&_debug_info,(void *)b)
-#define ACPI_FUNCTION_TRACE_U32(a,b)        ACPI_FUNCTION_NAME(a) \
-                                                                                                acpi_ut_trace_u32(__LINE__,&_debug_info,(u32)b)
-#define ACPI_FUNCTION_TRACE_STR(a,b)        ACPI_FUNCTION_NAME(a) \
-                                                                                                acpi_ut_trace_str(__LINE__,&_debug_info,(char *)b)
-
-#define ACPI_FUNCTION_ENTRY()               acpi_ut_track_stack_ptr()
+#ifndef ACPI_GET_FUNCTION_NAME
+#define ACPI_GET_FUNCTION_NAME          _acpi_function_name
+/*
+ * The Name parameter should be the procedure name as a quoted string.
+ * This is declared as a local string ("my_function_name") so that it can
+ * be also used by the function exit macros below.
+ * Note: (const char) is used to be compatible with the debug interfaces
+ * and macros such as __FUNCTION__.
+ */
+#define ACPI_FUNCTION_NAME(name)        const char *_acpi_function_name = name;
+
+#else
+/* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
+
+#define ACPI_FUNCTION_NAME(name)
+#endif
+
+#define ACPI_FUNCTION_TRACE(a)          ACPI_FUNCTION_NAME(a) \
+                                                                                        acpi_ut_trace(ACPI_DEBUG_PARAMETERS)
+#define ACPI_FUNCTION_TRACE_PTR(a,b)    ACPI_FUNCTION_NAME(a) \
+                                                                                        acpi_ut_trace_ptr(ACPI_DEBUG_PARAMETERS,(void *)b)
+#define ACPI_FUNCTION_TRACE_U32(a,b)    ACPI_FUNCTION_NAME(a) \
+                                                                                        acpi_ut_trace_u32(ACPI_DEBUG_PARAMETERS,(u32)b)
+#define ACPI_FUNCTION_TRACE_STR(a,b)    ACPI_FUNCTION_NAME(a) \
+                                                                                        acpi_ut_trace_str(ACPI_DEBUG_PARAMETERS,(char *)b)
+
+#define ACPI_FUNCTION_ENTRY()           acpi_ut_track_stack_ptr()
 
 /*
  * Function exit tracing.
  * WARNING: These macros include a return statement.  This is usually considered
  * bad form, but having a separate exit macro is very ugly and difficult to maintain.
  * One of the FUNCTION_TRACE macros above must be used in conjunction with these macros
- * so that "_proc_name" is defined.
+ * so that "_acpi_function_name" is defined.
  */
 #ifdef ACPI_USE_DO_WHILE_0
 #define ACPI_DO_WHILE0(a)               do a while(0)
@@ -517,10 +532,10 @@
 #define ACPI_DO_WHILE0(a)               a
 #endif
 
-#define return_VOID                     ACPI_DO_WHILE0 ({acpi_ut_exit(__LINE__,&_debug_info);return;})
-#define return_ACPI_STATUS(s)           ACPI_DO_WHILE0 ({acpi_ut_status_exit(__LINE__,&_debug_info,(s));return((s));})
-#define return_VALUE(s)                 ACPI_DO_WHILE0 ({acpi_ut_value_exit(__LINE__,&_debug_info,(acpi_integer)(s));return((s));})
-#define return_PTR(s)                   ACPI_DO_WHILE0 ({acpi_ut_ptr_exit(__LINE__,&_debug_info,(u8 *)(s));return((s));})
+#define return_VOID                     ACPI_DO_WHILE0 ({acpi_ut_exit(ACPI_DEBUG_PARAMETERS);return;})
+#define return_ACPI_STATUS(s)           ACPI_DO_WHILE0 ({acpi_ut_status_exit(ACPI_DEBUG_PARAMETERS,(s));return((s));})
+#define return_VALUE(s)                 ACPI_DO_WHILE0 ({acpi_ut_value_exit(ACPI_DEBUG_PARAMETERS,(acpi_integer)(s));return((s));})
+#define return_PTR(s)                   ACPI_DO_WHILE0 ({acpi_ut_ptr_exit(ACPI_DEBUG_PARAMETERS,(u8 *)(s));return((s));})
 
 /* Conditional execution */
 
@@ -531,25 +546,17 @@
 #define ACPI_DEBUG_ONLY_MEMBERS(a)      a;
 #define _VERBOSE_STRUCTURES
 
-
 /* Stack and buffer dumping */
 
 #define ACPI_DUMP_STACK_ENTRY(a)        acpi_ex_dump_operand((a),0)
-#define ACPI_DUMP_OPERANDS(a,b,c,d,e)   acpi_ex_dump_operands(a,b,c,d,e,_THIS_MODULE,__LINE__)
-
+#define ACPI_DUMP_OPERANDS(a,b,c,d,e)   acpi_ex_dump_operands(a,b,c,d,e,_acpi_module_name,__LINE__)
 
 #define ACPI_DUMP_ENTRY(a,b)            acpi_ns_dump_entry (a,b)
-
-#ifdef ACPI_FUTURE_USAGE
-#define ACPI_DUMP_TABLES(a,b)           acpi_ns_dump_tables(a,b)
-#endif
-
 #define ACPI_DUMP_PATHNAME(a,b,c,d)     acpi_ns_dump_pathname(a,b,c,d)
 #define ACPI_DUMP_RESOURCE_LIST(a)      acpi_rs_dump_resource_list(a)
 #define ACPI_DUMP_BUFFER(a,b)           acpi_ut_dump_buffer((u8 *)a,b,DB_BYTE_DISPLAY,_COMPONENT)
 #define ACPI_BREAK_MSG(a)               acpi_os_signal (ACPI_SIGNAL_BREAKPOINT,(a))
 
-
 /*
  * Generate INT3 on ACPI_ERROR (Debug only!)
  */
@@ -570,14 +577,13 @@
 #define ACPI_DEBUG_PRINT(pl)            acpi_ut_debug_print ACPI_PARAM_LIST(pl)
 #define ACPI_DEBUG_PRINT_RAW(pl)        acpi_ut_debug_print_raw ACPI_PARAM_LIST(pl)
 
-
 #else
 /*
  * This is the non-debug case -- make everything go away,
  * leaving no executable debug code!
  */
 #define ACPI_MODULE_NAME(name)
-#define _THIS_MODULE ""
+#define _acpi_module_name ""
 
 #define ACPI_DEBUG_EXEC(a)
 #define ACPI_NORMAL_EXEC(a)             a;
@@ -596,11 +602,6 @@
 #define ACPI_DUMP_STACK_ENTRY(a)
 #define ACPI_DUMP_OPERANDS(a,b,c,d,e)
 #define ACPI_DUMP_ENTRY(a,b)
-
-#ifdef ACPI_FUTURE_USAGE
-#define ACPI_DUMP_TABLES(a,b)
-#endif
-
 #define ACPI_DUMP_PATHNAME(a,b,c,d)
 #define ACPI_DUMP_RESOURCE_LIST(a)
 #define ACPI_DUMP_BUFFER(a,b)
@@ -626,7 +627,6 @@
 #define ACPI_DEBUGGER_EXEC(a)
 #endif
 
-
 /*
  * For 16-bit code, we want to shrink some things even though
  * we are using ACPI_DEBUG_OUTPUT to get the debug output
@@ -637,7 +637,6 @@
 #define ACPI_DEBUG_ONLY_MEMBERS(a)
 #endif
 
-
 #ifdef ACPI_DEBUG_OUTPUT
 /*
  * 1) Set name to blanks
@@ -650,7 +649,6 @@
 #define ACPI_ADD_OBJECT_NAME(a,b)
 #endif
 
-
 /*
  * Memory allocation tracking (DEBUG ONLY)
  */
@@ -658,21 +656,20 @@
 
 /* Memory allocation */
 
-#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate((acpi_size)(a),_COMPONENT,_THIS_MODULE,__LINE__)
-#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate((acpi_size)(a), _COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate((acpi_size)(a),_COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate((acpi_size)(a), _COMPONENT,_acpi_module_name,__LINE__)
 #define ACPI_MEM_FREE(a)                acpi_os_free(a)
 #define ACPI_MEM_TRACKING(a)
 
-
 #else
 
 /* Memory allocation */
 
-#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate_and_track((acpi_size)(a),_COMPONENT,_THIS_MODULE,__LINE__)
-#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate_and_track((acpi_size)(a), _COMPONENT,_THIS_MODULE,__LINE__)
-#define ACPI_MEM_FREE(a)                acpi_ut_free_and_track(a,_COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate_and_track((acpi_size)(a),_COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate_and_track((acpi_size)(a), _COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_MEM_FREE(a)                acpi_ut_free_and_track(a,_COMPONENT,_acpi_module_name,__LINE__)
 #define ACPI_MEM_TRACKING(a)            a
 
-#endif /* ACPI_DBG_TRACK_ALLOCATIONS */
+#endif                          /* ACPI_DBG_TRACK_ALLOCATIONS */
 
-#endif /* ACMACROS_H */
+#endif                          /* ACMACROS_H */
diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h
new file mode 100644
index 000000000000..4f9063f3e951
--- /dev/null
+++ b/include/acpi/acnames.h
@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
+ * Name: acnames.h - Global names and strings
+ *
+ *****************************************************************************/
+
+/*
+ * Copyright (C) 2000 - 2005, R. Byron Moore
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    substantially similar to the "NO WARRANTY" disclaimer below
+ *    ("Disclaimer") and any redistribution must be conditioned upon
+ *    including a substantially similar Disclaimer requirement for further
+ *    binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#ifndef __ACNAMES_H__
+#define __ACNAMES_H__
+
+/* Method names - these methods can appear anywhere in the namespace */
+
+#define METHOD_NAME__HID        "_HID"
+#define METHOD_NAME__CID        "_CID"
+#define METHOD_NAME__UID        "_UID"
+#define METHOD_NAME__ADR        "_ADR"
+#define METHOD_NAME__INI        "_INI"
+#define METHOD_NAME__STA        "_STA"
+#define METHOD_NAME__REG        "_REG"
+#define METHOD_NAME__SEG        "_SEG"
+#define METHOD_NAME__BBN        "_BBN"
+#define METHOD_NAME__PRT        "_PRT"
+#define METHOD_NAME__CRS        "_CRS"
+#define METHOD_NAME__PRS        "_PRS"
+#define METHOD_NAME__PRW        "_PRW"
+#define METHOD_NAME__SRS        "_SRS"
+
+/* Method names - these methods must appear at the namespace root */
+
+#define METHOD_NAME__BFS        "\\_BFS"
+#define METHOD_NAME__GTS        "\\_GTS"
+#define METHOD_NAME__PTS        "\\_PTS"
+#define METHOD_NAME__SST        "\\_SI._SST"
+#define METHOD_NAME__WAK        "\\_WAK"
+
+/* Definitions of the predefined namespace names  */
+
+#define ACPI_UNKNOWN_NAME       (u32) 0x3F3F3F3F        /* Unknown name is "????" */
+#define ACPI_ROOT_NAME          (u32) 0x5F5F5F5C        /* Root name is    "\___" */
+
+#define ACPI_PREFIX_MIXED       (u32) 0x69706341        /* "Acpi" */
+#define ACPI_PREFIX_LOWER       (u32) 0x69706361        /* "acpi" */
+
+#define ACPI_NS_ROOT_PATH       "\\"
+#define ACPI_NS_SYSTEM_BUS      "_SB_"
+
+#endif                          /* __ACNAMES_H__  */
diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h
index 8b3cdc3566b1..dd3501f7e5d6 100644
--- a/include/acpi/acnamesp.h
+++ b/include/acpi/acnamesp.h
@@ -44,7 +44,6 @@
 #ifndef __ACNAMESP_H__
 #define __ACNAMESP_H__
 
-
 /* To search the entire name space, pass this as search_base */
 
 #define ACPI_NS_ALL                 ((acpi_handle)0)
@@ -54,19 +53,8 @@
  * and should be one-to-one with values of acpi_object_type
  */
 #define ACPI_NS_NORMAL              0
-#define ACPI_NS_NEWSCOPE            1   /* a definition of this type opens a name scope */
-#define ACPI_NS_LOCAL               2   /* suppress search of enclosing scopes */
-
-
-/* Definitions of the predefined namespace names  */
-
-#define ACPI_UNKNOWN_NAME           (u32) 0x3F3F3F3F     /* Unknown name is  "????" */
-#define ACPI_ROOT_NAME              (u32) 0x5F5F5F5C     /* Root name is     "\___" */
-#define ACPI_SYS_BUS_NAME           (u32) 0x5F53425F     /* Sys bus name is  "_SB_" */
-
-#define ACPI_NS_ROOT_PATH           "\\"
-#define ACPI_NS_SYSTEM_BUS          "_SB_"
-
+#define ACPI_NS_NEWSCOPE            1   /* a definition of this type opens a name scope */
+#define ACPI_NS_LOCAL               2   /* suppress search of enclosing scopes */
 
 /* Flags for acpi_ns_lookup, acpi_ns_search_and_enter */
 
@@ -79,437 +67,237 @@
 #define ACPI_NS_WALK_UNLOCK         TRUE
 #define ACPI_NS_WALK_NO_UNLOCK      FALSE
 
+/*
+ * nsinit - Namespace initialization
+ */
+acpi_status acpi_ns_initialize_objects(void);
 
-acpi_status
-acpi_ns_load_namespace (
-        void);
-
-acpi_status
-acpi_ns_initialize_objects (
-        void);
-
-acpi_status
-acpi_ns_initialize_devices (
-        void);
-
-
-/* Namespace init - nsxfinit */
-
-acpi_status
-acpi_ns_init_one_device (
-        acpi_handle                     obj_handle,
-        u32                             nesting_level,
-        void                            *context,
-        void                            **return_value);
-
-acpi_status
-acpi_ns_init_one_object (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+acpi_status acpi_ns_initialize_devices(void);
 
+/*
+ * nsload -  Namespace loading
+ */
+acpi_status acpi_ns_load_namespace(void);
 
 acpi_status
-acpi_ns_walk_namespace (
-        acpi_object_type                type,
-        acpi_handle                     start_object,
-        u32                             max_depth,
-        u8                              unlock_before_callback,
-        acpi_walk_callback              user_function,
-        void                            *context,
-        void                            **return_value);
-
-struct acpi_namespace_node *
-acpi_ns_get_next_node (
-        acpi_object_type                type,
-        struct acpi_namespace_node      *parent,
-        struct acpi_namespace_node      *child);
-
-void
-acpi_ns_delete_namespace_by_owner (
-        u16                             table_id);
-
-
-/* Namespace loading - nsload */
+acpi_ns_load_table(struct acpi_table_desc *table_desc,
+                   struct acpi_namespace_node *node);
 
+/*
+ * nswalk - walk the namespace
+ */
 acpi_status
-acpi_ns_one_complete_parse (
-        u32                             pass_number,
-        struct acpi_table_desc          *table_desc);
+acpi_ns_walk_namespace(acpi_object_type type,
+                       acpi_handle start_object,
+                       u32 max_depth,
+                       u8 unlock_before_callback,
+                       acpi_walk_callback user_function,
+                       void *context, void **return_value);
 
-acpi_status
-acpi_ns_parse_table (
-        struct acpi_table_desc          *table_desc,
-        struct acpi_namespace_node      *scope);
+struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type,
+                                                  struct acpi_namespace_node
+                                                  *parent,
+                                                  struct acpi_namespace_node
+                                                  *child);
 
+/*
+ * nsparse - table parsing
+ */
 acpi_status
-acpi_ns_load_table (
-        struct acpi_table_desc          *table_desc,
-        struct acpi_namespace_node      *node);
+acpi_ns_parse_table(struct acpi_table_desc *table_desc,
+                    struct acpi_namespace_node *scope);
 
 acpi_status
-acpi_ns_load_table_by_type (
-        acpi_table_type                 table_type);
-
+acpi_ns_one_complete_parse(u8 pass_number, struct acpi_table_desc *table_desc);
 
 /*
- * Top-level namespace access - nsaccess
+ * nsaccess - Top-level namespace access
  */
+acpi_status acpi_ns_root_initialize(void);
 
 acpi_status
-acpi_ns_root_initialize (
-        void);
-
-acpi_status
-acpi_ns_lookup (
-        union acpi_generic_state        *scope_info,
-        char                            *name,
-        acpi_object_type                type,
-        acpi_interpreter_mode           interpreter_mode,
-        u32                             flags,
-        struct acpi_walk_state          *walk_state,
-        struct acpi_namespace_node      **ret_node);
-
+acpi_ns_lookup(union acpi_generic_state *scope_info,
+               char *name,
+               acpi_object_type type,
+               acpi_interpreter_mode interpreter_mode,
+               u32 flags,
+               struct acpi_walk_state *walk_state,
+               struct acpi_namespace_node **ret_node);
 
 /*
- * Named object allocation/deallocation - nsalloc
+ * nsalloc - Named object allocation/deallocation
  */
+struct acpi_namespace_node *acpi_ns_create_node(u32 name);
 
-struct acpi_namespace_node *
-acpi_ns_create_node (
-        u32                             name);
-
-void
-acpi_ns_delete_node (
-        struct acpi_namespace_node      *node);
-
-void
-acpi_ns_delete_namespace_subtree (
-        struct acpi_namespace_node      *parent_handle);
+void acpi_ns_delete_node(struct acpi_namespace_node *node);
 
 void
-acpi_ns_detach_object (
-        struct acpi_namespace_node      *node);
-
-void
-acpi_ns_delete_children (
-        struct acpi_namespace_node      *parent);
-
-int
-acpi_ns_compare_names (
-        char                            *name1,
-        char                            *name2);
-
-void
-acpi_ns_remove_reference (
-        struct acpi_namespace_node      *node);
-
+acpi_ns_delete_namespace_subtree(struct acpi_namespace_node *parent_handle);
 
-/*
- * Namespace modification - nsmodify
- */
+void acpi_ns_delete_namespace_by_owner(acpi_owner_id owner_id);
 
-#ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_ns_unload_namespace (
-        acpi_handle                     handle);
+void acpi_ns_detach_object(struct acpi_namespace_node *node);
 
-acpi_status
-acpi_ns_delete_subtree (
-        acpi_handle                     start_handle);
-#endif
+void acpi_ns_delete_children(struct acpi_namespace_node *parent);
 
+int acpi_ns_compare_names(char *name1, char *name2);
 
 /*
- * Namespace dump/print utilities - nsdump
+ * nsdump - Namespace dump/print utilities
  */
+#ifdef  ACPI_FUTURE_USAGE
+void acpi_ns_dump_tables(acpi_handle search_base, u32 max_depth);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-#ifdef ACPI_FUTURE_USAGE
-void
-acpi_ns_dump_tables (
-        acpi_handle                     search_base,
-        u32                             max_depth);
-#endif
+void acpi_ns_dump_entry(acpi_handle handle, u32 debug_level);
 
 void
-acpi_ns_dump_entry (
-        acpi_handle                     handle,
-        u32                             debug_level);
-
-void
-acpi_ns_dump_pathname (
-        acpi_handle                     handle,
-        char                            *msg,
-        u32                             level,
-        u32                             component);
-
-void
-acpi_ns_print_pathname (
-        u32                             num_segments,
-        char                            *pathname);
-
-#ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_ns_dump_one_device (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+acpi_ns_dump_pathname(acpi_handle handle, char *msg, u32 level, u32 component);
 
-void
-acpi_ns_dump_root_devices (
-        void);
-#endif  /*  ACPI_FUTURE_USAGE  */
+void acpi_ns_print_pathname(u32 num_segments, char *pathname);
 
 acpi_status
-acpi_ns_dump_one_object (
-        acpi_handle                     obj_handle,
-        u32                             level,
-        void                            *context,
-        void                            **return_value);
+acpi_ns_dump_one_object(acpi_handle obj_handle,
+                        u32 level, void *context, void **return_value);
 
-#ifdef ACPI_FUTURE_USAGE
+#ifdef  ACPI_FUTURE_USAGE
 void
-acpi_ns_dump_objects (
-        acpi_object_type                type,
-        u8                              display_type,
-        u32                             max_depth,
-        u32                             ownder_id,
-        acpi_handle                     start_handle);
-#endif
-
+acpi_ns_dump_objects(acpi_object_type type,
+                     u8 display_type,
+                     u32 max_depth,
+                     acpi_owner_id owner_id, acpi_handle start_handle);
+#endif                          /* ACPI_FUTURE_USAGE */
 
 /*
- * Namespace evaluation functions - nseval
+ * nseval - Namespace evaluation functions
  */
+acpi_status acpi_ns_evaluate_by_handle(struct acpi_parameter_info *info);
 
 acpi_status
-acpi_ns_evaluate_by_handle (
-        struct acpi_parameter_info      *info);
-
-acpi_status
-acpi_ns_evaluate_by_name (
-        char                            *pathname,
-        struct acpi_parameter_info      *info);
-
-acpi_status
-acpi_ns_evaluate_relative (
-        char                            *pathname,
-        struct acpi_parameter_info      *info);
+acpi_ns_evaluate_by_name(char *pathname, struct acpi_parameter_info *info);
 
 acpi_status
-acpi_ns_execute_control_method (
-        struct acpi_parameter_info      *info);
-
-acpi_status
-acpi_ns_get_object_value (
-        struct acpi_parameter_info      *info);
-
-
-/*
- * Parent/Child/Peer utility functions
- */
-
-#ifdef ACPI_FUTURE_USAGE
-acpi_name
-acpi_ns_find_parent_name (
-        struct acpi_namespace_node      *node_to_search);
-#endif
-
+acpi_ns_evaluate_relative(char *pathname, struct acpi_parameter_info *info);
 
 /*
- * Name and Scope manipulation - nsnames
+ * nsnames - Name and Scope manipulation
  */
+u32 acpi_ns_opens_scope(acpi_object_type type);
 
-u32
-acpi_ns_opens_scope (
-        acpi_object_type                type);
-
-void
-acpi_ns_build_external_path (
-        struct acpi_namespace_node      *node,
-        acpi_size                       size,
-        char                            *name_buffer);
-
-char *
-acpi_ns_get_external_pathname (
-        struct acpi_namespace_node      *node);
+char *acpi_ns_get_external_pathname(struct acpi_namespace_node *node);
 
-char *
-acpi_ns_name_of_current_scope (
-        struct acpi_walk_state          *walk_state);
+char *acpi_ns_name_of_current_scope(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ns_handle_to_pathname (
-        acpi_handle                     target_handle,
-        struct acpi_buffer              *buffer);
+acpi_ns_handle_to_pathname(acpi_handle target_handle,
+                           struct acpi_buffer *buffer);
 
 u8
-acpi_ns_pattern_match (
-        struct acpi_namespace_node      *obj_node,
-        char                            *search_for);
+acpi_ns_pattern_match(struct acpi_namespace_node *obj_node, char *search_for);
 
 acpi_status
-acpi_ns_get_node_by_path (
-        char                            *external_pathname,
-        struct acpi_namespace_node      *in_prefix_node,
-        u32                             flags,
-        struct acpi_namespace_node      **out_node);
-
-acpi_size
-acpi_ns_get_pathname_length (
-        struct acpi_namespace_node      *node);
+acpi_ns_get_node_by_path(char *external_pathname,
+                         struct acpi_namespace_node *in_prefix_node,
+                         u32 flags, struct acpi_namespace_node **out_node);
 
+acpi_size acpi_ns_get_pathname_length(struct acpi_namespace_node *node);
 
 /*
- * Object management for namespace nodes - nsobject
+ * nsobject - Object management for namespace nodes
  */
-
 acpi_status
-acpi_ns_attach_object (
-        struct acpi_namespace_node      *node,
-        union acpi_operand_object       *object,
-        acpi_object_type                type);
+acpi_ns_attach_object(struct acpi_namespace_node *node,
+                      union acpi_operand_object *object, acpi_object_type type);
 
-union acpi_operand_object *
-acpi_ns_get_attached_object (
-        struct acpi_namespace_node      *node);
+union acpi_operand_object *acpi_ns_get_attached_object(struct
+                                                       acpi_namespace_node
+                                                       *node);
 
-union acpi_operand_object *
-acpi_ns_get_secondary_object (
-        union acpi_operand_object       *obj_desc);
+union acpi_operand_object *acpi_ns_get_secondary_object(union
+                                                        acpi_operand_object
+                                                        *obj_desc);
 
 acpi_status
-acpi_ns_attach_data (
-        struct acpi_namespace_node      *node,
-        acpi_object_handler             handler,
-        void                            *data);
+acpi_ns_attach_data(struct acpi_namespace_node *node,
+                    acpi_object_handler handler, void *data);
 
 acpi_status
-acpi_ns_detach_data (
-        struct acpi_namespace_node      *node,
-        acpi_object_handler             handler);
+acpi_ns_detach_data(struct acpi_namespace_node *node,
+                    acpi_object_handler handler);
 
 acpi_status
-acpi_ns_get_attached_data (
-        struct acpi_namespace_node      *node,
-        acpi_object_handler             handler,
-        void                            **data);
-
+acpi_ns_get_attached_data(struct acpi_namespace_node *node,
+                          acpi_object_handler handler, void **data);
 
 /*
- * Namespace searching and entry - nssearch
+ * nssearch - Namespace searching and entry
  */
-
 acpi_status
-acpi_ns_search_and_enter (
-        u32                             entry_name,
-        struct acpi_walk_state          *walk_state,
-        struct acpi_namespace_node      *node,
-        acpi_interpreter_mode           interpreter_mode,
-        acpi_object_type                type,
-        u32                             flags,
-        struct acpi_namespace_node      **ret_node);
+acpi_ns_search_and_enter(u32 entry_name,
+                         struct acpi_walk_state *walk_state,
+                         struct acpi_namespace_node *node,
+                         acpi_interpreter_mode interpreter_mode,
+                         acpi_object_type type,
+                         u32 flags, struct acpi_namespace_node **ret_node);
 
 acpi_status
-acpi_ns_search_node (
-        u32                             entry_name,
-        struct acpi_namespace_node      *node,
-        acpi_object_type                type,
-        struct acpi_namespace_node      **ret_node);
+acpi_ns_search_node(u32 entry_name,
+                    struct acpi_namespace_node *node,
+                    acpi_object_type type,
+                    struct acpi_namespace_node **ret_node);
 
 void
-acpi_ns_install_node (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_namespace_node      *parent_node,
-        struct acpi_namespace_node      *node,
-        acpi_object_type                type);
-
+acpi_ns_install_node(struct acpi_walk_state *walk_state,
+                     struct acpi_namespace_node *parent_node,
+                     struct acpi_namespace_node *node, acpi_object_type type);
 
 /*
- * Utility functions - nsutils
+ * nsutils - Utility functions
  */
+u8 acpi_ns_valid_root_prefix(char prefix);
 
-u8
-acpi_ns_valid_root_prefix (
-        char                            prefix);
-
-u8
-acpi_ns_valid_path_separator (
-        char                            sep);
+acpi_object_type acpi_ns_get_type(struct acpi_namespace_node *node);
 
-acpi_object_type
-acpi_ns_get_type (
-        struct acpi_namespace_node      *node);
-
-u32
-acpi_ns_local (
-        acpi_object_type                type);
+u32 acpi_ns_local(acpi_object_type type);
 
 void
-acpi_ns_report_error (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id,
-        char                            *internal_name,
-        acpi_status                     lookup_status);
+acpi_ns_report_error(char *module_name,
+                     u32 line_number,
+                     u32 component_id,
+                     char *internal_name, acpi_status lookup_status);
 
 void
-acpi_ns_report_method_error (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id,
-        char                            *message,
-        struct acpi_namespace_node      *node,
-        char                            *path,
-        acpi_status                     lookup_status);
+acpi_ns_report_method_error(char *module_name,
+                            u32 line_number,
+                            u32 component_id,
+                            char *message,
+                            struct acpi_namespace_node *node,
+                            char *path, acpi_status lookup_status);
 
-void
-acpi_ns_print_node_pathname (
-        struct acpi_namespace_node      *node,
-        char                            *msg);
+void acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *msg);
 
-acpi_status
-acpi_ns_build_internal_name (
-        struct acpi_namestring_info     *info);
+acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info);
 
-void
-acpi_ns_get_internal_name_length (
-        struct acpi_namestring_info     *info);
+void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info);
 
-acpi_status
-acpi_ns_internalize_name (
-        char                            *dotted_name,
-        char                            **converted_name);
+acpi_status acpi_ns_internalize_name(char *dotted_name, char **converted_name);
 
 acpi_status
-acpi_ns_externalize_name (
-        u32                             internal_name_length,
-        char                            *internal_name,
-        u32                             *converted_name_length,
-        char                            **converted_name);
-
-struct acpi_namespace_node *
-acpi_ns_map_handle_to_node (
-        acpi_handle                     handle);
+acpi_ns_externalize_name(u32 internal_name_length,
+                         char *internal_name,
+                         u32 * converted_name_length, char **converted_name);
 
-acpi_handle
-acpi_ns_convert_entry_to_handle(
-        struct acpi_namespace_node      *node);
-
-void
-acpi_ns_terminate (
-        void);
+struct acpi_namespace_node *acpi_ns_map_handle_to_node(acpi_handle handle);
 
-struct acpi_namespace_node *
-acpi_ns_get_parent_node (
-        struct acpi_namespace_node      *node);
+acpi_handle acpi_ns_convert_entry_to_handle(struct acpi_namespace_node *node);
 
+void acpi_ns_terminate(void);
 
-struct acpi_namespace_node *
-acpi_ns_get_next_valid_node (
-        struct acpi_namespace_node      *node);
+struct acpi_namespace_node *acpi_ns_get_parent_node(struct acpi_namespace_node
+                                                    *node);
 
+struct acpi_namespace_node *acpi_ns_get_next_valid_node(struct
+                                                        acpi_namespace_node
+                                                        *node);
 
-#endif /* __ACNAMESP_H__ */
+#endif                          /* __ACNAMESP_H__ */
diff --git a/include/acpi/acobject.h b/include/acpi/acobject.h
index 036023a940b2..4a326ba6d482 100644
--- a/include/acpi/acobject.h
+++ b/include/acpi/acobject.h
@@ -45,7 +45,6 @@
 #ifndef _ACOBJECT_H
 #define _ACOBJECT_H
 
-
 /*
  * The union acpi_operand_object    is used to pass AML operands from the dispatcher
  * to the interpreter, and to keep track of the various handlers such as
@@ -81,7 +80,6 @@
 #define AOPOBJ_SETUP_COMPLETE       0x10
 #define AOPOBJ_SINGLE_DATUM         0x20
 
-
 /*
  * Common bitfield for the field objects
  * "Field Datum"  -- a datum from the actual field object
@@ -96,8 +94,7 @@
         u8                                      start_field_bit_offset;/* Bit offset within first field datum (0-63) */\
         u8                                      access_bit_width;   /* Read/Write size in bits (8-64) */\
         u32                                     value;              /* Value to store into the Bank or Index register */\
-        struct acpi_namespace_node              *node;              /* Link back to parent node */
-
+        struct acpi_namespace_node              *node;  /* Link back to parent node */
 
 /*
  * Fields common to both Strings and Buffers
@@ -105,15 +102,13 @@
 #define ACPI_COMMON_BUFFER_INFO \
         u32                                     length;
 
-
 /*
  * Common fields for objects that support ASL notifications
  */
 #define ACPI_COMMON_NOTIFY_INFO \
         union acpi_operand_object               *system_notify;     /* Handler for system notifies */\
         union acpi_operand_object               *device_notify;     /* Handler for driver notifies */\
-        union acpi_operand_object               *handler;           /* Handler for Address space */
-
+        union acpi_operand_object               *handler;       /* Handler for Address space */
 
 /******************************************************************************
  *
@@ -121,160 +116,110 @@
  *
  *****************************************************************************/
 
-struct acpi_object_common
-{
-        ACPI_OBJECT_COMMON_HEADER
-};
+struct acpi_object_common {
+ACPI_OBJECT_COMMON_HEADER};
 
-
-struct acpi_object_integer
-{
-        ACPI_OBJECT_COMMON_HEADER
-        acpi_integer                            value;
+struct acpi_object_integer {
+        ACPI_OBJECT_COMMON_HEADER acpi_integer value;
 };
 
 /*
  * Note: The String and Buffer object must be identical through the Pointer
  * element.  There is code that depends on this.
  */
-struct acpi_object_string           /* Null terminated, ASCII characters only */
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_BUFFER_INFO
-        char                                    *pointer;           /* String in AML stream or allocated string */
+struct acpi_object_string {     /* Null terminated, ASCII characters only */
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_BUFFER_INFO char *pointer;        /* String in AML stream or allocated string */
 };
 
-
-struct acpi_object_buffer
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_BUFFER_INFO
-        u8                                      *pointer;           /* Buffer in AML stream or allocated buffer */
-        struct acpi_namespace_node              *node;              /* Link back to parent node */
-        u8                                      *aml_start;
-        u32                                     aml_length;
+struct acpi_object_buffer {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_BUFFER_INFO u8 * pointer; /* Buffer in AML stream or allocated buffer */
+        struct acpi_namespace_node *node;       /* Link back to parent node */
+        u8 *aml_start;
+        u32 aml_length;
 };
 
-
-struct acpi_object_package
-{
-        ACPI_OBJECT_COMMON_HEADER
-
-        u32                                     count;              /* # of elements in package */
-        u32                                     aml_length;
-        u8                                      *aml_start;
-        struct acpi_namespace_node              *node;              /* Link back to parent node */
-        union acpi_operand_object               **elements;         /* Array of pointers to acpi_objects */
+struct acpi_object_package {
+        ACPI_OBJECT_COMMON_HEADER u32 count;    /* # of elements in package */
+        u32 aml_length;
+        u8 *aml_start;
+        struct acpi_namespace_node *node;       /* Link back to parent node */
+        union acpi_operand_object **elements;   /* Array of pointers to acpi_objects */
 };
 
-
 /******************************************************************************
  *
  * Complex data types
  *
  *****************************************************************************/
 
-struct acpi_object_event
-{
-        ACPI_OBJECT_COMMON_HEADER
-        void                                    *semaphore;
+struct acpi_object_event {
+        ACPI_OBJECT_COMMON_HEADER void *semaphore;
 };
 
-
 #define ACPI_INFINITE_CONCURRENCY   0xFF
 
 typedef
-acpi_status (*ACPI_INTERNAL_METHOD) (
-        struct acpi_walk_state          *walk_state);
-
-struct acpi_object_method
-{
-        ACPI_OBJECT_COMMON_HEADER
-        u8                                      method_flags;
-        u8                                      param_count;
-        u32                                     aml_length;
-        void                                    *semaphore;
-        u8                                      *aml_start;
-        ACPI_INTERNAL_METHOD            implementation;
-        u8                                      concurrency;
-        u8                                      thread_count;
-        acpi_owner_id                           owning_id;
+acpi_status(*ACPI_INTERNAL_METHOD) (struct acpi_walk_state * walk_state);
+
+struct acpi_object_method {
+        ACPI_OBJECT_COMMON_HEADER u8 method_flags;
+        u8 param_count;
+        u32 aml_length;
+        void *semaphore;
+        u8 *aml_start;
+        ACPI_INTERNAL_METHOD implementation;
+        u8 concurrency;
+        u8 thread_count;
+        acpi_owner_id owner_id;
 };
 
-
-struct acpi_object_mutex
-{
-        ACPI_OBJECT_COMMON_HEADER
-        u8                                      sync_level;         /* 0-15, specified in Mutex() call */
-        u16                                     acquisition_depth;  /* Allow multiple Acquires, same thread */
-        struct acpi_thread_state                *owner_thread;      /* Current owner of the mutex */
-        void                                    *semaphore;         /* Actual OS synchronization object */
-        union acpi_operand_object               *prev;              /* Link for list of acquired mutexes */
-        union acpi_operand_object               *next;              /* Link for list of acquired mutexes */
-        struct acpi_namespace_node              *node;              /* Containing namespace node */
-        u8                                      original_sync_level; /* Owner's original sync level (0-15) */
+struct acpi_object_mutex {
+        ACPI_OBJECT_COMMON_HEADER u8 sync_level;        /* 0-15, specified in Mutex() call */
+        u16 acquisition_depth;  /* Allow multiple Acquires, same thread */
+        struct acpi_thread_state *owner_thread; /* Current owner of the mutex */
+        void *semaphore;        /* Actual OS synchronization object */
+        union acpi_operand_object *prev;        /* Link for list of acquired mutexes */
+        union acpi_operand_object *next;        /* Link for list of acquired mutexes */
+        struct acpi_namespace_node *node;       /* Containing namespace node */
+        u8 original_sync_level; /* Owner's original sync level (0-15) */
 };
 
-
-struct acpi_object_region
-{
-        ACPI_OBJECT_COMMON_HEADER
-
-        u8                                      space_id;
-        union acpi_operand_object               *handler;           /* Handler for region access */
-        struct acpi_namespace_node              *node;              /* Containing namespace node */
-        union acpi_operand_object               *next;
-        u32                                     length;
-        acpi_physical_address                   address;
+struct acpi_object_region {
+        ACPI_OBJECT_COMMON_HEADER u8 space_id;
+        union acpi_operand_object *handler;     /* Handler for region access */
+        struct acpi_namespace_node *node;       /* Containing namespace node */
+        union acpi_operand_object *next;
+        u32 length;
+        acpi_physical_address address;
 };
 
-
 /******************************************************************************
  *
  * Objects that can be notified.  All share a common notify_info area.
  *
  *****************************************************************************/
 
-struct acpi_object_notify_common            /* COMMON NOTIFY for POWER, PROCESSOR, DEVICE, and THERMAL */
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_NOTIFY_INFO
-};
-
-
-struct acpi_object_device
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_NOTIFY_INFO
-        struct acpi_gpe_block_info              *gpe_block;
-};
-
+struct acpi_object_notify_common {      /* COMMON NOTIFY for POWER, PROCESSOR, DEVICE, and THERMAL */
+ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO};
 
-struct acpi_object_power_resource
-{
+struct acpi_object_device {
         ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_NOTIFY_INFO
-        u32                                     system_level;
-        u32                                     resource_order;
+            ACPI_COMMON_NOTIFY_INFO struct acpi_gpe_block_info *gpe_block;
 };
 
-
-struct acpi_object_processor
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_NOTIFY_INFO
-        u32                                     proc_id;
-        u32                                     length;
-        acpi_io_address                         address;
+struct acpi_object_power_resource {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO u32 system_level;
+        u32 resource_order;
 };
 
-
-struct acpi_object_thermal_zone
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_NOTIFY_INFO
+struct acpi_object_processor {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO u32 proc_id;
+        u32 length;
+        acpi_io_address address;
 };
 
+struct acpi_object_thermal_zone {
+ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO};
 
 /******************************************************************************
  *
@@ -282,90 +227,63 @@ struct acpi_object_thermal_zone
  *
  *****************************************************************************/
 
-struct acpi_object_field_common                         /* COMMON FIELD (for BUFFER, REGION, BANK, and INDEX fields) */
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_FIELD_INFO
-        union acpi_operand_object               *region_obj;        /* Containing Operation Region object */
-                          /* (REGION/BANK fields only) */
+struct acpi_object_field_common {       /* COMMON FIELD (for BUFFER, REGION, BANK, and INDEX fields) */
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj; /* Containing Operation Region object */
+        /* (REGION/BANK fields only) */
 };
 
-
-struct acpi_object_region_field
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_FIELD_INFO
-        union acpi_operand_object               *region_obj;        /* Containing op_region object */
+struct acpi_object_region_field {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj; /* Containing op_region object */
 };
 
-
-struct acpi_object_bank_field
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_FIELD_INFO
-        union acpi_operand_object               *region_obj;        /* Containing op_region object */
-        union acpi_operand_object               *bank_obj;          /* bank_select Register object */
+struct acpi_object_bank_field {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj; /* Containing op_region object */
+        union acpi_operand_object *bank_obj;    /* bank_select Register object */
 };
 
-
-struct acpi_object_index_field
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_FIELD_INFO
-
-        /*
-         * No "region_obj" pointer needed since the Index and Data registers
-         * are each field definitions unto themselves.
-         */
-        union acpi_operand_object               *index_obj;         /* Index register */
-        union acpi_operand_object               *data_obj;          /* Data register */
+struct acpi_object_index_field {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO
+            /*
+             * No "region_obj" pointer needed since the Index and Data registers
+             * are each field definitions unto themselves.
+             */
+        union acpi_operand_object *index_obj;   /* Index register */
+        union acpi_operand_object *data_obj;    /* Data register */
 };
 
-
 /* The buffer_field is different in that it is part of a Buffer, not an op_region */
 
-struct acpi_object_buffer_field
-{
-        ACPI_OBJECT_COMMON_HEADER
-        ACPI_COMMON_FIELD_INFO
-        union acpi_operand_object               *buffer_obj;        /* Containing Buffer object */
+struct acpi_object_buffer_field {
+        ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *buffer_obj; /* Containing Buffer object */
 };
 
-
 /******************************************************************************
  *
  * Objects for handlers
  *
  *****************************************************************************/
 
-struct acpi_object_notify_handler
-{
-        ACPI_OBJECT_COMMON_HEADER
-        struct acpi_namespace_node              *node;              /* Parent device */
-        acpi_notify_handler                     handler;
-        void                                    *context;
+struct acpi_object_notify_handler {
+        ACPI_OBJECT_COMMON_HEADER struct acpi_namespace_node *node;     /* Parent device */
+        acpi_notify_handler handler;
+        void *context;
 };
 
-
 /* Flags for address handler */
 
 #define ACPI_ADDR_HANDLER_DEFAULT_INSTALLED  0x1
 
-
-struct acpi_object_addr_handler
-{
-        ACPI_OBJECT_COMMON_HEADER
-        u8                                      space_id;
-        u16                                     hflags;
-        acpi_adr_space_handler                  handler;
-        struct acpi_namespace_node              *node;              /* Parent device */
-        void                                    *context;
-        acpi_adr_space_setup                    setup;
-        union acpi_operand_object               *region_list;       /* regions using this handler */
-        union acpi_operand_object               *next;
+struct acpi_object_addr_handler {
+        ACPI_OBJECT_COMMON_HEADER u8 space_id;
+        u16 hflags;
+        acpi_adr_space_handler handler;
+        struct acpi_namespace_node *node;       /* Parent device */
+        void *context;
+        acpi_adr_space_setup setup;
+        union acpi_operand_object *region_list; /* regions using this handler */
+        union acpi_operand_object *next;
 };
 
-
 /******************************************************************************
  *
  * Special internal objects
@@ -376,18 +294,15 @@ struct acpi_object_addr_handler
  * The Reference object type is used for these opcodes:
  * Arg[0-6], Local[0-7], index_op, name_op, zero_op, one_op, ones_op, debug_op
  */
-struct acpi_object_reference
-{
-        ACPI_OBJECT_COMMON_HEADER
-        u8                                      target_type;        /* Used for index_op */
-        u16                                     opcode;
-        u32                                     offset;             /* Used for arg_op, local_op, and index_op */
-        void                                    *object;            /* name_op=>HANDLE to obj, index_op=>union acpi_operand_object  */
-        struct acpi_namespace_node              *node;
-        union acpi_operand_object               **where;
+struct acpi_object_reference {
+        ACPI_OBJECT_COMMON_HEADER u8 target_type;       /* Used for index_op */
+        u16 opcode;
+        u32 offset;             /* Used for arg_op, local_op, and index_op */
+        void *object;           /* name_op=>HANDLE to obj, index_op=>union acpi_operand_object  */
+        struct acpi_namespace_node *node;
+        union acpi_operand_object **where;
 };
 
-
 /*
  * Extra object is used as additional storage for types that
  * have AML code in their declarations (term_args) that must be
@@ -395,83 +310,71 @@ struct acpi_object_reference
  *
  * Currently: Region and field_unit types
  */
-struct acpi_object_extra
-{
-        ACPI_OBJECT_COMMON_HEADER
-        u8                                      byte_fill1;
-        u16                                     word_fill1;
-        u32                                     aml_length;
-        u8                                      *aml_start;
-        struct acpi_namespace_node              *method_REG;        /* _REG method for this region (if any) */
-        void                                    *region_context;    /* Region-specific data */
+struct acpi_object_extra {
+        ACPI_OBJECT_COMMON_HEADER u8 byte_fill1;
+        u16 word_fill1;
+        u32 aml_length;
+        u8 *aml_start;
+        struct acpi_namespace_node *method_REG; /* _REG method for this region (if any) */
+        void *region_context;   /* Region-specific data */
 };
 
-
 /* Additional data that can be attached to namespace nodes */
 
-struct acpi_object_data
-{
-        ACPI_OBJECT_COMMON_HEADER
-        acpi_object_handler                     handler;
-        void                                    *pointer;
+struct acpi_object_data {
+        ACPI_OBJECT_COMMON_HEADER acpi_object_handler handler;
+        void *pointer;
 };
 
-
 /* Structure used when objects are cached for reuse */
 
-struct acpi_object_cache_list
-{
-        ACPI_OBJECT_COMMON_HEADER
-        union acpi_operand_object               *next;              /* Link for object cache and internal lists*/
+struct acpi_object_cache_list {
+        ACPI_OBJECT_COMMON_HEADER union acpi_operand_object *next;      /* Link for object cache and internal lists */
 };
 
-
 /******************************************************************************
  *
  * union acpi_operand_object Descriptor - a giant union of all of the above
  *
  *****************************************************************************/
 
-union acpi_operand_object
-{
-        struct acpi_object_common               common;
-        struct acpi_object_integer              integer;
-        struct acpi_object_string               string;
-        struct acpi_object_buffer               buffer;
-        struct acpi_object_package              package;
-        struct acpi_object_event                event;
-        struct acpi_object_method               method;
-        struct acpi_object_mutex                mutex;
-        struct acpi_object_region               region;
-        struct acpi_object_notify_common        common_notify;
-        struct acpi_object_device               device;
-        struct acpi_object_power_resource       power_resource;
-        struct acpi_object_processor            processor;
-        struct acpi_object_thermal_zone         thermal_zone;
-        struct acpi_object_field_common         common_field;
-        struct acpi_object_region_field         field;
-        struct acpi_object_buffer_field         buffer_field;
-        struct acpi_object_bank_field           bank_field;
-        struct acpi_object_index_field          index_field;
-        struct acpi_object_notify_handler       notify;
-        struct acpi_object_addr_handler         address_space;
-        struct acpi_object_reference            reference;
-        struct acpi_object_extra                extra;
-        struct acpi_object_data                 data;
-        struct acpi_object_cache_list           cache;
+union acpi_operand_object {
+        struct acpi_object_common common;
+        struct acpi_object_integer integer;
+        struct acpi_object_string string;
+        struct acpi_object_buffer buffer;
+        struct acpi_object_package package;
+        struct acpi_object_event event;
+        struct acpi_object_method method;
+        struct acpi_object_mutex mutex;
+        struct acpi_object_region region;
+        struct acpi_object_notify_common common_notify;
+        struct acpi_object_device device;
+        struct acpi_object_power_resource power_resource;
+        struct acpi_object_processor processor;
+        struct acpi_object_thermal_zone thermal_zone;
+        struct acpi_object_field_common common_field;
+        struct acpi_object_region_field field;
+        struct acpi_object_buffer_field buffer_field;
+        struct acpi_object_bank_field bank_field;
+        struct acpi_object_index_field index_field;
+        struct acpi_object_notify_handler notify;
+        struct acpi_object_addr_handler address_space;
+        struct acpi_object_reference reference;
+        struct acpi_object_extra extra;
+        struct acpi_object_data data;
+        struct acpi_object_cache_list cache;
 };
 
-
 /******************************************************************************
  *
  * union acpi_descriptor - objects that share a common descriptor identifier
  *
  *****************************************************************************/
 
-
 /* Object descriptor types */
 
-#define ACPI_DESC_TYPE_CACHED           0x01        /* Used only when object is cached */
+#define ACPI_DESC_TYPE_CACHED           0x01    /* Used only when object is cached */
 #define ACPI_DESC_TYPE_STATE            0x02
 #define ACPI_DESC_TYPE_STATE_UPDATE     0x03
 #define ACPI_DESC_TYPE_STATE_PACKAGE    0x04
@@ -488,14 +391,11 @@ union acpi_operand_object
 #define ACPI_DESC_TYPE_NAMED            0x0F
 #define ACPI_DESC_TYPE_MAX              0x0F
 
-
-union acpi_descriptor
-{
-        u8                                      descriptor_id;  /* To differentiate various internal objs */\
-        union acpi_operand_object               object;
-        struct acpi_namespace_node              node;
-        union acpi_parse_object                 op;
+union acpi_descriptor {
+        u8 descriptor_id;       /* To differentiate various internal objs */
+        union acpi_operand_object object;
+        struct acpi_namespace_node node;
+        union acpi_parse_object op;
 };
 
-
-#endif /* _ACOBJECT_H */
+#endif                          /* _ACOBJECT_H */
diff --git a/include/acpi/acopcode.h b/include/acpi/acopcode.h
new file mode 100644
index 000000000000..64da42992199
--- /dev/null
+++ b/include/acpi/acopcode.h
@@ -0,0 +1,323 @@
+/******************************************************************************
+ *
+ * Name: acopcode.h - AML opcode information for the AML parser and interpreter
+ *
+ *****************************************************************************/
+
+/*
+ * Copyright (C) 2000 - 2005, R. Byron Moore
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    substantially similar to the "NO WARRANTY" disclaimer below
+ *    ("Disclaimer") and any redistribution must be conditioned upon
+ *    including a substantially similar Disclaimer requirement for further
+ *    binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#ifndef __ACOPCODE_H__
+#define __ACOPCODE_H__
+
+#define MAX_EXTENDED_OPCODE         0x88
+#define NUM_EXTENDED_OPCODE         (MAX_EXTENDED_OPCODE + 1)
+#define MAX_INTERNAL_OPCODE
+#define NUM_INTERNAL_OPCODE         (MAX_INTERNAL_OPCODE + 1)
+
+/* Used for non-assigned opcodes */
+
+#define _UNK                        0x6B
+
+/*
+ * Reserved ASCII characters.  Do not use any of these for
+ * internal opcodes, since they are used to differentiate
+ * name strings from AML opcodes
+ */
+#define _ASC                        0x6C
+#define _NAM                        0x6C
+#define _PFX                        0x6D
+
+/*
+ * All AML opcodes and the parse-time arguments for each.  Used by the AML
+ * parser  Each list is compressed into a 32-bit number and stored in the
+ * master opcode table (in psopcode.c).
+ */
+#define ARGP_ACCESSFIELD_OP             ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_ACQUIRE_OP                 ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_WORDDATA)
+#define ARGP_ADD_OP                     ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_ALIAS_OP                   ARGP_LIST2 (ARGP_NAMESTRING, ARGP_NAME)
+#define ARGP_ARG0                       ARG_NONE
+#define ARGP_ARG1                       ARG_NONE
+#define ARGP_ARG2                       ARG_NONE
+#define ARGP_ARG3                       ARG_NONE
+#define ARGP_ARG4                       ARG_NONE
+#define ARGP_ARG5                       ARG_NONE
+#define ARGP_ARG6                       ARG_NONE
+#define ARGP_BANK_FIELD_OP              ARGP_LIST6 (ARGP_PKGLENGTH,  ARGP_NAMESTRING,    ARGP_NAMESTRING,ARGP_TERMARG,   ARGP_BYTEDATA,  ARGP_FIELDLIST)
+#define ARGP_BIT_AND_OP                 ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_BIT_NAND_OP                ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_BIT_NOR_OP                 ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_BIT_NOT_OP                 ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_BIT_OR_OP                  ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_BIT_XOR_OP                 ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_BREAK_OP                   ARG_NONE
+#define ARGP_BREAK_POINT_OP             ARG_NONE
+#define ARGP_BUFFER_OP                  ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_BYTELIST)
+#define ARGP_BYTE_OP                    ARGP_LIST1 (ARGP_BYTEDATA)
+#define ARGP_BYTELIST_OP                ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_CONCAT_OP                  ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_CONCAT_RES_OP              ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_COND_REF_OF_OP             ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_SUPERNAME)
+#define ARGP_CONTINUE_OP                ARG_NONE
+#define ARGP_COPY_OP                    ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_SIMPLENAME)
+#define ARGP_CREATE_BIT_FIELD_OP        ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_NAME)
+#define ARGP_CREATE_BYTE_FIELD_OP       ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_NAME)
+#define ARGP_CREATE_DWORD_FIELD_OP      ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_NAME)
+#define ARGP_CREATE_FIELD_OP            ARGP_LIST4 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TERMARG,   ARGP_NAME)
+#define ARGP_CREATE_QWORD_FIELD_OP      ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_NAME)
+#define ARGP_CREATE_WORD_FIELD_OP       ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_NAME)
+#define ARGP_DATA_REGION_OP             ARGP_LIST4 (ARGP_NAME,       ARGP_TERMARG,       ARGP_TERMARG,   ARGP_TERMARG)
+#define ARGP_DEBUG_OP                   ARG_NONE
+#define ARGP_DECREMENT_OP               ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_DEREF_OF_OP                ARGP_LIST1 (ARGP_TERMARG)
+#define ARGP_DEVICE_OP                  ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_OBJLIST)
+#define ARGP_DIVIDE_OP                  ARGP_LIST4 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET,    ARGP_TARGET)
+#define ARGP_DWORD_OP                   ARGP_LIST1 (ARGP_DWORDDATA)
+#define ARGP_ELSE_OP                    ARGP_LIST2 (ARGP_PKGLENGTH,  ARGP_TERMLIST)
+#define ARGP_EVENT_OP                   ARGP_LIST1 (ARGP_NAME)
+#define ARGP_FATAL_OP                   ARGP_LIST3 (ARGP_BYTEDATA,   ARGP_DWORDDATA,     ARGP_TERMARG)
+#define ARGP_FIELD_OP                   ARGP_LIST4 (ARGP_PKGLENGTH,  ARGP_NAMESTRING,    ARGP_BYTEDATA,  ARGP_FIELDLIST)
+#define ARGP_FIND_SET_LEFT_BIT_OP       ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_FIND_SET_RIGHT_BIT_OP      ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_FROM_BCD_OP                ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_IF_OP                      ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_TERMLIST)
+#define ARGP_INCREMENT_OP               ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_INDEX_FIELD_OP             ARGP_LIST5 (ARGP_PKGLENGTH,  ARGP_NAMESTRING,    ARGP_NAMESTRING,ARGP_BYTEDATA,  ARGP_FIELDLIST)
+#define ARGP_INDEX_OP                   ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_LAND_OP                    ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LEQUAL_OP                  ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LGREATER_OP                ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LGREATEREQUAL_OP           ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LLESS_OP                   ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LLESSEQUAL_OP              ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LNOT_OP                    ARGP_LIST1 (ARGP_TERMARG)
+#define ARGP_LNOTEQUAL_OP               ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_LOAD_OP                    ARGP_LIST2 (ARGP_NAMESTRING, ARGP_SUPERNAME)
+#define ARGP_LOAD_TABLE_OP              ARGP_LIST6 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TERMARG,   ARGP_TERMARG,  ARGP_TERMARG,   ARGP_TERMARG)
+#define ARGP_LOCAL0                     ARG_NONE
+#define ARGP_LOCAL1                     ARG_NONE
+#define ARGP_LOCAL2                     ARG_NONE
+#define ARGP_LOCAL3                     ARG_NONE
+#define ARGP_LOCAL4                     ARG_NONE
+#define ARGP_LOCAL5                     ARG_NONE
+#define ARGP_LOCAL6                     ARG_NONE
+#define ARGP_LOCAL7                     ARG_NONE
+#define ARGP_LOR_OP                     ARGP_LIST2 (ARGP_TERMARG,    ARGP_TERMARG)
+#define ARGP_MATCH_OP                   ARGP_LIST6 (ARGP_TERMARG,    ARGP_BYTEDATA,      ARGP_TERMARG,   ARGP_BYTEDATA,  ARGP_TERMARG,   ARGP_TERMARG)
+#define ARGP_METHOD_OP                  ARGP_LIST4 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_BYTEDATA,  ARGP_TERMLIST)
+#define ARGP_METHODCALL_OP              ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_MID_OP                     ARGP_LIST4 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TERMARG,   ARGP_TARGET)
+#define ARGP_MOD_OP                     ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_MULTIPLY_OP                ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_MUTEX_OP                   ARGP_LIST2 (ARGP_NAME,       ARGP_BYTEDATA)
+#define ARGP_NAME_OP                    ARGP_LIST2 (ARGP_NAME,       ARGP_DATAOBJ)
+#define ARGP_NAMEDFIELD_OP              ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_NAMEPATH_OP                ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_NOOP_OP                    ARG_NONE
+#define ARGP_NOTIFY_OP                  ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_TERMARG)
+#define ARGP_ONE_OP                     ARG_NONE
+#define ARGP_ONES_OP                    ARG_NONE
+#define ARGP_PACKAGE_OP                 ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_BYTEDATA,      ARGP_DATAOBJLIST)
+#define ARGP_POWER_RES_OP               ARGP_LIST5 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_BYTEDATA,  ARGP_WORDDATA,  ARGP_OBJLIST)
+#define ARGP_PROCESSOR_OP               ARGP_LIST6 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_BYTEDATA,  ARGP_DWORDDATA, ARGP_BYTEDATA,  ARGP_OBJLIST)
+#define ARGP_QWORD_OP                   ARGP_LIST1 (ARGP_QWORDDATA)
+#define ARGP_REF_OF_OP                  ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_REGION_OP                  ARGP_LIST4 (ARGP_NAME,       ARGP_BYTEDATA,      ARGP_TERMARG,   ARGP_TERMARG)
+#define ARGP_RELEASE_OP                 ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_RESERVEDFIELD_OP           ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_RESET_OP                   ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_RETURN_OP                  ARGP_LIST1 (ARGP_TERMARG)
+#define ARGP_REVISION_OP                ARG_NONE
+#define ARGP_SCOPE_OP                   ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_TERMLIST)
+#define ARGP_SHIFT_LEFT_OP              ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_SHIFT_RIGHT_OP             ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_SIGNAL_OP                  ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_SIZE_OF_OP                 ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_SLEEP_OP                   ARGP_LIST1 (ARGP_TERMARG)
+#define ARGP_STALL_OP                   ARGP_LIST1 (ARGP_TERMARG)
+#define ARGP_STATICSTRING_OP            ARGP_LIST1 (ARGP_NAMESTRING)
+#define ARGP_STORE_OP                   ARGP_LIST2 (ARGP_TERMARG,    ARGP_SUPERNAME)
+#define ARGP_STRING_OP                  ARGP_LIST1 (ARGP_CHARLIST)
+#define ARGP_SUBTRACT_OP                ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_THERMAL_ZONE_OP            ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_NAME,          ARGP_OBJLIST)
+#define ARGP_TIMER_OP                   ARG_NONE
+#define ARGP_TO_BCD_OP                  ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_TO_BUFFER_OP               ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_TO_DEC_STR_OP              ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_TO_HEX_STR_OP              ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_TO_INTEGER_OP              ARGP_LIST2 (ARGP_TERMARG,    ARGP_TARGET)
+#define ARGP_TO_STRING_OP               ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
+#define ARGP_TYPE_OP                    ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_UNLOAD_OP                  ARGP_LIST1 (ARGP_SUPERNAME)
+#define ARGP_VAR_PACKAGE_OP             ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_DATAOBJLIST)
+#define ARGP_WAIT_OP                    ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_TERMARG)
+#define ARGP_WHILE_OP                   ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_TERMLIST)
+#define ARGP_WORD_OP                    ARGP_LIST1 (ARGP_WORDDATA)
+#define ARGP_ZERO_OP                    ARG_NONE
+
+/*
+ * All AML opcodes and the runtime arguments for each.  Used by the AML
+ * interpreter  Each list is compressed into a 32-bit number and stored
+ * in the master opcode table (in psopcode.c).
+ *
+ * (Used by prep_operands procedure and the ASL Compiler)
+ */
+#define ARGI_ACCESSFIELD_OP             ARGI_INVALID_OPCODE
+#define ARGI_ACQUIRE_OP                 ARGI_LIST2 (ARGI_MUTEX,      ARGI_INTEGER)
+#define ARGI_ADD_OP                     ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_ALIAS_OP                   ARGI_INVALID_OPCODE
+#define ARGI_ARG0                       ARG_NONE
+#define ARGI_ARG1                       ARG_NONE
+#define ARGI_ARG2                       ARG_NONE
+#define ARGI_ARG3                       ARG_NONE
+#define ARGI_ARG4                       ARG_NONE
+#define ARGI_ARG5                       ARG_NONE
+#define ARGI_ARG6                       ARG_NONE
+#define ARGI_BANK_FIELD_OP              ARGI_INVALID_OPCODE
+#define ARGI_BIT_AND_OP                 ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_BIT_NAND_OP                ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_BIT_NOR_OP                 ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_BIT_NOT_OP                 ARGI_LIST2 (ARGI_INTEGER,    ARGI_TARGETREF)
+#define ARGI_BIT_OR_OP                  ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_BIT_XOR_OP                 ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_BREAK_OP                   ARG_NONE
+#define ARGI_BREAK_POINT_OP             ARG_NONE
+#define ARGI_BUFFER_OP                  ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_BYTE_OP                    ARGI_INVALID_OPCODE
+#define ARGI_BYTELIST_OP                ARGI_INVALID_OPCODE
+#define ARGI_CONCAT_OP                  ARGI_LIST3 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA,   ARGI_TARGETREF)
+#define ARGI_CONCAT_RES_OP              ARGI_LIST3 (ARGI_BUFFER,     ARGI_BUFFER,        ARGI_TARGETREF)
+#define ARGI_COND_REF_OF_OP             ARGI_LIST2 (ARGI_OBJECT_REF, ARGI_TARGETREF)
+#define ARGI_CONTINUE_OP                ARGI_INVALID_OPCODE
+#define ARGI_COPY_OP                    ARGI_LIST2 (ARGI_ANYTYPE,    ARGI_SIMPLE_TARGET)
+#define ARGI_CREATE_BIT_FIELD_OP        ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_REFERENCE)
+#define ARGI_CREATE_BYTE_FIELD_OP       ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_REFERENCE)
+#define ARGI_CREATE_DWORD_FIELD_OP      ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_REFERENCE)
+#define ARGI_CREATE_FIELD_OP            ARGI_LIST4 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_INTEGER,      ARGI_REFERENCE)
+#define ARGI_CREATE_QWORD_FIELD_OP      ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_REFERENCE)
+#define ARGI_CREATE_WORD_FIELD_OP       ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_REFERENCE)
+#define ARGI_DATA_REGION_OP             ARGI_LIST3 (ARGI_STRING,     ARGI_STRING,        ARGI_STRING)
+#define ARGI_DEBUG_OP                   ARG_NONE
+#define ARGI_DECREMENT_OP               ARGI_LIST1 (ARGI_INTEGER_REF)
+#define ARGI_DEREF_OF_OP                ARGI_LIST1 (ARGI_REF_OR_STRING)
+#define ARGI_DEVICE_OP                  ARGI_INVALID_OPCODE
+#define ARGI_DIVIDE_OP                  ARGI_LIST4 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF,    ARGI_TARGETREF)
+#define ARGI_DWORD_OP                   ARGI_INVALID_OPCODE
+#define ARGI_ELSE_OP                    ARGI_INVALID_OPCODE
+#define ARGI_EVENT_OP                   ARGI_INVALID_OPCODE
+#define ARGI_FATAL_OP                   ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_INTEGER)
+#define ARGI_FIELD_OP                   ARGI_INVALID_OPCODE
+#define ARGI_FIND_SET_LEFT_BIT_OP       ARGI_LIST2 (ARGI_INTEGER,    ARGI_TARGETREF)
+#define ARGI_FIND_SET_RIGHT_BIT_OP      ARGI_LIST2 (ARGI_INTEGER,    ARGI_TARGETREF)
+#define ARGI_FROM_BCD_OP                ARGI_LIST2 (ARGI_INTEGER,    ARGI_FIXED_TARGET)
+#define ARGI_IF_OP                      ARGI_INVALID_OPCODE
+#define ARGI_INCREMENT_OP               ARGI_LIST1 (ARGI_INTEGER_REF)
+#define ARGI_INDEX_FIELD_OP             ARGI_INVALID_OPCODE
+#define ARGI_INDEX_OP                   ARGI_LIST3 (ARGI_COMPLEXOBJ, ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_LAND_OP                    ARGI_LIST2 (ARGI_INTEGER,    ARGI_INTEGER)
+#define ARGI_LEQUAL_OP                  ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA)
+#define ARGI_LGREATER_OP                ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA)
+#define ARGI_LGREATEREQUAL_OP           ARGI_INVALID_OPCODE
+#define ARGI_LLESS_OP                   ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA)
+#define ARGI_LLESSEQUAL_OP              ARGI_INVALID_OPCODE
+#define ARGI_LNOT_OP                    ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_LNOTEQUAL_OP               ARGI_INVALID_OPCODE
+#define ARGI_LOAD_OP                    ARGI_LIST2 (ARGI_REGION_OR_FIELD,ARGI_TARGETREF)
+#define ARGI_LOAD_TABLE_OP              ARGI_LIST6 (ARGI_STRING,     ARGI_STRING,        ARGI_STRING,       ARGI_STRING,    ARGI_STRING, ARGI_ANYTYPE)
+#define ARGI_LOCAL0                     ARG_NONE
+#define ARGI_LOCAL1                     ARG_NONE
+#define ARGI_LOCAL2                     ARG_NONE
+#define ARGI_LOCAL3                     ARG_NONE
+#define ARGI_LOCAL4                     ARG_NONE
+#define ARGI_LOCAL5                     ARG_NONE
+#define ARGI_LOCAL6                     ARG_NONE
+#define ARGI_LOCAL7                     ARG_NONE
+#define ARGI_LOR_OP                     ARGI_LIST2 (ARGI_INTEGER,    ARGI_INTEGER)
+#define ARGI_MATCH_OP                   ARGI_LIST6 (ARGI_PACKAGE,    ARGI_INTEGER,   ARGI_COMPUTEDATA,      ARGI_INTEGER,ARGI_COMPUTEDATA,ARGI_INTEGER)
+#define ARGI_METHOD_OP                  ARGI_INVALID_OPCODE
+#define ARGI_METHODCALL_OP              ARGI_INVALID_OPCODE
+#define ARGI_MID_OP                     ARGI_LIST4 (ARGI_BUFFER_OR_STRING,ARGI_INTEGER,  ARGI_INTEGER,      ARGI_TARGETREF)
+#define ARGI_MOD_OP                     ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_MULTIPLY_OP                ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_MUTEX_OP                   ARGI_INVALID_OPCODE
+#define ARGI_NAME_OP                    ARGI_INVALID_OPCODE
+#define ARGI_NAMEDFIELD_OP              ARGI_INVALID_OPCODE
+#define ARGI_NAMEPATH_OP                ARGI_INVALID_OPCODE
+#define ARGI_NOOP_OP                    ARG_NONE
+#define ARGI_NOTIFY_OP                  ARGI_LIST2 (ARGI_DEVICE_REF, ARGI_INTEGER)
+#define ARGI_ONE_OP                     ARG_NONE
+#define ARGI_ONES_OP                    ARG_NONE
+#define ARGI_PACKAGE_OP                 ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_POWER_RES_OP               ARGI_INVALID_OPCODE
+#define ARGI_PROCESSOR_OP               ARGI_INVALID_OPCODE
+#define ARGI_QWORD_OP                   ARGI_INVALID_OPCODE
+#define ARGI_REF_OF_OP                  ARGI_LIST1 (ARGI_OBJECT_REF)
+#define ARGI_REGION_OP                  ARGI_LIST2 (ARGI_INTEGER,    ARGI_INTEGER)
+#define ARGI_RELEASE_OP                 ARGI_LIST1 (ARGI_MUTEX)
+#define ARGI_RESERVEDFIELD_OP           ARGI_INVALID_OPCODE
+#define ARGI_RESET_OP                   ARGI_LIST1 (ARGI_EVENT)
+#define ARGI_RETURN_OP                  ARGI_INVALID_OPCODE
+#define ARGI_REVISION_OP                ARG_NONE
+#define ARGI_SCOPE_OP                   ARGI_INVALID_OPCODE
+#define ARGI_SHIFT_LEFT_OP              ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_SHIFT_RIGHT_OP             ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_SIGNAL_OP                  ARGI_LIST1 (ARGI_EVENT)
+#define ARGI_SIZE_OF_OP                 ARGI_LIST1 (ARGI_DATAOBJECT)
+#define ARGI_SLEEP_OP                   ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_STALL_OP                   ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_STATICSTRING_OP            ARGI_INVALID_OPCODE
+#define ARGI_STORE_OP                   ARGI_LIST2 (ARGI_DATAREFOBJ, ARGI_TARGETREF)
+#define ARGI_STRING_OP                  ARGI_INVALID_OPCODE
+#define ARGI_SUBTRACT_OP                ARGI_LIST3 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF)
+#define ARGI_THERMAL_ZONE_OP            ARGI_INVALID_OPCODE
+#define ARGI_TIMER_OP                   ARG_NONE
+#define ARGI_TO_BCD_OP                  ARGI_LIST2 (ARGI_INTEGER,    ARGI_FIXED_TARGET)
+#define ARGI_TO_BUFFER_OP               ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
+#define ARGI_TO_DEC_STR_OP              ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
+#define ARGI_TO_HEX_STR_OP              ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
+#define ARGI_TO_INTEGER_OP              ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET)
+#define ARGI_TO_STRING_OP               ARGI_LIST3 (ARGI_BUFFER,     ARGI_INTEGER,       ARGI_FIXED_TARGET)
+#define ARGI_TYPE_OP                    ARGI_LIST1 (ARGI_ANYTYPE)
+#define ARGI_UNLOAD_OP                  ARGI_LIST1 (ARGI_DDBHANDLE)
+#define ARGI_VAR_PACKAGE_OP             ARGI_LIST1 (ARGI_INTEGER)
+#define ARGI_WAIT_OP                    ARGI_LIST2 (ARGI_EVENT,      ARGI_INTEGER)
+#define ARGI_WHILE_OP                   ARGI_INVALID_OPCODE
+#define ARGI_WORD_OP                    ARGI_INVALID_OPCODE
+#define ARGI_ZERO_OP                    ARG_NONE
+
+#endif                          /* __ACOPCODE_H__ */
diff --git a/include/acpi/acoutput.h b/include/acpi/acoutput.h
index 2fbe180fee6b..68d7edf0f697 100644
--- a/include/acpi/acoutput.h
+++ b/include/acpi/acoutput.h
@@ -73,12 +73,10 @@
 #define ACPI_ALL_COMPONENTS         0x00003FFF
 #define ACPI_COMPONENT_DEFAULT      (ACPI_ALL_COMPONENTS)
 
-
 /* Component IDs reserved for ACPI drivers */
 
 #define ACPI_ALL_DRIVERS            0xFFFF0000
 
-
 /*
  * Raw debug output levels, do not use these in the DEBUG_PRINT macros
  */
@@ -132,11 +130,10 @@
 
 #define ACPI_LV_VERBOSE             0xF0000000
 
-
 /*
  * Debug level macros that are used in the DEBUG_PRINT macros
  */
-#define ACPI_DEBUG_LEVEL(dl)        (u32) dl,__LINE__,&_debug_info
+#define ACPI_DEBUG_LEVEL(dl)        (u32) dl,ACPI_DEBUG_PARAMETERS
 
 /* Exception level -- used in the global "debug_level" */
 
@@ -147,7 +144,6 @@
 #define ACPI_DB_INFO                ACPI_DEBUG_LEVEL (ACPI_LV_INFO)
 #define ACPI_DB_ALL_EXCEPTIONS      ACPI_DEBUG_LEVEL (ACPI_LV_ALL_EXCEPTIONS)
 
-
 /* Trace level -- also used in the global "debug_level" */
 
 #define ACPI_DB_INIT_NAMES          ACPI_DEBUG_LEVEL (ACPI_LV_INIT_NAMES)
@@ -174,12 +170,10 @@
 
 #define ACPI_DB_ALL                 ACPI_DEBUG_LEVEL (ACPI_LV_ALL)
 
-
 /* Defaults for debug_level, debug and normal */
 
 #define ACPI_DEBUG_DEFAULT          (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR | ACPI_LV_DEBUG_OBJECT)
 #define ACPI_NORMAL_DEFAULT         (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR | ACPI_LV_DEBUG_OBJECT)
 #define ACPI_DEBUG_ALL              (ACPI_LV_AML_DISASSEMBLE | ACPI_LV_ALL_EXCEPTIONS | ACPI_LV_ALL)
 
-
-#endif /* __ACOUTPUT_H__ */
+#endif                          /* __ACOUTPUT_H__ */
diff --git a/include/acpi/acparser.h b/include/acpi/acparser.h
index c0395ef2b0d0..d352d40de1f3 100644
--- a/include/acpi/acparser.h
+++ b/include/acpi/acparser.h
@@ -41,18 +41,15 @@
  * POSSIBILITY OF SUCH DAMAGES.
  */
 
-
 #ifndef __ACPARSER_H__
 #define __ACPARSER_H__
 
-
 #define OP_HAS_RETURN_VALUE             1
 
 /* variable # arguments */
 
 #define ACPI_VAR_ARGS                   ACPI_UINT32_MAX
 
-
 #define ACPI_PARSE_DELETE_TREE          0x0001
 #define ACPI_PARSE_NO_TREE_DELETE       0x0000
 #define ACPI_PARSE_TREE_MASK            0x0001
@@ -63,18 +60,7 @@
 #define ACPI_PARSE_MODE_MASK            0x0030
 
 #define ACPI_PARSE_DEFERRED_OP          0x0100
-
-/* Parser external interfaces */
-
-acpi_status
-acpi_psx_load_table (
-        u8                              *pcode_addr,
-        u32                             pcode_length);
-
-acpi_status
-acpi_psx_execute (
-        struct acpi_parameter_info      *info);
-
+#define ACPI_PARSE_DISASSEMBLE          0x0200
 
 /******************************************************************************
  *
@@ -82,270 +68,165 @@ acpi_psx_execute (
  *
  *****************************************************************************/
 
+/*
+ * psxface - Parser external interfaces
+ */
+acpi_status acpi_ps_execute_method(struct acpi_parameter_info *info);
 
-/* psargs - Parse AML opcode arguments */
-
-u8 *
-acpi_ps_get_next_package_end (
-        struct acpi_parse_state         *parser_state);
-
-u32
-acpi_ps_get_next_package_length (
-        struct acpi_parse_state         *parser_state);
+/*
+ * psargs - Parse AML opcode arguments
+ */
+u8 *acpi_ps_get_next_package_end(struct acpi_parse_state *parser_state);
 
-char *
-acpi_ps_get_next_namestring (
-        struct acpi_parse_state         *parser_state);
+char *acpi_ps_get_next_namestring(struct acpi_parse_state *parser_state);
 
 void
-acpi_ps_get_next_simple_arg (
-        struct acpi_parse_state         *parser_state,
-        u32                             arg_type,
-        union acpi_parse_object         *arg);
+acpi_ps_get_next_simple_arg(struct acpi_parse_state *parser_state,
+                            u32 arg_type, union acpi_parse_object *arg);
 
 acpi_status
-acpi_ps_get_next_namepath (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_parse_state         *parser_state,
-        union acpi_parse_object         *arg,
-        u8                              method_call);
-
-union acpi_parse_object *
-acpi_ps_get_next_field (
-        struct acpi_parse_state         *parser_state);
+acpi_ps_get_next_namepath(struct acpi_walk_state *walk_state,
+                          struct acpi_parse_state *parser_state,
+                          union acpi_parse_object *arg, u8 method_call);
 
 acpi_status
-acpi_ps_get_next_arg (
-        struct acpi_walk_state          *walk_state,
-        struct acpi_parse_state         *parser_state,
-        u32                             arg_type,
-        union acpi_parse_object         **return_arg);
-
-
-/* psfind */
-
-union acpi_parse_object *
-acpi_ps_find_name (
-        union acpi_parse_object         *scope,
-        u32                             name,
-        u32                             opcode);
-
-union acpi_parse_object*
-acpi_ps_get_parent (
-        union acpi_parse_object         *op);
-
-
-/* psopcode - AML Opcode information */
-
-const struct acpi_opcode_info *
-acpi_ps_get_opcode_info (
-        u16                             opcode);
-
-char *
-acpi_ps_get_opcode_name (
-        u16                             opcode);
+acpi_ps_get_next_arg(struct acpi_walk_state *walk_state,
+                     struct acpi_parse_state *parser_state,
+                     u32 arg_type, union acpi_parse_object **return_arg);
 
+/*
+ * psfind
+ */
+union acpi_parse_object *acpi_ps_find_name(union acpi_parse_object *scope,
+                                           u32 name, u32 opcode);
 
-/* psparse - top level parsing routines */
+union acpi_parse_object *acpi_ps_get_parent(union acpi_parse_object *op);
 
-u32
-acpi_ps_get_opcode_size (
-        u32                             opcode);
+/*
+ * psopcode - AML Opcode information
+ */
+const struct acpi_opcode_info *acpi_ps_get_opcode_info(u16 opcode);
 
-void
-acpi_ps_complete_this_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op);
+char *acpi_ps_get_opcode_name(u16 opcode);
 
-acpi_status
-acpi_ps_next_parse_state (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        acpi_status                     callback_status);
+/*
+ * psparse - top level parsing routines
+ */
+acpi_status acpi_ps_parse_aml(struct acpi_walk_state *walk_state);
 
-acpi_status
-acpi_ps_find_object (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         **out_op);
+u32 acpi_ps_get_opcode_size(u32 opcode);
 
-void
-acpi_ps_delete_parse_tree (
-        union acpi_parse_object         *root);
+u16 acpi_ps_peek_opcode(struct acpi_parse_state *state);
 
 acpi_status
-acpi_ps_parse_loop (
-        struct acpi_walk_state          *walk_state);
+acpi_ps_complete_this_op(struct acpi_walk_state *walk_state,
+                         union acpi_parse_object *op);
 
 acpi_status
-acpi_ps_parse_aml (
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ps_parse_table (
-        u8                              *aml,
-        u32                             aml_size,
-        acpi_parse_downwards            descending_callback,
-        acpi_parse_upwards              ascending_callback,
-        union acpi_parse_object         **root_object);
-
-u16
-acpi_ps_peek_opcode (
-        struct acpi_parse_state         *state);
-
-
-/* psscope - Scope stack management routines */
+acpi_ps_next_parse_state(struct acpi_walk_state *walk_state,
+                         union acpi_parse_object *op,
+                         acpi_status callback_status);
 
+/*
+ * psloop - main parse loop
+ */
+acpi_status acpi_ps_parse_loop(struct acpi_walk_state *walk_state);
 
+/*
+ * psscope - Scope stack management routines
+ */
 acpi_status
-acpi_ps_init_scope (
-        struct acpi_parse_state         *parser_state,
-        union acpi_parse_object         *root);
+acpi_ps_init_scope(struct acpi_parse_state *parser_state,
+                   union acpi_parse_object *root);
 
-union acpi_parse_object *
-acpi_ps_get_parent_scope (
-        struct acpi_parse_state         *state);
+union acpi_parse_object *acpi_ps_get_parent_scope(struct acpi_parse_state
+                                                  *state);
 
-u8
-acpi_ps_has_completed_scope (
-        struct acpi_parse_state         *parser_state);
+u8 acpi_ps_has_completed_scope(struct acpi_parse_state *parser_state);
 
 void
-acpi_ps_pop_scope (
-        struct acpi_parse_state         *parser_state,
-        union acpi_parse_object         **op,
-        u32                             *arg_list,
-        u32                             *arg_count);
+acpi_ps_pop_scope(struct acpi_parse_state *parser_state,
+                  union acpi_parse_object **op,
+                  u32 * arg_list, u32 * arg_count);
 
 acpi_status
-acpi_ps_push_scope (
-        struct acpi_parse_state         *parser_state,
-        union acpi_parse_object         *op,
-        u32                             remaining_args,
-        u32                             arg_count);
+acpi_ps_push_scope(struct acpi_parse_state *parser_state,
+                   union acpi_parse_object *op,
+                   u32 remaining_args, u32 arg_count);
 
-void
-acpi_ps_cleanup_scope (
-        struct acpi_parse_state         *state);
-
-
-/* pstree - parse tree manipulation routines */
+void acpi_ps_cleanup_scope(struct acpi_parse_state *state);
 
+/*
+ * pstree - parse tree manipulation routines
+ */
 void
-acpi_ps_append_arg(
-        union acpi_parse_object         *op,
-        union acpi_parse_object         *arg);
+acpi_ps_append_arg(union acpi_parse_object *op, union acpi_parse_object *arg);
 
-union acpi_parse_object*
-acpi_ps_find (
-        union acpi_parse_object         *scope,
-        char                            *path,
-        u16                             opcode,
-        u32                             create);
+union acpi_parse_object *acpi_ps_find(union acpi_parse_object *scope,
+                                      char *path, u16 opcode, u32 create);
 
-union acpi_parse_object *
-acpi_ps_get_arg(
-        union acpi_parse_object         *op,
-        u32                              argn);
+union acpi_parse_object *acpi_ps_get_arg(union acpi_parse_object *op, u32 argn);
 
-#ifdef ACPI_FUTURE_USAGE
-union acpi_parse_object *
-acpi_ps_get_child (
-        union acpi_parse_object         *op);
-
-union acpi_parse_object *
-acpi_ps_get_depth_next (
-        union acpi_parse_object         *origin,
-        union acpi_parse_object         *op);
-#endif  /*  ACPI_FUTURE_USAGE  */
-
-
-/* pswalk - parse tree walk routines */
-
-acpi_status
-acpi_ps_walk_parsed_aml (
-        union acpi_parse_object         *start_op,
-        union acpi_parse_object         *end_op,
-        union acpi_operand_object       *mth_desc,
-        struct acpi_namespace_node      *start_node,
-        union acpi_operand_object       **params,
-        union acpi_operand_object       **caller_return_desc,
-        acpi_owner_id                   owner_id,
-        acpi_parse_downwards            descending_callback,
-        acpi_parse_upwards              ascending_callback);
+#ifdef  ACPI_FUTURE_USAGE
+union acpi_parse_object *acpi_ps_get_depth_next(union acpi_parse_object *origin,
+                                                union acpi_parse_object *op);
+#endif                          /* ACPI_FUTURE_USAGE */
 
+/*
+ * pswalk - parse tree walk routines
+ */
 acpi_status
-acpi_ps_get_next_walk_op (
-        struct acpi_walk_state          *walk_state,
-        union acpi_parse_object         *op,
-        acpi_parse_upwards              ascending_callback);
+acpi_ps_walk_parsed_aml(union acpi_parse_object *start_op,
+                        union acpi_parse_object *end_op,
+                        union acpi_operand_object *mth_desc,
+                        struct acpi_namespace_node *start_node,
+                        union acpi_operand_object **params,
+                        union acpi_operand_object **caller_return_desc,
+                        acpi_owner_id owner_id,
+                        acpi_parse_downwards descending_callback,
+                        acpi_parse_upwards ascending_callback);
 
 acpi_status
-acpi_ps_delete_completed_op (
-        struct acpi_walk_state          *walk_state);
+acpi_ps_get_next_walk_op(struct acpi_walk_state *walk_state,
+                         union acpi_parse_object *op,
+                         acpi_parse_upwards ascending_callback);
 
+acpi_status acpi_ps_delete_completed_op(struct acpi_walk_state *walk_state);
 
-/* psutils - parser utilities */
+void acpi_ps_delete_parse_tree(union acpi_parse_object *root);
 
-union acpi_parse_object *
-acpi_ps_create_scope_op (
-        void);
-
-void
-acpi_ps_init_op (
-        union acpi_parse_object         *op,
-        u16                             opcode);
-
-union acpi_parse_object *
-acpi_ps_alloc_op (
-        u16                             opcode);
-
-void
-acpi_ps_free_op (
-        union acpi_parse_object         *op);
+/*
+ * psutils - parser utilities
+ */
+union acpi_parse_object *acpi_ps_create_scope_op(void);
 
-#ifdef ACPI_ENABLE_OBJECT_CACHE
-void
-acpi_ps_delete_parse_cache (
-        void);
-#endif
+void acpi_ps_init_op(union acpi_parse_object *op, u16 opcode);
 
-u8
-acpi_ps_is_leading_char (
-        u32                             c);
+union acpi_parse_object *acpi_ps_alloc_op(u16 opcode);
 
-u8
-acpi_ps_is_prefix_char (
-        u32                             c);
+void acpi_ps_free_op(union acpi_parse_object *op);
 
-#ifdef ACPI_FUTURE_USAGE
-u32
-acpi_ps_get_name(
-        union acpi_parse_object         *op);
-#endif
+u8 acpi_ps_is_leading_char(u32 c);
 
-void
-acpi_ps_set_name(
-        union acpi_parse_object         *op,
-        u32                             name);
+u8 acpi_ps_is_prefix_char(u32 c);
 
+#ifdef  ACPI_FUTURE_USAGE
+u32 acpi_ps_get_name(union acpi_parse_object *op);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-/* psdump - display parser tree */
+void acpi_ps_set_name(union acpi_parse_object *op, u32 name);
 
+/*
+ * psdump - display parser tree
+ */
 u32
-acpi_ps_sprint_path (
-        char                            *buffer_start,
-        u32                             buffer_size,
-        union acpi_parse_object         *op);
+acpi_ps_sprint_path(char *buffer_start,
+                    u32 buffer_size, union acpi_parse_object *op);
 
 u32
-acpi_ps_sprint_op (
-        char                            *buffer_start,
-        u32                             buffer_size,
-        union acpi_parse_object         *op);
-
-void
-acpi_ps_show (
-        union acpi_parse_object         *op);
+acpi_ps_sprint_op(char *buffer_start,
+                  u32 buffer_size, union acpi_parse_object *op);
 
+void acpi_ps_show(union acpi_parse_object *op);
 
-#endif /* __ACPARSER_H__ */
+#endif                          /* __ACPARSER_H__ */
diff --git a/include/acpi/acpi.h b/include/acpi/acpi.h
index ad53252dd42d..ccf34f9dac64 100644
--- a/include/acpi/acpi.h
+++ b/include/acpi/acpi.h
@@ -49,21 +49,21 @@
  * We put them here because we don't want to duplicate them
  * in the rest of the source code again and again.
  */
-#include "acconfig.h"           /* Configuration constants */
-#include "platform/acenv.h"     /* Target environment specific items */
-#include "actypes.h"            /* Fundamental common data types */
-#include "acexcep.h"            /* ACPI exception codes */
-#include "acmacros.h"           /* C macros */
-#include "actbl.h"              /* ACPI table definitions */
-#include "aclocal.h"            /* Internal data types */
-#include "acoutput.h"           /* Error output and Debug macros */
-#include "acpiosxf.h"           /* Interfaces to the ACPI-to-OS layer*/
-#include "acpixf.h"             /* ACPI core subsystem external interfaces */
-#include "acobject.h"           /* ACPI internal object */
-#include "acstruct.h"           /* Common structures */
-#include "acglobal.h"           /* All global variables */
-#include "achware.h"            /* Hardware defines and interfaces */
-#include "acutils.h"            /* Utility interfaces */
+#include "acnames.h"            /* Global ACPI names and strings */
+#include "acconfig.h"           /* Configuration constants */
+#include "platform/acenv.h"     /* Target environment specific items */
+#include "actypes.h"            /* Fundamental common data types */
+#include "acexcep.h"            /* ACPI exception codes */
+#include "acmacros.h"           /* C macros */
+#include "actbl.h"              /* ACPI table definitions */
+#include "aclocal.h"            /* Internal data types */
+#include "acoutput.h"           /* Error output and Debug macros */
+#include "acpiosxf.h"           /* Interfaces to the ACPI-to-OS layer */
+#include "acpixf.h"             /* ACPI core subsystem external interfaces */
+#include "acobject.h"           /* ACPI internal object */
+#include "acstruct.h"           /* Common structures */
+#include "acglobal.h"           /* All global variables */
+#include "achware.h"            /* Hardware defines and interfaces */
+#include "acutils.h"            /* Utility interfaces */
 
-
-#endif /* __ACPI_H__ */
+#endif                          /* __ACPI_H__ */
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index c627bc408a6b..0b54e9a4a8a1 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -35,48 +35,41 @@
 /* TBD: Make dynamic */
 #define ACPI_MAX_HANDLES        10
 struct acpi_handle_list {
-        u32                     count;
-        acpi_handle             handles[ACPI_MAX_HANDLES];
+        u32 count;
+        acpi_handle handles[ACPI_MAX_HANDLES];
 };
 
-
 /* acpi_utils.h */
 acpi_status
-acpi_extract_package (
-        union acpi_object       *package,
-        struct acpi_buffer      *format,
-        struct acpi_buffer      *buffer);
+acpi_extract_package(union acpi_object *package,
+                     struct acpi_buffer *format, struct acpi_buffer *buffer);
 acpi_status
-acpi_evaluate_integer (
-        acpi_handle             handle,
-        acpi_string             pathname,
-        struct acpi_object_list *arguments,
-        unsigned long           *data);
+acpi_evaluate_integer(acpi_handle handle,
+                      acpi_string pathname,
+                      struct acpi_object_list *arguments, unsigned long *data);
 acpi_status
-acpi_evaluate_reference (
-        acpi_handle             handle,
-        acpi_string             pathname,
-        struct acpi_object_list *arguments,
-        struct acpi_handle_list *list);
-
+acpi_evaluate_reference(acpi_handle handle,
+                        acpi_string pathname,
+                        struct acpi_object_list *arguments,
+                        struct acpi_handle_list *list);
 
-#ifdef CONFIG_ACPI_BUS
+#ifdef CONFIG_ACPI
 
 #include <linux/proc_fs.h>
 
 #define ACPI_BUS_FILE_ROOT      "acpi"
-extern struct proc_dir_entry    *acpi_root_dir;
-extern FADT_DESCRIPTOR          acpi_fadt;
+extern struct proc_dir_entry *acpi_root_dir;
+extern FADT_DESCRIPTOR acpi_fadt;
 
 enum acpi_bus_removal_type {
-        ACPI_BUS_REMOVAL_NORMAL = 0,
+        ACPI_BUS_REMOVAL_NORMAL = 0,
         ACPI_BUS_REMOVAL_EJECT,
         ACPI_BUS_REMOVAL_SUPRISE,
         ACPI_BUS_REMOVAL_TYPE_COUNT
 };
 
 enum acpi_bus_device_type {
-        ACPI_BUS_TYPE_DEVICE    = 0,
+        ACPI_BUS_TYPE_DEVICE = 0,
         ACPI_BUS_TYPE_POWER,
         ACPI_BUS_TYPE_PROCESSOR,
         ACPI_BUS_TYPE_THERMAL,
@@ -89,46 +82,60 @@ enum acpi_bus_device_type {
 struct acpi_driver;
 struct acpi_device;
 
-
 /*
  * ACPI Driver
  * -----------
  */
 
-typedef int (*acpi_op_add)      (struct acpi_device *device);
-typedef int (*acpi_op_remove)   (struct acpi_device *device, int type);
-typedef int (*acpi_op_lock)     (struct acpi_device *device, int type);
-typedef int (*acpi_op_start)    (struct acpi_device *device);
-typedef int (*acpi_op_stop)     (struct acpi_device *device, int type);
-typedef int (*acpi_op_suspend)  (struct acpi_device *device, int state);
-typedef int (*acpi_op_resume)   (struct acpi_device *device, int state);
-typedef int (*acpi_op_scan)     (struct acpi_device *device);
-typedef int (*acpi_op_bind)     (struct acpi_device *device);
-typedef int (*acpi_op_unbind)   (struct acpi_device *device);
-typedef int (*acpi_op_match)    (struct acpi_device *device,
-                                 struct acpi_driver *driver);
+typedef int (*acpi_op_add) (struct acpi_device * device);
+typedef int (*acpi_op_remove) (struct acpi_device * device, int type);
+typedef int (*acpi_op_lock) (struct acpi_device * device, int type);
+typedef int (*acpi_op_start) (struct acpi_device * device);
+typedef int (*acpi_op_stop) (struct acpi_device * device, int type);
+typedef int (*acpi_op_suspend) (struct acpi_device * device, int state);
+typedef int (*acpi_op_resume) (struct acpi_device * device, int state);
+typedef int (*acpi_op_scan) (struct acpi_device * device);
+typedef int (*acpi_op_bind) (struct acpi_device * device);
+typedef int (*acpi_op_unbind) (struct acpi_device * device);
+typedef int (*acpi_op_match) (struct acpi_device * device,
+                              struct acpi_driver * driver);
+
+struct acpi_bus_ops {
+        u32 acpi_op_add:1;
+        u32 acpi_op_remove:1;
+        u32 acpi_op_lock:1;
+        u32 acpi_op_start:1;
+        u32 acpi_op_stop:1;
+        u32 acpi_op_suspend:1;
+        u32 acpi_op_resume:1;
+        u32 acpi_op_scan:1;
+        u32 acpi_op_bind:1;
+        u32 acpi_op_unbind:1;
+        u32 acpi_op_match:1;
+        u32 reserved:21;
+};
 
 struct acpi_device_ops {
-        acpi_op_add             add;
-        acpi_op_remove          remove;
-        acpi_op_lock            lock;
-        acpi_op_start           start;
-        acpi_op_stop            stop;
-        acpi_op_suspend         suspend;
-        acpi_op_resume          resume;
-        acpi_op_scan            scan;
-        acpi_op_bind            bind;
-        acpi_op_unbind          unbind;
-        acpi_op_match           match;
+        acpi_op_add add;
+        acpi_op_remove remove;
+        acpi_op_lock lock;
+        acpi_op_start start;
+        acpi_op_stop stop;
+        acpi_op_suspend suspend;
+        acpi_op_resume resume;
+        acpi_op_scan scan;
+        acpi_op_bind bind;
+        acpi_op_unbind unbind;
+        acpi_op_match match;
 };
 
 struct acpi_driver {
-        struct list_head        node;
-        char                    name[80];
-        char                    class[80];
-        atomic_t                references;
-        char                    *ids;           /* Supported Hardware IDs */
-        struct acpi_device_ops  ops;
+        struct list_head node;
+        char name[80];
+        char class[80];
+        atomic_t references;
+        char *ids;              /* Supported Hardware IDs */
+        struct acpi_device_ops ops;
 };
 
 /*
@@ -139,60 +146,57 @@ struct acpi_driver {
 /* Status (_STA) */
 
 struct acpi_device_status {
-        u32                     present:1;
-        u32                     enabled:1;
-        u32                     show_in_ui:1;
-        u32                     functional:1;
-        u32                     battery_present:1;
-        u32                     reserved:27;
+        u32 present:1;
+        u32 enabled:1;
+        u32 show_in_ui:1;
+        u32 functional:1;
+        u32 battery_present:1;
+        u32 reserved:27;
 };
 
-
 /* Flags */
 
 struct acpi_device_flags {
-        u32                     dynamic_status:1;
-        u32                     hardware_id:1;
-        u32                     compatible_ids:1;
-        u32                     bus_address:1;
-        u32                     unique_id:1;
-        u32                     removable:1;
-        u32                     ejectable:1;
-        u32                     lockable:1;
-        u32                     suprise_removal_ok:1;
-        u32                     power_manageable:1;
-        u32                     performance_manageable:1;
-        u32                     wake_capable:1; /* Wakeup(_PRW) supported? */
-        u32                     reserved:20;
+        u32 dynamic_status:1;
+        u32 hardware_id:1;
+        u32 compatible_ids:1;
+        u32 bus_address:1;
+        u32 unique_id:1;
+        u32 removable:1;
+        u32 ejectable:1;
+        u32 lockable:1;
+        u32 suprise_removal_ok:1;
+        u32 power_manageable:1;
+        u32 performance_manageable:1;
+        u32 wake_capable:1;     /* Wakeup(_PRW) supported? */
+        u32 reserved:20;
 };
 
-
 /* File System */
 
 struct acpi_device_dir {
-        struct proc_dir_entry   *entry;
+        struct proc_dir_entry *entry;
 };
 
 #define acpi_device_dir(d)      ((d)->dir.entry)
 
-
 /* Plug and Play */
 
-typedef char                    acpi_bus_id[5];
-typedef unsigned long           acpi_bus_address;
-typedef char                    acpi_hardware_id[9];
-typedef char                    acpi_unique_id[9];
-typedef char                    acpi_device_name[40];
-typedef char                    acpi_device_class[20];
+typedef char acpi_bus_id[5];
+typedef unsigned long acpi_bus_address;
+typedef char acpi_hardware_id[9];
+typedef char acpi_unique_id[9];
+typedef char acpi_device_name[40];
+typedef char acpi_device_class[20];
 
 struct acpi_device_pnp {
-        acpi_bus_id             bus_id;                        /* Object name */
-        acpi_bus_address        bus_address;                          /* _ADR */
-        acpi_hardware_id        hardware_id;                          /* _HID */
-        struct acpi_compatible_id_list *cid_list;                    /* _CIDs */
-        acpi_unique_id          unique_id;                            /* _UID */
-        acpi_device_name        device_name;             /* Driver-determined */
-        acpi_device_class       device_class;            /*        "          */
+        acpi_bus_id bus_id;     /* Object name */
+        acpi_bus_address bus_address;   /* _ADR */
+        acpi_hardware_id hardware_id;   /* _HID */
+        struct acpi_compatible_id_list *cid_list;       /* _CIDs */
+        acpi_unique_id unique_id;       /* _UID */
+        acpi_device_name device_name;   /* Driver-determined */
+        acpi_device_class device_class; /*        "          */
 };
 
 #define acpi_device_bid(d)      ((d)->pnp.bus_id)
@@ -202,114 +206,111 @@ struct acpi_device_pnp {
 #define acpi_device_name(d)     ((d)->pnp.device_name)
 #define acpi_device_class(d)    ((d)->pnp.device_class)
 
-
 /* Power Management */
 
 struct acpi_device_power_flags {
-        u32                     explicit_get:1;              /* _PSC present? */
-        u32                     power_resources:1;         /* Power resources */
-        u32                     inrush_current:1;         /* Serialize Dx->D0 */
-        u32                     power_removed:1;           /* Optimize Dx->D0 */
-        u32                     reserved:28;
+        u32 explicit_get:1;     /* _PSC present? */
+        u32 power_resources:1;  /* Power resources */
+        u32 inrush_current:1;   /* Serialize Dx->D0 */
+        u32 power_removed:1;    /* Optimize Dx->D0 */
+        u32 reserved:28;
 };
 
 struct acpi_device_power_state {
         struct {
-                u8                      valid:1;        
-                u8                      explicit_set:1;      /* _PSx present? */
-                u8                      reserved:6;
-        }                       flags;
-        int                     power;            /* % Power (compared to D0) */
-        int                     latency;        /* Dx->D0 time (microseconds) */
-        struct acpi_handle_list resources;      /* Power resources referenced */
+                u8 valid:1;
+                u8 explicit_set:1;      /* _PSx present? */
+                u8 reserved:6;
+        } flags;
+        int power;              /* % Power (compared to D0) */
+        int latency;            /* Dx->D0 time (microseconds) */
+        struct acpi_handle_list resources;      /* Power resources referenced */
 };
 
 struct acpi_device_power {
-        int                     state;                       /* Current state */
+        int state;              /* Current state */
         struct acpi_device_power_flags flags;
-        struct acpi_device_power_state states[4];     /* Power states (D0-D3) */
+        struct acpi_device_power_state states[4];       /* Power states (D0-D3) */
 };
 
-
 /* Performance Management */
 
 struct acpi_device_perf_flags {
-        u8                      reserved:8;
+        u8 reserved:8;
 };
 
 struct acpi_device_perf_state {
         struct {
-                u8                      valid:1;        
-                u8                      reserved:7;
-        }                       flags;
-        u8                      power;            /* % Power (compared to P0) */
-        u8                      performance;      /* % Performance (    "   ) */
-        int                     latency;        /* Px->P0 time (microseconds) */
+                u8 valid:1;
+                u8 reserved:7;
+        } flags;
+        u8 power;               /* % Power (compared to P0) */
+        u8 performance;         /* % Performance (    "   ) */
+        int latency;            /* Px->P0 time (microseconds) */
 };
 
 struct acpi_device_perf {
-        int                     state;
+        int state;
         struct acpi_device_perf_flags flags;
-        int                     state_count;
+        int state_count;
         struct acpi_device_perf_state *states;
 };
 
 /* Wakeup Management */
 struct acpi_device_wakeup_flags {
-        u8      valid:1; /* Can successfully enable wakeup? */
-        u8      run_wake:1; /* Run-Wake GPE devices */
+        u8 valid:1;             /* Can successfully enable wakeup? */
+        u8 run_wake:1;          /* Run-Wake GPE devices */
 };
 
 struct acpi_device_wakeup_state {
-        u8      enabled:1;
-        u8      active:1;
+        u8 enabled:1;
+        u8 active:1;
 };
 
 struct acpi_device_wakeup {
-        acpi_handle             gpe_device;
-        acpi_integer            gpe_number;;
-        acpi_integer            sleep_state;
-        struct acpi_handle_list resources;
-        struct acpi_device_wakeup_state state;
-        struct acpi_device_wakeup_flags flags;
+        acpi_handle gpe_device;
+        acpi_integer gpe_number;;
+        acpi_integer sleep_state;
+        struct acpi_handle_list resources;
+        struct acpi_device_wakeup_state state;
+        struct acpi_device_wakeup_flags flags;
 };
 
 /* Device */
 
 struct acpi_device {
-        acpi_handle             handle;
-        struct acpi_device      *parent;
-        struct list_head        children;
-        struct list_head        node;
-        struct list_head        wakeup_list;
-        struct list_head        g_list;
+        acpi_handle handle;
+        struct acpi_device *parent;
+        struct list_head children;
+        struct list_head node;
+        struct list_head wakeup_list;
+        struct list_head g_list;
         struct acpi_device_status status;
         struct acpi_device_flags flags;
-        struct acpi_device_pnp  pnp;
+        struct acpi_device_pnp pnp;
         struct acpi_device_power power;
         struct acpi_device_wakeup wakeup;
-        struct acpi_device_perf performance;
-        struct acpi_device_dir  dir;
-        struct acpi_device_ops  ops;
-        struct acpi_driver      *driver;
-        void                    *driver_data;
-        struct kobject          kobj;
+        struct acpi_device_perf performance;
+        struct acpi_device_dir dir;
+        struct acpi_device_ops ops;
+        struct acpi_driver *driver;
+        void *driver_data;
+        struct kobject kobj;
 };
 
 #define acpi_driver_data(d)     ((d)->driver_data)
 
-
 /*
  * Events
  * ------
  */
 
 struct acpi_bus_event {
-        struct list_head        node;
-        acpi_device_class       device_class;
-        acpi_bus_id             bus_id;
-        u32                     type;
-        u32                     data;
+        struct list_head node;
+        acpi_device_class device_class;
+        acpi_bus_id bus_id;
+        u32 type;
+        u32 data;
 };
 
 extern struct subsystem acpi_subsys;
@@ -320,22 +321,41 @@ extern struct subsystem acpi_subsys;
 
 int acpi_bus_get_device(acpi_handle handle, struct acpi_device **device);
 void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context);
-int acpi_bus_get_status (struct acpi_device *device);
-int acpi_bus_get_power (acpi_handle handle, int *state);
-int acpi_bus_set_power (acpi_handle handle, int state);
-int acpi_bus_generate_event (struct acpi_device *device, u8 type, int data);
-int acpi_bus_receive_event (struct acpi_bus_event *event);
-int acpi_bus_register_driver (struct acpi_driver *driver);
-int acpi_bus_unregister_driver (struct acpi_driver *driver);
-int acpi_bus_scan (struct acpi_device *start);
-int acpi_bus_add (struct acpi_device **child, struct acpi_device *parent,
-                acpi_handle handle, int type);
-
-
-int acpi_match_ids (struct acpi_device  *device, char   *ids);
+int acpi_bus_get_status(struct acpi_device *device);
+int acpi_bus_get_power(acpi_handle handle, int *state);
+int acpi_bus_set_power(acpi_handle handle, int state);
+int acpi_bus_generate_event(struct acpi_device *device, u8 type, int data);
+int acpi_bus_receive_event(struct acpi_bus_event *event);
+int acpi_bus_register_driver(struct acpi_driver *driver);
+int acpi_bus_unregister_driver(struct acpi_driver *driver);
+int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent,
+                 acpi_handle handle, int type);
+int acpi_bus_start(struct acpi_device *device);
+
+int acpi_match_ids(struct acpi_device *device, char *ids);
 int acpi_create_dir(struct acpi_device *);
 void acpi_remove_dir(struct acpi_device *);
 
-#endif /*CONFIG_ACPI_BUS*/
+/*
+ * Bind physical devices with ACPI devices
+ */
+#include <linux/device.h>
+struct acpi_bus_type {
+        struct list_head list;
+        struct bus_type *bus;
+        /* For general devices under the bus */
+        int (*find_device) (struct device *, acpi_handle *);
+        /* For bridges, such as PCI root bridge, IDE controller */
+        int (*find_bridge) (struct device *, acpi_handle *);
+};
+int register_acpi_bus_type(struct acpi_bus_type *);
+int unregister_acpi_bus_type(struct acpi_bus_type *);
+struct device *acpi_get_physical_device(acpi_handle);
+/* helper */
+acpi_handle acpi_get_child(acpi_handle, acpi_integer);
+acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int);
+#define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->firmware_data))
+
+#endif /* CONFIG_ACPI */
 
 #endif /*__ACPI_BUS_H__*/
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index c62e92ec43b2..c1b4e1f882e4 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -29,7 +29,6 @@
 #include <linux/acpi.h>
 #include <acpi/acpi_bus.h>
 
-
 #define ACPI_MAX_STRING                 80
 
 #define ACPI_BUS_COMPONENT              0x00010000
@@ -44,58 +43,55 @@
 #define ACPI_BUTTON_HID_POWERF          "ACPI_FPB"
 #define ACPI_BUTTON_HID_SLEEPF          "ACPI_FSB"
 
-
 /* --------------------------------------------------------------------------
                                        PCI
    -------------------------------------------------------------------------- */
 
-#ifdef CONFIG_ACPI_PCI
-
 #define ACPI_PCI_COMPONENT              0x00400000
 
 /* ACPI PCI Interrupt Link (pci_link.c) */
 
-int acpi_irq_penalty_init (void);
-int acpi_pci_link_get_irq (acpi_handle handle, int index, int *edge_level,
-        int *active_high_low, char **name);
+int acpi_irq_penalty_init(void);
+int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *edge_level,
+                               int *active_high_low, char **name);
+int acpi_pci_link_free_irq(acpi_handle handle);
 
 /* ACPI PCI Interrupt Routing (pci_irq.c) */
 
-int acpi_pci_irq_add_prt (acpi_handle handle, int segment, int bus);
-void acpi_pci_irq_del_prt (int segment, int bus);
+int acpi_pci_irq_add_prt(acpi_handle handle, int segment, int bus);
+void acpi_pci_irq_del_prt(int segment, int bus);
 
 /* ACPI PCI Device Binding (pci_bind.c) */
 
 struct pci_bus;
 
-int acpi_pci_bind (struct acpi_device *device);
-int acpi_pci_unbind (struct acpi_device *device);
-int acpi_pci_bind_root (struct acpi_device *device, struct acpi_pci_id *id, struct pci_bus *bus);
+acpi_status acpi_get_pci_id(acpi_handle handle, struct acpi_pci_id *id);
+int acpi_pci_bind(struct acpi_device *device);
+int acpi_pci_unbind(struct acpi_device *device);
+int acpi_pci_bind_root(struct acpi_device *device, struct acpi_pci_id *id,
+                       struct pci_bus *bus);
 
 /* Arch-defined function to add a bus to the system */
 
-struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain, int bus);
-
-#endif /*CONFIG_ACPI_PCI*/
-
+struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain,
+                                   int bus);
 
 /* --------------------------------------------------------------------------
                                   Power Resource
    -------------------------------------------------------------------------- */
 
 #ifdef CONFIG_ACPI_POWER
-int acpi_enable_wakeup_device_power (struct acpi_device *dev);
-int acpi_disable_wakeup_device_power (struct acpi_device *dev);
-int acpi_power_get_inferred_state (struct acpi_device *device);
-int acpi_power_transition (struct acpi_device *device, int state);
+int acpi_enable_wakeup_device_power(struct acpi_device *dev);
+int acpi_disable_wakeup_device_power(struct acpi_device *dev);
+int acpi_power_get_inferred_state(struct acpi_device *device);
+int acpi_power_transition(struct acpi_device *device, int state);
 #endif
 
-
 /* --------------------------------------------------------------------------
                                   Embedded Controller
    -------------------------------------------------------------------------- */
 #ifdef CONFIG_ACPI_EC
-int acpi_ec_ecdt_probe (void);
+int acpi_ec_ecdt_probe(void);
 #endif
 
 /* --------------------------------------------------------------------------
@@ -108,5 +104,10 @@ int acpi_ec_ecdt_probe (void);
 
 int acpi_processor_set_thermal_limit(acpi_handle handle, int type);
 
+/* --------------------------------------------------------------------------
+                                    Hot Keys
+   -------------------------------------------------------------------------- */
+
+extern int acpi_specific_hotkey_enabled;
 
 #endif /*__ACPI_DRIVERS_H__*/
diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h
index 857c8072eb1e..98e0b8cd14ed 100644
--- a/include/acpi/acpiosxf.h
+++ b/include/acpi/acpiosxf.h
@@ -7,7 +7,6 @@
  *
  *****************************************************************************/
 
-
 /*
  * Copyright (C) 2000 - 2005, R. Byron Moore
  * All rights reserved.
@@ -51,7 +50,6 @@
 #include "platform/acenv.h"
 #include "actypes.h"
 
-
 /* Priorities for acpi_os_queue_for_execution */
 
 #define OSD_PRIORITY_GPE            1
@@ -62,328 +60,206 @@
 #define ACPI_NO_UNIT_LIMIT          ((u32) -1)
 #define ACPI_MUTEX_SEM              1
 
-
 /* Functions for acpi_os_signal */
 
 #define ACPI_SIGNAL_FATAL           0
 #define ACPI_SIGNAL_BREAKPOINT      1
 
-struct acpi_signal_fatal_info
-{
-        u32                             type;
-        u32                             code;
-        u32                             argument;
+struct acpi_signal_fatal_info {
+        u32 type;
+        u32 code;
+        u32 argument;
 };
 
-
 /*
  * OSL Initialization and shutdown primitives
  */
+acpi_status acpi_os_initialize(void);
 
-acpi_status
-acpi_os_initialize (
-        void);
-
-acpi_status
-acpi_os_terminate (
-        void);
-
+acpi_status acpi_os_terminate(void);
 
 /*
  * ACPI Table interfaces
  */
+acpi_status acpi_os_get_root_pointer(u32 flags, struct acpi_pointer *address);
 
 acpi_status
-acpi_os_get_root_pointer (
-        u32                             flags,
-        struct acpi_pointer             *address);
+acpi_os_predefined_override(const struct acpi_predefined_names *init_val,
+                            acpi_string * new_val);
 
 acpi_status
-acpi_os_predefined_override (
-        const struct acpi_predefined_names *init_val,
-        acpi_string                         *new_val);
-
-acpi_status
-acpi_os_table_override (
-        struct acpi_table_header        *existing_table,
-        struct acpi_table_header        **new_table);
-
+acpi_os_table_override(struct acpi_table_header *existing_table,
+                       struct acpi_table_header **new_table);
 
 /*
  * Synchronization primitives
  */
-
 acpi_status
-acpi_os_create_semaphore (
-        u32                             max_units,
-        u32                             initial_units,
-        acpi_handle                     *out_handle);
+acpi_os_create_semaphore(u32 max_units,
+                         u32 initial_units, acpi_handle * out_handle);
 
-acpi_status
-acpi_os_delete_semaphore (
-        acpi_handle                     handle);
+acpi_status acpi_os_delete_semaphore(acpi_handle handle);
 
-acpi_status
-acpi_os_wait_semaphore (
-        acpi_handle                     handle,
-        u32                             units,
-        u16                             timeout);
+acpi_status acpi_os_wait_semaphore(acpi_handle handle, u32 units, u16 timeout);
 
-acpi_status
-acpi_os_signal_semaphore (
-        acpi_handle                     handle,
-        u32                             units);
+acpi_status acpi_os_signal_semaphore(acpi_handle handle, u32 units);
 
-acpi_status
-acpi_os_create_lock (
-        acpi_handle                     *out_handle);
+acpi_status acpi_os_create_lock(acpi_handle * out_handle);
 
-void
-acpi_os_delete_lock (
-        acpi_handle                     handle);
-
-void
-acpi_os_acquire_lock (
-        acpi_handle                     handle,
-        u32                             flags);
+void acpi_os_delete_lock(acpi_handle handle);
 
-void
-acpi_os_release_lock (
-        acpi_handle                     handle,
-        u32                             flags);
+unsigned long acpi_os_acquire_lock(acpi_handle handle);
 
+void acpi_os_release_lock(acpi_handle handle, unsigned long flags);
 
 /*
  * Memory allocation and mapping
  */
+void *acpi_os_allocate(acpi_size size);
 
-void *
-acpi_os_allocate (
-        acpi_size                       size);
-
-void
-acpi_os_free (
-        void *                          memory);
+void acpi_os_free(void *memory);
 
 acpi_status
-acpi_os_map_memory (
-        acpi_physical_address           physical_address,
-        acpi_size                       size,
-        void __iomem                  **logical_address);
+acpi_os_map_memory(acpi_physical_address physical_address,
+                   acpi_size size, void __iomem ** logical_address);
 
-void
-acpi_os_unmap_memory (
-        void __iomem                  *logical_address,
-        acpi_size                       size);
+void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_os_get_physical_address (
-        void                            *logical_address,
-        acpi_physical_address           *physical_address);
+acpi_os_get_physical_address(void *logical_address,
+                             acpi_physical_address * physical_address);
 #endif
 
+/*
+ * Memory/Object Cache
+ */
+acpi_status
+acpi_os_create_cache(char *cache_name,
+                     u16 object_size,
+                     u16 max_depth, acpi_cache_t ** return_cache);
+
+acpi_status acpi_os_delete_cache(acpi_cache_t * cache);
+
+acpi_status acpi_os_purge_cache(acpi_cache_t * cache);
+
+void *acpi_os_acquire_object(acpi_cache_t * cache);
+
+acpi_status acpi_os_release_object(acpi_cache_t * cache, void *object);
 
 /*
  * Interrupt handlers
  */
-
 acpi_status
-acpi_os_install_interrupt_handler (
-        u32                             gsi,
-        acpi_osd_handler                service_routine,
-        void                            *context);
+acpi_os_install_interrupt_handler(u32 gsi,
+                                  acpi_osd_handler service_routine,
+                                  void *context);
 
 acpi_status
-acpi_os_remove_interrupt_handler (
-        u32                             gsi,
-        acpi_osd_handler                service_routine);
-
+acpi_os_remove_interrupt_handler(u32 gsi, acpi_osd_handler service_routine);
 
 /*
  * Threads and Scheduling
  */
-
-u32
-acpi_os_get_thread_id (
-        void);
+u32 acpi_os_get_thread_id(void);
 
 acpi_status
-acpi_os_queue_for_execution (
-        u32                             priority,
-        acpi_osd_exec_callback          function,
-        void                            *context);
-
-void
-acpi_os_wait_events_complete(
-        void * context);
+acpi_os_queue_for_execution(u32 priority,
+                            acpi_osd_exec_callback function, void *context);
 
-void
-acpi_os_wait_events_complete (
-        void                            *context);
+void acpi_os_wait_events_complete(void *context);
 
-void
-acpi_os_sleep (
-        acpi_integer                    milliseconds);
+void acpi_os_wait_events_complete(void *context);
 
-void
-acpi_os_stall (
-        u32                             microseconds);
+void acpi_os_sleep(acpi_integer milliseconds);
 
+void acpi_os_stall(u32 microseconds);
 
 /*
  * Platform and hardware-independent I/O interfaces
  */
+acpi_status acpi_os_read_port(acpi_io_address address, u32 * value, u32 width);
 
-acpi_status
-acpi_os_read_port (
-        acpi_io_address                 address,
-        u32                             *value,
-        u32                             width);
-
-acpi_status
-acpi_os_write_port (
-        acpi_io_address                 address,
-        u32                             value,
-        u32                             width);
-
+acpi_status acpi_os_write_port(acpi_io_address address, u32 value, u32 width);
 
 /*
  * Platform and hardware-independent physical memory interfaces
  */
-
 acpi_status
-acpi_os_read_memory (
-        acpi_physical_address           address,
-        u32                             *value,
-        u32                             width);
+acpi_os_read_memory(acpi_physical_address address, u32 * value, u32 width);
 
 acpi_status
-acpi_os_write_memory (
-        acpi_physical_address           address,
-        u32                             value,
-        u32                             width);
-
+acpi_os_write_memory(acpi_physical_address address, u32 value, u32 width);
 
 /*
  * Platform and hardware-independent PCI configuration space access
  * Note: Can't use "Register" as a parameter, changed to "Reg" --
  * certain compilers complain.
  */
-
 acpi_status
-acpi_os_read_pci_configuration (
-        struct acpi_pci_id              *pci_id,
-        u32                             reg,
-        void                            *value,
-        u32                             width);
+acpi_os_read_pci_configuration(struct acpi_pci_id *pci_id,
+                               u32 reg, void *value, u32 width);
 
 acpi_status
-acpi_os_write_pci_configuration (
-        struct acpi_pci_id              *pci_id,
-        u32                             reg,
-        acpi_integer                    value,
-        u32                             width);
+acpi_os_write_pci_configuration(struct acpi_pci_id *pci_id,
+                                u32 reg, acpi_integer value, u32 width);
 
 /*
  * Interim function needed for PCI IRQ routing
  */
-
 void
-acpi_os_derive_pci_id(
-        acpi_handle                     rhandle,
-        acpi_handle                     chandle,
-        struct acpi_pci_id              **pci_id);
+acpi_os_derive_pci_id(acpi_handle rhandle,
+                      acpi_handle chandle, struct acpi_pci_id **pci_id);
 
 /*
  * Miscellaneous
  */
-
-u8
-acpi_os_readable (
-        void                            *pointer,
-        acpi_size                       length);
+u8 acpi_os_readable(void *pointer, acpi_size length);
 
 #ifdef ACPI_FUTURE_USAGE
-u8
-acpi_os_writable (
-        void                            *pointer,
-        acpi_size                       length);
+u8 acpi_os_writable(void *pointer, acpi_size length);
 #endif
 
-u64
-acpi_os_get_timer (
-        void);
+u64 acpi_os_get_timer(void);
 
-acpi_status
-acpi_os_signal (
-        u32                             function,
-        void                            *info);
+acpi_status acpi_os_signal(u32 function, void *info);
 
 /*
  * Debug print routines
  */
+void ACPI_INTERNAL_VAR_XFACE acpi_os_printf(const char *format, ...);
 
-void ACPI_INTERNAL_VAR_XFACE
-acpi_os_printf (
-        const char                      *format,
-        ...);
-
-void
-acpi_os_vprintf (
-        const char                      *format,
-        va_list                 args);
-
-void
-acpi_os_redirect_output (
-        void                            *destination);
+void acpi_os_vprintf(const char *format, va_list args);
 
+void acpi_os_redirect_output(void *destination);
 
+#ifdef ACPI_FUTURE_USAGE
 /*
  * Debug input
  */
-
-#ifdef ACPI_FUTURE_USAGE
-u32
-acpi_os_get_line (
-        char                            *buffer);
+u32 acpi_os_get_line(char *buffer);
 #endif
 
-
 /*
  * Directory manipulation
  */
-
-void *
-acpi_os_open_directory (
-        char                            *pathname,
-        char                            *wildcard_spec,
-        char                            requested_file_type);
+void *acpi_os_open_directory(char *pathname,
+                             char *wildcard_spec, char requested_file_type);
 
 /* requeste_file_type values */
 
 #define REQUEST_FILE_ONLY                   0
 #define REQUEST_DIR_ONLY                    1
 
+char *acpi_os_get_next_filename(void *dir_handle);
 
-char *
-acpi_os_get_next_filename (
-        void                            *dir_handle);
-
-void
-acpi_os_close_directory (
-        void                            *dir_handle);
+void acpi_os_close_directory(void *dir_handle);
 
 /*
  * Debug
  */
-
 void
-acpi_os_dbg_assert(
-        void                            *failed_assertion,
-        void                            *file_name,
-        u32                             line_number,
-        char                            *message);
-
+acpi_os_dbg_assert(void *failed_assertion,
+                   void *file_name, u32 line_number, char *message);
 
-#endif /* __ACPIOSXF_H__ */
+#endif                          /* __ACPIOSXF_H__ */
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index 00d78b79652e..2a9dbc13b0f2 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -42,456 +42,283 @@
  * POSSIBILITY OF SUCH DAMAGES.
  */
 
-
 #ifndef __ACXFACE_H__
 #define __ACXFACE_H__
 
 #include "actypes.h"
 #include "actbl.h"
 
-
- /*
+/*
  * Global interfaces
  */
+acpi_status acpi_initialize_subsystem(void);
 
-acpi_status
-acpi_initialize_subsystem (
-        void);
+acpi_status acpi_enable_subsystem(u32 flags);
 
-acpi_status
-acpi_enable_subsystem (
-        u32                             flags);
+acpi_status acpi_initialize_objects(u32 flags);
 
-acpi_status
-acpi_initialize_objects (
-        u32                             flags);
-
-acpi_status
-acpi_terminate (
-        void);
+acpi_status acpi_terminate(void);
 
 #ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_subsystem_status (
-        void);
+acpi_status acpi_subsystem_status(void);
 #endif
 
-acpi_status
-acpi_enable (
-        void);
+acpi_status acpi_enable(void);
 
-acpi_status
-acpi_disable (
-        void);
+acpi_status acpi_disable(void);
 
 #ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_get_system_info (
-        struct acpi_buffer              *ret_buffer);
+acpi_status acpi_get_system_info(struct acpi_buffer *ret_buffer);
 #endif
 
-const char *
-acpi_format_exception (
-        acpi_status                     exception);
+const char *acpi_format_exception(acpi_status exception);
 
-acpi_status
-acpi_purge_cached_objects (
-        void);
+acpi_status acpi_purge_cached_objects(void);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_install_initialization_handler (
-        acpi_init_handler               handler,
-        u32                             function);
+acpi_install_initialization_handler(acpi_init_handler handler, u32 function);
 #endif
 
 /*
- * ACPI Memory manager
+ * ACPI Memory managment
  */
+void *acpi_allocate(u32 size);
 
-void *
-acpi_allocate (
-        u32                             size);
-
-void *
-acpi_callocate (
-        u32                             size);
-
-void
-acpi_free (
-        void                            *address);
+void *acpi_callocate(u32 size);
 
+void acpi_free(void *address);
 
 /*
  * ACPI table manipulation interfaces
  */
-
 acpi_status
-acpi_find_root_pointer (
-        u32                             flags,
-        struct acpi_pointer             *rsdp_address);
+acpi_find_root_pointer(u32 flags, struct acpi_pointer *rsdp_address);
 
-acpi_status
-acpi_load_tables (
-        void);
+acpi_status acpi_load_tables(void);
 
 #ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_load_table (
-        struct acpi_table_header        *table_ptr);
+acpi_status acpi_load_table(struct acpi_table_header *table_ptr);
 
-acpi_status
-acpi_unload_table (
-        acpi_table_type                 table_type);
+acpi_status acpi_unload_table(acpi_table_type table_type);
 
 acpi_status
-acpi_get_table_header (
-        acpi_table_type                 table_type,
-        u32                             instance,
-        struct acpi_table_header        *out_table_header);
-#endif  /*  ACPI_FUTURE_USAGE  */
+acpi_get_table_header(acpi_table_type table_type,
+                      u32 instance, struct acpi_table_header *out_table_header);
+#endif                          /*  ACPI_FUTURE_USAGE  */
 
 acpi_status
-acpi_get_table (
-        acpi_table_type                 table_type,
-        u32                             instance,
-        struct acpi_buffer              *ret_buffer);
+acpi_get_table(acpi_table_type table_type,
+               u32 instance, struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_get_firmware_table (
-        acpi_string                     signature,
-        u32                             instance,
-        u32                             flags,
-        struct acpi_table_header        **table_pointer);
-
+acpi_get_firmware_table(acpi_string signature,
+                        u32 instance,
+                        u32 flags, struct acpi_table_header **table_pointer);
 
 /*
  * Namespace and name interfaces
  */
-
 acpi_status
-acpi_walk_namespace (
-        acpi_object_type                type,
-        acpi_handle                     start_object,
-        u32                             max_depth,
-        acpi_walk_callback              user_function,
-        void                            *context,
-        void                            **return_value);
+acpi_walk_namespace(acpi_object_type type,
+                    acpi_handle start_object,
+                    u32 max_depth,
+                    acpi_walk_callback user_function,
+                    void *context, void **return_value);
 
 acpi_status
-acpi_get_devices (
-        char                            *HID,
-        acpi_walk_callback              user_function,
-        void                            *context,
-        void                            **return_value);
+acpi_get_devices(char *HID,
+                 acpi_walk_callback user_function,
+                 void *context, void **return_value);
 
 acpi_status
-acpi_get_name (
-        acpi_handle                     handle,
-        u32                             name_type,
-        struct acpi_buffer              *ret_path_ptr);
+acpi_get_name(acpi_handle handle,
+              u32 name_type, struct acpi_buffer *ret_path_ptr);
 
 acpi_status
-acpi_get_handle (
-        acpi_handle                     parent,
-        acpi_string                     pathname,
-        acpi_handle                     *ret_handle);
+acpi_get_handle(acpi_handle parent,
+                acpi_string pathname, acpi_handle * ret_handle);
 
 acpi_status
-acpi_attach_data (
-        acpi_handle                     obj_handle,
-        acpi_object_handler             handler,
-        void                            *data);
+acpi_attach_data(acpi_handle obj_handle,
+                 acpi_object_handler handler, void *data);
 
 acpi_status
-acpi_detach_data (
-        acpi_handle                     obj_handle,
-        acpi_object_handler             handler);
+acpi_detach_data(acpi_handle obj_handle, acpi_object_handler handler);
 
 acpi_status
-acpi_get_data (
-        acpi_handle                     obj_handle,
-        acpi_object_handler             handler,
-        void                            **data);
-
+acpi_get_data(acpi_handle obj_handle, acpi_object_handler handler, void **data);
 
 /*
  * Object manipulation and enumeration
  */
-
 acpi_status
-acpi_evaluate_object (
-        acpi_handle                     object,
-        acpi_string                     pathname,
-        struct acpi_object_list         *parameter_objects,
-        struct acpi_buffer              *return_object_buffer);
+acpi_evaluate_object(acpi_handle object,
+                     acpi_string pathname,
+                     struct acpi_object_list *parameter_objects,
+                     struct acpi_buffer *return_object_buffer);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_evaluate_object_typed (
-        acpi_handle                     object,
-        acpi_string                     pathname,
-        struct acpi_object_list         *external_params,
-        struct acpi_buffer              *return_buffer,
-        acpi_object_type                return_type);
+acpi_evaluate_object_typed(acpi_handle object,
+                           acpi_string pathname,
+                           struct acpi_object_list *external_params,
+                           struct acpi_buffer *return_buffer,
+                           acpi_object_type return_type);
 #endif
 
 acpi_status
-acpi_get_object_info (
-        acpi_handle                     handle,
-        struct acpi_buffer              *return_buffer);
-
-acpi_status
-acpi_get_next_object (
-        acpi_object_type                type,
-        acpi_handle                     parent,
-        acpi_handle                     child,
-        acpi_handle                     *out_handle);
+acpi_get_object_info(acpi_handle handle, struct acpi_buffer *return_buffer);
 
 acpi_status
-acpi_get_type (
-        acpi_handle                     object,
-        acpi_object_type                *out_type);
+acpi_get_next_object(acpi_object_type type,
+                     acpi_handle parent,
+                     acpi_handle child, acpi_handle * out_handle);
 
-acpi_status
-acpi_get_parent (
-        acpi_handle                     object,
-        acpi_handle                     *out_handle);
+acpi_status acpi_get_type(acpi_handle object, acpi_object_type * out_type);
 
+acpi_status acpi_get_parent(acpi_handle object, acpi_handle * out_handle);
 
 /*
  * Event handler interfaces
  */
-
 acpi_status
-acpi_install_fixed_event_handler (
-        u32                             acpi_event,
-        acpi_event_handler              handler,
-        void                            *context);
+acpi_install_fixed_event_handler(u32 acpi_event,
+                                 acpi_event_handler handler, void *context);
 
 acpi_status
-acpi_remove_fixed_event_handler (
-        u32                             acpi_event,
-        acpi_event_handler              handler);
+acpi_remove_fixed_event_handler(u32 acpi_event, acpi_event_handler handler);
 
 acpi_status
-acpi_install_notify_handler (
-        acpi_handle                     device,
-        u32                             handler_type,
-        acpi_notify_handler             handler,
-        void                            *context);
+acpi_install_notify_handler(acpi_handle device,
+                            u32 handler_type,
+                            acpi_notify_handler handler, void *context);
 
 acpi_status
-acpi_remove_notify_handler (
-        acpi_handle                     device,
-        u32                             handler_type,
-        acpi_notify_handler             handler);
+acpi_remove_notify_handler(acpi_handle device,
+                           u32 handler_type, acpi_notify_handler handler);
 
 acpi_status
-acpi_install_address_space_handler (
-        acpi_handle                     device,
-        acpi_adr_space_type             space_id,
-        acpi_adr_space_handler          handler,
-        acpi_adr_space_setup            setup,
-        void                            *context);
+acpi_install_address_space_handler(acpi_handle device,
+                                   acpi_adr_space_type space_id,
+                                   acpi_adr_space_handler handler,
+                                   acpi_adr_space_setup setup, void *context);
 
 acpi_status
-acpi_remove_address_space_handler (
-        acpi_handle                     device,
-        acpi_adr_space_type             space_id,
-        acpi_adr_space_handler          handler);
+acpi_remove_address_space_handler(acpi_handle device,
+                                  acpi_adr_space_type space_id,
+                                  acpi_adr_space_handler handler);
 
 acpi_status
-acpi_install_gpe_handler (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u32                             type,
-        acpi_event_handler              address,
-        void                            *context);
+acpi_install_gpe_handler(acpi_handle gpe_device,
+                         u32 gpe_number,
+                         u32 type, acpi_event_handler address, void *context);
 
 #ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_install_exception_handler (
-        acpi_exception_handler          handler);
+acpi_status acpi_install_exception_handler(acpi_exception_handler handler);
 #endif
 
-
 /*
  * Event interfaces
  */
+acpi_status acpi_acquire_global_lock(u16 timeout, u32 * handle);
 
-acpi_status
-acpi_acquire_global_lock (
-        u16                             timeout,
-        u32                             *handle);
+acpi_status acpi_release_global_lock(u32 handle);
 
 acpi_status
-acpi_release_global_lock (
-        u32                             handle);
+acpi_remove_gpe_handler(acpi_handle gpe_device,
+                        u32 gpe_number, acpi_event_handler address);
 
-acpi_status
-acpi_remove_gpe_handler (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        acpi_event_handler              address);
+acpi_status acpi_enable_event(u32 event, u32 flags);
 
-acpi_status
-acpi_enable_event (
-        u32                             event,
-        u32                             flags);
+acpi_status acpi_disable_event(u32 event, u32 flags);
 
-acpi_status
-acpi_disable_event (
-        u32                             event,
-        u32                             flags);
-
-acpi_status
-acpi_clear_event (
-        u32                             event);
+acpi_status acpi_clear_event(u32 event);
 
 #ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_get_event_status (
-        u32                             event,
-        acpi_event_status               *event_status);
-#endif  /*  ACPI_FUTURE_USAGE  */
+acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status);
+#endif                          /*  ACPI_FUTURE_USAGE  */
 
-acpi_status
-acpi_set_gpe_type (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u8                              type);
+acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type);
 
-acpi_status
-acpi_enable_gpe (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u32                             flags);
+acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
-acpi_status
-acpi_disable_gpe (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u32                             flags);
+acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
-acpi_status
-acpi_clear_gpe (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u32                             flags);
+acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_get_gpe_status (
-        acpi_handle                     gpe_device,
-        u32                             gpe_number,
-        u32                             flags,
-        acpi_event_status               *event_status);
-#endif  /*  ACPI_FUTURE_USAGE  */
-
-acpi_status
-acpi_install_gpe_block (
-        acpi_handle                     gpe_device,
-        struct acpi_generic_address     *gpe_block_address,
-        u32                             register_count,
-        u32                             interrupt_level);
+acpi_get_gpe_status(acpi_handle gpe_device,
+                    u32 gpe_number,
+                    u32 flags, acpi_event_status * event_status);
+#endif                          /*  ACPI_FUTURE_USAGE  */
 
 acpi_status
-acpi_remove_gpe_block (
-        acpi_handle                     gpe_device);
+acpi_install_gpe_block(acpi_handle gpe_device,
+                       struct acpi_generic_address *gpe_block_address,
+                       u32 register_count, u32 interrupt_number);
 
+acpi_status acpi_remove_gpe_block(acpi_handle gpe_device);
 
 /*
  * Resource interfaces
  */
-
 typedef
-acpi_status (*ACPI_WALK_RESOURCE_CALLBACK) (
-        struct acpi_resource            *resource,
-        void                            *context);
-
+acpi_status(*ACPI_WALK_RESOURCE_CALLBACK) (struct acpi_resource * resource,
+                                           void *context);
 
 acpi_status
-acpi_get_current_resources(
-        acpi_handle                     device_handle,
-        struct acpi_buffer              *ret_buffer);
+acpi_get_current_resources(acpi_handle device_handle,
+                           struct acpi_buffer *ret_buffer);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_get_possible_resources(
-        acpi_handle                     device_handle,
-        struct acpi_buffer              *ret_buffer);
+acpi_get_possible_resources(acpi_handle device_handle,
+                            struct acpi_buffer *ret_buffer);
 #endif
 
 acpi_status
-acpi_walk_resources (
-        acpi_handle                             device_handle,
-        char                                    *path,
-        ACPI_WALK_RESOURCE_CALLBACK     user_function,
-        void                                    *context);
+acpi_walk_resources(acpi_handle device_handle,
+                    char *path,
+                    ACPI_WALK_RESOURCE_CALLBACK user_function, void *context);
 
 acpi_status
-acpi_set_current_resources (
-        acpi_handle                     device_handle,
-        struct acpi_buffer              *in_buffer);
+acpi_set_current_resources(acpi_handle device_handle,
+                           struct acpi_buffer *in_buffer);
 
 acpi_status
-acpi_get_irq_routing_table (
-        acpi_handle                     bus_device_handle,
-        struct acpi_buffer              *ret_buffer);
+acpi_get_irq_routing_table(acpi_handle bus_device_handle,
+                           struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_resource_to_address64 (
-        struct acpi_resource            *resource,
-        struct acpi_resource_address64 *out);
+acpi_resource_to_address64(struct acpi_resource *resource,
+                           struct acpi_resource_address64 *out);
 
 /*
  * Hardware (ACPI device) interfaces
  */
+acpi_status acpi_get_register(u32 register_id, u32 * return_value, u32 flags);
 
-acpi_status
-acpi_get_register (
-        u32                             register_id,
-        u32                             *return_value,
-        u32                             flags);
-
-acpi_status
-acpi_set_register (
-        u32                             register_id,
-        u32                             value,
-        u32                             flags);
+acpi_status acpi_set_register(u32 register_id, u32 value, u32 flags);
 
 acpi_status
-acpi_set_firmware_waking_vector (
-        acpi_physical_address           physical_address);
+acpi_set_firmware_waking_vector(acpi_physical_address physical_address);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_get_firmware_waking_vector (
-        acpi_physical_address           *physical_address);
+acpi_get_firmware_waking_vector(acpi_physical_address * physical_address);
 #endif
 
 acpi_status
-acpi_get_sleep_type_data (
-        u8                              sleep_state,
-        u8                              *slp_typ_a,
-        u8                              *slp_typ_b);
+acpi_get_sleep_type_data(u8 sleep_state, u8 * slp_typ_a, u8 * slp_typ_b);
 
-acpi_status
-acpi_enter_sleep_state_prep (
-        u8                              sleep_state);
-
-acpi_status asmlinkage
-acpi_enter_sleep_state (
-        u8                              sleep_state);
+acpi_status acpi_enter_sleep_state_prep(u8 sleep_state);
 
-acpi_status asmlinkage
-acpi_enter_sleep_state_s4bios (
-        void);
+acpi_status asmlinkage acpi_enter_sleep_state(u8 sleep_state);
 
-acpi_status
-acpi_leave_sleep_state (
-        u8                              sleep_state);
+acpi_status asmlinkage acpi_enter_sleep_state_s4bios(void);
 
+acpi_status acpi_leave_sleep_state(u8 sleep_state);
 
-#endif /* __ACXFACE_H__ */
+#endif                          /* __ACXFACE_H__ */
diff --git a/include/acpi/acresrc.h b/include/acpi/acresrc.h
index 93c55ff5c237..38e798b05d08 100644
--- a/include/acpi/acresrc.h
+++ b/include/acpi/acresrc.h
@@ -44,352 +44,216 @@
 #ifndef __ACRESRC_H__
 #define __ACRESRC_H__
 
-
 /*
  *  Function prototypes called from Acpi* APIs
  */
-
 acpi_status
-acpi_rs_get_prt_method_data (
-        acpi_handle                     handle,
-        struct acpi_buffer              *ret_buffer);
-
+acpi_rs_get_prt_method_data(acpi_handle handle, struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_rs_get_crs_method_data (
-        acpi_handle                     handle,
-        struct acpi_buffer              *ret_buffer);
+acpi_rs_get_crs_method_data(acpi_handle handle, struct acpi_buffer *ret_buffer);
 
-#ifdef ACPI_FUTURE_USAGE
+#ifdef  ACPI_FUTURE_USAGE
 acpi_status
-acpi_rs_get_prs_method_data (
-        acpi_handle                     handle,
-        struct acpi_buffer              *ret_buffer);
-#endif
+acpi_rs_get_prs_method_data(acpi_handle handle, struct acpi_buffer *ret_buffer);
+#endif                          /* ACPI_FUTURE_USAGE */
 
 acpi_status
-acpi_rs_get_method_data (
-        acpi_handle                     handle,
-        char                            *path,
-        struct acpi_buffer              *ret_buffer);
+acpi_rs_get_method_data(acpi_handle handle,
+                        char *path, struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_rs_set_srs_method_data (
-        acpi_handle                     handle,
-        struct acpi_buffer              *ret_buffer);
+acpi_rs_set_srs_method_data(acpi_handle handle, struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_rs_create_resource_list (
-        union acpi_operand_object       *byte_stream_buffer,
-        struct acpi_buffer              *output_buffer);
+acpi_rs_create_resource_list(union acpi_operand_object *byte_stream_buffer,
+                             struct acpi_buffer *output_buffer);
 
 acpi_status
-acpi_rs_create_byte_stream (
-        struct acpi_resource            *linked_list_buffer,
-        struct acpi_buffer              *output_buffer);
+acpi_rs_create_byte_stream(struct acpi_resource *linked_list_buffer,
+                           struct acpi_buffer *output_buffer);
 
 acpi_status
-acpi_rs_create_pci_routing_table (
-        union acpi_operand_object       *package_object,
-        struct acpi_buffer              *output_buffer);
-
+acpi_rs_create_pci_routing_table(union acpi_operand_object *package_object,
+                                 struct acpi_buffer *output_buffer);
 
 /*
- * Function prototypes called from acpi_rs_create*
+ * rsdump
  */
-#ifdef ACPI_FUTURE_USAGE
-void
-acpi_rs_dump_irq (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_address16 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_address32 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_address64 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_dma (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_io (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_extended_irq (
-        union acpi_resource_data        *data);
+#ifdef  ACPI_FUTURE_USAGE
+void acpi_rs_dump_resource_list(struct acpi_resource *resource);
 
-void
-acpi_rs_dump_fixed_io (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_fixed_memory32 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_memory24 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_memory32 (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_start_depend_fns (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_vendor_specific (
-        union acpi_resource_data        *data);
-
-void
-acpi_rs_dump_resource_list (
-        struct acpi_resource            *resource);
-
-void
-acpi_rs_dump_irq_list (
-        u8                              *route_table);
-#endif  /*  ACPI_FUTURE_USAGE  */
+void acpi_rs_dump_irq_list(u8 * route_table);
+#endif                          /* ACPI_FUTURE_USAGE */
 
+/*
+ * rscalc
+ */
 acpi_status
-acpi_rs_get_byte_stream_start (
-        u8                              *byte_stream_buffer,
-        u8                              **byte_stream_start,
-        u32                             *size);
+acpi_rs_get_byte_stream_start(u8 * byte_stream_buffer,
+                              u8 ** byte_stream_start, u32 * size);
 
 acpi_status
-acpi_rs_get_list_length (
-        u8                              *byte_stream_buffer,
-        u32                             byte_stream_buffer_length,
-        acpi_size                       *size_needed);
+acpi_rs_get_list_length(u8 * byte_stream_buffer,
+                        u32 byte_stream_buffer_length, acpi_size * size_needed);
 
 acpi_status
-acpi_rs_get_byte_stream_length (
-        struct acpi_resource            *linked_list_buffer,
-        acpi_size                       *size_needed);
+acpi_rs_get_byte_stream_length(struct acpi_resource *linked_list_buffer,
+                               acpi_size * size_needed);
 
 acpi_status
-acpi_rs_get_pci_routing_table_length (
-        union acpi_operand_object       *package_object,
-        acpi_size                       *buffer_size_needed);
+acpi_rs_get_pci_routing_table_length(union acpi_operand_object *package_object,
+                                     acpi_size * buffer_size_needed);
 
 acpi_status
-acpi_rs_byte_stream_to_list (
-        u8                              *byte_stream_buffer,
-        u32                             byte_stream_buffer_length,
-        u8                              *output_buffer);
+acpi_rs_byte_stream_to_list(u8 * byte_stream_buffer,
+                            u32 byte_stream_buffer_length, u8 * output_buffer);
 
 acpi_status
-acpi_rs_list_to_byte_stream (
-        struct acpi_resource            *linked_list,
-        acpi_size                       byte_stream_size_needed,
-        u8                              *output_buffer);
+acpi_rs_list_to_byte_stream(struct acpi_resource *linked_list,
+                            acpi_size byte_stream_size_needed,
+                            u8 * output_buffer);
 
 acpi_status
-acpi_rs_io_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_io_resource(u8 * byte_stream_buffer,
+                    acpi_size * bytes_consumed,
+                    u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_fixed_io_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_fixed_io_resource(u8 * byte_stream_buffer,
+                          acpi_size * bytes_consumed,
+                          u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_io_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_io_stream(struct acpi_resource *linked_list,
+                  u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_fixed_io_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_fixed_io_stream(struct acpi_resource *linked_list,
+                        u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_irq_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_irq_resource(u8 * byte_stream_buffer,
+                     acpi_size * bytes_consumed,
+                     u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_irq_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_irq_stream(struct acpi_resource *linked_list,
+                   u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_dma_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_dma_resource(u8 * byte_stream_buffer,
+                     acpi_size * bytes_consumed,
+                     u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_dma_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_dma_stream(struct acpi_resource *linked_list,
+                   u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_address16_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_address16_resource(u8 * byte_stream_buffer,
+                           acpi_size * bytes_consumed,
+                           u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_address16_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_address16_stream(struct acpi_resource *linked_list,
+                         u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_address32_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_address32_resource(u8 * byte_stream_buffer,
+                           acpi_size * bytes_consumed,
+                           u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_address32_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_address32_stream(struct acpi_resource *linked_list,
+                         u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_address64_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_address64_resource(u8 * byte_stream_buffer,
+                           acpi_size * bytes_consumed,
+                           u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_address64_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_address64_stream(struct acpi_resource *linked_list,
+                         u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_start_depend_fns_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_start_depend_fns_resource(u8 * byte_stream_buffer,
+                                  acpi_size * bytes_consumed,
+                                  u8 ** output_buffer,
+                                  acpi_size * structure_size);
 
 acpi_status
-acpi_rs_end_depend_fns_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_end_depend_fns_resource(u8 * byte_stream_buffer,
+                                acpi_size * bytes_consumed,
+                                u8 ** output_buffer,
+                                acpi_size * structure_size);
 
 acpi_status
-acpi_rs_start_depend_fns_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_start_depend_fns_stream(struct acpi_resource *linked_list,
+                                u8 ** output_buffer,
+                                acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_end_depend_fns_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_end_depend_fns_stream(struct acpi_resource *linked_list,
+                              u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_memory24_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_memory24_resource(u8 * byte_stream_buffer,
+                          acpi_size * bytes_consumed,
+                          u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_memory24_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_memory24_stream(struct acpi_resource *linked_list,
+                        u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_memory32_range_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_memory32_range_resource(u8 * byte_stream_buffer,
+                                acpi_size * bytes_consumed,
+                                u8 ** output_buffer,
+                                acpi_size * structure_size);
 
 acpi_status
-acpi_rs_fixed_memory32_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_fixed_memory32_resource(u8 * byte_stream_buffer,
+                                acpi_size * bytes_consumed,
+                                u8 ** output_buffer,
+                                acpi_size * structure_size);
 
 acpi_status
-acpi_rs_memory32_range_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_memory32_range_stream(struct acpi_resource *linked_list,
+                              u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_fixed_memory32_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_fixed_memory32_stream(struct acpi_resource *linked_list,
+                              u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_extended_irq_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_extended_irq_resource(u8 * byte_stream_buffer,
+                              acpi_size * bytes_consumed,
+                              u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_extended_irq_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_extended_irq_stream(struct acpi_resource *linked_list,
+                            u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_end_tag_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_end_tag_resource(u8 * byte_stream_buffer,
+                         acpi_size * bytes_consumed,
+                         u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_end_tag_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_end_tag_stream(struct acpi_resource *linked_list,
+                       u8 ** output_buffer, acpi_size * bytes_consumed);
 
 acpi_status
-acpi_rs_vendor_resource (
-        u8                              *byte_stream_buffer,
-        acpi_size                       *bytes_consumed,
-        u8                              **output_buffer,
-        acpi_size                       *structure_size);
+acpi_rs_vendor_resource(u8 * byte_stream_buffer,
+                        acpi_size * bytes_consumed,
+                        u8 ** output_buffer, acpi_size * structure_size);
 
 acpi_status
-acpi_rs_vendor_stream (
-        struct acpi_resource            *linked_list,
-        u8                              **output_buffer,
-        acpi_size                       *bytes_consumed);
+acpi_rs_vendor_stream(struct acpi_resource *linked_list,
+                      u8 ** output_buffer, acpi_size * bytes_consumed);
 
-u8
-acpi_rs_get_resource_type (
-        u8                              resource_start_byte);
+u8 acpi_rs_get_resource_type(u8 resource_start_byte);
 
-#endif  /* __ACRESRC_H__ */
+#endif                          /* __ACRESRC_H__ */
diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h
index c97843f6bcbc..99d235339801 100644
--- a/include/acpi/acstruct.h
+++ b/include/acpi/acstruct.h
@@ -44,19 +44,16 @@
 #ifndef __ACSTRUCT_H__
 #define __ACSTRUCT_H__
 
-
 /*****************************************************************************
  *
  * Tree walking typedefs and structs
  *
  ****************************************************************************/
 
-
 /*
  * Walk state - current state of a parse tree walk.  Used for both a leisurely stroll through
  * the tree (for whatever reason), and for control method execution.
  */
-
 #define ACPI_NEXT_OP_DOWNWARD       1
 #define ACPI_NEXT_OP_UPWARD         2
 
@@ -66,152 +63,142 @@
 #define ACPI_WALK_CONST_REQUIRED    3
 #define ACPI_WALK_CONST_OPTIONAL    4
 
-struct acpi_walk_state
-{
-        u8                                  data_type;                          /* To differentiate various internal objs MUST BE FIRST!*/\
-        u8                                  walk_type;
-        acpi_owner_id                       owner_id;                           /* Owner of objects created during the walk */
-        u8                                  last_predicate;                     /* Result of last predicate */
-        u8                                  reserved;                           /* For alignment */
-        u8                                  current_result;                     /* */
-        u8                                  next_op_info;                       /* Info about next_op */
-        u8                                  num_operands;                       /* Stack pointer for Operands[] array */
-        u8                                  return_used;
-        u16                                 opcode;                             /* Current AML opcode */
-        u8                                  scope_depth;
-        u8                                  reserved1;
-        u32                                 arg_count;                          /* push for fixed or var args */
-        u32                                 aml_offset;
-        u32                                 arg_types;
-        u32                                 method_breakpoint;                  /* For single stepping */
-        u32                                 user_breakpoint;                    /* User AML breakpoint */
-        u32                                 parse_flags;
-        u32                                 prev_arg_types;
-
-        u8                                  *aml_last_while;
-        struct acpi_namespace_node          arguments[ACPI_METHOD_NUM_ARGS];    /* Control method arguments */
-        union acpi_operand_object           **caller_return_desc;
-        union acpi_generic_state            *control_state;                     /* List of control states (nested IFs) */
-        struct acpi_namespace_node          *deferred_node;                     /* Used when executing deferred opcodes */
-        struct acpi_gpe_event_info          *gpe_event_info;                    /* Info for GPE (_Lxx/_Exx methods only */
-        union acpi_operand_object           *implicit_return_obj;
-        struct acpi_namespace_node          local_variables[ACPI_METHOD_NUM_LOCALS];    /* Control method locals */
-        struct acpi_namespace_node          *method_call_node;                  /* Called method Node*/
-        union acpi_parse_object             *method_call_op;                    /* method_call Op if running a method */
-        union acpi_operand_object           *method_desc;                       /* Method descriptor if running a method */
-        struct acpi_namespace_node          *method_node;                       /* Method node if running a method. */
-        union acpi_parse_object             *op;                                /* Current parser op */
-        union acpi_operand_object           *operands[ACPI_OBJ_NUM_OPERANDS+1]; /* Operands passed to the interpreter (+1 for NULL terminator) */
-        const struct acpi_opcode_info       *op_info;                           /* Info on current opcode */
-        union acpi_parse_object             *origin;                            /* Start of walk [Obsolete] */
-        union acpi_operand_object           **params;
-        struct acpi_parse_state             parser_state;                       /* Current state of parser */
-        union acpi_operand_object           *result_obj;
-        union acpi_generic_state            *results;                           /* Stack of accumulated results */
-        union acpi_operand_object           *return_desc;                       /* Return object, if any */
-        union acpi_generic_state            *scope_info;                        /* Stack of nested scopes */
-
-        union acpi_parse_object             *prev_op;                           /* Last op that was processed */
-        union acpi_parse_object             *next_op;                           /* next op to be processed */
-        acpi_parse_downwards                descending_callback;
-        acpi_parse_upwards                  ascending_callback;
-        struct acpi_thread_state            *thread;
-        struct acpi_walk_state              *next;                              /* Next walk_state in list */
+struct acpi_walk_state {
+        u8 data_type;           /* To differentiate various internal objs MUST BE FIRST! */
+        u8 walk_type;
+        acpi_owner_id owner_id; /* Owner of objects created during the walk */
+        u8 last_predicate;      /* Result of last predicate */
+        u8 current_result;      /* */
+        u8 next_op_info;        /* Info about next_op */
+        u8 num_operands;        /* Stack pointer for Operands[] array */
+        u8 return_used;
+        u16 opcode;             /* Current AML opcode */
+        u8 scope_depth;
+        u8 pass_number;         /* Parse pass during table load */
+        u32 arg_count;          /* push for fixed or var args */
+        u32 aml_offset;
+        u32 arg_types;
+        u32 method_breakpoint;  /* For single stepping */
+        u32 user_breakpoint;    /* User AML breakpoint */
+        u32 parse_flags;
+        u32 prev_arg_types;
+
+        u8 *aml_last_while;
+        struct acpi_namespace_node arguments[ACPI_METHOD_NUM_ARGS];     /* Control method arguments */
+        union acpi_operand_object **caller_return_desc;
+        union acpi_generic_state *control_state;        /* List of control states (nested IFs) */
+        struct acpi_namespace_node *deferred_node;      /* Used when executing deferred opcodes */
+        struct acpi_gpe_event_info *gpe_event_info;     /* Info for GPE (_Lxx/_Exx methods only */
+        union acpi_operand_object *implicit_return_obj;
+        struct acpi_namespace_node local_variables[ACPI_METHOD_NUM_LOCALS];     /* Control method locals */
+        struct acpi_namespace_node *method_call_node;   /* Called method Node */
+        union acpi_parse_object *method_call_op;        /* method_call Op if running a method */
+        union acpi_operand_object *method_desc; /* Method descriptor if running a method */
+        struct acpi_namespace_node *method_node;        /* Method node if running a method. */
+        union acpi_parse_object *op;    /* Current parser op */
+        union acpi_operand_object *operands[ACPI_OBJ_NUM_OPERANDS + 1]; /* Operands passed to the interpreter (+1 for NULL terminator) */
+        const struct acpi_opcode_info *op_info; /* Info on current opcode */
+        union acpi_parse_object *origin;        /* Start of walk [Obsolete] */
+        union acpi_operand_object **params;
+        struct acpi_parse_state parser_state;   /* Current state of parser */
+        union acpi_operand_object *result_obj;
+        union acpi_generic_state *results;      /* Stack of accumulated results */
+        union acpi_operand_object *return_desc; /* Return object, if any */
+        union acpi_generic_state *scope_info;   /* Stack of nested scopes */
+
+        union acpi_parse_object *prev_op;       /* Last op that was processed */
+        union acpi_parse_object *next_op;       /* next op to be processed */
+        acpi_parse_downwards descending_callback;
+        acpi_parse_upwards ascending_callback;
+        struct acpi_thread_state *thread;
+        struct acpi_walk_state *next;   /* Next walk_state in list */
 };
 
-
 /* Info used by acpi_ps_init_objects */
 
-struct acpi_init_walk_info
-{
-        u16                             method_count;
-        u16                             device_count;
-        u16                             op_region_count;
-        u16                             field_count;
-        u16                             buffer_count;
-        u16                             package_count;
-        u16                             op_region_init;
-        u16                             field_init;
-        u16                             buffer_init;
-        u16                             package_init;
-        u16                             object_count;
-        struct acpi_table_desc          *table_desc;
+struct acpi_init_walk_info {
+        u16 method_count;
+        u16 device_count;
+        u16 op_region_count;
+        u16 field_count;
+        u16 buffer_count;
+        u16 package_count;
+        u16 op_region_init;
+        u16 field_init;
+        u16 buffer_init;
+        u16 package_init;
+        u16 object_count;
+        struct acpi_table_desc *table_desc;
 };
 
-
 /* Info used by acpi_ns_initialize_devices */
 
-struct acpi_device_walk_info
-{
-        u16                             device_count;
-        u16                             num_STA;
-        u16                             num_INI;
-        struct acpi_table_desc          *table_desc;
+struct acpi_device_walk_info {
+        u16 device_count;
+        u16 num_STA;
+        u16 num_INI;
+        struct acpi_table_desc *table_desc;
 };
 
-
 /* TBD: [Restructure] Merge with struct above */
 
-struct acpi_walk_info
-{
-        u32                             debug_level;
-        u32                             owner_id;
-        u8                              display_type;
+struct acpi_walk_info {
+        u32 debug_level;
+        u32 count;
+        acpi_owner_id owner_id;
+        u8 display_type;
 };
 
 /* Display Types */
 
-#define ACPI_DISPLAY_SUMMARY    0
-#define ACPI_DISPLAY_OBJECTS    1
+#define ACPI_DISPLAY_SUMMARY    (u8) 0
+#define ACPI_DISPLAY_OBJECTS    (u8) 1
+#define ACPI_DISPLAY_MASK       (u8) 1
 
-struct acpi_get_devices_info
-{
-        acpi_walk_callback              user_function;
-        void                            *context;
-        char                            *hid;
-};
+#define ACPI_DISPLAY_SHORT      (u8) 2
 
+struct acpi_get_devices_info {
+        acpi_walk_callback user_function;
+        void *context;
+        char *hid;
+};
 
-union acpi_aml_operands
-{
-        union acpi_operand_object           *operands[7];
+union acpi_aml_operands {
+        union acpi_operand_object *operands[7];
 
-        struct
-        {
-                struct acpi_object_integer      *type;
-                struct acpi_object_integer      *code;
-                struct acpi_object_integer      *argument;
+        struct {
+                struct acpi_object_integer *type;
+                struct acpi_object_integer *code;
+                struct acpi_object_integer *argument;
 
         } fatal;
 
-        struct
-        {
-                union acpi_operand_object       *source;
-                struct acpi_object_integer      *index;
-                union acpi_operand_object       *target;
+        struct {
+                union acpi_operand_object *source;
+                struct acpi_object_integer *index;
+                union acpi_operand_object *target;
 
         } index;
 
-        struct
-        {
-                union acpi_operand_object       *source;
-                struct acpi_object_integer      *index;
-                struct acpi_object_integer      *length;
-                union acpi_operand_object       *target;
+        struct {
+                union acpi_operand_object *source;
+                struct acpi_object_integer *index;
+                struct acpi_object_integer *length;
+                union acpi_operand_object *target;
 
         } mid;
 };
 
-
 /* Internal method parameter list */
 
-struct acpi_parameter_info
-{
-        struct acpi_namespace_node      *node;
-        union acpi_operand_object       **parameters;
-        union acpi_operand_object       *return_object;
-        u8                              parameter_type;
-        u8                              return_object_type;
+struct acpi_parameter_info {
+        struct acpi_namespace_node *node;
+        union acpi_operand_object *obj_desc;
+        union acpi_operand_object **parameters;
+        union acpi_operand_object *return_object;
+        u8 pass_number;
+        u8 parameter_type;
+        u8 return_object_type;
 };
 
 /* Types for parameter_type above */
@@ -219,5 +206,4 @@ struct acpi_parameter_info
 #define ACPI_PARAM_ARGS                 0
 #define ACPI_PARAM_GPE                  1
 
-
 #endif
diff --git a/include/acpi/actables.h b/include/acpi/actables.h
index e8f5d4ffd452..f92c1858b808 100644
--- a/include/acpi/actables.h
+++ b/include/acpi/actables.h
@@ -44,192 +44,101 @@
 #ifndef __ACTABLES_H__
 #define __ACTABLES_H__
 
-
 /* Used in acpi_tb_map_acpi_table for size parameter if table header is to be used */
 
 #define SIZE_IN_HEADER          0
 
-
-#ifdef ACPI_FUTURE_USAGE
-acpi_status
-acpi_tb_handle_to_object (
-        u16                             table_id,
-        struct acpi_table_desc          **table_desc);
-#endif
-
 /*
  * tbconvrt - Table conversion routines
  */
+acpi_status acpi_tb_convert_to_xsdt(struct acpi_table_desc *table_info);
 
-acpi_status
-acpi_tb_convert_to_xsdt (
-        struct acpi_table_desc          *table_info);
+acpi_status acpi_tb_convert_table_fadt(void);
 
-acpi_status
-acpi_tb_convert_table_fadt (
-        void);
-
-acpi_status
-acpi_tb_build_common_facs (
-        struct acpi_table_desc          *table_info);
+acpi_status acpi_tb_build_common_facs(struct acpi_table_desc *table_info);
 
 u32
-acpi_tb_get_table_count (
-        struct rsdp_descriptor          *RSDP,
-        struct acpi_table_header        *RSDT);
+acpi_tb_get_table_count(struct rsdp_descriptor *RSDP,
+                        struct acpi_table_header *RSDT);
 
 /*
  * tbget - Table "get" routines
  */
-
 acpi_status
-acpi_tb_get_table (
-        struct acpi_pointer             *address,
-        struct acpi_table_desc          *table_info);
+acpi_tb_get_table(struct acpi_pointer *address,
+                  struct acpi_table_desc *table_info);
 
 acpi_status
-acpi_tb_get_table_header (
-        struct acpi_pointer             *address,
-        struct acpi_table_header        *return_header);
+acpi_tb_get_table_header(struct acpi_pointer *address,
+                         struct acpi_table_header *return_header);
 
 acpi_status
-acpi_tb_get_table_body (
-        struct acpi_pointer             *address,
-        struct acpi_table_header        *header,
-        struct acpi_table_desc          *table_info);
+acpi_tb_get_table_body(struct acpi_pointer *address,
+                       struct acpi_table_header *header,
+                       struct acpi_table_desc *table_info);
 
 acpi_status
-acpi_tb_get_this_table (
-        struct acpi_pointer             *address,
-        struct acpi_table_header        *header,
-        struct acpi_table_desc          *table_info);
+acpi_tb_get_table_ptr(acpi_table_type table_type,
+                      u32 instance, struct acpi_table_header **table_ptr_loc);
 
-acpi_status
-acpi_tb_table_override (
-        struct acpi_table_header        *header,
-        struct acpi_table_desc          *table_info);
+acpi_status acpi_tb_verify_rsdp(struct acpi_pointer *address);
 
-acpi_status
-acpi_tb_get_table_ptr (
-        acpi_table_type                 table_type,
-        u32                             instance,
-        struct acpi_table_header        **table_ptr_loc);
+void acpi_tb_get_rsdt_address(struct acpi_pointer *out_address);
 
-acpi_status
-acpi_tb_verify_rsdp (
-        struct acpi_pointer             *address);
+acpi_status acpi_tb_validate_rsdt(struct acpi_table_header *table_ptr);
 
-void
-acpi_tb_get_rsdt_address (
-        struct acpi_pointer             *out_address);
-
-acpi_status
-acpi_tb_validate_rsdt (
-        struct acpi_table_header        *table_ptr);
-
-acpi_status
-acpi_tb_get_required_tables (
-        void);
-
-acpi_status
-acpi_tb_get_primary_table (
-        struct acpi_pointer             *address,
-        struct acpi_table_desc          *table_info);
-
-acpi_status
-acpi_tb_get_secondary_table (
-        struct acpi_pointer             *address,
-        acpi_string                     signature,
-        struct acpi_table_desc          *table_info);
+/*
+ * tbgetall - get multiple required tables
+ */
+acpi_status acpi_tb_get_required_tables(void);
 
 /*
  * tbinstall - Table installation
  */
+acpi_status acpi_tb_install_table(struct acpi_table_desc *table_info);
 
 acpi_status
-acpi_tb_install_table (
-        struct acpi_table_desc          *table_info);
+acpi_tb_recognize_table(struct acpi_table_desc *table_info, u8 search_type);
 
 acpi_status
-acpi_tb_match_signature (
-        char                            *signature,
-        struct acpi_table_desc          *table_info,
-        u8                              search_type);
-
-acpi_status
-acpi_tb_recognize_table (
-        struct acpi_table_desc          *table_info,
-        u8                              search_type);
-
-acpi_status
-acpi_tb_init_table_descriptor (
-        acpi_table_type                 table_type,
-        struct acpi_table_desc          *table_info);
-
+acpi_tb_init_table_descriptor(acpi_table_type table_type,
+                              struct acpi_table_desc *table_info);
 
 /*
  * tbremove - Table removal and deletion
  */
+void acpi_tb_delete_all_tables(void);
 
-void
-acpi_tb_delete_all_tables (
-        void);
+void acpi_tb_delete_tables_by_type(acpi_table_type type);
 
-void
-acpi_tb_delete_tables_by_type (
-        acpi_table_type                 type);
-
-void
-acpi_tb_delete_single_table (
-        struct acpi_table_desc          *table_desc);
-
-struct acpi_table_desc *
-acpi_tb_uninstall_table (
-        struct acpi_table_desc          *table_desc);
+void acpi_tb_delete_single_table(struct acpi_table_desc *table_desc);
 
+struct acpi_table_desc *acpi_tb_uninstall_table(struct acpi_table_desc
+                                                *table_desc);
 
 /*
- * tbrsd - RSDP, RSDT utilities
+ * tbxfroot - RSDP, RSDT utilities
  */
-
 acpi_status
-acpi_tb_get_table_rsdt (
-        void);
-
-u8 *
-acpi_tb_scan_memory_for_rsdp (
-        u8                              *start_address,
-        u32                             length);
+acpi_tb_find_table(char *signature,
+                   char *oem_id,
+                   char *oem_table_id, struct acpi_table_header **table_ptr);
 
-acpi_status
-acpi_tb_find_rsdp (
-        struct acpi_table_desc          *table_info,
-        u32                             flags);
+acpi_status acpi_tb_get_table_rsdt(void);
 
+acpi_status acpi_tb_validate_rsdp(struct rsdp_descriptor *rsdp);
 
 /*
  * tbutils - common table utilities
  */
+acpi_status acpi_tb_is_table_installed(struct acpi_table_desc *new_table_desc);
 
 acpi_status
-acpi_tb_find_table (
-        char                            *signature,
-        char                            *oem_id,
-        char                            *oem_table_id,
-        struct acpi_table_header        **table_ptr);
-
-acpi_status
-acpi_tb_verify_table_checksum (
-        struct acpi_table_header        *table_header);
+acpi_tb_verify_table_checksum(struct acpi_table_header *table_header);
 
-u8
-acpi_tb_checksum (
-        void                            *buffer,
-        u32                             length);
+u8 acpi_tb_generate_checksum(void *buffer, u32 length);
 
 acpi_status
-acpi_tb_validate_table_header (
-        struct acpi_table_header        *table_header);
-
+acpi_tb_validate_table_header(struct acpi_table_header *table_header);
 
-#endif /* __ACTABLES_H__ */
+#endif                          /* __ACTABLES_H__ */
diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h
index 7eee731112b1..a46f406e1c94 100644
--- a/include/acpi/actbl.h
+++ b/include/acpi/actbl.h
@@ -44,27 +44,24 @@
 #ifndef __ACTBL_H__
 #define __ACTBL_H__
 
-
 /*
  *  Values for description table header signatures
  */
 #define RSDP_NAME               "RSDP"
-#define RSDP_SIG                "RSD PTR "  /* RSDT Pointer signature */
-#define APIC_SIG                "APIC"      /* Multiple APIC Description Table */
-#define DSDT_SIG                "DSDT"      /* Differentiated System Description Table */
-#define FADT_SIG                "FACP"      /* Fixed ACPI Description Table */
-#define FACS_SIG                "FACS"      /* Firmware ACPI Control Structure */
-#define PSDT_SIG                "PSDT"      /* Persistent System Description Table */
-#define RSDT_SIG                "RSDT"      /* Root System Description Table */
-#define XSDT_SIG                "XSDT"      /* Extended  System Description Table */
-#define SSDT_SIG                "SSDT"      /* Secondary System Description Table */
-#define SBST_SIG                "SBST"      /* Smart Battery Specification Table */
-#define SPIC_SIG                "SPIC"      /* IOSAPIC table */
-#define BOOT_SIG                "BOOT"      /* Boot table */
-
-
-#define GL_OWNED                0x02        /* Ownership of global lock is bit 1 */
-
+#define RSDP_SIG                "RSD PTR "      /* RSDT Pointer signature */
+#define APIC_SIG                "APIC"  /* Multiple APIC Description Table */
+#define DSDT_SIG                "DSDT"  /* Differentiated System Description Table */
+#define FADT_SIG                "FACP"  /* Fixed ACPI Description Table */
+#define FACS_SIG                "FACS"  /* Firmware ACPI Control Structure */
+#define PSDT_SIG                "PSDT"  /* Persistent System Description Table */
+#define RSDT_SIG                "RSDT"  /* Root System Description Table */
+#define XSDT_SIG                "XSDT"  /* Extended  System Description Table */
+#define SSDT_SIG                "SSDT"  /* Secondary System Description Table */
+#define SBST_SIG                "SBST"  /* Smart Battery Specification Table */
+#define SPIC_SIG                "SPIC"  /* IOSAPIC table */
+#define BOOT_SIG                "BOOT"  /* Boot table */
+
+#define GL_OWNED                0x02    /* Ownership of global lock is bit 1 */
 
 /*
  * Common table types.  The base code can remain
@@ -75,7 +72,6 @@
 #define FACS_DESCRIPTOR         struct facs_descriptor_rev2
 #define FADT_DESCRIPTOR         struct fadt_descriptor_rev2
 
-
 #pragma pack(1)
 
 /*
@@ -84,45 +80,37 @@
  * NOTE: The tables that are specific to ACPI versions (1.0, 2.0, etc.)
  * are in separate files.
  */
-struct rsdp_descriptor         /* Root System Descriptor Pointer */
-{
-        char                            signature [8];          /* ACPI signature, contains "RSD PTR " */
-        u8                              checksum;               /* To make sum of struct == 0 */
-        char                            oem_id [6];             /* OEM identification */
-        u8                              revision;               /* Must be 0 for 1.0, 2 for 2.0 */
-        u32                             rsdt_physical_address;  /* 32-bit physical address of RSDT */
-        u32                             length;                 /* XSDT Length in bytes including hdr */
-        u64                             xsdt_physical_address;  /* 64-bit physical address of XSDT */
-        u8                              extended_checksum;      /* Checksum of entire table */
-        char                            reserved [3];           /* Reserved field must be 0 */
+struct rsdp_descriptor {        /* Root System Descriptor Pointer */
+        char signature[8];      /* ACPI signature, contains "RSD PTR " */
+        u8 checksum;            /* ACPI 1.0 checksum */
+        char oem_id[6];         /* OEM identification */
+        u8 revision;            /* Must be (0) for ACPI 1.0 or (2) for ACPI 2.0+ */
+        u32 rsdt_physical_address;      /* 32-bit physical address of the RSDT */
+        u32 length;             /* XSDT Length in bytes, including header */
+        u64 xsdt_physical_address;      /* 64-bit physical address of the XSDT */
+        u8 extended_checksum;   /* Checksum of entire table (ACPI 2.0) */
+        char reserved[3];       /* Reserved, must be zero */
 };
 
-
-struct acpi_common_facs          /* Common FACS for internal use */
-{
-        u32                             *global_lock;
-        u64                             *firmware_waking_vector;
-        u8                              vector_width;
+struct acpi_common_facs {       /* Common FACS for internal use */
+        u32 *global_lock;
+        u64 *firmware_waking_vector;
+        u8 vector_width;
 };
 
-
 #define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
-        char                            signature [4];          /* ACPI signature (4 ASCII characters) */\
-        u32                             length;                 /* Length of table, in bytes, including header */\
+        char                            signature[4];           /* ASCII table signature */\
+        u32                             length;                 /* Length of table in bytes, including this header */\
         u8                              revision;               /* ACPI Specification minor version # */\
         u8                              checksum;               /* To make sum of entire table == 0 */\
-        char                            oem_id [6];             /* OEM identification */\
-        char                            oem_table_id [8];       /* OEM table identification */\
+        char                            oem_id[6];              /* ASCII OEM identification */\
+        char                            oem_table_id[8];        /* ASCII OEM table identification */\
         u32                             oem_revision;           /* OEM revision number */\
-        char                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
-        u32                             asl_compiler_revision;  /* ASL compiler revision number */
-
-
-struct acpi_table_header         /* ACPI common table header */
-{
-        ACPI_TABLE_HEADER_DEF
-};
+        char                            asl_compiler_id [4];    /* ASCII ASL compiler vendor ID */\
+        u32                             asl_compiler_revision;  /* ASL compiler version */
 
+struct acpi_table_header {      /* ACPI common table header */
+ACPI_TABLE_HEADER_DEF};
 
 /*
  * MADT values and structures
@@ -133,17 +121,18 @@ struct acpi_table_header         /* ACPI common table header */
 #define DUAL_PIC                0
 #define MULTIPLE_APIC           1
 
-
 /* Master MADT */
 
-struct multiple_apic_table
-{
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-        u32                             local_apic_address;     /* Physical address of local APIC */
-        u32                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
-        u32                             reserved1       : 31;
-};
+struct multiple_apic_table {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        u32 local_apic_address; /* Physical address of local APIC */
+
+        /* Flags (32 bits) */
 
+        u8 PCATcompat:1;        /* 00:    System also has dual 8259s */
+         u8:7;                  /* 01-07: Reserved, must be zero */
+        u8 reserved1[3];        /* 08-31: Reserved, must be zero */
+};
 
 /* Values for Type in APIC_HEADER_DEF */
 
@@ -156,7 +145,7 @@ struct multiple_apic_table
 #define APIC_IO_SAPIC           6
 #define APIC_LOCAL_SAPIC        7
 #define APIC_XRUPT_SOURCE       8
-#define APIC_RESERVED           9           /* 9 and greater are reserved */
+#define APIC_RESERVED           9       /* 9 and greater are reserved */
 
 /*
  * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -165,10 +154,8 @@ struct multiple_apic_table
         u8                              type; \
         u8                              length;
 
-struct apic_header
-{
-        APIC_HEADER_DEF
-};
+struct apic_header {
+APIC_HEADER_DEF};
 
 /* Values for MPS INTI flags */
 
@@ -182,117 +169,90 @@ struct apic_header
 #define TRIGGER_RESERVED        2
 #define TRIGGER_LEVEL           3
 
-/* Common flag definitions */
+/* Common flag definitions (16 bits each) */
 
 #define MPS_INTI_FLAGS \
-        u16                             polarity        : 2;    /* Polarity of APIC I/O input signals */\
-        u16                             trigger_mode    : 2;    /* Trigger mode of APIC input signals */\
-        u16                             reserved1       : 12;   /* Reserved, must be zero */
+        u8                              polarity        : 2;    /* 00-01: Polarity of APIC I/O input signals */\
+        u8                              trigger_mode    : 2;    /* 02-03: Trigger mode of APIC input signals */\
+        u8                                              : 4;    /* 04-07: Reserved, must be zero */\
+        u8                              reserved1;      /* 08-15: Reserved, must be zero */
 
 #define LOCAL_APIC_FLAGS \
-        u32                             processor_enabled: 1;   /* Processor is usable if set */\
-        u32                             reserved2       : 31;   /* Reserved, must be zero */
+        u8                              processor_enabled: 1;   /* 00:    Processor is usable if set */\
+        u8                                              : 7;    /* 01-07: Reserved, must be zero */\
+        u8                              reserved2;      /* 08-15: Reserved, must be zero */
 
 /* Sub-structures for MADT */
 
-struct madt_processor_apic
-{
-        APIC_HEADER_DEF
-        u8                              processor_id;           /* ACPI processor id */
-        u8                              local_apic_id;          /* Processor's local APIC id */
-        LOCAL_APIC_FLAGS
+struct madt_processor_apic {
+        APIC_HEADER_DEF u8 processor_id;        /* ACPI processor id */
+        u8 local_apic_id;       /* Processor's local APIC id */
+ LOCAL_APIC_FLAGS};
+
+struct madt_io_apic {
+        APIC_HEADER_DEF u8 io_apic_id;  /* I/O APIC ID */
+        u8 reserved;            /* Reserved - must be zero */
+        u32 address;            /* APIC physical address */
+        u32 interrupt;          /* Global system interrupt where INTI
+                                 * lines start */
 };
 
-struct madt_io_apic
-{
-        APIC_HEADER_DEF
-        u8                              io_apic_id;             /* I/O APIC ID */
-        u8                              reserved;               /* Reserved - must be zero */
-        u32                             address;                /* APIC physical address */
-        u32                             interrupt;              /* Global system interrupt where INTI
-                          * lines start */
-};
+struct madt_interrupt_override {
+        APIC_HEADER_DEF u8 bus; /* 0 - ISA */
+        u8 source;              /* Interrupt source (IRQ) */
+        u32 interrupt;          /* Global system interrupt */
+ MPS_INTI_FLAGS};
 
-struct madt_interrupt_override
-{
-        APIC_HEADER_DEF
-        u8                              bus;                    /* 0 - ISA */
-        u8                              source;                 /* Interrupt source (IRQ) */
-        u32                             interrupt;              /* Global system interrupt */
-        MPS_INTI_FLAGS
+struct madt_nmi_source {
+        APIC_HEADER_DEF MPS_INTI_FLAGS u32 interrupt;   /* Global system interrupt */
 };
 
-struct madt_nmi_source
-{
-        APIC_HEADER_DEF
-        MPS_INTI_FLAGS
-        u32                             interrupt;              /* Global system interrupt */
+struct madt_local_apic_nmi {
+        APIC_HEADER_DEF u8 processor_id;        /* ACPI processor id */
+        MPS_INTI_FLAGS u8 lint; /* LINTn to which NMI is connected */
 };
 
-struct madt_local_apic_nmi
-{
-        APIC_HEADER_DEF
-        u8                              processor_id;           /* ACPI processor id */
-        MPS_INTI_FLAGS
-        u8                              lint;                   /* LINTn to which NMI is connected */
+struct madt_address_override {
+        APIC_HEADER_DEF u16 reserved;   /* Reserved, must be zero */
+        u64 address;            /* APIC physical address */
 };
 
-struct madt_address_override
-{
-        APIC_HEADER_DEF
-        u16                             reserved;               /* Reserved - must be zero */
-        u64                             address;                /* APIC physical address */
+struct madt_io_sapic {
+        APIC_HEADER_DEF u8 io_sapic_id; /* I/O SAPIC ID */
+        u8 reserved;            /* Reserved, must be zero */
+        u32 interrupt_base;     /* Glocal interrupt for SAPIC start */
+        u64 address;            /* SAPIC physical address */
 };
 
-struct madt_io_sapic
-{
-        APIC_HEADER_DEF
-        u8                              io_sapic_id;            /* I/O SAPIC ID */
-        u8                              reserved;               /* Reserved - must be zero */
-        u32                             interrupt_base;         /* Glocal interrupt for SAPIC start */
-        u64                             address;                /* SAPIC physical address */
+struct madt_local_sapic {
+        APIC_HEADER_DEF u8 processor_id;        /* ACPI processor id */
+        u8 local_sapic_id;      /* SAPIC ID */
+        u8 local_sapic_eid;     /* SAPIC EID */
+        u8 reserved[3];         /* Reserved, must be zero */
+         LOCAL_APIC_FLAGS u32 processor_uID;    /* Numeric UID - ACPI 3.0 */
+        char processor_uIDstring[1];    /* String UID  - ACPI 3.0 */
 };
 
-struct madt_local_sapic
-{
-        APIC_HEADER_DEF
-        u8                              processor_id;           /* ACPI processor id */
-        u8                              local_sapic_id;         /* SAPIC ID */
-        u8                              local_sapic_eid;        /* SAPIC EID */
-        u8                              reserved [3];           /* Reserved - must be zero */
-        LOCAL_APIC_FLAGS
-        u32                             processor_uID;          /* Numeric UID - ACPI 3.0 */
-        char                            processor_uIDstring[1]; /* String UID  - ACPI 3.0 */
+struct madt_interrupt_source {
+        APIC_HEADER_DEF MPS_INTI_FLAGS u8 interrupt_type;       /* 1=PMI, 2=INIT, 3=corrected */
+        u8 processor_id;        /* Processor ID */
+        u8 processor_eid;       /* Processor EID */
+        u8 io_sapic_vector;     /* Vector value for PMI interrupts */
+        u32 interrupt;          /* Global system interrupt */
+        u32 flags;              /* Interrupt Source Flags */
 };
 
-struct madt_interrupt_source
-{
-        APIC_HEADER_DEF
-        MPS_INTI_FLAGS
-        u8                              interrupt_type;         /* 1=PMI, 2=INIT, 3=corrected */
-        u8                              processor_id;           /* Processor ID */
-        u8                              processor_eid;          /* Processor EID */
-        u8                              io_sapic_vector;        /* Vector value for PMI interrupts */
-        u32                             interrupt;              /* Global system interrupt */
-        u32                             flags;                  /* Interrupt Source Flags */
-};
-
-
 /*
  * Smart Battery
  */
-struct smart_battery_table
-{
-        ACPI_TABLE_HEADER_DEF
-        u32                             warning_level;
-        u32                             low_level;
-        u32                             critical_level;
+struct smart_battery_table {
+        ACPI_TABLE_HEADER_DEF u32 warning_level;
+        u32 low_level;
+        u32 critical_level;
 };
 
-
 #pragma pack()
 
-
 /*
  * ACPI Table information.  We save the table address, length,
  * and type of memory allocation (mapped or allocated) for each
@@ -316,39 +276,35 @@ struct smart_battery_table
 
 /* Data about each known table type */
 
-struct acpi_table_support
-{
-        char                            *name;
-        char                            *signature;
-        void                            **global_ptr;
-        u8                              sig_length;
-        u8                              flags;
+struct acpi_table_support {
+        char *name;
+        char *signature;
+        void **global_ptr;
+        u8 sig_length;
+        u8 flags;
 };
 
-
 /*
  * Get the ACPI version-specific tables
  */
-#include "actbl1.h"   /* Acpi 1.0 table definitions */
-#include "actbl2.h"   /* Acpi 2.0 table definitions */
+#include "actbl1.h"             /* Acpi 1.0 table definitions */
+#include "actbl2.h"             /* Acpi 2.0 table definitions */
 
-extern u8 acpi_fadt_is_v1; /* is set to 1 if FADT is revision 1,
-                            * needed for certain workarounds */
+extern u8 acpi_fadt_is_v1;      /* is set to 1 if FADT is revision 1,
+                                 * needed for certain workarounds */
 
 #pragma pack(1)
 /*
  * High performance timer
  */
-struct hpet_table
-{
-        ACPI_TABLE_HEADER_DEF
-        u32                             hardware_id;
-        struct acpi_generic_address     base_address;
-        u8                              hpet_number;
-        u16                             clock_tick;
-        u8                              attributes;
+struct hpet_table {
+        ACPI_TABLE_HEADER_DEF u32 hardware_id;
+        struct acpi_generic_address base_address;
+        u8 hpet_number;
+        u16 clock_tick;
+        u8 attributes;
 };
 
 #pragma pack()
 
-#endif /* __ACTBL_H__ */
+#endif                          /* __ACTBL_H__ */
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 33de5f4d2ccc..67312c3a915a 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -49,88 +49,87 @@
 /*
  * ACPI 1.0 Root System Description Table (RSDT)
  */
-struct rsdt_descriptor_rev1
-{
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-        u32                             table_offset_entry [1]; /* Array of pointers to other */
-                         /* ACPI tables */
+struct rsdt_descriptor_rev1 {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        u32 table_offset_entry[1];      /* Array of pointers to ACPI tables */
 };
 
-
 /*
  * ACPI 1.0 Firmware ACPI Control Structure (FACS)
  */
-struct facs_descriptor_rev1
-{
-        char                            signature[4];           /* ACPI Signature */
-        u32                             length;                 /* Length of structure, in bytes */
-        u32                             hardware_signature;     /* Hardware configuration signature */
-        u32                             firmware_waking_vector; /* ACPI OS waking vector */
-        u32                             global_lock;            /* Global Lock */
-        u32                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
-        u32                             reserved1       : 31;   /* Must be 0 */
-        u8                              resverved3 [40];        /* Reserved - must be zero */
-};
+struct facs_descriptor_rev1 {
+        char signature[4];      /* ASCII table signature */
+        u32 length;             /* Length of structure in bytes */
+        u32 hardware_signature; /* Hardware configuration signature */
+        u32 firmware_waking_vector;     /* ACPI OS waking vector */
+        u32 global_lock;        /* Global Lock */
+
+        /* Flags (32 bits) */
 
+        u8 S4bios_f:1;          /* 00:    S4BIOS support is present */
+         u8:7;                  /* 01-07: Reserved, must be zero */
+        u8 reserved1[3];        /* 08-31: Reserved, must be zero */
+
+        u8 reserved2[40];       /* Reserved, must be zero */
+};
 
 /*
  * ACPI 1.0 Fixed ACPI Description Table (FADT)
  */
-struct fadt_descriptor_rev1
-{
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-        u32                             firmware_ctrl;          /* Physical address of FACS */
-        u32                             dsdt;                   /* Physical address of DSDT */
-        u8                              model;                  /* System Interrupt Model */
-        u8                              reserved1;              /* Reserved */
-        u16                             sci_int;                /* System vector of SCI interrupt */
-        u32                             smi_cmd;                /* Port address of SMI command port */
-        u8                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
-        u8                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
-        u8                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
-        u8                              reserved2;              /* Reserved - must be zero */
-        u32                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
-        u32                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
-        u32                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
-        u32                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
-        u32                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
-        u32                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
-        u32                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
-        u32                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
-        u8                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
-        u8                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
-        u8                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
-        u8                              pm_tm_len;              /* Byte Length of ports at pm_tm_blk */
-        u8                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
-        u8                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
-        u8                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
-        u8                              reserved3;              /* Reserved */
-        u16                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
-        u16                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
-        u16                             flush_size;             /* Size of area read to flush caches */
-        u16                             flush_stride;           /* Stride used in flushing caches */
-        u8                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
-        u8                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
-        u8                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
-        u8                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
-        u8                              century;                /* Index to century in RTC CMOS RAM */
-        u8                              reserved4;              /* Reserved */
-        u8                              reserved4a;             /* Reserved */
-        u8                              reserved4b;             /* Reserved */
-        u32                             wb_invd         : 1;    /* The wbinvd instruction works properly */
-        u32                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
-        u32                             proc_c1         : 1;    /* All processors support C1 state */
-        u32                             plvl2_up        : 1;    /* C2 state works on MP system */
-        u32                             pwr_button      : 1;    /* Power button is handled as a generic feature */
-        u32                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
-        u32                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
-        u32                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
-        u32                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
-        u32                             reserved5       : 23;   /* Reserved - must be zero */
-};
+struct fadt_descriptor_rev1 {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        u32 firmware_ctrl;      /* Physical address of FACS */
+        u32 dsdt;               /* Physical address of DSDT */
+        u8 model;               /* System Interrupt Model */
+        u8 reserved1;           /* Reserved, must be zero */
+        u16 sci_int;            /* System vector of SCI interrupt */
+        u32 smi_cmd;            /* Port address of SMI command port */
+        u8 acpi_enable;         /* Value to write to smi_cmd to enable ACPI */
+        u8 acpi_disable;        /* Value to write to smi_cmd to disable ACPI */
+        u8 S4bios_req;          /* Value to write to SMI CMD to enter S4BIOS state */
+        u8 reserved2;           /* Reserved, must be zero */
+        u32 pm1a_evt_blk;       /* Port address of Power Mgt 1a acpi_event Reg Blk */
+        u32 pm1b_evt_blk;       /* Port address of Power Mgt 1b acpi_event Reg Blk */
+        u32 pm1a_cnt_blk;       /* Port address of Power Mgt 1a Control Reg Blk */
+        u32 pm1b_cnt_blk;       /* Port address of Power Mgt 1b Control Reg Blk */
+        u32 pm2_cnt_blk;        /* Port address of Power Mgt 2 Control Reg Blk */
+        u32 pm_tmr_blk;         /* Port address of Power Mgt Timer Ctrl Reg Blk */
+        u32 gpe0_blk;           /* Port addr of General Purpose acpi_event 0 Reg Blk */
+        u32 gpe1_blk;           /* Port addr of General Purpose acpi_event 1 Reg Blk */
+        u8 pm1_evt_len;         /* Byte length of ports at pm1_x_evt_blk */
+        u8 pm1_cnt_len;         /* Byte length of ports at pm1_x_cnt_blk */
+        u8 pm2_cnt_len;         /* Byte Length of ports at pm2_cnt_blk */
+        u8 pm_tm_len;           /* Byte Length of ports at pm_tm_blk */
+        u8 gpe0_blk_len;        /* Byte Length of ports at gpe0_blk */
+        u8 gpe1_blk_len;        /* Byte Length of ports at gpe1_blk */
+        u8 gpe1_base;           /* Offset in gpe model where gpe1 events start */
+        u8 reserved3;           /* Reserved, must be zero */
+        u16 plvl2_lat;          /* Worst case HW latency to enter/exit C2 state */
+        u16 plvl3_lat;          /* Worst case HW latency to enter/exit C3 state */
+        u16 flush_size;         /* Size of area read to flush caches */
+        u16 flush_stride;       /* Stride used in flushing caches */
+        u8 duty_offset;         /* Bit location of duty cycle field in p_cnt reg */
+        u8 duty_width;          /* Bit width of duty cycle field in p_cnt reg */
+        u8 day_alrm;            /* Index to day-of-month alarm in RTC CMOS RAM */
+        u8 mon_alrm;            /* Index to month-of-year alarm in RTC CMOS RAM */
+        u8 century;             /* Index to century in RTC CMOS RAM */
+        u8 reserved4[3];        /* Reserved, must be zero */
 
-#pragma pack()
+        /* Flags (32 bits) */
 
-#endif /* __ACTBL1_H__ */
+        u8 wb_invd:1;           /* 00:    The wbinvd instruction works properly */
+        u8 wb_invd_flush:1;     /* 01:    The wbinvd flushes but does not invalidate */
+        u8 proc_c1:1;           /* 02:    All processors support C1 state */
+        u8 plvl2_up:1;          /* 03:    C2 state works on MP system */
+        u8 pwr_button:1;        /* 04:    Power button is handled as a generic feature */
+        u8 sleep_button:1;      /* 05:    Sleep button is handled as a generic feature, or not present */
+        u8 fixed_rTC:1;         /* 06:    RTC wakeup stat not in fixed register space */
+        u8 rtcs4:1;             /* 07:    RTC wakeup stat not possible from S4 */
+        u8 tmr_val_ext:1;       /* 08:    tmr_val width is 32 bits (0 = 24 bits) */
+         u8:7;                  /* 09-15: Reserved, must be zero */
+        u8 reserved5[2];        /* 16-31: Reserved, must be zero */
+};
 
+#pragma pack()
 
+#endif                          /* __ACTBL1_H__ */
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index e1729c967e05..50305ce2681a 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -64,62 +64,56 @@
 #define FADT2_REVISION_ID               3
 #define FADT2_MINUS_REVISION_ID         2
 
-
 #pragma pack(1)
 
 /*
  * ACPI 2.0 Root System Description Table (RSDT)
  */
-struct rsdt_descriptor_rev2
-{
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-        u32                             table_offset_entry [1]; /* Array of pointers to  */
-                         /* ACPI table headers */
+struct rsdt_descriptor_rev2 {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        u32 table_offset_entry[1];      /* Array of pointers to ACPI tables */
 };
 
-
 /*
  * ACPI 2.0 Extended System Description Table (XSDT)
  */
-struct xsdt_descriptor_rev2
-{
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-        u64                             table_offset_entry [1]; /* Array of pointers to  */
-                         /* ACPI table headers */
+struct xsdt_descriptor_rev2 {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        u64 table_offset_entry[1];      /* Array of pointers to ACPI tables */
 };
 
-
 /*
  * ACPI 2.0 Firmware ACPI Control Structure (FACS)
  */
-struct facs_descriptor_rev2
-{
-        char                            signature[4];           /* ACPI signature */
-        u32                             length;                 /* Length of structure, in bytes */
-        u32                             hardware_signature;     /* Hardware configuration signature */
-        u32                             firmware_waking_vector; /* 32bit physical address of the Firmware Waking Vector. */
-        u32                             global_lock;            /* Global Lock used to synchronize access to shared hardware resources */
-        u32                             S4bios_f        : 1;    /* S4Bios_f - Indicates if S4BIOS support is present */
-        u32                             reserved1       : 31;   /* Must be 0 */
-        u64                             xfirmware_waking_vector; /* 64bit physical address of the Firmware Waking Vector. */
-        u8                              version;                /* Version of this table */
-        u8                              reserved3 [31];         /* Reserved - must be zero */
+struct facs_descriptor_rev2 {
+        char signature[4];      /* ASCII table signature */
+        u32 length;             /* Length of structure, in bytes */
+        u32 hardware_signature; /* Hardware configuration signature */
+        u32 firmware_waking_vector;     /* 32-bit physical address of the Firmware Waking Vector. */
+        u32 global_lock;        /* Global Lock used to synchronize access to shared hardware resources */
+
+        /* Flags (32 bits) */
+
+        u8 S4bios_f:1;          /* 00:    S4BIOS support is present */
+         u8:7;                  /* 01-07: Reserved, must be zero */
+        u8 reserved1[3];        /* 08-31: Reserved, must be zero */
+
+        u64 xfirmware_waking_vector;    /* 64-bit physical address of the Firmware Waking Vector. */
+        u8 version;             /* Version of this table */
+        u8 reserved3[31];       /* Reserved, must be zero */
 };
 
-
 /*
  * ACPI 2.0+ Generic Address Structure (GAS)
  */
-struct acpi_generic_address
-{
-        u8                              address_space_id;       /* Address space where struct or register exists. */
-        u8                              register_bit_width;     /* Size in bits of given register */
-        u8                              register_bit_offset;    /* Bit offset within the register */
-        u8                              access_width;           /* Minimum Access size (ACPI 3.0) */
-        u64                             address;                /* 64-bit address of struct or register */
+struct acpi_generic_address {
+        u8 address_space_id;    /* Address space where struct or register exists. */
+        u8 register_bit_width;  /* Size in bits of given register */
+        u8 register_bit_offset; /* Bit offset within the register */
+        u8 access_width;        /* Minimum Access size (ACPI 3.0) */
+        u64 address;            /* 64-bit address of struct or register */
 };
 
-
 #define FADT_REV2_COMMON \
         u32                             V1_firmware_ctrl;   /* 32-bit physical address of FACS */ \
         u32                             V1_dsdt;            /* 32-bit physical address of DSDT */ \
@@ -161,129 +155,123 @@ struct acpi_generic_address
 /*
  * ACPI 2.0+ Fixed ACPI Description Table (FADT)
  */
-struct fadt_descriptor_rev2
-{
-        ACPI_TABLE_HEADER_DEF                       /* ACPI common table header */
-        FADT_REV2_COMMON
-        u8                              reserved2;          /* Reserved */
-        u32                             wb_invd     : 1;    /* The wbinvd instruction works properly */
-        u32                             wb_invd_flush : 1;  /* The wbinvd flushes but does not invalidate */
-        u32                             proc_c1     : 1;    /* All processors support C1 state */
-        u32                             plvl2_up    : 1;    /* C2 state works on MP system */
-        u32                             pwr_button  : 1;    /* Power button is handled as a generic feature */
-        u32                             sleep_button : 1;   /* Sleep button is handled as a generic feature, or not present */
-        u32                             fixed_rTC   : 1;    /* RTC wakeup stat not in fixed register space */
-        u32                             rtcs4       : 1;    /* RTC wakeup stat not possible from S4 */
-        u32                             tmr_val_ext : 1;    /* Indicates tmr_val is 32 bits 0=24-bits */
-        u32                             dock_cap    : 1;    /* Supports Docking */
-        u32                             reset_reg_sup : 1;  /* Indicates system supports system reset via the FADT RESET_REG */
-        u32                             sealed_case : 1;    /* Indicates system has no internal expansion capabilities and case is sealed */
-        u32                             headless    : 1;    /* Indicates system does not have local video capabilities or local input devices */
-        u32                             cpu_sw_sleep : 1;   /* Indicates to OSPM that a processor native instruction */
-                           /* must be executed after writing the SLP_TYPx register */
-        /* ACPI 3.0 flag bits */
-
-        u32                             pci_exp_wak                         : 1; /* System supports PCIEXP_WAKE (STS/EN) bits */
-        u32                             use_platform_clock                  : 1; /* OSPM should use platform-provided timer */
-        u32                             S4rtc_sts_valid                     : 1; /* Contents of RTC_STS valid after S4 wake */
-        u32                             remote_power_on_capable             : 1; /* System is compatible with remote power on */
-        u32                             force_apic_cluster_model            : 1; /* All local APICs must use cluster model */
-        u32                             force_apic_physical_destination_mode : 1; /* all local x_aPICs must use physical dest mode */
-        u32                             reserved6                           : 12;/* Reserved - must be zero */
-
-        struct acpi_generic_address     reset_register;     /* Reset register address in GAS format */
-        u8                              reset_value;        /* Value to write to the reset_register port to reset the system */
-        u8                              reserved7[3];       /* These three bytes must be zero */
-        u64                             xfirmware_ctrl;     /* 64-bit physical address of FACS */
-        u64                             Xdsdt;              /* 64-bit physical address of DSDT */
-        struct acpi_generic_address     xpm1a_evt_blk;      /* Extended Power Mgt 1a acpi_event Reg Blk address */
-        struct acpi_generic_address     xpm1b_evt_blk;      /* Extended Power Mgt 1b acpi_event Reg Blk address */
-        struct acpi_generic_address     xpm1a_cnt_blk;      /* Extended Power Mgt 1a Control Reg Blk address */
-        struct acpi_generic_address     xpm1b_cnt_blk;      /* Extended Power Mgt 1b Control Reg Blk address */
-        struct acpi_generic_address     xpm2_cnt_blk;       /* Extended Power Mgt 2 Control Reg Blk address */
-        struct acpi_generic_address     xpm_tmr_blk;        /* Extended Power Mgt Timer Ctrl Reg Blk address */
-        struct acpi_generic_address     xgpe0_blk;          /* Extended General Purpose acpi_event 0 Reg Blk address */
-        struct acpi_generic_address     xgpe1_blk;          /* Extended General Purpose acpi_event 1 Reg Blk address */
+struct fadt_descriptor_rev2 {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        FADT_REV2_COMMON u8 reserved2;  /* Reserved, must be zero */
+
+        /* Flags (32 bits) */
+
+        u8 wb_invd:1;           /* 00:    The wbinvd instruction works properly */
+        u8 wb_invd_flush:1;     /* 01:    The wbinvd flushes but does not invalidate */
+        u8 proc_c1:1;           /* 02:    All processors support C1 state */
+        u8 plvl2_up:1;          /* 03:    C2 state works on MP system */
+        u8 pwr_button:1;        /* 04:    Power button is handled as a generic feature */
+        u8 sleep_button:1;      /* 05:    Sleep button is handled as a generic feature, or not present */
+        u8 fixed_rTC:1;         /* 06:    RTC wakeup stat not in fixed register space */
+        u8 rtcs4:1;             /* 07:    RTC wakeup stat not possible from S4 */
+        u8 tmr_val_ext:1;       /* 08:    tmr_val is 32 bits 0=24-bits */
+        u8 dock_cap:1;          /* 09:    Docking supported */
+        u8 reset_reg_sup:1;     /* 10:    System reset via the FADT RESET_REG supported */
+        u8 sealed_case:1;       /* 11:    No internal expansion capabilities and case is sealed */
+        u8 headless:1;          /* 12:    No local video capabilities or local input devices */
+        u8 cpu_sw_sleep:1;      /* 13:    Must execute native instruction after writing SLP_TYPx register */
+
+        u8 pci_exp_wak:1;       /* 14:    System supports PCIEXP_WAKE (STS/EN) bits (ACPI 3.0) */
+        u8 use_platform_clock:1;        /* 15:    OSPM should use platform-provided timer (ACPI 3.0) */
+        u8 S4rtc_sts_valid:1;   /* 16:    Contents of RTC_STS valid after S4 wake (ACPI 3.0) */
+        u8 remote_power_on_capable:1;   /* 17:    System is compatible with remote power on (ACPI 3.0) */
+        u8 force_apic_cluster_model:1;  /* 18:    All local APICs must use cluster model (ACPI 3.0) */
+        u8 force_apic_physical_destination_mode:1;      /* 19:   all local x_aPICs must use physical dest mode (ACPI 3.0) */
+         u8:4;                  /* 20-23: Reserved, must be zero */
+        u8 reserved3;           /* 24-31: Reserved, must be zero */
+
+        struct acpi_generic_address reset_register;     /* Reset register address in GAS format */
+        u8 reset_value;         /* Value to write to the reset_register port to reset the system */
+        u8 reserved4[3];        /* These three bytes must be zero */
+        u64 xfirmware_ctrl;     /* 64-bit physical address of FACS */
+        u64 Xdsdt;              /* 64-bit physical address of DSDT */
+        struct acpi_generic_address xpm1a_evt_blk;      /* Extended Power Mgt 1a acpi_event Reg Blk address */
+        struct acpi_generic_address xpm1b_evt_blk;      /* Extended Power Mgt 1b acpi_event Reg Blk address */
+        struct acpi_generic_address xpm1a_cnt_blk;      /* Extended Power Mgt 1a Control Reg Blk address */
+        struct acpi_generic_address xpm1b_cnt_blk;      /* Extended Power Mgt 1b Control Reg Blk address */
+        struct acpi_generic_address xpm2_cnt_blk;       /* Extended Power Mgt 2 Control Reg Blk address */
+        struct acpi_generic_address xpm_tmr_blk;        /* Extended Power Mgt Timer Ctrl Reg Blk address */
+        struct acpi_generic_address xgpe0_blk;  /* Extended General Purpose acpi_event 0 Reg Blk address */
+        struct acpi_generic_address xgpe1_blk;  /* Extended General Purpose acpi_event 1 Reg Blk address */
 };
 
-
 /* "Down-revved" ACPI 2.0 FADT descriptor */
 
-struct fadt_descriptor_rev2_minus
-{
-        ACPI_TABLE_HEADER_DEF                       /* ACPI common table header */
-        FADT_REV2_COMMON
-        u8                              reserved2;          /* Reserved */
-        u32                             flags;
-        struct acpi_generic_address     reset_register;     /* Reset register address in GAS format */
-        u8                              reset_value;        /* Value to write to the reset_register port to reset the system. */
-        u8                              reserved7[3];       /* These three bytes must be zero */
+struct fadt_descriptor_rev2_minus {
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
+        FADT_REV2_COMMON u8 reserved2;  /* Reserved, must be zero */
+        u32 flags;
+        struct acpi_generic_address reset_register;     /* Reset register address in GAS format */
+        u8 reset_value;         /* Value to write to the reset_register port to reset the system. */
+        u8 reserved7[3];        /* Reserved, must be zero */
 };
 
-
 /* ECDT - Embedded Controller Boot Resources Table */
 
-struct ec_boot_resources
-{
-        ACPI_TABLE_HEADER_DEF
-        struct acpi_generic_address     ec_control;         /* Address of EC command/status register */
-        struct acpi_generic_address     ec_data;            /* Address of EC data register */
-        u32                             uid;                /* Unique ID - must be same as the EC _UID method */
-        u8                              gpe_bit;            /* The GPE for the EC */
-        u8                              ec_id[1];           /* Full namepath of the EC in the ACPI namespace */
+struct ec_boot_resources {
+        ACPI_TABLE_HEADER_DEF struct acpi_generic_address ec_control;   /* Address of EC command/status register */
+        struct acpi_generic_address ec_data;    /* Address of EC data register */
+        u32 uid;                /* Unique ID - must be same as the EC _UID method */
+        u8 gpe_bit;             /* The GPE for the EC */
+        u8 ec_id[1];            /* Full namepath of the EC in the ACPI namespace */
 };
 
-
 /* SRAT - System Resource Affinity Table */
 
-struct static_resource_alloc
-{
-        u8                              type;
-        u8                              length;
-        u8                              proximity_domain_lo;
-        u8                              apic_id;
-        u32                             enabled         :1;
-        u32                             reserved3       :31;
-        u8                              local_sapic_eid;
-        u8                              proximity_domain_hi[3];
-        u32                             reserved4;
-};
+struct static_resource_alloc {
+        u8 type;
+        u8 length;
+        u8 proximity_domain_lo;
+        u8 apic_id;
 
-struct memory_affinity
-{
-        u8                              type;
-        u8                              length;
-        u32                             proximity_domain;
-        u16                             reserved3;
-        u64                             base_address;
-        u64                             address_length;
-        u32                             reserved4;
-        u32                             enabled         :1;
-        u32                             hot_pluggable   :1;
-        u32                             non_volatile    :1;
-        u32                             reserved5       :29;
-        u64                             reserved6;
+        /* Flags (32 bits) */
+
+        u8 enabled:1;           /* 00:    Use affinity structure */
+         u8:7;                  /* 01-07: Reserved, must be zero */
+        u8 reserved3[3];        /* 08-31: Reserved, must be zero */
+
+        u8 local_sapic_eid;
+        u8 proximity_domain_hi[3];
+        u32 reserved4;          /* Reserved, must be zero */
 };
 
-struct system_resource_affinity
-{
-        ACPI_TABLE_HEADER_DEF
-        u32                             reserved1;          /* Must be value '1' */
-        u64                             reserved2;
+struct memory_affinity {
+        u8 type;
+        u8 length;
+        u32 proximity_domain;
+        u16 reserved3;
+        u64 base_address;
+        u64 address_length;
+        u32 reserved4;
+
+        /* Flags (32 bits) */
+
+        u8 enabled:1;           /* 00:    Use affinity structure */
+        u8 hot_pluggable:1;     /* 01:    Memory region is hot pluggable */
+        u8 non_volatile:1;      /* 02:    Memory is non-volatile */
+         u8:5;                  /* 03-07: Reserved, must be zero */
+        u8 reserved5[3];        /* 08-31: Reserved, must be zero */
+
+        u64 reserved6;          /* Reserved, must be zero */
 };
 
+struct system_resource_affinity {
+        ACPI_TABLE_HEADER_DEF u32 reserved1;    /* Must be value '1' */
+        u64 reserved2;          /* Reserved, must be zero */
+};
 
 /* SLIT - System Locality Distance Information Table */
 
-struct system_locality_info
-{
-        ACPI_TABLE_HEADER_DEF
-        u64                             locality_count;
-        u8                              entry[1][1];
+struct system_locality_info {
+        ACPI_TABLE_HEADER_DEF u64 locality_count;
+        u8 entry[1][1];
 };
 
-
 #pragma pack()
 
-#endif /* __ACTBL2_H__ */
-
+#endif                          /* __ACTBL2_H__ */
diff --git a/include/acpi/actbl71.h b/include/acpi/actbl71.h
index 7b4fb44261f3..10ac05bb36bc 100644
--- a/include/acpi/actbl71.h
+++ b/include/acpi/actbl71.h
@@ -27,7 +27,6 @@
 #ifndef __ACTBL71_H__
 #define __ACTBL71_H__
 
-
 /* 0.71 FADT address_space data item bitmasks defines */
 /* If the associated bit is zero then it is in memory space else in io space */
 
@@ -40,105 +39,96 @@
 
 /* Only for clarity in declarations */
 
-typedef u64                         IO_ADDRESS;
-
+typedef u64 IO_ADDRESS;
 
 #pragma pack(1)
-struct  /* Root System Descriptor Pointer */
-{
-        NATIVE_CHAR             signature [8];          /* contains "RSD PTR " */
-        u8                              checksum;               /* to make sum of struct == 0 */
-        NATIVE_CHAR             oem_id [6];             /* OEM identification */
-        u8                              reserved;               /* Must be 0 for 1.0, 2 for 2.0 */
-        u64                             rsdt_physical_address;  /* 64-bit physical address of RSDT */
+struct {                        /* Root System Descriptor Pointer */
+        NATIVE_CHAR signature[8];       /* contains "RSD PTR " */
+        u8 checksum;            /* to make sum of struct == 0 */
+        NATIVE_CHAR oem_id[6];  /* OEM identification */
+        u8 reserved;            /* Must be 0 for 1.0, 2 for 2.0 */
+        u64 rsdt_physical_address;      /* 64-bit physical address of RSDT */
 };
 
-
 /*****************************************/
 /* IA64 Extensions to ACPI Spec Rev 0.71 */
 /* for the Root System Description Table */
 /*****************************************/
-struct
-{
-        struct acpi_table_header    header;                 /* Table header */
-        u32                         reserved_pad;           /* IA64 alignment, must be 0 */
-        u64                         table_offset_entry [1]; /* Array of pointers to other */
-                           /* tables' headers */
+struct {
+        struct acpi_table_header header;        /* Table header */
+        u32 reserved_pad;       /* IA64 alignment, must be 0 */
+        u64 table_offset_entry[1];      /* Array of pointers to other */
+        /* tables' headers */
 };
 
-
 /*******************************************/
 /* IA64 Extensions to ACPI Spec Rev 0.71   */
 /* for the Firmware ACPI Control Structure */
 /*******************************************/
-struct
-{
-        NATIVE_CHAR         signature[4];         /* signature "FACS" */
-        u32                         length;               /* length of structure, in bytes */
-        u32                         hardware_signature;   /* hardware configuration signature */
-        u32                         reserved4;            /* must be 0 */
-        u64                         firmware_waking_vector; /* ACPI OS waking vector */
-        u64                         global_lock;          /* Global Lock */
-        u32                         S4bios_f      : 1;    /* Indicates if S4BIOS support is present */
-        u32                         reserved1     : 31;   /* must be 0 */
-        u8                          reserved3 [28];       /* reserved - must be zero */
+struct {
+        NATIVE_CHAR signature[4];       /* signature "FACS" */
+        u32 length;             /* length of structure, in bytes */
+        u32 hardware_signature; /* hardware configuration signature */
+        u32 reserved4;          /* must be 0 */
+        u64 firmware_waking_vector;     /* ACPI OS waking vector */
+        u64 global_lock;        /* Global Lock */
+        u32 S4bios_f:1;         /* Indicates if S4BIOS support is present */
+        u32 reserved1:31;       /* must be 0 */
+        u8 reserved3[28];       /* reserved - must be zero */
 };
 
-
 /******************************************/
 /* IA64 Extensions to ACPI Spec Rev 0.71  */
 /* for the Fixed ACPI Description Table   */
 /******************************************/
-struct
-{
-        struct acpi_table_header    header;             /* table header */
-        u32                         reserved_pad;       /* IA64 alignment, must be 0 */
-        u64                         firmware_ctrl;      /* 64-bit Physical address of FACS */
-        u64                         dsdt;               /* 64-bit Physical address of DSDT */
-        u8                          model;              /* System Interrupt Model */
-        u8                          address_space;      /* Address Space Bitmask */
-        u16                         sci_int;            /* System vector of SCI interrupt */
-        u8                          acpi_enable;        /* value to write to smi_cmd to enable ACPI */
-        u8                          acpi_disable;       /* value to write to smi_cmd to disable ACPI */
-        u8                          S4bios_req;         /* Value to write to SMI CMD to enter S4BIOS state */
-        u8                          reserved2;          /* reserved - must be zero */
-        u64                         smi_cmd;            /* Port address of SMI command port */
-        u64                         pm1a_evt_blk;       /* Port address of Power Mgt 1a acpi_event Reg Blk */
-        u64                         pm1b_evt_blk;       /* Port address of Power Mgt 1b acpi_event Reg Blk */
-        u64                         pm1a_cnt_blk;       /* Port address of Power Mgt 1a Control Reg Blk */
-        u64                         pm1b_cnt_blk;       /* Port address of Power Mgt 1b Control Reg Blk */
-        u64                         pm2_cnt_blk;        /* Port address of Power Mgt 2 Control Reg Blk */
-        u64                         pm_tmr_blk;         /* Port address of Power Mgt Timer Ctrl Reg Blk */
-        u64                         gpe0_blk;           /* Port addr of General Purpose acpi_event 0 Reg Blk */
-        u64                         gpe1_blk;           /* Port addr of General Purpose acpi_event 1 Reg Blk */
-        u8                          pm1_evt_len;        /* Byte length of ports at pm1_x_evt_blk */
-        u8                          pm1_cnt_len;        /* Byte length of ports at pm1_x_cnt_blk */
-        u8                          pm2_cnt_len;        /* Byte Length of ports at pm2_cnt_blk */
-        u8                          pm_tm_len;          /* Byte Length of ports at pm_tm_blk */
-        u8                          gpe0_blk_len;       /* Byte Length of ports at gpe0_blk */
-        u8                          gpe1_blk_len;       /* Byte Length of ports at gpe1_blk */
-        u8                          gpe1_base;          /* offset in gpe model where gpe1 events start */
-        u8                          reserved3;          /* reserved */
-        u16                         plvl2_lat;          /* worst case HW latency to enter/exit C2 state */
-        u16                         plvl3_lat;          /* worst case HW latency to enter/exit C3 state */
-        u8                          day_alrm;           /* index to day-of-month alarm in RTC CMOS RAM */
-        u8                          mon_alrm;           /* index to month-of-year alarm in RTC CMOS RAM */
-        u8                          century;            /* index to century in RTC CMOS RAM */
-        u8                          reserved4;          /* reserved */
-        u32                         flush_cash  : 1;    /* PAL_FLUSH_CACHE is correctly supported */
-        u32                         reserved5   : 1;    /* reserved - must be zero */
-        u32                         proc_c1     : 1;    /* all processors support C1 state */
-        u32                         plvl2_up    : 1;    /* C2 state works on MP system */
-        u32                         pwr_button  : 1;    /* Power button is handled as a generic feature */
-        u32                         sleep_button : 1;   /* Sleep button is handled as a generic feature, or not present */
-        u32                         fixed_rTC   : 1;    /* RTC wakeup stat not in fixed register space */
-        u32                         rtcs4       : 1;    /* RTC wakeup stat not possible from S4 */
-        u32                         tmr_val_ext : 1;    /* tmr_val is 32 bits */
-        u32                         dock_cap    : 1;    /* Supports Docking */
-        u32                         reserved6   : 22;    /* reserved - must be zero */
+struct {
+        struct acpi_table_header header;        /* table header */
+        u32 reserved_pad;       /* IA64 alignment, must be 0 */
+        u64 firmware_ctrl;      /* 64-bit Physical address of FACS */
+        u64 dsdt;               /* 64-bit Physical address of DSDT */
+        u8 model;               /* System Interrupt Model */
+        u8 address_space;       /* Address Space Bitmask */
+        u16 sci_int;            /* System vector of SCI interrupt */
+        u8 acpi_enable;         /* value to write to smi_cmd to enable ACPI */
+        u8 acpi_disable;        /* value to write to smi_cmd to disable ACPI */
+        u8 S4bios_req;          /* Value to write to SMI CMD to enter S4BIOS state */
+        u8 reserved2;           /* reserved - must be zero */
+        u64 smi_cmd;            /* Port address of SMI command port */
+        u64 pm1a_evt_blk;       /* Port address of Power Mgt 1a acpi_event Reg Blk */
+        u64 pm1b_evt_blk;       /* Port address of Power Mgt 1b acpi_event Reg Blk */
+        u64 pm1a_cnt_blk;       /* Port address of Power Mgt 1a Control Reg Blk */
+        u64 pm1b_cnt_blk;       /* Port address of Power Mgt 1b Control Reg Blk */
+        u64 pm2_cnt_blk;        /* Port address of Power Mgt 2 Control Reg Blk */
+        u64 pm_tmr_blk;         /* Port address of Power Mgt Timer Ctrl Reg Blk */
+        u64 gpe0_blk;           /* Port addr of General Purpose acpi_event 0 Reg Blk */
+        u64 gpe1_blk;           /* Port addr of General Purpose acpi_event 1 Reg Blk */
+        u8 pm1_evt_len;         /* Byte length of ports at pm1_x_evt_blk */
+        u8 pm1_cnt_len;         /* Byte length of ports at pm1_x_cnt_blk */
+        u8 pm2_cnt_len;         /* Byte Length of ports at pm2_cnt_blk */
+        u8 pm_tm_len;           /* Byte Length of ports at pm_tm_blk */
+        u8 gpe0_blk_len;        /* Byte Length of ports at gpe0_blk */
+        u8 gpe1_blk_len;        /* Byte Length of ports at gpe1_blk */
+        u8 gpe1_base;           /* offset in gpe model where gpe1 events start */
+        u8 reserved3;           /* reserved */
+        u16 plvl2_lat;          /* worst case HW latency to enter/exit C2 state */
+        u16 plvl3_lat;          /* worst case HW latency to enter/exit C3 state */
+        u8 day_alrm;            /* index to day-of-month alarm in RTC CMOS RAM */
+        u8 mon_alrm;            /* index to month-of-year alarm in RTC CMOS RAM */
+        u8 century;             /* index to century in RTC CMOS RAM */
+        u8 reserved4;           /* reserved */
+        u32 flush_cash:1;       /* PAL_FLUSH_CACHE is correctly supported */
+        u32 reserved5:1;        /* reserved - must be zero */
+        u32 proc_c1:1;          /* all processors support C1 state */
+        u32 plvl2_up:1;         /* C2 state works on MP system */
+        u32 pwr_button:1;       /* Power button is handled as a generic feature */
+        u32 sleep_button:1;     /* Sleep button is handled as a generic feature, or not present */
+        u32 fixed_rTC:1;        /* RTC wakeup stat not in fixed register space */
+        u32 rtcs4:1;            /* RTC wakeup stat not possible from S4 */
+        u32 tmr_val_ext:1;      /* tmr_val is 32 bits */
+        u32 dock_cap:1;         /* Supports Docking */
+        u32 reserved6:22;       /* reserved - must be zero */
 };
 
 #pragma pack()
 
-#endif /* __ACTBL71_H__ */
-
+#endif                          /* __ACTBL71_H__ */
diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index 7acb550af3eb..6213b27516e8 100644
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -46,35 +46,31 @@
 
 /*! [Begin] no source code translation (keep the typedefs) */
 
-
-
 /*
  * Data type ranges
  * Note: These macros are designed to be compiler independent as well as
  * working around problems that some 32-bit compilers have with 64-bit
  * constants.
  */
-#define ACPI_UINT8_MAX                  (UINT8) (~((UINT8)  0)) /* 0xFF               */
-#define ACPI_UINT16_MAX                 (UINT16)(~((UINT16) 0)) /* 0xFFFF             */
-#define ACPI_UINT32_MAX                 (UINT32)(~((UINT32) 0)) /* 0xFFFFFFFF         */
-#define ACPI_UINT64_MAX                 (UINT64)(~((UINT64) 0)) /* 0xFFFFFFFFFFFFFFFF */
+#define ACPI_UINT8_MAX                  (UINT8) (~((UINT8)  0)) /* 0xFF               */
+#define ACPI_UINT16_MAX                 (UINT16)(~((UINT16) 0)) /* 0xFFFF             */
+#define ACPI_UINT32_MAX                 (UINT32)(~((UINT32) 0)) /* 0xFFFFFFFF         */
+#define ACPI_UINT64_MAX                 (UINT64)(~((UINT64) 0)) /* 0xFFFFFFFFFFFFFFFF */
 #define ACPI_ASCII_MAX                  0x7F
 
-
 #ifdef DEFINE_ALTERNATE_TYPES
 /*
  * Types used only in translated source, defined here to enable
  * cross-platform compilation only.
  */
-typedef int                             s32;
-typedef unsigned char                   u8;
-typedef unsigned short                  u16;
-typedef unsigned int                    u32;
-typedef COMPILER_DEPENDENT_UINT64       u64;
+typedef int s32;
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef COMPILER_DEPENDENT_UINT64 u64;
 
 #endif
 
-
 /*
  * Data types - Fixed across all compilation models (16/32/64)
  *
@@ -102,30 +98,29 @@ typedef COMPILER_DEPENDENT_UINT64       u64;
 /*
  * 64-bit type definitions
  */
-typedef unsigned char                   UINT8;
-typedef unsigned char                   BOOLEAN;
-typedef unsigned short                  UINT16;
-typedef int                             INT32;
-typedef unsigned int                    UINT32;
-typedef COMPILER_DEPENDENT_INT64        INT64;
-typedef COMPILER_DEPENDENT_UINT64       UINT64;
+typedef unsigned char UINT8;
+typedef unsigned char BOOLEAN;
+typedef unsigned short UINT16;
+typedef int INT32;
+typedef unsigned int UINT32;
+typedef COMPILER_DEPENDENT_INT64 INT64;
+typedef COMPILER_DEPENDENT_UINT64 UINT64;
 
 /*! [End] no source code translation !*/
 
-typedef s64                                     acpi_native_int;
-typedef u64                                     acpi_native_uint;
+typedef s64 acpi_native_int;
+typedef u64 acpi_native_uint;
 
-typedef u64                                     acpi_table_ptr;
-typedef u64                                     acpi_io_address;
-typedef u64                                     acpi_physical_address;
-typedef u64                                     acpi_size;
+typedef u64 acpi_table_ptr;
+typedef u64 acpi_io_address;
+typedef u64 acpi_physical_address;
+typedef u64 acpi_size;
 
-#define ALIGNED_ADDRESS_BOUNDARY        0x00000008      /* No hardware alignment support in IA64 */
-#define ACPI_USE_NATIVE_DIVIDE                          /* Native 64-bit integer support */
+#define ALIGNED_ADDRESS_BOUNDARY        0x00000008      /* No hardware alignment support in IA64 */
+#define ACPI_USE_NATIVE_DIVIDE  /* Native 64-bit integer support */
 #define ACPI_MAX_PTR                    ACPI_UINT64_MAX
 #define ACPI_SIZE_MAX                   ACPI_UINT64_MAX
 
-
 #elif ACPI_MACHINE_WIDTH == 16
 
 /*! [Begin] no source code translation (keep the typedefs) */
@@ -133,32 +128,31 @@ typedef u64                                     acpi_size;
 /*
  * 16-bit type definitions
  */
-typedef unsigned char                   UINT8;
-typedef unsigned char                   BOOLEAN;
-typedef unsigned int                    UINT16;
-typedef long                            INT32;
-typedef int                             INT16;
-typedef unsigned long                   UINT32;
-
-struct
-{
-        UINT32                                  Lo;
-        UINT32                                  Hi;
+typedef unsigned char UINT8;
+typedef unsigned char BOOLEAN;
+typedef unsigned int UINT16;
+typedef long INT32;
+typedef int INT16;
+typedef unsigned long UINT32;
+
+struct {
+        UINT32 Lo;
+        UINT32 Hi;
 };
 
 /*! [End] no source code translation !*/
 
-typedef u16                                     acpi_native_uint;
-typedef s16                                     acpi_native_int;
+typedef u16 acpi_native_uint;
+typedef s16 acpi_native_int;
 
-typedef u32                                     acpi_table_ptr;
-typedef u32                                     acpi_io_address;
-typedef char                                    *acpi_physical_address;
-typedef u16                                     acpi_size;
+typedef u32 acpi_table_ptr;
+typedef u32 acpi_io_address;
+typedef char *acpi_physical_address;
+typedef u16 acpi_size;
 
 #define ALIGNED_ADDRESS_BOUNDARY        0x00000002
 #define ACPI_MISALIGNED_TRANSFERS
-#define ACPI_USE_NATIVE_DIVIDE                          /* No 64-bit integers, ok to use native divide */
+#define ACPI_USE_NATIVE_DIVIDE  /* No 64-bit integers, ok to use native divide */
 #define ACPI_MAX_PTR                    ACPI_UINT16_MAX
 #define ACPI_SIZE_MAX                   ACPI_UINT16_MAX
 
@@ -168,7 +162,6 @@ typedef u16                                     acpi_size;
  */
 #define ACPI_NO_INTEGER64_SUPPORT
 
-
 #elif ACPI_MACHINE_WIDTH == 32
 
 /*! [Begin] no source code translation (keep the typedefs) */
@@ -176,23 +169,23 @@ typedef u16                                     acpi_size;
 /*
  * 32-bit type definitions (default)
  */
-typedef unsigned char                   UINT8;
-typedef unsigned char                   BOOLEAN;
-typedef unsigned short                  UINT16;
-typedef int                             INT32;
-typedef unsigned int                    UINT32;
-typedef COMPILER_DEPENDENT_INT64        INT64;
-typedef COMPILER_DEPENDENT_UINT64       UINT64;
+typedef unsigned char UINT8;
+typedef unsigned char BOOLEAN;
+typedef unsigned short UINT16;
+typedef int INT32;
+typedef unsigned int UINT32;
+typedef COMPILER_DEPENDENT_INT64 INT64;
+typedef COMPILER_DEPENDENT_UINT64 UINT64;
 
 /*! [End] no source code translation !*/
 
-typedef s32                                     acpi_native_int;
-typedef u32                                     acpi_native_uint;
+typedef s32 acpi_native_int;
+typedef u32 acpi_native_uint;
 
-typedef u64                                     acpi_table_ptr;
-typedef u32                                     acpi_io_address;
-typedef u64                                     acpi_physical_address;
-typedef u32                                     acpi_size;
+typedef u64 acpi_table_ptr;
+typedef u32 acpi_io_address;
+typedef u64 acpi_physical_address;
+typedef u32 acpi_size;
 
 #define ALIGNED_ADDRESS_BOUNDARY        0x00000004
 #define ACPI_MISALIGNED_TRANSFERS
@@ -203,29 +196,27 @@ typedef u32                                     acpi_size;
 #error unknown ACPI_MACHINE_WIDTH
 #endif
 
-
 /*
- * Miscellaneous common types
+ * This type is used for bitfields in ACPI tables. The only type that is
+ * even remotely portable is u8. Anything else is not portable, so
+ * do not add any more bitfield types.
  */
-typedef u16                                     UINT16_BIT;
-typedef u32                                     UINT32_BIT;
-typedef acpi_native_uint                        ACPI_PTRDIFF;
+typedef u8 UINT8_BIT;
+typedef acpi_native_uint ACPI_PTRDIFF;
 
 /*
  * Pointer overlays to avoid lots of typecasting for
  * code that accepts both physical and logical pointers.
  */
-union acpi_pointers
-{
-        acpi_physical_address               physical;
-        void                                *logical;
-        acpi_table_ptr                      value;
+union acpi_pointers {
+        acpi_physical_address physical;
+        void *logical;
+        acpi_table_ptr value;
 };
 
-struct acpi_pointer
-{
-        u32                                 pointer_type;
-        union acpi_pointers                 pointer;
+struct acpi_pointer {
+        u32 pointer_type;
+        union acpi_pointers pointer;
 };
 
 /* pointer_types for above */
@@ -243,6 +234,14 @@ struct acpi_pointer
 #define ACPI_LOGMODE_PHYSPTR            ACPI_LOGICAL_ADDRESSING  | ACPI_PHYSICAL_POINTER
 #define ACPI_LOGMODE_LOGPTR             ACPI_LOGICAL_ADDRESSING  | ACPI_LOGICAL_POINTER
 
+/*
+ * If acpi_cache_t was not defined in the OS-dependent header,
+ * define it now. This is typically the case where the local cache
+ * manager implementation is to be used (ACPI_USE_LOCAL_CACHE)
+ */
+#ifndef acpi_cache_t
+#define acpi_cache_t                            struct acpi_memory_list
+#endif
 
 /*
  * Useful defines
@@ -261,34 +260,29 @@ struct acpi_pointer
 #define NULL                            (void *) 0
 #endif
 
-
 /*
  * Local datatypes
  */
-typedef u32                                     acpi_status;    /* All ACPI Exceptions */
-typedef u32                                     acpi_name;      /* 4-byte ACPI name */
-typedef char *                                  acpi_string;    /* Null terminated ASCII string */
-typedef void *                                  acpi_handle;    /* Actually a ptr to an Node */
-
-struct uint64_struct
-{
-        u32                                 lo;
-        u32                                 hi;
+typedef u32 acpi_status;        /* All ACPI Exceptions */
+typedef u32 acpi_name;          /* 4-byte ACPI name */
+typedef char *acpi_string;      /* Null terminated ASCII string */
+typedef void *acpi_handle;      /* Actually a ptr to an Node */
+
+struct uint64_struct {
+        u32 lo;
+        u32 hi;
 };
 
-union uint64_overlay
-{
-        u64                                 full;
-        struct uint64_struct                part;
+union uint64_overlay {
+        u64 full;
+        struct uint64_struct part;
 };
 
-struct uint32_struct
-{
-        u32                                 lo;
-        u32                                 hi;
+struct uint32_struct {
+        u32 lo;
+        u32 hi;
 };
 
-
 /*
  * Acpi integer width. In ACPI version 1, integers are
  * 32 bits.  In ACPI version 2, integers are 64 bits.
@@ -300,26 +294,24 @@ struct uint32_struct
 
 /* 32-bit integers only, no 64-bit support */
 
-typedef u32                                     acpi_integer;
+typedef u32 acpi_integer;
 #define ACPI_INTEGER_MAX                ACPI_UINT32_MAX
 #define ACPI_INTEGER_BIT_SIZE           32
-#define ACPI_MAX_DECIMAL_DIGITS         10  /* 2^32 = 4,294,967,296 */
-
-#define ACPI_USE_NATIVE_DIVIDE          /* Use compiler native 32-bit divide */
+#define ACPI_MAX_DECIMAL_DIGITS         10      /* 2^32 = 4,294,967,296 */
 
+#define ACPI_USE_NATIVE_DIVIDE  /* Use compiler native 32-bit divide */
 
 #else
 
 /* 64-bit integers */
 
-typedef u64                                     acpi_integer;
+typedef u64 acpi_integer;
 #define ACPI_INTEGER_MAX                ACPI_UINT64_MAX
 #define ACPI_INTEGER_BIT_SIZE           64
-#define ACPI_MAX_DECIMAL_DIGITS         20  /* 2^64 = 18,446,744,073,709,551,616 */
-
+#define ACPI_MAX_DECIMAL_DIGITS         20      /* 2^64 = 18,446,744,073,709,551,616 */
 
 #if ACPI_MACHINE_WIDTH == 64
-#define ACPI_USE_NATIVE_DIVIDE          /* Use compiler native 64-bit divide */
+#define ACPI_USE_NATIVE_DIVIDE  /* Use compiler native 64-bit divide */
 #endif
 #endif
 
@@ -333,7 +325,6 @@ typedef u64                                     acpi_integer;
  */
 #define ACPI_ROOT_OBJECT                (acpi_handle) ACPI_PTR_ADD (char, NULL, ACPI_MAX_PTR)
 
-
 /*
  * Initialization sequence
  */
@@ -400,7 +391,7 @@ typedef u64                                     acpi_integer;
 /*
  *  Table types.  These values are passed to the table related APIs
  */
-typedef u32                                     acpi_table_type;
+typedef u32 acpi_table_type;
 
 #define ACPI_TABLE_RSDP                 (acpi_table_type) 0
 #define ACPI_TABLE_DSDT                 (acpi_table_type) 1
@@ -421,22 +412,22 @@ typedef u32                                     acpi_table_type;
  * NOTE: Types must be kept in sync with the global acpi_ns_properties
  * and acpi_ns_type_names arrays.
  */
-typedef u32                                     acpi_object_type;
+typedef u32 acpi_object_type;
 
 #define ACPI_TYPE_ANY                   0x00
-#define ACPI_TYPE_INTEGER               0x01  /* Byte/Word/Dword/Zero/One/Ones */
+#define ACPI_TYPE_INTEGER               0x01    /* Byte/Word/Dword/Zero/One/Ones */
 #define ACPI_TYPE_STRING                0x02
 #define ACPI_TYPE_BUFFER                0x03
-#define ACPI_TYPE_PACKAGE               0x04  /* byte_const, multiple data_term/Constant/super_name */
+#define ACPI_TYPE_PACKAGE               0x04    /* byte_const, multiple data_term/Constant/super_name */
 #define ACPI_TYPE_FIELD_UNIT            0x05
-#define ACPI_TYPE_DEVICE                0x06  /* Name, multiple Node */
+#define ACPI_TYPE_DEVICE                0x06    /* Name, multiple Node */
 #define ACPI_TYPE_EVENT                 0x07
-#define ACPI_TYPE_METHOD                0x08  /* Name, byte_const, multiple Code */
+#define ACPI_TYPE_METHOD                0x08    /* Name, byte_const, multiple Code */
 #define ACPI_TYPE_MUTEX                 0x09
 #define ACPI_TYPE_REGION                0x0A
-#define ACPI_TYPE_POWER                 0x0B  /* Name,byte_const,word_const,multi Node */
-#define ACPI_TYPE_PROCESSOR             0x0C  /* Name,byte_const,Dword_const,byte_const,multi nm_o */
-#define ACPI_TYPE_THERMAL               0x0D  /* Name, multiple Node */
+#define ACPI_TYPE_POWER                 0x0B    /* Name,byte_const,word_const,multi Node */
+#define ACPI_TYPE_PROCESSOR             0x0C    /* Name,byte_const,Dword_const,byte_const,multi nm_o */
+#define ACPI_TYPE_THERMAL               0x0D    /* Name, multiple Node */
 #define ACPI_TYPE_BUFFER_FIELD          0x0E
 #define ACPI_TYPE_DDB_HANDLE            0x0F
 #define ACPI_TYPE_DEBUG_OBJECT          0x10
@@ -453,16 +444,16 @@ typedef u32                                     acpi_object_type;
 #define ACPI_TYPE_LOCAL_REGION_FIELD    0x11
 #define ACPI_TYPE_LOCAL_BANK_FIELD      0x12
 #define ACPI_TYPE_LOCAL_INDEX_FIELD     0x13
-#define ACPI_TYPE_LOCAL_REFERENCE       0x14  /* Arg#, Local#, Name, Debug, ref_of, Index */
+#define ACPI_TYPE_LOCAL_REFERENCE       0x14    /* Arg#, Local#, Name, Debug, ref_of, Index */
 #define ACPI_TYPE_LOCAL_ALIAS           0x15
 #define ACPI_TYPE_LOCAL_METHOD_ALIAS    0x16
 #define ACPI_TYPE_LOCAL_NOTIFY          0x17
 #define ACPI_TYPE_LOCAL_ADDRESS_HANDLER 0x18
 #define ACPI_TYPE_LOCAL_RESOURCE        0x19
 #define ACPI_TYPE_LOCAL_RESOURCE_FIELD  0x1A
-#define ACPI_TYPE_LOCAL_SCOPE           0x1B  /* 1 Name, multiple object_list Nodes */
+#define ACPI_TYPE_LOCAL_SCOPE           0x1B    /* 1 Name, multiple object_list Nodes */
 
-#define ACPI_TYPE_NS_NODE_MAX           0x1B  /* Last typecode used within a NS Node */
+#define ACPI_TYPE_NS_NODE_MAX           0x1B    /* Last typecode used within a NS Node */
 
 /*
  * These are special object types that never appear in
@@ -478,7 +469,6 @@ typedef u32                                     acpi_object_type;
 #define ACPI_TYPE_INVALID               0x1E
 #define ACPI_TYPE_NOT_FOUND             0xFF
 
-
 /*
  * Bitmapped ACPI types.  Used internally only
  */
@@ -507,7 +497,7 @@ typedef u32                                     acpi_object_type;
 #define ACPI_BTYPE_DATA                 (ACPI_BTYPE_COMPUTE_DATA  | ACPI_BTYPE_PACKAGE)
 #define ACPI_BTYPE_DATA_REFERENCE       (ACPI_BTYPE_DATA | ACPI_BTYPE_REFERENCE | ACPI_BTYPE_DDB_HANDLE)
 #define ACPI_BTYPE_DEVICE_OBJECTS       (ACPI_BTYPE_DEVICE | ACPI_BTYPE_THERMAL | ACPI_BTYPE_PROCESSOR)
-#define ACPI_BTYPE_OBJECTS_AND_REFS     0x0001FFFF  /* ARG or LOCAL */
+#define ACPI_BTYPE_OBJECTS_AND_REFS     0x0001FFFF      /* ARG or LOCAL */
 #define ACPI_BTYPE_ALL_OBJECTS          0x0000FFFF
 
 /*
@@ -520,7 +510,7 @@ typedef u32                                     acpi_object_type;
 /*
  * Event Types: Fixed & General Purpose
  */
-typedef u32                                     acpi_event_type;
+typedef u32 acpi_event_type;
 
 /*
  * Fixed events
@@ -548,7 +538,7 @@ typedef u32                                     acpi_event_type;
  *          |     +----- Set?
  *          +----------- <Reserved>
  */
-typedef u32                                     acpi_event_status;
+typedef u32 acpi_event_status;
 
 #define ACPI_EVENT_FLAG_DISABLED        (acpi_event_status) 0x00
 #define ACPI_EVENT_FLAG_ENABLED         (acpi_event_status) 0x01
@@ -565,7 +555,6 @@ typedef u32                                     acpi_event_status;
 #define ACPI_GPE_ENABLE                 0
 #define ACPI_GPE_DISABLE                1
 
-
 /*
  * GPE info flags - Per GPE
  * +-+-+-+---+---+-+
@@ -586,22 +575,22 @@ typedef u32                                     acpi_event_status;
 #define ACPI_GPE_TYPE_MASK              (u8) 0x06
 #define ACPI_GPE_TYPE_WAKE_RUN          (u8) 0x06
 #define ACPI_GPE_TYPE_WAKE              (u8) 0x02
-#define ACPI_GPE_TYPE_RUNTIME           (u8) 0x04    /* Default */
+#define ACPI_GPE_TYPE_RUNTIME           (u8) 0x04       /* Default */
 
 #define ACPI_GPE_DISPATCH_MASK          (u8) 0x18
 #define ACPI_GPE_DISPATCH_HANDLER       (u8) 0x08
 #define ACPI_GPE_DISPATCH_METHOD        (u8) 0x10
-#define ACPI_GPE_DISPATCH_NOT_USED      (u8) 0x00    /* Default */
+#define ACPI_GPE_DISPATCH_NOT_USED      (u8) 0x00       /* Default */
 
 #define ACPI_GPE_RUN_ENABLE_MASK        (u8) 0x20
 #define ACPI_GPE_RUN_ENABLED            (u8) 0x20
-#define ACPI_GPE_RUN_DISABLED           (u8) 0x00    /* Default */
+#define ACPI_GPE_RUN_DISABLED           (u8) 0x00       /* Default */
 
 #define ACPI_GPE_WAKE_ENABLE_MASK       (u8) 0x40
 #define ACPI_GPE_WAKE_ENABLED           (u8) 0x40
-#define ACPI_GPE_WAKE_DISABLED          (u8) 0x00    /* Default */
+#define ACPI_GPE_WAKE_DISABLED          (u8) 0x00       /* Default */
 
-#define ACPI_GPE_ENABLE_MASK            (u8) 0x60    /* Both run/wake */
+#define ACPI_GPE_ENABLE_MASK            (u8) 0x60       /* Both run/wake */
 
 #define ACPI_GPE_SYSTEM_MASK            (u8) 0x80
 #define ACPI_GPE_SYSTEM_RUNNING         (u8) 0x80
@@ -610,13 +599,12 @@ typedef u32                                     acpi_event_status;
 /*
  * Flags for GPE and Lock interfaces
  */
-#define ACPI_EVENT_WAKE_ENABLE          0x2             /* acpi_gpe_enable */
-#define ACPI_EVENT_WAKE_DISABLE         0x2             /* acpi_gpe_disable */
+#define ACPI_EVENT_WAKE_ENABLE          0x2     /* acpi_gpe_enable */
+#define ACPI_EVENT_WAKE_DISABLE         0x2     /* acpi_gpe_disable */
 
 #define ACPI_NOT_ISR                    0x1
 #define ACPI_ISR                        0x0
 
-
 /* Notify types */
 
 #define ACPI_SYSTEM_NOTIFY              0x1
@@ -626,10 +614,9 @@ typedef u32                                     acpi_event_status;
 
 #define ACPI_MAX_SYS_NOTIFY             0x7f
 
-
 /* Address Space (Operation Region) Types */
 
-typedef u8                                      acpi_adr_space_type;
+typedef u8 acpi_adr_space_type;
 
 #define ACPI_ADR_SPACE_SYSTEM_MEMORY    (acpi_adr_space_type) 0
 #define ACPI_ADR_SPACE_SYSTEM_IO        (acpi_adr_space_type) 1
@@ -641,7 +628,6 @@ typedef u8                                      acpi_adr_space_type;
 #define ACPI_ADR_SPACE_DATA_TABLE       (acpi_adr_space_type) 7
 #define ACPI_ADR_SPACE_FIXED_HARDWARE   (acpi_adr_space_type) 127
 
-
 /*
  * bit_register IDs
  * These are bitfields defined within the full ACPI registers
@@ -675,74 +661,62 @@ typedef u8                                      acpi_adr_space_type;
 #define ACPI_BITREG_MAX                         0x15
 #define ACPI_NUM_BITREG                         ACPI_BITREG_MAX + 1
 
-
 /*
  * External ACPI object definition
  */
-union acpi_object
-{
-        acpi_object_type                    type;   /* See definition of acpi_ns_type for values */
-        struct
-        {
-                acpi_object_type                    type;
-                acpi_integer                        value;      /* The actual number */
+union acpi_object {
+        acpi_object_type type;  /* See definition of acpi_ns_type for values */
+        struct {
+                acpi_object_type type;
+                acpi_integer value;     /* The actual number */
         } integer;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 length;     /* # of bytes in string, excluding trailing null */
-                char                                *pointer;   /* points to the string value */
+        struct {
+                acpi_object_type type;
+                u32 length;     /* # of bytes in string, excluding trailing null */
+                char *pointer;  /* points to the string value */
         } string;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 length;     /* # of bytes in buffer */
-                u8                                  *pointer;   /* points to the buffer */
+        struct {
+                acpi_object_type type;
+                u32 length;     /* # of bytes in buffer */
+                u8 *pointer;    /* points to the buffer */
         } buffer;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 fill1;
-                acpi_handle                         handle;     /* object reference */
+        struct {
+                acpi_object_type type;
+                u32 fill1;
+                acpi_handle handle;     /* object reference */
         } reference;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 count;      /* # of elements in package */
-                union acpi_object                   *elements;  /* Pointer to an array of ACPI_OBJECTs */
+        struct {
+                acpi_object_type type;
+                u32 count;      /* # of elements in package */
+                union acpi_object *elements;    /* Pointer to an array of ACPI_OBJECTs */
         } package;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 proc_id;
-                acpi_io_address                     pblk_address;
-                u32                                 pblk_length;
+        struct {
+                acpi_object_type type;
+                u32 proc_id;
+                acpi_io_address pblk_address;
+                u32 pblk_length;
         } processor;
 
-        struct
-        {
-                acpi_object_type                    type;
-                u32                                 system_level;
-                u32                                 resource_order;
+        struct {
+                acpi_object_type type;
+                u32 system_level;
+                u32 resource_order;
         } power_resource;
 };
 
-
 /*
  * List of objects, used as a parameter list for control method evaluation
  */
-struct acpi_object_list
-{
-        u32                                 count;
-        union acpi_object                   *pointer;
+struct acpi_object_list {
+        u32 count;
+        union acpi_object *pointer;
 };
 
-
 /*
  * Miscellaneous common Data Structures used by the interfaces
  */
@@ -750,13 +724,11 @@ struct acpi_object_list
 #define ACPI_ALLOCATE_BUFFER        (acpi_size) (-1)
 #define ACPI_ALLOCATE_LOCAL_BUFFER  (acpi_size) (-2)
 
-struct acpi_buffer
-{
-        acpi_size                           length;         /* Length in bytes of the buffer */
-        void                                *pointer;       /* pointer to buffer */
+struct acpi_buffer {
+        acpi_size length;       /* Length in bytes of the buffer */
+        void *pointer;          /* pointer to buffer */
 };
 
-
 /*
  * name_type for acpi_get_name
  */
@@ -764,7 +736,6 @@ struct acpi_buffer
 #define ACPI_SINGLE_NAME                1
 #define ACPI_NAME_TYPE_MAX              1
 
-
 /*
  * Structure and flags for acpi_get_system_info
  */
@@ -773,140 +744,106 @@ struct acpi_buffer
 #define ACPI_SYS_MODE_LEGACY            0x0002
 #define ACPI_SYS_MODES_MASK             0x0003
 
-
 /*
  * ACPI Table Info.  One per ACPI table _type_
  */
-struct acpi_table_info
-{
-        u32                                 count;
+struct acpi_table_info {
+        u32 count;
 };
 
-
 /*
  * System info returned by acpi_get_system_info()
  */
-struct acpi_system_info
-{
-        u32                                 acpi_ca_version;
-        u32                                 flags;
-        u32                                 timer_resolution;
-        u32                                 reserved1;
-        u32                                 reserved2;
-        u32                                 debug_level;
-        u32                                 debug_layer;
-        u32                                 num_table_types;
-        struct acpi_table_info              table_info [NUM_ACPI_TABLE_TYPES];
+struct acpi_system_info {
+        u32 acpi_ca_version;
+        u32 flags;
+        u32 timer_resolution;
+        u32 reserved1;
+        u32 reserved2;
+        u32 debug_level;
+        u32 debug_layer;
+        u32 num_table_types;
+        struct acpi_table_info table_info[NUM_ACPI_TABLE_TYPES];
 };
 
-
 /*
  * Types specific to the OS service interfaces
  */
-
-typedef u32
-(ACPI_SYSTEM_XFACE *acpi_osd_handler) (
-        void                            *context);
+typedef u32(ACPI_SYSTEM_XFACE * acpi_osd_handler) (void *context);
 
 typedef void
-(ACPI_SYSTEM_XFACE *acpi_osd_exec_callback) (
-        void                            *context);
+ (ACPI_SYSTEM_XFACE * acpi_osd_exec_callback) (void *context);
 
 /*
  * Various handlers and callback procedures
  */
-typedef
-u32 (*acpi_event_handler) (
-        void                                *context);
+typedef u32(*acpi_event_handler) (void *context);
 
 typedef
-void (*acpi_notify_handler) (
-        acpi_handle                         device,
-        u32                                 value,
-        void                                *context);
+void (*acpi_notify_handler) (acpi_handle device, u32 value, void *context);
 
 typedef
-void (*acpi_object_handler) (
-        acpi_handle                         object,
-        u32                                 function,
-        void                                *data);
+void (*acpi_object_handler) (acpi_handle object, u32 function, void *data);
 
-typedef
-acpi_status (*acpi_init_handler) (
-        acpi_handle                         object,
-        u32                                 function);
+typedef acpi_status(*acpi_init_handler) (acpi_handle object, u32 function);
 
 #define ACPI_INIT_DEVICE_INI        1
 
 typedef
-acpi_status (*acpi_exception_handler) (
-        acpi_status                     aml_status,
-        acpi_name                       name,
-        u16                             opcode,
-        u32                             aml_offset,
-        void                            *context);
-
+acpi_status(*acpi_exception_handler) (acpi_status aml_status,
+                                      acpi_name name,
+                                      u16 opcode,
+                                      u32 aml_offset, void *context);
 
 /* Address Spaces (For Operation Regions) */
 
 typedef
-acpi_status (*acpi_adr_space_handler) (
-        u32                                 function,
-        acpi_physical_address               address,
-        u32                                 bit_width,
-        acpi_integer                        *value,
-        void                                *handler_context,
-        void                                *region_context);
+acpi_status(*acpi_adr_space_handler) (u32 function,
+                                      acpi_physical_address address,
+                                      u32 bit_width,
+                                      acpi_integer * value,
+                                      void *handler_context,
+                                      void *region_context);
 
 #define ACPI_DEFAULT_HANDLER        NULL
 
-
 typedef
-acpi_status (*acpi_adr_space_setup) (
-        acpi_handle                         region_handle,
-        u32                                 function,
-        void                                *handler_context,
-        void                                **region_context);
+acpi_status(*acpi_adr_space_setup) (acpi_handle region_handle,
+                                    u32 function,
+                                    void *handler_context,
+                                    void **region_context);
 
 #define ACPI_REGION_ACTIVATE    0
 #define ACPI_REGION_DEACTIVATE  1
 
 typedef
-acpi_status (*acpi_walk_callback) (
-        acpi_handle                         obj_handle,
-        u32                                 nesting_level,
-        void                                *context,
-        void                                **return_value);
-
+acpi_status(*acpi_walk_callback) (acpi_handle obj_handle,
+                                  u32 nesting_level,
+                                  void *context, void **return_value);
 
 /* Interrupt handler return values */
 
 #define ACPI_INTERRUPT_NOT_HANDLED      0x00
 #define ACPI_INTERRUPT_HANDLED          0x01
 
-
 /* Common string version of device HIDs and UIDs */
 
-struct acpi_device_id
-{
-        char                            value[ACPI_DEVICE_ID_LENGTH];
+struct acpi_device_id {
+        char value[ACPI_DEVICE_ID_LENGTH];
 };
 
 /* Common string version of device CIDs */
 
-struct acpi_compatible_id
-{
-        char                            value[ACPI_MAX_CID_LENGTH];
+struct acpi_compatible_id {
+        char value[ACPI_MAX_CID_LENGTH];
 };
 
-struct acpi_compatible_id_list
-{
-        u32                             count;
-        u32                             size;
-        struct acpi_compatible_id       id[1];
+struct acpi_compatible_id_list {
+        u32 count;
+        u32 size;
+        struct acpi_compatible_id id[1];
 };
 
-
 /* Structure and flags for acpi_get_object_info */
 
 #define ACPI_VALID_STA                  0x0001
@@ -916,55 +853,45 @@ struct acpi_compatible_id_list
 #define ACPI_VALID_CID                  0x0010
 #define ACPI_VALID_SXDS                 0x0020
 
-
 #define ACPI_COMMON_OBJ_INFO \
         acpi_object_type                    type;           /* ACPI object type */ \
-        acpi_name                           name            /* ACPI object Name */
-
+        acpi_name                           name        /* ACPI object Name */
 
-struct acpi_obj_info_header
-{
+struct acpi_obj_info_header {
         ACPI_COMMON_OBJ_INFO;
 };
 
-
 /* Structure returned from Get Object Info */
 
-struct acpi_device_info
-{
+struct acpi_device_info {
         ACPI_COMMON_OBJ_INFO;
 
-        u32                                 valid;              /* Indicates which fields below are valid */
-        u32                                 current_status;     /* _STA value */
-        acpi_integer                        address;            /* _ADR value if any */
-        struct acpi_device_id               hardware_id;        /* _HID value if any */
-        struct acpi_device_id               unique_id;          /* _UID value if any */
-        u8                                  highest_dstates[4]; /* _sx_d values: 0xFF indicates not valid */
-        struct acpi_compatible_id_list      compatibility_id;   /* List of _CIDs if any */
+        u32 valid;              /* Indicates which fields below are valid */
+        u32 current_status;     /* _STA value */
+        acpi_integer address;   /* _ADR value if any */
+        struct acpi_device_id hardware_id;      /* _HID value if any */
+        struct acpi_device_id unique_id;        /* _UID value if any */
+        u8 highest_dstates[4];  /* _sx_d values: 0xFF indicates not valid */
+        struct acpi_compatible_id_list compatibility_id;        /* List of _CIDs if any */
 };
 
-
 /* Context structs for address space handlers */
 
-struct acpi_pci_id
-{
-        u16                                 segment;
-        u16                                 bus;
-        u16                                 device;
-        u16                                 function;
+struct acpi_pci_id {
+        u16 segment;
+        u16 bus;
+        u16 device;
+        u16 function;
 };
 
-
-struct acpi_mem_space_context
-{
-        u32                                 length;
-        acpi_physical_address               address;
-        acpi_physical_address               mapped_physical_address;
-        u8                                  *mapped_logical_address;
-        acpi_size                           mapped_length;
+struct acpi_mem_space_context {
+        u32 length;
+        acpi_physical_address address;
+        acpi_physical_address mapped_physical_address;
+        u8 *mapped_logical_address;
+        acpi_size mapped_length;
 };
 
-
 /*
  * Definitions for Resource Attributes
  */
@@ -994,8 +921,8 @@ struct acpi_mem_space_context
 /*
  *  IO Port Descriptor Decode
  */
-#define ACPI_DECODE_10                  (u8) 0x00    /* 10-bit IO address decode */
-#define ACPI_DECODE_16                  (u8) 0x01    /* 16-bit IO address decode */
+#define ACPI_DECODE_10                  (u8) 0x00       /* 10-bit IO address decode */
+#define ACPI_DECODE_16                  (u8) 0x01       /* 16-bit IO address decode */
 
 /*
  *  IRQ Attributes
@@ -1047,32 +974,28 @@ struct acpi_mem_space_context
 #define ACPI_PRODUCER                   (u8) 0x00
 #define ACPI_CONSUMER                   (u8) 0x01
 
-
 /*
  *  Structures used to describe device resources
  */
-struct acpi_resource_irq
-{
-        u32                                 edge_level;
-        u32                                 active_high_low;
-        u32                                 shared_exclusive;
-        u32                                 number_of_interrupts;
-        u32                                 interrupts[1];
+struct acpi_resource_irq {
+        u32 edge_level;
+        u32 active_high_low;
+        u32 shared_exclusive;
+        u32 number_of_interrupts;
+        u32 interrupts[1];
 };
 
-struct acpi_resource_dma
-{
-        u32                                 type;
-        u32                                 bus_master;
-        u32                                 transfer;
-        u32                                 number_of_channels;
-        u32                                 channels[1];
+struct acpi_resource_dma {
+        u32 type;
+        u32 bus_master;
+        u32 transfer;
+        u32 number_of_channels;
+        u32 channels[1];
 };
 
-struct acpi_resource_start_dpf
-{
-        u32                                 compatibility_priority;
-        u32                                 performance_robustness;
+struct acpi_resource_start_dpf {
+        u32 compatibility_priority;
+        u32 performance_robustness;
 };
 
 /*
@@ -1080,149 +1003,127 @@ struct acpi_resource_start_dpf
  * needed because it has no fields
  */
 
-struct acpi_resource_io
-{
-        u32                                 io_decode;
-        u32                                 min_base_address;
-        u32                                 max_base_address;
-        u32                                 alignment;
-        u32                                 range_length;
+struct acpi_resource_io {
+        u32 io_decode;
+        u32 min_base_address;
+        u32 max_base_address;
+        u32 alignment;
+        u32 range_length;
 };
 
-struct acpi_resource_fixed_io
-{
-        u32                                 base_address;
-        u32                                 range_length;
+struct acpi_resource_fixed_io {
+        u32 base_address;
+        u32 range_length;
 };
 
-struct acpi_resource_vendor
-{
-        u32                                 length;
-        u8                                  reserved[1];
+struct acpi_resource_vendor {
+        u32 length;
+        u8 reserved[1];
 };
 
-struct acpi_resource_end_tag
-{
-        u8                                  checksum;
+struct acpi_resource_end_tag {
+        u8 checksum;
 };
 
-struct acpi_resource_mem24
-{
-        u32                                 read_write_attribute;
-        u32                                 min_base_address;
-        u32                                 max_base_address;
-        u32                                 alignment;
-        u32                                 range_length;
+struct acpi_resource_mem24 {
+        u32 read_write_attribute;
+        u32 min_base_address;
+        u32 max_base_address;
+        u32 alignment;
+        u32 range_length;
 };
 
-struct acpi_resource_mem32
-{
-        u32                                 read_write_attribute;
-        u32                                 min_base_address;
-        u32                                 max_base_address;
-        u32                                 alignment;
-        u32                                 range_length;
+struct acpi_resource_mem32 {
+        u32 read_write_attribute;
+        u32 min_base_address;
+        u32 max_base_address;
+        u32 alignment;
+        u32 range_length;
 };
 
-struct acpi_resource_fixed_mem32
-{
-        u32                                 read_write_attribute;
-        u32                                 range_base_address;
-        u32                                 range_length;
+struct acpi_resource_fixed_mem32 {
+        u32 read_write_attribute;
+        u32 range_base_address;
+        u32 range_length;
 };
 
-struct acpi_memory_attribute
-{
-        u16                                 cache_attribute;
-        u16                                 read_write_attribute;
+struct acpi_memory_attribute {
+        u16 cache_attribute;
+        u16 read_write_attribute;
 };
 
-struct acpi_io_attribute
-{
-        u16                                 range_attribute;
-        u16                                 translation_attribute;
+struct acpi_io_attribute {
+        u16 range_attribute;
+        u16 translation_attribute;
 };
 
-struct acpi_bus_attribute
-{
-        u16                                 reserved1;
-        u16                                 reserved2;
+struct acpi_bus_attribute {
+        u16 reserved1;
+        u16 reserved2;
 };
 
-union acpi_resource_attribute
-{
-        struct acpi_memory_attribute        memory;
-        struct acpi_io_attribute            io;
-        struct acpi_bus_attribute           bus;
+union acpi_resource_attribute {
+        struct acpi_memory_attribute memory;
+        struct acpi_io_attribute io;
+        struct acpi_bus_attribute bus;
 };
 
-struct acpi_resource_source
-{
-        u32                                 index;
-        u32                                 string_length;
-        char                                *string_ptr;
+struct acpi_resource_source {
+        u32 index;
+        u32 string_length;
+        char *string_ptr;
 };
 
-struct acpi_resource_address16
-{
-        u32                                 resource_type;
-        u32                                 producer_consumer;
-        u32                                 decode;
-        u32                                 min_address_fixed;
-        u32                                 max_address_fixed;
-        union acpi_resource_attribute       attribute;
-        u32                                 granularity;
-        u32                                 min_address_range;
-        u32                                 max_address_range;
-        u32                                 address_translation_offset;
-        u32                                 address_length;
-        struct acpi_resource_source         resource_source;
-};
+/* Fields common to all address descriptors, 16/32/64 bit */
 
-struct acpi_resource_address32
-{
-        u32                                 resource_type;
-        u32                                 producer_consumer;
-        u32                                 decode;
-        u32                                 min_address_fixed;
-        u32                                 max_address_fixed;
+#define ACPI_RESOURCE_ADDRESS_COMMON \
+        u32                                 resource_type; \
+        u32                                 producer_consumer; \
+        u32                                 decode; \
+        u32                                 min_address_fixed; \
+        u32                                 max_address_fixed; \
         union acpi_resource_attribute       attribute;
-        u32                                 granularity;
-        u32                                 min_address_range;
-        u32                                 max_address_range;
-        u32                                 address_translation_offset;
-        u32                                 address_length;
-        struct acpi_resource_source         resource_source;
+
+struct acpi_resource_address {
+ACPI_RESOURCE_ADDRESS_COMMON};
+
+struct acpi_resource_address16 {
+        ACPI_RESOURCE_ADDRESS_COMMON u32 granularity;
+        u32 min_address_range;
+        u32 max_address_range;
+        u32 address_translation_offset;
+        u32 address_length;
+        struct acpi_resource_source resource_source;
 };
 
-struct acpi_resource_address64
-{
-        u32                                 resource_type;
-        u32                                 producer_consumer;
-        u32                                 decode;
-        u32                                 min_address_fixed;
-        u32                                 max_address_fixed;
-        union acpi_resource_attribute       attribute;
-        u64                                 granularity;
-        u64                                 min_address_range;
-        u64                                 max_address_range;
-        u64                                 address_translation_offset;
-        u64                                 address_length;
-        u64                                 type_specific_attributes;
-        struct acpi_resource_source         resource_source;
+struct acpi_resource_address32 {
+        ACPI_RESOURCE_ADDRESS_COMMON u32 granularity;
+        u32 min_address_range;
+        u32 max_address_range;
+        u32 address_translation_offset;
+        u32 address_length;
+        struct acpi_resource_source resource_source;
 };
 
-struct acpi_resource_ext_irq
-{
-        u32                                 producer_consumer;
-        u32                                 edge_level;
-        u32                                 active_high_low;
-        u32                                 shared_exclusive;
-        u32                                 number_of_interrupts;
-        struct acpi_resource_source         resource_source;
-        u32                                 interrupts[1];
+struct acpi_resource_address64 {
+        ACPI_RESOURCE_ADDRESS_COMMON u64 granularity;
+        u64 min_address_range;
+        u64 max_address_range;
+        u64 address_translation_offset;
+        u64 address_length;
+        u64 type_specific_attributes;
+        struct acpi_resource_source resource_source;
 };
 
+struct acpi_resource_ext_irq {
+        u32 producer_consumer;
+        u32 edge_level;
+        u32 active_high_low;
+        u32 shared_exclusive;
+        u32 number_of_interrupts;
+        struct acpi_resource_source resource_source;
+        u32 interrupts[1];
+};
 
 /* ACPI_RESOURCE_TYPEs */
 
@@ -1242,35 +1143,34 @@ struct acpi_resource_ext_irq
 #define ACPI_RSTYPE_ADDRESS64           13
 #define ACPI_RSTYPE_EXT_IRQ             14
 
-typedef u32                                     acpi_resource_type;
-
-union acpi_resource_data
-{
-        struct acpi_resource_irq            irq;
-        struct acpi_resource_dma            dma;
-        struct acpi_resource_start_dpf      start_dpf;
-        struct acpi_resource_io             io;
-        struct acpi_resource_fixed_io       fixed_io;
-        struct acpi_resource_vendor         vendor_specific;
-        struct acpi_resource_end_tag        end_tag;
-        struct acpi_resource_mem24          memory24;
-        struct acpi_resource_mem32          memory32;
-        struct acpi_resource_fixed_mem32    fixed_memory32;
-        struct acpi_resource_address16      address16;
-        struct acpi_resource_address32      address32;
-        struct acpi_resource_address64      address64;
-        struct acpi_resource_ext_irq        extended_irq;
+typedef u32 acpi_resource_type;
+
+union acpi_resource_data {
+        struct acpi_resource_irq irq;
+        struct acpi_resource_dma dma;
+        struct acpi_resource_start_dpf start_dpf;
+        struct acpi_resource_io io;
+        struct acpi_resource_fixed_io fixed_io;
+        struct acpi_resource_vendor vendor_specific;
+        struct acpi_resource_end_tag end_tag;
+        struct acpi_resource_mem24 memory24;
+        struct acpi_resource_mem32 memory32;
+        struct acpi_resource_fixed_mem32 fixed_memory32;
+        struct acpi_resource_address address;   /* Common 16/32/64 address fields */
+        struct acpi_resource_address16 address16;
+        struct acpi_resource_address32 address32;
+        struct acpi_resource_address64 address64;
+        struct acpi_resource_ext_irq extended_irq;
 };
 
-struct acpi_resource
-{
-        acpi_resource_type                  id;
-        u32                                 length;
-        union acpi_resource_data            data;
+struct acpi_resource {
+        acpi_resource_type id;
+        u32 length;
+        union acpi_resource_data data;
 };
 
 #define ACPI_RESOURCE_LENGTH                12
-#define ACPI_RESOURCE_LENGTH_NO_DATA        8       /* Id + Length fields */
+#define ACPI_RESOURCE_LENGTH_NO_DATA        8   /* Id + Length fields */
 
 #define ACPI_SIZEOF_RESOURCE(type)          (ACPI_RESOURCE_LENGTH_NO_DATA + sizeof (type))
 
@@ -1286,19 +1186,16 @@ struct acpi_resource
  * END: of definitions for Resource Attributes
  */
 
-
-struct acpi_pci_routing_table
-{
-        u32                                 length;
-        u32                                 pin;
-        acpi_integer                        address;        /* here for 64-bit alignment */
-        u32                                 source_index;
-        char                                source[4];      /* pad to 64 bits so sizeof() works in all cases */
+struct acpi_pci_routing_table {
+        u32 length;
+        u32 pin;
+        acpi_integer address;   /* here for 64-bit alignment */
+        u32 source_index;
+        char source[4];         /* pad to 64 bits so sizeof() works in all cases */
 };
 
 /*
  * END: of definitions for PCI Routing tables
  */
 
-
-#endif /* __ACTYPES_H__ */
+#endif                          /* __ACTYPES_H__ */
diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h
index 0de26b8f1028..c1086452696e 100644
--- a/include/acpi/acutils.h
+++ b/include/acpi/acutils.h
@@ -44,27 +44,17 @@
 #ifndef _ACUTILS_H
 #define _ACUTILS_H
 
-
 typedef
-acpi_status (*acpi_pkg_callback) (
-        u8                              object_type,
-        union acpi_operand_object       *source_object,
-        union acpi_generic_state        *state,
-        void                            *context);
-
-acpi_status
-acpi_ut_walk_package_tree (
-        union acpi_operand_object       *source_object,
-        void                            *target_object,
-        acpi_pkg_callback               walk_callback,
-        void                            *context);
-
-struct acpi_pkg_info
-{
-        u8                              *free_space;
-        acpi_size                       length;
-        u32                             object_space;
-        u32                             num_packages;
+acpi_status(*acpi_pkg_callback) (u8 object_type,
+                                 union acpi_operand_object * source_object,
+                                 union acpi_generic_state * state,
+                                 void *context);
+
+struct acpi_pkg_info {
+        u8 *free_space;
+        acpi_size length;
+        u32 object_space;
+        u32 num_packages;
 };
 
 #define REF_INCREMENT       (u16) 0
@@ -78,176 +68,89 @@ struct acpi_pkg_info
 #define DB_DWORD_DISPLAY    4
 #define DB_QWORD_DISPLAY    8
 
+/*
+ * utglobal - Global data structures and procedures
+ */
+void acpi_ut_init_globals(void);
 
-/* Global initialization interfaces */
+#if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DEBUGGER)
 
-void
-acpi_ut_init_globals (
-        void);
+char *acpi_ut_get_mutex_name(u32 mutex_id);
 
-void
-acpi_ut_terminate (
-        void);
+#endif
 
+char *acpi_ut_get_type_name(acpi_object_type type);
 
-/*
- * ut_init - miscellaneous initialization and shutdown
- */
+char *acpi_ut_get_node_name(void *object);
 
-acpi_status
-acpi_ut_hardware_initialize (
-        void);
+char *acpi_ut_get_descriptor_name(void *object);
 
-void
-acpi_ut_subsystem_shutdown (
-        void);
+char *acpi_ut_get_object_type_name(union acpi_operand_object *obj_desc);
 
-acpi_status
-acpi_ut_validate_fadt (
-        void);
+char *acpi_ut_get_region_name(u8 space_id);
+
+char *acpi_ut_get_event_name(u32 event_id);
+
+char acpi_ut_hex_to_ascii_char(acpi_integer integer, u32 position);
+
+u8 acpi_ut_valid_object_type(acpi_object_type type);
 
 /*
- * ut_global - Global data structures and procedures
+ * utinit - miscellaneous initialization and shutdown
  */
+acpi_status acpi_ut_hardware_initialize(void);
 
-#if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DEBUGGER)
+void acpi_ut_subsystem_shutdown(void);
 
-char *
-acpi_ut_get_mutex_name (
-        u32                             mutex_id);
+acpi_status acpi_ut_validate_fadt(void);
 
-#endif
+/*
+ * utclib - Local implementations of C library functions
+ */
+#ifndef ACPI_USE_SYSTEM_CLIBRARY
 
-char *
-acpi_ut_get_type_name (
-        acpi_object_type                type);
+acpi_size acpi_ut_strlen(const char *string);
 
-char *
-acpi_ut_get_node_name (
-        void                            *object);
+char *acpi_ut_strcpy(char *dst_string, const char *src_string);
 
-char *
-acpi_ut_get_descriptor_name (
-        void                            *object);
+char *acpi_ut_strncpy(char *dst_string,
+                      const char *src_string, acpi_size count);
 
-char *
-acpi_ut_get_object_type_name (
-        union acpi_operand_object       *obj_desc);
+int acpi_ut_memcmp(const char *buffer1, const char *buffer2, acpi_size count);
 
-char *
-acpi_ut_get_region_name (
-        u8                              space_id);
+int acpi_ut_strncmp(const char *string1, const char *string2, acpi_size count);
 
-char *
-acpi_ut_get_event_name (
-        u32                             event_id);
+int acpi_ut_strcmp(const char *string1, const char *string2);
 
-char
-acpi_ut_hex_to_ascii_char (
-        acpi_integer                    integer,
-        u32                             position);
+char *acpi_ut_strcat(char *dst_string, const char *src_string);
 
-u8
-acpi_ut_valid_object_type (
-        acpi_object_type                type);
+char *acpi_ut_strncat(char *dst_string,
+                      const char *src_string, acpi_size count);
 
-acpi_owner_id
-acpi_ut_allocate_owner_id (
-        u32                             id_type);
+u32 acpi_ut_strtoul(const char *string, char **terminator, u32 base);
 
+char *acpi_ut_strstr(char *string1, char *string2);
 
-/*
- * ut_clib - Local implementations of C library functions
- */
+void *acpi_ut_memcpy(void *dest, const void *src, acpi_size count);
 
-#ifndef ACPI_USE_SYSTEM_CLIBRARY
+void *acpi_ut_memset(void *dest, acpi_native_uint value, acpi_size count);
+
+int acpi_ut_to_upper(int c);
 
-acpi_size
-acpi_ut_strlen (
-        const char                      *string);
-
-char *
-acpi_ut_strcpy (
-        char                            *dst_string,
-        const char                      *src_string);
-
-char *
-acpi_ut_strncpy (
-        char                            *dst_string,
-        const char                      *src_string,
-        acpi_size                       count);
-
-int
-acpi_ut_memcmp (
-        const char                      *buffer1,
-        const char                      *buffer2,
-        acpi_size                       count);
-
-int
-acpi_ut_strncmp (
-        const char                      *string1,
-        const char                      *string2,
-        acpi_size                       count);
-
-int
-acpi_ut_strcmp (
-        const char                      *string1,
-        const char                      *string2);
-
-char *
-acpi_ut_strcat (
-        char                            *dst_string,
-        const char                      *src_string);
-
-char *
-acpi_ut_strncat (
-        char                            *dst_string,
-        const char                      *src_string,
-        acpi_size                       count);
-
-u32
-acpi_ut_strtoul (
-        const char                      *string,
-        char                            **terminator,
-        u32                             base);
-
-char *
-acpi_ut_strstr (
-        char                            *string1,
-        char                            *string2);
-
-void *
-acpi_ut_memcpy (
-        void                            *dest,
-        const void                      *src,
-        acpi_size                       count);
-
-void *
-acpi_ut_memset (
-        void                            *dest,
-        acpi_native_uint                value,
-        acpi_size                       count);
-
-int
-acpi_ut_to_upper (
-        int                             c);
-
-int
-acpi_ut_to_lower (
-        int                             c);
+int acpi_ut_to_lower(int c);
 
 extern const u8 _acpi_ctype[];
 
-#define _ACPI_XA     0x00    /* extra alphabetic - not supported */
-#define _ACPI_XS     0x40    /* extra space */
-#define _ACPI_BB     0x00    /* BEL, BS, etc. - not supported */
-#define _ACPI_CN     0x20    /* CR, FF, HT, NL, VT */
-#define _ACPI_DI     0x04    /* '0'-'9' */
-#define _ACPI_LO     0x02    /* 'a'-'z' */
-#define _ACPI_PU     0x10    /* punctuation */
-#define _ACPI_SP     0x08    /* space */
-#define _ACPI_UP     0x01    /* 'A'-'Z' */
-#define _ACPI_XD     0x80    /* '0'-'9', 'A'-'F', 'a'-'f' */
+#define _ACPI_XA     0x00       /* extra alphabetic - not supported */
+#define _ACPI_XS     0x40       /* extra space */
+#define _ACPI_BB     0x00       /* BEL, BS, etc. - not supported */
+#define _ACPI_CN     0x20       /* CR, FF, HT, NL, VT */
+#define _ACPI_DI     0x04       /* '0'-'9' */
+#define _ACPI_LO     0x02       /* 'a'-'z' */
+#define _ACPI_PU     0x10       /* punctuation */
+#define _ACPI_SP     0x08       /* space */
+#define _ACPI_UP     0x01       /* 'A'-'Z' */
+#define _ACPI_XD     0x80       /* '0'-'9', 'A'-'F', 'a'-'f' */
 
 #define ACPI_IS_DIGIT(c)  (_acpi_ctype[(unsigned char)(c)] & (_ACPI_DI))
 #define ACPI_IS_SPACE(c)  (_acpi_ctype[(unsigned char)(c)] & (_ACPI_SP))
@@ -258,618 +161,323 @@ extern const u8 _acpi_ctype[];
 #define ACPI_IS_ALPHA(c)  (_acpi_ctype[(unsigned char)(c)] & (_ACPI_LO | _ACPI_UP))
 #define ACPI_IS_ASCII(c)  ((c) < 0x80)
 
-#endif /* ACPI_USE_SYSTEM_CLIBRARY */
+#endif                          /* ACPI_USE_SYSTEM_CLIBRARY */
 
 /*
- * ut_copy - Object construction and conversion interfaces
+ * utcopy - Object construction and conversion interfaces
  */
-
-acpi_status
-acpi_ut_build_simple_object(
-        union acpi_operand_object       *obj,
-        union acpi_object               *user_obj,
-        u8                              *data_space,
-        u32                             *buffer_space_used);
-
-acpi_status
-acpi_ut_build_package_object (
-        union acpi_operand_object       *obj,
-        u8                              *buffer,
-        u32                             *space_used);
-
 acpi_status
-acpi_ut_copy_ielement_to_eelement (
-        u8                              object_type,
-        union acpi_operand_object       *source_object,
-        union acpi_generic_state        *state,
-        void                            *context);
+acpi_ut_build_simple_object(union acpi_operand_object *obj,
+                            union acpi_object *user_obj,
+                            u8 * data_space, u32 * buffer_space_used);
 
 acpi_status
-acpi_ut_copy_ielement_to_ielement (
-        u8                              object_type,
-        union acpi_operand_object       *source_object,
-        union acpi_generic_state        *state,
-        void                            *context);
+acpi_ut_build_package_object(union acpi_operand_object *obj,
+                             u8 * buffer, u32 * space_used);
 
 acpi_status
-acpi_ut_copy_iobject_to_eobject (
-        union acpi_operand_object       *obj,
-        struct acpi_buffer              *ret_buffer);
+acpi_ut_copy_iobject_to_eobject(union acpi_operand_object *obj,
+                                struct acpi_buffer *ret_buffer);
 
 acpi_status
-acpi_ut_copy_esimple_to_isimple(
-        union acpi_object               *user_obj,
-        union acpi_operand_object       **return_obj);
+acpi_ut_copy_eobject_to_iobject(union acpi_object *obj,
+                                union acpi_operand_object **internal_obj);
 
 acpi_status
-acpi_ut_copy_eobject_to_iobject (
-        union acpi_object               *obj,
-        union acpi_operand_object       **internal_obj);
+acpi_ut_copy_isimple_to_isimple(union acpi_operand_object *source_obj,
+                                union acpi_operand_object *dest_obj);
 
 acpi_status
-acpi_ut_copy_isimple_to_isimple (
-        union acpi_operand_object       *source_obj,
-        union acpi_operand_object       *dest_obj);
-
-acpi_status
-acpi_ut_copy_ipackage_to_ipackage (
-        union acpi_operand_object       *source_obj,
-        union acpi_operand_object       *dest_obj,
-        struct acpi_walk_state          *walk_state);
-
-acpi_status
-acpi_ut_copy_simple_object (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       *dest_desc);
-
-acpi_status
-acpi_ut_copy_iobject_to_iobject (
-        union acpi_operand_object       *source_desc,
-        union acpi_operand_object       **dest_desc,
-        struct acpi_walk_state          *walk_state);
-
+acpi_ut_copy_iobject_to_iobject(union acpi_operand_object *source_desc,
+                                union acpi_operand_object **dest_desc,
+                                struct acpi_walk_state *walk_state);
 
 /*
- * ut_create - Object creation
+ * utcreate - Object creation
  */
-
 acpi_status
-acpi_ut_update_object_reference (
-        union acpi_operand_object       *object,
-        u16                             action);
-
+acpi_ut_update_object_reference(union acpi_operand_object *object, u16 action);
 
 /*
- * ut_debug - Debug interfaces
+ * utdebug - Debug interfaces
  */
+void acpi_ut_init_stack_ptr_trace(void);
 
-void
-acpi_ut_init_stack_ptr_trace (
-        void);
-
-void
-acpi_ut_track_stack_ptr (
-        void);
+void acpi_ut_track_stack_ptr(void);
 
 void
-acpi_ut_trace (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info);
+acpi_ut_trace(u32 line_number,
+              const char *function_name, char *module_name, u32 component_id);
 
 void
-acpi_ut_trace_ptr (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        void                            *pointer);
+acpi_ut_trace_ptr(u32 line_number,
+                  const char *function_name,
+                  char *module_name, u32 component_id, void *pointer);
 
 void
-acpi_ut_trace_u32 (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        u32                             integer);
+acpi_ut_trace_u32(u32 line_number,
+                  const char *function_name,
+                  char *module_name, u32 component_id, u32 integer);
 
 void
-acpi_ut_trace_str (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        char                            *string);
+acpi_ut_trace_str(u32 line_number,
+                  const char *function_name,
+                  char *module_name, u32 component_id, char *string);
 
 void
-acpi_ut_exit (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info);
+acpi_ut_exit(u32 line_number,
+             const char *function_name, char *module_name, u32 component_id);
 
 void
-acpi_ut_status_exit (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        acpi_status                     status);
+acpi_ut_status_exit(u32 line_number,
+                    const char *function_name,
+                    char *module_name, u32 component_id, acpi_status status);
 
 void
-acpi_ut_value_exit (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        acpi_integer                    value);
+acpi_ut_value_exit(u32 line_number,
+                   const char *function_name,
+                   char *module_name, u32 component_id, acpi_integer value);
 
 void
-acpi_ut_ptr_exit (
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        u8                              *ptr);
+acpi_ut_ptr_exit(u32 line_number,
+                 const char *function_name,
+                 char *module_name, u32 component_id, u8 * ptr);
 
-void
-acpi_ut_report_info (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id);
+void acpi_ut_report_info(char *module_name, u32 line_number, u32 component_id);
 
-void
-acpi_ut_report_error (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id);
+void acpi_ut_report_error(char *module_name, u32 line_number, u32 component_id);
 
 void
-acpi_ut_report_warning (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id);
+acpi_ut_report_warning(char *module_name, u32 line_number, u32 component_id);
 
-void
-acpi_ut_dump_buffer (
-        u8                              *buffer,
-        u32                             count,
-        u32                             display,
-        u32                             component_id);
+void acpi_ut_dump_buffer(u8 * buffer, u32 count, u32 display, u32 component_id);
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_debug_print (
-        u32                             requested_debug_level,
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        char                            *format,
-        ...) ACPI_PRINTF_LIKE_FUNC;
+acpi_ut_debug_print(u32 requested_debug_level,
+                    u32 line_number,
+                    const char *function_name,
+                    char *module_name,
+                    u32 component_id, char *format, ...) ACPI_PRINTF_LIKE_FUNC;
 
 void ACPI_INTERNAL_VAR_XFACE
-acpi_ut_debug_print_raw (
-        u32                             requested_debug_level,
-        u32                             line_number,
-        struct acpi_debug_print_info    *dbg_info,
-        char                            *format,
-        ...) ACPI_PRINTF_LIKE_FUNC;
-
+acpi_ut_debug_print_raw(u32 requested_debug_level,
+                        u32 line_number,
+                        const char *function_name,
+                        char *module_name,
+                        u32 component_id,
+                        char *format, ...) ACPI_PRINTF_LIKE_FUNC;
 
 /*
- * ut_delete - Object deletion
+ * utdelete - Object deletion and reference counts
  */
+void acpi_ut_add_reference(union acpi_operand_object *object);
 
-void
-acpi_ut_delete_internal_obj (
-        union acpi_operand_object       *object);
-
-void
-acpi_ut_delete_internal_package_object (
-        union acpi_operand_object       *object);
+void acpi_ut_remove_reference(union acpi_operand_object *object);
 
-void
-acpi_ut_delete_internal_simple_object (
-        union acpi_operand_object       *object);
+void acpi_ut_delete_internal_package_object(union acpi_operand_object *object);
 
-void
-acpi_ut_delete_internal_object_list (
-        union acpi_operand_object       **obj_list);
+void acpi_ut_delete_internal_simple_object(union acpi_operand_object *object);
 
+void acpi_ut_delete_internal_object_list(union acpi_operand_object **obj_list);
 
 /*
- * ut_eval - object evaluation
+ * uteval - object evaluation
  */
-
-/* Method name strings */
-
-#define METHOD_NAME__HID        "_HID"
-#define METHOD_NAME__CID        "_CID"
-#define METHOD_NAME__UID        "_UID"
-#define METHOD_NAME__ADR        "_ADR"
-#define METHOD_NAME__STA        "_STA"
-#define METHOD_NAME__REG        "_REG"
-#define METHOD_NAME__SEG        "_SEG"
-#define METHOD_NAME__BBN        "_BBN"
-#define METHOD_NAME__PRT        "_PRT"
-#define METHOD_NAME__CRS        "_CRS"
-#define METHOD_NAME__PRS        "_PRS"
-#define METHOD_NAME__PRW        "_PRW"
-
+acpi_status acpi_ut_osi_implementation(struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ut_osi_implementation (
-        struct acpi_walk_state          *walk_state);
+acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node,
+                        char *path,
+                        u32 expected_return_btypes,
+                        union acpi_operand_object **return_desc);
 
 acpi_status
-acpi_ut_evaluate_object (
-        struct acpi_namespace_node      *prefix_node,
-        char                            *path,
-        u32                             expected_return_btypes,
-        union acpi_operand_object       **return_desc);
+acpi_ut_evaluate_numeric_object(char *object_name,
+                                struct acpi_namespace_node *device_node,
+                                acpi_integer * address);
 
 acpi_status
-acpi_ut_evaluate_numeric_object (
-        char                            *object_name,
-        struct acpi_namespace_node      *device_node,
-        acpi_integer                    *address);
+acpi_ut_execute_HID(struct acpi_namespace_node *device_node,
+                    struct acpi_device_id *hid);
 
 acpi_status
-acpi_ut_execute_HID (
-        struct acpi_namespace_node      *device_node,
-        struct acpi_device_id           *hid);
+acpi_ut_execute_CID(struct acpi_namespace_node *device_node,
+                    struct acpi_compatible_id_list **return_cid_list);
 
 acpi_status
-acpi_ut_execute_CID (
-        struct acpi_namespace_node      *device_node,
-        struct acpi_compatible_id_list **return_cid_list);
+acpi_ut_execute_STA(struct acpi_namespace_node *device_node,
+                    u32 * status_flags);
 
 acpi_status
-acpi_ut_execute_STA (
-        struct acpi_namespace_node      *device_node,
-        u32                             *status_flags);
+acpi_ut_execute_UID(struct acpi_namespace_node *device_node,
+                    struct acpi_device_id *uid);
 
 acpi_status
-acpi_ut_execute_UID (
-        struct acpi_namespace_node      *device_node,
-        struct acpi_device_id           *uid);
-
-acpi_status
-acpi_ut_execute_sxds (
-        struct acpi_namespace_node      *device_node,
-        u8                              *highest);
+acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest);
 
 /*
- * ut_mutex - mutual exclusion interfaces
+ * utobject - internal object create/delete/cache routines
  */
+union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name,
+                                                              u32 line_number,
+                                                              u32 component_id,
+                                                              acpi_object_type
+                                                              type);
 
-acpi_status
-acpi_ut_mutex_initialize (
-        void);
+void *acpi_ut_allocate_object_desc_dbg(char *module_name,
+                                       u32 line_number, u32 component_id);
 
-void
-acpi_ut_mutex_terminate (
-        void);
+#define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_acpi_module_name,__LINE__,_COMPONENT,t)
+#define acpi_ut_allocate_object_desc()  acpi_ut_allocate_object_desc_dbg (_acpi_module_name,__LINE__,_COMPONENT)
 
-acpi_status
-acpi_ut_create_mutex (
-        acpi_mutex_handle               mutex_id);
+void acpi_ut_delete_object_desc(union acpi_operand_object *object);
 
-acpi_status
-acpi_ut_delete_mutex (
-        acpi_mutex_handle               mutex_id);
+u8 acpi_ut_valid_internal_object(void *object);
 
-acpi_status
-acpi_ut_acquire_mutex (
-        acpi_mutex_handle               mutex_id);
+union acpi_operand_object *acpi_ut_create_buffer_object(acpi_size buffer_size);
 
-acpi_status
-acpi_ut_release_mutex (
-        acpi_mutex_handle               mutex_id);
+union acpi_operand_object *acpi_ut_create_string_object(acpi_size string_size);
 
+acpi_status
+acpi_ut_get_object_size(union acpi_operand_object *obj, acpi_size * obj_length);
 
 /*
- * ut_object - internal object create/delete/cache routines
+ * utstate - Generic state creation/cache routines
  */
-
-union acpi_operand_object    *
-acpi_ut_create_internal_object_dbg (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id,
-        acpi_object_type                type);
-
-void *
-acpi_ut_allocate_object_desc_dbg (
-        char                            *module_name,
-        u32                             line_number,
-        u32                             component_id);
-
-#define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_THIS_MODULE,__LINE__,_COMPONENT,t)
-#define acpi_ut_allocate_object_desc()  acpi_ut_allocate_object_desc_dbg (_THIS_MODULE,__LINE__,_COMPONENT)
-
 void
-acpi_ut_delete_object_desc (
-        union acpi_operand_object       *object);
-
-u8
-acpi_ut_valid_internal_object (
-        void                            *object);
-
-union acpi_operand_object *
-acpi_ut_create_buffer_object (
-        acpi_size                       buffer_size);
+acpi_ut_push_generic_state(union acpi_generic_state **list_head,
+                           union acpi_generic_state *state);
 
-union acpi_operand_object *
-acpi_ut_create_string_object (
-        acpi_size                       string_size);
+union acpi_generic_state *acpi_ut_pop_generic_state(union acpi_generic_state
+                                                    **list_head);
 
+union acpi_generic_state *acpi_ut_create_generic_state(void);
 
-/*
- * ut_ref_cnt - Object reference count management
- */
-
-void
-acpi_ut_add_reference (
-        union acpi_operand_object       *object);
+struct acpi_thread_state *acpi_ut_create_thread_state(void);
 
-void
-acpi_ut_remove_reference (
-        union acpi_operand_object       *object);
+union acpi_generic_state *acpi_ut_create_update_state(union acpi_operand_object
+                                                      *object, u16 action);
 
-/*
- * ut_size - Object size routines
- */
+union acpi_generic_state *acpi_ut_create_pkg_state(void *internal_object,
+                                                   void *external_object,
+                                                   u16 index);
 
 acpi_status
-acpi_ut_get_simple_object_size (
-        union acpi_operand_object       *obj,
-        acpi_size                       *obj_length);
+acpi_ut_create_update_state_and_push(union acpi_operand_object *object,
+                                     u16 action,
+                                     union acpi_generic_state **state_list);
 
+#ifdef  ACPI_FUTURE_USAGE
 acpi_status
-acpi_ut_get_package_object_size (
-        union acpi_operand_object       *obj,
-        acpi_size                       *obj_length);
+acpi_ut_create_pkg_state_and_push(void *internal_object,
+                                  void *external_object,
+                                  u16 index,
+                                  union acpi_generic_state **state_list);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-acpi_status
-acpi_ut_get_object_size(
-        union acpi_operand_object       *obj,
-        acpi_size                       *obj_length);
-
-acpi_status
-acpi_ut_get_element_length (
-        u8                              object_type,
-        union acpi_operand_object       *source_object,
-        union acpi_generic_state        *state,
-        void                            *context);
+union acpi_generic_state *acpi_ut_create_control_state(void);
 
+void acpi_ut_delete_generic_state(union acpi_generic_state *state);
 
 /*
- * ut_state - Generic state creation/cache routines
+ * utmath
  */
-
-void
-acpi_ut_push_generic_state (
-        union acpi_generic_state        **list_head,
-        union acpi_generic_state        *state);
-
-union acpi_generic_state *
-acpi_ut_pop_generic_state (
-        union acpi_generic_state        **list_head);
-
-
-union acpi_generic_state *
-acpi_ut_create_generic_state (
-        void);
-
-struct acpi_thread_state *
-acpi_ut_create_thread_state (
-        void);
-
-union acpi_generic_state *
-acpi_ut_create_update_state (
-        union acpi_operand_object       *object,
-        u16                             action);
-
-union acpi_generic_state *
-acpi_ut_create_pkg_state (
-        void                            *internal_object,
-        void                            *external_object,
-        u16                             index);
-
 acpi_status
-acpi_ut_create_update_state_and_push (
-        union acpi_operand_object       *object,
-        u16                             action,
-        union acpi_generic_state        **state_list);
+acpi_ut_divide(acpi_integer in_dividend,
+               acpi_integer in_divisor,
+               acpi_integer * out_quotient, acpi_integer * out_remainder);
 
-#ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_ut_create_pkg_state_and_push (
-        void                            *internal_object,
-        void                            *external_object,
-        u16                             index,
-        union acpi_generic_state        **state_list);
-#endif
-
-union acpi_generic_state *
-acpi_ut_create_control_state (
-        void);
-
-void
-acpi_ut_delete_generic_state (
-        union acpi_generic_state        *state);
-
-#ifdef ACPI_ENABLE_OBJECT_CACHE
-void
-acpi_ut_delete_generic_state_cache (
-        void);
-
-void
-acpi_ut_delete_object_cache (
-        void);
-#endif
+acpi_ut_short_divide(acpi_integer in_dividend,
+                     u32 divisor,
+                     acpi_integer * out_quotient, u32 * out_remainder);
 
 /*
  * utmisc
  */
+acpi_status acpi_ut_allocate_owner_id(acpi_owner_id * owner_id);
 
-void
-acpi_ut_print_string (
-        char                            *string,
-        u8                              max_length);
+void acpi_ut_release_owner_id(acpi_owner_id * owner_id);
 
 acpi_status
-acpi_ut_divide (
-        acpi_integer                    in_dividend,
-        acpi_integer                    in_divisor,
-        acpi_integer                    *out_quotient,
-        acpi_integer                    *out_remainder);
+acpi_ut_walk_package_tree(union acpi_operand_object *source_object,
+                          void *target_object,
+                          acpi_pkg_callback walk_callback, void *context);
 
-acpi_status
-acpi_ut_short_divide (
-        acpi_integer                    in_dividend,
-        u32                             divisor,
-        acpi_integer                    *out_quotient,
-        u32                             *out_remainder);
+void acpi_ut_strupr(char *src_string);
+
+void acpi_ut_print_string(char *string, u8 max_length);
 
-u8
-acpi_ut_valid_acpi_name (
-        u32                             name);
+u8 acpi_ut_valid_acpi_name(u32 name);
 
-u8
-acpi_ut_valid_acpi_character (
-        char                            character);
+u8 acpi_ut_valid_acpi_character(char character);
 
 acpi_status
-acpi_ut_strtoul64 (
-        char                            *string,
-        u32                             base,
-        acpi_integer                    *ret_integer);
+acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer);
 
 /* Values for Base above (16=Hex, 10=Decimal) */
 
 #define ACPI_ANY_BASE        0
 
-#ifdef ACPI_FUTURE_USAGE
-char *
-acpi_ut_strupr (
-        char                            *src_string);
-#endif
-
-u8 *
-acpi_ut_get_resource_end_tag (
-        union acpi_operand_object       *obj_desc);
+u8 *acpi_ut_get_resource_end_tag(union acpi_operand_object *obj_desc);
 
-u8
-acpi_ut_generate_checksum (
-        u8                              *buffer,
-        u32                             length);
+u8 acpi_ut_generate_checksum(u8 * buffer, u32 length);
 
-u32
-acpi_ut_dword_byte_swap (
-        u32                             value);
+u32 acpi_ut_dword_byte_swap(u32 value);
 
-void
-acpi_ut_set_integer_width (
-        u8                              revision);
+void acpi_ut_set_integer_width(u8 revision);
 
 #ifdef ACPI_DEBUG_OUTPUT
 void
-acpi_ut_display_init_pathname (
-        u8                              type,
-        struct acpi_namespace_node      *obj_handle,
-        char                            *path);
+acpi_ut_display_init_pathname(u8 type,
+                              struct acpi_namespace_node *obj_handle,
+                              char *path);
 
 #endif
 
-
 /*
- * Utalloc - memory allocation and object caching
+ * utmutex - mutex support
  */
+acpi_status acpi_ut_mutex_initialize(void);
 
-void *
-acpi_ut_acquire_from_cache (
-        u32                             list_id);
+void acpi_ut_mutex_terminate(void);
 
-void
-acpi_ut_release_to_cache (
-        u32                             list_id,
-        void                            *object);
-
-#ifdef ACPI_ENABLE_OBJECT_CACHE
-void
-acpi_ut_delete_generic_cache (
-        u32                             list_id);
-#endif
+acpi_status acpi_ut_acquire_mutex(acpi_mutex_handle mutex_id);
 
-acpi_status
-acpi_ut_validate_buffer (
-        struct acpi_buffer              *buffer);
+acpi_status acpi_ut_release_mutex(acpi_mutex_handle mutex_id);
 
-acpi_status
-acpi_ut_initialize_buffer (
-        struct acpi_buffer              *buffer,
-        acpi_size                       required_length);
+/*
+ * utalloc - memory allocation and object caching
+ */
+acpi_status acpi_ut_create_caches(void);
 
+acpi_status acpi_ut_delete_caches(void);
 
-/* Memory allocation functions */
+acpi_status acpi_ut_validate_buffer(struct acpi_buffer *buffer);
 
-void *
-acpi_ut_allocate (
-        acpi_size                       size,
-        u32                             component,
-        char                            *module,
-        u32                             line);
+acpi_status
+acpi_ut_initialize_buffer(struct acpi_buffer *buffer,
+                          acpi_size required_length);
 
-void *
-acpi_ut_callocate (
-        acpi_size                       size,
-        u32                             component,
-        char                            *module,
-        u32                             line);
+void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line);
 
+void *acpi_ut_callocate(acpi_size size, u32 component, char *module, u32 line);
 
 #ifdef ACPI_DBG_TRACK_ALLOCATIONS
+void *acpi_ut_allocate_and_track(acpi_size size,
+                                 u32 component, char *module, u32 line);
 
-void *
-acpi_ut_allocate_and_track (
-        acpi_size                       size,
-        u32                             component,
-        char                            *module,
-        u32                             line);
-
-void *
-acpi_ut_callocate_and_track (
-        acpi_size                       size,
-        u32                             component,
-        char                            *module,
-        u32                             line);
+void *acpi_ut_callocate_and_track(acpi_size size,
+                                  u32 component, char *module, u32 line);
 
 void
-acpi_ut_free_and_track (
-        void                            *address,
-        u32                             component,
-        char                            *module,
-        u32                             line);
+acpi_ut_free_and_track(void *address, u32 component, char *module, u32 line);
 
-struct acpi_debug_mem_block *
-acpi_ut_find_allocation (
-        u32                             list_id,
-        void                            *allocation);
+#ifdef  ACPI_FUTURE_USAGE
+void acpi_ut_dump_allocation_info(void);
+#endif                          /* ACPI_FUTURE_USAGE */
 
-acpi_status
-acpi_ut_track_allocation (
-        u32                             list_id,
-        struct acpi_debug_mem_block     *address,
-        acpi_size                       size,
-        u8                              alloc_type,
-        u32                             component,
-        char                            *module,
-        u32                             line);
-
-acpi_status
-acpi_ut_remove_allocation (
-        u32                             list_id,
-        struct acpi_debug_mem_block     *address,
-        u32                             component,
-        char                            *module,
-        u32                             line);
-
-#ifdef ACPI_FUTURE_USAGE
-void
-acpi_ut_dump_allocation_info (
-        void);
+void acpi_ut_dump_allocations(u32 component, char *module);
 #endif
 
-void
-acpi_ut_dump_allocations (
-        u32                             component,
-        char                            *module);
-#endif
-
-
-#endif /* _ACUTILS_H */
+#endif                          /* _ACUTILS_H */
diff --git a/include/acpi/amlcode.h b/include/acpi/amlcode.h
index 2ec538eac58e..7fdf5299f501 100644
--- a/include/acpi/amlcode.h
+++ b/include/acpi/amlcode.h
@@ -59,17 +59,17 @@
 #define AML_WORD_OP                 (u16) 0x0b
 #define AML_DWORD_OP                (u16) 0x0c
 #define AML_STRING_OP               (u16) 0x0d
-#define AML_QWORD_OP                (u16) 0x0e     /* ACPI 2.0 */
+#define AML_QWORD_OP                (u16) 0x0e  /* ACPI 2.0 */
 #define AML_SCOPE_OP                (u16) 0x10
 #define AML_BUFFER_OP               (u16) 0x11
 #define AML_PACKAGE_OP              (u16) 0x12
-#define AML_VAR_PACKAGE_OP          (u16) 0x13     /* ACPI 2.0 */
+#define AML_VAR_PACKAGE_OP          (u16) 0x13  /* ACPI 2.0 */
 #define AML_METHOD_OP               (u16) 0x14
 #define AML_DUAL_NAME_PREFIX        (u16) 0x2e
 #define AML_MULTI_NAME_PREFIX_OP    (u16) 0x2f
 #define AML_NAME_CHAR_SUBSEQ        (u16) 0x30
 #define AML_NAME_CHAR_FIRST         (u16) 0x41
-#define AML_OP_PREFIX               (u16) 0x5b
+#define AML_EXTENDED_OP_PREFIX      (u16) 0x5b
 #define AML_ROOT_PREFIX             (u16) 0x5c
 #define AML_PARENT_PREFIX           (u16) 0x5e
 #define AML_LOCAL_OP                (u16) 0x60
@@ -109,8 +109,8 @@
 #define AML_FIND_SET_LEFT_BIT_OP    (u16) 0x81
 #define AML_FIND_SET_RIGHT_BIT_OP   (u16) 0x82
 #define AML_DEREF_OF_OP             (u16) 0x83
-#define AML_CONCAT_RES_OP           (u16) 0x84     /* ACPI 2.0 */
-#define AML_MOD_OP                  (u16) 0x85     /* ACPI 2.0 */
+#define AML_CONCAT_RES_OP           (u16) 0x84  /* ACPI 2.0 */
+#define AML_MOD_OP                  (u16) 0x85  /* ACPI 2.0 */
 #define AML_NOTIFY_OP               (u16) 0x86
 #define AML_SIZE_OF_OP              (u16) 0x87
 #define AML_INDEX_OP                (u16) 0x88
@@ -120,21 +120,21 @@
 #define AML_CREATE_BYTE_FIELD_OP    (u16) 0x8c
 #define AML_CREATE_BIT_FIELD_OP     (u16) 0x8d
 #define AML_TYPE_OP                 (u16) 0x8e
-#define AML_CREATE_QWORD_FIELD_OP   (u16) 0x8f     /* ACPI 2.0 */
+#define AML_CREATE_QWORD_FIELD_OP   (u16) 0x8f  /* ACPI 2.0 */
 #define AML_LAND_OP                 (u16) 0x90
 #define AML_LOR_OP                  (u16) 0x91
 #define AML_LNOT_OP                 (u16) 0x92
 #define AML_LEQUAL_OP               (u16) 0x93
 #define AML_LGREATER_OP             (u16) 0x94
 #define AML_LLESS_OP                (u16) 0x95
-#define AML_TO_BUFFER_OP            (u16) 0x96     /* ACPI 2.0 */
-#define AML_TO_DECSTRING_OP         (u16) 0x97     /* ACPI 2.0 */
-#define AML_TO_HEXSTRING_OP         (u16) 0x98     /* ACPI 2.0 */
-#define AML_TO_INTEGER_OP           (u16) 0x99     /* ACPI 2.0 */
-#define AML_TO_STRING_OP            (u16) 0x9c     /* ACPI 2.0 */
-#define AML_COPY_OP                 (u16) 0x9d     /* ACPI 2.0 */
-#define AML_MID_OP                  (u16) 0x9e     /* ACPI 2.0 */
-#define AML_CONTINUE_OP             (u16) 0x9f     /* ACPI 2.0 */
+#define AML_TO_BUFFER_OP            (u16) 0x96  /* ACPI 2.0 */
+#define AML_TO_DECSTRING_OP         (u16) 0x97  /* ACPI 2.0 */
+#define AML_TO_HEXSTRING_OP         (u16) 0x98  /* ACPI 2.0 */
+#define AML_TO_INTEGER_OP           (u16) 0x99  /* ACPI 2.0 */
+#define AML_TO_STRING_OP            (u16) 0x9c  /* ACPI 2.0 */
+#define AML_COPY_OP                 (u16) 0x9d  /* ACPI 2.0 */
+#define AML_MID_OP                  (u16) 0x9e  /* ACPI 2.0 */
+#define AML_CONTINUE_OP             (u16) 0x9f  /* ACPI 2.0 */
 #define AML_IF_OP                   (u16) 0xa0
 #define AML_ELSE_OP                 (u16) 0xa1
 #define AML_WHILE_OP                (u16) 0xa2
@@ -146,8 +146,7 @@
 
 /* prefixed opcodes */
 
-#define AML_EXTOP                   (u16) 0x005b
-
+#define AML_EXTENDED_OPCODE         (u16) 0x5b00        /* prefix for 2-byte opcodes */
 
 #define AML_MUTEX_OP                (u16) 0x5b01
 #define AML_EVENT_OP                (u16) 0x5b02
@@ -155,7 +154,7 @@
 #define AML_SHIFT_LEFT_BIT_OP       (u16) 0x5b11
 #define AML_COND_REF_OF_OP          (u16) 0x5b12
 #define AML_CREATE_FIELD_OP         (u16) 0x5b13
-#define AML_LOAD_TABLE_OP           (u16) 0x5b1f     /* ACPI 2.0 */
+#define AML_LOAD_TABLE_OP           (u16) 0x5b1f        /* ACPI 2.0 */
 #define AML_LOAD_OP                 (u16) 0x5b20
 #define AML_STALL_OP                (u16) 0x5b21
 #define AML_SLEEP_OP                (u16) 0x5b22
@@ -170,7 +169,7 @@
 #define AML_REVISION_OP             (u16) 0x5b30
 #define AML_DEBUG_OP                (u16) 0x5b31
 #define AML_FATAL_OP                (u16) 0x5b32
-#define AML_TIMER_OP                (u16) 0x5b33     /* ACPI 3.0 */
+#define AML_TIMER_OP                (u16) 0x5b33        /* ACPI 3.0 */
 #define AML_REGION_OP               (u16) 0x5b80
 #define AML_FIELD_OP                (u16) 0x5b81
 #define AML_DEVICE_OP               (u16) 0x5b82
@@ -179,8 +178,7 @@
 #define AML_THERMAL_ZONE_OP         (u16) 0x5b85
 #define AML_INDEX_FIELD_OP          (u16) 0x5b86
 #define AML_BANK_FIELD_OP           (u16) 0x5b87
-#define AML_DATA_REGION_OP          (u16) 0x5b88     /* ACPI 2.0 */
-
+#define AML_DATA_REGION_OP          (u16) 0x5b88        /* ACPI 2.0 */
 
 /* Bogus opcodes (they are actually two separate opcodes) */
 
@@ -188,13 +186,11 @@
 #define AML_LLESSEQUAL_OP           (u16) 0x9294
 #define AML_LNOTEQUAL_OP            (u16) 0x9293
 
-
 /*
  * Internal opcodes
  * Use only "Unknown" AML opcodes, don't attempt to use
  * any valid ACPI ASCII values (A-Z, 0-9, '-')
  */
-
 #define AML_INT_NAMEPATH_OP         (u16) 0x002d
 #define AML_INT_NAMEDFIELD_OP       (u16) 0x0030
 #define AML_INT_RESERVEDFIELD_OP    (u16) 0x0031
@@ -205,7 +201,6 @@
 #define AML_INT_RETURN_VALUE_OP     (u16) 0x0036
 #define AML_INT_EVAL_SUBTREE_OP     (u16) 0x0037
 
-
 #define ARG_NONE                    0x0
 
 /*
@@ -214,7 +209,6 @@
  * There can be up to 31 unique argument types
  * Zero is reserved as end-of-list indicator
  */
-
 #define ARGP_BYTEDATA               0x01
 #define ARGP_BYTELIST               0x02
 #define ARGP_CHARLIST               0x03
@@ -248,7 +242,7 @@
 
 /* Single, simple types */
 
-#define ARGI_ANYTYPE                0x01    /* Don't care */
+#define ARGI_ANYTYPE                0x01        /* Don't care */
 #define ARGI_PACKAGE                0x02
 #define ARGI_EVENT                  0x03
 #define ARGI_MUTEX                  0x04
@@ -259,8 +253,8 @@
 #define ARGI_INTEGER                0x06
 #define ARGI_STRING                 0x07
 #define ARGI_BUFFER                 0x08
-#define ARGI_BUFFER_OR_STRING       0x09    /* Used by MID op only */
-#define ARGI_COMPUTEDATA            0x0A    /* Buffer, String, or Integer */
+#define ARGI_BUFFER_OR_STRING       0x09        /* Used by MID op only */
+#define ARGI_COMPUTEDATA            0x0A        /* Buffer, String, or Integer */
 
 /* Reference objects */
 
@@ -268,39 +262,35 @@
 #define ARGI_OBJECT_REF             0x0C
 #define ARGI_DEVICE_REF             0x0D
 #define ARGI_REFERENCE              0x0E
-#define ARGI_TARGETREF              0x0F    /* Target, subject to implicit conversion */
-#define ARGI_FIXED_TARGET           0x10    /* Target, no implicit conversion */
-#define ARGI_SIMPLE_TARGET          0x11    /* Name, Local, Arg -- no implicit conversion */
+#define ARGI_TARGETREF              0x0F        /* Target, subject to implicit conversion */
+#define ARGI_FIXED_TARGET           0x10        /* Target, no implicit conversion */
+#define ARGI_SIMPLE_TARGET          0x11        /* Name, Local, Arg -- no implicit conversion */
 
 /* Multiple/complex types */
 
-#define ARGI_DATAOBJECT             0x12    /* Buffer, String, package or reference to a Node - Used only by size_of operator*/
-#define ARGI_COMPLEXOBJ             0x13    /* Buffer, String, or package (Used by INDEX op only) */
-#define ARGI_REF_OR_STRING          0x14    /* Reference or String (Used by DEREFOF op only) */
-#define ARGI_REGION_OR_FIELD        0x15    /* Used by LOAD op only */
+#define ARGI_DATAOBJECT             0x12        /* Buffer, String, package or reference to a Node - Used only by size_of operator */
+#define ARGI_COMPLEXOBJ             0x13        /* Buffer, String, or package (Used by INDEX op only) */
+#define ARGI_REF_OR_STRING          0x14        /* Reference or String (Used by DEREFOF op only) */
+#define ARGI_REGION_OR_FIELD        0x15        /* Used by LOAD op only */
 #define ARGI_DATAREFOBJ             0x16
 
 /* Note: types above can expand to 0x1F maximum */
 
 #define ARGI_INVALID_OPCODE         0xFFFFFFFF
 
-
 /*
  * hash offsets
  */
 #define AML_EXTOP_HASH_OFFSET       22
 #define AML_LNOT_HASH_OFFSET        19
 
-
 /*
  * opcode groups and types
  */
-
 #define OPGRP_NAMED                 0x01
 #define OPGRP_FIELD                 0x02
 #define OPGRP_BYTELIST              0x04
 
-
 /*
  * Opcode information
  */
@@ -326,31 +316,30 @@
 /* Convenient flag groupings */
 
 #define AML_FLAGS_EXEC_0A_0T_1R                                     AML_HAS_RETVAL
-#define AML_FLAGS_EXEC_1A_0T_0R     AML_HAS_ARGS                                   /* Monadic1  */
-#define AML_FLAGS_EXEC_1A_0T_1R     AML_HAS_ARGS |                  AML_HAS_RETVAL /* Monadic2  */
+#define AML_FLAGS_EXEC_1A_0T_0R     AML_HAS_ARGS        /* Monadic1  */
+#define AML_FLAGS_EXEC_1A_0T_1R     AML_HAS_ARGS |                  AML_HAS_RETVAL      /* Monadic2  */
 #define AML_FLAGS_EXEC_1A_1T_0R     AML_HAS_ARGS | AML_HAS_TARGET
-#define AML_FLAGS_EXEC_1A_1T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL /* monadic2_r */
-#define AML_FLAGS_EXEC_2A_0T_0R     AML_HAS_ARGS                                   /* Dyadic1   */
-#define AML_FLAGS_EXEC_2A_0T_1R     AML_HAS_ARGS |                  AML_HAS_RETVAL /* Dyadic2   */
-#define AML_FLAGS_EXEC_2A_1T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL /* dyadic2_r  */
+#define AML_FLAGS_EXEC_1A_1T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL      /* monadic2_r */
+#define AML_FLAGS_EXEC_2A_0T_0R     AML_HAS_ARGS        /* Dyadic1   */
+#define AML_FLAGS_EXEC_2A_0T_1R     AML_HAS_ARGS |                  AML_HAS_RETVAL      /* Dyadic2   */
+#define AML_FLAGS_EXEC_2A_1T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL      /* dyadic2_r  */
 #define AML_FLAGS_EXEC_2A_2T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL
 #define AML_FLAGS_EXEC_3A_0T_0R     AML_HAS_ARGS
 #define AML_FLAGS_EXEC_3A_1T_1R     AML_HAS_ARGS | AML_HAS_TARGET | AML_HAS_RETVAL
 #define AML_FLAGS_EXEC_6A_0T_1R     AML_HAS_ARGS |                  AML_HAS_RETVAL
 
-
 /*
  * The opcode Type is used in a dispatch table, do not change
  * without updating the table.
  */
 #define AML_TYPE_EXEC_0A_0T_1R      0x00
-#define AML_TYPE_EXEC_1A_0T_0R      0x01 /* Monadic1  */
-#define AML_TYPE_EXEC_1A_0T_1R      0x02 /* Monadic2  */
+#define AML_TYPE_EXEC_1A_0T_0R      0x01        /* Monadic1  */
+#define AML_TYPE_EXEC_1A_0T_1R      0x02        /* Monadic2  */
 #define AML_TYPE_EXEC_1A_1T_0R      0x03
-#define AML_TYPE_EXEC_1A_1T_1R      0x04 /* monadic2_r */
-#define AML_TYPE_EXEC_2A_0T_0R      0x05 /* Dyadic1   */
-#define AML_TYPE_EXEC_2A_0T_1R      0x06 /* Dyadic2   */
-#define AML_TYPE_EXEC_2A_1T_1R      0x07 /* dyadic2_r  */
+#define AML_TYPE_EXEC_1A_1T_1R      0x04        /* monadic2_r */
+#define AML_TYPE_EXEC_2A_0T_0R      0x05        /* Dyadic1   */
+#define AML_TYPE_EXEC_2A_0T_1R      0x06        /* Dyadic2   */
+#define AML_TYPE_EXEC_2A_1T_1R      0x07        /* dyadic2_r  */
 #define AML_TYPE_EXEC_2A_2T_1R      0x08
 #define AML_TYPE_EXEC_3A_0T_0R      0x09
 #define AML_TYPE_EXEC_3A_1T_1R      0x0A
@@ -381,6 +370,12 @@
 #define AML_TYPE_UNDEFINED          0x19
 #define AML_TYPE_BOGUS              0x1A
 
+/* AML Package Length encodings */
+
+#define ACPI_AML_PACKAGE_TYPE1      0x40
+#define ACPI_AML_PACKAGE_TYPE2      0x4000
+#define ACPI_AML_PACKAGE_TYPE3      0x400000
+#define ACPI_AML_PACKAGE_TYPE4      0x40000000
 
 /*
  * Opcode classes
@@ -397,40 +392,33 @@
 #define AML_CLASS_METHOD_CALL       0x09
 #define AML_CLASS_UNKNOWN           0x0A
 
-
 /* Predefined Operation Region space_iDs */
 
-typedef enum
-{
-        REGION_MEMORY                   = 0,
+typedef enum {
+        REGION_MEMORY = 0,
         REGION_IO,
         REGION_PCI_CONFIG,
         REGION_EC,
         REGION_SMBUS,
         REGION_CMOS,
         REGION_PCI_BAR,
-        REGION_DATA_TABLE,              /* Internal use only */
-        REGION_FIXED_HW                 = 0x7F
-
+        REGION_DATA_TABLE,      /* Internal use only */
+        REGION_FIXED_HW = 0x7F
 } AML_REGION_TYPES;
 
-
 /* Comparison operation codes for match_op operator */
 
-typedef enum
-{
-        MATCH_MTR                       = 0,
-        MATCH_MEQ                       = 1,
-        MATCH_MLE                       = 2,
-        MATCH_MLT                       = 3,
-        MATCH_MGE                       = 4,
-        MATCH_MGT                       = 5
-
+typedef enum {
+        MATCH_MTR = 0,
+        MATCH_MEQ = 1,
+        MATCH_MLE = 2,
+        MATCH_MLT = 3,
+        MATCH_MGE = 4,
+        MATCH_MGT = 5
 } AML_MATCH_OPERATOR;
 
 #define MAX_MATCH_OPERATOR          5
 
-
 /*
  * field_flags
  *
@@ -448,60 +436,47 @@ typedef enum
 #define AML_FIELD_LOCK_RULE_MASK    0x10
 #define AML_FIELD_UPDATE_RULE_MASK  0x60
 
-
 /* 1) Field Access Types */
 
-typedef enum
-{
-        AML_FIELD_ACCESS_ANY            = 0x00,
-        AML_FIELD_ACCESS_BYTE           = 0x01,
-        AML_FIELD_ACCESS_WORD           = 0x02,
-        AML_FIELD_ACCESS_DWORD          = 0x03,
-        AML_FIELD_ACCESS_QWORD          = 0x04,    /* ACPI 2.0 */
-        AML_FIELD_ACCESS_BUFFER         = 0x05     /* ACPI 2.0 */
-
+typedef enum {
+        AML_FIELD_ACCESS_ANY = 0x00,
+        AML_FIELD_ACCESS_BYTE = 0x01,
+        AML_FIELD_ACCESS_WORD = 0x02,
+        AML_FIELD_ACCESS_DWORD = 0x03,
+        AML_FIELD_ACCESS_QWORD = 0x04,  /* ACPI 2.0 */
+        AML_FIELD_ACCESS_BUFFER = 0x05  /* ACPI 2.0 */
 } AML_ACCESS_TYPE;
 
-
 /* 2) Field Lock Rules */
 
-typedef enum
-{
-        AML_FIELD_LOCK_NEVER            = 0x00,
-        AML_FIELD_LOCK_ALWAYS           = 0x10
-
+typedef enum {
+        AML_FIELD_LOCK_NEVER = 0x00,
+        AML_FIELD_LOCK_ALWAYS = 0x10
 } AML_LOCK_RULE;
 
-
 /* 3) Field Update Rules */
 
-typedef enum
-{
-        AML_FIELD_UPDATE_PRESERVE       = 0x00,
-        AML_FIELD_UPDATE_WRITE_AS_ONES  = 0x20,
+typedef enum {
+        AML_FIELD_UPDATE_PRESERVE = 0x00,
+        AML_FIELD_UPDATE_WRITE_AS_ONES = 0x20,
         AML_FIELD_UPDATE_WRITE_AS_ZEROS = 0x40
-
 } AML_UPDATE_RULE;
 
-
 /*
  * Field Access Attributes.
  * This byte is extracted from the AML via the
  * access_as keyword
  */
-typedef enum
-{
-        AML_FIELD_ATTRIB_SMB_QUICK      = 0x02,
-        AML_FIELD_ATTRIB_SMB_SEND_RCV   = 0x04,
-        AML_FIELD_ATTRIB_SMB_BYTE       = 0x06,
-        AML_FIELD_ATTRIB_SMB_WORD       = 0x08,
-        AML_FIELD_ATTRIB_SMB_BLOCK      = 0x0A,
-        AML_FIELD_ATTRIB_SMB_WORD_CALL  = 0x0C,
+typedef enum {
+        AML_FIELD_ATTRIB_SMB_QUICK = 0x02,
+        AML_FIELD_ATTRIB_SMB_SEND_RCV = 0x04,
+        AML_FIELD_ATTRIB_SMB_BYTE = 0x06,
+        AML_FIELD_ATTRIB_SMB_WORD = 0x08,
+        AML_FIELD_ATTRIB_SMB_BLOCK = 0x0A,
+        AML_FIELD_ATTRIB_SMB_WORD_CALL = 0x0C,
         AML_FIELD_ATTRIB_SMB_BLOCK_CALL = 0x0D
-
 } AML_ACCESS_ATTRIBUTE;
 
-
 /* Bit fields in method_flags byte */
 
 #define AML_METHOD_ARG_COUNT        0x07
@@ -514,5 +489,4 @@ typedef enum
 #define AML_METHOD_RESERVED1        0x02
 #define AML_METHOD_RESERVED2        0x04
 
-
-#endif /* __AMLCODE_H__ */
+#endif                          /* __AMLCODE_H__ */
diff --git a/include/acpi/amlresrc.h b/include/acpi/amlresrc.h
index b20ec303df07..051786e4b210 100644
--- a/include/acpi/amlresrc.h
+++ b/include/acpi/amlresrc.h
@@ -42,29 +42,27 @@
  * POSSIBILITY OF SUCH DAMAGES.
  */
 
-
 #ifndef __AMLRESRC_H
 #define __AMLRESRC_H
 
-
 #define ASL_RESNAME_ADDRESS                     "_ADR"
 #define ASL_RESNAME_ALIGNMENT                   "_ALN"
 #define ASL_RESNAME_ADDRESSSPACE                "_ASI"
 #define ASL_RESNAME_ACCESSSIZE                  "_ASZ"
 #define ASL_RESNAME_TYPESPECIFICATTRIBUTES      "_ATT"
 #define ASL_RESNAME_BASEADDRESS                 "_BAS"
-#define ASL_RESNAME_BUSMASTER                   "_BM_"  /* Master(1), Slave(0) */
+#define ASL_RESNAME_BUSMASTER                   "_BM_"  /* Master(1), Slave(0) */
 #define ASL_RESNAME_DECODE                      "_DEC"
 #define ASL_RESNAME_DMA                         "_DMA"
-#define ASL_RESNAME_DMATYPE                     "_TYP"  /* Compatible(0), A(1), B(2), F(3) */
+#define ASL_RESNAME_DMATYPE                     "_TYP"  /* Compatible(0), A(1), B(2), F(3) */
 #define ASL_RESNAME_GRANULARITY                 "_GRA"
 #define ASL_RESNAME_INTERRUPT                   "_INT"
-#define ASL_RESNAME_INTERRUPTLEVEL              "_LL_"  /* active_lo(1), active_hi(0) */
-#define ASL_RESNAME_INTERRUPTSHARE              "_SHR"  /* Shareable(1), no_share(0) */
-#define ASL_RESNAME_INTERRUPTTYPE               "_HE_"  /* Edge(1), Level(0) */
+#define ASL_RESNAME_INTERRUPTLEVEL              "_LL_"  /* active_lo(1), active_hi(0) */
+#define ASL_RESNAME_INTERRUPTSHARE              "_SHR"  /* Shareable(1), no_share(0) */
+#define ASL_RESNAME_INTERRUPTTYPE               "_HE_"  /* Edge(1), Level(0) */
 #define ASL_RESNAME_LENGTH                      "_LEN"
-#define ASL_RESNAME_MEMATTRIBUTES               "_MTP"  /* Memory(0), Reserved(1), ACPI(2), NVS(3) */
-#define ASL_RESNAME_MEMTYPE                     "_MEM"  /* non_cache(0), Cacheable(1) Cache+combine(2), Cache+prefetch(3) */
+#define ASL_RESNAME_MEMATTRIBUTES               "_MTP"  /* Memory(0), Reserved(1), ACPI(2), NVS(3) */
+#define ASL_RESNAME_MEMTYPE                     "_MEM"  /* non_cache(0), Cacheable(1) Cache+combine(2), Cache+prefetch(3) */
 #define ASL_RESNAME_MAXADDR                     "_MAX"
 #define ASL_RESNAME_MINADDR                     "_MIN"
 #define ASL_RESNAME_MAXTYPE                     "_MAF"
@@ -72,12 +70,11 @@
 #define ASL_RESNAME_REGISTERBITOFFSET           "_RBO"
 #define ASL_RESNAME_REGISTERBITWIDTH            "_RBW"
 #define ASL_RESNAME_RANGETYPE                   "_RNG"
-#define ASL_RESNAME_READWRITETYPE               "_RW_"  /* read_only(0), Writeable (1) */
+#define ASL_RESNAME_READWRITETYPE               "_RW_"  /* read_only(0), Writeable (1) */
 #define ASL_RESNAME_TRANSLATION                 "_TRA"
-#define ASL_RESNAME_TRANSTYPE                   "_TRS"  /* Sparse(1), Dense(0) */
-#define ASL_RESNAME_TYPE                        "_TTP"  /* Translation(1), Static (0) */
-#define ASL_RESNAME_XFERTYPE                    "_SIz"  /* 8(0), 8_and16(1), 16(2) */
-
+#define ASL_RESNAME_TRANSTYPE                   "_TRS"  /* Sparse(1), Dense(0) */
+#define ASL_RESNAME_TYPE                        "_TTP"  /* Translation(1), Static (0) */
+#define ASL_RESNAME_XFERTYPE                    "_SIz"  /* 8(0), 8_and16(1), 16(2) */
 
 /* Default sizes for "small" resource descriptors */
 
@@ -89,15 +86,12 @@
 #define ASL_RDESC_FIXED_IO_SIZE                 0x03
 #define ASL_RDESC_END_TAG_SIZE                  0x01
 
-
-struct asl_resource_node
-{
-        u32                                 buffer_length;
-        void                                *buffer;
-        struct asl_resource_node            *next;
+struct asl_resource_node {
+        u32 buffer_length;
+        void *buffer;
+        struct asl_resource_node *next;
 };
 
-
 /*
  * Resource descriptors defined in the ACPI specification.
  *
@@ -106,214 +100,175 @@ struct asl_resource_node
  */
 #pragma pack(1)
 
-struct asl_irq_format_desc
-{
-        u8                                  descriptor_type;
-        u16                                 irq_mask;
-        u8                                  flags;
+struct asl_irq_format_desc {
+        u8 descriptor_type;
+        u16 irq_mask;
+        u8 flags;
 };
 
-
-struct asl_irq_noflags_desc
-{
-        u8                                  descriptor_type;
-        u16                                 irq_mask;
+struct asl_irq_noflags_desc {
+        u8 descriptor_type;
+        u16 irq_mask;
 };
 
-
-struct asl_dma_format_desc
-{
-        u8                                  descriptor_type;
-        u8                                  dma_channel_mask;
-        u8                                  flags;
+struct asl_dma_format_desc {
+        u8 descriptor_type;
+        u8 dma_channel_mask;
+        u8 flags;
 };
 
-
-struct asl_start_dependent_desc
-{
-        u8                                  descriptor_type;
-        u8                                  flags;
+struct asl_start_dependent_desc {
+        u8 descriptor_type;
+        u8 flags;
 };
 
-
-struct asl_start_dependent_noprio_desc
-{
-        u8                                  descriptor_type;
+struct asl_start_dependent_noprio_desc {
+        u8 descriptor_type;
 };
 
-
-struct asl_end_dependent_desc
-{
-        u8                                  descriptor_type;
+struct asl_end_dependent_desc {
+        u8 descriptor_type;
 };
 
-
-struct asl_io_port_desc
-{
-        u8                                  descriptor_type;
-        u8                                  information;
-        u16                                 address_min;
-        u16                                 address_max;
-        u8                                  alignment;
-        u8                                  length;
+struct asl_io_port_desc {
+        u8 descriptor_type;
+        u8 information;
+        u16 address_min;
+        u16 address_max;
+        u8 alignment;
+        u8 length;
 };
 
-
-struct asl_fixed_io_port_desc
-{
-        u8                                  descriptor_type;
-        u16                                 base_address;
-        u8                                  length;
+struct asl_fixed_io_port_desc {
+        u8 descriptor_type;
+        u16 base_address;
+        u8 length;
 };
 
-
-struct asl_small_vendor_desc
-{
-        u8                                  descriptor_type;
-        u8                                  vendor_defined[7];
+struct asl_small_vendor_desc {
+        u8 descriptor_type;
+        u8 vendor_defined[7];
 };
 
-
-struct asl_end_tag_desc
-{
-        u8                                  descriptor_type;
-        u8                                  checksum;
+struct asl_end_tag_desc {
+        u8 descriptor_type;
+        u8 checksum;
 };
 
-
 /* LARGE descriptors */
 
-struct asl_memory_24_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  information;
-        u16                                 address_min;
-        u16                                 address_max;
-        u16                                 alignment;
-        u16                                 range_length;
+struct asl_memory_24_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 information;
+        u16 address_min;
+        u16 address_max;
+        u16 alignment;
+        u16 range_length;
 };
 
-
-struct asl_large_vendor_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  vendor_defined[1];
+struct asl_large_vendor_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 vendor_defined[1];
 };
 
-
-struct asl_memory_32_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  information;
-        u32                                 address_min;
-        u32                                 address_max;
-        u32                                 alignment;
-        u32                                 range_length;
+struct asl_memory_32_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 information;
+        u32 address_min;
+        u32 address_max;
+        u32 alignment;
+        u32 range_length;
 };
 
-
-struct asl_fixed_memory_32_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  information;
-        u32                                 base_address;
-        u32                                 range_length;
+struct asl_fixed_memory_32_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 information;
+        u32 base_address;
+        u32 range_length;
 };
 
-
-struct asl_extended_address_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  resource_type;
-        u8                                  flags;
-        u8                                  specific_flags;
-        u8                                  revision_iD;
-        u8                                  reserved;
-        u64                                 granularity;
-        u64                                 address_min;
-        u64                                 address_max;
-        u64                                 translation_offset;
-        u64                                 address_length;
-        u64                                 type_specific_attributes;
-        u8                                  optional_fields[2]; /* Used for length calculation only */
+struct asl_extended_address_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 resource_type;
+        u8 flags;
+        u8 specific_flags;
+        u8 revision_iD;
+        u8 reserved;
+        u64 granularity;
+        u64 address_min;
+        u64 address_max;
+        u64 translation_offset;
+        u64 address_length;
+        u64 type_specific_attributes;
+        u8 optional_fields[2];  /* Used for length calculation only */
 };
 
-#define ASL_EXTENDED_ADDRESS_DESC_REVISION          1       /* ACPI 3.0 */
-
-
-struct asl_qword_address_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  resource_type;
-        u8                                  flags;
-        u8                                  specific_flags;
-        u64                                 granularity;
-        u64                                 address_min;
-        u64                                 address_max;
-        u64                                 translation_offset;
-        u64                                 address_length;
-        u8                                  optional_fields[2];
+#define ASL_EXTENDED_ADDRESS_DESC_REVISION          1   /* ACPI 3.0 */
+
+struct asl_qword_address_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 resource_type;
+        u8 flags;
+        u8 specific_flags;
+        u64 granularity;
+        u64 address_min;
+        u64 address_max;
+        u64 translation_offset;
+        u64 address_length;
+        u8 optional_fields[2];
 };
 
-
-struct asl_dword_address_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  resource_type;
-        u8                                  flags;
-        u8                                  specific_flags;
-        u32                                 granularity;
-        u32                                 address_min;
-        u32                                 address_max;
-        u32                                 translation_offset;
-        u32                                 address_length;
-        u8                                  optional_fields[2];
+struct asl_dword_address_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 resource_type;
+        u8 flags;
+        u8 specific_flags;
+        u32 granularity;
+        u32 address_min;
+        u32 address_max;
+        u32 translation_offset;
+        u32 address_length;
+        u8 optional_fields[2];
 };
 
-
-struct asl_word_address_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  resource_type;
-        u8                                  flags;
-        u8                                  specific_flags;
-        u16                                 granularity;
-        u16                                 address_min;
-        u16                                 address_max;
-        u16                                 translation_offset;
-        u16                                 address_length;
-        u8                                  optional_fields[2];
+struct asl_word_address_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 resource_type;
+        u8 flags;
+        u8 specific_flags;
+        u16 granularity;
+        u16 address_min;
+        u16 address_max;
+        u16 translation_offset;
+        u16 address_length;
+        u8 optional_fields[2];
 };
 
-
-struct asl_extended_xrupt_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  flags;
-        u8                                  table_length;
-        u32                                 interrupt_number[1];
+struct asl_extended_xrupt_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 flags;
+        u8 table_length;
+        u32 interrupt_number[1];
         /* res_source_index, res_source optional fields follow */
 };
 
-
-struct asl_general_register_desc
-{
-        u8                                  descriptor_type;
-        u16                                 length;
-        u8                                  address_space_id;
-        u8                                  bit_width;
-        u8                                  bit_offset;
-        u8                                  access_size; /* ACPI 3.0, was Reserved */
-        u64                                 address;
+struct asl_general_register_desc {
+        u8 descriptor_type;
+        u16 length;
+        u8 address_space_id;
+        u8 bit_width;
+        u8 bit_offset;
+        u8 access_size;         /* ACPI 3.0, was Reserved */
+        u64 address;
 };
 
 /* restore default alignment */
@@ -322,32 +277,29 @@ struct asl_general_register_desc
 
 /* Union of all resource descriptors, so we can allocate the worst case */
 
-union asl_resource_desc
-{
-        struct asl_irq_format_desc          irq;
-        struct asl_dma_format_desc          dma;
-        struct asl_start_dependent_desc     std;
-        struct asl_end_dependent_desc       end;
-        struct asl_io_port_desc             iop;
-        struct asl_fixed_io_port_desc       fio;
-        struct asl_small_vendor_desc        smv;
-        struct asl_end_tag_desc             et;
-
-        struct asl_memory_24_desc           M24;
-        struct asl_large_vendor_desc        lgv;
-        struct asl_memory_32_desc           M32;
-        struct asl_fixed_memory_32_desc     F32;
-        struct asl_qword_address_desc       qas;
-        struct asl_dword_address_desc       das;
-        struct asl_word_address_desc        was;
-        struct asl_extended_address_desc    eas;
-        struct asl_extended_xrupt_desc      exx;
-        struct asl_general_register_desc    grg;
-        u32                                 u32_item;
-        u16                                 u16_item;
-        u8                                  U8item;
+union asl_resource_desc {
+        struct asl_irq_format_desc irq;
+        struct asl_dma_format_desc dma;
+        struct asl_start_dependent_desc std;
+        struct asl_end_dependent_desc end;
+        struct asl_io_port_desc iop;
+        struct asl_fixed_io_port_desc fio;
+        struct asl_small_vendor_desc smv;
+        struct asl_end_tag_desc et;
+
+        struct asl_memory_24_desc M24;
+        struct asl_large_vendor_desc lgv;
+        struct asl_memory_32_desc M32;
+        struct asl_fixed_memory_32_desc F32;
+        struct asl_qword_address_desc qas;
+        struct asl_dword_address_desc das;
+        struct asl_word_address_desc was;
+        struct asl_extended_address_desc eas;
+        struct asl_extended_xrupt_desc exx;
+        struct asl_general_register_desc grg;
+        u32 u32_item;
+        u16 u16_item;
+        u8 U8item;
 };
 
-
 #endif
-
diff --git a/include/acpi/container.h b/include/acpi/container.h
index d716df04d9dc..a703f14e049e 100644
--- a/include/acpi/container.h
+++ b/include/acpi/container.h
@@ -9,5 +9,4 @@ struct acpi_container {
         int state;
 };
 
-#endif /* __ACPI_CONTAINER_H */
-
+#endif                          /* __ACPI_CONTAINER_H */
diff --git a/include/acpi/pdc_intel.h b/include/acpi/pdc_intel.h
new file mode 100644
index 000000000000..91f4a12a99a1
--- /dev/null
+++ b/include/acpi/pdc_intel.h
@@ -0,0 +1,27 @@
+
+/* _PDC bit definition for Intel processors */
+
+#ifndef __PDC_INTEL_H__
+#define __PDC_INTEL_H__
+
+#define ACPI_PDC_P_FFH                  (0x0001)
+#define ACPI_PDC_C_C1_HALT              (0x0002)
+#define ACPI_PDC_T_FFH                  (0x0004)
+#define ACPI_PDC_SMP_C1PT               (0x0008)
+#define ACPI_PDC_SMP_C2C3               (0x0010)
+#define ACPI_PDC_SMP_P_SWCOORD          (0x0020)
+#define ACPI_PDC_SMP_C_SWCOORD          (0x0040)
+#define ACPI_PDC_SMP_T_SWCOORD          (0x0080)
+#define ACPI_PDC_C_C1_FFH               (0x0100)
+
+#define ACPI_PDC_EST_CAPABILITY_SMP     (ACPI_PDC_SMP_C1PT | \
+                                         ACPI_PDC_C_C1_HALT)
+
+#define ACPI_PDC_EST_CAPABILITY_SMP_MSR (ACPI_PDC_EST_CAPABILITY_SMP | \
+                                         ACPI_PDC_P_FFH)
+
+#define ACPI_PDC_C_CAPABILITY_SMP       (ACPI_PDC_SMP_C2C3 | \
+                                         ACPI_PDC_SMP_C1PT | \
+                                         ACPI_PDC_C_C1_HALT)
+
+#endif                          /* __PDC_INTEL_H__ */
diff --git a/include/acpi/platform/acenv.h b/include/acpi/platform/acenv.h
index 57bf9362335d..16609c1ab2eb 100644
--- a/include/acpi/platform/acenv.h
+++ b/include/acpi/platform/acenv.h
@@ -44,40 +44,42 @@
 #ifndef __ACENV_H__
 #define __ACENV_H__
 
-
 /*
  * Configuration for ACPI tools and utilities
  */
 
-#ifdef _ACPI_DUMP_APP
+#ifdef ACPI_LIBRARY
+#define ACPI_USE_LOCAL_CACHE
+#endif
+
+#ifdef ACPI_DUMP_APP
 #ifndef MSDOS
 #define ACPI_DEBUG_OUTPUT
 #endif
 #define ACPI_APPLICATION
 #define ACPI_DISASSEMBLER
 #define ACPI_NO_METHOD_EXECUTION
-#define ACPI_USE_SYSTEM_CLIBRARY
-#define ACPI_ENABLE_OBJECT_CACHE
 #endif
 
-#ifdef _ACPI_EXEC_APP
+#ifdef ACPI_EXEC_APP
 #undef DEBUGGER_THREADING
 #define DEBUGGER_THREADING      DEBUGGER_SINGLE_THREADED
 #define ACPI_DEBUG_OUTPUT
 #define ACPI_APPLICATION
 #define ACPI_DEBUGGER
 #define ACPI_DISASSEMBLER
-#define ACPI_USE_SYSTEM_CLIBRARY
-#define ACPI_ENABLE_OBJECT_CACHE
 #endif
 
-#ifdef _ACPI_ASL_COMPILER
+#ifdef ACPI_ASL_COMPILER
 #define ACPI_DEBUG_OUTPUT
 #define ACPI_APPLICATION
 #define ACPI_DISASSEMBLER
 #define ACPI_CONSTANT_EVAL_ONLY
+#endif
+
+#ifdef ACPI_APPLICATION
 #define ACPI_USE_SYSTEM_CLIBRARY
-#define ACPI_ENABLE_OBJECT_CACHE
+#define ACPI_USE_LOCAL_CACHE
 #endif
 
 /*
@@ -131,7 +133,7 @@
 #elif defined(WIN64)
 #include "acwin64.h"
 
-#elif defined(MSDOS)        /* Must appear after WIN32 and WIN64 check */
+#elif defined(MSDOS)            /* Must appear after WIN32 and WIN64 check */
 #include "acdos16.h"
 
 #elif defined(__FreeBSD__)
@@ -177,7 +179,6 @@
 
 /*! [End] no source code translation !*/
 
-
 /*
  * Debugger threading model
  * Use single threaded if the entire subsystem is contained in an application
@@ -196,7 +197,7 @@
 #else
 #define DEBUGGER_THREADING          DEBUGGER_MULTI_THREADED
 #endif
-#endif /* !DEBUGGER_THREADING */
+#endif                          /* !DEBUGGER_THREADING */
 
 /******************************************************************************
  *
@@ -209,7 +210,6 @@
  * Use the standard C library headers.
  * We want to keep these to a minimum.
  */
-
 #ifdef ACPI_USE_STANDARD_HEADERS
 /*
  * Use the standard headers from the standard locations
@@ -219,19 +219,13 @@
 #include <string.h>
 #include <ctype.h>
 
-#endif /* ACPI_USE_STANDARD_HEADERS */
+#endif                          /* ACPI_USE_STANDARD_HEADERS */
 
 /*
  * We will be linking to the standard Clib functions
  */
-
 #define ACPI_STRSTR(s1,s2)      strstr((s1), (s2))
 #define ACPI_STRCHR(s1,c)       strchr((s1), (c))
-
-#ifdef ACPI_FUTURE_USAGE
-#define ACPI_STRUPR(s)          (void) acpi_ut_strupr ((s))
-#endif
-
 #define ACPI_STRLEN(s)          (acpi_size) strlen((s))
 #define ACPI_STRCPY(d,s)        (void) strcpy((d), (s))
 #define ACPI_STRNCPY(d,s,n)     (void) strncpy((d), (s), (acpi_size)(n))
@@ -244,63 +238,56 @@
 #define ACPI_MEMCPY(d,s,n)      (void) memcpy((d), (s), (acpi_size)(n))
 #define ACPI_MEMSET(d,s,n)      (void) memset((d), (s), (acpi_size)(n))
 
-#define ACPI_TOUPPER            toupper
-#define ACPI_TOLOWER            tolower
-#define ACPI_IS_XDIGIT          isxdigit
-#define ACPI_IS_DIGIT           isdigit
-#define ACPI_IS_SPACE           isspace
-#define ACPI_IS_UPPER           isupper
-#define ACPI_IS_PRINT           isprint
-#define ACPI_IS_ALPHA           isalpha
-#define ACPI_IS_ASCII           isascii
+#define ACPI_TOUPPER(i)         toupper((int) (i))
+#define ACPI_TOLOWER(i)         tolower((int) (i))
+#define ACPI_IS_XDIGIT(i)       isxdigit((int) (i))
+#define ACPI_IS_DIGIT(i)        isdigit((int) (i))
+#define ACPI_IS_SPACE(i)        isspace((int) (i))
+#define ACPI_IS_UPPER(i)        isupper((int) (i))
+#define ACPI_IS_PRINT(i)        isprint((int) (i))
+#define ACPI_IS_ALPHA(i)        isalpha((int) (i))
+#define ACPI_IS_ASCII(i)        isascii((int) (i))
+
+#else
 
 /******************************************************************************
  *
  * Not using native C library, use local implementations
  *
  *****************************************************************************/
-#else
 
-/*
- * Use local definitions of C library macros and functions
- * NOTE: The function implementations may not be as efficient
- * as an inline or assembly code implementation provided by a
- * native C library.
- */
+ /*
+  * Use local definitions of C library macros and functions
+  * NOTE: The function implementations may not be as efficient
+  * as an inline or assembly code implementation provided by a
+  * native C library.
+  */
 
 #ifndef va_arg
 
 #ifndef _VALIST
 #define _VALIST
 typedef char *va_list;
-#endif /* _VALIST */
+#endif                          /* _VALIST */
 
 /*
  * Storage alignment properties
  */
-
 #define  _AUPBND                (sizeof (acpi_native_int) - 1)
 #define  _ADNBND                (sizeof (acpi_native_int) - 1)
 
 /*
  * Variable argument list macro definitions
  */
-
 #define _bnd(X, bnd)            (((sizeof (X)) + (bnd)) & (~(bnd)))
 #define va_arg(ap, T)           (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
 #define va_end(ap)              (void) 0
 #define va_start(ap, A)         (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
 
-#endif /* va_arg */
-
+#endif                          /* va_arg */
 
 #define ACPI_STRSTR(s1,s2)      acpi_ut_strstr ((s1), (s2))
 #define ACPI_STRCHR(s1,c)       acpi_ut_strchr ((s1), (c))
-
-#ifdef ACPI_FUTURE_USAGE
-#define ACPI_STRUPR(s)          (void) acpi_ut_strupr ((s))
-#endif
-
 #define ACPI_STRLEN(s)          (acpi_size) acpi_ut_strlen ((s))
 #define ACPI_STRCPY(d,s)        (void) acpi_ut_strcpy ((d), (s))
 #define ACPI_STRNCPY(d,s,n)     (void) acpi_ut_strncpy ((d), (s), (acpi_size)(n))
@@ -315,8 +302,7 @@ typedef char *va_list;
 #define ACPI_TOUPPER            acpi_ut_to_upper
 #define ACPI_TOLOWER            acpi_ut_to_lower
 
-#endif /* ACPI_USE_SYSTEM_CLIBRARY */
-
+#endif                          /* ACPI_USE_SYSTEM_CLIBRARY */
 
 /******************************************************************************
  *
@@ -357,8 +343,7 @@ typedef char *va_list;
 #define ACPI_ACQUIRE_GLOBAL_LOCK(Glptr, acq)
 #define ACPI_RELEASE_GLOBAL_LOCK(Glptr, acq)
 
-#endif /* ACPI_ASM_MACROS */
-
+#endif                          /* ACPI_ASM_MACROS */
 
 #ifdef ACPI_APPLICATION
 
@@ -368,11 +353,10 @@ typedef char *va_list;
 #define BREAKPOINT3
 #endif
 
-
 /******************************************************************************
  *
  * Compiler-specific information is contained in the compiler-specific
  * headers.
  *
  *****************************************************************************/
-#endif /* __ACENV_H__ */
+#endif                          /* __ACENV_H__ */
diff --git a/include/acpi/platform/acgcc.h b/include/acpi/platform/acgcc.h
index 91fda36b042b..4c0e0ba09ba0 100644
--- a/include/acpi/platform/acgcc.h
+++ b/include/acpi/platform/acgcc.h
@@ -44,16 +44,20 @@
 #ifndef __ACGCC_H__
 #define __ACGCC_H__
 
+/* Function name is used for debug output. Non-ANSI, compiler-dependent */
+
+#define ACPI_GET_FUNCTION_NAME          __FUNCTION__
+
 /* This macro is used to tag functions as "printf-like" because
  * some compilers (like GCC) can catch printf format string problems.
  */
-#define ACPI_PRINTF_LIKE_FUNC __attribute__ ((__format__ (__printf__, 4, 5)))
+#define ACPI_PRINTF_LIKE_FUNC __attribute__ ((__format__ (__printf__, 6, 7)))
 
 /* Some compilers complain about unused variables. Sometimes we don't want to
- * use all the variables (most specifically for _THIS_MODULE). This allow us
+ * use all the variables (for example, _acpi_module_name). This allows us
  * to to tell the compiler warning in a per-variable manner that a variable
  * is unused.
  */
 #define ACPI_UNUSED_VAR __attribute__ ((unused))
 
-#endif /* __ACGCC_H__ */
+#endif                          /* __ACGCC_H__ */
diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h
index a3de0db85694..c93e6562f0e1 100644
--- a/include/acpi/platform/aclinux.h
+++ b/include/acpi/platform/aclinux.h
@@ -62,7 +62,16 @@
 
 #define ACPI_MACHINE_WIDTH  BITS_PER_LONG
 
-#else /* !__KERNEL__ */
+/* Type(s) for the OSL */
+
+#ifdef ACPI_USE_LOCAL_CACHE
+#define acpi_cache_t    struct acpi_memory_list
+#else
+#include <linux/slab.h>
+#define acpi_cache_t    kmem_cache_t
+#endif
+
+#else                           /* !__KERNEL__ */
 
 #include <stdarg.h>
 #include <string.h>
@@ -83,10 +92,10 @@
 
 #define __cdecl
 #define ACPI_FLUSH_CPU_CACHE()
-#endif /* __KERNEL__ */
+#endif                          /* __KERNEL__ */
 
 /* Linux uses GCC */
 
 #include "acgcc.h"
 
-#endif /* __ACLINUX_H__ */
+#endif                          /* __ACLINUX_H__ */
diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 2f50a5bb0c78..7a00d5089de9 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -4,6 +4,8 @@
 #include <linux/kernel.h>
 #include <linux/config.h>
 
+#include <asm/acpi.h>
+
 #define ACPI_PROCESSOR_BUSY_METRIC      10
 
 #define ACPI_PROCESSOR_MAX_POWER        8
@@ -14,137 +16,136 @@
 #define ACPI_PROCESSOR_MAX_THROTTLE     250     /* 25% */
 #define ACPI_PROCESSOR_MAX_DUTY_WIDTH   4
 
+#define ACPI_PDC_REVISION_ID            0x1
+
 /* Power Management */
 
 struct acpi_processor_cx;
 
 struct acpi_power_register {
-        u8                      descriptor;
-        u16                     length;
-        u8                      space_id;
-        u8                      bit_width;
-        u8                      bit_offset;
-        u8                      reserved;
-        u64                     address;
+        u8 descriptor;
+        u16 length;
+        u8 space_id;
+        u8 bit_width;
+        u8 bit_offset;
+        u8 reserved;
+        u64 address;
 } __attribute__ ((packed));
 
-
 struct acpi_processor_cx_policy {
-        u32                     count;
+        u32 count;
         struct acpi_processor_cx *state;
         struct {
-                u32                     time;
-                u32                     ticks;
-                u32                     count;
-                u32                     bm;
-        }                       threshold;
+                u32 time;
+                u32 ticks;
+                u32 count;
+                u32 bm;
+        } threshold;
 };
 
 struct acpi_processor_cx {
-        u8                      valid;
-        u8                      type;
-        u32                     address;
-        u32                     latency;
-        u32                     latency_ticks;
-        u32                     power;
-        u32                     usage;
+        u8 valid;
+        u8 type;
+        u32 address;
+        u32 latency;
+        u32 latency_ticks;
+        u32 power;
+        u32 usage;
         struct acpi_processor_cx_policy promotion;
         struct acpi_processor_cx_policy demotion;
 };
 
 struct acpi_processor_power {
         struct acpi_processor_cx *state;
-        unsigned long           bm_check_timestamp;
-        u32                     default_state;
-        u32                     bm_activity;
-        int                     count;
+        unsigned long bm_check_timestamp;
+        u32 default_state;
+        u32 bm_activity;
+        int count;
         struct acpi_processor_cx states[ACPI_PROCESSOR_MAX_POWER];
+
+        /* the _PDC objects passed by the driver, if any */
+        struct acpi_object_list *pdc;
 };
 
 /* Performance Management */
 
 struct acpi_pct_register {
-        u8                      descriptor;
-        u16                     length;
-        u8                      space_id;
-        u8                      bit_width;
-        u8                      bit_offset;
-        u8                      reserved;
-        u64                     address;
+        u8 descriptor;
+        u16 length;
+        u8 space_id;
+        u8 bit_width;
+        u8 bit_offset;
+        u8 reserved;
+        u64 address;
 } __attribute__ ((packed));
 
 struct acpi_processor_px {
-        acpi_integer            core_frequency;         /* megahertz */
-        acpi_integer            power;                  /* milliWatts */
-        acpi_integer            transition_latency;     /* microseconds */
-        acpi_integer            bus_master_latency;     /* microseconds */
-        acpi_integer            control;                /* control value */
-        acpi_integer            status;                 /* success indicator */
+        acpi_integer core_frequency;    /* megahertz */
+        acpi_integer power;     /* milliWatts */
+        acpi_integer transition_latency;        /* microseconds */
+        acpi_integer bus_master_latency;        /* microseconds */
+        acpi_integer control;   /* control value */
+        acpi_integer status;    /* success indicator */
 };
 
-#define ACPI_PDC_REVISION_ID                   0x1
-
 struct acpi_processor_performance {
-        unsigned int             state;
-        unsigned int             platform_limit;
+        unsigned int state;
+        unsigned int platform_limit;
         struct acpi_pct_register control_register;
         struct acpi_pct_register status_register;
-        unsigned int             state_count;
+        unsigned int state_count;
         struct acpi_processor_px *states;
 
         /* the _PDC objects passed by the driver, if any */
         struct acpi_object_list *pdc;
 };
 
-
-
 /* Throttling Control */
 
 struct acpi_processor_tx {
-        u16                     power;
-        u16                     performance;
+        u16 power;
+        u16 performance;
 };
 
 struct acpi_processor_throttling {
-        int                     state;
-        u32                     address;
-        u8                      duty_offset;
-        u8                      duty_width;
-        int                     state_count;
+        int state;
+        u32 address;
+        u8 duty_offset;
+        u8 duty_width;
+        int state_count;
         struct acpi_processor_tx states[ACPI_PROCESSOR_MAX_THROTTLING];
 };
 
 /* Limit Interface */
 
 struct acpi_processor_lx {
-        int                     px;             /* performace state */  
-        int                     tx;             /* throttle level */
+        int px;                 /* performace state */
+        int tx;                 /* throttle level */
 };
 
 struct acpi_processor_limit {
-        struct acpi_processor_lx state;         /* current limit */
+        struct acpi_processor_lx state; /* current limit */
         struct acpi_processor_lx thermal;       /* thermal limit */
-        struct acpi_processor_lx user;          /* user limit */
+        struct acpi_processor_lx user;  /* user limit */
 };
 
-
 struct acpi_processor_flags {
-        u8                      power:1;
-        u8                      performance:1;
-        u8                      throttling:1;
-        u8                      limit:1;
-        u8                      bm_control:1;
-        u8                      bm_check:1;
-        u8                      has_cst:1;
-        u8                      power_setup_done:1;
+        u8 power:1;
+        u8 performance:1;
+        u8 throttling:1;
+        u8 limit:1;
+        u8 bm_control:1;
+        u8 bm_check:1;
+        u8 has_cst:1;
+        u8 power_setup_done:1;
 };
 
 struct acpi_processor {
-        acpi_handle             handle;
-        u32                     acpi_id;
-        u32                     id;
-        u32                     pblk;
-        int                     performance_platform_limit;
+        acpi_handle handle;
+        u32 acpi_id;
+        u32 id;
+        u32 pblk;
+        int performance_platform_limit;
         struct acpi_processor_flags flags;
         struct acpi_processor_power power;
         struct acpi_processor_performance *performance;
@@ -153,83 +154,118 @@ struct acpi_processor {
 };
 
 struct acpi_processor_errata {
-        u8                      smp;
+        u8 smp;
         struct {
-                u8                      throttle:1;
-                u8                      fdma:1;
-                u8                      reserved:6;
-                u32                     bmisx;
-        }                       piix4;
+                u8 throttle:1;
+                u8 fdma:1;
+                u8 reserved:6;
+                u32 bmisx;
+        } piix4;
 };
 
-extern int acpi_processor_register_performance (
-        struct acpi_processor_performance * performance,
-        unsigned int cpu);
-extern void acpi_processor_unregister_performance (
-        struct acpi_processor_performance * performance,
-        unsigned int cpu);
+extern int acpi_processor_register_performance(struct acpi_processor_performance
+                                               *performance, unsigned int cpu);
+extern void acpi_processor_unregister_performance(struct
+                                                  acpi_processor_performance
+                                                  *performance,
+                                                  unsigned int cpu);
 
 /* note: this locks both the calling module and the processor module
          if a _PPC object exists, rmmod is disallowed then */
 int acpi_processor_notify_smm(struct module *calling_module);
 
-
-
 /* for communication between multiple parts of the processor kernel module */
-extern struct acpi_processor    *processors[NR_CPUS];
+extern struct acpi_processor *processors[NR_CPUS];
 extern struct acpi_processor_errata errata;
 
+int acpi_processor_set_pdc(struct acpi_processor *pr,
+                           struct acpi_object_list *pdc_in);
+
+#ifdef ARCH_HAS_POWER_PDC_INIT
+void acpi_processor_power_init_pdc(struct acpi_processor_power *pow,
+                                   unsigned int cpu);
+void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
+                                        unsigned int cpu);
+#else
+static inline void acpi_processor_power_init_pdc(struct acpi_processor_power
+                                                 *pow, unsigned int cpu)
+{
+        pow->pdc = NULL;
+        return;
+}
+
+static inline void acpi_processor_power_init_bm_check(struct
+                                                      acpi_processor_flags
+                                                      *flags, unsigned int cpu)
+{
+        flags->bm_check = 1;
+        return;
+}
+#endif
+
 /* in processor_perflib.c */
+
 #ifdef CONFIG_CPU_FREQ
 void acpi_processor_ppc_init(void);
 void acpi_processor_ppc_exit(void);
 int acpi_processor_ppc_has_changed(struct acpi_processor *pr);
 #else
-static inline void acpi_processor_ppc_init(void) { return; }
-static inline void acpi_processor_ppc_exit(void) { return; }
-static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr) {
+static inline void acpi_processor_ppc_init(void)
+{
+        return;
+}
+static inline void acpi_processor_ppc_exit(void)
+{
+        return;
+}
+static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr)
+{
         static unsigned int printout = 1;
         if (printout) {
-                printk(KERN_WARNING "Warning: Processor Platform Limit event detected, but not handled.\n");
-                printk(KERN_WARNING "Consider compiling CPUfreq support into your kernel.\n");
+                printk(KERN_WARNING
+                       "Warning: Processor Platform Limit event detected, but not handled.\n");
+                printk(KERN_WARNING
+                       "Consider compiling CPUfreq support into your kernel.\n");
                 printout = 0;
         }
         return 0;
 }
-#endif /* CONFIG_CPU_FREQ */
+#endif                          /* CONFIG_CPU_FREQ */
 
 /* in processor_throttling.c */
-int acpi_processor_get_throttling_info (struct acpi_processor *pr);
-int acpi_processor_set_throttling (struct acpi_processor *pr, int state);
-ssize_t acpi_processor_write_throttling (
-        struct file             *file,
-        const char              __user *buffer,
-        size_t                  count,
-        loff_t                  *data);
+int acpi_processor_get_throttling_info(struct acpi_processor *pr);
+int acpi_processor_set_throttling(struct acpi_processor *pr, int state);
+ssize_t acpi_processor_write_throttling(struct file *file,
+                                        const char __user * buffer,
+                                        size_t count, loff_t * data);
 extern struct file_operations acpi_processor_throttling_fops;
 
 /* in processor_idle.c */
-int acpi_processor_power_init(struct acpi_processor *pr, struct acpi_device *device);
-int acpi_processor_cst_has_changed (struct acpi_processor *pr);
-int acpi_processor_power_exit(struct acpi_processor *pr, struct acpi_device *device);
-
+int acpi_processor_power_init(struct acpi_processor *pr,
+                              struct acpi_device *device);
+int acpi_processor_cst_has_changed(struct acpi_processor *pr);
+int acpi_processor_power_exit(struct acpi_processor *pr,
+                              struct acpi_device *device);
 
 /* in processor_thermal.c */
-int acpi_processor_get_limit_info (struct acpi_processor *pr);
-ssize_t acpi_processor_write_limit (
-        struct file             *file,
-        const char              __user *buffer,
-        size_t                  count,
-        loff_t                  *data);
+int acpi_processor_get_limit_info(struct acpi_processor *pr);
+ssize_t acpi_processor_write_limit(struct file *file,
+                                   const char __user * buffer,
+                                   size_t count, loff_t * data);
 extern struct file_operations acpi_processor_limit_fops;
 
 #ifdef CONFIG_CPU_FREQ
 void acpi_thermal_cpufreq_init(void);
 void acpi_thermal_cpufreq_exit(void);
 #else
-static inline void acpi_thermal_cpufreq_init(void) { return; }
-static inline void acpi_thermal_cpufreq_exit(void) { return; }
+static inline void acpi_thermal_cpufreq_init(void)
+{
+        return;
+}
+static inline void acpi_thermal_cpufreq_exit(void)
+{
+        return;
+}
 #endif
 
-
 #endif
diff --git a/include/asm-alpha/auxvec.h b/include/asm-alpha/auxvec.h
new file mode 100644
index 000000000000..e96fe880e310
--- /dev/null
+++ b/include/asm-alpha/auxvec.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_ALPHA_AUXVEC_H
+#define __ASM_ALPHA_AUXVEC_H
+
+/* Reserve these numbers for any future use of a VDSO.  */
+#if 0
+#define AT_SYSINFO              32
+#define AT_SYSINFO_EHDR         33
+#endif
+
+/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
+   value is -1, then the cache doesn't exist.  Otherwise:
+
+      bit 0-3:    Cache set-associativity; 0 means fully associative.
+      bit 4-7:    Log2 of cacheline size.
+      bit 8-31:   Size of the entire cache >> 8.
+      bit 32-63:  Reserved.
+*/
+
+#define AT_L1I_CACHESHAPE       34
+#define AT_L1D_CACHESHAPE       35
+#define AT_L2_CACHESHAPE        36
+#define AT_L3_CACHESHAPE        37
+
+#endif /* __ASM_ALPHA_AUXVEC_H */
diff --git a/include/asm-alpha/elf.h b/include/asm-alpha/elf.h
index e94a945a2314..6c2d78fba264 100644
--- a/include/asm-alpha/elf.h
+++ b/include/asm-alpha/elf.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ALPHA_ELF_H
 #define __ASM_ALPHA_ELF_H
 
+#include <asm/auxvec.h>
+
 /* Special values for the st_other field in the symbol table.  */
 
 #define STO_ALPHA_NOPV          0x80
@@ -142,26 +144,6 @@ extern int dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task);
         : amask (AMASK_CIX) ? "ev6" : "ev67");  \
 })
 
-/* Reserve these numbers for any future use of a VDSO.  */
-#if 0
-#define AT_SYSINFO              32
-#define AT_SYSINFO_EHDR         33
-#endif
-
-/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
-   value is -1, then the cache doesn't exist.  Otherwise:
-
-      bit 0-3:    Cache set-associativity; 0 means fully associative.
-      bit 4-7:    Log2 of cacheline size.
-      bit 8-31:   Size of the entire cache >> 8.
-      bit 32-63:  Reserved.
-*/
-
-#define AT_L1I_CACHESHAPE       34
-#define AT_L1D_CACHESHAPE       35
-#define AT_L2_CACHESHAPE        36
-#define AT_L3_CACHESHAPE        37
-
 #ifdef __KERNEL__
 
 #define SET_PERSONALITY(EX, IBCS2)                              \
diff --git a/include/asm-alpha/emergency-restart.h b/include/asm-alpha/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-alpha/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-alpha/fcntl.h b/include/asm-alpha/fcntl.h
index 6b7d6c1649ce..87f2cf459e26 100644
--- a/include/asm-alpha/fcntl.h
+++ b/include/asm-alpha/fcntl.h
@@ -3,10 +3,6 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_ACCMODE         0003
-#define O_RDONLY            00
-#define O_WRONLY            01
-#define O_RDWR              02
 #define O_CREAT          01000  /* not fcntl */
 #define O_TRUNC          02000  /* not fcntl */
 #define O_EXCL           04000  /* not fcntl */
@@ -14,20 +10,13 @@
 
 #define O_NONBLOCK       00004
 #define O_APPEND         00010
-#define O_NDELAY        O_NONBLOCK
 #define O_SYNC          040000
-#define FASYNC          020000  /* fcntl, for BSD compatibility */
 #define O_DIRECTORY     0100000 /* must be a directory */
 #define O_NOFOLLOW      0200000 /* don't follow links */
 #define O_LARGEFILE     0400000 /* will be set by the kernel on every open */
 #define O_DIRECT        02000000 /* direct disk access - should check with OSF/1 */
 #define O_NOATIME       04000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
 #define F_GETLK         7
 #define F_SETLK         8
 #define F_SETLKW        9
@@ -37,9 +26,6 @@
 #define F_SETSIG        10      /*  for sockets. */
 #define F_GETSIG        11      /*  for sockets. */
 
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
 /* for posix fcntl() and lockf() */
 #define F_RDLCK         1
 #define F_WRLCK         2
@@ -51,25 +37,6 @@
 
 #define F_INPROGRESS    64
 
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-#define LOCK_MAND      32      /* This is a mandatory flock */
-#define LOCK_READ      64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE     128     /* ... Which allows concurrent write operations */
-#define LOCK_RW        192     /* ... Which allows concurrent read & write ops */
- 
-struct flock {
-        short l_type;
-        short l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
-        __kernel_pid_t l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE  1024
+#include <asm-generic/fcntl.h>
 
 #endif
diff --git a/include/asm-alpha/futex.h b/include/asm-alpha/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-alpha/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-alpha/hdreg.h b/include/asm-alpha/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-alpha/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-alpha/mmzone.h b/include/asm-alpha/mmzone.h
index 726c150dcbe4..a011ef4cf3d3 100644
--- a/include/asm-alpha/mmzone.h
+++ b/include/asm-alpha/mmzone.h
@@ -57,7 +57,6 @@ PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
  * Given a kernel address, find the home node of the underlying memory.
  */
 #define kvaddr_to_nid(kaddr)    pa_to_nid(__pa(kaddr))
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 
 #define local_mapnr(kvaddr) \
@@ -108,7 +107,7 @@ PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
 #define pfn_to_page(pfn)                                                \
 ({                                                                      \
         unsigned long kaddr = (unsigned long)__va((pfn) << PAGE_SHIFT); \
-        (node_mem_map(kvaddr_to_nid(kaddr)) + local_mapnr(kaddr));      \
+        (NODE_DATA(kvaddr_to_nid(kaddr))->node_mem_map + local_mapnr(kaddr));   \
 })
 
 #define page_to_pfn(page)                                               \
diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h
index 0577daffc720..fa0b41b164a7 100644
--- a/include/asm-alpha/page.h
+++ b/include/asm-alpha/page.h
@@ -63,20 +63,6 @@ typedef unsigned long pgprot_t;
 
 #endif /* STRICT_MM_TYPECHECKS */
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #ifdef USE_48_BIT_KSEG
 #define PAGE_OFFSET             0xffff800000000000UL
 #else
@@ -112,4 +98,6 @@ extern __inline__ int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _ALPHA_PAGE_H */
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index 0c7b57bc043a..f681e675b823 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -58,7 +58,7 @@ struct pci_controller {
 
 extern void pcibios_set_master(struct pci_dev *dev);
 
-extern inline void pcibios_penalize_isa_irq(int irq)
+extern inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -223,6 +223,25 @@ pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
         /* Nothing to do. */
 }
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_BOUNDARY;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
 /* TODO: integrate with include/asm-generic/pci.h ? */
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
@@ -232,6 +251,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
                                     struct resource *);
 
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h
index 408aea55e0cc..22b53e369f59 100644
--- a/include/asm-alpha/pgtable.h
+++ b/include/asm-alpha/pgtable.h
@@ -133,6 +133,12 @@
 #define __S111  _PAGE_S(0)
 
 /*
+ * pgprot_noncached() is only for infiniband pci support, and a real
+ * implementation for RAM would be more complicated.
+ */
+#define pgprot_noncached(prot)  (prot)
+
+/*
  * BAD_PAGETABLE is used when we need a bogus page-table, while
  * BAD_PAGE is used for a bogus page.
  *
diff --git a/include/asm-alpha/serial.h b/include/asm-alpha/serial.h
index 7b2d9ee95a44..7e4b2987d453 100644
--- a/include/asm-alpha/serial.h
+++ b/include/asm-alpha/serial.h
@@ -22,54 +22,9 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#endif
-        
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h
index cbc173ae45aa..9950706abdf8 100644
--- a/include/asm-alpha/smp.h
+++ b/include/asm-alpha/smp.h
@@ -43,7 +43,7 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
 #define PROC_CHANGE_PENALTY     20
 
 #define hard_smp_processor_id() __hard_smp_processor_id()
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 extern cpumask_t cpu_present_mask;
 extern cpumask_t cpu_online_map;
diff --git a/include/asm-alpha/socket.h b/include/asm-alpha/socket.h
index d00259d3dc78..b5193229132a 100644
--- a/include/asm-alpha/socket.h
+++ b/include/asm-alpha/socket.h
@@ -25,6 +25,8 @@
 #define SO_ERROR        0x1007
 #define SO_SNDBUF       0x1001
 #define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
 #define SO_RCVLOWAT     0x1010
 #define SO_SNDLOWAT     0x1011
 #define SO_RCVTIMEO     0x1012
diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h
index c08ce970ff8c..bdb4d66418f1 100644
--- a/include/asm-alpha/system.h
+++ b/include/asm-alpha/system.h
@@ -443,22 +443,19 @@ __xchg_u64(volatile long *m, unsigned long val)
    if something tries to do an invalid xchg().  */
 extern void __xchg_called_with_bad_pointer(void);
 
-static inline unsigned long
-__xchg(volatile void *ptr, unsigned long x, int size)
-{
-        switch (size) {
-                case 1:
-                        return __xchg_u8(ptr, x);
-                case 2:
-                        return __xchg_u16(ptr, x);
-                case 4:
-                        return __xchg_u32(ptr, x);
-                case 8:
-                        return __xchg_u64(ptr, x);
-        }
-        __xchg_called_with_bad_pointer();
-        return x;
-}
+#define __xchg(ptr, x, size) \
+({ \
+        unsigned long __xchg__res; \
+        volatile void *__xchg__ptr = (ptr); \
+        switch (size) { \
+                case 1: __xchg__res = __xchg_u8(__xchg__ptr, x); break; \
+                case 2: __xchg__res = __xchg_u16(__xchg__ptr, x); break; \
+                case 4: __xchg__res = __xchg_u32(__xchg__ptr, x); break; \
+                case 8: __xchg__res = __xchg_u64(__xchg__ptr, x); break; \
+                default: __xchg_called_with_bad_pointer(); __xchg__res = x; \
+        } \
+        __xchg__res; \
+})
 
 #define xchg(ptr,x)                                                          \
   ({                                                                         \
diff --git a/include/asm-alpha/types.h b/include/asm-alpha/types.h
index 43264d219246..f5716139ec89 100644
--- a/include/asm-alpha/types.h
+++ b/include/asm-alpha/types.h
@@ -56,8 +56,6 @@ typedef unsigned long u64;
 typedef u64 dma_addr_t;
 typedef u64 dma64_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_TYPES_H */
diff --git a/include/asm-alpha/uaccess.h b/include/asm-alpha/uaccess.h
index 4c39ee750f38..22de3b434a22 100644
--- a/include/asm-alpha/uaccess.h
+++ b/include/asm-alpha/uaccess.h
@@ -48,12 +48,6 @@
         __access_ok(((unsigned long)(addr)),(size),get_fs());   \
 })
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
 /*
  * These are the main single-value transfer routines.  They automatically
  * use the right size if we just have the right pointer type.
diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h
index 535bc425f243..ef25b6585119 100644
--- a/include/asm-alpha/unistd.h
+++ b/include/asm-alpha/unistd.h
@@ -377,8 +377,13 @@
 #define __NR_add_key                    439
 #define __NR_request_key                440
 #define __NR_keyctl                     441
+#define __NR_ioprio_set                 442
+#define __NR_ioprio_get                 443
+#define __NR_inotify_init               444
+#define __NR_inotify_add_watch          445
+#define __NR_inotify_rm_watch           446
 
-#define NR_SYSCALLS                     442
+#define NR_SYSCALLS                     447
 
 #if defined(__GNUC__)
 
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
new file mode 100644
index 000000000000..0e9b7e18af05
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -0,0 +1,151 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/aaec2000.h
+ *
+ *  AAEC-2000 registers definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_AAEC2000_H
+#define __ASM_ARCH_AAEC2000_H
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not this file
+#endif /* __ASM_ARCH_HARDWARE_H */
+
+/* Interrupt controller */
+#define IRQ_BASE        __REG(0x80000500)
+#define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
+#define IRQ_INTRSR      __REG(0x80000504)       /* Int Raw (unmasked) Status */
+#define IRQ_INTENS      __REG(0x80000508)       /* Int Enable Set */
+#define IRQ_INTENC      __REG(0x8000050c)       /* Int Enable Clear */
+
+/* UART 1 */
+#define UART1_BASE      __REG(0x80000600)
+#define UART1_DR        __REG(0x80000600) /* Data/FIFO Register */
+#define UART1_LCR       __REG(0x80000604) /* Link Control Register */
+#define UART1_BRCR      __REG(0x80000608) /* Baud Rate Control Register */
+#define UART1_CR        __REG(0x8000060c) /* Control Register */
+#define UART1_SR        __REG(0x80000610) /* Status Register */
+#define UART1_INT       __REG(0x80000614) /* Interrupt Status Register */
+#define UART1_INTM      __REG(0x80000618) /* Interrupt Mask Register */
+#define UART1_INTRES    __REG(0x8000061c) /* Int Result (masked status) Register */
+
+/* UART 2 */
+#define UART2_BASE      __REG(0x80000700)
+#define UART2_DR        __REG(0x80000700) /* Data/FIFO Register */
+#define UART2_LCR       __REG(0x80000704) /* Link Control Register */
+#define UART2_BRCR      __REG(0x80000708) /* Baud Rate Control Register */
+#define UART2_CR        __REG(0x8000070c) /* Control Register */
+#define UART2_SR        __REG(0x80000710) /* Status Register */
+#define UART2_INT       __REG(0x80000714) /* Interrupt Status Register */
+#define UART2_INTM      __REG(0x80000718) /* Interrupt Mask Register */
+#define UART2_INTRES    __REG(0x8000071c) /* Int Result (masked status) Register */
+
+/* UART 3 */
+#define UART3_BASE      __REG(0x80000800)
+#define UART3_DR        __REG(0x80000800) /* Data/FIFO Register */
+#define UART3_LCR       __REG(0x80000804) /* Link Control Register */
+#define UART3_BRCR      __REG(0x80000808) /* Baud Rate Control Register */
+#define UART3_CR        __REG(0x8000080c) /* Control Register */
+#define UART3_SR        __REG(0x80000810) /* Status Register */
+#define UART3_INT       __REG(0x80000814) /* Interrupt Status Register */
+#define UART3_INTM      __REG(0x80000818) /* Interrupt Mask Register */
+#define UART3_INTRES    __REG(0x8000081c) /* Int Result (masked status) Register */
+
+/* These are used in some places */
+#define _UART1_BASE __PREG(UART1_BASE)
+#define _UART2_BASE __PREG(UART2_BASE)
+#define _UART3_BASE __PREG(UART3_BASE)
+
+/* UART Registers Offsets */
+#define UART_DR         0x00
+#define UART_LCR        0x04
+#define UART_BRCR       0x08
+#define UART_CR         0x0c
+#define UART_SR         0x10
+#define UART_INT        0x14
+#define UART_INTM       0x18
+#define UART_INTRES     0x1c
+
+/* UART_LCR Bitmask */
+#define UART_LCR_BRK    (1 << 0) /* Send Break */
+#define UART_LCR_PEN    (1 << 1) /* Parity Enable */
+#define UART_LCR_EP     (1 << 2) /* Even/Odd Parity */
+#define UART_LCR_S2     (1 << 3) /* One/Two Stop bits */
+#define UART_LCR_FIFO   (1 << 4) /* FIFO Enable */
+#define UART_LCR_WL5    (0 << 5) /* Word Length - 5 bits */
+#define UART_LCR_WL6    (1 << 5) /* Word Length - 6 bits */
+#define UART_LCR_WL7    (1 << 6) /* Word Length - 7 bits */
+#define UART_LCR_WL8    (1 << 7) /* Word Length - 8 bits */
+
+/* UART_CR Bitmask */
+#define UART_CR_EN      (1 << 0) /* UART Enable */
+#define UART_CR_SIR     (1 << 1) /* IrDA SIR Enable */
+#define UART_CR_SIRLP   (1 << 2) /* Low Power IrDA Enable */
+#define UART_CR_RXP     (1 << 3) /* Receive Pin Polarity */
+#define UART_CR_TXP     (1 << 4) /* Transmit Pin Polarity */
+#define UART_CR_MXP     (1 << 5) /* Modem Pin Polarity */
+#define UART_CR_LOOP    (1 << 6) /* Loopback Mode */
+
+/* UART_SR Bitmask */
+#define UART_SR_CTS     (1 << 0) /* Clear To Send Status */
+#define UART_SR_DSR     (1 << 1) /* Data Set Ready Status */
+#define UART_SR_DCD     (1 << 2) /* Data Carrier Detect Status */
+#define UART_SR_TxBSY   (1 << 3) /* Transmitter Busy Status */
+#define UART_SR_RxFE    (1 << 4) /* Receive FIFO Empty Status */
+#define UART_SR_TxFF    (1 << 5) /* Transmit FIFO Full Status */
+#define UART_SR_RxFF    (1 << 6) /* Receive FIFO Full Status */
+#define UART_SR_TxFE    (1 << 7) /* Transmit FIFO Empty Status */
+
+/* UART_INT Bitmask */
+#define UART_INT_RIS    (1 << 0) /* Rx Interrupt */
+#define UART_INT_TIS    (1 << 1) /* Tx Interrupt */
+#define UART_INT_MIS    (1 << 2) /* Modem Interrupt */
+#define UART_INT_RTIS   (1 << 3) /* Receive Timeout Interrupt */
+
+/* Timer 1 */
+#define TIMER1_BASE     __REG(0x80000c00)
+#define TIMER1_LOAD     __REG(0x80000c00)       /* Timer 1 Load Register */
+#define TIMER1_VAL      __REG(0x80000c04)       /* Timer 1 Value Register */
+#define TIMER1_CTRL     __REG(0x80000c08)       /* Timer 1 Control Register */
+#define TIMER1_CLEAR    __REG(0x80000c0c)       /* Timer 1 Clear Register */
+
+/* Timer 2 */
+#define TIMER2_BASE     __REG(0x80000d00)
+#define TIMER2_LOAD     __REG(0x80000d00)       /* Timer 2 Load Register */
+#define TIMER2_VAL      __REG(0x80000d04)       /* Timer 2 Value Register */
+#define TIMER2_CTRL     __REG(0x80000d08)       /* Timer 2 Control Register */
+#define TIMER2_CLEAR    __REG(0x80000d0c)       /* Timer 2 Clear Register */
+
+/* Timer 3 */
+#define TIMER3_BASE     __REG(0x80000e00)
+#define TIMER3_LOAD     __REG(0x80000e00)       /* Timer 3 Load Register */
+#define TIMER3_VAL      __REG(0x80000e04)       /* Timer 3 Value Register */
+#define TIMER3_CTRL     __REG(0x80000e08)       /* Timer 3 Control Register */
+#define TIMER3_CLEAR    __REG(0x80000e0c)       /* Timer 3 Clear Register */
+
+/* Timer Control register bits */
+#define TIMER_CTRL_ENABLE       (1 << 7) /* Enable (Start° Timer */
+#define TIMER_CTRL_PERIODIC     (1 << 6) /* Periodic Running Mode */
+#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
+#define TIMER_CTRL_CLKSEL_508K  (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
+#define TIMER_CTRL_CLKSEL_2K    (0 << 3) /* 2KHz Clock Select (Timer 1, 2)*/
+
+/* Power and State Control */
+#define POWER_BASE      __REG(0x80000400)
+#define POWER_PWRSR     __REG(0x80000400) /* Power Status Register */
+#define POWER_PWRCNT    __REG(0x80000404) /* Power/Clock control */
+#define POWER_HALT      __REG(0x80000408) /* Power Idle Mode */
+#define POWER_STDBY     __REG(0x8000040c) /* Power Standby Mode */
+#define POWER_BLEOI     __REG(0x80000410) /* Battery Low End of Interrupt */
+#define POWER_MCEOI     __REG(0x80000414) /* Media Changed EoI */
+#define POWER_TEOI      __REG(0x80000418) /* Tick EoI */
+#define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
+#define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
+
+#endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/debug-macro.S b/include/asm-arm/arch-aaec2000/debug-macro.S
new file mode 100644
index 000000000000..e4f1fa539a74
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/debug-macro.S
@@ -0,0 +1,36 @@
+/*  linux/include/asm-arm/arch-aaec2000/debug-macro.S
+ *
+ *  Debugging macro include header
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000                @ physical
+                movne   \rx, #io_p2v(0x80000000)        @ virtual
+                orr     \rx, \rx, #0x00000800
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 7)
+                beq     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+#if 0
+1001:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 5)
+                beq     1001b
+#endif
+                .endm
diff --git a/include/asm-arm/arch-aaec2000/dma.h b/include/asm-arm/arch-aaec2000/dma.h
new file mode 100644
index 000000000000..28c890b4a1d3
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/dma.h
@@ -0,0 +1,17 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/dma.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+
+#endif
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S
new file mode 100644
index 000000000000..df31313ab07e
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/entry-macro.S
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/entry-macro.S
+ *
+ *  Low-level IRQ helper for aaec-2000 based platforms
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xf8000000
+                add     r4, r4, #0x00000500
+                mov     \base, r4
+                ldr     \irqstat, [\base, #0]
+                cmp     \irqstat, #0
+                bne     1001f
+                ldr     \irqnr, =NR_IRQS+1
+                b       1003f
+1001:           mov     \irqnr, #0
+1002:           ands    \tmp, \irqstat, #1
+                mov     \irqstat, \irqstat, LSR #1
+                add     \irqnr, \irqnr, #1
+                beq     1002b
+                sub     \irqnr, \irqnr, #1
+1003:
+                .endm
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
new file mode 100644
index 000000000000..4c37219e030e
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/hardware.h
@@ -0,0 +1,49 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/hardware.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+/* The kernel is loaded at physical address 0xf8000000.
+ * We map the IO space a bit after
+ */
+#define PIO_APB_BASE    0x80000000
+#define VIO_APB_BASE    0xf8000000
+#define IO_APB_LENGTH   0x2000
+#define PIO_AHB_BASE    0x80002000
+#define VIO_AHB_BASE    0xf8002000
+#define IO_AHB_LENGTH   0x2000
+
+#define VIO_BASE    VIO_APB_BASE
+#define PIO_BASE    PIO_APB_BASE
+
+#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
+#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+/* FIXME: Is it needed to optimize this a la pxa ?? */
+#define __REG(x)    (*((volatile u32 *)io_p2v(x)))
+#define __PREG(x)   (io_v2p((u32)&(x)))
+
+#else /* __ASSEMBLY__ */
+
+#define __REG(x)    io_p2v(x)
+#define __PREG(x)   io_v2p(x)
+
+#endif
+
+#include "aaec2000.h"
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
new file mode 100644
index 000000000000..c58a8d10425a
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/io.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/io.h
+ *
+ *  Copied from asm/arch/sa1100/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-aaec2000/irqs.h b/include/asm-arm/arch-aaec2000/irqs.h
new file mode 100644
index 000000000000..de252220e806
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/irqs.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/irqs.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define INT_GPIOF0_FIQ  0  /* External GPIO Port F O Fast Interrupt Input */
+#define INT_BL_FIQ      1  /* Battery Low Fast Interrupt */
+#define INT_WE_FIQ      2  /* Watchdog Expired Fast Interrupt */
+#define INT_MV_FIQ      3  /* Media Changed Interrupt */
+#define INT_SC          4  /* Sound Codec Interrupt */
+#define INT_GPIO1       5  /* GPIO Port F Configurable Int 1 */
+#define INT_GPIO2       6  /* GPIO Port F Configurable Int 2 */
+#define INT_GPIO3       7  /* GPIO Port F Configurable Int 3 */
+#define INT_TMR1_OFL    8  /* Timer 1 Overflow Interrupt */
+#define INT_TMR2_OFL    9  /* Timer 2 Overflow Interrupt */
+#define INT_RTC_CM      10 /* RTC Compare Match Interrupt */
+#define INT_TICK        11 /* 64Hz Tick Interrupt */
+#define INT_UART1       12 /* UART1 Interrupt */
+#define INT_UART2       13 /* UART2 & Modem State Changed Interrupt */
+#define INT_LCD         14 /* LCD Interrupt */
+#define INT_SSI         15 /* SSI End of Transfer Interrupt */
+#define INT_UART3       16 /* UART3 Interrupt */
+#define INT_SCI         17 /* SCI Interrupt */
+#define INT_AAC         18 /* Advanced Audio Codec Interrupt */
+#define INT_MMC         19 /* MMC Interrupt */
+#define INT_USB         20 /* USB Interrupt */
+#define INT_DMA         21 /* DMA Interrupt */
+#define INT_TMR3_UOFL   22 /* Timer 3 Underflow Interrupt */
+#define INT_GPIO4       23 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO5       24 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO6       25 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO7       26 /* GPIO Port F Configurable Int 4 */
+#define INT_BMI         27 /* BMI Interrupt */
+
+#define NR_IRQS         (INT_BMI + 1)
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
new file mode 100644
index 000000000000..681b6a6171a1
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -0,0 +1,73 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/memory.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <linux/config.h>
+
+#define PHYS_OFFSET     (0xf0000000UL)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+
+/*
+ * The nodes are the followings:
+ *
+ *   node 0: 0xf000.0000 - 0xf3ff.ffff
+ *   node 1: 0xf400.0000 - 0xf7ff.ffff
+ *   node 2: 0xf800.0000 - 0xfbff.ffff
+ *   node 3: 0xfc00.0000 - 0xffff.ffff
+ */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ *  Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ *  and returns the index corresponding to the appropriate page in the
+ *  node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
+
+#define NODE_MAX_MEM_SHIFT      26
+#define NODE_MAX_MEM_SIZE       (1 << NODE_MAX_MEM_SHIFT)
+
+#else
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-aaec2000/param.h b/include/asm-arm/arch-aaec2000/param.h
new file mode 100644
index 000000000000..139936c2faf2
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/param.h
@@ -0,0 +1,15 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/param.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+#endif /* __ASM_ARCH_PARAM_H */
+
diff --git a/include/asm-arm/arch-aaec2000/system.h b/include/asm-arm/arch-aaec2000/system.h
new file mode 100644
index 000000000000..08de97b407a8
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/system.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/arch-aaed2000/system.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-aaec2000/timex.h b/include/asm-arm/arch-aaec2000/timex.h
new file mode 100644
index 000000000000..f5708b38fb7f
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/timex.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/timex.h
+ *
+ *  AAEC-2000 Architecture timex specification
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE         508000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h
new file mode 100644
index 000000000000..fff0c94b75c4
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/uncompress.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include "hardware.h"
+
+#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
+
+static void putstr( const char *s )
+{
+        unsigned long serial_port;
+        do {
+                serial_port = _UART3_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART1_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART2_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                return;
+        } while (0);
+
+        for (; *s; s++) {
+                /* wait for space in the UART's transmitter */
+                while ((UART(UART_SR) & UART_SR_TxFF));
+                /* send the character out. */
+                UART(UART_DR) = *s;
+                /* if a LF, also do CR... */
+                if (*s == 10) {
+                        while ((UART(UART_SR) & UART_SR_TxFF));
+                        UART(UART_DR) = 13;
+                }
+        }
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-aaec2000/vmalloc.h b/include/asm-arm/arch-aaec2000/vmalloc.h
new file mode 100644
index 000000000000..ecb991e2e4ff
--- /dev/null
+++ b/include/asm-arm/arch-aaec2000/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ *  linux/include/asm-arm/arch-aaec2000/vmalloc.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h
index 2346d454ab9c..7dbc7bbba65d 100644
--- a/include/asm-arm/arch-imx/imxfb.h
+++ b/include/asm-arm/arch-imx/imxfb.h
@@ -25,6 +25,7 @@ struct imxfb_mach_info {
         u_int           pcr;
         u_int           pwmr;
         u_int           lscr1;
+        u_int           dmacr;
 
         u_char * fixed_screen_cpu;
         dma_addr_t fixed_screen_dma;
diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h
index bd364f5a99bc..96ad3d2a66d1 100644
--- a/include/asm-arm/arch-integrator/platform.h
+++ b/include/asm-arm/arch-integrator/platform.h
@@ -293,7 +293,11 @@
 #define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
 
 
+#if defined(CONFIG_ARCH_INTEGRATOR_AP)
 #define INTEGRATOR_GPIO_BASE            0x1B000000       /*  GPIO */
+#elif defined(CONFIG_ARCH_INTEGRATOR_CP)
+#define INTEGRATOR_GPIO_BASE            0xC9000000       /*  GPIO */
+#endif
 
 /* ------------------------------------------------------------------------
  *  KMI keyboard/mouse definitions
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
new file mode 100644
index 000000000000..0ec7093f7c37
--- /dev/null
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -0,0 +1,19 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+#include <linux/config.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define hard_smp_processor_id()                         \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+
+extern void secondary_scan_irqs(void);
+
+#endif
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
index 84634af5cc64..03cbbe1fd9d8 100644
--- a/include/asm-arm/arch-ixp2000/gpio.h
+++ b/include/asm-arm/arch-ixp2000/gpio.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-ixp2000/ixp2000-gpio.h
+ * include/asm-arm/arch-ixp2000/gpio.h
  *
  * Copyright (C) 2002 Intel Corporation.
  *
@@ -16,26 +16,18 @@
  * Use this instead of directly setting the GPIO registers.
  * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
  */
-#ifndef _ASM_ARCH_IXP2000_GPIO_H_
-#define _ASM_ARCH_IXP2000_GPIO_H_
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
 
 #ifndef __ASSEMBLY__
-#define GPIO_OUT                        0x0
-#define GPIO_IN                         0x80
+
+#define GPIO_IN                         0
+#define GPIO_OUT                        1
 
 #define IXP2000_GPIO_LOW                0
 #define IXP2000_GPIO_HIGH               1
 
-#define GPIO_NO_EDGES                   0
-#define GPIO_FALLING_EDGE               1
-#define GPIO_RISING_EDGE                2
-#define GPIO_BOTH_EDGES                 3
-#define GPIO_LEVEL_LOW                  4
-#define GPIO_LEVEL_HIGH                 8
-
-extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
-extern void set_GPIO_IRQ_level(int gpio_nr, int level);
-extern void gpio_line_config(int line, int style);
+extern void gpio_line_config(int line, int direction);
 
 static inline int gpio_line_get(int line)
 {
@@ -45,11 +37,12 @@ static inline int gpio_line_get(int line)
 static inline void gpio_line_set(int line, int value)
 {
         if (value == IXP2000_GPIO_HIGH) {
-                ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
-        } else if (value == IXP2000_GPIO_LOW)
-                ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
+                ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
+        } else if (value == IXP2000_GPIO_LOW) {
+                ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
+        }
 }
 
 #endif /* !__ASSEMBLY__ */
-#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
 
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 083462668e18..3241cd6f0778 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -17,18 +17,23 @@
 
 #define IO_SPACE_LIMIT          0xffffffff
 #define __mem_pci(a)            (a)
-#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
- * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
  * transactions the other way round (MEM transactions don't have this
- * issue), so we need to override the standard functions.  B0 and later
- * have a bit that can be set to 1 to get the 'proper' behavior, but
- * since that isn't available on the A? revisions we just keep doing
- * things manually.
+ * issue), so if we want to support those models, we need to override
+ * the standard I/O functions.
+ *
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
  */
-#define alignb(addr)            (void __iomem *)((unsigned long)addr ^ 3)
-#define alignw(addr)            (void __iomem *)((unsigned long)addr ^ 2)
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
+#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+#define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
+#define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
 
 #define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
 #define outw(v,p)               __raw_writew((v),alignw(___io(p)))
@@ -48,6 +53,81 @@
 #define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
 #define insl(p,d,l)             __raw_readsl(___io(p),d,l)
 
+#define __is_io_address(p)      ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
+
+#define ioread8(p)                                              \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readb(alignb(p));           \
+                } else {                                        \
+                        __v = __raw_readb(p);                   \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })                                                      \
+
+#define ioread16(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readw(alignw(p));           \
+                } else {                                        \
+                        __v = le16_to_cpu(__raw_readw(p));      \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })
+
+#define ioread32(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readl(p);                   \
+                } else {                                        \
+                        __v = le32_to_cpu(__raw_readl(p));      \
+                }                                               \
+                                                                \
+                 __v;                                           \
+        })
+
+#define iowrite8(v,p)                                           \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writeb((v), alignb(p));           \
+                } else {                                        \
+                        __raw_writeb((v), p);                   \
+                }                                               \
+        })
+
+#define iowrite16(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writew((v), alignw(p));           \
+                } else {                                        \
+                        __raw_writew(cpu_to_le16(v), p);        \
+                }                                               \
+        })
+
+#define iowrite32(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writel((v), p);                   \
+                } else {                                        \
+                        __raw_writel(cpu_to_le32(v), p);        \
+                }                                               \
+        })
+
+#define ioport_map(port, nr)    ___io(port)
+
+#define ioport_unmap(addr)
+#else
+#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
+
 
 #ifdef CONFIG_ARCH_IXDP2X01
 /*
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
index 3a398dfbf125..229381c64283 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x00.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -21,8 +21,8 @@
  * On board CPLD memory map
  */
 #define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
-#define IXDP2X00_VIRT_CPLD_BASE         0xfafff000
-#define IXDP2X00_CPLD_SIZE              0x00001000
+#define IXDP2X00_VIRT_CPLD_BASE         0xfe000000
+#define IXDP2X00_CPLD_SIZE              0x00100000
 
 
 #define IXDP2X00_CPLD_REG(x)    \
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b3a1bcda8d01..b768009c3a51 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -18,8 +18,8 @@
 #define __IXDP2X01_H__
 
 #define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
-#define IXDP2X01_VIRT_CPLD_BASE         0xfafff000
-#define IXDP2X01_CPLD_REGION_SIZE       0x00001000
+#define IXDP2X01_VIRT_CPLD_BASE         0xfe000000
+#define IXDP2X01_CPLD_REGION_SIZE       0x00100000
 
 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
 #define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 6c56708d0ff0..75623f81ef75 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -18,6 +18,21 @@
 #ifndef _IXP2000_REGS_H_
 #define _IXP2000_REGS_H_
 
+/*
+ * IXP2000 linux memory map:
+ *
+ * virt         phys            size
+ * fb000000     db000000        16M             PCI CFG1
+ * fc000000     da000000        16M             PCI CFG0
+ * fd000000     d8000000        16M             PCI I/O
+ * fe[0-7]00000                 8M              per-platform mappings
+ * feb00000     c8000000        1M              MSF
+ * fec00000     df000000        1M              PCI CSRs
+ * fed00000     de000000        1M              PCI CREG
+ * fee00000     d6000000        1M              INTCTL
+ * fef00000     c0000000        1M              CAP
+ */
+
 /* 
  * Static I/O regions.
  *
@@ -71,6 +86,10 @@
 #define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
 #define IXP2000_PCI_CSR_SIZE            0x00100000
 
+#define IXP2000_MSF_PHYS_BASE           0xc8000000
+#define IXP2000_MSF_VIRT_BASE           0xfeb00000
+#define IXP2000_MSF_SIZE                0x00100000
+
 #define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
 #define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE             0x01000000
@@ -241,7 +260,7 @@
 #define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
 #define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
 #define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_PNR                 (1 << 17)       /* PCI Not Reset bit */
+#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
 
 #define IXP2000_PCI_RST_REL             (1 << 2)
 #define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
@@ -363,6 +382,7 @@
 #define IXP2000_MIN_REV_MASK            0x0000000F
 #define IXP2000_PROD_ID_MASK            0xFFFFFFFF
 
+#define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
 #define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
 #define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
 #define IXP2000_RESET0                  GLOBAL_REG(0x0c)
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index 901bba6d02b4..c0caf3e3e6fd 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -115,6 +115,7 @@ static inline unsigned int ixp2000_is_pcimaster(void)
 }
 
 void ixp2000_map_io(void);
+void ixp2000_uart_init(void);
 void ixp2000_init_irq(void);
 void ixp2000_init_time(unsigned long);
 unsigned long ixp2000_gettimeoffset(void);
@@ -138,30 +139,10 @@ struct ixp2000_flash_data {
         unsigned long (*bank_setup)(unsigned long);
 };
 
-/*
- * GPIO helper functions
- */
-#define GPIO_IN         0
-#define GPIO_OUT        1
-
-extern void gpio_line_config(int line, int style);
-
-static inline int gpio_line_get(int line)
-{
-        return (((*IXP2000_GPIO_PLR) >> line) & 1);
-}
-
-static inline void gpio_line_set(int line, int value)
-{
-        if (value) 
-                ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
-        else 
-                ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
-}
-
 struct ixp2000_i2c_pins {
         unsigned long sda_pin;
         unsigned long scl_pin;
 };
 
+
 #endif /*  !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
index 473dff4ec561..275136963a0c 100644
--- a/include/asm-arm/arch-ixp2000/vmalloc.h
+++ b/include/asm-arm/arch-ixp2000/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END         0xfaffefff
+#define VMALLOC_END         0xfb000000
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
index 4499ae8e4b44..2e23651e217f 100644
--- a/include/asm-arm/arch-ixp4xx/debug-macro.S
+++ b/include/asm-arm/arch-ixp4xx/debug-macro.S
@@ -15,6 +15,7 @@
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0xc8000000
                 movne   \rx, #0xff000000
+                orrne   \rx, \rx, #0x00b00000
                 add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
                                                 @ byte writes used - Big Endian.
                 .endm
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index c27b9d3079a7..e350dcb544e8 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -3,7 +3,7 @@
  *
  * Author: Deepak Saxena <dsaxena@plexity.net>
  *
- * Copyright (C) 2002-2004  MontaVista Software, Inc.
+ * Copyright (C) 2002-2005  MontaVista Software, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -383,6 +383,198 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
                 *vaddr++ = inl(io_addr);
 }
 
+#define PIO_OFFSET      0x10000UL
+#define PIO_MASK        0x0ffffUL
+
+#define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
+                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
+static inline unsigned int
+__ixp4xx_ioread8(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return (unsigned int)__raw_readb(port);
+#else
+                return (unsigned int)__ixp4xx_readb(port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsb(addr, vaddr, count);
+#else
+                __ixp4xx_readsb(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread16(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le16_to_cpu(__raw_readw((u32)port));
+#else
+                return (unsigned int)__ixp4xx_readw((u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsw(addr, vaddr, count);
+#else
+                __ixp4xx_readsw(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread32(void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
+        else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le32_to_cpu(__raw_readl((u32)port));
+#else
+                return (unsigned int)__ixp4xx_readl((u32)port);
+#endif
+        }
+}
+
+static inline void
+__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsl(addr, vaddr, count);
+#else
+                __ixp4xx_readsl(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outb(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writeb(value, port);
+#else
+                __ixp4xx_writeb(value, port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesb(addr, vaddr, count);
+#else
+                __ixp4xx_writesb(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outw(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writew(cpu_to_le16(value), addr);
+#else
+                __ixp4xx_writew(value, port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesw(addr, vaddr, count);
+#else
+                __ixp4xx_writesw(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outl(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writel(cpu_to_le32(value), port);
+#else
+                __ixp4xx_writel(value, port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesl(addr, vaddr, count);
+#else
+                __ixp4xx_writesl(port, vaddr, count);
+#endif
+}
+
+#define ioread8(p)                      __ixp4xx_ioread8(p)
+#define ioread16(p)                     __ixp4xx_ioread16(p)
+#define ioread32(p)                     __ixp4xx_ioread32(p)
+
+#define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
+
+#define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
+
+#define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
+
+#define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
+#define ioport_unmap(addr)
 
 #endif  //  __ASM_ARM_ARCH_IO_H
 
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 8eeb1db6309d..004696a95bdb 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -69,6 +69,16 @@
 #define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
 
+/*
+ * Debug UART
+ *
+ * This is basically a remap of UART1 into a region that is section
+ * aligned so that it * can be used with the low-level debug code.
+ */
+#define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
+
 #define IXP4XX_EXP_CS0_OFFSET   0x00
 #define IXP4XX_EXP_CS1_OFFSET   0x04
 #define IXP4XX_EXP_CS2_OFFSET   0x08
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 3a626c03ea26..d13ee7f78c70 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_OUT                 0x1
 #define IXP4XX_GPIO_IN                  0x2
 
-#define IXP4XX_GPIO_INTSTYLE_MASK       0x7C  /* Bits [6:2] define interrupt style */
-
-/* 
- * GPIO interrupt types.
- */
-#define IXP4XX_GPIO_ACTIVE_HIGH         0x4 /* Default */
-#define IXP4XX_GPIO_ACTIVE_LOW          0x8
-#define IXP4XX_GPIO_RISING_EDGE         0x10
-#define IXP4XX_GPIO_FALLING_EDGE        0x20
-#define IXP4XX_GPIO_TRANSITIONAL        0x40
-
 /* GPIO signal types */
 #define IXP4XX_GPIO_LOW                 0
 #define IXP4XX_GPIO_HIGH                1
@@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_CLK_0               14
 #define IXP4XX_GPIO_CLK_1               15
 
-extern void gpio_line_config(u8 line, u32 style);
+static inline void gpio_line_config(u8 line, u32 direction)
+{
+        if (direction == IXP4XX_GPIO_OUT)
+                *IXP4XX_GPIO_GPOER |= (1 << line);
+        else
+                *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
 
 static inline void gpio_line_get(u8 line, int *value)
 {
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h
index 38c9d77d3727..3745e35cc030 100644
--- a/include/asm-arm/arch-ixp4xx/timex.h
+++ b/include/asm-arm/arch-ixp4xx/timex.h
@@ -7,7 +7,9 @@
 
 /*
  * We use IXP425 General purpose timer for our timer needs, it runs at 
- * 66.66... MHz
+ * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
+ * timer register ignores the bottom 2 bits of the LATCH value.
  */
-#define CLOCK_TICK_RATE (66666666)
+#define FREQ 66666666
+#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
 
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index 60f002b72983..39ca5a31aeea 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,11 +34,6 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
 
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
-
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index e4d1cd231731..1b12c1dcc2fa 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,11 +30,6 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
 
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE             SZ_32M
-#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
-
 /* Samsung NAND flash at CS2B or CS3(NAND Boot) */
 #define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
 #define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
index 79138dcfb4ac..d64ee9211eed 100644
--- a/include/asm-arm/arch-omap/board-h4.h
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -30,6 +30,9 @@
 #define __ASM_ARCH_OMAP_H4_H
 
 /* Placeholder for H4 specific defines */
+/* GPMC CS1 */
+#define OMAP24XX_ETHR_START             0x08000300
+#define OMAP24XX_ETHR_GPIO_IRQ          92
 
 #endif /*  __ASM_ARCH_OMAP_H4_H */
 
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 0f1abaefe4de..79574e0ed13d 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,31 +36,6 @@
 #define OMAP1510P1_EMIFS_PRI_VALUE              0x00
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
 
-/*
- * These definitions define an area of FLASH set aside
- * for the use of MTD/JFFS2. This is the area of flash
- * that a JFFS2 filesystem will reside which is mounted
- * at boot with the "root=/dev/mtdblock/0 rw"
- * command line option. The flash address used here must
- * fall within the legal range defined by rrload for storing
- * the filesystem component. This address will be sufficiently
- * deep into the overall flash range to avoid the other
- * components also stored in flash such as the bootloader,
- * the bootloader params, and the kernel.
- * The SW2 settings for the map below are:
- * 1 off, 2 off, 3 on, 4 off.
- */
-
-/* Intel flash_0, partitioned as expected by rrload */
-#define OMAP_FLASH_0_BASE       0xD8000000
-#define OMAP_FLASH_0_START      0x00000000
-#define OMAP_FLASH_0_SIZE       SZ_16M
-
-/* Intel flash_1, used for cramfs or other flash file systems */
-#define OMAP_FLASH_1_BASE       0xD9000000
-#define OMAP_FLASH_1_START      0x01000000
-#define OMAP_FLASH_1_SIZE       SZ_16M
-
 #define NR_FPGA_IRQS            24
 #define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
 
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index aaa49a0fbd21..2b1a8a4fe44e 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,10 +32,5 @@
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START             0x04800300
 
-/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
-#define OMAP_OSK_NOR_FLASH_BASE         0xD8000000
-#define OMAP_OSK_NOR_FLASH_SIZE         SZ_32M
-#define OMAP_OSK_NOR_FLASH_START        0x00000000
-
 #endif /*  __ASM_ARCH_OMAP_OSK_H */
 
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index 0c224cc74fe4..691e52a52b43 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,23 +36,14 @@
 #define OMAP_SDRAM_DEVICE               D256M_1X16_4B
 #endif
 
-/*
- * These definitions define an area of FLASH set aside
- * for the use of MTD/JFFS2. This is the area of flash
- * that a JFFS2 filesystem will reside which is mounted
- * at boot with the "root=/dev/mtdblock/0 rw"
- * command line option.
- */
-
-/* Intel flash_0, partitioned as expected by rrload */
-#define OMAP_FLASH_0_BASE       0xD8000000      /* VA */
-#define OMAP_FLASH_0_START      0x00000000      /* PA */
-#define OMAP_FLASH_0_SIZE       SZ_32M
-
 #define MAXIRQNUM               IH_BOARD_BASE
 #define MAXFIQNUM               MAXIRQNUM
 #define MAXSWINUM               MAXIRQNUM
 
 #define NR_IRQS                 (MAXIRQNUM + 1)
 
+/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
+#define OMAP_NAND_FLASH_START1     0x0A000000 /* CS2B */
+#define OMAP_NAND_FLASH_START2     0x0C000000 /* CS3 */
+
 #endif
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h
index 33977b8956fb..ed6d346ee123 100644
--- a/include/asm-arm/arch-omap/board-voiceblue.h
+++ b/include/asm-arm/arch-omap/board-voiceblue.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_VOICEBLUE_H
 #define __ASM_ARCH_VOICEBLUE_H
 
-#if (EXTERNAL_MAX_NR_PORTS < 4)
-#undef EXTERNAL_MAX_NR_PORTS
-#define EXTERNAL_MAX_NR_PORTS   4
-#endif
-
 extern void voiceblue_wdt_enable(void);
 extern void voiceblue_wdt_disable(void);
 extern void voiceblue_wdt_ping(void);
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 1cefd60b6f2a..a0040cd86639 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -16,10 +16,11 @@
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
 #define OMAP_TAG_MMC            0x4f02
-#define OMAP_TAG_UART           0x4f03
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 #define OMAP_TAG_USB            0x4f04
 #define OMAP_TAG_LCD            0x4f05
 #define OMAP_TAG_GPIO_SWITCH    0x4f06
+#define OMAP_TAG_UART           0x4f07
 
 #define OMAP_TAG_BOOT_REASON    0x4f80
 #define OMAP_TAG_FLASH_PART     0x4f81
@@ -29,13 +30,26 @@ struct omap_clock_config {
         u8 system_clock_type;
 };
 
+struct omap_mmc_conf {
+        unsigned enabled:1;
+        /* nomux means "standard" muxing is wrong on this board, and that
+         * board-specific code handled it before common init logic.
+         */
+        unsigned nomux:1;
+        /* switch pin can be for card detect (default) or card cover */
+        unsigned cover:1;
+        /* 4 wire signaling is optional, and is only used for SD/SDIO */
+        unsigned wire4:1;
+        s16 power_pin;
+        s16 switch_pin;
+        s16 wp_pin;
+};
+
 struct omap_mmc_config {
-        u8 mmc_blocks;
-        s16 mmc1_power_pin, mmc2_power_pin;
-        s16 mmc1_switch_pin, mmc2_switch_pin;
+        struct omap_mmc_conf mmc[2];
 };
 
-struct omap_uart_config {
+struct omap_serial_console_config {
         u8 console_uart;
         u32 console_speed;
 };
@@ -82,7 +96,8 @@ struct omap_lcd_config {
  */
 #define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
 #define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
 struct omap_gpio_switch_config {
         char name[12];
         u16 gpio;
@@ -99,6 +114,10 @@ struct omap_boot_reason_config {
         char reason_str[12];
 };
 
+struct omap_uart_config {
+        /* Bit field of UARTs present; bit 0 --> UART1 */
+        unsigned int enabled_uarts;
+};
 
 struct omap_board_config_entry {
         u16 tag;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
new file mode 100644
index 000000000000..2a676b4f13b5
--- /dev/null
+++ b/include/asm-arm/arch-omap/common.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/arch-omap/common.h
+ *
+ * Header for code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
+#define __ARCH_ARM_MACH_OMAP_COMMON_H
+
+struct sys_timer;
+
+extern void omap_map_common_io(void);
+extern struct sys_timer omap_timer;
+extern void omap_serial_init(int ports[]);
+
+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8786713ee5c..1119e2b53e72 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -38,146 +38,179 @@ extern unsigned int system_rev;
 /*
  * Test if multicore OMAP support is needed
  */
-#undef MULTI_OMAP
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
 #undef OMAP_NAME
 
 #ifdef CONFIG_ARCH_OMAP730
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
-#  define MULTI_OMAP
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
 # else
 #  define OMAP_NAME omap730
 # endif
 #endif
 #ifdef CONFIG_ARCH_OMAP1510
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
-#  define MULTI_OMAP
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
 # else
 #  define OMAP_NAME omap1510
 # endif
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 # ifdef OMAP_NAME
-#  undef  MULTI_OMAP
-#  define MULTI_OMAP
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
 # else
-#  define OMAP_NAME omap1610
+#  define OMAP_NAME omap16xx
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP
-#  define MULTI_OMAP
+#ifdef CONFIG_ARCH_OMAP24XX
+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
+#  error "OMAP1 and OMAP2 can't be selected at the same time"
 # else
-#  define OMAP_NAME omap1710
+#  undef  MULTI_OMAP2
+#  define OMAP_NAME omap24xx
 # endif
 #endif
 
 /*
- * Generate various OMAP cpu specific macros, and cpu class
- * specific macros
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730
+ * cpu_is_omap15xx():   True for OMAP1510 and OMAP5910
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ * cpu_is_omap24xx():   True for OMAP2420
  */
-#define GET_OMAP_TYPE   ((system_rev >> 24) & 0xff)
 #define GET_OMAP_CLASS  (system_rev & 0xff)
 
-#define IS_OMAP_TYPE(type, id)                          \
-static inline int is_omap ##type (void)                 \
-{                                                       \
-        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
-}
-
 #define IS_OMAP_CLASS(class, id)                        \
 static inline int is_omap ##class (void)                \
 {                                                       \
         return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
 
-IS_OMAP_TYPE(730, 0x07)
-IS_OMAP_TYPE(1510, 0x15)
-IS_OMAP_TYPE(1610, 0x16)
-IS_OMAP_TYPE(5912, 0x16)
-IS_OMAP_TYPE(1710, 0x17)
-IS_OMAP_TYPE(2420, 0x24)
-
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 
-/*
- * Macros to group OMAP types into cpu classes.
- * These can be used in most places.
- * cpu_is_omap15xx():   True for 1510 and 5910
- * cpu_is_omap16xx():   True for 1610, 5912 and 1710
- */
-#if defined(MULTI_OMAP)
-# define cpu_is_omap7xx()               is_omap7xx()
-# define cpu_is_omap15xx()              is_omap15xx()
-# if !(defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP730))
-#  define cpu_is_omap16xx()             1
-# else
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#define cpu_is_omap24xx()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
 #  define cpu_is_omap16xx()             is_omap16xx()
 # endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              1
-# else
-#  define cpu_is_omap7xx()              0
 # endif
 # if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             1
-# else
-#  define cpu_is_omap15xx()             0
 # endif
 # if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
 #  define cpu_is_omap16xx()             1
-# else
-#  define cpu_is_omap16xx()             0
+# endif
+# if defined(CONFIG_ARCH_OMAP24XX)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
 # endif
 #endif
 
-#if defined(MULTI_OMAP)
-# define cpu_is_omap730()               is_omap730()
-# define cpu_is_omap1510()              is_omap1510()
-# define cpu_is_omap1610()              is_omap1610()
-# define cpu_is_omap5912()              is_omap5912()
-# define cpu_is_omap1710()              is_omap1710()
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap730():    True for OMAP730
+ * cpu_is_omap1510():   True for OMAP1510
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ * cpu_is_omap2420():   True for OMAP2420
+ */
+#define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+IS_OMAP_TYPE(730, 0x0730)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+IS_OMAP_TYPE(2420, 0x2420)
+
+#define cpu_is_omap730()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_is_omap2420()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
+#  define cpu_is_omap730()              is_omap730()
+# endif
+# if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap1510
+#  define cpu_is_omap1510()             is_omap1510()
+# endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
 #  define cpu_is_omap730()              1
-# else
-#  define cpu_is_omap730()              0
 # endif
 # if defined(CONFIG_ARCH_OMAP1510)
+#  undef  cpu_is_omap1510
 #  define cpu_is_omap1510()             1
-# else
-#  define cpu_is_omap1510()             0
 # endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  define cpu_is_omap1610()             1
-# else
-#  define cpu_is_omap1610()             0
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  define cpu_is_omap5912()             1
-# else
-#  define cpu_is_omap5912()             0
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
+#endif
+
+/*
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ * between 1611B/5912 and 1710.
+ */
+#if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1610
+# undef  cpu_is_omap1611
+# undef  cpu_is_omap5912
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
 # define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
 # define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
 # define cpu_is_omap1710()              is_omap1710()
-# else
-# define cpu_is_omap1610()              0
-# define cpu_is_omap5912()              0
-# define cpu_is_omap1710()              0
-# endif
-# if defined(CONFIG_ARCH_OMAP2420)
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2420)
+#  undef  cpu_is_omap2420
 #  define cpu_is_omap2420()             1
-# else
-#  define cpu_is_omap2420()             0
-# endif
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
index 83bb458afd0b..ca4f577f9675 100644
--- a/include/asm-arm/arch-omap/debug-macro.S
+++ b/include/asm-arm/arch-omap/debug-macro.S
@@ -14,6 +14,7 @@
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
+#ifdef CONFIG_ARCH_OMAP1
                 moveq   \rx, #0xff000000        @ physical base address
                 movne   \rx, #0xfe000000        @ virtual base
                 orr     \rx, \rx, #0x00fb0000
@@ -23,6 +24,18 @@
 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
                 orr     \rx, \rx, #0x00000800   @ UART 2 & 3
 #endif
+
+#elif  CONFIG_ARCH_OMAP2
+                moveq   \rx, #0x48000000        @ physical base address
+                movne   \rx, #0xd8000000        @ virtual base
+                orr     \rx, \rx, #0x0006a000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART2
+                add     \rx, \rx, #0x00002000   @ UART 2
+#endif
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+                add     \rx, \rx, #0x00004000   @ UART 3
+#endif
+#endif
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index d785248377db..04ebef5c6e95 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -240,7 +240,9 @@ extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
 
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
+extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_dma_running(void);
 
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 extern int omap_dma_in_1510_mode(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
new file mode 100644
index 000000000000..11772c792f3e
--- /dev/null
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -0,0 +1,92 @@
+/*
+ * linux/include/asm-arm/arm/arch-omap/dmtimer.h
+ *
+ * OMAP Dual-Mode Timers
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+#include <linux/list.h>
+
+#define OMAP_TIMER_SRC_ARMXOR           0x00
+#define OMAP_TIMER_SRC_32_KHZ           0x01
+#define OMAP_TIMER_SRC_EXT_CLK          0x02
+
+/* timer control reg bits */
+#define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
+#define OMAP_TIMER_CTRL_PT              (1 << 12)
+#define OMAP_TIMER_CTRL_TRG_OVERFLOW    (0x1 << 10)
+#define OMAP_TIMER_CTRL_TRG_OFANDMATCH  (0x2 << 10)
+#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
+#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
+#define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
+#define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
+#define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
+#define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
+#define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
+#define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
+#define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
+
+/* timer interrupt enable bits */
+#define OMAP_TIMER_INT_CAPTURE          (1 << 2)
+#define OMAP_TIMER_INT_OVERFLOW         (1 << 1)
+#define OMAP_TIMER_INT_MATCH            (1 << 0)
+
+
+struct omap_dm_timer {
+        struct list_head timer_list;
+
+        u32 base;
+        unsigned int irq;
+};
+
+u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg);
+void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value);
+
+struct omap_dm_timer * omap_dm_timer_request(void);
+void omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
+
+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value);
+void omap_dm_timer_enable_compare(struct omap_dm_timer *timer);
+void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer);
+
+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+void omap_dm_timer_start(struct omap_dm_timer *timer);
+void omap_dm_timer_stop(struct omap_dm_timer *timer);
+
+void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load);
+void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match);
+
+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+
+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
+void omap_dm_timer_reset_counter(struct omap_dm_timer *timer);
+
+int omap_dm_timers_active(void);
+
+#endif /* __ASM_ARCH_TIMER_H */
diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h
new file mode 100644
index 000000000000..57bf4f39ca58
--- /dev/null
+++ b/include/asm-arm/arch-omap/dsp.h
@@ -0,0 +1,244 @@
+/*
+ * linux/include/asm-arm/arch-omap/dsp.h
+ *
+ * Header for OMAP DSP driver
+ *
+ * Copyright (C) 2002-2005 Nokia Corporation
+ *
+ * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * 2005/06/01:  DSP Gateway version 3.3
+ */
+
+#ifndef ASM_ARCH_DSP_H
+#define ASM_ARCH_DSP_H
+
+
+/*
+ * for /dev/dspctl/ctl
+ */
+#define OMAP_DSP_IOCTL_RESET                    1
+#define OMAP_DSP_IOCTL_RUN                      2
+#define OMAP_DSP_IOCTL_SETRSTVECT               3
+#define OMAP_DSP_IOCTL_CPU_IDLE                 4
+#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_ON         5
+#define OMAP_DSP_IOCTL_MPUI_WORDSWAP_OFF        6
+#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_ON         7
+#define OMAP_DSP_IOCTL_MPUI_BYTESWAP_OFF        8
+#define OMAP_DSP_IOCTL_GBL_IDLE                 9
+#define OMAP_DSP_IOCTL_DSPCFG                   10
+#define OMAP_DSP_IOCTL_DSPUNCFG                 11
+#define OMAP_DSP_IOCTL_TASKCNT                  12
+#define OMAP_DSP_IOCTL_POLL                     13
+#define OMAP_DSP_IOCTL_REGMEMR                  40
+#define OMAP_DSP_IOCTL_REGMEMW                  41
+#define OMAP_DSP_IOCTL_REGIOR                   42
+#define OMAP_DSP_IOCTL_REGIOW                   43
+#define OMAP_DSP_IOCTL_GETVAR                   44
+#define OMAP_DSP_IOCTL_SETVAR                   45
+#define OMAP_DSP_IOCTL_RUNLEVEL                 50
+#define OMAP_DSP_IOCTL_SUSPEND                  51
+#define OMAP_DSP_IOCTL_RESUME                   52
+#define OMAP_DSP_IOCTL_FBEN                     53
+#define OMAP_DSP_IOCTL_FBDIS                    54
+#define OMAP_DSP_IOCTL_MBSEND                   99
+
+/*
+ * for taskdev
+ * (ioctls below should be >= 0x10000)
+ */
+#define OMAP_DSP_TASK_IOCTL_BFLSH       0x10000
+#define OMAP_DSP_TASK_IOCTL_SETBSZ      0x10001
+#define OMAP_DSP_TASK_IOCTL_LOCK        0x10002
+#define OMAP_DSP_TASK_IOCTL_UNLOCK      0x10003
+#define OMAP_DSP_TASK_IOCTL_GETNAME     0x10004
+
+/*
+ * for /dev/dspctl/mem
+ */
+#define OMAP_DSP_MEM_IOCTL_EXMAP        1
+#define OMAP_DSP_MEM_IOCTL_EXUNMAP      2
+#define OMAP_DSP_MEM_IOCTL_EXMAP_FLUSH  3
+#define OMAP_DSP_MEM_IOCTL_FBEXPORT     5
+#define OMAP_DSP_MEM_IOCTL_MMUITACK     7
+#define OMAP_DSP_MEM_IOCTL_MMUINIT      9
+#define OMAP_DSP_MEM_IOCTL_KMEM_RESERVE 11
+#define OMAP_DSP_MEM_IOCTL_KMEM_RELEASE 12
+
+struct omap_dsp_mapinfo {
+        unsigned long dspadr;
+        unsigned long size;
+};
+
+/*
+ * for /dev/dspctl/twch
+ */
+#define OMAP_DSP_TWCH_IOCTL_MKDEV       1
+#define OMAP_DSP_TWCH_IOCTL_RMDEV       2
+#define OMAP_DSP_TWCH_IOCTL_TADD        11
+#define OMAP_DSP_TWCH_IOCTL_TDEL        12
+#define OMAP_DSP_TWCH_IOCTL_TKILL       13
+
+#define OMAP_DSP_DEVSTATE_NOTASK        0x00000001
+#define OMAP_DSP_DEVSTATE_ATTACHED      0x00000002
+#define OMAP_DSP_DEVSTATE_GARBAGE       0x00000004
+#define OMAP_DSP_DEVSTATE_INVALID       0x00000008
+#define OMAP_DSP_DEVSTATE_ADDREQ        0x00000100
+#define OMAP_DSP_DEVSTATE_DELREQ        0x00000200
+#define OMAP_DSP_DEVSTATE_ADDFAIL       0x00001000
+#define OMAP_DSP_DEVSTATE_ADDING        0x00010000
+#define OMAP_DSP_DEVSTATE_DELING        0x00020000
+#define OMAP_DSP_DEVSTATE_KILLING       0x00040000
+#define OMAP_DSP_DEVSTATE_STATE_MASK    0x7fffffff
+#define OMAP_DSP_DEVSTATE_STALE         0x80000000
+
+struct omap_dsp_taddinfo {
+        unsigned char minor;
+        unsigned long taskadr;
+};
+#define OMAP_DSP_TADD_ABORTADR  0xffffffff
+
+
+/*
+ * error cause definition (for error detection device)
+ */
+#define OMAP_DSP_ERRDT_WDT      0x00000001
+#define OMAP_DSP_ERRDT_MMU      0x00000002
+
+
+/*
+ * mailbox protocol definitions
+ */
+
+struct omap_dsp_mailbox_cmd {
+        unsigned short cmd;
+        unsigned short data;
+};
+
+struct omap_dsp_reginfo {
+        unsigned short adr;
+        unsigned short val;
+};
+
+struct omap_dsp_varinfo {
+        unsigned char varid;
+        unsigned short val[0];
+};
+
+#define OMAP_DSP_MBPROT_REVISION        0x0019
+
+#define OMAP_DSP_MBCMD_WDSND    0x10
+#define OMAP_DSP_MBCMD_WDREQ    0x11
+#define OMAP_DSP_MBCMD_BKSND    0x20
+#define OMAP_DSP_MBCMD_BKREQ    0x21
+#define OMAP_DSP_MBCMD_BKYLD    0x23
+#define OMAP_DSP_MBCMD_BKSNDP   0x24
+#define OMAP_DSP_MBCMD_BKREQP   0x25
+#define OMAP_DSP_MBCMD_TCTL     0x30
+#define OMAP_DSP_MBCMD_TCTLDATA 0x31
+#define OMAP_DSP_MBCMD_POLL     0x32
+#define OMAP_DSP_MBCMD_WDT      0x50    /* v3.3: obsolete */
+#define OMAP_DSP_MBCMD_RUNLEVEL 0x51
+#define OMAP_DSP_MBCMD_PM       0x52
+#define OMAP_DSP_MBCMD_SUSPEND  0x53
+#define OMAP_DSP_MBCMD_KFUNC    0x54
+#define OMAP_DSP_MBCMD_TCFG     0x60
+#define OMAP_DSP_MBCMD_TADD     0x62
+#define OMAP_DSP_MBCMD_TDEL     0x63
+#define OMAP_DSP_MBCMD_TSTOP    0x65
+#define OMAP_DSP_MBCMD_DSPCFG   0x70
+#define OMAP_DSP_MBCMD_REGRW    0x72
+#define OMAP_DSP_MBCMD_GETVAR   0x74
+#define OMAP_DSP_MBCMD_SETVAR   0x75
+#define OMAP_DSP_MBCMD_ERR      0x78
+#define OMAP_DSP_MBCMD_DBG      0x79
+
+#define OMAP_DSP_MBCMD_TCTL_TINIT       0x0000
+#define OMAP_DSP_MBCMD_TCTL_TEN         0x0001
+#define OMAP_DSP_MBCMD_TCTL_TDIS        0x0002
+#define OMAP_DSP_MBCMD_TCTL_TCLR        0x0003
+#define OMAP_DSP_MBCMD_TCTL_TCLR_FORCE  0x0004
+
+#define OMAP_DSP_MBCMD_RUNLEVEL_USER            0x01
+#define OMAP_DSP_MBCMD_RUNLEVEL_SUPER           0x0e
+#define OMAP_DSP_MBCMD_RUNLEVEL_RECOVERY        0x10
+
+#define OMAP_DSP_MBCMD_PM_DISABLE       0x00
+#define OMAP_DSP_MBCMD_PM_ENABLE        0x01
+
+#define OMAP_DSP_MBCMD_KFUNC_FBCTL      0x00
+
+#define OMAP_DSP_MBCMD_FBCTL_ENABLE     0x0002
+#define OMAP_DSP_MBCMD_FBCTL_DISABLE    0x0003
+
+#define OMAP_DSP_MBCMD_TDEL_SAFE        0x0000
+#define OMAP_DSP_MBCMD_TDEL_KILL        0x0001
+
+#define OMAP_DSP_MBCMD_DSPCFG_REQ       0x00
+#define OMAP_DSP_MBCMD_DSPCFG_SYSADRH   0x28
+#define OMAP_DSP_MBCMD_DSPCFG_SYSADRL   0x29
+#define OMAP_DSP_MBCMD_DSPCFG_PROTREV   0x70
+#define OMAP_DSP_MBCMD_DSPCFG_ABORT     0x78
+#define OMAP_DSP_MBCMD_DSPCFG_LAST      0x80
+
+#define OMAP_DSP_MBCMD_REGRW_MEMR       0x00
+#define OMAP_DSP_MBCMD_REGRW_MEMW       0x01
+#define OMAP_DSP_MBCMD_REGRW_IOR        0x02
+#define OMAP_DSP_MBCMD_REGRW_IOW        0x03
+#define OMAP_DSP_MBCMD_REGRW_DATA       0x04
+
+#define OMAP_DSP_MBCMD_VARID_ICRMASK    0x00
+#define OMAP_DSP_MBCMD_VARID_LOADINFO   0x01
+
+#define OMAP_DSP_TTYP_ARCV      0x0001
+#define OMAP_DSP_TTYP_ASND      0x0002
+#define OMAP_DSP_TTYP_BKMD      0x0004
+#define OMAP_DSP_TTYP_BKDM      0x0008
+#define OMAP_DSP_TTYP_PVMD      0x0010
+#define OMAP_DSP_TTYP_PVDM      0x0020
+
+#define OMAP_DSP_EID_BADTID     0x10
+#define OMAP_DSP_EID_BADTCN     0x11
+#define OMAP_DSP_EID_BADBID     0x20
+#define OMAP_DSP_EID_BADCNT     0x21
+#define OMAP_DSP_EID_NOTLOCKED  0x22
+#define OMAP_DSP_EID_STVBUF     0x23
+#define OMAP_DSP_EID_BADADR     0x24
+#define OMAP_DSP_EID_BADTCTL    0x30
+#define OMAP_DSP_EID_BADPARAM   0x50
+#define OMAP_DSP_EID_FATAL      0x58
+#define OMAP_DSP_EID_NOMEM      0xc0
+#define OMAP_DSP_EID_NORES      0xc1
+#define OMAP_DSP_EID_IPBFULL    0xc2
+#define OMAP_DSP_EID_WDT        0xd0
+#define OMAP_DSP_EID_TASKNOTRDY 0xe0
+#define OMAP_DSP_EID_TASKBSY    0xe1
+#define OMAP_DSP_EID_TASKERR    0xef
+#define OMAP_DSP_EID_BADCFGTYP  0xf0
+#define OMAP_DSP_EID_DEBUG      0xf8
+#define OMAP_DSP_EID_BADSEQ     0xfe
+#define OMAP_DSP_EID_BADCMD     0xff
+
+#define OMAP_DSP_TNM_LEN        16
+
+#define OMAP_DSP_TID_FREE       0xff
+#define OMAP_DSP_TID_ANON       0xfe
+
+#define OMAP_DSP_BID_NULL       0xffff
+#define OMAP_DSP_BID_PVT        0xfffe
+
+#endif /* ASM_ARCH_DSP_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h
new file mode 100644
index 000000000000..4fcce6944056
--- /dev/null
+++ b/include/asm-arm/arch-omap/dsp_common.h
@@ -0,0 +1,37 @@
+/*
+ * linux/include/asm-arm/arch-omap/dsp_common.h
+ *
+ * Header for OMAP DSP subsystem control
+ *
+ * Copyright (C) 2004,2005 Nokia Corporation
+ *
+ * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * 2005/06/03:  DSP Gateway version 3.3
+ */
+
+#ifndef ASM_ARCH_DSP_COMMON_H
+#define ASM_ARCH_DSP_COMMON_H
+
+void omap_dsp_pm_suspend(void);
+void omap_dsp_pm_resume(void);
+void omap_dsp_request_mpui(void);
+void omap_dsp_release_mpui(void);
+int omap_dsp_request_mem(void);
+int omap_dsp_release_mem(void);
+
+#endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index 57b126889b98..0d29b9c56a95 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -8,6 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#if defined(CONFIG_ARCH_OMAP1)
+
                 .macro  disable_fiq
                 .endm
 
@@ -30,3 +32,29 @@
 1510:
                 .endm
 
+#elif defined(CONFIG_ARCH_OMAP24XX)
+
+#include <asm/arch/omap24xx.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =VA_IC_BASE
+                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+                cmp     \irqnr, #0x0
+2222:
+                ldrne   \irqnr, [\base, #IRQ_SIR_IRQ]
+
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+
+#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index fad2fc93ee70..74cb2b93b700 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -3,7 +3,7 @@
  *
  * OMAP GPIO handling defines and functions
  *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003-2005 Nokia Corporation
  *
  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  *
@@ -30,7 +30,23 @@
 #include <asm/arch/irqs.h>
 #include <asm/io.h>
 
-#define OMAP_MPUIO_BASE                 0xfffb5000
+#define OMAP_MPUIO_BASE                 (void __iomem *)0xfffb5000
+
+#ifdef CONFIG_ARCH_OMAP730
+#define OMAP_MPUIO_INPUT_LATCH          0x00
+#define OMAP_MPUIO_OUTPUT               0x02
+#define OMAP_MPUIO_IO_CNTL              0x04
+#define OMAP_MPUIO_KBR_LATCH            0x08
+#define OMAP_MPUIO_KBC                  0x0a
+#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
+#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
+#define OMAP_MPUIO_KBD_INT              0x10
+#define OMAP_MPUIO_GPIO_INT             0x12
+#define OMAP_MPUIO_KBD_MASKIT           0x14
+#define OMAP_MPUIO_GPIO_MASKIT          0x16
+#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
+#define OMAP_MPUIO_LATCH                0x1a
+#else
 #define OMAP_MPUIO_INPUT_LATCH          0x00
 #define OMAP_MPUIO_OUTPUT               0x04
 #define OMAP_MPUIO_IO_CNTL              0x08
@@ -44,6 +60,7 @@
 #define OMAP_MPUIO_GPIO_MASKIT          0x2c
 #define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
 #define OMAP_MPUIO_LATCH                0x34
+#endif
 
 #define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
@@ -52,18 +69,11 @@
                                  IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                  IH_GPIO_BASE + ((nr) & 0x3f))
 
-/* For EDGECTRL */
-#define OMAP_GPIO_NO_EDGE         0x00
-#define OMAP_GPIO_FALLING_EDGE    0x01
-#define OMAP_GPIO_RISING_EDGE     0x02
-#define OMAP_GPIO_BOTH_EDGES      0x03
-
 extern int omap_gpio_init(void);        /* Call from board init only */
 extern int omap_request_gpio(int gpio);
 extern void omap_free_gpio(int gpio);
 extern void omap_set_gpio_direction(int gpio, int is_input);
 extern void omap_set_gpio_dataout(int gpio, int enable);
 extern int omap_get_gpio_datain(int gpio);
-extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
 
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 37e06c782bdf..60201e1dd6ad 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -43,6 +43,7 @@
 #include <asm/arch/cpu.h>
 #endif
 #include <asm/arch/io.h>
+#include <asm/arch/serial.h>
 
 /*
  * ---------------------------------------------------------------------------
@@ -54,6 +55,19 @@
 
 /*
  * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
+#define MPU_TIMER_FREE          (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
+#define MPU_TIMER_AR            (1 << 1)
+#define MPU_TIMER_ST            (1 << 0)
+
+/*
+ * ----------------------------------------------------------------------------
  * Clocks
  * ----------------------------------------------------------------------------
  */
@@ -76,10 +90,12 @@
 /* DPLL control registers */
 #define DPLL_CTL                (0xfffecf00)
 
-/* DSP clock control */
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
 #define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
 
 /*
  * ---------------------------------------------------------------------------
@@ -88,6 +104,7 @@
  */
 #define ULPD_REG_BASE           (0xfffe0800)
 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
 #       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 #       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
@@ -127,6 +144,13 @@
  * Interrupts
  * ---------------------------------------------------------------------------
  */
+#ifdef CONFIG_ARCH_OMAP1
+
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
+
 #define OMAP_IH1_BASE           0xfffecb00
 #define OMAP_IH2_BASE           0xfffe0000
 
@@ -155,6 +179,8 @@
 #define IRQ_ILR0_REG_OFFSET     0x1c
 #define IRQ_GMR_REG_OFFSET      0xa0
 
+#endif
+
 /*
  * ----------------------------------------------------------------------------
  * System control registers
@@ -245,40 +271,18 @@
 
 /*
  * ---------------------------------------------------------------------------
- * Serial ports
- * ---------------------------------------------------------------------------
- */
-#define OMAP_UART1_BASE         (unsigned char *)0xfffb0000
-#define OMAP_UART2_BASE         (unsigned char *)0xfffb0800
-#define OMAP_UART3_BASE         (unsigned char *)0xfffb9800
-#define OMAP_MAX_NR_PORTS       3
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
-
-#define is_omap_port(p) ({int __ret = 0;                        \
-                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
-                                __ret = 1;                      \
-                        __ret;                                  \
-                        })
-
-/*
- * ---------------------------------------------------------------------------
  * Processor specific defines
  * ---------------------------------------------------------------------------
  */
-#ifdef CONFIG_ARCH_OMAP730
-#include "omap730.h"
-#endif
 
-#ifdef CONFIG_ARCH_OMAP1510
+#include "omap730.h"
 #include "omap1510.h"
+
+#ifdef CONFIG_ARCH_OMAP24XX
+#include "omap24xx.h"
 #endif
 
-#ifdef CONFIG_ARCH_OMAP16XX
 #include "omap16xx.h"
-#endif
 
 /*
  * ---------------------------------------------------------------------------
@@ -304,7 +308,6 @@
 
 #ifdef CONFIG_MACH_OMAP_H4
 #include "board-h4.h"
-#error "Support for H4 board not yet implemented."
 #endif
 
 #ifdef CONFIG_MACH_OMAP_OSK
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 1c8c9fcc766e..11fbf629bf75 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -49,16 +49,24 @@
  * I/O mapping
  * ----------------------------------------------------------------------------
  */
-#define IO_PHYS                 0xFFFB0000
-#define IO_OFFSET               0x01000000      /* Virtual IO = 0xfefb0000 */
-#define IO_VIRT                 (IO_PHYS - IO_OFFSET)
-#define IO_SIZE                 0x40000
-#define IO_ADDRESS(x)           ((x) - IO_OFFSET)
 
-#define PCIO_BASE               0
+#if defined(CONFIG_ARCH_OMAP1)
+#define IO_PHYS         0xFFFB0000
+#define IO_OFFSET      -0x01000000      /* Virtual IO = 0xfefb0000 */
+#define IO_SIZE         0x40000
 
-#define io_p2v(x)               ((x) - IO_OFFSET)
-#define io_v2p(x)               ((x) + IO_OFFSET)
+#elif defined(CONFIG_ARCH_OMAP2)
+#define IO_PHYS         0x48000000      /* L4 peripherals; other stuff has to be mapped *
+                                         * manually. */
+#define IO_OFFSET       0x90000000      /* Virtual IO = 0xd8000000 */
+#define IO_SIZE         0x08000000
+#endif
+
+#define IO_VIRT         (IO_PHYS + IO_OFFSET)
+#define IO_ADDRESS(x)   ((x) + IO_OFFSET)
+#define PCIO_BASE       0
+#define io_p2v(x)       ((x) + IO_OFFSET)
+#define io_v2p(x)       ((x) - IO_OFFSET)
 
 #ifndef __ASSEMBLER__
 
@@ -96,6 +104,8 @@ typedef struct { volatile u32 offset[4096]; } __regbase32;
                                         ->offset[((vaddr)&4095)>>2]
 #define __REG32(paddr)          __REGV32(io_p2v(paddr))
 
+extern void omap_map_common_io(void);
+
 #else
 
 #define __REG8(paddr)           io_p2v(paddr)
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 6701fd9e5f9b..74e108ccac16 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -135,7 +135,6 @@
 /*
  * OMAP-1510 specific IRQ numbers for interrupt handler 2
  */
-#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 
 /*
@@ -159,6 +158,7 @@
 #define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
 #define INT_1610_MMC2           (42 + IH2_BASE)
 #define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
 #define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
 #define INT_1610_SPI            (49 + IH2_BASE)
 #define INT_1610_DMA_CH6        (53 + IH2_BASE)
@@ -231,6 +231,11 @@
 #define INT_730_DMA_CH15        (62 + IH2_BASE)
 #define INT_730_NAND            (63 + IH2_BASE)
 
+#define INT_24XX_GPIO_BANK1     29
+#define INT_24XX_GPIO_BANK2     30
+#define INT_24XX_GPIO_BANK3     31
+#define INT_24XX_GPIO_BANK4     32
+
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
@@ -238,6 +243,8 @@
 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
 #define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
 
+#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
+
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
 #endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
index f6b57dd846a3..84f81e315a25 100644
--- a/include/asm-arm/arch-omap/memory.h
+++ b/include/asm-arm/arch-omap/memory.h
@@ -36,12 +36,11 @@
 /*
  * Physical DRAM offset.
  */
+#if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             (0x10000000UL)
-
-/*
- * OMAP-1510 Local Bus address offset
- */
-#define OMAP1510_LB_OFFSET      (0x30000000UL)
+#elif defined(CONFIG_ARCH_OMAP2)
+#define PHYS_OFFSET             (0x80000000UL)
+#endif
 
 /*
  * Conversion between SDRAM and fake PCI bus, used by USB
@@ -64,6 +63,11 @@
  */
 #ifdef CONFIG_ARCH_OMAP1510
 
+/*
+ * OMAP-1510 Local Bus address offset
+ */
+#define OMAP1510_LB_OFFSET      (0x30000000UL)
+
 #define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
 #define is_lbus_device(dev)     (cpu_is_omap1510() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
diff --git a/include/asm-arm/arch-omap/mtd-xip.h b/include/asm-arm/arch-omap/mtd-xip.h
new file mode 100644
index 000000000000..a73a28571fee
--- /dev/null
+++ b/include/asm-arm/arch-omap/mtd-xip.h
@@ -0,0 +1,61 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions.
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ *
+ * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
+ *
+ * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
+ * terms of the GNU General Public License version 2.  This program is
+ * licensed "as is" without any warranty of any kind, whether express or
+ * implied.
+ */
+
+#ifndef __ARCH_OMAP_MTD_XIP_H__
+#define __ARCH_OMAP_MTD_XIP_H__
+
+#include <asm/hardware.h>
+#define OMAP_MPU_TIMER_BASE     (0xfffec500)
+#define OMAP_MPU_TIMER_OFFSET   0x100
+
+typedef struct {
+        u32 cntl;                       /* CNTL_TIMER, R/W */
+        u32 load_tim;                   /* LOAD_TIM,   W */
+        u32 read_tim;                   /* READ_TIM,   R */
+} xip_omap_mpu_timer_regs_t;
+
+#define xip_omap_mpu_timer_base(n)                                      \
+((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +  \
+        (n)*OMAP_MPU_TIMER_OFFSET))
+
+static inline unsigned long xip_omap_mpu_timer_read(int nr)
+{
+        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
+        return timer->read_tim;
+}
+
+#define xip_irqpending()        \
+        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
+#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
+
+/*
+ * It's permitted to do approxmation for xip_elapsed_since macro
+ * (see linux/mtd/xip.h)
+ */
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
+#else
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
+#endif
+
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+
+#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
+
+#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 39f99decbb7b..1b1ad4105349 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -185,6 +185,7 @@ typedef enum {
 
         /* MPUIO */
         MPUIO2,
+        N15_1610_MPUIO2,
         MPUIO4,
         MPUIO5,
         T20_1610_MPUIO5,
@@ -210,6 +211,7 @@ typedef enum {
 
         /* Misc ballouts */
         BALLOUT_V8_ARMIO3,
+        N20_HDQ,
 
         /* OMAP-1610 MMC2 */
         W8_1610_MMC2_DAT0,
@@ -231,23 +233,27 @@ typedef enum {
         J19_1610_ETM_D6,
         J18_1610_ETM_D7,
 
-        /* OMAP-1610 GPIO */
+        /* OMAP16XX GPIO */
         P20_1610_GPIO4,
         V9_1610_GPIO7,
         W8_1610_GPIO9,
+        N20_1610_GPIO11,
         N19_1610_GPIO13,
         P10_1610_GPIO22,
         V5_1610_GPIO24,
         AA20_1610_GPIO_41,
         W19_1610_GPIO48,
         M7_1610_GPIO62,
+        V14_16XX_GPIO37,
+        R9_16XX_GPIO18,
+        L14_16XX_GPIO49,
 
         /* OMAP-1610 uWire */
         V19_1610_UWIRE_SCLK,
         U18_1610_UWIRE_SDI,
         W21_1610_UWIRE_SDO,
         N14_1610_UWIRE_CS0,
-        P15_1610_UWIRE_CS0,
+        P15_1610_UWIRE_CS3,
         N15_1610_UWIRE_CS1,
 
         /* OMAP-1610 Flash */
@@ -285,12 +291,13 @@ typedef enum {
         V6_USB2_TXD,
         W5_USB2_SE0,
 
-        /* UART1 1610 */
-
+        /* 16XX UART */
         R13_1610_UART1_TX,
-        V14_1610_UART1_RX,
+        V14_16XX_UART1_RX,
         R14_1610_UART1_CTS,
         AA15_1610_UART1_RTS,
+        R9_16XX_UART2_RX,
+        L14_16XX_UART3_RX,
 
         /* I2C OMAP-1610 */
         I2C_SCL,
@@ -332,7 +339,7 @@ typedef enum {
  * Table of various FUNC_MUX and PULL_DWN combinations for each device.
  * See also reg_cfg_t above for the lookup table.
  */
-static reg_cfg_set __initdata_or_module
+static const reg_cfg_set __initdata_or_module
 reg_cfg_table[] = {
 /*
  *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
@@ -407,7 +414,8 @@ MUX_CFG("N21_1710_GPIO14",       6,    9,    0,   1,   1,   1,    1,     1,  1)
 MUX_CFG("W15_1710_GPIO40",       9,   27,    7,   2,   5,   1,    2,     1,  1)
 
 /* MPUIO */
-MUX_CFG("MPUIO2",                7,   18,    0,   1,   1,   1,   NA,     0,  1)
+MUX_CFG("MPUIO2",                7,   18,    0,   1,  14,   1,   NA,     0,  1)
+MUX_CFG("N15_1610_MPUIO2",       7,   18,    0,   1,  14,   1,    1,     0,  1)
 MUX_CFG("MPUIO4",                7,   15,    0,   1,  13,   1,   NA,     0,  1)
 MUX_CFG("MPUIO5",                7,   12,    0,   1,  12,   1,   NA,     0,  1)
 
@@ -434,6 +442,7 @@ MUX_CFG("MCBSP3_CLKX",		 9,    3,    1,	  1,  29,   0,	 NA,	 0,  1)
 
 /* Misc ballouts */
 MUX_CFG("BALLOUT_V8_ARMIO3",     B,   18,    0,   2,  25,   1,   NA,     0,  1)
+MUX_CFG("N20_HDQ",             6,   18,    1,   1,   4,   0,    1,     4,  0)
 
 /* OMAP-1610 MMC2 */
 MUX_CFG("W8_1610_MMC2_DAT0",     B,   21,    6,   2,  23,   1,    2,     1,  1)
@@ -455,16 +464,20 @@ MUX_CFG("L19_1610_ETM_D0",	 5,   18,    1,	  0,  26,   0,	  0,	 0,  1)
 MUX_CFG("J19_1610_ETM_D6",       5,    0,    1,   0,  20,   0,    0,     0,  1)
 MUX_CFG("J18_1610_ETM_D7",       5,   27,    1,   0,  19,   0,    0,     0,  1)
 
-/* OMAP-1610 GPIO */
+/* OMAP16XX GPIO */
 MUX_CFG("P20_1610_GPIO4",        6,   27,    0,   1,   7,   0,    1,     1,  1)
 MUX_CFG("V9_1610_GPIO7",         B,   12,    1,   2,  20,   0,    2,     1,  1)
 MUX_CFG("W8_1610_GPIO9",         B,   21,    0,   2,  23,   0,    2,     1,  1)
+MUX_CFG("N20_1610_GPIO11",       6,   18,    0,   1,   4,   0,    1,     1,  1)
 MUX_CFG("N19_1610_GPIO13",       6,   12,    0,   1,   2,   0,    1,     1,  1)
 MUX_CFG("P10_1610_GPIO22",       C,    0,    7,   2,  26,   0,    2,     1,  1)
 MUX_CFG("V5_1610_GPIO24",        B,   15,    7,   2,  21,   0,    2,     1,  1)
 MUX_CFG("AA20_1610_GPIO_41",     9,    9,    7,   1,  31,   0,    1,     1,  1)
 MUX_CFG("W19_1610_GPIO48",       8,   15,    7,   1,  23,   1,    1,     0,  1)
 MUX_CFG("M7_1610_GPIO62",       10,    0,    0,   4,  24,   0,    4,     0,  1)
+MUX_CFG("V14_16XX_GPIO37",       9,   18,    7,   2,   2,   0,    2,     2,  0)
+MUX_CFG("R9_16XX_GPIO18",        C,   18,    7,   3,   0,   0,    3,     0,  0)
+MUX_CFG("L14_16XX_GPIO49",       6,    3,    7,   0,  31,   0,    0,    31,  0)
 
 /* OMAP-1610 uWire */
 MUX_CFG("V19_1610_UWIRE_SCLK",   8,    6,    0,   1,  20,   0,    1,     1,  1)
@@ -503,16 +516,17 @@ MUX_CFG("Y10_USB0_SUSP",	 B,   3,     5,	  2,  17,   0,	  2,	 0,  1)
 MUX_CFG("W9_USB2_TXEN",          B,   9,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("AA9_USB2_VP",           B,   6,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("Y5_USB2_RCV",           C,  21,     1,  NA,   0,   0,   NA,     0,  1)
-MUX_CFG("R8_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("R9_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("V6_USB2_TXD",           C,  27,     2,  NA,   0,   0,   NA,     0,  1)
 MUX_CFG("W5_USB2_SE0",           C,  24,     2,  NA,   0,   0,   NA,     0,  1)
 
-
-/* UART1 */
+/* 16XX UART */
 MUX_CFG("R13_1610_UART1_TX",     A,  12,     6,   2,  10,   0,    2,    10,  1)
-MUX_CFG("V14_1610_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
+MUX_CFG("V14_16XX_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
 MUX_CFG("R14_1610_UART1_CTS",    9,  15,     0,   2,   1,   0,    2,     1,  1)
 MUX_CFG("AA15_1610_UART1_RTS",   9,  12,     1,   2,   0,   0,    2,     0,  1)
+MUX_CFG("R9_16XX_UART2_RX",      C,  18,     0,   3,   0,   0,    3,     0,  1)
+MUX_CFG("L14_16XX_UART3_RX",     6,   3,     0,   0,  31,   0,    0,    31,  1)
 
 /* I2C interface */
 MUX_CFG("I2C_SCL",               7,  24,     0,  NA,   0,   0,   NA,     0,  0)
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
index f491a48ef2e1..f086a3933906 100644
--- a/include/asm-arm/arch-omap/omap1510.h
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -36,10 +36,6 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP1510_SRAM_BASE      0xD0000000
-#define OMAP1510_SRAM_SIZE      (SZ_128K + SZ_64K)
-#define OMAP1510_SRAM_START     0x20000000
-
 #define OMAP1510_DSP_BASE       0xE0000000
 #define OMAP1510_DSP_SIZE       0x28000
 #define OMAP1510_DSP_START      0xE0000000
@@ -48,14 +44,5 @@
 #define OMAP1510_DSPREG_SIZE    SZ_128K
 #define OMAP1510_DSPREG_START   0xE1000000
 
-/*
- * ----------------------------------------------------------------------------
- * Memory used by power management
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1510_SRAM_IDLE_SUSPEND      (OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200)
-#define OMAP1510_SRAM_API_SUSPEND       (OMAP1510_SRAM_IDLE_SUSPEND + 0x100)
-
 #endif /*  __ASM_ARCH_OMAP1510_H */
 
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index 88b1fe43ae9e..f0c7f0fb4dc0 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -36,11 +36,6 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP16XX_SRAM_BASE      0xD0000000
-#define OMAP1610_SRAM_SIZE      (SZ_16K)
-#define OMAP5912_SRAM_SIZE      0x3E800
-#define OMAP16XX_SRAM_START     0x20000000
-
 #define OMAP16XX_DSP_BASE       0xE0000000
 #define OMAP16XX_DSP_SIZE       0x28000
 #define OMAP16XX_DSP_START      0xE0000000
@@ -50,17 +45,6 @@
 #define OMAP16XX_DSPREG_START   0xE1000000
 
 /*
- * ----------------------------------------------------------------------------
- * Memory used by power management
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1610_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
-#define OMAP1610_SRAM_API_SUSPEND       (OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
-#define OMAP5912_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
-#define OMAP5912_SRAM_API_SUSPEND       (OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
-
-/*
  * ---------------------------------------------------------------------------
  * Interrupts
  * ---------------------------------------------------------------------------
@@ -183,5 +167,37 @@
 #define OMAP16XX_PWL_ENABLE     (OMAP16XX_PWL_BASE + 0x00)
 #define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
 
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* 32-bit Watchdog timer in OMAP 16XX */
+#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
+#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
+#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
+#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
+#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
+#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
+#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
+#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
+
+#define WCLR_PRE_SHIFT         5
+#define WCLR_PTV_SHIFT         2
+
+#define WWPS_W_PEND_WSPR       (1 << 4)
+#define WWPS_W_PEND_WTGR       (1 << 3)
+#define WWPS_W_PEND_WLDR       (1 << 2)
+#define WWPS_W_PEND_WCRR       (1 << 1)
+#define WWPS_W_PEND_WCLR       (1 << 0)
+
+#define WSPR_ENABLE_0          (0x0000bbbb)
+#define WSPR_ENABLE_1          (0x00004444)
+#define WSPR_DISABLE_0         (0x0000aaaa)
+#define WSPR_DISABLE_1         (0x00005555)
+
 #endif /*  __ASM_ARCH_OMAP16XX_H */
 
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
new file mode 100644
index 000000000000..a9105466a417
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARCH_OMAP24XX_H
+#define __ASM_ARCH_OMAP24XX_H
+
+#define OMAP24XX_L4_IO_BASE     0x48000000
+
+/* interrupt controller */
+#define OMAP24XX_IC_BASE        (OMAP24XX_L4_IO_BASE + 0xfe000)
+#define VA_IC_BASE              IO_ADDRESS(OMAP24XX_IC_BASE)
+
+#define OMAP24XX_IVA_INTC_BASE  0x40000000
+
+#define IRQ_SIR_IRQ             0x0040
+
+#endif /* __ASM_ARCH_OMAP24XX_H */
+
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
index 599ab00f5488..755b64c5e9f0 100644
--- a/include/asm-arm/arch-omap/omap730.h
+++ b/include/asm-arm/arch-omap/omap730.h
@@ -36,10 +36,6 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP730_SRAM_BASE       0xD0000000
-#define OMAP730_SRAM_SIZE       (SZ_128K + SZ_64K + SZ_8K)
-#define OMAP730_SRAM_START      0x20000000
-
 #define OMAP730_DSP_BASE        0xE0000000
 #define OMAP730_DSP_SIZE        0x50000
 #define OMAP730_DSP_START       0xE0000000
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
index f209fc0953fb..fbd742d0c499 100644
--- a/include/asm-arm/arch-omap/pm.h
+++ b/include/asm-arm/arch-omap/pm.h
@@ -61,7 +61,10 @@
 #define PER_EN                          0x1
 
 #define CPU_SUSPEND_SIZE                200
-#define ULPD_LOW_POWER_EN               0x0001
+#define ULPD_LOW_PWR_EN                 0x0001
+#define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
+#define ULPD_SETUP_ANALOG_CELL_3_VAL    0
+#define ULPD_POWER_CTRL_REG_VAL         0x0219
 
 #define DSP_IDLE_DELAY                  10
 #define DSP_IDLE                        0x0040
@@ -86,46 +89,35 @@
 #define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
 #define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
 #define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
-#define OMAP1510_ULPD_LOW_POWER_REQ     0x0001
 
-#define OMAP1610_DEEP_SLEEP_REQUEST     0x17c7
-#define OMAP1610_BIG_SLEEP_REQUEST      TBD
+/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
+#define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
+#define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
+#define OMAP1610_IDLECT3_VAL            0x3f
+#define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
+#define OMAP1610_IDLECT3                0xfffece24
 #define OMAP1610_IDLE_LOOP_REQUEST      0x0400
-#define OMAP1610_IDLE_CLOCK_DOMAINS     0x09c7
-#define OMAP1610_ULPD_LOW_POWER_REQ     0x3
-
-#ifndef OMAP1510_SRAM_IDLE_SUSPEND
-#define OMAP1510_SRAM_IDLE_SUSPEND 0
-#endif
-#ifndef OMAP1610_SRAM_IDLE_SUSPEND
-#define OMAP1610_SRAM_IDLE_SUSPEND 0
-#endif
-#ifndef OMAP5912_SRAM_IDLE_SUSPEND
-#define OMAP5912_SRAM_IDLE_SUSPEND 0
-#endif
-
-#ifndef OMAP1510_SRAM_API_SUSPEND
-#define OMAP1510_SRAM_API_SUSPEND 0
-#endif
-#ifndef OMAP1610_SRAM_API_SUSPEND
-#define OMAP1610_SRAM_API_SUSPEND 0
-#endif
-#ifndef OMAP5912_SRAM_API_SUSPEND
-#define OMAP5912_SRAM_API_SUSPEND 0
-#endif
 
 #if     !defined(CONFIG_ARCH_OMAP1510) && \
-        !defined(CONFIG_ARCH_OMAP16XX)
+        !defined(CONFIG_ARCH_OMAP16XX) && \
+        !defined(CONFIG_ARCH_OMAP24XX)
 #error "Power management for this processor not implemented yet"
 #endif
 
 #ifndef __ASSEMBLER__
 extern void omap_pm_idle(void);
 extern void omap_pm_suspend(void);
-extern int omap1510_cpu_suspend(unsigned short, unsigned short);
-extern int omap1610_cpu_suspend(unsigned short, unsigned short);
-extern int omap1510_idle_loop_suspend(void);
-extern int omap1610_idle_loop_suspend(void);
+extern void omap1510_cpu_suspend(unsigned short, unsigned short);
+extern void omap1610_cpu_suspend(unsigned short, unsigned short);
+extern void omap1510_idle_loop_suspend(void);
+extern void omap1610_idle_loop_suspend(void);
+
+#ifdef CONFIG_OMAP_SERIAL_WAKE
+extern void omap_serial_wake_trigger(int enable);
+#else
+#define omap_serial_wake_trigger(x)     {}
+#endif  /* CONFIG_OMAP_SERIAL_WAKE */
+
 extern unsigned int omap1510_cpu_suspend_sz;
 extern unsigned int omap1510_idle_loop_suspend_sz;
 extern unsigned int omap1610_cpu_suspend_sz;
@@ -161,6 +153,7 @@ enum arm_save_state {
         ARM_SLEEP_SAVE_ARM_CKCTL,
         ARM_SLEEP_SAVE_ARM_IDLECT1,
         ARM_SLEEP_SAVE_ARM_IDLECT2,
+        ARM_SLEEP_SAVE_ARM_IDLECT3,
         ARM_SLEEP_SAVE_ARM_EWUPCT,
         ARM_SLEEP_SAVE_ARM_RSTCT1,
         ARM_SLEEP_SAVE_ARM_RSTCT2,
diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h
new file mode 100644
index 000000000000..79a5297af9fc
--- /dev/null
+++ b/include/asm-arm/arch-omap/serial.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/include/asm-arm/arch-omap/serial.h
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#if defined(CONFIG_ARCH_OMAP1)
+/* OMAP1 serial ports */
+#define OMAP_UART1_BASE         0xfffb0000
+#define OMAP_UART2_BASE         0xfffb0800
+#define OMAP_UART3_BASE         0xfffb9800
+#elif defined(CONFIG_ARCH_OMAP2)
+/* OMAP2 serial ports */
+#define OMAP_UART1_BASE         0x4806a000
+#define OMAP_UART2_BASE         0x4806c000
+#define OMAP_UART3_BASE         0x4806e000
+#endif
+
+#define OMAP_MAX_NR_PORTS       3
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+
+#define is_omap_port(p) ({int __ret = 0;                        \
+                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
+                                __ret = 1;                      \
+                        __ret;                                  \
+                        })
+
+#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 17a2c4825f07..ff37bc27e603 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -5,7 +5,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 #include <linux/config.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
+#include <asm/mach-types.h>
 
 static inline void arch_idle(void)
 {
@@ -14,7 +16,24 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode)
 {
-        omap_writew(1, ARM_RSTCT1);
+
+#ifdef CONFIG_ARCH_OMAP16XX
+        /*
+         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+         * "Global Software Reset Affects Traffic Controller Frequency".
+         */
+        if (cpu_is_omap5912()) {
+                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+                                 DPLL_CTL);
+                omap_writew(0x8, ARM_RSTCT1);
+        }
+#endif
+#ifdef CONFIG_MACH_VOICEBLUE
+        if (machine_is_voiceblue())
+                voiceblue_reset();
+        else
+#endif
+                omap_writew(1, ARM_RSTCT1);
 }
 
 #endif
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
index 0f97bb2e8fce..b9aa2b3a3909 100644
--- a/include/asm-arm/arch-omap/tps65010.h
+++ b/include/asm-arm/arch-omap/tps65010.h
@@ -30,6 +30,66 @@
 
 /*
  * ----------------------------------------------------------------------------
+ * Registers, all 8 bits
+ * ----------------------------------------------------------------------------
+ */
+
+#define TPS_CHGSTATUS           0x01
+#       define  TPS_CHG_USB             (1 << 7)
+#       define  TPS_CHG_AC              (1 << 6)
+#       define  TPS_CHG_THERM           (1 << 5)
+#       define  TPS_CHG_TERM            (1 << 4)
+#       define  TPS_CHG_TAPER_TMO       (1 << 3)
+#       define  TPS_CHG_CHG_TMO         (1 << 2)
+#       define  TPS_CHG_PRECHG_TMO      (1 << 1)
+#       define  TPS_CHG_TEMP_ERR        (1 << 0)
+#define TPS_REGSTATUS           0x02
+#       define  TPS_REG_ONOFF           (1 << 7)
+#       define  TPS_REG_COVER           (1 << 6)
+#       define  TPS_REG_UVLO            (1 << 5)
+#       define  TPS_REG_NO_CHG          (1 << 4)        /* tps65013 */
+#       define  TPS_REG_PG_LD02         (1 << 3)
+#       define  TPS_REG_PG_LD01         (1 << 2)
+#       define  TPS_REG_PG_MAIN         (1 << 1)
+#       define  TPS_REG_PG_CORE         (1 << 0)
+#define TPS_MASK1               0x03
+#define TPS_MASK2               0x04
+#define TPS_ACKINT1             0x05
+#define TPS_ACKINT2             0x06
+#define TPS_CHGCONFIG           0x07
+#       define  TPS_CHARGE_POR          (1 << 7)        /* 65010/65012 */
+#       define  TPS65013_AUA            (1 << 7)        /* 65011/65013 */
+#       define  TPS_CHARGE_RESET        (1 << 6)
+#       define  TPS_CHARGE_FAST         (1 << 5)
+#       define  TPS_CHARGE_CURRENT      (3 << 3)
+#       define  TPS_VBUS_500MA          (1 << 2)
+#       define  TPS_VBUS_CHARGING       (1 << 1)
+#       define  TPS_CHARGE_ENABLE       (1 << 0)
+#define TPS_LED1_ON             0x08
+#define TPS_LED1_PER            0x09
+#define TPS_LED2_ON             0x0a
+#define TPS_LED2_PER            0x0b
+#define TPS_VDCDC1              0x0c
+#       define  TPS_ENABLE_LP           (1 << 3)
+#define TPS_VDCDC2              0x0d
+#define TPS_VREGS1              0x0e
+#       define  TPS_LDO2_ENABLE (1 << 7)
+#       define  TPS_LDO2_OFF    (1 << 6)
+#       define  TPS_VLDO2_3_0V  (3 << 4)
+#       define  TPS_VLDO2_2_75V (2 << 4)
+#       define  TPS_VLDO2_2_5V  (1 << 4)
+#       define  TPS_VLDO2_1_8V  (0 << 4)
+#       define  TPS_LDO1_ENABLE (1 << 3)
+#       define  TPS_LDO1_OFF    (1 << 2)
+#       define  TPS_VLDO1_3_0V  (3 << 0)
+#       define  TPS_VLDO1_2_75V (2 << 0)
+#       define  TPS_VLDO1_2_5V  (1 << 0)
+#       define  TPS_VLDO1_ADJ   (0 << 0)
+#define TPS_MASK3               0x0f
+#define TPS_DEFGPIO             0x10
+
+/*
+ * ----------------------------------------------------------------------------
  * Macros used by exported functions
  * ----------------------------------------------------------------------------
  */
@@ -71,10 +131,26 @@ extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
  */
 extern int tps65010_set_led(unsigned led, unsigned mode);
 
+/* tps65010_set_vib parameter:
+ * value: ON or OFF
+ */
+extern int tps65010_set_vib(unsigned value);
+
 /* tps65010_set_low_pwr parameter:
  * mode: ON or OFF
  */
 extern int tps65010_set_low_pwr(unsigned mode);
 
+/* tps65010_config_vregs1 parameter:
+ * value to be written to VREGS1 register
+ * Note: The complete register is written, set all bits you need
+ */
+extern int tps65010_config_vregs1(unsigned value);
+
+/* tps65013_set_low_pwr parameter:
+ * mode: ON or OFF
+ */
+extern int tps65013_set_low_pwr(unsigned mode);
+
 #endif /*  __ASM_ARCH_TPS65010_H */
 
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index 3e640aba8c20..3545c86859cc 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -20,7 +20,7 @@
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/serial.h>
 
 unsigned int system_rev;
 
@@ -34,8 +34,9 @@ static void
 putstr(const char *s)
 {
         volatile u8 * uart = 0;
-        int shift;
+        int shift = 2;
 
+#ifdef CONFIG_ARCH_OMAP
 #ifdef  CONFIG_OMAP_LL_DEBUG_UART3
         uart = (volatile u8 *)(OMAP_UART3_BASE);
 #elif   CONFIG_OMAP_LL_DEBUG_UART2
@@ -44,6 +45,7 @@ putstr(const char *s)
         uart = (volatile u8 *)(OMAP_UART1_BASE);
 #endif
 
+#ifdef CONFIG_ARCH_OMAP1
         /* Determine which serial port to use */
         do {
                 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
@@ -51,14 +53,14 @@ putstr(const char *s)
 
                 if (omap_id == OMAP_ID_730)
                         shift = 0;
-                else
-                        shift = 2;
 
                 if (check_port(uart, shift))
                         break;
                 /* Silent boot if no serial ports are enabled. */
                 return;
         } while (0);
+#endif /* CONFIG_ARCH_OMAP1 */
+#endif
 
         /*
          * Now, xmit each character
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 1438c6cef0ca..054fb9a8e0c6 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -47,6 +47,15 @@
 #       define   HMC_TLLATTACH          (1 << 6)
 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
 #define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#       define   OTG_USB2_EN            (1 << 29)
+#       define   OTG_USB2_DP            (1 << 28)
+#       define   OTG_USB2_DM            (1 << 27)
+#       define   OTG_USB1_EN            (1 << 26)
+#       define   OTG_USB1_DP            (1 << 25)
+#       define   OTG_USB1_DM            (1 << 24)
+#       define   OTG_USB0_EN            (1 << 23)
+#       define   OTG_USB0_DP            (1 << 22)
+#       define   OTG_USB0_DM            (1 << 21)
 #       define   OTG_ASESSVLD           (1 << 20)
 #       define   OTG_BSESSEND           (1 << 19)
 #       define   OTG_BSESSVLD           (1 << 18)
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index 324db06b5dd4..4b7aa0b8391e 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -103,18 +103,20 @@
  * Shared data structures
  */
 extern struct platform_device corgiscoop_device;
+extern struct platform_device corgissp_device;
+extern struct platform_device corgifb_device;
 
 /*
  * External Functions
  */
 extern unsigned long corgi_ssp_ads7846_putget(unsigned long);
 extern unsigned long corgi_ssp_ads7846_get(void);
-extern void corgi_ssp_ads7846_put(ulong data);
+extern void corgi_ssp_ads7846_put(unsigned long data);
 extern void corgi_ssp_ads7846_lock(void);
 extern void corgi_ssp_ads7846_unlock(void);
-extern void corgi_ssp_lcdtg_send (u8 adrs, u8 data);
+extern void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data);
 extern void corgi_ssp_blduty_set(int duty);
-extern int corgi_ssp_max1111_get(ulong data);
+extern int corgi_ssp_max1111_get(unsigned long data);
 
 #endif /* __ASM_ARCH_CORGI_H  */
 
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
index f288e74b67c2..b6ec68879176 100644
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -11,6 +11,8 @@
  *
 */
 
+#include "hardware.h"
+
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 72b04d846a23..cf35721cfa45 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,24 +44,12 @@
 
 #ifndef __ASSEMBLY__
 
-#if 0
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
 
 /* With indexed regs we don't want to feed the index through io_p2v()
    especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y)     (*(volatile u32 *)((u32)&__REG(x) + (y)))
+# define __REG2(x,y)    \
+        (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
 
 # define __PREG(x)      (io_v2p((u32)&(x)))
 
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index 7492ea7ea614..88c17dd02ed2 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -9,7 +9,9 @@ struct mmc_host;
 
 struct pxamci_platform_data {
         unsigned int ocr_mask;                  /* available voltages */
+        unsigned long detect_delay;             /* delay in jiffies before detecting cards after interrupt */
         int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
+        int (*get_ro)(struct device *);
         void (*setpower)(struct device *, unsigned int);
         void (*exit)(struct device *, void *);
 };
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h
new file mode 100644
index 000000000000..8704dbceb432
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mtd-xip.h
@@ -0,0 +1,37 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+
+#ifndef __ARCH_PXA_MTD_XIP_H__
+#define __ARCH_PXA_MTD_XIP_H__
+
+#include <asm/arch/pxa-regs.h>
+
+#define xip_irqpending()        (ICIP & ICMR)
+
+/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
+#define xip_currtime()          (OSCR)
+#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+
+#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
+
+#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index b5e54a9e9fa7..939d9e5020a0 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -818,6 +818,23 @@
 #define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
                                            Interrupt Enable */
 
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+
 #define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
 #define UDCCSR0_SA      (1 << 7)        /* Setup Active */
@@ -1423,6 +1440,7 @@
 #define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
 #define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
 #define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
 #define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
@@ -1505,10 +1523,13 @@
 #define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
 #define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
 #define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
 #define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
 #define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
 #define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
 
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
 #define PCFR_RO         (1 << 15)       /* RDH Override */
 #define PCFR_PO         (1 << 14)       /* PH Override */
 #define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
@@ -1516,6 +1537,7 @@
 #define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
 #define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
 #define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
 #define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
 #define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
 #define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
@@ -1809,6 +1831,11 @@
 #define LCCR0_PDD_S     12
 #define LCCR0_BM        (1 << 20)       /* Branch mask */
 #define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
+#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
+#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
+#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
+#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
+#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
 
 #define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
 #define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
@@ -1965,6 +1992,7 @@
 #define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
 #define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
 
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
 #define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
 #define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
 #define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
@@ -2060,7 +2088,10 @@
 #define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
 #define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
 #define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
+
 #define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
+
 #define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
 #define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
 #define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h
new file mode 100644
index 000000000000..5675b1796b55
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-cpld.h
@@ -0,0 +1,24 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-cpld.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *
+*/
+
+#ifndef __ASM_ARCH_ANUBISCPLD_H
+#define __ASM_ARCH_ANUBISCPLD_H
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+
+#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-irq.h b/include/asm-arm/arch-s3c2410/anubis-irq.h
new file mode 100644
index 000000000000..82f15dbd97e8
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-irq.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-irq.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  ANUBIS - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ */
+
+#ifndef __ASM_ARCH_ANUBISIRQ_H
+#define __ASM_ARCH_ANUBISIRQ_H
+
+#define IRQ_IDE0       IRQ_EINT2
+#define IRQ_IDE1       IRQ_EINT3
+#define IRQ_ASIX       IRQ_EINT1
+
+#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
new file mode 100644
index 000000000000..97741d6e506a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -0,0 +1,46 @@
+/* linux/include/asm-arm/arch-s3c2410/anubis-map.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+*/
+
+/* needs arch/map.h including with this */
+
+#ifndef __ASM_ARCH_ANUBISMAP_H
+#define __ASM_ARCH_ANUBISMAP_H
+
+/* start peripherals off after the S3C2410 */
+
+#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x02000000))
+
+#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01300000 */
+#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
+
+#define ANUBIS_VA_CTRL2     ANUBIS_IOADDR(0x00100000)    /* 0x01400000 */
+#define ANUBIS_PA_CTRL2     (ANUBIS_PA_CPLD)
+
+#define ANUBIS_VA_CTRL3     ANUBIS_IOADDR(0x00200000)    /* 0x01500000 */
+#define ANUBIS_PA_CTRL3     (ANUBIS_PA_CPLD)
+
+#define ANUBIS_VA_CTRL4     ANUBIS_IOADDR(0x00300000)    /* 0x01600000 */
+#define ANUBIS_PA_CTRL4     (ANUBIS_PA_CPLD)
+
+#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
+
+#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h
new file mode 100644
index 000000000000..0d276e67f2fb
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/audio.h
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-s3c2410/audio.h
+ *
+ * (c) 2004-2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Audio platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *      20-Nov-2004 BJD  Created file
+ *      07-Mar-2005 BJD  Added suspend/resume calls
+*/
+
+#ifndef __ASM_ARCH_AUDIO_H
+#define __ASM_ARCH_AUDIO_H __FILE__
+
+/* struct s3c24xx_iis_ops
+ *
+ * called from the s3c24xx audio core to deal with the architecture
+ * or the codec's setup and control.
+ *
+ * the pointer to itself is passed through in case the caller wants to
+ * embed this in an larger structure for easy reference to it's context.
+*/
+
+struct s3c24xx_iis_ops {
+        struct module *owner;
+
+        int     (*startup)(struct s3c24xx_iis_ops *me);
+        void    (*shutdown)(struct s3c24xx_iis_ops *me);
+        int     (*suspend)(struct s3c24xx_iis_ops *me);
+        int     (*resume)(struct s3c24xx_iis_ops *me);
+
+        int     (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
+        int     (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
+        int     (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt);
+};
+
+struct s3c24xx_platdata_iis {
+        const char              *codec_clk;
+        struct s3c24xx_iis_ops  *ops;
+        int                     (*match_dev)(struct device *dev);
+};
+
+#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e5e938b79acc..16f4c3cc1388 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,7 +1,7 @@
 /* linux/include/asm/arch-s3c2410/regs-clock.h
  *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
+ * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://armlinux.simtec.co.uk/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,6 +17,7 @@
  *    29-Sep-2004 Ben Dooks         Fixed usage for assembly inclusion
  *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
  *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
+ *    27-Aug-2005 Ben Dooks         Add clock-slow info
  */
 
 #ifndef __ASM_ARM_REGS_CLOCK
@@ -74,6 +75,12 @@
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
 
+#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
+#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
+#define S3C2410_CLKSLOW_SLOW            (1<<4)
+#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
+#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
+
 #ifndef __ASSEMBLY__
 
 static inline unsigned int
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 385b07d510da..fdd62e8cd6cb 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -15,6 +15,9 @@
  *    12-03-2004     BJD     Updated include protection
  *    07-03-2005     BJD     Added FIFO size flags and S3C2440 MPLL
  *    05-04-2005     LCVR    Added IISFCON definitions for the S3C2400
+ *    18-07-2005     DA      Change IISCON_MPLL to IISMOD_MPLL
+ *                           Correct IISMOD_256FS and IISMOD_384FS
+ *                           Add IISCON_PSCEN
  */
 
 #ifndef __ASM_ARCH_REGS_IIS_H
@@ -22,7 +25,6 @@
 
 #define S3C2410_IISCON   (0x00)
 
-#define S3C2440_IISCON_MPLL       (1<<9)
 #define S3C2410_IISCON_LRINDEX    (1<<8)
 #define S3C2410_IISCON_TXFIFORDY  (1<<7)
 #define S3C2410_IISCON_RXFIFORDY  (1<<6)
@@ -30,10 +32,12 @@
 #define S3C2410_IISCON_RXDMAEN    (1<<4)
 #define S3C2410_IISCON_TXIDLE     (1<<3)
 #define S3C2410_IISCON_RXIDLE     (1<<2)
+#define S3C2410_IISCON_PSCEN      (1<<1)
 #define S3C2410_IISCON_IISEN      (1<<0)
 
 #define S3C2410_IISMOD   (0x04)
 
+#define S3C2440_IISMOD_MPLL       (1<<9)
 #define S3C2410_IISMOD_SLAVE      (1<<8)
 #define S3C2410_IISMOD_NOXFER     (0<<6)
 #define S3C2410_IISMOD_RXMODE     (1<<6)
@@ -46,8 +50,8 @@
 #define S3C2410_IISMOD_8BIT       (0<<3)
 #define S3C2410_IISMOD_16BIT      (1<<3)
 #define S3C2410_IISMOD_BITMASK    (1<<3)
-#define S3C2410_IISMOD_256FS      (0<<1)
-#define S3C2410_IISMOD_384FS      (1<<1)
+#define S3C2410_IISMOD_256FS      (0<<2)
+#define S3C2410_IISMOD_384FS      (1<<2)
 #define S3C2410_IISMOD_16FS       (0<<0)
 #define S3C2410_IISMOD_32FS       (1<<0)
 #define S3C2410_IISMOD_48FS       (2<<0)
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h
index 1cc85a096b23..bd43b566db3e 100644
--- a/include/asm-arm/arch-s3c2410/usb-control.h
+++ b/include/asm-arm/arch-s3c2410/usb-control.h
@@ -12,6 +12,7 @@
  * Changelog:
  *  11-Sep-2004 BJD  Created file
  *  21-Sep-2004 BJD  Updated port info
+ *  09-Aug-2005 BJD  Renamed s3c2410_report_oc s3c2410_usb_report_oc
 */
 
 #ifndef __ASM_ARCH_USBCONTROL_H
@@ -35,7 +36,7 @@ struct s3c2410_hcd_info {
         void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
 };
 
-static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
+static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
 {
         if (info->report_oc != NULL) {
                 (info->report_oc)(info, ports);
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 10c62db34362..19c3b1e186bb 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -49,23 +49,9 @@
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
 #ifndef __ASSEMBLY__
-#include <asm/types.h>
 
-#if 0
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
-#else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-#endif
-
-# define __PREG(x)      (io_v2p((u32)&(x)))
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
 #else
 
diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h
new file mode 100644
index 000000000000..f58a22755c61
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mcp.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-sa1100/mcp.h
+ *
+ *  Copyright (C) 2005 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_ARCH_MCP_H
+#define __ASM_ARM_ARCH_MCP_H
+
+#include <linux/types.h>
+
+struct mcp_plat_data {
+        u32 mccr0;
+        u32 mccr1;
+        unsigned int sclk_rate;
+};
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/include/asm-arm/arch-sa1100/mtd-xip.h
new file mode 100644
index 000000000000..80cfdac2b944
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mtd-xip.h
@@ -0,0 +1,26 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+
+#ifndef __ARCH_SA1100_MTD_XIP_H__
+#define __ARCH_SA1100_MTD_XIP_H__
+
+#define xip_irqpending()        (ICIP & ICMR)
+
+/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
+#define xip_currtime()          (OSCR)
+#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+
+#endif /* __ARCH_SA1100_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 1e7f26bc2e1d..5e6ed0038b2b 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -21,38 +21,8 @@
  */
 #define __PORT_PCIO(x)  (!((x) & 0x80000000))
 
-/*
- * Dynamic IO functions - let the compiler
- * optimize the expressions
- */
-#define DECLARE_DYN_OUT(fnsuffix,instr)                                         \
-static inline void __out##fnsuffix (unsigned int value, unsigned int port)      \
-{                                                                               \
-        unsigned long temp;                                                     \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "str" instr "   %1, [%0, %2]    @ out" #fnsuffix                        \
-        : "=&r" (temp)                                                          \
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)   \
-        : "cc");                                                                \
-}
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
 
-#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
-static inline unsigned sz __in##fnsuffix (unsigned int port)            \
-{                                                                               \
-        unsigned long temp, value;                                              \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "ldr" instr "   %1, [%0, %2]    @ in" #fnsuffix                         \
-        : "=&r" (temp), "=r" (value)                                            \
-        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
-        : "cc");                                                                \
-        return (unsigned sz)value;                                              \
-}
 
 static inline unsigned int __ioaddr (unsigned int port)                 \
 {                                                                               \
@@ -62,123 +32,8 @@ static inline unsigned int __ioaddr (unsigned int port)			\
                 return (unsigned int)(IO_BASE + (port));                        \
 }
 
-#define DECLARE_IO(sz,fnsuffix,instr)   \
-        DECLARE_DYN_OUT(fnsuffix,instr) \
-        DECLARE_DYN_IN(sz,fnsuffix,instr)
-
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"h")
-DECLARE_IO(long,l,"")
-
-#undef DECLARE_IO
-#undef DECLARE_DYN_OUT
-#undef DECLARE_DYN_IN
-
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port)                                                     \
-({                                                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]            @ outbc"                        \
-                : : "r" (value), "r" (PCIO_BASE), "Jr" (port));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]            @ outbc"                        \
-                : : "r" (value), "r" (IO_BASE), "r" (port));            \
-})
-
-#define __inbc(port)                                                            \
-({                                                                              \
-        unsigned char result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]            @ inbc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]            @ inbc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result;                                                                 \
-})
-
-#define __outwc(value,port)                                                     \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strh   %0, [%1, %2]            @ outwc"                        \
-                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" (port));       \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strh   %0, [%1, %2]            @ outwc"                        \
-                : : "r" (v|v<<16), "r" (IO_BASE), "r" (port));          \
-})
-
-#define __inwc(port)                                                            \
-({                                                                              \
-        unsigned short result;                                                  \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrh   %0, [%1, %2]            @ inwc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrh   %0, [%1, %2]            @ inwc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result & 0xffff;                                                        \
-})
-
-#define __outlc(value,port)                                                             \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]            @ outlc"                        \
-                : : "r" (v), "r" (PCIO_BASE), "Jr" (port));             \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]            @ outlc"                        \
-                : : "r" (v), "r" (IO_BASE), "r" (port));                        \
-})
-
-#define __inlc(port)                                                            \
-({                                                                              \
-        unsigned long result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]            @ inlc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]            @ inlc"                         \
-                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
-        result;                                                                 \
-})
-
-#define __ioaddrc(port)                                                         \
-({                                                                              \
-        unsigned long addr;                                                     \
-        if (__PORT_PCIO((port)))                                                \
-                addr = PCIO_BASE + (port);                              \
-        else                                                                    \
-                addr = IO_BASE + (port);                                        \
-        addr;                                                                   \
-})
-
 #define __mem_pci(addr) (addr)
 
-#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
-#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
-#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
-#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
-
 /*
  * Translated address IO functions
  *
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h
index d5fb4a251e7f..41c1bee342ad 100644
--- a/include/asm-arm/arch-versatile/hardware.h
+++ b/include/asm-arm/arch-versatile/hardware.h
@@ -25,19 +25,26 @@
 #include <asm/sizes.h>
 #include <asm/arch/platform.h>
 
-// FIXME = PCI settings need to be fixed!!!!!
-
 /*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
+ * PCI space virtual addresses
  */
-#define PCI_MEMORY_VADDR       0xe8000000
-#define PCI_CONFIG_VADDR       0xec000000
-#define PCI_V3_VADDR           0xed000000
-#define PCI_IO_VADDR           0xee000000
+#define VERSATILE_PCI_VIRT_BASE         0xe8000000
+#define VERSATILE_PCI_CFG_VIRT_BASE     0xe9000000
+
+#if 0
+#define VERSATILE_PCI_VIRT_MEM_BASE0    0xf4000000
+#define VERSATILE_PCI_VIRT_MEM_BASE1    0xf5000000
+#define VERSATILE_PCI_VIRT_MEM_BASE2    0xf6000000
+
+#define PCIO_BASE                       VERSATILE_PCI_VIRT_MEM_BASE0
+#define PCIMEM_BASE                     VERSATILE_PCI_VIRT_MEM_BASE1
+#endif
+
+/* CIK guesswork */
+#define PCIBIOS_MIN_IO                  0x44000000
+#define PCIBIOS_MIN_MEM                 0x50000000
 
-#define PCIO_BASE               PCI_IO_VADDR
-#define PCIMEM_BASE             PCI_MEMORY_VADDR
+#define pcibios_assign_all_busses()     1
 
 /* macro to get at IO space when running virtually */
 #define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
index dbb7158788fc..9f895bf61494 100644
--- a/include/asm-arm/arch-versatile/io.h
+++ b/include/asm-arm/arch-versatile/io.h
@@ -20,7 +20,7 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffff
+#define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h
index 2598d1f08548..cbdd9fb96332 100644
--- a/include/asm-arm/arch-versatile/platform.h
+++ b/include/asm-arm/arch-versatile/platform.h
@@ -76,7 +76,7 @@
 #define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
 #define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
 #define VERSATILE_SYS_RESETCTL_OFFSET         0x40
-#define VERSATILE_SYS_PICCTL_OFFSET           0x44
+#define VERSATILE_SYS_PCICTL_OFFSET           0x44
 #define VERSATILE_SYS_MCI_OFFSET              0x48
 #define VERSATILE_SYS_FLASH_OFFSET            0x4C
 #define VERSATILE_SYS_CLCD_OFFSET             0x50
@@ -114,7 +114,7 @@
 #define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
 #define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
 #define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
-#define VERSATILE_SYS_PICCTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
+#define VERSATILE_SYS_PCICTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
 #define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
 #define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
 #define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
@@ -225,7 +225,20 @@
 #define VERSATILE_SSMC_BASE            0x20000000       /* SSMC */
 #define VERSATILE_IB2_BASE             0x24000000       /* IB2 module */
 #define VERSATILE_MBX_BASE             0x40000000       /* MBX */
+
+/* PCI space */
 #define VERSATILE_PCI_BASE             0x41000000       /* PCI Interface */
+#define VERSATILE_PCI_CFG_BASE         0x42000000
+#define VERSATILE_PCI_MEM_BASE0        0x44000000
+#define VERSATILE_PCI_MEM_BASE1        0x50000000
+#define VERSATILE_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define VERSATILE_PCI_BASE_SIZE        0x01000000
+#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
+#define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000       /* 32Mb */
+#define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000       /* 256Mb */
+#define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000       /* 256Mb */
+
 #define VERSATILE_SDRAM67_BASE         0x70000000       /* SDRAM banks 6 and 7 */
 #define VERSATILE_LT_BASE              0x80000000       /* Logic Tile expansion */
 
@@ -498,11 +511,17 @@
 /*
  * IB2 Versatile/AB expansion board definitions
  */
-#define VERSATILE_IB2_CAMERA_BANK       0x24000000
-#define VERSATILE_IB2_KBD_DATAREG       0x25000000
-#define VERSATILE_IB2_IER               0x26000000      /* for VICINTSOURCE27 */
-#define VERSATILE_IB2_CTRL              0x27000000
-#define VERSATILE_IB2_STAT              0x27000004
+#define VERSATILE_IB2_CAMERA_BANK       VERSATILE_IB2_BASE
+#define VERSATILE_IB2_KBD_DATAREG       (VERSATILE_IB2_BASE + 0x01000000)
+
+/* VICINTSOURCE27 */
+#define VERSATILE_IB2_INT_BASE          (VERSATILE_IB2_BASE + 0x02000000)
+#define VERSATILE_IB2_IER               (VERSATILE_IB2_INT_BASE + 0)
+#define VERSATILE_IB2_ISR               (VERSATILE_IB2_INT_BASE + 4)
+
+#define VERSATILE_IB2_CTL_BASE          (VERSATILE_IB2_BASE + 0x03000000)
+#define VERSATILE_IB2_CTRL              (VERSATILE_IB2_CTL_BASE + 0)
+#define VERSATILE_IB2_STAT              (VERSATILE_IB2_CTL_BASE + 4)
 #endif
 
 #endif
diff --git a/include/asm-arm/auxvec.h b/include/asm-arm/auxvec.h
new file mode 100644
index 000000000000..c0536f6b29a7
--- /dev/null
+++ b/include/asm-arm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMARM_AUXVEC_H
+#define __ASMARM_AUXVEC_H
+
+#endif
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 4edd4dc40c5b..aad7aad026b3 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -21,8 +21,8 @@
 
 #include <asm/system.h>
 
-#define smp_mb__before_clear_bit()      do { } while (0)
-#define smp_mb__after_clear_bit()       do { } while (0)
+#define smp_mb__before_clear_bit()      mb()
+#define smp_mb__after_clear_bit()       mb()
 
 /*
  * These functions are the basis of our bit ops.
@@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset);
 extern int _find_first_bit_be(const unsigned long *p, unsigned size);
 extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 
+#ifndef CONFIG_SMP
 /*
  * The __* form of bitops are non-atomic and may be reordered.
  */
@@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
         (__builtin_constant_p(nr) ?             \
          ____atomic_##name(nr, p) :             \
          _##name##_be(nr,p))
+#else
+#define ATOMIC_BITOP_LE(name,nr,p)      _##name##_le(nr,p)
+#define ATOMIC_BITOP_BE(name,nr,p)      _##name##_be(nr,p)
+#endif
 
 #define NONATOMIC_BITOP(name,nr,p)              \
         (____nonatomic_##name(nr, p))
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 24d11672eb60..7fb02138f585 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -5,7 +5,7 @@
 
 #ifdef CONFIG_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
-extern volatile void __bug(const char *file, int line, void *data);
+extern void __bug(const char *file, int line, void *data) __attribute__((noreturn));
 
 /* give file/line information */
 #define BUG()           __bug(__FILE__, __LINE__, NULL)
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 09ffeed507c2..e81baff4f54b 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -16,6 +16,9 @@
 
 #include <asm/mman.h>
 #include <asm/glue.h>
+#include <asm/shmparam.h>
+
+#define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
 /*
  *      Cache Model
@@ -253,7 +256,7 @@ extern void dmac_flush_range(unsigned long, unsigned long);
  * Convert calls to our calling convention.
  */
 #define flush_cache_all()               __cpuc_flush_kern_all()
-
+#ifndef CONFIG_CPU_CACHE_VIPT
 static inline void flush_cache_mm(struct mm_struct *mm)
 {
         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
@@ -276,6 +279,11 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l
                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
         }
 }
+#else
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
+#endif
 
 /*
  * flush_cache_user_range is used when we want to ensure that the
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index ff48022e4720..4679f63688e9 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -31,7 +31,7 @@ extern struct processor {
         /*
          * Special stuff for a reset
          */
-        volatile void (*reset)(unsigned long addr);
+        void (*reset)(unsigned long addr) __attribute__((noreturn));
         /*
          * Idle the processor
          */
diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
index b5ec5d54665d..6723e67244fa 100644
--- a/include/asm-arm/cpu-single.h
+++ b/include/asm-arm/cpu-single.h
@@ -41,4 +41,4 @@ extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_set_pte(pte_t *ptep, pte_t pte);
-extern volatile void cpu_reset(unsigned long addr);
+extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
diff --git a/include/asm-arm/emergency-restart.h b/include/asm-arm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-arm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-arm/fcntl.h b/include/asm-arm/fcntl.h
index 485b6bdf4d7a..a80b6607b2ef 100644
--- a/include/asm-arm/fcntl.h
+++ b/include/asm-arm/fcntl.h
@@ -1,87 +1,11 @@
 #ifndef _ARM_FCNTL_H
 #define _ARM_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
 #define O_LARGEFILE     0400000
-#define O_NOATIME       01000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
+#include <asm-generic/fcntl.h>
 
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif
diff --git a/include/asm-arm/futex.h b/include/asm-arm/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-arm/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/include/asm-arm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
+#define __ASM_ARM_HARDWARE_ARM_TIMER_H
+
+#define TIMER_LOAD      0x00
+#define TIMER_VALUE     0x04
+#define TIMER_CTRL      0x08
+#define TIMER_CTRL_ONESHOT      (1 << 0)
+#define TIMER_CTRL_32BIT        (1 << 1)
+#define TIMER_CTRL_DIV1         (0 << 2)
+#define TIMER_CTRL_DIV16        (1 << 2)
+#define TIMER_CTRL_DIV256       (2 << 2)
+#define TIMER_CTRL_IE           (1 << 5)        /* Interrupt Enable (versatile only) */
+#define TIMER_CTRL_PERIODIC     (1 << 6)
+#define TIMER_CTRL_ENABLE       (1 << 7)
+
+#define TIMER_INTCLR    0x0c
+#define TIMER_RIS       0x10
+#define TIMER_MIS       0x14
+#define TIMER_BGLOAD    0x18
+
+#endif
diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h
new file mode 100644
index 000000000000..3fa5eb70f64e
--- /dev/null
+++ b/include/asm-arm/hardware/gic.h
@@ -0,0 +1,41 @@
+/*
+ *  linux/include/asm-arm/hardware/gic.h
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_HARDWARE_GIC_H
+#define __ASM_ARM_HARDWARE_GIC_H
+
+#include <linux/compiler.h>
+
+#define GIC_CPU_CTRL                    0x00
+#define GIC_CPU_PRIMASK                 0x04
+#define GIC_CPU_BINPOINT                0x08
+#define GIC_CPU_INTACK                  0x0c
+#define GIC_CPU_EOI                     0x10
+#define GIC_CPU_RUNNINGPRI              0x14
+#define GIC_CPU_HIGHPRI                 0x18
+
+#define GIC_DIST_CTRL                   0x000
+#define GIC_DIST_CTR                    0x004
+#define GIC_DIST_ENABLE_SET             0x100
+#define GIC_DIST_ENABLE_CLEAR           0x180
+#define GIC_DIST_PENDING_SET            0x200
+#define GIC_DIST_PENDING_CLEAR          0x280
+#define GIC_DIST_ACTIVE_BIT             0x300
+#define GIC_DIST_PRI                    0x400
+#define GIC_DIST_TARGET                 0x800
+#define GIC_DIST_CONFIG                 0xc00
+#define GIC_DIST_SOFTINT                0xf00
+
+#ifndef __ASSEMBLY__
+void gic_dist_init(void __iomem *base);
+void gic_cpu_init(void __iomem *base);
+void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
+#endif
+
+#endif
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index 7ea771ff6144..527404b5a8df 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -40,6 +40,19 @@ struct scoop_config {
         unsigned short io_dir;
 };
 
+/* Structure for linking scoop devices to PCMCIA sockets */
+struct scoop_pcmcia_dev {
+        struct device *dev;     /* Pointer to this socket's scoop device */
+        int     irq;                /* irq for socket */
+        int cd_irq;
+        const char *cd_irq_str;
+        unsigned char keep_vs;
+        unsigned char keep_rd;
+};
+
+extern int scoop_num;
+extern struct scoop_pcmcia_dev *scoop_devs;
+
 void reset_scoop(struct device *dev);
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
 unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
diff --git a/include/asm-arm/hdreg.h b/include/asm-arm/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-arm/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
index 2114acb3d237..4f68c8a5a199 100644
--- a/include/asm-arm/ide.h
+++ b/include/asm-arm/ide.h
@@ -5,7 +5,7 @@
  */
 
 /*
- *  This file contains the i386 architecture specific IDE code.
+ *  This file contains the ARM architecture specific IDE code.
  */
 
 #ifndef __ASMARM_IDE_H
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 658ffa384fda..cfa71a0dffb6 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -82,7 +82,7 @@ extern void __readwrite_bug(const char *fn);
  * only.  Their primary purpose is to access PCI and ISA peripherals.
  *
  * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
  * ARM documents:
  *
  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
@@ -273,6 +273,35 @@ extern void __iounmap(void __iomem *addr);
 #endif
 
 /*
+ * io{read,write}{8,16,32} macros
+ */
+#ifndef ioread8
+#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
+#define ioread16(p)     ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
+#define ioread32(p)     ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
+
+#define iowrite8(v,p)   __raw_writeb(v, p)
+#define iowrite16(v,p)  __raw_writew(cpu_to_le16(v), p)
+#define iowrite32(v,p)  __raw_writel(cpu_to_le32(v), p)
+
+#define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
+#define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
+#define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
+
+#define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
+#define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
+#define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
+
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *addr);
+#endif
+
+struct pci_dev;
+
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
+
+/*
  * can the hardware map this into one segment or not, given no other
  * constraints.
  */
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index c26298f3891f..f08dc8447913 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -28,7 +28,8 @@
 "       blmi    " #fail                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         })
 
 #define __down_op_ret(ptr,fail)                 \
@@ -48,12 +49,14 @@
 "       mov     %0, ip"                         \
         : "=&r" (ret)                           \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         ret;                                    \
         })
 
 #define __up_op(ptr,wake)                       \
         ({                                      \
+        smp_mb();                               \
         __asm__ __volatile__(                   \
         "@ up_op\n"                             \
 "1:     ldrex   lr, [%0]\n"                     \
@@ -61,12 +64,12 @@
 "       strex   ip, lr, [%0]\n"                 \
 "       teq     ip, #0\n"                       \
 "       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
+"       cmp     lr, #0\n"                       \
 "       movle   ip, %0\n"                       \
 "       blle    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
         })
 
 /*
@@ -92,15 +95,17 @@
 "       blne    " #fail                         \
         :                                       \
         : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         })
 
 #define __up_op_write(ptr,wake)                 \
         ({                                      \
+        smp_mb();                               \
         __asm__ __volatile__(                   \
         "@ up_op_read\n"                        \
 "1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
+"       adds    lr, lr, %1\n"                   \
 "       strex   ip, lr, [%0]\n"                 \
 "       teq     ip, #0\n"                       \
 "       bne     1b\n"                           \
@@ -108,7 +113,7 @@
 "       blcs    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
         })
 
 #define __down_op_read(ptr,fail)                \
@@ -116,6 +121,7 @@
 
 #define __up_op_read(ptr,wake)                  \
         ({                                      \
+        smp_mb();                               \
         __asm__ __volatile__(                   \
         "@ up_op_read\n"                        \
 "1:     ldrex   lr, [%0]\n"                     \
@@ -128,7 +134,7 @@
 "       bleq    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
         })
 
 #else
@@ -148,7 +154,8 @@
 "       blmi    " #fail                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         })
 
 #define __down_op_ret(ptr,fail)                 \
@@ -169,12 +176,14 @@
 "       mov     %0, ip"                         \
         : "=&r" (ret)                           \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         ret;                                    \
         })
 
 #define __up_op(ptr,wake)                       \
         ({                                      \
+        smp_mb();                               \
         __asm__ __volatile__(                   \
         "@ up_op\n"                             \
 "       mrs     ip, cpsr\n"                     \
@@ -188,7 +197,7 @@
 "       blle    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
         })
 
 /*
@@ -215,7 +224,8 @@
 "       blne    " #fail                         \
         :                                       \
         : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         })
 
 #define __up_op_write(ptr,wake)                 \
@@ -233,7 +243,8 @@
 "       blcs    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
+        smp_mb();                               \
         })
 
 #define __down_op_read(ptr,fail)                \
@@ -241,6 +252,7 @@
 
 #define __up_op_read(ptr,wake)                  \
         ({                                      \
+        smp_mb();                               \
         __asm__ __volatile__(                   \
         "@ up_op_read\n"                        \
 "       mrs     ip, cpsr\n"                     \
@@ -254,7 +266,7 @@
 "       bleq    " #wake                         \
         :                                       \
         : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc", "memory");          \
+        : "ip", "lr", "cc");                    \
         })
 
 #endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 3a32e929ec8c..56c6bf4ab0c3 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -26,7 +26,7 @@ struct machine_desc {
                                                  * page tabe entry      */
 
         const char              *name;          /* architecture name    */
-        unsigned int            param_offset;   /* parameter page       */
+        unsigned long           boot_params;    /* tagged list          */
 
         unsigned int            video_start;    /* start of video RAM   */
         unsigned int            video_end;      /* end of video RAM     */
@@ -54,38 +54,6 @@ const struct machine_desc __mach_desc_##_type	\
         .nr             = MACH_TYPE_##_type,    \
         .name           = _name,
 
-#define MAINTAINER(n)
-
-#define BOOT_MEM(_pram,_pio,_vio)               \
-        .phys_ram       = _pram,                \
-        .phys_io        = _pio,                 \
-        .io_pg_offst    = ((_vio)>>18)&0xfffc,
-
-#define BOOT_PARAMS(_params)                    \
-        .param_offset   = _params,
-
-#define VIDEO(_start,_end)                      \
-        .video_start    = _start,               \
-        .video_end      = _end,
-
-#define DISABLE_PARPORT(_n)                     \
-        .reserve_lp##_n = 1,
-
-#define SOFT_REBOOT                             \
-        .soft_reboot    = 1,
-
-#define FIXUP(_func)                            \
-        .fixup          = _func,
-
-#define MAPIO(_func)                            \
-        .map_io         = _func,
-
-#define INITIRQ(_func)                          \
-        .init_irq       = _func,
-
-#define INIT_MACHINE(_func)                     \
-        .init_machine   = _func,
-
 #define MACHINE_END                             \
 };
 
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index a43a353f6c7b..0ce6ca588d8c 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -42,11 +42,11 @@ struct irqchip {
         /*
          * Set the type of the IRQ.
          */
-        int (*type)(unsigned int, unsigned int);
+        int (*set_type)(unsigned int, unsigned int);
         /*
          * Set wakeup-enable on the selected IRQ
          */
-        int (*wake)(unsigned int, unsigned int);
+        int (*set_wake)(unsigned int, unsigned int);
 
 #ifdef CONFIG_SMP
         /*
@@ -92,6 +92,14 @@ struct irqdesc {
 extern struct irqdesc irq_desc[];
 
 /*
+ * Helpful inline function for calling irq descriptor handlers.
+ */
+static inline void desc_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+        desc->handle(irq, desc, regs);
+}
+
+/*
  * This is internal.  Do not use it.
  */
 extern void (*init_arch_irq)(void);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5cf4fd659fd5..96c6db7dd0e1 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -39,8 +39,29 @@ struct sys_timer {
         void                    (*suspend)(void);
         void                    (*resume)(void);
         unsigned long           (*offset)(void);
+
+#ifdef CONFIG_NO_IDLE_HZ
+        struct dyn_tick_timer   *dyn_tick;
+#endif
+};
+
+#ifdef CONFIG_NO_IDLE_HZ
+
+#define DYN_TICK_ENABLED        (1 << 1)
+
+struct dyn_tick_timer {
+        unsigned int    state;                  /* Current state */
+        int             (*enable)(void);        /* Enables dynamic tick */
+        int             (*disable)(void);       /* Disables dynamic tick */
+        void            (*reprogram)(unsigned long); /* Reprograms the timer */
+        int             (*handler)(int, void *, struct pt_regs *);
 };
 
+void timer_dyn_reprogram(void);
+#else
+#define timer_dyn_reprogram()   do { } while (0)
+#endif
+
 extern struct sys_timer *system_timer;
 extern void timer_tick(struct pt_regs *);
 
diff --git a/include/asm-arm/mtd-xip.h b/include/asm-arm/mtd-xip.h
new file mode 100644
index 000000000000..9eb127cc7db2
--- /dev/null
+++ b/include/asm-arm/mtd-xip.h
@@ -0,0 +1,26 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+
+#ifndef __ARM_MTD_XIP_H__
+#define __ARM_MTD_XIP_H__
+
+#include <asm/hardware.h>
+#include <asm/arch/mtd-xip.h>
+
+/* fill instruction prefetch */
+#define xip_iprefetch()         do { asm volatile (".rep 8; nop; .endr"); } while (0)
+
+#endif /* __ARM_MTD_XIP_H__ */
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 019c45d75730..4da1d532cbeb 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -163,20 +163,6 @@ typedef unsigned long pgprot_t;
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
 
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #include <asm/memory.h>
 
 #endif /* !__ASSEMBLY__ */
@@ -186,4 +172,6 @@ static inline int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 40ffaefbeb1a..38ea5899a580 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -14,7 +14,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -42,6 +42,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
 #define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 #define HAVE_PCI_MMAP
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
@@ -50,6 +60,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                          struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index e814f8144f8b..bc18ff405181 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -89,6 +89,13 @@ static inline void pte_free(struct page *pte)
         __free_page(pte);
 }
 
+static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
+{
+        pmdp[0] = __pmd(pmdval);
+        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+        flush_pmd_entry(pmdp);
+}
+
 /*
  * Populate the pmdp entry with a pointer to the pte.  This pmd is part
  * of the mm address space.
@@ -99,32 +106,19 @@ static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 {
         unsigned long pte_ptr = (unsigned long)ptep;
-        unsigned long pmdval;
-
-        BUG_ON(mm != &init_mm);
 
         /*
          * The pmd must be loaded with the physical
          * address of the PTE table
          */
         pte_ptr -= PTRS_PER_PTE * sizeof(void *);
-        pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
-        pmdp[0] = __pmd(pmdval);
-        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
-        flush_pmd_entry(pmdp);
+        __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE);
 }
 
 static inline void
 pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
 {
-        unsigned long pmdval;
-
-        BUG_ON(mm == &init_mm);
-
-        pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
-        pmdp[0] = __pmd(pmdval);
-        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
-        flush_pmd_entry(pmdp);
+        __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
 }
 
 #endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index a9892eb42a23..478c49b56e18 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -188,12 +188,18 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 /*
  *   - extended small page/tiny page
  */
+#define PTE_EXT_XN              (1 << 0)        /* v6 */
 #define PTE_EXT_AP_MASK         (3 << 4)
+#define PTE_EXT_AP0             (1 << 4)
+#define PTE_EXT_AP1             (2 << 4)
 #define PTE_EXT_AP_UNO_SRO      (0 << 4)
-#define PTE_EXT_AP_UNO_SRW      (1 << 4)
-#define PTE_EXT_AP_URO_SRW      (2 << 4)
-#define PTE_EXT_AP_URW_SRW      (3 << 4)
+#define PTE_EXT_AP_UNO_SRW      (PTE_EXT_AP0)
+#define PTE_EXT_AP_URO_SRW      (PTE_EXT_AP1)
+#define PTE_EXT_AP_URW_SRW      (PTE_EXT_AP1|PTE_EXT_AP0)
 #define PTE_EXT_TEX(x)          ((x) << 6)      /* v5 */
+#define PTE_EXT_APX             (1 << 9)        /* v6 */
+#define PTE_EXT_SHARED          (1 << 10)       /* v6 */
+#define PTE_EXT_NG              (1 << 11)       /* v6 */
 
 /*
  *   - small page
@@ -224,6 +230,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_WRITE             (1 << 5)
 #define L_PTE_EXEC              (1 << 6)
 #define L_PTE_DIRTY             (1 << 7)
+#define L_PTE_SHARED            (1 << 10)       /* shared between CPUs (v6) */
+#define L_PTE_ASID              (1 << 11)       /* non-global (use ASID, v6) */
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
index 46e69ae395af..760f6e65af05 100644
--- a/include/asm-arm/signal.h
+++ b/include/asm-arm/signal.h
@@ -114,6 +114,7 @@ typedef unsigned long sigset_t;
 #define SIGSTKSZ        8192
 
 #ifdef __KERNEL__
+#define SA_TIMER                0x40000000
 #define SA_IRQNOMASK            0x08000000
 #endif
 
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f21fd8f6bcdd..dbb4d859c586 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -21,10 +21,7 @@
 # error "<asm-arm/smp.h> included in non-SMP build"
 #endif
 
-#define smp_processor_id()      (current_thread_info()->cpu)
-
-extern cpumask_t cpu_present_mask;
-#define cpu_possible_map cpu_present_mask
+#define raw_smp_processor_id() (current_thread_info()->cpu)
 
 /*
  * at the moment, there's not a big penalty for changing CPUs
@@ -55,4 +52,18 @@ extern void smp_cross_call(cpumask_t callmap);
  */
 extern int boot_secondary(unsigned int cpu, struct task_struct *);
 
+/*
+ * Perform platform specific initialisation of the specified CPU.
+ */
+extern void platform_secondary_init(unsigned int cpu);
+
+/*
+ * Initial data for bringing up a secondary CPU.
+ */
+struct secondary_data {
+        unsigned long pgdir;
+        void *stack;
+};
+extern struct secondary_data secondary_data;
+
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h
index 46d20585d951..3c51da6438c9 100644
--- a/include/asm-arm/socket.h
+++ b/include/asm-arm/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index 182323619caa..1f906d09b688 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -8,9 +8,10 @@
 /*
  * ARMv6 Spin-locking.
  *
- * We (exclusively) read the old value, and decrement it.  If it
- * hits zero, we may have won the lock, so we try (exclusively)
- * storing it.
+ * We exclusively read the old value.  If it is zero, we may have
+ * won the lock, so we try exclusively storing it.  A memory barrier
+ * is required after we get a lock, and before we release it, because
+ * V6 CPUs are assumed to have weakly ordered memory.
  *
  * Unlocked value: 0
  * Locked value: 1
@@ -41,7 +42,9 @@ static inline void _raw_spin_lock(spinlock_t *lock)
 "       bne     1b"
         : "=&r" (tmp)
         : "r" (&lock->lock), "r" (1)
-        : "cc", "memory");
+        : "cc");
+
+        smp_mb();
 }
 
 static inline int _raw_spin_trylock(spinlock_t *lock)
@@ -54,18 +57,25 @@ static inline int _raw_spin_trylock(spinlock_t *lock)
 "       strexeq %0, %2, [%1]"
         : "=&r" (tmp)
         : "r" (&lock->lock), "r" (1)
-        : "cc", "memory");
-
-        return tmp == 0;
+        : "cc");
+
+        if (tmp == 0) {
+                smp_mb();
+                return 1;
+        } else {
+                return 0;
+        }
 }
 
 static inline void _raw_spin_unlock(spinlock_t *lock)
 {
+        smp_mb();
+
         __asm__ __volatile__(
 "       str     %1, [%0]"
         :
         : "r" (&lock->lock), "r" (0)
-        : "cc", "memory");
+        : "cc");
 }
 
 /*
@@ -79,7 +89,8 @@ typedef struct {
 } rwlock_t;
 
 #define RW_LOCK_UNLOCKED        (rwlock_t) { 0 }
-#define rwlock_init(x)          do { *(x) + RW_LOCK_UNLOCKED; } while (0)
+#define rwlock_init(x)          do { *(x) = RW_LOCK_UNLOCKED; } while (0)
+#define rwlock_is_locked(x)     (*((volatile unsigned int *)(x)) != 0)
 
 /*
  * Write locks are easy - we just set bit 31.  When unlocking, we can
@@ -97,16 +108,40 @@ static inline void _raw_write_lock(rwlock_t *rw)
 "       bne     1b"
         : "=&r" (tmp)
         : "r" (&rw->lock), "r" (0x80000000)
-        : "cc", "memory");
+        : "cc");
+
+        smp_mb();
+}
+
+static inline int _raw_write_trylock(rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]"
+        : "=&r" (tmp)
+        : "r" (&rw->lock), "r" (0x80000000)
+        : "cc");
+
+        if (tmp == 0) {
+                smp_mb();
+                return 1;
+        } else {
+                return 0;
+        }
 }
 
 static inline void _raw_write_unlock(rwlock_t *rw)
 {
+        smp_mb();
+
         __asm__ __volatile__(
         "str    %1, [%0]"
         :
         : "r" (&rw->lock), "r" (0)
-        : "cc", "memory");
+        : "cc");
 }
 
 /*
@@ -133,11 +168,17 @@ static inline void _raw_read_lock(rwlock_t *rw)
 "       bmi     1b"
         : "=&r" (tmp), "=&r" (tmp2)
         : "r" (&rw->lock)
-        : "cc", "memory");
+        : "cc");
+
+        smp_mb();
 }
 
 static inline void _raw_read_unlock(rwlock_t *rw)
 {
+        unsigned long tmp, tmp2;
+
+        smp_mb();
+
         __asm__ __volatile__(
 "1:     ldrex   %0, [%2]\n"
 "       sub     %0, %0, #1\n"
@@ -146,24 +187,9 @@ static inline void _raw_read_unlock(rwlock_t *rw)
 "       bne     1b"
         : "=&r" (tmp), "=&r" (tmp2)
         : "r" (&rw->lock)
-        : "cc", "memory");
+        : "cc");
 }
 
 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
 
-static inline int _raw_write_trylock(rwlock_t *rw)
-{
-        unsigned long tmp;
-
-        __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-"       strexeq %0, %2, [%1]"
-        : "=&r" (tmp)
-        : "r" (&rw->lock), "r" (0x80000000)
-        : "cc", "memory");
-
-        return tmp == 0;
-}
-
 #endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-arm/stat.h b/include/asm-arm/stat.h
index ca8e7a8436da..ec4e2c2e3b47 100644
--- a/include/asm-arm/stat.h
+++ b/include/asm-arm/stat.h
@@ -89,6 +89,6 @@ struct stat64 {
         unsigned long   st_ctime_nsec;
 
         unsigned long long      st_ino;
-};
+} __attribute__((packed));
 
 #endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index b13a8da4847b..8efa4ebdcacb 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -85,7 +85,9 @@ struct pt_regs;
 void die(const char *msg, struct pt_regs *regs, int err)
                 __attribute__((noreturn));
 
-void die_if_kernel(const char *str, struct pt_regs *regs, int err);
+struct siginfo;
+void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
+                unsigned long err, unsigned long trap);
 
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                        struct pt_regs *),
@@ -104,6 +106,7 @@ extern void show_pte(struct mm_struct *mm, unsigned long addr);
 extern void __show_regs(struct pt_regs *);
 
 extern int cpu_architecture(void);
+extern void cpu_init(void);
 
 #define set_cr(x)                                       \
         __asm__ __volatile__(                           \
@@ -136,7 +139,12 @@ extern unsigned int user_debug;
 #define vectors_high()  (0)
 #endif
 
+#if __LINUX_ARM_ARCH__ >= 6
+#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                   : : "r" (0) : "memory")
+#else
 #define mb() __asm__ __volatile__ ("" : : : "memory")
+#endif
 #define rmb() mb()
 #define wmb() mb()
 #define read_barrier_depends() do { } while(0)
@@ -144,34 +152,12 @@ extern unsigned int user_debug;
 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
-#ifdef CONFIG_SMP
-/*
- * Define our own context switch locking.  This allows us to enable
- * interrupts over the context switch, otherwise we end up with high
- * interrupt latency.  The real problem area is switch_mm() which may
- * do a full cache flush.
- */
-#define prepare_arch_switch(rq,next)                                    \
-do {                                                                    \
-        spin_lock(&(next)->switch_lock);                                \
-        spin_unlock_irq(&(rq)->lock);                                   \
-} while (0)
-
-#define finish_arch_switch(rq,prev)                                     \
-        spin_unlock(&(prev)->switch_lock)
-
-#define task_running(rq,p)                                              \
-        ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
-#else
 /*
- * Our UP-case is more simple, but we assume knowledge of how
- * spin_unlock_irq() and friends are implemented.  This avoids
- * us needlessly decrementing and incrementing the preempt count.
+ * switch_mm() may do a full cache flush over the context switch,
+ * so enable interrupts over the context switch to avoid high
+ * latency.
  */
-#define prepare_arch_switch(rq,next)    local_irq_enable()
-#define finish_arch_switch(rq,prev)     spin_unlock(&(rq)->lock)
-#define task_running(rq,p)              ((rq)->curr == (p))
-#endif
+#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 
 /*
  * switch_to(prev, next) should switch from task `prev' to `next'
@@ -307,11 +293,10 @@ do {									\
 ({                                      \
         unsigned long flags;            \
         local_save_flags(flags);        \
-        flags & PSR_I_BIT;              \
+        (int)(flags & PSR_I_BIT);       \
 })
 
 #ifdef CONFIG_SMP
-#error SMP not supported
 
 #define smp_mb()                mb()
 #define smp_rmb()               rmb()
@@ -325,6 +310,8 @@ do {									\
 #define smp_wmb()               barrier()
 #define smp_read_barrier_depends()              do { } while(0)
 
+#endif /* CONFIG_SMP */
+
 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 /*
  * On the StrongARM, "swp" is terminally broken since it bypasses the
@@ -337,6 +324,9 @@ do {									\
  *
  * We choose (1) since its the "easiest" to achieve here and is not
  * dependent on the processor type.
+ *
+ * NOTE that this solution won't work on an SMP system, so explcitly
+ * forbid it here.
  */
 #define swp_is_buggy
 #endif
@@ -348,42 +338,73 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 #ifdef swp_is_buggy
         unsigned long flags;
 #endif
+#if __LINUX_ARM_ARCH__ >= 6
+        unsigned int tmp;
+#endif
 
         switch (size) {
-#ifdef swp_is_buggy
-                case 1:
-                        local_irq_save(flags);
-                        ret = *(volatile unsigned char *)ptr;
-                        *(volatile unsigned char *)ptr = x;
-                        local_irq_restore(flags);
-                        break;
-
-                case 4:
-                        local_irq_save(flags);
-                        ret = *(volatile unsigned long *)ptr;
-                        *(volatile unsigned long *)ptr = x;
-                        local_irq_restore(flags);
-                        break;
+#if __LINUX_ARM_ARCH__ >= 6
+        case 1:
+                asm volatile("@ __xchg1\n"
+                "1:     ldrexb  %0, [%3]\n"
+                "       strexb  %1, %2, [%3]\n"
+                "       teq     %1, #0\n"
+                "       bne     1b"
+                        : "=&r" (ret), "=&r" (tmp)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
+        case 4:
+                asm volatile("@ __xchg4\n"
+                "1:     ldrex   %0, [%3]\n"
+                "       strex   %1, %2, [%3]\n"
+                "       teq     %1, #0\n"
+                "       bne     1b"
+                        : "=&r" (ret), "=&r" (tmp)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
+#elif defined(swp_is_buggy)
+#ifdef CONFIG_SMP
+#error SMP is not supported on this platform
+#endif
+        case 1:
+                local_irq_save(flags);
+                ret = *(volatile unsigned char *)ptr;
+                *(volatile unsigned char *)ptr = x;
+                local_irq_restore(flags);
+                break;
+
+        case 4:
+                local_irq_save(flags);
+                ret = *(volatile unsigned long *)ptr;
+                *(volatile unsigned long *)ptr = x;
+                local_irq_restore(flags);
+                break;
 #else
-                case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
-                                        : "=&r" (ret)
-                                        : "r" (x), "r" (ptr)
-                                        : "memory", "cc");
-                        break;
-                case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
-                                        : "=&r" (ret)
-                                        : "r" (x), "r" (ptr)
-                                        : "memory", "cc");
-                        break;
+        case 1:
+                asm volatile("@ __xchg1\n"
+                "       swpb    %0, %1, [%2]"
+                        : "=&r" (ret)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
+        case 4:
+                asm volatile("@ __xchg4\n"
+                "       swp     %0, %1, [%2]"
+                        : "=&r" (ret)
+                        : "r" (x), "r" (ptr)
+                        : "memory", "cc");
+                break;
 #endif
-                default: __bad_xchg(ptr, size), ret = 0;
+        default:
+                __bad_xchg(ptr, size), ret = 0;
+                break;
         }
 
         return ret;
 }
 
-#endif /* CONFIG_SMP */
-
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 66c585c50cf9..8252a4cd860f 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -49,7 +49,7 @@ struct cpu_context_save {
  */
 struct thread_info {
         unsigned long           flags;          /* low level flags */
-        __s32                   preempt_count;  /* 0 => preemptable, <0 => bug */
+        int                     preempt_count;  /* 0 => preemptable, <0 => bug */
         mm_segment_t            addr_limit;     /* address limit */
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8a864b118569..9387a5e1ffe0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb;
 
 #define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
 
-static inline void flush_tlb_all(void)
+static inline void local_flush_tlb_all(void)
 {
         const int zero = 0;
         const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -253,7 +253,7 @@ static inline void flush_tlb_all(void)
                 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
 }
 
-static inline void flush_tlb_mm(struct mm_struct *mm)
+static inline void local_flush_tlb_mm(struct mm_struct *mm)
 {
         const int zero = 0;
         const int asid = ASID(mm);
@@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 }
 
 static inline void
-flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 {
         const int zero = 0;
         const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
 }
 
-static inline void flush_tlb_kernel_page(unsigned long kaddr)
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 {
         const int zero = 0;
         const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd)
 /*
  * Convert calls to our calling convention.
  */
-#define flush_tlb_range(vma,start,end)  __cpu_flush_user_tlb_range(start,end,vma)
-#define flush_tlb_kernel_range(s,e)     __cpu_flush_kern_tlb_range(s,e)
+#define local_flush_tlb_range(vma,start,end)    __cpu_flush_user_tlb_range(start,end,vma)
+#define local_flush_tlb_kernel_range(s,e)       __cpu_flush_kern_tlb_range(s,e)
+
+#ifndef CONFIG_SMP
+#define flush_tlb_all           local_flush_tlb_all
+#define flush_tlb_mm            local_flush_tlb_mm
+#define flush_tlb_page          local_flush_tlb_page
+#define flush_tlb_kernel_page   local_flush_tlb_kernel_page
+#define flush_tlb_range         local_flush_tlb_range
+#define flush_tlb_kernel_range  local_flush_tlb_kernel_range
+#else
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+#endif
 
 /*
  * if PG_dcache_dirty is set for the page, we need to ensure that any
diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
index f4c92e4c8c02..22992ee0627a 100644
--- a/include/asm-arm/types.h
+++ b/include/asm-arm/types.h
@@ -52,8 +52,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/uaccess.h b/include/asm-arm/uaccess.h
index a7c018b8a0d4..a2fdad0138b3 100644
--- a/include/asm-arm/uaccess.h
+++ b/include/asm-arm/uaccess.h
@@ -77,12 +77,6 @@ static inline void set_fs (mm_segment_t fs)
 
 #define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user *addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
 /*
  * Single-value transfer routines.  They automatically use the right
  * size if we just have the right pointer type.  Note that the functions
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index ace27480886e..278de61224d1 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -295,7 +295,7 @@
 #define __NR_fstatfs64                  (__NR_SYSCALL_BASE+267)
 #define __NR_tgkill                     (__NR_SYSCALL_BASE+268)
 #define __NR_utimes                     (__NR_SYSCALL_BASE+269)
-#define __NR_fadvise64_64               (__NR_SYSCALL_BASE+270)
+#define __NR_arm_fadvise64_64           (__NR_SYSCALL_BASE+270)
 #define __NR_pciconfig_iobase           (__NR_SYSCALL_BASE+271)
 #define __NR_pciconfig_read             (__NR_SYSCALL_BASE+272)
 #define __NR_pciconfig_write            (__NR_SYSCALL_BASE+273)
@@ -350,6 +350,11 @@
 #endif
 
 #define __NR_vserver                    (__NR_SYSCALL_BASE+313)
+#define __NR_ioprio_set                 (__NR_SYSCALL_BASE+314)
+#define __NR_ioprio_get                 (__NR_SYSCALL_BASE+315)
+#define __NR_inotify_init               (__NR_SYSCALL_BASE+316)
+#define __NR_inotify_add_watch          (__NR_SYSCALL_BASE+317)
+#define __NR_inotify_rm_watch           (__NR_SYSCALL_BASE+318)
 
 /*
  * The following SWIs are ARM private.
@@ -510,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_SYS_TIME
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
 #define __ARCH_WANT_SYS_GETPGRP
 #define __ARCH_WANT_SYS_LLSEEK
 #define __ARCH_WANT_SYS_NICE
diff --git a/include/asm-arm26/auxvec.h b/include/asm-arm26/auxvec.h
new file mode 100644
index 000000000000..c0536f6b29a7
--- /dev/null
+++ b/include/asm-arm26/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMARM_AUXVEC_H
+#define __ASMARM_AUXVEC_H
+
+#endif
diff --git a/include/asm-arm26/emergency-restart.h b/include/asm-arm26/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-arm26/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-arm26/fcntl.h b/include/asm-arm26/fcntl.h
index 485b6bdf4d7a..d85995e7459e 100644
--- a/include/asm-arm26/fcntl.h
+++ b/include/asm-arm26/fcntl.h
@@ -3,85 +3,11 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
 #define O_LARGEFILE     0400000
-#define O_NOATIME       01000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
+#include <asm-generic/fcntl.h>
 
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif
diff --git a/include/asm-arm26/futex.h b/include/asm-arm26/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-arm26/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-arm26/hdreg.h b/include/asm-arm26/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-arm26/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-arm26/page.h b/include/asm-arm26/page.h
index c334079b082b..d3f23ac4d468 100644
--- a/include/asm-arm26/page.h
+++ b/include/asm-arm26/page.h
@@ -89,20 +89,6 @@ typedef unsigned long pgprot_t;
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #include <asm/memory.h>
 
 #endif /* !__ASSEMBLY__ */
@@ -112,4 +98,6 @@ static inline int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif
diff --git a/include/asm-arm26/serial.h b/include/asm-arm26/serial.h
index 21e1df31f086..5fc747d1b501 100644
--- a/include/asm-arm26/serial.h
+++ b/include/asm-arm26/serial.h
@@ -30,34 +30,16 @@
 #if defined(CONFIG_ARCH_A5K)
      /* UART CLK        PORT  IRQ     FLAGS        */
 
-#define STD_SERIAL_PORT_DEFNS                                           \
+#define SERIAL_PORT_DFNS                                                \
         { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS },     /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS },     /* ttyS1 */
 
 #else
 
-#define STD_SERIAL_PORT_DEFNS                                           \
+#define SERIAL_PORT_DFNS                                                \
         { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS0 */     \
         { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS1 */
 
 #endif
 
-#define EXTRA_SERIAL_PORT_DEFNS \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS2 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS3 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS12 */    \
-        { 0, BASE_BAUD, 0    ,  0, STD_COM_FLAGS },     /* ttyS13 */
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS
-
 #endif
diff --git a/include/asm-arm26/socket.h b/include/asm-arm26/socket.h
index 46d20585d951..3c51da6438c9 100644
--- a/include/asm-arm26/socket.h
+++ b/include/asm-arm26/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-arm26/thread_info.h b/include/asm-arm26/thread_info.h
index 50f41b50268a..aff3e5699c64 100644
--- a/include/asm-arm26/thread_info.h
+++ b/include/asm-arm26/thread_info.h
@@ -44,7 +44,7 @@ struct cpu_context_save {
  */
 struct thread_info {
         unsigned long           flags;          /* low level flags */
-        __s32                   preempt_count;  /* 0 => preemptable, <0 => bug */
+        int                     preempt_count;  /* 0 => preemptable, <0 => bug */
         mm_segment_t            addr_limit;     /* address limit */
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
diff --git a/include/asm-arm26/types.h b/include/asm-arm26/types.h
index 56cbe573a234..81bd357ada02 100644
--- a/include/asm-arm26/types.h
+++ b/include/asm-arm26/types.h
@@ -52,8 +52,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm26/uaccess.h b/include/asm-arm26/uaccess.h
index ab9ce38c6aec..3f2dd1093e58 100644
--- a/include/asm-arm26/uaccess.h
+++ b/include/asm-arm26/uaccess.h
@@ -40,12 +40,6 @@ extern int fixup_exception(struct pt_regs *regs);
 
 #define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
 /*
  * Single-value transfer routines.  They automatically use the right
  * size if we just have the right pointer type.  Note that the functions
diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h
new file mode 100644
index 000000000000..6ef5e7d09024
--- /dev/null
+++ b/include/asm-cris/arch-v10/atomic.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_CRIS_ARCH_ATOMIC__
+#define __ASM_CRIS_ARCH_ATOMIC__
+
+#define cris_atomic_save(addr, flags) local_irq_save(flags);
+#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
+
+#endif
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h
index 21b7ae8c9bb3..b73f5396e5a6 100644
--- a/include/asm-cris/arch-v10/bitops.h
+++ b/include/asm-cris/arch-v10/bitops.h
@@ -51,7 +51,7 @@ extern inline unsigned long ffz(unsigned long w)
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
-extern __inline__ unsigned long __ffs(unsigned long word)
+extern inline unsigned long __ffs(unsigned long word)
 {
         return cris_swapnwbrlz(~word);
 }
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h
index 9e078b9bc934..ecb9dba6fa4f 100644
--- a/include/asm-cris/arch-v10/dma.h
+++ b/include/asm-cris/arch-v10/dma.h
@@ -44,3 +44,31 @@
 #define USB_RX_DMA_NBR 9
 
 #endif
+
+enum dma_owner
+{
+  dma_eth,
+  dma_ser0,
+  dma_ser1, /* Async and sync */
+  dma_ser2,
+  dma_ser3, /* Async and sync */
+  dma_ata,
+  dma_par0,
+  dma_par1,
+  dma_ext0,
+  dma_ext1,
+  dma_int6,
+  dma_int7,
+  dma_usb,
+  dma_scsi0,
+  dma_scsi1
+};
+
+/* Masks used by cris_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR    (1<<0)
+#define DMA_PANIC_ON_ERROR     ((1<<1)|DMA_VERBOSE_ON_ERROR)
+
+int cris_request_dma(unsigned int dmanr, const char * device_id,
+                     unsigned options, enum dma_owner owner);
+
+void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h
index 2a2201ca538e..1c38ee728b17 100644
--- a/include/asm-cris/arch-v10/elf.h
+++ b/include/asm-cris/arch-v10/elf.h
@@ -1,6 +1,16 @@
 #ifndef __ASMCRIS_ARCH_ELF_H
 #define __ASMCRIS_ARCH_ELF_H
 
+#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)                       \
+ ((x)->e_machine == EM_CRIS                     \
+  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10      \
+      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
+
 /*
  * ELF register definitions..
  */
diff --git a/include/asm-cris/arch-v10/ide.h b/include/asm-cris/arch-v10/ide.h
new file mode 100644
index 000000000000..8cf2d7cb22ac
--- /dev/null
+++ b/include/asm-cris/arch-v10/ide.h
@@ -0,0 +1,99 @@
+/*
+ *  linux/include/asm-cris/ide.h
+ *
+ *  Copyright (C) 2000, 2001, 2002  Axis Communications AB
+ *
+ *  Authors:    Bjorn Wesen
+ *
+ */
+
+/*
+ *  This file contains the ETRAX 100LX specific IDE code.
+ */
+
+#ifndef __ASMCRIS_IDE_H
+#define __ASMCRIS_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm-generic/ide_iops.h>
+
+
+/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */
+
+#define MAX_HWIFS       4
+
+extern __inline__ int ide_default_irq(unsigned long base)
+{
+        /* all IDE busses share the same IRQ, number 4.
+         * this has the side-effect that ide-probe.c will cluster our 4 interfaces
+         * together in a hwgroup, and will serialize accesses. this is good, because
+         * we can't access more than one interface at the same time on ETRAX100.
+         */
+        return 4;
+}
+
+extern __inline__ unsigned long ide_default_io_base(int index)
+{
+        /* we have no real I/O base address per interface, since all go through the
+         * same register. but in a bitfield in that register, we have the i/f number.
+         * so we can use the io_base to remember that bitfield.
+         */
+        static const unsigned long io_bases[MAX_HWIFS] = {
+                IO_FIELD(R_ATA_CTRL_DATA, sel, 0),
+                IO_FIELD(R_ATA_CTRL_DATA, sel, 1),
+                IO_FIELD(R_ATA_CTRL_DATA, sel, 2),
+                IO_FIELD(R_ATA_CTRL_DATA, sel, 3)
+        };
+        return io_bases[index];
+}
+
+/* this is called once for each interface, to setup the port addresses. data_port is the result
+ * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us.
+ */
+
+extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
+{
+        int i;
+
+        /* fill in ports for ATA addresses 0 to 7 */
+
+        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+                hw->io_ports[i] = data_port |
+                        IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
+                        IO_STATE(R_ATA_CTRL_DATA, cs0, active);
+        }
+
+        /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
+
+        hw->io_ports[IDE_CONTROL_OFFSET] = data_port |
+                        IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
+                        IO_STATE(R_ATA_CTRL_DATA, cs1, active);
+
+        /* whats this for ? */
+
+        hw->io_ports[IDE_IRQ_OFFSET] = 0;
+}
+
+extern __inline__ void ide_init_default_hwifs(void)
+{
+        hw_regs_t hw;
+        int index;
+
+        for(index = 0; index < MAX_HWIFS; index++) {
+                ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
+                hw.irq = ide_default_irq(ide_default_io_base(index));
+                ide_register_hw(&hw, NULL);
+        }
+}
+
+/* some configuration options we don't need */
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h
index 0bc38a0313c1..dd39198ec67d 100644
--- a/include/asm-cris/arch-v10/io.h
+++ b/include/asm-cris/arch-v10/io.h
@@ -6,6 +6,7 @@
 
 /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
 
+extern unsigned long gen_config_ii_shadow;
 extern unsigned long port_g_data_shadow;
 extern unsigned char port_pa_dir_shadow;
 extern unsigned char port_pa_data_shadow;
diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h
new file mode 100644
index 000000000000..d92500080883
--- /dev/null
+++ b/include/asm-cris/arch-v10/io_interface_mux.h
@@ -0,0 +1,75 @@
+/* IO interface mux allocator for ETRAX100LX.
+ * Copyright 2004, Axis Communications AB
+ * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
+ */
+
+
+#ifndef _IO_INTERFACE_MUX_H
+#define _IO_INTERFACE_MUX_H
+
+
+/* C.f. ETRAX100LX Designer's Reference 20.9 */
+
+/* The order in enum must match the order of interfaces[] in
+ * io_interface_mux.c */
+enum cris_io_interface {
+        /* Begin Non-multiplexed interfaces */
+        if_eth = 0,
+        if_serial_0,
+        /* End Non-multiplexed interfaces */
+        if_serial_1,
+        if_serial_2,
+        if_serial_3,
+        if_sync_serial_1,
+        if_sync_serial_3,
+        if_shared_ram,
+        if_shared_ram_w,
+        if_par_0,
+        if_par_1,
+        if_par_w,
+        if_scsi8_0,
+        if_scsi8_1,
+        if_scsi_w,
+        if_ata,
+        if_csp,
+        if_i2c,
+        if_usb_1,
+        if_usb_2,
+        /* GPIO pins */
+        if_gpio_grp_a,
+        if_gpio_grp_b,
+        if_gpio_grp_c,
+        if_gpio_grp_d,
+        if_gpio_grp_e,
+        if_gpio_grp_f,
+        if_max_interfaces,
+        if_unclaimed
+};
+
+int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
+
+void cris_free_io_interface(enum cris_io_interface ioif);
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
+                                    const char port,
+                                    const unsigned start_bit,
+                                    const unsigned stop_bit);
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_free_pins(const enum cris_io_interface ioif,
+                                const char port,
+                                const unsigned start_bit,
+                                const unsigned stop_bit);
+
+int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
+                                                      const unsigned int gpio_out_available,
+                                                      const unsigned char pa_available,
+                                                      const unsigned char pb_available));
+
+void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
+                                                     const unsigned int gpio_out_available,
+                                                     const unsigned char pa_available,
+                                                     const unsigned char pb_available));
+
+#endif /* _IO_INTERFACE_MUX_H */
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h
index a2a6e1533ea0..4fa8945b0263 100644
--- a/include/asm-cris/arch-v10/irq.h
+++ b/include/asm-cris/arch-v10/irq.h
@@ -74,12 +74,9 @@ struct etrax_interrupt_vector {
 };
 
 extern struct etrax_interrupt_vector *etrax_irv;
-void set_int_vector(int n, irqvectptr addr, irqvectptr saddr);
+void set_int_vector(int n, irqvectptr addr);
 void set_break_vector(int n, irqvectptr addr);
 
-#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
-#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
-
 #define __STR(x) #x
 #define STR(x) __STR(x)
  
@@ -121,26 +118,17 @@ void set_break_vector(int n, irqvectptr addr);
 
 #define BUILD_IRQ(nr,mask) \
 void IRQ_NAME(nr); \
-void sIRQ_NAME(nr); \
-void BAD_IRQ_NAME(nr); \
 __asm__ ( \
           ".text\n\t" \
           "IRQ" #nr "_interrupt:\n\t" \
           SAVE_ALL \
-          "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
           BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
           "moveq "#nr",$r10\n\t" \
           "move.d $sp,$r11\n\t" \
           "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
           UNBLOCK_IRQ(mask) \
           "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-          "jump ret_from_intr\n\t" \
-          "bad_IRQ" #nr "_interrupt:\n\t" \
-          "push $r0\n\t" \
-          BLOCK_IRQ(mask,nr) \
-          "pop $r0\n\t" \
-          "reti\n\t" \
-          "nop\n");
+          "jump ret_from_intr\n\t");
 
 /* This is subtle. The timer interrupt is crucial and it should not be disabled for 
  * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
@@ -159,23 +147,14 @@ __asm__ ( \
 
 #define BUILD_TIMER_IRQ(nr,mask) \
 void IRQ_NAME(nr); \
-void sIRQ_NAME(nr); \
-void BAD_IRQ_NAME(nr); \
 __asm__ ( \
           ".text\n\t" \
           "IRQ" #nr "_interrupt:\n\t" \
           SAVE_ALL \
-          "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
           "moveq "#nr",$r10\n\t" \
           "move.d $sp,$r11\n\t" \
           "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
           "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-          "jump ret_from_intr\n\t" \
-          "bad_IRQ" #nr "_interrupt:\n\t" \
-          "push $r0\n\t" \
-          BLOCK_IRQ(mask,nr) \
-          "pop $r0\n\t" \
-          "reti\n\t" \
-          "nop\n");
+          "jump ret_from_intr\n\t");
 
 #endif
diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h
new file mode 100644
index 000000000000..13f3b971407f
--- /dev/null
+++ b/include/asm-cris/arch-v10/memmap.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h
index d18aa00e50bc..df84f1716e6b 100644
--- a/include/asm-cris/arch-v10/mmu.h
+++ b/include/asm-cris/arch-v10/mmu.h
@@ -7,7 +7,10 @@
 
 /* type used in struct mm to couple an MMU context to an active mm */
 
-typedef unsigned int mm_context_t;
+typedef struct
+{
+  unsigned int page_id;
+} mm_context_t;
 
 /* kernel memory segments */
 
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h
index fcbd77eab281..675b51d85639 100644
--- a/include/asm-cris/arch-v10/offset.h
+++ b/include/asm-cris/arch-v10/offset.h
@@ -25,7 +25,7 @@
 #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
 #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
 
-#define TASK_pid 133 /* offsetof(struct task_struct, pid) */
+#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
 
 #define LCLONE_VM 256 /* CLONE_VM */
 #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h
index 9355d8675a58..e23df8dc96e8 100644
--- a/include/asm-cris/arch-v10/processor.h
+++ b/include/asm-cris/arch-v10/processor.h
@@ -59,4 +59,12 @@ struct thread_struct {
         wrusp(usp);           \
 } while(0)
 
+/* Called when handling a kernel bus fault fixup.
+ *
+ * After a fixup we do not want to return by restoring the CPU-state
+ * anymore, so switch frame-types (see ptrace.h)
+ */
+#define arch_fixup(regs) \
+   regs->frametype = CRIS_FRAME_NORMAL;
+
 #endif
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h
index 781ca30229a8..6cc35642b8ab 100644
--- a/include/asm-cris/arch-v10/system.h
+++ b/include/asm-cris/arch-v10/system.h
@@ -11,6 +11,8 @@ extern inline unsigned long rdvr(void) {
         return vr;
 }
 
+#define cris_machine_name "cris"
+
 /* read/write the user-mode stackpointer */
 
 extern inline unsigned long rdusp(void) {
diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h
new file mode 100644
index 000000000000..dba3c285cacd
--- /dev/null
+++ b/include/asm-cris/arch-v32/arbiter.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_CRIS_ARCH_ARBITER_H
+#define _ASM_CRIS_ARCH_ARBITER_H
+
+#define EXT_REGION 0
+#define INT_REGION 1
+
+typedef void (watch_callback)(void);
+
+enum
+{
+  arbiter_all_dmas = 0x3ff,
+  arbiter_cpu = 0xc00,
+  arbiter_all_clients = 0x3fff
+};
+
+enum
+{
+  arbiter_all_read = 0x55,
+  arbiter_all_write = 0xaa,
+  arbiter_all_accesses = 0xff
+};
+
+int crisv32_arbiter_allocate_bandwith(int client, int region,
+                                      unsigned long bandwidth);
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+                          unsigned long clients, unsigned long accesses,
+                          watch_callback* cb);
+int crisv32_arbiter_unwatch(int id);
+
+#endif
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h
new file mode 100644
index 000000000000..bbfb7a5ae315
--- /dev/null
+++ b/include/asm-cris/arch-v32/atomic.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_CRIS_ARCH_ATOMIC__
+#define __ASM_CRIS_ARCH_ATOMIC__
+
+#include <asm/system.h>
+
+extern void cris_spin_unlock(void *l, int val);
+extern void cris_spin_lock(void *l);
+extern int cris_spin_trylock(void* l);
+
+#ifndef CONFIG_SMP
+#define cris_atomic_save(addr, flags) local_irq_save(flags);
+#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
+#else
+
+extern spinlock_t cris_atomic_locks[];
+#define LOCK_COUNT 128
+#define HASH_ADDR(a) (((int)a) & 127)
+
+#define cris_atomic_save(addr, flags) \
+  local_irq_save(flags); \
+  cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock);
+
+#define cris_atomic_restore(addr, flags) \
+  { \
+    spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
+    __asm__ volatile ("move.d %1,%0" \
+                          : "=m" (lock->lock) \
+                          : "r" (1) \
+                          : "memory"); \
+    local_irq_restore(flags); \
+  }
+
+#endif
+
+#endif
+
diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h
new file mode 100644
index 000000000000..e40a58d3b862
--- /dev/null
+++ b/include/asm-cris/arch-v32/bitops.h
@@ -0,0 +1,64 @@
+#ifndef _ASM_CRIS_ARCH_BITOPS_H
+#define _ASM_CRIS_ARCH_BITOPS_H
+
+/*
+ * Helper functions for the core of the ff[sz] functions. They compute the
+ * number of leading zeroes of a bits-in-byte, byte-in-word and
+ * word-in-dword-swapped number. They differ in that the first function also
+ * inverts all bits in the input.
+ */
+
+extern inline unsigned long
+cris_swapnwbrlz(unsigned long w)
+{
+        unsigned long res;
+
+        __asm__ __volatile__ ("swapnwbr %0\n\t"
+                              "lz %0,%0"
+                              : "=r" (res) : "0" (w));
+
+        return res;
+}
+
+extern inline unsigned long
+cris_swapwbrlz(unsigned long w)
+{
+        unsigned long res;
+
+        __asm__ __volatile__ ("swapwbr %0\n\t"
+                              "lz %0,%0"
+                              : "=r" (res) : "0" (w));
+
+        return res;
+}
+
+/*
+ * Find First Zero in word. Undefined if no zero exist, so the caller should
+ * check against ~0 first.
+ */
+extern inline unsigned long
+ffz(unsigned long w)
+{
+        return cris_swapnwbrlz(w);
+}
+
+/*
+ * Find First Set bit in word. Undefined if no 1 exist, so the caller
+ * should check against 0 first.
+ */
+extern inline unsigned long
+__ffs(unsigned long w)
+{
+        return cris_swapnwbrlz(~w);
+}
+
+/*
+ * Find First Bit that is set.
+ */
+extern inline unsigned long
+kernel_ffs(unsigned long w)
+{
+        return w ? cris_swapwbrlz (w) + 1 : 0;
+}
+
+#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h
new file mode 100644
index 000000000000..74846ee6cf99
--- /dev/null
+++ b/include/asm-cris/arch-v32/byteorder.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_CRIS_ARCH_BYTEORDER_H
+#define _ASM_CRIS_ARCH_BYTEORDER_H
+
+#include <asm/types.h>
+
+extern __inline__ __const__ __u32
+___arch__swab32(__u32 x)
+{
+        __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
+        return (x);
+}
+
+extern __inline__ __const__ __u16
+___arch__swab16(__u16 x)
+{
+        __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
+        return (x);
+}
+
+#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
new file mode 100644
index 000000000000..4fed8d62ccc8
--- /dev/null
+++ b/include/asm-cris/arch-v32/cache.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_ARCH_CACHE_H
+#define _ASM_CRIS_ARCH_CACHE_H
+
+/* A cache-line is 32 bytes. */
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_SHIFT_MAX 5
+
+#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h
new file mode 100644
index 000000000000..a1d6b2a6cc44
--- /dev/null
+++ b/include/asm-cris/arch-v32/checksum.h
@@ -0,0 +1,29 @@
+#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
+#define _ASM_CRIS_ARCH_CHECKSUM_H
+
+/*
+ * Check values used in TCP/UDP headers.
+ *
+ * The gain of doing this in assembler instead of C, is that C doesn't
+ * generate carry-additions for the 32-bit components of the
+ * checksum. Which means it would be necessary to split all those into
+ * 16-bit components and then add.
+ */
+extern inline unsigned int
+csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr,
+                   unsigned short len, unsigned short proto, unsigned int sum)
+{
+        int res;
+
+        __asm__ __volatile__ ("add.d %2, %0\n\t"
+                              "addc %3, %0\n\t"
+                              "addc %4, %0\n\t"
+                              "addc 0, %0\n\t"
+                              : "=r" (res)
+                              : "0" (sum), "r" (daddr), "r" (saddr), \
+                              "r" ((ntohs(len) << 16) + (proto << 8)));
+
+        return res;
+}
+
+#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h
new file mode 100644
index 000000000000..dfa1f66fb987
--- /dev/null
+++ b/include/asm-cris/arch-v32/cryptocop.h
@@ -0,0 +1,272 @@
+/*
+ * The device /dev/cryptocop is accessible using this driver using
+ * CRYPTOCOP_MAJOR (254) and minor number 0.
+ */
+
+#ifndef CRYPTOCOP_H
+#define CRYPTOCOP_H
+
+#include <linux/uio.h>
+
+
+#define CRYPTOCOP_SESSION_ID_NONE (0)
+
+typedef unsigned long long int cryptocop_session_id;
+
+/* cryptocop ioctls */
+#define ETRAXCRYPTOCOP_IOCTYPE         (250)
+
+#define CRYPTOCOP_IO_CREATE_SESSION    _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
+#define CRYPTOCOP_IO_CLOSE_SESSION     _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
+#define CRYPTOCOP_IO_PROCESS_OP        _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
+#define CRYPTOCOP_IO_MAXNR             (3)
+
+typedef enum {
+        cryptocop_cipher_des = 0,
+        cryptocop_cipher_3des = 1,
+        cryptocop_cipher_aes = 2,
+        cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
+        cryptocop_cipher_none
+} cryptocop_cipher_type;
+
+typedef enum {
+        cryptocop_digest_sha1 = 0,
+        cryptocop_digest_md5 = 1,
+        cryptocop_digest_none
+} cryptocop_digest_type;
+
+typedef enum {
+        cryptocop_csum_le = 0,
+        cryptocop_csum_be = 1,
+        cryptocop_csum_none
+} cryptocop_csum_type;
+
+typedef enum {
+        cryptocop_cipher_mode_ecb = 0,
+        cryptocop_cipher_mode_cbc,
+        cryptocop_cipher_mode_none
+} cryptocop_cipher_mode;
+
+typedef enum {
+        cryptocop_3des_eee = 0,
+        cryptocop_3des_eed = 1,
+        cryptocop_3des_ede = 2,
+        cryptocop_3des_edd = 3,
+        cryptocop_3des_dee = 4,
+        cryptocop_3des_ded = 5,
+        cryptocop_3des_dde = 6,
+        cryptocop_3des_ddd = 7
+} cryptocop_3des_mode;
+
+/* Usermode accessible (ioctl) operations. */
+struct strcop_session_op{
+        cryptocop_session_id    ses_id;
+
+        cryptocop_cipher_type   cipher; /* AES, DES, 3DES, m2m, none */
+
+        cryptocop_cipher_mode   cmode; /* ECB, CBC, none */
+        cryptocop_3des_mode     des3_mode;
+
+        cryptocop_digest_type   digest; /* MD5, SHA1, none */
+
+        cryptocop_csum_type     csum;   /* BE, LE, none */
+
+        unsigned char           *key;
+        size_t                  keylen;
+};
+
+#define CRYPTOCOP_CSUM_LENGTH         (2)
+#define CRYPTOCOP_MAX_DIGEST_LENGTH   (20)  /* SHA-1 20, MD5 16 */
+#define CRYPTOCOP_MAX_IV_LENGTH       (16)  /* (3)DES==8, AES == 16 */
+#define CRYPTOCOP_MAX_KEY_LENGTH      (32)
+
+struct strcop_crypto_op{
+        cryptocop_session_id ses_id;
+
+        /* Indata. */
+        unsigned char            *indata;
+        size_t                   inlen; /* Total indata length. */
+
+        /* Cipher configuration. */
+        unsigned char            do_cipher:1;
+        unsigned char            decrypt:1; /* 1 == decrypt, 0 == encrypt */
+        unsigned char            cipher_explicit:1;
+        size_t                   cipher_start;
+        size_t                   cipher_len;
+        /* cipher_iv is used if do_cipher and cipher_explicit and the cipher
+           mode is CBC.  The length is controlled by the type of cipher,
+           e.g. DES/3DES 8 octets and AES 16 octets. */
+        unsigned char            cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
+        /* Outdata. */
+        unsigned char            *cipher_outdata;
+        size_t                   cipher_outlen;
+
+        /* digest configuration. */
+        unsigned char            do_digest:1;
+        size_t                   digest_start;
+        size_t                   digest_len;
+        /* Outdata.  The actual length is determined by the type of the digest. */
+        unsigned char            digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
+
+        /* Checksum configuration. */
+        unsigned char            do_csum:1;
+        size_t                   csum_start;
+        size_t                   csum_len;
+        /* Outdata. */
+        unsigned char            csum[CRYPTOCOP_CSUM_LENGTH];
+};
+
+
+
+#ifdef __KERNEL__
+
+/********** The API to use from inside the kernel. ************/
+
+#include <asm/arch/hwregs/dma.h>
+
+typedef enum {
+        cryptocop_alg_csum = 0,
+        cryptocop_alg_mem2mem,
+        cryptocop_alg_md5,
+        cryptocop_alg_sha1,
+        cryptocop_alg_des,
+        cryptocop_alg_3des,
+        cryptocop_alg_aes,
+        cryptocop_no_alg,
+} cryptocop_algorithm;
+
+typedef u8 cryptocop_tfrm_id;
+
+
+struct cryptocop_operation;
+
+typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
+
+struct cryptocop_transform_init {
+        cryptocop_algorithm    alg;
+        /* Keydata for ciphers. */
+        unsigned char          key[CRYPTOCOP_MAX_KEY_LENGTH];
+        unsigned int           keylen;
+        cryptocop_cipher_mode  cipher_mode;
+        cryptocop_3des_mode    tdes_mode;
+        cryptocop_csum_type    csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
+
+        cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
+        struct cryptocop_transform_init *next;
+};
+
+
+typedef enum {
+        cryptocop_source_dma = 0,
+        cryptocop_source_des,
+        cryptocop_source_3des,
+        cryptocop_source_aes,
+        cryptocop_source_md5,
+        cryptocop_source_sha1,
+        cryptocop_source_csum,
+        cryptocop_source_none,
+} cryptocop_source;
+
+
+struct cryptocop_desc_cfg {
+        cryptocop_tfrm_id tid;
+        cryptocop_source src;
+        unsigned int last:1; /* Last use of this transform in the operation.  Will push outdata when encountered. */
+        struct cryptocop_desc_cfg *next;
+};
+
+struct cryptocop_desc {
+        size_t length;
+        struct cryptocop_desc_cfg *cfg;
+        struct cryptocop_desc *next;
+};
+
+
+/* Flags for cryptocop_tfrm_cfg */
+#define CRYPTOCOP_NO_FLAG     (0x00)
+#define CRYPTOCOP_ENCRYPT     (0x01)
+#define CRYPTOCOP_DECRYPT     (0x02)
+#define CRYPTOCOP_EXPLICIT_IV (0x04)
+
+struct cryptocop_tfrm_cfg {
+        cryptocop_tfrm_id tid;
+
+        unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
+
+        /* CBC initialisation vector for cihers. */
+        u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
+
+        /* The position in output where to write the transform output.  The order
+           in which the driver writes the output is unspecified, hence if several
+           transforms write on the same positions in the output the result is
+           unspecified. */
+        size_t inject_ix;
+
+        struct cryptocop_tfrm_cfg *next;
+};
+
+
+
+struct cryptocop_dma_list_operation{
+        /* The consumer can provide DMA lists to send to the co-processor.  'use_dmalists' in
+           struct cryptocop_operation must be set for the driver to use them.  outlist,
+           out_data_buf, inlist and in_data_buf must all be physical addresses since they will
+           be loaded to DMA . */
+        dma_descr_data *outlist; /* Out from memory to the co-processor. */
+        char           *out_data_buf;
+        dma_descr_data *inlist; /* In from the co-processor to memory. */
+        char           *in_data_buf;
+
+        cryptocop_3des_mode tdes_mode;
+        cryptocop_csum_type csum_mode;
+};
+
+
+struct cryptocop_tfrm_operation{
+        /* Operation configuration, if not 'use_dmalists' is set. */
+        struct cryptocop_tfrm_cfg *tfrm_cfg;
+        struct cryptocop_desc *desc;
+
+        struct iovec *indata;
+        size_t incount;
+        size_t inlen; /* Total inlength. */
+
+        struct iovec *outdata;
+        size_t outcount;
+        size_t outlen; /* Total outlength. */
+};
+
+
+struct cryptocop_operation {
+        cryptocop_callback *cb;
+        void *cb_data;
+
+        cryptocop_session_id sid;
+
+        /* The status of the operation when returned to consumer. */
+        int operation_status; /* 0, -EAGAIN */
+
+        /* Flags */
+        unsigned int use_dmalists:1;  /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
+        unsigned int in_interrupt:1;  /* Set if inserting job from interrupt context. */
+        unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
+
+        union{
+                struct cryptocop_dma_list_operation list_op;
+                struct cryptocop_tfrm_operation tfrm_op;
+        };
+};
+
+
+int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
+int cryptocop_free_session(cryptocop_session_id sid);
+
+int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
+
+int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
+
+int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
+
+#endif /* __KERNEL__ */
+
+#endif /* CRYPTOCOP_H */
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h
new file mode 100644
index 000000000000..f36f7f760e89
--- /dev/null
+++ b/include/asm-cris/arch-v32/delay.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_CRIS_ARCH_DELAY_H
+#define _ASM_CRIS_ARCH_DELAY_H
+
+extern __inline__ void
+__delay(int loops)
+{
+        __asm__ __volatile__ (
+                "move.d %0, $r9\n\t"
+                "beq 2f\n\t"
+                "subq 1, $r9\n\t"
+                "1:\n\t"
+                "bne 1b\n\t"
+                "subq 1, $r9\n"
+                "2:"
+                : : "g" (loops) : "r9");
+}
+
+#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h
new file mode 100644
index 000000000000..3674081389fd
--- /dev/null
+++ b/include/asm-cris/arch-v32/dma.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS        10
+
+#define NETWORK_ETH0_TX_DMA_NBR 0       /* Ethernet 0 out. */
+#define NETWORK_ETH0 RX_DMA_NBR 1       /* Ethernet 0 in. */
+
+#define IO_PROC_DMA0_TX_DMA_NBR 2       /* IO processor DMA0 out. */
+#define IO_PROC_DMA0_RX_DMA_NBR 3       /* IO processor DMA0 in. */
+
+#define ATA_TX_DMA_NBR 2                /* ATA interface out. */
+#define ATA_RX_DMA_NBR 3                /* ATA interface in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 2         /* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 3         /* Asynchronous serial port 2 in. */
+
+#define IO_PROC_DMA1_TX_DMA_NBR 4       /* IO processor DMA1 out. */
+#define IO_PROC_DMA1_RX_DMA_NBR 5       /* IO processor DMA1 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4         /* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5         /* Asynchronous serial port 1 in. */
+
+#define SYNC_SER0_TX_DMA_NBR 4          /* Synchronous serial port 0 out. */
+#define SYNC_SER0_RX_DMA_NBR 5          /* Synchronous serial port 0 in. */
+
+#define EXTDMA0_TX_DMA_NBR 6            /* External DMA 0 out. */
+#define EXTDMA1_RX_DMA_NBR 7            /* External DMA 1 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 6         /* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 7         /* Asynchronous serial port 0 in. */
+
+#define SYNC_SER1_TX_DMA_NBR 6          /* Synchronous serial port 1 out. */
+#define SYNC_SER1_RX_DMA_NBR 7          /* Synchronous serial port 1 in. */
+
+#define NETWORK_ETH1_TX_DMA_NBR 6       /* Ethernet 1 out. */
+#define NETWORK_ETH1_RX_DMA_NBR 7       /* Ethernet 1 in. */
+
+#define EXTDMA2_TX_DMA_NBR 8            /* External DMA 2 out. */
+#define EXTDMA3_RX_DMA_NBR 9            /* External DMA 3 in. */
+
+#define STRCOP_TX_DMA_NBR 8             /* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 9             /* Stream co-processor in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 8         /* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 9         /* Asynchronous serial port 3 in. */
+
+enum dma_owner
+{
+  dma_eth0,
+  dma_eth1,
+  dma_iop0,
+  dma_iop1,
+  dma_ser0,
+  dma_ser1,
+  dma_ser2,
+  dma_ser3,
+  dma_sser0,
+  dma_sser1,
+  dma_ata,
+  dma_strp,
+  dma_ext0,
+  dma_ext1,
+  dma_ext2,
+  dma_ext3
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char * device_id,
+                        unsigned options, unsigned bandwidth, enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h
new file mode 100644
index 000000000000..1324e505a4d8
--- /dev/null
+++ b/include/asm-cris/arch-v32/elf.h
@@ -0,0 +1,73 @@
+#ifndef _ASM_CRIS_ELF_H
+#define _ASM_CRIS_ELF_H
+
+#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)                       \
+ ((x)->e_machine == EM_CRIS                     \
+  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32     \
+      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
+
+/* CRISv32 ELF register definitions. */
+
+#include <asm/ptrace.h>
+
+/* Explicitly zero out registers to increase determinism. */
+#define ELF_PLAT_INIT(_r, load_addr)    do { \
+        (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
+        (_r)->r9 = 0;  (_r)->r8 = 0;  (_r)->r7 = 0;  (_r)->r6 = 0;  \
+        (_r)->r5 = 0;  (_r)->r4 = 0;  (_r)->r3 = 0;  (_r)->r2 = 0;  \
+        (_r)->r1 = 0;  (_r)->r0 = 0;  (_r)->mof = 0; (_r)->srp = 0; \
+        (_r)->acr = 0; \
+} while (0)
+
+/*
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically.
+ */
+#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack)     (!(have_pt_gnu_stack))
+
+/*
+ * This is basically a pt_regs with the additional definition
+ * of the stack pointer since it's needed in a core dump.
+ * pr_regs is a elf_gregset_t and should be filled according
+ * to the layout of user_regs_struct.
+ */
+#define ELF_CORE_COPY_REGS(pr_reg, regs)                   \
+        pr_reg[0] = regs->r0;                              \
+        pr_reg[1] = regs->r1;                              \
+        pr_reg[2] = regs->r2;                              \
+        pr_reg[3] = regs->r3;                              \
+        pr_reg[4] = regs->r4;                              \
+        pr_reg[5] = regs->r5;                              \
+        pr_reg[6] = regs->r6;                              \
+        pr_reg[7] = regs->r7;                              \
+        pr_reg[8] = regs->r8;                              \
+        pr_reg[9] = regs->r9;                              \
+        pr_reg[10] = regs->r10;                            \
+        pr_reg[11] = regs->r11;                            \
+        pr_reg[12] = regs->r12;                            \
+        pr_reg[13] = regs->r13;                            \
+        pr_reg[14] = rdusp();               /* SP */       \
+        pr_reg[15] = regs->acr;             /* ACR */      \
+        pr_reg[16] = 0;                     /* BZ */       \
+        pr_reg[17] = rdvr();                /* VR */       \
+        pr_reg[18] = 0;                     /* PID */      \
+        pr_reg[19] = regs->srs;             /* SRS */      \
+        pr_reg[20] = 0;                     /* WZ */       \
+        pr_reg[21] = regs->exs;             /* EXS */      \
+        pr_reg[22] = regs->eda;             /* EDA */      \
+        pr_reg[23] = regs->mof;             /* MOF */      \
+        pr_reg[24] = 0;                     /* DZ */       \
+        pr_reg[25] = 0;                     /* EBP */      \
+        pr_reg[26] = regs->erp;             /* ERP */      \
+        pr_reg[27] = regs->srp;             /* SRP */      \
+        pr_reg[28] = 0;                     /* NRP */      \
+        pr_reg[29] = regs->ccs;             /* CCS */      \
+        pr_reg[30] = rdusp();               /* USP */      \
+        pr_reg[31] = regs->spc;             /* SPC */      \
+
+#endif /* _ASM_CRIS_ELF_H */
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile
new file mode 100644
index 000000000000..c9160f9949a9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/Makefile
@@ -0,0 +1,187 @@
+# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $
+# Makefile to generate or copy the latest register definitions
+# and related datastructures and helpermacros.
+# The offical place for these files is at:
+RELEASE ?= r1_alfa5
+OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
+
+# which is updated on each new release.
+INCL_ASMFILES   =
+INCL_FILES      = ata_defs.h
+INCL_FILES     += bif_core_defs.h
+INCL_ASMFILES  += bif_core_defs_asm.h
+INCL_FILES     += bif_slave_defs.h
+#INCL_FILES     += bif_slave_ext_defs.h
+INCL_FILES     += config_defs.h
+INCL_ASMFILES  += config_defs_asm.h
+INCL_FILES     += cpu_vect.h
+#INCL_FILES     += cris_defs.h
+#INCL_FILES     += cris_supp_reg.h # In handcrafted supp_reg.h
+INCL_FILES     += dma.h
+INCL_FILES     += dma_defs.h
+INCL_FILES     += eth_defs.h
+INCL_FILES     += extmem_defs.h
+INCL_FILES     += gio_defs.h
+INCL_ASMFILES  += gio_defs_asm.h
+INCL_FILES     += intr_vect.h
+INCL_FILES     += intr_vect_defs.h
+INCL_ASMFILES  += intr_vect_defs_asm.h
+INCL_FILES     += marb_bp_defs.h
+INCL_FILES     += marb_defs.h
+INCL_ASMFILES  += mmu_defs_asm.h
+#INCL_FILES     += mmu_supp_reg.h # In handcrafted supp_reg.h
+#INCL_FILES     += par_defs.h # No useful content
+INCL_FILES     += pinmux_defs.h
+INCL_FILES     += reg_map.h
+INCL_ASMFILES  += reg_map_asm.h
+INCL_FILES     += reg_rdwr.h
+INCL_FILES     += ser_defs.h
+#INCL_FILES     += spec_reg.h # In handcrafted supp_reg.h
+INCL_FILES     += sser_defs.h
+INCL_FILES     += strcop_defs.h
+#INCL_FILES     += strcop.h # Where is this?
+INCL_FILES     += strmux_defs.h
+#INCL_FILES     += supp_reg.h # Handcrafted instead
+INCL_FILES     += timer_defs.h
+
+REGDESC =
+REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
+REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
+REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
+#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
+REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
+REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
+REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
+REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
+REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
+REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
+REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
+#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
+REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
+REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
+REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
+REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
+REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
+#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
+
+
+BASEDIR = /n/asic/design
+DESIGNDIR = /n/asic/projects/guinness/design
+RDES2C = /n/asic/bin/rdes2c
+RDES2C = /n/asic/design/tools/rdesc/rdes2c
+RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
+RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
+
+## all    - Just print help - you probably want to do 'make gen'
+all: help
+
+# Disable implicit rule that may generate deleted files from RCS/ directory.
+%.r:
+
+%.h:
+
+## help   - This help
+help:
+        @grep '^## ' Makefile
+
+## gen    - Generate include files
+gen: $(INCL_FILES) $(INCL_ASMFILES)
+
+ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
+        $(RDES2C) $<
+config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
+        $(RDES2C) $<
+config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
+        $(RDES2C) -asm $<
+# Can't generate cpu_vect.h yet
+#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
+#       $(RDES2INTR) $<
+cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
+        $(RDES2C) $<
+$(BASEDIR)/core/dma/sw/dma.h:
+dma.h: $(BASEDIR)/core/dma/sw/dma.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
+        $(RDES2C) $<
+extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
+        $(RDES2C) $<
+gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
+        $(RDES2C) $<
+intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+        $(RDES2C) $<
+intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+        $(RDES2C) -asm $<
+# Can't generate intr_vect.h yet
+#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+#       $(RDES2INTR) $<
+intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
+        $(RDES2C) -asm $<
+par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
+        $(RDES2C) $<
+
+# From /n/asic/projects/guinness/design/
+reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
+        $(RDES2C) -base 0xb0000000 $^
+reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
+        $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
+
+reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+
+ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
+        $(RDES2C) $<
+strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
+        $(RDES2C) $<
+strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
+        $(RDES2C) $<
+timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
+        $(RDES2C) $<
+usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
+        $(RDES2C) $<
+
+## copy   - Copy files from official location
+copy:
+        @for HFILE in $(INCL_FILES); do \
+                echo "  $$HFILE"; \
+                cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+        done
+        @for HFILE in $(INCL_ASMFILES); do \
+                echo "  $$HFILE"; \
+                cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+        done
+## ls_official - List official location
+ls_official:
+        (cd $(OFFICIAL_INCDIR); ls -l *.h )
+
+## diff_official - Diff current directory with official location
+diff_official:
+        diff . $(OFFICIAL_INCDIR)
+
+## doc    - Generate .axw files from register description.
+doc: $(REGDESC)
+        for RDES in $^; do \
+                $(RDES2TXT) $$RDES; \
+        done
+
+.PHONY: axw
+## %.axw  - Generate the specified .axw file (doesn't work for all files
+##          due to inconsistent naming ir .r files.
+%.axw: axw
+        @for RDES in $(REGDESC); do \
+                if echo "$$RDES" | grep $* ; then \
+                  $(RDES2TXT) $$RDES; \
+                fi \
+        done
+
+.PHONY: clean
+## clean  - Remove .h files and .axw files.
+clean:
+        rm -rf $(INCL_FILES) *.axw
+
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
new file mode 100644
index 000000000000..866191418f9c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
@@ -0,0 +1,222 @@
+#ifndef __ata_defs_asm_h
+#define __ata_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ata/rtl/ata_regs.r
+ *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
+ *     last modfied: Mon Apr 11 16:06:25 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
+ *      id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ctrl0, scope ata, type rw */
+#define reg_ata_rw_ctrl0___pio_hold___lsb 0
+#define reg_ata_rw_ctrl0___pio_hold___width 6
+#define reg_ata_rw_ctrl0___pio_strb___lsb 6
+#define reg_ata_rw_ctrl0___pio_strb___width 6
+#define reg_ata_rw_ctrl0___pio_setup___lsb 12
+#define reg_ata_rw_ctrl0___pio_setup___width 6
+#define reg_ata_rw_ctrl0___dma_hold___lsb 18
+#define reg_ata_rw_ctrl0___dma_hold___width 6
+#define reg_ata_rw_ctrl0___dma_strb___lsb 24
+#define reg_ata_rw_ctrl0___dma_strb___width 6
+#define reg_ata_rw_ctrl0___rst___lsb 30
+#define reg_ata_rw_ctrl0___rst___width 1
+#define reg_ata_rw_ctrl0___rst___bit 30
+#define reg_ata_rw_ctrl0___en___lsb 31
+#define reg_ata_rw_ctrl0___en___width 1
+#define reg_ata_rw_ctrl0___en___bit 31
+#define reg_ata_rw_ctrl0_offset 12
+
+/* Register rw_ctrl1, scope ata, type rw */
+#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
+#define reg_ata_rw_ctrl1___udma_tcyc___width 4
+#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
+#define reg_ata_rw_ctrl1___udma_tdvs___width 4
+#define reg_ata_rw_ctrl1_offset 16
+
+/* Register rw_ctrl2, scope ata, type rw */
+#define reg_ata_rw_ctrl2___data___lsb 0
+#define reg_ata_rw_ctrl2___data___width 16
+#define reg_ata_rw_ctrl2___dma_size___lsb 19
+#define reg_ata_rw_ctrl2___dma_size___width 1
+#define reg_ata_rw_ctrl2___dma_size___bit 19
+#define reg_ata_rw_ctrl2___multi___lsb 20
+#define reg_ata_rw_ctrl2___multi___width 1
+#define reg_ata_rw_ctrl2___multi___bit 20
+#define reg_ata_rw_ctrl2___hsh___lsb 21
+#define reg_ata_rw_ctrl2___hsh___width 2
+#define reg_ata_rw_ctrl2___trf_mode___lsb 23
+#define reg_ata_rw_ctrl2___trf_mode___width 1
+#define reg_ata_rw_ctrl2___trf_mode___bit 23
+#define reg_ata_rw_ctrl2___rw___lsb 24
+#define reg_ata_rw_ctrl2___rw___width 1
+#define reg_ata_rw_ctrl2___rw___bit 24
+#define reg_ata_rw_ctrl2___addr___lsb 25
+#define reg_ata_rw_ctrl2___addr___width 3
+#define reg_ata_rw_ctrl2___cs0___lsb 28
+#define reg_ata_rw_ctrl2___cs0___width 1
+#define reg_ata_rw_ctrl2___cs0___bit 28
+#define reg_ata_rw_ctrl2___cs1___lsb 29
+#define reg_ata_rw_ctrl2___cs1___width 1
+#define reg_ata_rw_ctrl2___cs1___bit 29
+#define reg_ata_rw_ctrl2___sel___lsb 30
+#define reg_ata_rw_ctrl2___sel___width 2
+#define reg_ata_rw_ctrl2_offset 0
+
+/* Register rs_stat_data, scope ata, type rs */
+#define reg_ata_rs_stat_data___data___lsb 0
+#define reg_ata_rs_stat_data___data___width 16
+#define reg_ata_rs_stat_data___dav___lsb 16
+#define reg_ata_rs_stat_data___dav___width 1
+#define reg_ata_rs_stat_data___dav___bit 16
+#define reg_ata_rs_stat_data___busy___lsb 17
+#define reg_ata_rs_stat_data___busy___width 1
+#define reg_ata_rs_stat_data___busy___bit 17
+#define reg_ata_rs_stat_data_offset 4
+
+/* Register r_stat_data, scope ata, type r */
+#define reg_ata_r_stat_data___data___lsb 0
+#define reg_ata_r_stat_data___data___width 16
+#define reg_ata_r_stat_data___dav___lsb 16
+#define reg_ata_r_stat_data___dav___width 1
+#define reg_ata_r_stat_data___dav___bit 16
+#define reg_ata_r_stat_data___busy___lsb 17
+#define reg_ata_r_stat_data___busy___width 1
+#define reg_ata_r_stat_data___busy___bit 17
+#define reg_ata_r_stat_data_offset 8
+
+/* Register rw_trf_cnt, scope ata, type rw */
+#define reg_ata_rw_trf_cnt___cnt___lsb 0
+#define reg_ata_rw_trf_cnt___cnt___width 17
+#define reg_ata_rw_trf_cnt_offset 20
+
+/* Register r_stat_misc, scope ata, type r */
+#define reg_ata_r_stat_misc___crc___lsb 0
+#define reg_ata_r_stat_misc___crc___width 16
+#define reg_ata_r_stat_misc_offset 24
+
+/* Register rw_intr_mask, scope ata, type rw */
+#define reg_ata_rw_intr_mask___bus0___lsb 0
+#define reg_ata_rw_intr_mask___bus0___width 1
+#define reg_ata_rw_intr_mask___bus0___bit 0
+#define reg_ata_rw_intr_mask___bus1___lsb 1
+#define reg_ata_rw_intr_mask___bus1___width 1
+#define reg_ata_rw_intr_mask___bus1___bit 1
+#define reg_ata_rw_intr_mask___bus2___lsb 2
+#define reg_ata_rw_intr_mask___bus2___width 1
+#define reg_ata_rw_intr_mask___bus2___bit 2
+#define reg_ata_rw_intr_mask___bus3___lsb 3
+#define reg_ata_rw_intr_mask___bus3___width 1
+#define reg_ata_rw_intr_mask___bus3___bit 3
+#define reg_ata_rw_intr_mask_offset 28
+
+/* Register rw_ack_intr, scope ata, type rw */
+#define reg_ata_rw_ack_intr___bus0___lsb 0
+#define reg_ata_rw_ack_intr___bus0___width 1
+#define reg_ata_rw_ack_intr___bus0___bit 0
+#define reg_ata_rw_ack_intr___bus1___lsb 1
+#define reg_ata_rw_ack_intr___bus1___width 1
+#define reg_ata_rw_ack_intr___bus1___bit 1
+#define reg_ata_rw_ack_intr___bus2___lsb 2
+#define reg_ata_rw_ack_intr___bus2___width 1
+#define reg_ata_rw_ack_intr___bus2___bit 2
+#define reg_ata_rw_ack_intr___bus3___lsb 3
+#define reg_ata_rw_ack_intr___bus3___width 1
+#define reg_ata_rw_ack_intr___bus3___bit 3
+#define reg_ata_rw_ack_intr_offset 32
+
+/* Register r_intr, scope ata, type r */
+#define reg_ata_r_intr___bus0___lsb 0
+#define reg_ata_r_intr___bus0___width 1
+#define reg_ata_r_intr___bus0___bit 0
+#define reg_ata_r_intr___bus1___lsb 1
+#define reg_ata_r_intr___bus1___width 1
+#define reg_ata_r_intr___bus1___bit 1
+#define reg_ata_r_intr___bus2___lsb 2
+#define reg_ata_r_intr___bus2___width 1
+#define reg_ata_r_intr___bus2___bit 2
+#define reg_ata_r_intr___bus3___lsb 3
+#define reg_ata_r_intr___bus3___width 1
+#define reg_ata_r_intr___bus3___bit 3
+#define reg_ata_r_intr_offset 36
+
+/* Register r_masked_intr, scope ata, type r */
+#define reg_ata_r_masked_intr___bus0___lsb 0
+#define reg_ata_r_masked_intr___bus0___width 1
+#define reg_ata_r_masked_intr___bus0___bit 0
+#define reg_ata_r_masked_intr___bus1___lsb 1
+#define reg_ata_r_masked_intr___bus1___width 1
+#define reg_ata_r_masked_intr___bus1___bit 1
+#define reg_ata_r_masked_intr___bus2___lsb 2
+#define reg_ata_r_masked_intr___bus2___width 1
+#define reg_ata_r_masked_intr___bus2___bit 2
+#define reg_ata_r_masked_intr___bus3___lsb 3
+#define reg_ata_r_masked_intr___bus3___width 1
+#define reg_ata_r_masked_intr___bus3___bit 3
+#define reg_ata_r_masked_intr_offset 40
+
+
+/* Constants */
+#define regk_ata_active                           0x00000001
+#define regk_ata_byte                             0x00000001
+#define regk_ata_data                             0x00000001
+#define regk_ata_dma                              0x00000001
+#define regk_ata_inactive                         0x00000000
+#define regk_ata_no                               0x00000000
+#define regk_ata_nodata                           0x00000000
+#define regk_ata_pio                              0x00000000
+#define regk_ata_rd                               0x00000001
+#define regk_ata_reg                              0x00000000
+#define regk_ata_rw_ctrl0_default                 0x00000000
+#define regk_ata_rw_ctrl2_default                 0x00000000
+#define regk_ata_rw_intr_mask_default             0x00000000
+#define regk_ata_udma                             0x00000002
+#define regk_ata_word                             0x00000000
+#define regk_ata_wr                               0x00000000
+#define regk_ata_yes                              0x00000001
+#endif /* __ata_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
new file mode 100644
index 000000000000..c686cb335621
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
@@ -0,0 +1,319 @@
+#ifndef __bif_core_defs_asm_h
+#define __bif_core_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_core_regs.r
+ *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
+ *      id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp1_cfg___lw___width 6
+#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp1_cfg___ew___width 3
+#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp1_cfg___zw___width 3
+#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp1_cfg___aw___width 2
+#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp1_cfg___dw___width 2
+#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp1_cfg___ewb___width 2
+#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp1_cfg___bw___width 1
+#define reg_bif_core_rw_grp1_cfg___bw___bit 18
+#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp1_cfg___mode___width 1
+#define reg_bif_core_rw_grp1_cfg___mode___bit 21
+#define reg_bif_core_rw_grp1_cfg_offset 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp2_cfg___lw___width 6
+#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp2_cfg___ew___width 3
+#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp2_cfg___zw___width 3
+#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp2_cfg___aw___width 2
+#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp2_cfg___dw___width 2
+#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp2_cfg___ewb___width 2
+#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp2_cfg___bw___width 1
+#define reg_bif_core_rw_grp2_cfg___bw___bit 18
+#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp2_cfg___mode___width 1
+#define reg_bif_core_rw_grp2_cfg___mode___bit 21
+#define reg_bif_core_rw_grp2_cfg_offset 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp3_cfg___lw___width 6
+#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp3_cfg___ew___width 3
+#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp3_cfg___zw___width 3
+#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp3_cfg___aw___width 2
+#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp3_cfg___dw___width 2
+#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp3_cfg___ewb___width 2
+#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp3_cfg___bw___width 1
+#define reg_bif_core_rw_grp3_cfg___bw___bit 18
+#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp3_cfg___mode___width 1
+#define reg_bif_core_rw_grp3_cfg___mode___bit 21
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
+#define reg_bif_core_rw_grp3_cfg_offset 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp4_cfg___lw___width 6
+#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp4_cfg___ew___width 3
+#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp4_cfg___zw___width 3
+#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp4_cfg___aw___width 2
+#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp4_cfg___dw___width 2
+#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp4_cfg___ewb___width 2
+#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp4_cfg___bw___width 1
+#define reg_bif_core_rw_grp4_cfg___bw___bit 18
+#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp4_cfg___mode___width 1
+#define reg_bif_core_rw_grp4_cfg___mode___bit 21
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
+#define reg_bif_core_rw_grp4_cfg_offset 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_timing___cl___lsb 0
+#define reg_bif_core_rw_sdram_timing___cl___width 3
+#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
+#define reg_bif_core_rw_sdram_timing___rcd___width 3
+#define reg_bif_core_rw_sdram_timing___rp___lsb 6
+#define reg_bif_core_rw_sdram_timing___rp___width 3
+#define reg_bif_core_rw_sdram_timing___rc___lsb 9
+#define reg_bif_core_rw_sdram_timing___rc___width 2
+#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
+#define reg_bif_core_rw_sdram_timing___dpl___width 2
+#define reg_bif_core_rw_sdram_timing___pde___lsb 13
+#define reg_bif_core_rw_sdram_timing___pde___width 1
+#define reg_bif_core_rw_sdram_timing___pde___bit 13
+#define reg_bif_core_rw_sdram_timing___ref___lsb 14
+#define reg_bif_core_rw_sdram_timing___ref___width 2
+#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
+#define reg_bif_core_rw_sdram_timing___cpd___width 1
+#define reg_bif_core_rw_sdram_timing___cpd___bit 16
+#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
+#define reg_bif_core_rw_sdram_timing___sdcke___width 1
+#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
+#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
+#define reg_bif_core_rw_sdram_timing___sdclk___width 1
+#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
+#define reg_bif_core_rw_sdram_timing_offset 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
+#define reg_bif_core_rw_sdram_cmd___cmd___width 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
+#define reg_bif_core_rw_sdram_cmd_offset 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
+#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_rs_sdram_ref_stat_offset 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_r_sdram_ref_stat___ok___width 1
+#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_r_sdram_ref_stat_offset 36
+
+
+/* Constants */
+#define regk_bif_core_bank2                       0x00000000
+#define regk_bif_core_bank4                       0x00000001
+#define regk_bif_core_bit10                       0x0000000a
+#define regk_bif_core_bit11                       0x0000000b
+#define regk_bif_core_bit12                       0x0000000c
+#define regk_bif_core_bit13                       0x0000000d
+#define regk_bif_core_bit14                       0x0000000e
+#define regk_bif_core_bit15                       0x0000000f
+#define regk_bif_core_bit16                       0x00000010
+#define regk_bif_core_bit17                       0x00000011
+#define regk_bif_core_bit18                       0x00000012
+#define regk_bif_core_bit19                       0x00000013
+#define regk_bif_core_bit20                       0x00000014
+#define regk_bif_core_bit21                       0x00000015
+#define regk_bif_core_bit22                       0x00000016
+#define regk_bif_core_bit23                       0x00000017
+#define regk_bif_core_bit24                       0x00000018
+#define regk_bif_core_bit25                       0x00000019
+#define regk_bif_core_bit26                       0x0000001a
+#define regk_bif_core_bit27                       0x0000001b
+#define regk_bif_core_bit28                       0x0000001c
+#define regk_bif_core_bit29                       0x0000001d
+#define regk_bif_core_bit9                        0x00000009
+#define regk_bif_core_bw16                        0x00000001
+#define regk_bif_core_bw32                        0x00000000
+#define regk_bif_core_bwe                         0x00000000
+#define regk_bif_core_cwe                         0x00000001
+#define regk_bif_core_e15us                       0x00000001
+#define regk_bif_core_e7800ns                     0x00000002
+#define regk_bif_core_grp0                        0x00000000
+#define regk_bif_core_grp1                        0x00000001
+#define regk_bif_core_mrs                         0x00000003
+#define regk_bif_core_no                          0x00000000
+#define regk_bif_core_none                        0x00000000
+#define regk_bif_core_nop                         0x00000000
+#define regk_bif_core_off                         0x00000000
+#define regk_bif_core_pre                         0x00000002
+#define regk_bif_core_r_sdram_ref_stat_default    0x00000001
+#define regk_bif_core_rd                          0x00000002
+#define regk_bif_core_ref                         0x00000001
+#define regk_bif_core_rs_sdram_ref_stat_default   0x00000001
+#define regk_bif_core_rw_grp1_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp2_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp3_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp4_cfg_default         0x000006cf
+#define regk_bif_core_rw_sdram_cfg_grp1_default   0x00000000
+#define regk_bif_core_slf                         0x00000004
+#define regk_bif_core_wr                          0x00000001
+#define regk_bif_core_yes                         0x00000001
+#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
new file mode 100644
index 000000000000..71532aa18168
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
@@ -0,0 +1,495 @@
+#ifndef __bif_dma_defs_asm_h
+#define __bif_dma_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_dma_regs.r
+ *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
+ *      id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ch0_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
+#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
+#define reg_bif_dma_rw_ch0_ctrl_offset 0
+
+/* Register rw_ch0_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch0_addr___addr___width 32
+#define reg_bif_dma_rw_ch0_addr_offset 4
+
+/* Register rw_ch0_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_start___run___lsb 0
+#define reg_bif_dma_rw_ch0_start___run___width 1
+#define reg_bif_dma_rw_ch0_start___run___bit 0
+#define reg_bif_dma_rw_ch0_start_offset 8
+
+/* Register rw_ch0_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch0_cnt_offset 12
+
+/* Register r_ch0_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch0_stat___cnt___width 16
+#define reg_bif_dma_r_ch0_stat___run___lsb 31
+#define reg_bif_dma_r_ch0_stat___run___width 1
+#define reg_bif_dma_r_ch0_stat___run___bit 31
+#define reg_bif_dma_r_ch0_stat_offset 16
+
+/* Register rw_ch1_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
+#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch1_ctrl_offset 32
+
+/* Register rw_ch1_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch1_addr___addr___width 32
+#define reg_bif_dma_rw_ch1_addr_offset 36
+
+/* Register rw_ch1_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_start___run___lsb 0
+#define reg_bif_dma_rw_ch1_start___run___width 1
+#define reg_bif_dma_rw_ch1_start___run___bit 0
+#define reg_bif_dma_rw_ch1_start_offset 40
+
+/* Register rw_ch1_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch1_cnt_offset 44
+
+/* Register r_ch1_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch1_stat___cnt___width 16
+#define reg_bif_dma_r_ch1_stat___run___lsb 31
+#define reg_bif_dma_r_ch1_stat___run___width 1
+#define reg_bif_dma_r_ch1_stat___run___bit 31
+#define reg_bif_dma_r_ch1_stat_offset 48
+
+/* Register rw_ch2_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
+#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
+#define reg_bif_dma_rw_ch2_ctrl_offset 64
+
+/* Register rw_ch2_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch2_addr___addr___width 32
+#define reg_bif_dma_rw_ch2_addr_offset 68
+
+/* Register rw_ch2_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_start___run___lsb 0
+#define reg_bif_dma_rw_ch2_start___run___width 1
+#define reg_bif_dma_rw_ch2_start___run___bit 0
+#define reg_bif_dma_rw_ch2_start_offset 72
+
+/* Register rw_ch2_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch2_cnt_offset 76
+
+/* Register r_ch2_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch2_stat___cnt___width 16
+#define reg_bif_dma_r_ch2_stat___run___lsb 31
+#define reg_bif_dma_r_ch2_stat___run___width 1
+#define reg_bif_dma_r_ch2_stat___run___bit 31
+#define reg_bif_dma_r_ch2_stat_offset 80
+
+/* Register rw_ch3_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
+#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch3_ctrl_offset 96
+
+/* Register rw_ch3_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch3_addr___addr___width 32
+#define reg_bif_dma_rw_ch3_addr_offset 100
+
+/* Register rw_ch3_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_start___run___lsb 0
+#define reg_bif_dma_rw_ch3_start___run___width 1
+#define reg_bif_dma_rw_ch3_start___run___bit 0
+#define reg_bif_dma_rw_ch3_start_offset 104
+
+/* Register rw_ch3_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch3_cnt_offset 108
+
+/* Register r_ch3_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch3_stat___cnt___width 16
+#define reg_bif_dma_r_ch3_stat___run___lsb 31
+#define reg_bif_dma_r_ch3_stat___run___width 1
+#define reg_bif_dma_r_ch3_stat___run___bit 31
+#define reg_bif_dma_r_ch3_stat_offset 112
+
+/* Register rw_intr_mask, scope bif_dma, type rw */
+#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
+#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
+#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
+#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
+#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
+#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
+#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
+#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
+#define reg_bif_dma_rw_intr_mask_offset 128
+
+/* Register rw_ack_intr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
+#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
+#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
+#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
+#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
+#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
+#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
+#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
+#define reg_bif_dma_rw_ack_intr_offset 132
+
+/* Register r_intr, scope bif_dma, type r */
+#define reg_bif_dma_r_intr___ext_dma0___lsb 0
+#define reg_bif_dma_r_intr___ext_dma0___width 1
+#define reg_bif_dma_r_intr___ext_dma0___bit 0
+#define reg_bif_dma_r_intr___ext_dma1___lsb 1
+#define reg_bif_dma_r_intr___ext_dma1___width 1
+#define reg_bif_dma_r_intr___ext_dma1___bit 1
+#define reg_bif_dma_r_intr___ext_dma2___lsb 2
+#define reg_bif_dma_r_intr___ext_dma2___width 1
+#define reg_bif_dma_r_intr___ext_dma2___bit 2
+#define reg_bif_dma_r_intr___ext_dma3___lsb 3
+#define reg_bif_dma_r_intr___ext_dma3___width 1
+#define reg_bif_dma_r_intr___ext_dma3___bit 3
+#define reg_bif_dma_r_intr_offset 136
+
+/* Register r_masked_intr, scope bif_dma, type r */
+#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
+#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
+#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
+#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
+#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
+#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
+#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
+#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
+#define reg_bif_dma_r_masked_intr_offset 140
+
+/* Register rw_pin0_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin0_cfg_offset 160
+
+/* Register rw_pin1_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin1_cfg_offset 164
+
+/* Register rw_pin2_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin2_cfg_offset 168
+
+/* Register rw_pin3_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin3_cfg_offset 172
+
+/* Register rw_pin4_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin4_cfg_offset 176
+
+/* Register rw_pin5_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin5_cfg_offset 180
+
+/* Register rw_pin6_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin6_cfg_offset 184
+
+/* Register rw_pin7_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin7_cfg_offset 188
+
+/* Register r_pin_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_pin_stat___pin0___lsb 0
+#define reg_bif_dma_r_pin_stat___pin0___width 1
+#define reg_bif_dma_r_pin_stat___pin0___bit 0
+#define reg_bif_dma_r_pin_stat___pin1___lsb 1
+#define reg_bif_dma_r_pin_stat___pin1___width 1
+#define reg_bif_dma_r_pin_stat___pin1___bit 1
+#define reg_bif_dma_r_pin_stat___pin2___lsb 2
+#define reg_bif_dma_r_pin_stat___pin2___width 1
+#define reg_bif_dma_r_pin_stat___pin2___bit 2
+#define reg_bif_dma_r_pin_stat___pin3___lsb 3
+#define reg_bif_dma_r_pin_stat___pin3___width 1
+#define reg_bif_dma_r_pin_stat___pin3___bit 3
+#define reg_bif_dma_r_pin_stat___pin4___lsb 4
+#define reg_bif_dma_r_pin_stat___pin4___width 1
+#define reg_bif_dma_r_pin_stat___pin4___bit 4
+#define reg_bif_dma_r_pin_stat___pin5___lsb 5
+#define reg_bif_dma_r_pin_stat___pin5___width 1
+#define reg_bif_dma_r_pin_stat___pin5___bit 5
+#define reg_bif_dma_r_pin_stat___pin6___lsb 6
+#define reg_bif_dma_r_pin_stat___pin6___width 1
+#define reg_bif_dma_r_pin_stat___pin6___bit 6
+#define reg_bif_dma_r_pin_stat___pin7___lsb 7
+#define reg_bif_dma_r_pin_stat___pin7___width 1
+#define reg_bif_dma_r_pin_stat___pin7___bit 7
+#define reg_bif_dma_r_pin_stat_offset 192
+
+
+/* Constants */
+#define regk_bif_dma_as_master                    0x00000001
+#define regk_bif_dma_as_slave                     0x00000001
+#define regk_bif_dma_burst1                       0x00000000
+#define regk_bif_dma_burst8                       0x00000001
+#define regk_bif_dma_bw16                         0x00000001
+#define regk_bif_dma_bw32                         0x00000002
+#define regk_bif_dma_bw8                          0x00000000
+#define regk_bif_dma_dack                         0x00000006
+#define regk_bif_dma_dack_inv                     0x00000007
+#define regk_bif_dma_force                        0x00000001
+#define regk_bif_dma_hi                           0x00000003
+#define regk_bif_dma_inv                          0x00000003
+#define regk_bif_dma_lo                           0x00000002
+#define regk_bif_dma_master                       0x00000001
+#define regk_bif_dma_no                           0x00000000
+#define regk_bif_dma_norm                         0x00000002
+#define regk_bif_dma_off                          0x00000000
+#define regk_bif_dma_rw_ch0_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch0_start_default         0x00000000
+#define regk_bif_dma_rw_ch1_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch1_start_default         0x00000000
+#define regk_bif_dma_rw_ch2_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch2_start_default         0x00000000
+#define regk_bif_dma_rw_ch3_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch3_start_default         0x00000000
+#define regk_bif_dma_rw_intr_mask_default         0x00000000
+#define regk_bif_dma_rw_pin0_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin1_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin2_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin3_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin4_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin5_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin6_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin7_cfg_default          0x00000000
+#define regk_bif_dma_slave                        0x00000002
+#define regk_bif_dma_sreq                         0x00000006
+#define regk_bif_dma_sreq_inv                     0x00000007
+#define regk_bif_dma_tc                           0x00000004
+#define regk_bif_dma_tc_inv                       0x00000005
+#define regk_bif_dma_yes                          0x00000001
+#endif /* __bif_dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
new file mode 100644
index 000000000000..031f33a365bb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
@@ -0,0 +1,249 @@
+#ifndef __bif_slave_defs_asm_h
+#define __bif_slave_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_slave_regs.r
+ *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
+ *     last modfied: Mon Apr 11 16:06:34 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
+ *      id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_slave_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
+#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
+#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
+#define reg_bif_slave_rw_slave_cfg___loopback___width 1
+#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
+#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
+#define reg_bif_slave_rw_slave_cfg___dis___width 1
+#define reg_bif_slave_rw_slave_cfg___dis___bit 6
+#define reg_bif_slave_rw_slave_cfg_offset 0
+
+/* Register r_slave_mode, scope bif_slave, type r */
+#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
+#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
+#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
+#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
+#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
+#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
+#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
+#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
+#define reg_bif_slave_r_slave_mode_offset 4
+
+/* Register rw_ch0_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch0_cfg_offset 16
+
+/* Register rw_ch1_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch1_cfg_offset 20
+
+/* Register rw_ch2_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch2_cfg_offset 24
+
+/* Register rw_ch3_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch3_cfg_offset 28
+
+/* Register rw_arb_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
+#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
+#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
+#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
+#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
+#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
+#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
+#define reg_bif_slave_rw_arb_cfg___release___lsb 7
+#define reg_bif_slave_rw_arb_cfg___release___width 2
+#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
+#define reg_bif_slave_rw_arb_cfg___acquire___width 1
+#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
+#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
+#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
+#define reg_bif_slave_rw_arb_cfg_offset 32
+
+/* Register r_arb_stat, scope bif_slave, type r */
+#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
+#define reg_bif_slave_r_arb_stat___init_mode___width 1
+#define reg_bif_slave_r_arb_stat___init_mode___bit 0
+#define reg_bif_slave_r_arb_stat___mode___lsb 1
+#define reg_bif_slave_r_arb_stat___mode___width 1
+#define reg_bif_slave_r_arb_stat___mode___bit 1
+#define reg_bif_slave_r_arb_stat___brin___lsb 2
+#define reg_bif_slave_r_arb_stat___brin___width 1
+#define reg_bif_slave_r_arb_stat___brin___bit 2
+#define reg_bif_slave_r_arb_stat___brout___lsb 3
+#define reg_bif_slave_r_arb_stat___brout___width 1
+#define reg_bif_slave_r_arb_stat___brout___bit 3
+#define reg_bif_slave_r_arb_stat___bg___lsb 4
+#define reg_bif_slave_r_arb_stat___bg___width 1
+#define reg_bif_slave_r_arb_stat___bg___bit 4
+#define reg_bif_slave_r_arb_stat_offset 36
+
+/* Register rw_intr_mask, scope bif_slave, type rw */
+#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
+#define reg_bif_slave_rw_intr_mask___bus_release___width 1
+#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
+#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
+#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
+#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
+#define reg_bif_slave_rw_intr_mask_offset 64
+
+/* Register rw_ack_intr, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
+#define reg_bif_slave_rw_ack_intr___bus_release___width 1
+#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
+#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
+#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
+#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
+#define reg_bif_slave_rw_ack_intr_offset 68
+
+/* Register r_intr, scope bif_slave, type r */
+#define reg_bif_slave_r_intr___bus_release___lsb 0
+#define reg_bif_slave_r_intr___bus_release___width 1
+#define reg_bif_slave_r_intr___bus_release___bit 0
+#define reg_bif_slave_r_intr___bus_acquire___lsb 1
+#define reg_bif_slave_r_intr___bus_acquire___width 1
+#define reg_bif_slave_r_intr___bus_acquire___bit 1
+#define reg_bif_slave_r_intr_offset 72
+
+/* Register r_masked_intr, scope bif_slave, type r */
+#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
+#define reg_bif_slave_r_masked_intr___bus_release___width 1
+#define reg_bif_slave_r_masked_intr___bus_release___bit 0
+#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
+#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
+#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
+#define reg_bif_slave_r_masked_intr_offset 76
+
+
+/* Constants */
+#define regk_bif_slave_active_hi                  0x00000003
+#define regk_bif_slave_active_lo                  0x00000002
+#define regk_bif_slave_addr                       0x00000000
+#define regk_bif_slave_always                     0x00000001
+#define regk_bif_slave_at_idle                    0x00000002
+#define regk_bif_slave_burst_end                  0x00000003
+#define regk_bif_slave_dma                        0x00000001
+#define regk_bif_slave_hi                         0x00000003
+#define regk_bif_slave_inv                        0x00000001
+#define regk_bif_slave_lo                         0x00000002
+#define regk_bif_slave_local                      0x00000001
+#define regk_bif_slave_master                     0x00000000
+#define regk_bif_slave_mode_reg                   0x00000001
+#define regk_bif_slave_no                         0x00000000
+#define regk_bif_slave_norm                       0x00000000
+#define regk_bif_slave_on_access                  0x00000000
+#define regk_bif_slave_rw_arb_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch0_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch1_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch2_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch3_cfg_default         0x00000000
+#define regk_bif_slave_rw_intr_mask_default       0x00000000
+#define regk_bif_slave_rw_slave_cfg_default       0x00000000
+#define regk_bif_slave_shared                     0x00000000
+#define regk_bif_slave_slave                      0x00000001
+#define regk_bif_slave_t0ns                       0x00000003
+#define regk_bif_slave_t10ns                      0x00000002
+#define regk_bif_slave_t20ns                      0x00000003
+#define regk_bif_slave_t30ns                      0x00000002
+#define regk_bif_slave_t40ns                      0x00000001
+#define regk_bif_slave_t50ns                      0x00000000
+#define regk_bif_slave_yes                        0x00000001
+#define regk_bif_slave_z                          0x00000004
+#endif /* __bif_slave_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
new file mode 100644
index 000000000000..e98476332e1f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
@@ -0,0 +1,131 @@
+#ifndef __config_defs_asm_h
+#define __config_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../rtl/config_regs.r
+ *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ *     last modfied: Thu Mar  4 12:34:39 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
+ *      id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_bootsel, scope config, type r */
+#define reg_config_r_bootsel___boot_mode___lsb 0
+#define reg_config_r_bootsel___boot_mode___width 3
+#define reg_config_r_bootsel___full_duplex___lsb 3
+#define reg_config_r_bootsel___full_duplex___width 1
+#define reg_config_r_bootsel___full_duplex___bit 3
+#define reg_config_r_bootsel___user___lsb 4
+#define reg_config_r_bootsel___user___width 1
+#define reg_config_r_bootsel___user___bit 4
+#define reg_config_r_bootsel___pll___lsb 5
+#define reg_config_r_bootsel___pll___width 1
+#define reg_config_r_bootsel___pll___bit 5
+#define reg_config_r_bootsel___flash_bw___lsb 6
+#define reg_config_r_bootsel___flash_bw___width 1
+#define reg_config_r_bootsel___flash_bw___bit 6
+#define reg_config_r_bootsel_offset 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+#define reg_config_rw_clk_ctrl___pll___lsb 0
+#define reg_config_rw_clk_ctrl___pll___width 1
+#define reg_config_rw_clk_ctrl___pll___bit 0
+#define reg_config_rw_clk_ctrl___cpu___lsb 1
+#define reg_config_rw_clk_ctrl___cpu___width 1
+#define reg_config_rw_clk_ctrl___cpu___bit 1
+#define reg_config_rw_clk_ctrl___iop___lsb 2
+#define reg_config_rw_clk_ctrl___iop___width 1
+#define reg_config_rw_clk_ctrl___iop___bit 2
+#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
+#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
+#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
+#define reg_config_rw_clk_ctrl___dma23___lsb 4
+#define reg_config_rw_clk_ctrl___dma23___width 1
+#define reg_config_rw_clk_ctrl___dma23___bit 4
+#define reg_config_rw_clk_ctrl___dma45___lsb 5
+#define reg_config_rw_clk_ctrl___dma45___width 1
+#define reg_config_rw_clk_ctrl___dma45___bit 5
+#define reg_config_rw_clk_ctrl___dma67___lsb 6
+#define reg_config_rw_clk_ctrl___dma67___width 1
+#define reg_config_rw_clk_ctrl___dma67___bit 6
+#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
+#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
+#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
+#define reg_config_rw_clk_ctrl___bif___lsb 8
+#define reg_config_rw_clk_ctrl___bif___width 1
+#define reg_config_rw_clk_ctrl___bif___bit 8
+#define reg_config_rw_clk_ctrl___fix_io___lsb 9
+#define reg_config_rw_clk_ctrl___fix_io___width 1
+#define reg_config_rw_clk_ctrl___fix_io___bit 9
+#define reg_config_rw_clk_ctrl_offset 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
+#define reg_config_rw_pad_ctrl___usb_susp___width 1
+#define reg_config_rw_pad_ctrl___usb_susp___bit 0
+#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
+#define reg_config_rw_pad_ctrl___phyrst_n___width 1
+#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
+#define reg_config_rw_pad_ctrl_offset 8
+
+
+/* Constants */
+#define regk_config_bw16                          0x00000000
+#define regk_config_bw32                          0x00000001
+#define regk_config_master                        0x00000005
+#define regk_config_nand                          0x00000003
+#define regk_config_net_rx                        0x00000001
+#define regk_config_net_tx_rx                     0x00000002
+#define regk_config_no                            0x00000000
+#define regk_config_none                          0x00000007
+#define regk_config_nor                           0x00000000
+#define regk_config_rw_clk_ctrl_default           0x00000002
+#define regk_config_rw_pad_ctrl_default           0x00000000
+#define regk_config_ser                           0x00000004
+#define regk_config_slave                         0x00000006
+#define regk_config_yes                           0x00000001
+#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
new file mode 100644
index 000000000000..8370aee8a14a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
@@ -0,0 +1,41 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/crisp/doc/cpu_vect.r
+version . */
+
+#ifndef _______INST_CRISP_DOC_CPU_VECT_R
+#define _______INST_CRISP_DOC_CPU_VECT_R
+#define NMI_INTR_VECT   0x00
+#define RESERVED_1_INTR_VECT    0x01
+#define RESERVED_2_INTR_VECT    0x02
+#define SINGLE_STEP_INTR_VECT   0x03
+#define INSTR_TLB_REFILL_INTR_VECT      0x04
+#define INSTR_TLB_INV_INTR_VECT 0x05
+#define INSTR_TLB_ACC_INTR_VECT 0x06
+#define TLB_EX_INTR_VECT        0x07
+#define DATA_TLB_REFILL_INTR_VECT       0x08
+#define DATA_TLB_INV_INTR_VECT  0x09
+#define DATA_TLB_ACC_INTR_VECT  0x0a
+#define DATA_TLB_WE_INTR_VECT   0x0b
+#define HW_BP_INTR_VECT 0x0c
+#define RESERVED_D_INTR_VECT    0x0d
+#define RESERVED_E_INTR_VECT    0x0e
+#define RESERVED_F_INTR_VECT    0x0f
+#define BREAK_0_INTR_VECT       0x10
+#define BREAK_1_INTR_VECT       0x11
+#define BREAK_2_INTR_VECT       0x12
+#define BREAK_3_INTR_VECT       0x13
+#define BREAK_4_INTR_VECT       0x14
+#define BREAK_5_INTR_VECT       0x15
+#define BREAK_6_INTR_VECT       0x16
+#define BREAK_7_INTR_VECT       0x17
+#define BREAK_8_INTR_VECT       0x18
+#define BREAK_9_INTR_VECT       0x19
+#define BREAK_10_INTR_VECT      0x1a
+#define BREAK_11_INTR_VECT      0x1b
+#define BREAK_12_INTR_VECT      0x1c
+#define BREAK_13_INTR_VECT      0x1d
+#define BREAK_14_INTR_VECT      0x1e
+#define BREAK_15_INTR_VECT      0x1f
+#define MULTIPLE_INTR_VECT      0x30
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
new file mode 100644
index 000000000000..7f768db272e2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
@@ -0,0 +1,114 @@
+#ifndef __cris_defs_asm_h
+#define __cris_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/crisp/doc/cris.r
+ *     id:           cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
+ *     last modfied: Mon Apr 11 16:06:39 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
+ *      id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_gc_cfg, scope cris, type rw */
+#define reg_cris_rw_gc_cfg___ic___lsb 0
+#define reg_cris_rw_gc_cfg___ic___width 1
+#define reg_cris_rw_gc_cfg___ic___bit 0
+#define reg_cris_rw_gc_cfg___dc___lsb 1
+#define reg_cris_rw_gc_cfg___dc___width 1
+#define reg_cris_rw_gc_cfg___dc___bit 1
+#define reg_cris_rw_gc_cfg___im___lsb 2
+#define reg_cris_rw_gc_cfg___im___width 1
+#define reg_cris_rw_gc_cfg___im___bit 2
+#define reg_cris_rw_gc_cfg___dm___lsb 3
+#define reg_cris_rw_gc_cfg___dm___width 1
+#define reg_cris_rw_gc_cfg___dm___bit 3
+#define reg_cris_rw_gc_cfg___gb___lsb 4
+#define reg_cris_rw_gc_cfg___gb___width 1
+#define reg_cris_rw_gc_cfg___gb___bit 4
+#define reg_cris_rw_gc_cfg___gk___lsb 5
+#define reg_cris_rw_gc_cfg___gk___width 1
+#define reg_cris_rw_gc_cfg___gk___bit 5
+#define reg_cris_rw_gc_cfg___gp___lsb 6
+#define reg_cris_rw_gc_cfg___gp___width 1
+#define reg_cris_rw_gc_cfg___gp___bit 6
+#define reg_cris_rw_gc_cfg_offset 0
+
+/* Register rw_gc_ccs, scope cris, type rw */
+#define reg_cris_rw_gc_ccs_offset 4
+
+/* Register rw_gc_srs, scope cris, type rw */
+#define reg_cris_rw_gc_srs___srs___lsb 0
+#define reg_cris_rw_gc_srs___srs___width 8
+#define reg_cris_rw_gc_srs_offset 8
+
+/* Register rw_gc_nrp, scope cris, type rw */
+#define reg_cris_rw_gc_nrp_offset 12
+
+/* Register rw_gc_exs, scope cris, type rw */
+#define reg_cris_rw_gc_exs_offset 16
+
+/* Register rw_gc_eda, scope cris, type rw */
+#define reg_cris_rw_gc_eda_offset 20
+
+/* Register rw_gc_r0, scope cris, type rw */
+#define reg_cris_rw_gc_r0_offset 32
+
+/* Register rw_gc_r1, scope cris, type rw */
+#define reg_cris_rw_gc_r1_offset 36
+
+/* Register rw_gc_r2, scope cris, type rw */
+#define reg_cris_rw_gc_r2_offset 40
+
+/* Register rw_gc_r3, scope cris, type rw */
+#define reg_cris_rw_gc_r3_offset 44
+
+
+/* Constants */
+#define regk_cris_no                              0x00000000
+#define regk_cris_rw_gc_cfg_default               0x00000000
+#define regk_cris_yes                             0x00000001
+#endif /* __cris_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
new file mode 100644
index 000000000000..7d3689a6f80d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
@@ -0,0 +1,10 @@
+#define RW_GC_CFG       0
+#define RW_GC_CCS       1
+#define RW_GC_SRS       2
+#define RW_GC_NRP       3
+#define RW_GC_EXS       4
+#define RW_GC_EDA       5
+#define RW_GC_R0        8
+#define RW_GC_R1        9
+#define RW_GC_R2        10
+#define RW_GC_R3        11
diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
new file mode 100644
index 000000000000..0cb71bc127ae
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
@@ -0,0 +1,368 @@
+#ifndef __dma_defs_asm_h
+#define __dma_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
+ *     last modfied: Mon Apr 11 16:06:51 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *      id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_data, scope dma, type rw */
+#define reg_dma_rw_data_offset 0
+
+/* Register rw_data_next, scope dma, type rw */
+#define reg_dma_rw_data_next_offset 4
+
+/* Register rw_data_buf, scope dma, type rw */
+#define reg_dma_rw_data_buf_offset 8
+
+/* Register rw_data_ctrl, scope dma, type rw */
+#define reg_dma_rw_data_ctrl___eol___lsb 0
+#define reg_dma_rw_data_ctrl___eol___width 1
+#define reg_dma_rw_data_ctrl___eol___bit 0
+#define reg_dma_rw_data_ctrl___out_eop___lsb 3
+#define reg_dma_rw_data_ctrl___out_eop___width 1
+#define reg_dma_rw_data_ctrl___out_eop___bit 3
+#define reg_dma_rw_data_ctrl___intr___lsb 4
+#define reg_dma_rw_data_ctrl___intr___width 1
+#define reg_dma_rw_data_ctrl___intr___bit 4
+#define reg_dma_rw_data_ctrl___wait___lsb 5
+#define reg_dma_rw_data_ctrl___wait___width 1
+#define reg_dma_rw_data_ctrl___wait___bit 5
+#define reg_dma_rw_data_ctrl_offset 12
+
+/* Register rw_data_stat, scope dma, type rw */
+#define reg_dma_rw_data_stat___in_eop___lsb 3
+#define reg_dma_rw_data_stat___in_eop___width 1
+#define reg_dma_rw_data_stat___in_eop___bit 3
+#define reg_dma_rw_data_stat_offset 16
+
+/* Register rw_data_md, scope dma, type rw */
+#define reg_dma_rw_data_md___md___lsb 0
+#define reg_dma_rw_data_md___md___width 16
+#define reg_dma_rw_data_md_offset 20
+
+/* Register rw_data_md_s, scope dma, type rw */
+#define reg_dma_rw_data_md_s___md_s___lsb 0
+#define reg_dma_rw_data_md_s___md_s___width 16
+#define reg_dma_rw_data_md_s_offset 24
+
+/* Register rw_data_after, scope dma, type rw */
+#define reg_dma_rw_data_after_offset 28
+
+/* Register rw_ctxt, scope dma, type rw */
+#define reg_dma_rw_ctxt_offset 32
+
+/* Register rw_ctxt_next, scope dma, type rw */
+#define reg_dma_rw_ctxt_next_offset 36
+
+/* Register rw_ctxt_ctrl, scope dma, type rw */
+#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
+#define reg_dma_rw_ctxt_ctrl___eol___width 1
+#define reg_dma_rw_ctxt_ctrl___eol___bit 0
+#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
+#define reg_dma_rw_ctxt_ctrl___intr___width 1
+#define reg_dma_rw_ctxt_ctrl___intr___bit 4
+#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
+#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
+#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
+#define reg_dma_rw_ctxt_ctrl___en___lsb 7
+#define reg_dma_rw_ctxt_ctrl___en___width 1
+#define reg_dma_rw_ctxt_ctrl___en___bit 7
+#define reg_dma_rw_ctxt_ctrl_offset 40
+
+/* Register rw_ctxt_stat, scope dma, type rw */
+#define reg_dma_rw_ctxt_stat___dis___lsb 7
+#define reg_dma_rw_ctxt_stat___dis___width 1
+#define reg_dma_rw_ctxt_stat___dis___bit 7
+#define reg_dma_rw_ctxt_stat_offset 44
+
+/* Register rw_ctxt_md0, scope dma, type rw */
+#define reg_dma_rw_ctxt_md0___md0___lsb 0
+#define reg_dma_rw_ctxt_md0___md0___width 16
+#define reg_dma_rw_ctxt_md0_offset 48
+
+/* Register rw_ctxt_md0_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
+#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
+#define reg_dma_rw_ctxt_md0_s_offset 52
+
+/* Register rw_ctxt_md1, scope dma, type rw */
+#define reg_dma_rw_ctxt_md1_offset 56
+
+/* Register rw_ctxt_md1_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md1_s_offset 60
+
+/* Register rw_ctxt_md2, scope dma, type rw */
+#define reg_dma_rw_ctxt_md2_offset 64
+
+/* Register rw_ctxt_md2_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md2_s_offset 68
+
+/* Register rw_ctxt_md3, scope dma, type rw */
+#define reg_dma_rw_ctxt_md3_offset 72
+
+/* Register rw_ctxt_md3_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md3_s_offset 76
+
+/* Register rw_ctxt_md4, scope dma, type rw */
+#define reg_dma_rw_ctxt_md4_offset 80
+
+/* Register rw_ctxt_md4_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md4_s_offset 84
+
+/* Register rw_saved_data, scope dma, type rw */
+#define reg_dma_rw_saved_data_offset 88
+
+/* Register rw_saved_data_buf, scope dma, type rw */
+#define reg_dma_rw_saved_data_buf_offset 92
+
+/* Register rw_group, scope dma, type rw */
+#define reg_dma_rw_group_offset 96
+
+/* Register rw_group_next, scope dma, type rw */
+#define reg_dma_rw_group_next_offset 100
+
+/* Register rw_group_ctrl, scope dma, type rw */
+#define reg_dma_rw_group_ctrl___eol___lsb 0
+#define reg_dma_rw_group_ctrl___eol___width 1
+#define reg_dma_rw_group_ctrl___eol___bit 0
+#define reg_dma_rw_group_ctrl___tol___lsb 1
+#define reg_dma_rw_group_ctrl___tol___width 1
+#define reg_dma_rw_group_ctrl___tol___bit 1
+#define reg_dma_rw_group_ctrl___bol___lsb 2
+#define reg_dma_rw_group_ctrl___bol___width 1
+#define reg_dma_rw_group_ctrl___bol___bit 2
+#define reg_dma_rw_group_ctrl___intr___lsb 4
+#define reg_dma_rw_group_ctrl___intr___width 1
+#define reg_dma_rw_group_ctrl___intr___bit 4
+#define reg_dma_rw_group_ctrl___en___lsb 7
+#define reg_dma_rw_group_ctrl___en___width 1
+#define reg_dma_rw_group_ctrl___en___bit 7
+#define reg_dma_rw_group_ctrl_offset 104
+
+/* Register rw_group_stat, scope dma, type rw */
+#define reg_dma_rw_group_stat___dis___lsb 7
+#define reg_dma_rw_group_stat___dis___width 1
+#define reg_dma_rw_group_stat___dis___bit 7
+#define reg_dma_rw_group_stat_offset 108
+
+/* Register rw_group_md, scope dma, type rw */
+#define reg_dma_rw_group_md___md___lsb 0
+#define reg_dma_rw_group_md___md___width 16
+#define reg_dma_rw_group_md_offset 112
+
+/* Register rw_group_md_s, scope dma, type rw */
+#define reg_dma_rw_group_md_s___md_s___lsb 0
+#define reg_dma_rw_group_md_s___md_s___width 16
+#define reg_dma_rw_group_md_s_offset 116
+
+/* Register rw_group_up, scope dma, type rw */
+#define reg_dma_rw_group_up_offset 120
+
+/* Register rw_group_down, scope dma, type rw */
+#define reg_dma_rw_group_down_offset 124
+
+/* Register rw_cmd, scope dma, type rw */
+#define reg_dma_rw_cmd___cont_data___lsb 0
+#define reg_dma_rw_cmd___cont_data___width 1
+#define reg_dma_rw_cmd___cont_data___bit 0
+#define reg_dma_rw_cmd_offset 128
+
+/* Register rw_cfg, scope dma, type rw */
+#define reg_dma_rw_cfg___en___lsb 0
+#define reg_dma_rw_cfg___en___width 1
+#define reg_dma_rw_cfg___en___bit 0
+#define reg_dma_rw_cfg___stop___lsb 1
+#define reg_dma_rw_cfg___stop___width 1
+#define reg_dma_rw_cfg___stop___bit 1
+#define reg_dma_rw_cfg_offset 132
+
+/* Register rw_stat, scope dma, type rw */
+#define reg_dma_rw_stat___mode___lsb 0
+#define reg_dma_rw_stat___mode___width 5
+#define reg_dma_rw_stat___list_state___lsb 5
+#define reg_dma_rw_stat___list_state___width 3
+#define reg_dma_rw_stat___stream_cmd_src___lsb 8
+#define reg_dma_rw_stat___stream_cmd_src___width 8
+#define reg_dma_rw_stat___buf___lsb 24
+#define reg_dma_rw_stat___buf___width 8
+#define reg_dma_rw_stat_offset 136
+
+/* Register rw_intr_mask, scope dma, type rw */
+#define reg_dma_rw_intr_mask___group___lsb 0
+#define reg_dma_rw_intr_mask___group___width 1
+#define reg_dma_rw_intr_mask___group___bit 0
+#define reg_dma_rw_intr_mask___ctxt___lsb 1
+#define reg_dma_rw_intr_mask___ctxt___width 1
+#define reg_dma_rw_intr_mask___ctxt___bit 1
+#define reg_dma_rw_intr_mask___data___lsb 2
+#define reg_dma_rw_intr_mask___data___width 1
+#define reg_dma_rw_intr_mask___data___bit 2
+#define reg_dma_rw_intr_mask___in_eop___lsb 3
+#define reg_dma_rw_intr_mask___in_eop___width 1
+#define reg_dma_rw_intr_mask___in_eop___bit 3
+#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
+#define reg_dma_rw_intr_mask___stream_cmd___width 1
+#define reg_dma_rw_intr_mask___stream_cmd___bit 4
+#define reg_dma_rw_intr_mask_offset 140
+
+/* Register rw_ack_intr, scope dma, type rw */
+#define reg_dma_rw_ack_intr___group___lsb 0
+#define reg_dma_rw_ack_intr___group___width 1
+#define reg_dma_rw_ack_intr___group___bit 0
+#define reg_dma_rw_ack_intr___ctxt___lsb 1
+#define reg_dma_rw_ack_intr___ctxt___width 1
+#define reg_dma_rw_ack_intr___ctxt___bit 1
+#define reg_dma_rw_ack_intr___data___lsb 2
+#define reg_dma_rw_ack_intr___data___width 1
+#define reg_dma_rw_ack_intr___data___bit 2
+#define reg_dma_rw_ack_intr___in_eop___lsb 3
+#define reg_dma_rw_ack_intr___in_eop___width 1
+#define reg_dma_rw_ack_intr___in_eop___bit 3
+#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
+#define reg_dma_rw_ack_intr___stream_cmd___width 1
+#define reg_dma_rw_ack_intr___stream_cmd___bit 4
+#define reg_dma_rw_ack_intr_offset 144
+
+/* Register r_intr, scope dma, type r */
+#define reg_dma_r_intr___group___lsb 0
+#define reg_dma_r_intr___group___width 1
+#define reg_dma_r_intr___group___bit 0
+#define reg_dma_r_intr___ctxt___lsb 1
+#define reg_dma_r_intr___ctxt___width 1
+#define reg_dma_r_intr___ctxt___bit 1
+#define reg_dma_r_intr___data___lsb 2
+#define reg_dma_r_intr___data___width 1
+#define reg_dma_r_intr___data___bit 2
+#define reg_dma_r_intr___in_eop___lsb 3
+#define reg_dma_r_intr___in_eop___width 1
+#define reg_dma_r_intr___in_eop___bit 3
+#define reg_dma_r_intr___stream_cmd___lsb 4
+#define reg_dma_r_intr___stream_cmd___width 1
+#define reg_dma_r_intr___stream_cmd___bit 4
+#define reg_dma_r_intr_offset 148
+
+/* Register r_masked_intr, scope dma, type r */
+#define reg_dma_r_masked_intr___group___lsb 0
+#define reg_dma_r_masked_intr___group___width 1
+#define reg_dma_r_masked_intr___group___bit 0
+#define reg_dma_r_masked_intr___ctxt___lsb 1
+#define reg_dma_r_masked_intr___ctxt___width 1
+#define reg_dma_r_masked_intr___ctxt___bit 1
+#define reg_dma_r_masked_intr___data___lsb 2
+#define reg_dma_r_masked_intr___data___width 1
+#define reg_dma_r_masked_intr___data___bit 2
+#define reg_dma_r_masked_intr___in_eop___lsb 3
+#define reg_dma_r_masked_intr___in_eop___width 1
+#define reg_dma_r_masked_intr___in_eop___bit 3
+#define reg_dma_r_masked_intr___stream_cmd___lsb 4
+#define reg_dma_r_masked_intr___stream_cmd___width 1
+#define reg_dma_r_masked_intr___stream_cmd___bit 4
+#define reg_dma_r_masked_intr_offset 152
+
+/* Register rw_stream_cmd, scope dma, type rw */
+#define reg_dma_rw_stream_cmd___cmd___lsb 0
+#define reg_dma_rw_stream_cmd___cmd___width 10
+#define reg_dma_rw_stream_cmd___n___lsb 16
+#define reg_dma_rw_stream_cmd___n___width 8
+#define reg_dma_rw_stream_cmd___busy___lsb 31
+#define reg_dma_rw_stream_cmd___busy___width 1
+#define reg_dma_rw_stream_cmd___busy___bit 31
+#define reg_dma_rw_stream_cmd_offset 156
+
+
+/* Constants */
+#define regk_dma_ack_pkt                          0x00000100
+#define regk_dma_anytime                          0x00000001
+#define regk_dma_array                            0x00000008
+#define regk_dma_burst                            0x00000020
+#define regk_dma_client                           0x00000002
+#define regk_dma_copy_next                        0x00000010
+#define regk_dma_copy_up                          0x00000020
+#define regk_dma_data_at_eol                      0x00000001
+#define regk_dma_dis_c                            0x00000010
+#define regk_dma_dis_g                            0x00000020
+#define regk_dma_idle                             0x00000001
+#define regk_dma_intern                           0x00000004
+#define regk_dma_load_c                           0x00000200
+#define regk_dma_load_c_n                         0x00000280
+#define regk_dma_load_c_next                      0x00000240
+#define regk_dma_load_d                           0x00000140
+#define regk_dma_load_g                           0x00000300
+#define regk_dma_load_g_down                      0x000003c0
+#define regk_dma_load_g_next                      0x00000340
+#define regk_dma_load_g_up                        0x00000380
+#define regk_dma_next_en                          0x00000010
+#define regk_dma_next_pkt                         0x00000010
+#define regk_dma_no                               0x00000000
+#define regk_dma_only_at_wait                     0x00000000
+#define regk_dma_restore                          0x00000020
+#define regk_dma_rst                              0x00000001
+#define regk_dma_running                          0x00000004
+#define regk_dma_rw_cfg_default                   0x00000000
+#define regk_dma_rw_cmd_default                   0x00000000
+#define regk_dma_rw_intr_mask_default             0x00000000
+#define regk_dma_rw_stat_default                  0x00000101
+#define regk_dma_rw_stream_cmd_default            0x00000000
+#define regk_dma_save_down                        0x00000020
+#define regk_dma_save_up                          0x00000020
+#define regk_dma_set_reg                          0x00000050
+#define regk_dma_set_w_size1                      0x00000190
+#define regk_dma_set_w_size2                      0x000001a0
+#define regk_dma_set_w_size4                      0x000001c0
+#define regk_dma_stopped                          0x00000002
+#define regk_dma_store_c                          0x00000002
+#define regk_dma_store_descr                      0x00000000
+#define regk_dma_store_g                          0x00000004
+#define regk_dma_store_md                         0x00000001
+#define regk_dma_sw                               0x00000008
+#define regk_dma_update_down                      0x00000020
+#define regk_dma_yes                              0x00000001
+#endif /* __dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
new file mode 100644
index 000000000000..c9f49864831b
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
@@ -0,0 +1,498 @@
+#ifndef __eth_defs_asm_h
+#define __eth_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/eth/rtl/eth_regs.r
+ *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
+ *     last modfied: Mon Apr 11 16:07:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
+ *      id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ma0_lo, scope eth, type rw */
+#define reg_eth_rw_ma0_lo___addr___lsb 0
+#define reg_eth_rw_ma0_lo___addr___width 32
+#define reg_eth_rw_ma0_lo_offset 0
+
+/* Register rw_ma0_hi, scope eth, type rw */
+#define reg_eth_rw_ma0_hi___addr___lsb 0
+#define reg_eth_rw_ma0_hi___addr___width 16
+#define reg_eth_rw_ma0_hi_offset 4
+
+/* Register rw_ma1_lo, scope eth, type rw */
+#define reg_eth_rw_ma1_lo___addr___lsb 0
+#define reg_eth_rw_ma1_lo___addr___width 32
+#define reg_eth_rw_ma1_lo_offset 8
+
+/* Register rw_ma1_hi, scope eth, type rw */
+#define reg_eth_rw_ma1_hi___addr___lsb 0
+#define reg_eth_rw_ma1_hi___addr___width 16
+#define reg_eth_rw_ma1_hi_offset 12
+
+/* Register rw_ga_lo, scope eth, type rw */
+#define reg_eth_rw_ga_lo___table___lsb 0
+#define reg_eth_rw_ga_lo___table___width 32
+#define reg_eth_rw_ga_lo_offset 16
+
+/* Register rw_ga_hi, scope eth, type rw */
+#define reg_eth_rw_ga_hi___table___lsb 0
+#define reg_eth_rw_ga_hi___table___width 32
+#define reg_eth_rw_ga_hi_offset 20
+
+/* Register rw_gen_ctrl, scope eth, type rw */
+#define reg_eth_rw_gen_ctrl___en___lsb 0
+#define reg_eth_rw_gen_ctrl___en___width 1
+#define reg_eth_rw_gen_ctrl___en___bit 0
+#define reg_eth_rw_gen_ctrl___phy___lsb 1
+#define reg_eth_rw_gen_ctrl___phy___width 2
+#define reg_eth_rw_gen_ctrl___protocol___lsb 3
+#define reg_eth_rw_gen_ctrl___protocol___width 1
+#define reg_eth_rw_gen_ctrl___protocol___bit 3
+#define reg_eth_rw_gen_ctrl___loopback___lsb 4
+#define reg_eth_rw_gen_ctrl___loopback___width 1
+#define reg_eth_rw_gen_ctrl___loopback___bit 4
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
+#define reg_eth_rw_gen_ctrl_offset 24
+
+/* Register rw_rec_ctrl, scope eth, type rw */
+#define reg_eth_rw_rec_ctrl___ma0___lsb 0
+#define reg_eth_rw_rec_ctrl___ma0___width 1
+#define reg_eth_rw_rec_ctrl___ma0___bit 0
+#define reg_eth_rw_rec_ctrl___ma1___lsb 1
+#define reg_eth_rw_rec_ctrl___ma1___width 1
+#define reg_eth_rw_rec_ctrl___ma1___bit 1
+#define reg_eth_rw_rec_ctrl___individual___lsb 2
+#define reg_eth_rw_rec_ctrl___individual___width 1
+#define reg_eth_rw_rec_ctrl___individual___bit 2
+#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
+#define reg_eth_rw_rec_ctrl___broadcast___width 1
+#define reg_eth_rw_rec_ctrl___broadcast___bit 3
+#define reg_eth_rw_rec_ctrl___undersize___lsb 4
+#define reg_eth_rw_rec_ctrl___undersize___width 1
+#define reg_eth_rw_rec_ctrl___undersize___bit 4
+#define reg_eth_rw_rec_ctrl___oversize___lsb 5
+#define reg_eth_rw_rec_ctrl___oversize___width 1
+#define reg_eth_rw_rec_ctrl___oversize___bit 5
+#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
+#define reg_eth_rw_rec_ctrl___bad_crc___width 1
+#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
+#define reg_eth_rw_rec_ctrl___duplex___lsb 7
+#define reg_eth_rw_rec_ctrl___duplex___width 1
+#define reg_eth_rw_rec_ctrl___duplex___bit 7
+#define reg_eth_rw_rec_ctrl___max_size___lsb 8
+#define reg_eth_rw_rec_ctrl___max_size___width 1
+#define reg_eth_rw_rec_ctrl___max_size___bit 8
+#define reg_eth_rw_rec_ctrl_offset 28
+
+/* Register rw_tr_ctrl, scope eth, type rw */
+#define reg_eth_rw_tr_ctrl___crc___lsb 0
+#define reg_eth_rw_tr_ctrl___crc___width 1
+#define reg_eth_rw_tr_ctrl___crc___bit 0
+#define reg_eth_rw_tr_ctrl___pad___lsb 1
+#define reg_eth_rw_tr_ctrl___pad___width 1
+#define reg_eth_rw_tr_ctrl___pad___bit 1
+#define reg_eth_rw_tr_ctrl___retry___lsb 2
+#define reg_eth_rw_tr_ctrl___retry___width 1
+#define reg_eth_rw_tr_ctrl___retry___bit 2
+#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
+#define reg_eth_rw_tr_ctrl___ignore_col___width 1
+#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
+#define reg_eth_rw_tr_ctrl___cancel___lsb 4
+#define reg_eth_rw_tr_ctrl___cancel___width 1
+#define reg_eth_rw_tr_ctrl___cancel___bit 4
+#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
+#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
+#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
+#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
+#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
+#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
+#define reg_eth_rw_tr_ctrl_offset 32
+
+/* Register rw_clr_err, scope eth, type rw */
+#define reg_eth_rw_clr_err___clr___lsb 0
+#define reg_eth_rw_clr_err___clr___width 1
+#define reg_eth_rw_clr_err___clr___bit 0
+#define reg_eth_rw_clr_err_offset 36
+
+/* Register rw_mgm_ctrl, scope eth, type rw */
+#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
+#define reg_eth_rw_mgm_ctrl___mdio___width 1
+#define reg_eth_rw_mgm_ctrl___mdio___bit 0
+#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
+#define reg_eth_rw_mgm_ctrl___mdoe___width 1
+#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
+#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
+#define reg_eth_rw_mgm_ctrl___mdc___width 1
+#define reg_eth_rw_mgm_ctrl___mdc___bit 2
+#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
+#define reg_eth_rw_mgm_ctrl___phyclk___width 1
+#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
+#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
+#define reg_eth_rw_mgm_ctrl___txdata___width 4
+#define reg_eth_rw_mgm_ctrl___txen___lsb 8
+#define reg_eth_rw_mgm_ctrl___txen___width 1
+#define reg_eth_rw_mgm_ctrl___txen___bit 8
+#define reg_eth_rw_mgm_ctrl_offset 40
+
+/* Register r_stat, scope eth, type r */
+#define reg_eth_r_stat___mdio___lsb 0
+#define reg_eth_r_stat___mdio___width 1
+#define reg_eth_r_stat___mdio___bit 0
+#define reg_eth_r_stat___exc_col___lsb 1
+#define reg_eth_r_stat___exc_col___width 1
+#define reg_eth_r_stat___exc_col___bit 1
+#define reg_eth_r_stat___urun___lsb 2
+#define reg_eth_r_stat___urun___width 1
+#define reg_eth_r_stat___urun___bit 2
+#define reg_eth_r_stat___phyclk___lsb 3
+#define reg_eth_r_stat___phyclk___width 1
+#define reg_eth_r_stat___phyclk___bit 3
+#define reg_eth_r_stat___txdata___lsb 4
+#define reg_eth_r_stat___txdata___width 4
+#define reg_eth_r_stat___txen___lsb 8
+#define reg_eth_r_stat___txen___width 1
+#define reg_eth_r_stat___txen___bit 8
+#define reg_eth_r_stat___col___lsb 9
+#define reg_eth_r_stat___col___width 1
+#define reg_eth_r_stat___col___bit 9
+#define reg_eth_r_stat___crs___lsb 10
+#define reg_eth_r_stat___crs___width 1
+#define reg_eth_r_stat___crs___bit 10
+#define reg_eth_r_stat___txclk___lsb 11
+#define reg_eth_r_stat___txclk___width 1
+#define reg_eth_r_stat___txclk___bit 11
+#define reg_eth_r_stat___rxdata___lsb 12
+#define reg_eth_r_stat___rxdata___width 4
+#define reg_eth_r_stat___rxer___lsb 16
+#define reg_eth_r_stat___rxer___width 1
+#define reg_eth_r_stat___rxer___bit 16
+#define reg_eth_r_stat___rxdv___lsb 17
+#define reg_eth_r_stat___rxdv___width 1
+#define reg_eth_r_stat___rxdv___bit 17
+#define reg_eth_r_stat___rxclk___lsb 18
+#define reg_eth_r_stat___rxclk___width 1
+#define reg_eth_r_stat___rxclk___bit 18
+#define reg_eth_r_stat_offset 44
+
+/* Register rs_rec_cnt, scope eth, type rs */
+#define reg_eth_rs_rec_cnt___crc_err___lsb 0
+#define reg_eth_rs_rec_cnt___crc_err___width 8
+#define reg_eth_rs_rec_cnt___align_err___lsb 8
+#define reg_eth_rs_rec_cnt___align_err___width 8
+#define reg_eth_rs_rec_cnt___oversize___lsb 16
+#define reg_eth_rs_rec_cnt___oversize___width 8
+#define reg_eth_rs_rec_cnt___congestion___lsb 24
+#define reg_eth_rs_rec_cnt___congestion___width 8
+#define reg_eth_rs_rec_cnt_offset 48
+
+/* Register r_rec_cnt, scope eth, type r */
+#define reg_eth_r_rec_cnt___crc_err___lsb 0
+#define reg_eth_r_rec_cnt___crc_err___width 8
+#define reg_eth_r_rec_cnt___align_err___lsb 8
+#define reg_eth_r_rec_cnt___align_err___width 8
+#define reg_eth_r_rec_cnt___oversize___lsb 16
+#define reg_eth_r_rec_cnt___oversize___width 8
+#define reg_eth_r_rec_cnt___congestion___lsb 24
+#define reg_eth_r_rec_cnt___congestion___width 8
+#define reg_eth_r_rec_cnt_offset 52
+
+/* Register rs_tr_cnt, scope eth, type rs */
+#define reg_eth_rs_tr_cnt___single_col___lsb 0
+#define reg_eth_rs_tr_cnt___single_col___width 8
+#define reg_eth_rs_tr_cnt___mult_col___lsb 8
+#define reg_eth_rs_tr_cnt___mult_col___width 8
+#define reg_eth_rs_tr_cnt___late_col___lsb 16
+#define reg_eth_rs_tr_cnt___late_col___width 8
+#define reg_eth_rs_tr_cnt___deferred___lsb 24
+#define reg_eth_rs_tr_cnt___deferred___width 8
+#define reg_eth_rs_tr_cnt_offset 56
+
+/* Register r_tr_cnt, scope eth, type r */
+#define reg_eth_r_tr_cnt___single_col___lsb 0
+#define reg_eth_r_tr_cnt___single_col___width 8
+#define reg_eth_r_tr_cnt___mult_col___lsb 8
+#define reg_eth_r_tr_cnt___mult_col___width 8
+#define reg_eth_r_tr_cnt___late_col___lsb 16
+#define reg_eth_r_tr_cnt___late_col___width 8
+#define reg_eth_r_tr_cnt___deferred___lsb 24
+#define reg_eth_r_tr_cnt___deferred___width 8
+#define reg_eth_r_tr_cnt_offset 60
+
+/* Register rs_phy_cnt, scope eth, type rs */
+#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
+#define reg_eth_rs_phy_cnt___carrier_loss___width 8
+#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
+#define reg_eth_rs_phy_cnt___sqe_err___width 8
+#define reg_eth_rs_phy_cnt_offset 64
+
+/* Register r_phy_cnt, scope eth, type r */
+#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
+#define reg_eth_r_phy_cnt___carrier_loss___width 8
+#define reg_eth_r_phy_cnt___sqe_err___lsb 8
+#define reg_eth_r_phy_cnt___sqe_err___width 8
+#define reg_eth_r_phy_cnt_offset 68
+
+/* Register rw_test_ctrl, scope eth, type rw */
+#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
+#define reg_eth_rw_test_ctrl___snmp_inc___width 1
+#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
+#define reg_eth_rw_test_ctrl___snmp___lsb 1
+#define reg_eth_rw_test_ctrl___snmp___width 1
+#define reg_eth_rw_test_ctrl___snmp___bit 1
+#define reg_eth_rw_test_ctrl___backoff___lsb 2
+#define reg_eth_rw_test_ctrl___backoff___width 1
+#define reg_eth_rw_test_ctrl___backoff___bit 2
+#define reg_eth_rw_test_ctrl_offset 72
+
+/* Register rw_intr_mask, scope eth, type rw */
+#define reg_eth_rw_intr_mask___crc___lsb 0
+#define reg_eth_rw_intr_mask___crc___width 1
+#define reg_eth_rw_intr_mask___crc___bit 0
+#define reg_eth_rw_intr_mask___align___lsb 1
+#define reg_eth_rw_intr_mask___align___width 1
+#define reg_eth_rw_intr_mask___align___bit 1
+#define reg_eth_rw_intr_mask___oversize___lsb 2
+#define reg_eth_rw_intr_mask___oversize___width 1
+#define reg_eth_rw_intr_mask___oversize___bit 2
+#define reg_eth_rw_intr_mask___congestion___lsb 3
+#define reg_eth_rw_intr_mask___congestion___width 1
+#define reg_eth_rw_intr_mask___congestion___bit 3
+#define reg_eth_rw_intr_mask___single_col___lsb 4
+#define reg_eth_rw_intr_mask___single_col___width 1
+#define reg_eth_rw_intr_mask___single_col___bit 4
+#define reg_eth_rw_intr_mask___mult_col___lsb 5
+#define reg_eth_rw_intr_mask___mult_col___width 1
+#define reg_eth_rw_intr_mask___mult_col___bit 5
+#define reg_eth_rw_intr_mask___late_col___lsb 6
+#define reg_eth_rw_intr_mask___late_col___width 1
+#define reg_eth_rw_intr_mask___late_col___bit 6
+#define reg_eth_rw_intr_mask___deferred___lsb 7
+#define reg_eth_rw_intr_mask___deferred___width 1
+#define reg_eth_rw_intr_mask___deferred___bit 7
+#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
+#define reg_eth_rw_intr_mask___carrier_loss___width 1
+#define reg_eth_rw_intr_mask___carrier_loss___bit 8
+#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
+#define reg_eth_rw_intr_mask___sqe_test_err___width 1
+#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
+#define reg_eth_rw_intr_mask___orun___lsb 10
+#define reg_eth_rw_intr_mask___orun___width 1
+#define reg_eth_rw_intr_mask___orun___bit 10
+#define reg_eth_rw_intr_mask___urun___lsb 11
+#define reg_eth_rw_intr_mask___urun___width 1
+#define reg_eth_rw_intr_mask___urun___bit 11
+#define reg_eth_rw_intr_mask___excessive_col___lsb 12
+#define reg_eth_rw_intr_mask___excessive_col___width 1
+#define reg_eth_rw_intr_mask___excessive_col___bit 12
+#define reg_eth_rw_intr_mask___mdio___lsb 13
+#define reg_eth_rw_intr_mask___mdio___width 1
+#define reg_eth_rw_intr_mask___mdio___bit 13
+#define reg_eth_rw_intr_mask_offset 76
+
+/* Register rw_ack_intr, scope eth, type rw */
+#define reg_eth_rw_ack_intr___crc___lsb 0
+#define reg_eth_rw_ack_intr___crc___width 1
+#define reg_eth_rw_ack_intr___crc___bit 0
+#define reg_eth_rw_ack_intr___align___lsb 1
+#define reg_eth_rw_ack_intr___align___width 1
+#define reg_eth_rw_ack_intr___align___bit 1
+#define reg_eth_rw_ack_intr___oversize___lsb 2
+#define reg_eth_rw_ack_intr___oversize___width 1
+#define reg_eth_rw_ack_intr___oversize___bit 2
+#define reg_eth_rw_ack_intr___congestion___lsb 3
+#define reg_eth_rw_ack_intr___congestion___width 1
+#define reg_eth_rw_ack_intr___congestion___bit 3
+#define reg_eth_rw_ack_intr___single_col___lsb 4
+#define reg_eth_rw_ack_intr___single_col___width 1
+#define reg_eth_rw_ack_intr___single_col___bit 4
+#define reg_eth_rw_ack_intr___mult_col___lsb 5
+#define reg_eth_rw_ack_intr___mult_col___width 1
+#define reg_eth_rw_ack_intr___mult_col___bit 5
+#define reg_eth_rw_ack_intr___late_col___lsb 6
+#define reg_eth_rw_ack_intr___late_col___width 1
+#define reg_eth_rw_ack_intr___late_col___bit 6
+#define reg_eth_rw_ack_intr___deferred___lsb 7
+#define reg_eth_rw_ack_intr___deferred___width 1
+#define reg_eth_rw_ack_intr___deferred___bit 7
+#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
+#define reg_eth_rw_ack_intr___carrier_loss___width 1
+#define reg_eth_rw_ack_intr___carrier_loss___bit 8
+#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
+#define reg_eth_rw_ack_intr___sqe_test_err___width 1
+#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
+#define reg_eth_rw_ack_intr___orun___lsb 10
+#define reg_eth_rw_ack_intr___orun___width 1
+#define reg_eth_rw_ack_intr___orun___bit 10
+#define reg_eth_rw_ack_intr___urun___lsb 11
+#define reg_eth_rw_ack_intr___urun___width 1
+#define reg_eth_rw_ack_intr___urun___bit 11
+#define reg_eth_rw_ack_intr___excessive_col___lsb 12
+#define reg_eth_rw_ack_intr___excessive_col___width 1
+#define reg_eth_rw_ack_intr___excessive_col___bit 12
+#define reg_eth_rw_ack_intr___mdio___lsb 13
+#define reg_eth_rw_ack_intr___mdio___width 1
+#define reg_eth_rw_ack_intr___mdio___bit 13
+#define reg_eth_rw_ack_intr_offset 80
+
+/* Register r_intr, scope eth, type r */
+#define reg_eth_r_intr___crc___lsb 0
+#define reg_eth_r_intr___crc___width 1
+#define reg_eth_r_intr___crc___bit 0
+#define reg_eth_r_intr___align___lsb 1
+#define reg_eth_r_intr___align___width 1
+#define reg_eth_r_intr___align___bit 1
+#define reg_eth_r_intr___oversize___lsb 2
+#define reg_eth_r_intr___oversize___width 1
+#define reg_eth_r_intr___oversize___bit 2
+#define reg_eth_r_intr___congestion___lsb 3
+#define reg_eth_r_intr___congestion___width 1
+#define reg_eth_r_intr___congestion___bit 3
+#define reg_eth_r_intr___single_col___lsb 4
+#define reg_eth_r_intr___single_col___width 1
+#define reg_eth_r_intr___single_col___bit 4
+#define reg_eth_r_intr___mult_col___lsb 5
+#define reg_eth_r_intr___mult_col___width 1
+#define reg_eth_r_intr___mult_col___bit 5
+#define reg_eth_r_intr___late_col___lsb 6
+#define reg_eth_r_intr___late_col___width 1
+#define reg_eth_r_intr___late_col___bit 6
+#define reg_eth_r_intr___deferred___lsb 7
+#define reg_eth_r_intr___deferred___width 1
+#define reg_eth_r_intr___deferred___bit 7
+#define reg_eth_r_intr___carrier_loss___lsb 8
+#define reg_eth_r_intr___carrier_loss___width 1
+#define reg_eth_r_intr___carrier_loss___bit 8
+#define reg_eth_r_intr___sqe_test_err___lsb 9
+#define reg_eth_r_intr___sqe_test_err___width 1
+#define reg_eth_r_intr___sqe_test_err___bit 9
+#define reg_eth_r_intr___orun___lsb 10
+#define reg_eth_r_intr___orun___width 1
+#define reg_eth_r_intr___orun___bit 10
+#define reg_eth_r_intr___urun___lsb 11
+#define reg_eth_r_intr___urun___width 1
+#define reg_eth_r_intr___urun___bit 11
+#define reg_eth_r_intr___excessive_col___lsb 12
+#define reg_eth_r_intr___excessive_col___width 1
+#define reg_eth_r_intr___excessive_col___bit 12
+#define reg_eth_r_intr___mdio___lsb 13
+#define reg_eth_r_intr___mdio___width 1
+#define reg_eth_r_intr___mdio___bit 13
+#define reg_eth_r_intr_offset 84
+
+/* Register r_masked_intr, scope eth, type r */
+#define reg_eth_r_masked_intr___crc___lsb 0
+#define reg_eth_r_masked_intr___crc___width 1
+#define reg_eth_r_masked_intr___crc___bit 0
+#define reg_eth_r_masked_intr___align___lsb 1
+#define reg_eth_r_masked_intr___align___width 1
+#define reg_eth_r_masked_intr___align___bit 1
+#define reg_eth_r_masked_intr___oversize___lsb 2
+#define reg_eth_r_masked_intr___oversize___width 1
+#define reg_eth_r_masked_intr___oversize___bit 2
+#define reg_eth_r_masked_intr___congestion___lsb 3
+#define reg_eth_r_masked_intr___congestion___width 1
+#define reg_eth_r_masked_intr___congestion___bit 3
+#define reg_eth_r_masked_intr___single_col___lsb 4
+#define reg_eth_r_masked_intr___single_col___width 1
+#define reg_eth_r_masked_intr___single_col___bit 4
+#define reg_eth_r_masked_intr___mult_col___lsb 5
+#define reg_eth_r_masked_intr___mult_col___width 1
+#define reg_eth_r_masked_intr___mult_col___bit 5
+#define reg_eth_r_masked_intr___late_col___lsb 6
+#define reg_eth_r_masked_intr___late_col___width 1
+#define reg_eth_r_masked_intr___late_col___bit 6
+#define reg_eth_r_masked_intr___deferred___lsb 7
+#define reg_eth_r_masked_intr___deferred___width 1
+#define reg_eth_r_masked_intr___deferred___bit 7
+#define reg_eth_r_masked_intr___carrier_loss___lsb 8
+#define reg_eth_r_masked_intr___carrier_loss___width 1
+#define reg_eth_r_masked_intr___carrier_loss___bit 8
+#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
+#define reg_eth_r_masked_intr___sqe_test_err___width 1
+#define reg_eth_r_masked_intr___sqe_test_err___bit 9
+#define reg_eth_r_masked_intr___orun___lsb 10
+#define reg_eth_r_masked_intr___orun___width 1
+#define reg_eth_r_masked_intr___orun___bit 10
+#define reg_eth_r_masked_intr___urun___lsb 11
+#define reg_eth_r_masked_intr___urun___width 1
+#define reg_eth_r_masked_intr___urun___bit 11
+#define reg_eth_r_masked_intr___excessive_col___lsb 12
+#define reg_eth_r_masked_intr___excessive_col___width 1
+#define reg_eth_r_masked_intr___excessive_col___bit 12
+#define reg_eth_r_masked_intr___mdio___lsb 13
+#define reg_eth_r_masked_intr___mdio___width 1
+#define reg_eth_r_masked_intr___mdio___bit 13
+#define reg_eth_r_masked_intr_offset 88
+
+
+/* Constants */
+#define regk_eth_discard                          0x00000000
+#define regk_eth_ether                            0x00000000
+#define regk_eth_full                             0x00000001
+#define regk_eth_half                             0x00000000
+#define regk_eth_hsh                              0x00000001
+#define regk_eth_mii                              0x00000001
+#define regk_eth_mii_clk                          0x00000000
+#define regk_eth_mii_rec                          0x00000002
+#define regk_eth_no                               0x00000000
+#define regk_eth_rec                              0x00000001
+#define regk_eth_rw_ga_hi_default                 0x00000000
+#define regk_eth_rw_ga_lo_default                 0x00000000
+#define regk_eth_rw_gen_ctrl_default              0x00000000
+#define regk_eth_rw_intr_mask_default             0x00000000
+#define regk_eth_rw_ma0_hi_default                0x00000000
+#define regk_eth_rw_ma0_lo_default                0x00000000
+#define regk_eth_rw_ma1_hi_default                0x00000000
+#define regk_eth_rw_ma1_lo_default                0x00000000
+#define regk_eth_rw_mgm_ctrl_default              0x00000000
+#define regk_eth_rw_test_ctrl_default             0x00000000
+#define regk_eth_size1518                         0x00000000
+#define regk_eth_size1522                         0x00000001
+#define regk_eth_yes                              0x00000001
+#endif /* __eth_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
new file mode 100644
index 000000000000..35356bc08629
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
@@ -0,0 +1,276 @@
+#ifndef __gio_defs_asm_h
+#define __gio_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/gio/rtl/gio_regs.r
+ *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ *     last modfied: Mon Apr 11 16:07:47 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
+ *      id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa_dout, scope gio, type rw */
+#define reg_gio_rw_pa_dout___data___lsb 0
+#define reg_gio_rw_pa_dout___data___width 8
+#define reg_gio_rw_pa_dout_offset 0
+
+/* Register r_pa_din, scope gio, type r */
+#define reg_gio_r_pa_din___data___lsb 0
+#define reg_gio_r_pa_din___data___width 8
+#define reg_gio_r_pa_din_offset 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+#define reg_gio_rw_pa_oe___oe___lsb 0
+#define reg_gio_rw_pa_oe___oe___width 8
+#define reg_gio_rw_pa_oe_offset 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+#define reg_gio_rw_intr_cfg___pa0___lsb 0
+#define reg_gio_rw_intr_cfg___pa0___width 3
+#define reg_gio_rw_intr_cfg___pa1___lsb 3
+#define reg_gio_rw_intr_cfg___pa1___width 3
+#define reg_gio_rw_intr_cfg___pa2___lsb 6
+#define reg_gio_rw_intr_cfg___pa2___width 3
+#define reg_gio_rw_intr_cfg___pa3___lsb 9
+#define reg_gio_rw_intr_cfg___pa3___width 3
+#define reg_gio_rw_intr_cfg___pa4___lsb 12
+#define reg_gio_rw_intr_cfg___pa4___width 3
+#define reg_gio_rw_intr_cfg___pa5___lsb 15
+#define reg_gio_rw_intr_cfg___pa5___width 3
+#define reg_gio_rw_intr_cfg___pa6___lsb 18
+#define reg_gio_rw_intr_cfg___pa6___width 3
+#define reg_gio_rw_intr_cfg___pa7___lsb 21
+#define reg_gio_rw_intr_cfg___pa7___width 3
+#define reg_gio_rw_intr_cfg_offset 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+#define reg_gio_rw_intr_mask___pa0___lsb 0
+#define reg_gio_rw_intr_mask___pa0___width 1
+#define reg_gio_rw_intr_mask___pa0___bit 0
+#define reg_gio_rw_intr_mask___pa1___lsb 1
+#define reg_gio_rw_intr_mask___pa1___width 1
+#define reg_gio_rw_intr_mask___pa1___bit 1
+#define reg_gio_rw_intr_mask___pa2___lsb 2
+#define reg_gio_rw_intr_mask___pa2___width 1
+#define reg_gio_rw_intr_mask___pa2___bit 2
+#define reg_gio_rw_intr_mask___pa3___lsb 3
+#define reg_gio_rw_intr_mask___pa3___width 1
+#define reg_gio_rw_intr_mask___pa3___bit 3
+#define reg_gio_rw_intr_mask___pa4___lsb 4
+#define reg_gio_rw_intr_mask___pa4___width 1
+#define reg_gio_rw_intr_mask___pa4___bit 4
+#define reg_gio_rw_intr_mask___pa5___lsb 5
+#define reg_gio_rw_intr_mask___pa5___width 1
+#define reg_gio_rw_intr_mask___pa5___bit 5
+#define reg_gio_rw_intr_mask___pa6___lsb 6
+#define reg_gio_rw_intr_mask___pa6___width 1
+#define reg_gio_rw_intr_mask___pa6___bit 6
+#define reg_gio_rw_intr_mask___pa7___lsb 7
+#define reg_gio_rw_intr_mask___pa7___width 1
+#define reg_gio_rw_intr_mask___pa7___bit 7
+#define reg_gio_rw_intr_mask_offset 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+#define reg_gio_rw_ack_intr___pa0___lsb 0
+#define reg_gio_rw_ack_intr___pa0___width 1
+#define reg_gio_rw_ack_intr___pa0___bit 0
+#define reg_gio_rw_ack_intr___pa1___lsb 1
+#define reg_gio_rw_ack_intr___pa1___width 1
+#define reg_gio_rw_ack_intr___pa1___bit 1
+#define reg_gio_rw_ack_intr___pa2___lsb 2
+#define reg_gio_rw_ack_intr___pa2___width 1
+#define reg_gio_rw_ack_intr___pa2___bit 2
+#define reg_gio_rw_ack_intr___pa3___lsb 3
+#define reg_gio_rw_ack_intr___pa3___width 1
+#define reg_gio_rw_ack_intr___pa3___bit 3
+#define reg_gio_rw_ack_intr___pa4___lsb 4
+#define reg_gio_rw_ack_intr___pa4___width 1
+#define reg_gio_rw_ack_intr___pa4___bit 4
+#define reg_gio_rw_ack_intr___pa5___lsb 5
+#define reg_gio_rw_ack_intr___pa5___width 1
+#define reg_gio_rw_ack_intr___pa5___bit 5
+#define reg_gio_rw_ack_intr___pa6___lsb 6
+#define reg_gio_rw_ack_intr___pa6___width 1
+#define reg_gio_rw_ack_intr___pa6___bit 6
+#define reg_gio_rw_ack_intr___pa7___lsb 7
+#define reg_gio_rw_ack_intr___pa7___width 1
+#define reg_gio_rw_ack_intr___pa7___bit 7
+#define reg_gio_rw_ack_intr_offset 20
+
+/* Register r_intr, scope gio, type r */
+#define reg_gio_r_intr___pa0___lsb 0
+#define reg_gio_r_intr___pa0___width 1
+#define reg_gio_r_intr___pa0___bit 0
+#define reg_gio_r_intr___pa1___lsb 1
+#define reg_gio_r_intr___pa1___width 1
+#define reg_gio_r_intr___pa1___bit 1
+#define reg_gio_r_intr___pa2___lsb 2
+#define reg_gio_r_intr___pa2___width 1
+#define reg_gio_r_intr___pa2___bit 2
+#define reg_gio_r_intr___pa3___lsb 3
+#define reg_gio_r_intr___pa3___width 1
+#define reg_gio_r_intr___pa3___bit 3
+#define reg_gio_r_intr___pa4___lsb 4
+#define reg_gio_r_intr___pa4___width 1
+#define reg_gio_r_intr___pa4___bit 4
+#define reg_gio_r_intr___pa5___lsb 5
+#define reg_gio_r_intr___pa5___width 1
+#define reg_gio_r_intr___pa5___bit 5
+#define reg_gio_r_intr___pa6___lsb 6
+#define reg_gio_r_intr___pa6___width 1
+#define reg_gio_r_intr___pa6___bit 6
+#define reg_gio_r_intr___pa7___lsb 7
+#define reg_gio_r_intr___pa7___width 1
+#define reg_gio_r_intr___pa7___bit 7
+#define reg_gio_r_intr_offset 24
+
+/* Register r_masked_intr, scope gio, type r */
+#define reg_gio_r_masked_intr___pa0___lsb 0
+#define reg_gio_r_masked_intr___pa0___width 1
+#define reg_gio_r_masked_intr___pa0___bit 0
+#define reg_gio_r_masked_intr___pa1___lsb 1
+#define reg_gio_r_masked_intr___pa1___width 1
+#define reg_gio_r_masked_intr___pa1___bit 1
+#define reg_gio_r_masked_intr___pa2___lsb 2
+#define reg_gio_r_masked_intr___pa2___width 1
+#define reg_gio_r_masked_intr___pa2___bit 2
+#define reg_gio_r_masked_intr___pa3___lsb 3
+#define reg_gio_r_masked_intr___pa3___width 1
+#define reg_gio_r_masked_intr___pa3___bit 3
+#define reg_gio_r_masked_intr___pa4___lsb 4
+#define reg_gio_r_masked_intr___pa4___width 1
+#define reg_gio_r_masked_intr___pa4___bit 4
+#define reg_gio_r_masked_intr___pa5___lsb 5
+#define reg_gio_r_masked_intr___pa5___width 1
+#define reg_gio_r_masked_intr___pa5___bit 5
+#define reg_gio_r_masked_intr___pa6___lsb 6
+#define reg_gio_r_masked_intr___pa6___width 1
+#define reg_gio_r_masked_intr___pa6___bit 6
+#define reg_gio_r_masked_intr___pa7___lsb 7
+#define reg_gio_r_masked_intr___pa7___width 1
+#define reg_gio_r_masked_intr___pa7___bit 7
+#define reg_gio_r_masked_intr_offset 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+#define reg_gio_rw_pb_dout___data___lsb 0
+#define reg_gio_rw_pb_dout___data___width 18
+#define reg_gio_rw_pb_dout_offset 32
+
+/* Register r_pb_din, scope gio, type r */
+#define reg_gio_r_pb_din___data___lsb 0
+#define reg_gio_r_pb_din___data___width 18
+#define reg_gio_r_pb_din_offset 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+#define reg_gio_rw_pb_oe___oe___lsb 0
+#define reg_gio_rw_pb_oe___oe___width 18
+#define reg_gio_rw_pb_oe_offset 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+#define reg_gio_rw_pc_dout___data___lsb 0
+#define reg_gio_rw_pc_dout___data___width 18
+#define reg_gio_rw_pc_dout_offset 48
+
+/* Register r_pc_din, scope gio, type r */
+#define reg_gio_r_pc_din___data___lsb 0
+#define reg_gio_r_pc_din___data___width 18
+#define reg_gio_r_pc_din_offset 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+#define reg_gio_rw_pc_oe___oe___lsb 0
+#define reg_gio_rw_pc_oe___oe___width 18
+#define reg_gio_rw_pc_oe_offset 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+#define reg_gio_rw_pd_dout___data___lsb 0
+#define reg_gio_rw_pd_dout___data___width 18
+#define reg_gio_rw_pd_dout_offset 64
+
+/* Register r_pd_din, scope gio, type r */
+#define reg_gio_r_pd_din___data___lsb 0
+#define reg_gio_r_pd_din___data___width 18
+#define reg_gio_r_pd_din_offset 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+#define reg_gio_rw_pd_oe___oe___lsb 0
+#define reg_gio_rw_pd_oe___oe___width 18
+#define reg_gio_rw_pd_oe_offset 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+#define reg_gio_rw_pe_dout___data___lsb 0
+#define reg_gio_rw_pe_dout___data___width 18
+#define reg_gio_rw_pe_dout_offset 80
+
+/* Register r_pe_din, scope gio, type r */
+#define reg_gio_r_pe_din___data___lsb 0
+#define reg_gio_r_pe_din___data___width 18
+#define reg_gio_r_pe_din_offset 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+#define reg_gio_rw_pe_oe___oe___lsb 0
+#define reg_gio_rw_pe_oe___oe___width 18
+#define reg_gio_rw_pe_oe_offset 88
+
+
+/* Constants */
+#define regk_gio_anyedge                          0x00000007
+#define regk_gio_hi                               0x00000001
+#define regk_gio_lo                               0x00000002
+#define regk_gio_negedge                          0x00000006
+#define regk_gio_no                               0x00000000
+#define regk_gio_off                              0x00000000
+#define regk_gio_posedge                          0x00000005
+#define regk_gio_rw_intr_cfg_default              0x00000000
+#define regk_gio_rw_intr_mask_default             0x00000000
+#define regk_gio_rw_pa_oe_default                 0x00000000
+#define regk_gio_rw_pb_oe_default                 0x00000000
+#define regk_gio_rw_pc_oe_default                 0x00000000
+#define regk_gio_rw_pd_oe_default                 0x00000000
+#define regk_gio_rw_pe_oe_default                 0x00000000
+#define regk_gio_set                              0x00000003
+#define regk_gio_yes                              0x00000001
+#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
new file mode 100644
index 000000000000..c8315905c571
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
@@ -0,0 +1,38 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+version . */
+
+#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define MEMARB_INTR_VECT        0x31
+#define GEN_IO_INTR_VECT        0x32
+#define IOP0_INTR_VECT  0x33
+#define IOP1_INTR_VECT  0x34
+#define IOP2_INTR_VECT  0x35
+#define IOP3_INTR_VECT  0x36
+#define DMA0_INTR_VECT  0x37
+#define DMA1_INTR_VECT  0x38
+#define DMA2_INTR_VECT  0x39
+#define DMA3_INTR_VECT  0x3a
+#define DMA4_INTR_VECT  0x3b
+#define DMA5_INTR_VECT  0x3c
+#define DMA6_INTR_VECT  0x3d
+#define DMA7_INTR_VECT  0x3e
+#define DMA8_INTR_VECT  0x3f
+#define DMA9_INTR_VECT  0x40
+#define ATA_INTR_VECT   0x41
+#define SSER0_INTR_VECT 0x42
+#define SSER1_INTR_VECT 0x43
+#define SER0_INTR_VECT  0x44
+#define SER1_INTR_VECT  0x45
+#define SER2_INTR_VECT  0x46
+#define SER3_INTR_VECT  0x47
+#define P21_INTR_VECT   0x48
+#define ETH0_INTR_VECT  0x49
+#define ETH1_INTR_VECT  0x4a
+#define TIMER_INTR_VECT 0x4b
+#define BIF_ARB_INTR_VECT       0x4c
+#define BIF_DMA_INTR_VECT       0x4d
+#define EXT_INTR_VECT   0x4e
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
new file mode 100644
index 000000000000..6df2a433b02d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
@@ -0,0 +1,355 @@
+#ifndef __intr_vect_defs_asm_h
+#define __intr_vect_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
+ *     last modfied: Mon Apr 11 16:08:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *      id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mask, scope intr_vect, type rw */
+#define reg_intr_vect_rw_mask___memarb___lsb 0
+#define reg_intr_vect_rw_mask___memarb___width 1
+#define reg_intr_vect_rw_mask___memarb___bit 0
+#define reg_intr_vect_rw_mask___gen_io___lsb 1
+#define reg_intr_vect_rw_mask___gen_io___width 1
+#define reg_intr_vect_rw_mask___gen_io___bit 1
+#define reg_intr_vect_rw_mask___iop0___lsb 2
+#define reg_intr_vect_rw_mask___iop0___width 1
+#define reg_intr_vect_rw_mask___iop0___bit 2
+#define reg_intr_vect_rw_mask___iop1___lsb 3
+#define reg_intr_vect_rw_mask___iop1___width 1
+#define reg_intr_vect_rw_mask___iop1___bit 3
+#define reg_intr_vect_rw_mask___iop2___lsb 4
+#define reg_intr_vect_rw_mask___iop2___width 1
+#define reg_intr_vect_rw_mask___iop2___bit 4
+#define reg_intr_vect_rw_mask___iop3___lsb 5
+#define reg_intr_vect_rw_mask___iop3___width 1
+#define reg_intr_vect_rw_mask___iop3___bit 5
+#define reg_intr_vect_rw_mask___dma0___lsb 6
+#define reg_intr_vect_rw_mask___dma0___width 1
+#define reg_intr_vect_rw_mask___dma0___bit 6
+#define reg_intr_vect_rw_mask___dma1___lsb 7
+#define reg_intr_vect_rw_mask___dma1___width 1
+#define reg_intr_vect_rw_mask___dma1___bit 7
+#define reg_intr_vect_rw_mask___dma2___lsb 8
+#define reg_intr_vect_rw_mask___dma2___width 1
+#define reg_intr_vect_rw_mask___dma2___bit 8
+#define reg_intr_vect_rw_mask___dma3___lsb 9
+#define reg_intr_vect_rw_mask___dma3___width 1
+#define reg_intr_vect_rw_mask___dma3___bit 9
+#define reg_intr_vect_rw_mask___dma4___lsb 10
+#define reg_intr_vect_rw_mask___dma4___width 1
+#define reg_intr_vect_rw_mask___dma4___bit 10
+#define reg_intr_vect_rw_mask___dma5___lsb 11
+#define reg_intr_vect_rw_mask___dma5___width 1
+#define reg_intr_vect_rw_mask___dma5___bit 11
+#define reg_intr_vect_rw_mask___dma6___lsb 12
+#define reg_intr_vect_rw_mask___dma6___width 1
+#define reg_intr_vect_rw_mask___dma6___bit 12
+#define reg_intr_vect_rw_mask___dma7___lsb 13
+#define reg_intr_vect_rw_mask___dma7___width 1
+#define reg_intr_vect_rw_mask___dma7___bit 13
+#define reg_intr_vect_rw_mask___dma8___lsb 14
+#define reg_intr_vect_rw_mask___dma8___width 1
+#define reg_intr_vect_rw_mask___dma8___bit 14
+#define reg_intr_vect_rw_mask___dma9___lsb 15
+#define reg_intr_vect_rw_mask___dma9___width 1
+#define reg_intr_vect_rw_mask___dma9___bit 15
+#define reg_intr_vect_rw_mask___ata___lsb 16
+#define reg_intr_vect_rw_mask___ata___width 1
+#define reg_intr_vect_rw_mask___ata___bit 16
+#define reg_intr_vect_rw_mask___sser0___lsb 17
+#define reg_intr_vect_rw_mask___sser0___width 1
+#define reg_intr_vect_rw_mask___sser0___bit 17
+#define reg_intr_vect_rw_mask___sser1___lsb 18
+#define reg_intr_vect_rw_mask___sser1___width 1
+#define reg_intr_vect_rw_mask___sser1___bit 18
+#define reg_intr_vect_rw_mask___ser0___lsb 19
+#define reg_intr_vect_rw_mask___ser0___width 1
+#define reg_intr_vect_rw_mask___ser0___bit 19
+#define reg_intr_vect_rw_mask___ser1___lsb 20
+#define reg_intr_vect_rw_mask___ser1___width 1
+#define reg_intr_vect_rw_mask___ser1___bit 20
+#define reg_intr_vect_rw_mask___ser2___lsb 21
+#define reg_intr_vect_rw_mask___ser2___width 1
+#define reg_intr_vect_rw_mask___ser2___bit 21
+#define reg_intr_vect_rw_mask___ser3___lsb 22
+#define reg_intr_vect_rw_mask___ser3___width 1
+#define reg_intr_vect_rw_mask___ser3___bit 22
+#define reg_intr_vect_rw_mask___p21___lsb 23
+#define reg_intr_vect_rw_mask___p21___width 1
+#define reg_intr_vect_rw_mask___p21___bit 23
+#define reg_intr_vect_rw_mask___eth0___lsb 24
+#define reg_intr_vect_rw_mask___eth0___width 1
+#define reg_intr_vect_rw_mask___eth0___bit 24
+#define reg_intr_vect_rw_mask___eth1___lsb 25
+#define reg_intr_vect_rw_mask___eth1___width 1
+#define reg_intr_vect_rw_mask___eth1___bit 25
+#define reg_intr_vect_rw_mask___timer___lsb 26
+#define reg_intr_vect_rw_mask___timer___width 1
+#define reg_intr_vect_rw_mask___timer___bit 26
+#define reg_intr_vect_rw_mask___bif_arb___lsb 27
+#define reg_intr_vect_rw_mask___bif_arb___width 1
+#define reg_intr_vect_rw_mask___bif_arb___bit 27
+#define reg_intr_vect_rw_mask___bif_dma___lsb 28
+#define reg_intr_vect_rw_mask___bif_dma___width 1
+#define reg_intr_vect_rw_mask___bif_dma___bit 28
+#define reg_intr_vect_rw_mask___ext___lsb 29
+#define reg_intr_vect_rw_mask___ext___width 1
+#define reg_intr_vect_rw_mask___ext___bit 29
+#define reg_intr_vect_rw_mask_offset 0
+
+/* Register r_vect, scope intr_vect, type r */
+#define reg_intr_vect_r_vect___memarb___lsb 0
+#define reg_intr_vect_r_vect___memarb___width 1
+#define reg_intr_vect_r_vect___memarb___bit 0
+#define reg_intr_vect_r_vect___gen_io___lsb 1
+#define reg_intr_vect_r_vect___gen_io___width 1
+#define reg_intr_vect_r_vect___gen_io___bit 1
+#define reg_intr_vect_r_vect___iop0___lsb 2
+#define reg_intr_vect_r_vect___iop0___width 1
+#define reg_intr_vect_r_vect___iop0___bit 2
+#define reg_intr_vect_r_vect___iop1___lsb 3
+#define reg_intr_vect_r_vect___iop1___width 1
+#define reg_intr_vect_r_vect___iop1___bit 3
+#define reg_intr_vect_r_vect___iop2___lsb 4
+#define reg_intr_vect_r_vect___iop2___width 1
+#define reg_intr_vect_r_vect___iop2___bit 4
+#define reg_intr_vect_r_vect___iop3___lsb 5
+#define reg_intr_vect_r_vect___iop3___width 1
+#define reg_intr_vect_r_vect___iop3___bit 5
+#define reg_intr_vect_r_vect___dma0___lsb 6
+#define reg_intr_vect_r_vect___dma0___width 1
+#define reg_intr_vect_r_vect___dma0___bit 6
+#define reg_intr_vect_r_vect___dma1___lsb 7
+#define reg_intr_vect_r_vect___dma1___width 1
+#define reg_intr_vect_r_vect___dma1___bit 7
+#define reg_intr_vect_r_vect___dma2___lsb 8
+#define reg_intr_vect_r_vect___dma2___width 1
+#define reg_intr_vect_r_vect___dma2___bit 8
+#define reg_intr_vect_r_vect___dma3___lsb 9
+#define reg_intr_vect_r_vect___dma3___width 1
+#define reg_intr_vect_r_vect___dma3___bit 9
+#define reg_intr_vect_r_vect___dma4___lsb 10
+#define reg_intr_vect_r_vect___dma4___width 1
+#define reg_intr_vect_r_vect___dma4___bit 10
+#define reg_intr_vect_r_vect___dma5___lsb 11
+#define reg_intr_vect_r_vect___dma5___width 1
+#define reg_intr_vect_r_vect___dma5___bit 11
+#define reg_intr_vect_r_vect___dma6___lsb 12
+#define reg_intr_vect_r_vect___dma6___width 1
+#define reg_intr_vect_r_vect___dma6___bit 12
+#define reg_intr_vect_r_vect___dma7___lsb 13
+#define reg_intr_vect_r_vect___dma7___width 1
+#define reg_intr_vect_r_vect___dma7___bit 13
+#define reg_intr_vect_r_vect___dma8___lsb 14
+#define reg_intr_vect_r_vect___dma8___width 1
+#define reg_intr_vect_r_vect___dma8___bit 14
+#define reg_intr_vect_r_vect___dma9___lsb 15
+#define reg_intr_vect_r_vect___dma9___width 1
+#define reg_intr_vect_r_vect___dma9___bit 15
+#define reg_intr_vect_r_vect___ata___lsb 16
+#define reg_intr_vect_r_vect___ata___width 1
+#define reg_intr_vect_r_vect___ata___bit 16
+#define reg_intr_vect_r_vect___sser0___lsb 17
+#define reg_intr_vect_r_vect___sser0___width 1
+#define reg_intr_vect_r_vect___sser0___bit 17
+#define reg_intr_vect_r_vect___sser1___lsb 18
+#define reg_intr_vect_r_vect___sser1___width 1
+#define reg_intr_vect_r_vect___sser1___bit 18
+#define reg_intr_vect_r_vect___ser0___lsb 19
+#define reg_intr_vect_r_vect___ser0___width 1
+#define reg_intr_vect_r_vect___ser0___bit 19
+#define reg_intr_vect_r_vect___ser1___lsb 20
+#define reg_intr_vect_r_vect___ser1___width 1
+#define reg_intr_vect_r_vect___ser1___bit 20
+#define reg_intr_vect_r_vect___ser2___lsb 21
+#define reg_intr_vect_r_vect___ser2___width 1
+#define reg_intr_vect_r_vect___ser2___bit 21
+#define reg_intr_vect_r_vect___ser3___lsb 22
+#define reg_intr_vect_r_vect___ser3___width 1
+#define reg_intr_vect_r_vect___ser3___bit 22
+#define reg_intr_vect_r_vect___p21___lsb 23
+#define reg_intr_vect_r_vect___p21___width 1
+#define reg_intr_vect_r_vect___p21___bit 23
+#define reg_intr_vect_r_vect___eth0___lsb 24
+#define reg_intr_vect_r_vect___eth0___width 1
+#define reg_intr_vect_r_vect___eth0___bit 24
+#define reg_intr_vect_r_vect___eth1___lsb 25
+#define reg_intr_vect_r_vect___eth1___width 1
+#define reg_intr_vect_r_vect___eth1___bit 25
+#define reg_intr_vect_r_vect___timer___lsb 26
+#define reg_intr_vect_r_vect___timer___width 1
+#define reg_intr_vect_r_vect___timer___bit 26
+#define reg_intr_vect_r_vect___bif_arb___lsb 27
+#define reg_intr_vect_r_vect___bif_arb___width 1
+#define reg_intr_vect_r_vect___bif_arb___bit 27
+#define reg_intr_vect_r_vect___bif_dma___lsb 28
+#define reg_intr_vect_r_vect___bif_dma___width 1
+#define reg_intr_vect_r_vect___bif_dma___bit 28
+#define reg_intr_vect_r_vect___ext___lsb 29
+#define reg_intr_vect_r_vect___ext___width 1
+#define reg_intr_vect_r_vect___ext___bit 29
+#define reg_intr_vect_r_vect_offset 4
+
+/* Register r_masked_vect, scope intr_vect, type r */
+#define reg_intr_vect_r_masked_vect___memarb___lsb 0
+#define reg_intr_vect_r_masked_vect___memarb___width 1
+#define reg_intr_vect_r_masked_vect___memarb___bit 0
+#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
+#define reg_intr_vect_r_masked_vect___gen_io___width 1
+#define reg_intr_vect_r_masked_vect___gen_io___bit 1
+#define reg_intr_vect_r_masked_vect___iop0___lsb 2
+#define reg_intr_vect_r_masked_vect___iop0___width 1
+#define reg_intr_vect_r_masked_vect___iop0___bit 2
+#define reg_intr_vect_r_masked_vect___iop1___lsb 3
+#define reg_intr_vect_r_masked_vect___iop1___width 1
+#define reg_intr_vect_r_masked_vect___iop1___bit 3
+#define reg_intr_vect_r_masked_vect___iop2___lsb 4
+#define reg_intr_vect_r_masked_vect___iop2___width 1
+#define reg_intr_vect_r_masked_vect___iop2___bit 4
+#define reg_intr_vect_r_masked_vect___iop3___lsb 5
+#define reg_intr_vect_r_masked_vect___iop3___width 1
+#define reg_intr_vect_r_masked_vect___iop3___bit 5
+#define reg_intr_vect_r_masked_vect___dma0___lsb 6
+#define reg_intr_vect_r_masked_vect___dma0___width 1
+#define reg_intr_vect_r_masked_vect___dma0___bit 6
+#define reg_intr_vect_r_masked_vect___dma1___lsb 7
+#define reg_intr_vect_r_masked_vect___dma1___width 1
+#define reg_intr_vect_r_masked_vect___dma1___bit 7
+#define reg_intr_vect_r_masked_vect___dma2___lsb 8
+#define reg_intr_vect_r_masked_vect___dma2___width 1
+#define reg_intr_vect_r_masked_vect___dma2___bit 8
+#define reg_intr_vect_r_masked_vect___dma3___lsb 9
+#define reg_intr_vect_r_masked_vect___dma3___width 1
+#define reg_intr_vect_r_masked_vect___dma3___bit 9
+#define reg_intr_vect_r_masked_vect___dma4___lsb 10
+#define reg_intr_vect_r_masked_vect___dma4___width 1
+#define reg_intr_vect_r_masked_vect___dma4___bit 10
+#define reg_intr_vect_r_masked_vect___dma5___lsb 11
+#define reg_intr_vect_r_masked_vect___dma5___width 1
+#define reg_intr_vect_r_masked_vect___dma5___bit 11
+#define reg_intr_vect_r_masked_vect___dma6___lsb 12
+#define reg_intr_vect_r_masked_vect___dma6___width 1
+#define reg_intr_vect_r_masked_vect___dma6___bit 12
+#define reg_intr_vect_r_masked_vect___dma7___lsb 13
+#define reg_intr_vect_r_masked_vect___dma7___width 1
+#define reg_intr_vect_r_masked_vect___dma7___bit 13
+#define reg_intr_vect_r_masked_vect___dma8___lsb 14
+#define reg_intr_vect_r_masked_vect___dma8___width 1
+#define reg_intr_vect_r_masked_vect___dma8___bit 14
+#define reg_intr_vect_r_masked_vect___dma9___lsb 15
+#define reg_intr_vect_r_masked_vect___dma9___width 1
+#define reg_intr_vect_r_masked_vect___dma9___bit 15
+#define reg_intr_vect_r_masked_vect___ata___lsb 16
+#define reg_intr_vect_r_masked_vect___ata___width 1
+#define reg_intr_vect_r_masked_vect___ata___bit 16
+#define reg_intr_vect_r_masked_vect___sser0___lsb 17
+#define reg_intr_vect_r_masked_vect___sser0___width 1
+#define reg_intr_vect_r_masked_vect___sser0___bit 17
+#define reg_intr_vect_r_masked_vect___sser1___lsb 18
+#define reg_intr_vect_r_masked_vect___sser1___width 1
+#define reg_intr_vect_r_masked_vect___sser1___bit 18
+#define reg_intr_vect_r_masked_vect___ser0___lsb 19
+#define reg_intr_vect_r_masked_vect___ser0___width 1
+#define reg_intr_vect_r_masked_vect___ser0___bit 19
+#define reg_intr_vect_r_masked_vect___ser1___lsb 20
+#define reg_intr_vect_r_masked_vect___ser1___width 1
+#define reg_intr_vect_r_masked_vect___ser1___bit 20
+#define reg_intr_vect_r_masked_vect___ser2___lsb 21
+#define reg_intr_vect_r_masked_vect___ser2___width 1
+#define reg_intr_vect_r_masked_vect___ser2___bit 21
+#define reg_intr_vect_r_masked_vect___ser3___lsb 22
+#define reg_intr_vect_r_masked_vect___ser3___width 1
+#define reg_intr_vect_r_masked_vect___ser3___bit 22
+#define reg_intr_vect_r_masked_vect___p21___lsb 23
+#define reg_intr_vect_r_masked_vect___p21___width 1
+#define reg_intr_vect_r_masked_vect___p21___bit 23
+#define reg_intr_vect_r_masked_vect___eth0___lsb 24
+#define reg_intr_vect_r_masked_vect___eth0___width 1
+#define reg_intr_vect_r_masked_vect___eth0___bit 24
+#define reg_intr_vect_r_masked_vect___eth1___lsb 25
+#define reg_intr_vect_r_masked_vect___eth1___width 1
+#define reg_intr_vect_r_masked_vect___eth1___bit 25
+#define reg_intr_vect_r_masked_vect___timer___lsb 26
+#define reg_intr_vect_r_masked_vect___timer___width 1
+#define reg_intr_vect_r_masked_vect___timer___bit 26
+#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
+#define reg_intr_vect_r_masked_vect___bif_arb___width 1
+#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
+#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
+#define reg_intr_vect_r_masked_vect___bif_dma___width 1
+#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
+#define reg_intr_vect_r_masked_vect___ext___lsb 29
+#define reg_intr_vect_r_masked_vect___ext___width 1
+#define reg_intr_vect_r_masked_vect___ext___bit 29
+#define reg_intr_vect_r_masked_vect_offset 8
+
+/* Register r_nmi, scope intr_vect, type r */
+#define reg_intr_vect_r_nmi___ext___lsb 0
+#define reg_intr_vect_r_nmi___ext___width 1
+#define reg_intr_vect_r_nmi___ext___bit 0
+#define reg_intr_vect_r_nmi___watchdog___lsb 1
+#define reg_intr_vect_r_nmi___watchdog___width 1
+#define reg_intr_vect_r_nmi___watchdog___bit 1
+#define reg_intr_vect_r_nmi_offset 12
+
+/* Register r_guru, scope intr_vect, type r */
+#define reg_intr_vect_r_guru___jtag___lsb 0
+#define reg_intr_vect_r_guru___jtag___width 1
+#define reg_intr_vect_r_guru___jtag___bit 0
+#define reg_intr_vect_r_guru_offset 16
+
+
+/* Constants */
+#define regk_intr_vect_off                        0x00000000
+#define regk_intr_vect_on                         0x00000001
+#define regk_intr_vect_rw_mask_default            0x00000000
+#endif /* __intr_vect_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
new file mode 100644
index 000000000000..0c8084054840
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
@@ -0,0 +1,69 @@
+#ifndef __irq_nmi_defs_asm_h
+#define __irq_nmi_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../mod/irq_nmi.r
+ *     id:           <not found>
+ *     last modfied: Thu Jan 22 09:22:43 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
+ *      id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cmd, scope irq_nmi, type rw */
+#define reg_irq_nmi_rw_cmd___delay___lsb 0
+#define reg_irq_nmi_rw_cmd___delay___width 16
+#define reg_irq_nmi_rw_cmd___op___lsb 16
+#define reg_irq_nmi_rw_cmd___op___width 2
+#define reg_irq_nmi_rw_cmd_offset 0
+
+
+/* Constants */
+#define regk_irq_nmi_ack_irq                      0x00000002
+#define regk_irq_nmi_ack_nmi                      0x00000003
+#define regk_irq_nmi_irq                          0x00000000
+#define regk_irq_nmi_nmi                          0x00000001
+#endif /* __irq_nmi_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
new file mode 100644
index 000000000000..45400eb8d389
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
@@ -0,0 +1,579 @@
+#ifndef __marb_defs_asm_h
+#define __marb_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_marb_rw_int_slots 4
+/* Register rw_int_slots, scope marb, type rw */
+#define reg_marb_rw_int_slots___owner___lsb 0
+#define reg_marb_rw_int_slots___owner___width 4
+#define reg_marb_rw_int_slots_offset 0
+
+#define STRIDE_marb_rw_ext_slots 4
+/* Register rw_ext_slots, scope marb, type rw */
+#define reg_marb_rw_ext_slots___owner___lsb 0
+#define reg_marb_rw_ext_slots___owner___width 4
+#define reg_marb_rw_ext_slots_offset 256
+
+#define STRIDE_marb_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb, type rw */
+#define reg_marb_rw_regs_slots___owner___lsb 0
+#define reg_marb_rw_regs_slots___owner___width 4
+#define reg_marb_rw_regs_slots_offset 512
+
+/* Register rw_intr_mask, scope marb, type rw */
+#define reg_marb_rw_intr_mask___bp0___lsb 0
+#define reg_marb_rw_intr_mask___bp0___width 1
+#define reg_marb_rw_intr_mask___bp0___bit 0
+#define reg_marb_rw_intr_mask___bp1___lsb 1
+#define reg_marb_rw_intr_mask___bp1___width 1
+#define reg_marb_rw_intr_mask___bp1___bit 1
+#define reg_marb_rw_intr_mask___bp2___lsb 2
+#define reg_marb_rw_intr_mask___bp2___width 1
+#define reg_marb_rw_intr_mask___bp2___bit 2
+#define reg_marb_rw_intr_mask___bp3___lsb 3
+#define reg_marb_rw_intr_mask___bp3___width 1
+#define reg_marb_rw_intr_mask___bp3___bit 3
+#define reg_marb_rw_intr_mask_offset 528
+
+/* Register rw_ack_intr, scope marb, type rw */
+#define reg_marb_rw_ack_intr___bp0___lsb 0
+#define reg_marb_rw_ack_intr___bp0___width 1
+#define reg_marb_rw_ack_intr___bp0___bit 0
+#define reg_marb_rw_ack_intr___bp1___lsb 1
+#define reg_marb_rw_ack_intr___bp1___width 1
+#define reg_marb_rw_ack_intr___bp1___bit 1
+#define reg_marb_rw_ack_intr___bp2___lsb 2
+#define reg_marb_rw_ack_intr___bp2___width 1
+#define reg_marb_rw_ack_intr___bp2___bit 2
+#define reg_marb_rw_ack_intr___bp3___lsb 3
+#define reg_marb_rw_ack_intr___bp3___width 1
+#define reg_marb_rw_ack_intr___bp3___bit 3
+#define reg_marb_rw_ack_intr_offset 532
+
+/* Register r_intr, scope marb, type r */
+#define reg_marb_r_intr___bp0___lsb 0
+#define reg_marb_r_intr___bp0___width 1
+#define reg_marb_r_intr___bp0___bit 0
+#define reg_marb_r_intr___bp1___lsb 1
+#define reg_marb_r_intr___bp1___width 1
+#define reg_marb_r_intr___bp1___bit 1
+#define reg_marb_r_intr___bp2___lsb 2
+#define reg_marb_r_intr___bp2___width 1
+#define reg_marb_r_intr___bp2___bit 2
+#define reg_marb_r_intr___bp3___lsb 3
+#define reg_marb_r_intr___bp3___width 1
+#define reg_marb_r_intr___bp3___bit 3
+#define reg_marb_r_intr_offset 536
+
+/* Register r_masked_intr, scope marb, type r */
+#define reg_marb_r_masked_intr___bp0___lsb 0
+#define reg_marb_r_masked_intr___bp0___width 1
+#define reg_marb_r_masked_intr___bp0___bit 0
+#define reg_marb_r_masked_intr___bp1___lsb 1
+#define reg_marb_r_masked_intr___bp1___width 1
+#define reg_marb_r_masked_intr___bp1___bit 1
+#define reg_marb_r_masked_intr___bp2___lsb 2
+#define reg_marb_r_masked_intr___bp2___width 1
+#define reg_marb_r_masked_intr___bp2___bit 2
+#define reg_marb_r_masked_intr___bp3___lsb 3
+#define reg_marb_r_masked_intr___bp3___width 1
+#define reg_marb_r_masked_intr___bp3___bit 3
+#define reg_marb_r_masked_intr_offset 540
+
+/* Register rw_stop_mask, scope marb, type rw */
+#define reg_marb_rw_stop_mask___dma0___lsb 0
+#define reg_marb_rw_stop_mask___dma0___width 1
+#define reg_marb_rw_stop_mask___dma0___bit 0
+#define reg_marb_rw_stop_mask___dma1___lsb 1
+#define reg_marb_rw_stop_mask___dma1___width 1
+#define reg_marb_rw_stop_mask___dma1___bit 1
+#define reg_marb_rw_stop_mask___dma2___lsb 2
+#define reg_marb_rw_stop_mask___dma2___width 1
+#define reg_marb_rw_stop_mask___dma2___bit 2
+#define reg_marb_rw_stop_mask___dma3___lsb 3
+#define reg_marb_rw_stop_mask___dma3___width 1
+#define reg_marb_rw_stop_mask___dma3___bit 3
+#define reg_marb_rw_stop_mask___dma4___lsb 4
+#define reg_marb_rw_stop_mask___dma4___width 1
+#define reg_marb_rw_stop_mask___dma4___bit 4
+#define reg_marb_rw_stop_mask___dma5___lsb 5
+#define reg_marb_rw_stop_mask___dma5___width 1
+#define reg_marb_rw_stop_mask___dma5___bit 5
+#define reg_marb_rw_stop_mask___dma6___lsb 6
+#define reg_marb_rw_stop_mask___dma6___width 1
+#define reg_marb_rw_stop_mask___dma6___bit 6
+#define reg_marb_rw_stop_mask___dma7___lsb 7
+#define reg_marb_rw_stop_mask___dma7___width 1
+#define reg_marb_rw_stop_mask___dma7___bit 7
+#define reg_marb_rw_stop_mask___dma8___lsb 8
+#define reg_marb_rw_stop_mask___dma8___width 1
+#define reg_marb_rw_stop_mask___dma8___bit 8
+#define reg_marb_rw_stop_mask___dma9___lsb 9
+#define reg_marb_rw_stop_mask___dma9___width 1
+#define reg_marb_rw_stop_mask___dma9___bit 9
+#define reg_marb_rw_stop_mask___cpui___lsb 10
+#define reg_marb_rw_stop_mask___cpui___width 1
+#define reg_marb_rw_stop_mask___cpui___bit 10
+#define reg_marb_rw_stop_mask___cpud___lsb 11
+#define reg_marb_rw_stop_mask___cpud___width 1
+#define reg_marb_rw_stop_mask___cpud___bit 11
+#define reg_marb_rw_stop_mask___iop___lsb 12
+#define reg_marb_rw_stop_mask___iop___width 1
+#define reg_marb_rw_stop_mask___iop___bit 12
+#define reg_marb_rw_stop_mask___slave___lsb 13
+#define reg_marb_rw_stop_mask___slave___width 1
+#define reg_marb_rw_stop_mask___slave___bit 13
+#define reg_marb_rw_stop_mask_offset 544
+
+/* Register r_stopped, scope marb, type r */
+#define reg_marb_r_stopped___dma0___lsb 0
+#define reg_marb_r_stopped___dma0___width 1
+#define reg_marb_r_stopped___dma0___bit 0
+#define reg_marb_r_stopped___dma1___lsb 1
+#define reg_marb_r_stopped___dma1___width 1
+#define reg_marb_r_stopped___dma1___bit 1
+#define reg_marb_r_stopped___dma2___lsb 2
+#define reg_marb_r_stopped___dma2___width 1
+#define reg_marb_r_stopped___dma2___bit 2
+#define reg_marb_r_stopped___dma3___lsb 3
+#define reg_marb_r_stopped___dma3___width 1
+#define reg_marb_r_stopped___dma3___bit 3
+#define reg_marb_r_stopped___dma4___lsb 4
+#define reg_marb_r_stopped___dma4___width 1
+#define reg_marb_r_stopped___dma4___bit 4
+#define reg_marb_r_stopped___dma5___lsb 5
+#define reg_marb_r_stopped___dma5___width 1
+#define reg_marb_r_stopped___dma5___bit 5
+#define reg_marb_r_stopped___dma6___lsb 6
+#define reg_marb_r_stopped___dma6___width 1
+#define reg_marb_r_stopped___dma6___bit 6
+#define reg_marb_r_stopped___dma7___lsb 7
+#define reg_marb_r_stopped___dma7___width 1
+#define reg_marb_r_stopped___dma7___bit 7
+#define reg_marb_r_stopped___dma8___lsb 8
+#define reg_marb_r_stopped___dma8___width 1
+#define reg_marb_r_stopped___dma8___bit 8
+#define reg_marb_r_stopped___dma9___lsb 9
+#define reg_marb_r_stopped___dma9___width 1
+#define reg_marb_r_stopped___dma9___bit 9
+#define reg_marb_r_stopped___cpui___lsb 10
+#define reg_marb_r_stopped___cpui___width 1
+#define reg_marb_r_stopped___cpui___bit 10
+#define reg_marb_r_stopped___cpud___lsb 11
+#define reg_marb_r_stopped___cpud___width 1
+#define reg_marb_r_stopped___cpud___bit 11
+#define reg_marb_r_stopped___iop___lsb 12
+#define reg_marb_r_stopped___iop___width 1
+#define reg_marb_r_stopped___iop___bit 12
+#define reg_marb_r_stopped___slave___lsb 13
+#define reg_marb_r_stopped___slave___width 1
+#define reg_marb_r_stopped___slave___bit 13
+#define reg_marb_r_stopped_offset 548
+
+/* Register rw_no_snoop, scope marb, type rw */
+#define reg_marb_rw_no_snoop___dma0___lsb 0
+#define reg_marb_rw_no_snoop___dma0___width 1
+#define reg_marb_rw_no_snoop___dma0___bit 0
+#define reg_marb_rw_no_snoop___dma1___lsb 1
+#define reg_marb_rw_no_snoop___dma1___width 1
+#define reg_marb_rw_no_snoop___dma1___bit 1
+#define reg_marb_rw_no_snoop___dma2___lsb 2
+#define reg_marb_rw_no_snoop___dma2___width 1
+#define reg_marb_rw_no_snoop___dma2___bit 2
+#define reg_marb_rw_no_snoop___dma3___lsb 3
+#define reg_marb_rw_no_snoop___dma3___width 1
+#define reg_marb_rw_no_snoop___dma3___bit 3
+#define reg_marb_rw_no_snoop___dma4___lsb 4
+#define reg_marb_rw_no_snoop___dma4___width 1
+#define reg_marb_rw_no_snoop___dma4___bit 4
+#define reg_marb_rw_no_snoop___dma5___lsb 5
+#define reg_marb_rw_no_snoop___dma5___width 1
+#define reg_marb_rw_no_snoop___dma5___bit 5
+#define reg_marb_rw_no_snoop___dma6___lsb 6
+#define reg_marb_rw_no_snoop___dma6___width 1
+#define reg_marb_rw_no_snoop___dma6___bit 6
+#define reg_marb_rw_no_snoop___dma7___lsb 7
+#define reg_marb_rw_no_snoop___dma7___width 1
+#define reg_marb_rw_no_snoop___dma7___bit 7
+#define reg_marb_rw_no_snoop___dma8___lsb 8
+#define reg_marb_rw_no_snoop___dma8___width 1
+#define reg_marb_rw_no_snoop___dma8___bit 8
+#define reg_marb_rw_no_snoop___dma9___lsb 9
+#define reg_marb_rw_no_snoop___dma9___width 1
+#define reg_marb_rw_no_snoop___dma9___bit 9
+#define reg_marb_rw_no_snoop___cpui___lsb 10
+#define reg_marb_rw_no_snoop___cpui___width 1
+#define reg_marb_rw_no_snoop___cpui___bit 10
+#define reg_marb_rw_no_snoop___cpud___lsb 11
+#define reg_marb_rw_no_snoop___cpud___width 1
+#define reg_marb_rw_no_snoop___cpud___bit 11
+#define reg_marb_rw_no_snoop___iop___lsb 12
+#define reg_marb_rw_no_snoop___iop___width 1
+#define reg_marb_rw_no_snoop___iop___bit 12
+#define reg_marb_rw_no_snoop___slave___lsb 13
+#define reg_marb_rw_no_snoop___slave___width 1
+#define reg_marb_rw_no_snoop___slave___bit 13
+#define reg_marb_rw_no_snoop_offset 832
+
+/* Register rw_no_snoop_rq, scope marb, type rw */
+#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
+#define reg_marb_rw_no_snoop_rq___cpui___width 1
+#define reg_marb_rw_no_snoop_rq___cpui___bit 10
+#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
+#define reg_marb_rw_no_snoop_rq___cpud___width 1
+#define reg_marb_rw_no_snoop_rq___cpud___bit 11
+#define reg_marb_rw_no_snoop_rq_offset 836
+
+
+/* Constants */
+#define regk_marb_cpud                            0x0000000b
+#define regk_marb_cpui                            0x0000000a
+#define regk_marb_dma0                            0x00000000
+#define regk_marb_dma1                            0x00000001
+#define regk_marb_dma2                            0x00000002
+#define regk_marb_dma3                            0x00000003
+#define regk_marb_dma4                            0x00000004
+#define regk_marb_dma5                            0x00000005
+#define regk_marb_dma6                            0x00000006
+#define regk_marb_dma7                            0x00000007
+#define regk_marb_dma8                            0x00000008
+#define regk_marb_dma9                            0x00000009
+#define regk_marb_iop                             0x0000000c
+#define regk_marb_no                              0x00000000
+#define regk_marb_r_stopped_default               0x00000000
+#define regk_marb_rw_ext_slots_default            0x00000000
+#define regk_marb_rw_ext_slots_size               0x00000040
+#define regk_marb_rw_int_slots_default            0x00000000
+#define regk_marb_rw_int_slots_size               0x00000040
+#define regk_marb_rw_intr_mask_default            0x00000000
+#define regk_marb_rw_no_snoop_default             0x00000000
+#define regk_marb_rw_no_snoop_rq_default          0x00000000
+#define regk_marb_rw_regs_slots_default           0x00000000
+#define regk_marb_rw_regs_slots_size              0x00000004
+#define regk_marb_rw_stop_mask_default            0x00000000
+#define regk_marb_slave                           0x0000000d
+#define regk_marb_yes                             0x00000001
+#endif /* __marb_defs_asm_h */
+#ifndef __marb_bp_defs_asm_h
+#define __marb_bp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+#define reg_marb_bp_rw_first_addr_offset 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+#define reg_marb_bp_rw_last_addr_offset 4
+
+/* Register rw_op, scope marb_bp, type rw */
+#define reg_marb_bp_rw_op___rd___lsb 0
+#define reg_marb_bp_rw_op___rd___width 1
+#define reg_marb_bp_rw_op___rd___bit 0
+#define reg_marb_bp_rw_op___wr___lsb 1
+#define reg_marb_bp_rw_op___wr___width 1
+#define reg_marb_bp_rw_op___wr___bit 1
+#define reg_marb_bp_rw_op___rd_excl___lsb 2
+#define reg_marb_bp_rw_op___rd_excl___width 1
+#define reg_marb_bp_rw_op___rd_excl___bit 2
+#define reg_marb_bp_rw_op___pri_wr___lsb 3
+#define reg_marb_bp_rw_op___pri_wr___width 1
+#define reg_marb_bp_rw_op___pri_wr___bit 3
+#define reg_marb_bp_rw_op___us_rd___lsb 4
+#define reg_marb_bp_rw_op___us_rd___width 1
+#define reg_marb_bp_rw_op___us_rd___bit 4
+#define reg_marb_bp_rw_op___us_wr___lsb 5
+#define reg_marb_bp_rw_op___us_wr___width 1
+#define reg_marb_bp_rw_op___us_wr___bit 5
+#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
+#define reg_marb_bp_rw_op___us_rd_excl___width 1
+#define reg_marb_bp_rw_op___us_rd_excl___bit 6
+#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
+#define reg_marb_bp_rw_op___us_pri_wr___width 1
+#define reg_marb_bp_rw_op___us_pri_wr___bit 7
+#define reg_marb_bp_rw_op_offset 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+#define reg_marb_bp_rw_clients___dma0___lsb 0
+#define reg_marb_bp_rw_clients___dma0___width 1
+#define reg_marb_bp_rw_clients___dma0___bit 0
+#define reg_marb_bp_rw_clients___dma1___lsb 1
+#define reg_marb_bp_rw_clients___dma1___width 1
+#define reg_marb_bp_rw_clients___dma1___bit 1
+#define reg_marb_bp_rw_clients___dma2___lsb 2
+#define reg_marb_bp_rw_clients___dma2___width 1
+#define reg_marb_bp_rw_clients___dma2___bit 2
+#define reg_marb_bp_rw_clients___dma3___lsb 3
+#define reg_marb_bp_rw_clients___dma3___width 1
+#define reg_marb_bp_rw_clients___dma3___bit 3
+#define reg_marb_bp_rw_clients___dma4___lsb 4
+#define reg_marb_bp_rw_clients___dma4___width 1
+#define reg_marb_bp_rw_clients___dma4___bit 4
+#define reg_marb_bp_rw_clients___dma5___lsb 5
+#define reg_marb_bp_rw_clients___dma5___width 1
+#define reg_marb_bp_rw_clients___dma5___bit 5
+#define reg_marb_bp_rw_clients___dma6___lsb 6
+#define reg_marb_bp_rw_clients___dma6___width 1
+#define reg_marb_bp_rw_clients___dma6___bit 6
+#define reg_marb_bp_rw_clients___dma7___lsb 7
+#define reg_marb_bp_rw_clients___dma7___width 1
+#define reg_marb_bp_rw_clients___dma7___bit 7
+#define reg_marb_bp_rw_clients___dma8___lsb 8
+#define reg_marb_bp_rw_clients___dma8___width 1
+#define reg_marb_bp_rw_clients___dma8___bit 8
+#define reg_marb_bp_rw_clients___dma9___lsb 9
+#define reg_marb_bp_rw_clients___dma9___width 1
+#define reg_marb_bp_rw_clients___dma9___bit 9
+#define reg_marb_bp_rw_clients___cpui___lsb 10
+#define reg_marb_bp_rw_clients___cpui___width 1
+#define reg_marb_bp_rw_clients___cpui___bit 10
+#define reg_marb_bp_rw_clients___cpud___lsb 11
+#define reg_marb_bp_rw_clients___cpud___width 1
+#define reg_marb_bp_rw_clients___cpud___bit 11
+#define reg_marb_bp_rw_clients___iop___lsb 12
+#define reg_marb_bp_rw_clients___iop___width 1
+#define reg_marb_bp_rw_clients___iop___bit 12
+#define reg_marb_bp_rw_clients___slave___lsb 13
+#define reg_marb_bp_rw_clients___slave___width 1
+#define reg_marb_bp_rw_clients___slave___bit 13
+#define reg_marb_bp_rw_clients_offset 12
+
+/* Register rw_options, scope marb_bp, type rw */
+#define reg_marb_bp_rw_options___wrap___lsb 0
+#define reg_marb_bp_rw_options___wrap___width 1
+#define reg_marb_bp_rw_options___wrap___bit 0
+#define reg_marb_bp_rw_options_offset 16
+
+/* Register r_brk_addr, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_addr_offset 20
+
+/* Register r_brk_op, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_op___rd___lsb 0
+#define reg_marb_bp_r_brk_op___rd___width 1
+#define reg_marb_bp_r_brk_op___rd___bit 0
+#define reg_marb_bp_r_brk_op___wr___lsb 1
+#define reg_marb_bp_r_brk_op___wr___width 1
+#define reg_marb_bp_r_brk_op___wr___bit 1
+#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
+#define reg_marb_bp_r_brk_op___rd_excl___width 1
+#define reg_marb_bp_r_brk_op___rd_excl___bit 2
+#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
+#define reg_marb_bp_r_brk_op___pri_wr___width 1
+#define reg_marb_bp_r_brk_op___pri_wr___bit 3
+#define reg_marb_bp_r_brk_op___us_rd___lsb 4
+#define reg_marb_bp_r_brk_op___us_rd___width 1
+#define reg_marb_bp_r_brk_op___us_rd___bit 4
+#define reg_marb_bp_r_brk_op___us_wr___lsb 5
+#define reg_marb_bp_r_brk_op___us_wr___width 1
+#define reg_marb_bp_r_brk_op___us_wr___bit 5
+#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
+#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
+#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
+#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
+#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
+#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
+#define reg_marb_bp_r_brk_op_offset 24
+
+/* Register r_brk_clients, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_clients___dma0___lsb 0
+#define reg_marb_bp_r_brk_clients___dma0___width 1
+#define reg_marb_bp_r_brk_clients___dma0___bit 0
+#define reg_marb_bp_r_brk_clients___dma1___lsb 1
+#define reg_marb_bp_r_brk_clients___dma1___width 1
+#define reg_marb_bp_r_brk_clients___dma1___bit 1
+#define reg_marb_bp_r_brk_clients___dma2___lsb 2
+#define reg_marb_bp_r_brk_clients___dma2___width 1
+#define reg_marb_bp_r_brk_clients___dma2___bit 2
+#define reg_marb_bp_r_brk_clients___dma3___lsb 3
+#define reg_marb_bp_r_brk_clients___dma3___width 1
+#define reg_marb_bp_r_brk_clients___dma3___bit 3
+#define reg_marb_bp_r_brk_clients___dma4___lsb 4
+#define reg_marb_bp_r_brk_clients___dma4___width 1
+#define reg_marb_bp_r_brk_clients___dma4___bit 4
+#define reg_marb_bp_r_brk_clients___dma5___lsb 5
+#define reg_marb_bp_r_brk_clients___dma5___width 1
+#define reg_marb_bp_r_brk_clients___dma5___bit 5
+#define reg_marb_bp_r_brk_clients___dma6___lsb 6
+#define reg_marb_bp_r_brk_clients___dma6___width 1
+#define reg_marb_bp_r_brk_clients___dma6___bit 6
+#define reg_marb_bp_r_brk_clients___dma7___lsb 7
+#define reg_marb_bp_r_brk_clients___dma7___width 1
+#define reg_marb_bp_r_brk_clients___dma7___bit 7
+#define reg_marb_bp_r_brk_clients___dma8___lsb 8
+#define reg_marb_bp_r_brk_clients___dma8___width 1
+#define reg_marb_bp_r_brk_clients___dma8___bit 8
+#define reg_marb_bp_r_brk_clients___dma9___lsb 9
+#define reg_marb_bp_r_brk_clients___dma9___width 1
+#define reg_marb_bp_r_brk_clients___dma9___bit 9
+#define reg_marb_bp_r_brk_clients___cpui___lsb 10
+#define reg_marb_bp_r_brk_clients___cpui___width 1
+#define reg_marb_bp_r_brk_clients___cpui___bit 10
+#define reg_marb_bp_r_brk_clients___cpud___lsb 11
+#define reg_marb_bp_r_brk_clients___cpud___width 1
+#define reg_marb_bp_r_brk_clients___cpud___bit 11
+#define reg_marb_bp_r_brk_clients___iop___lsb 12
+#define reg_marb_bp_r_brk_clients___iop___width 1
+#define reg_marb_bp_r_brk_clients___iop___bit 12
+#define reg_marb_bp_r_brk_clients___slave___lsb 13
+#define reg_marb_bp_r_brk_clients___slave___width 1
+#define reg_marb_bp_r_brk_clients___slave___bit 13
+#define reg_marb_bp_r_brk_clients_offset 28
+
+/* Register r_brk_first_client, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
+#define reg_marb_bp_r_brk_first_client___dma0___width 1
+#define reg_marb_bp_r_brk_first_client___dma0___bit 0
+#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
+#define reg_marb_bp_r_brk_first_client___dma1___width 1
+#define reg_marb_bp_r_brk_first_client___dma1___bit 1
+#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
+#define reg_marb_bp_r_brk_first_client___dma2___width 1
+#define reg_marb_bp_r_brk_first_client___dma2___bit 2
+#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
+#define reg_marb_bp_r_brk_first_client___dma3___width 1
+#define reg_marb_bp_r_brk_first_client___dma3___bit 3
+#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
+#define reg_marb_bp_r_brk_first_client___dma4___width 1
+#define reg_marb_bp_r_brk_first_client___dma4___bit 4
+#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
+#define reg_marb_bp_r_brk_first_client___dma5___width 1
+#define reg_marb_bp_r_brk_first_client___dma5___bit 5
+#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
+#define reg_marb_bp_r_brk_first_client___dma6___width 1
+#define reg_marb_bp_r_brk_first_client___dma6___bit 6
+#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
+#define reg_marb_bp_r_brk_first_client___dma7___width 1
+#define reg_marb_bp_r_brk_first_client___dma7___bit 7
+#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
+#define reg_marb_bp_r_brk_first_client___dma8___width 1
+#define reg_marb_bp_r_brk_first_client___dma8___bit 8
+#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
+#define reg_marb_bp_r_brk_first_client___dma9___width 1
+#define reg_marb_bp_r_brk_first_client___dma9___bit 9
+#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
+#define reg_marb_bp_r_brk_first_client___cpui___width 1
+#define reg_marb_bp_r_brk_first_client___cpui___bit 10
+#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
+#define reg_marb_bp_r_brk_first_client___cpud___width 1
+#define reg_marb_bp_r_brk_first_client___cpud___bit 11
+#define reg_marb_bp_r_brk_first_client___iop___lsb 12
+#define reg_marb_bp_r_brk_first_client___iop___width 1
+#define reg_marb_bp_r_brk_first_client___iop___bit 12
+#define reg_marb_bp_r_brk_first_client___slave___lsb 13
+#define reg_marb_bp_r_brk_first_client___slave___width 1
+#define reg_marb_bp_r_brk_first_client___slave___bit 13
+#define reg_marb_bp_r_brk_first_client_offset 32
+
+/* Register r_brk_size, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_size_offset 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+#define reg_marb_bp_rw_ack_offset 40
+
+
+/* Constants */
+#define regk_marb_bp_no                           0x00000000
+#define regk_marb_bp_rw_op_default                0x00000000
+#define regk_marb_bp_rw_options_default           0x00000000
+#define regk_marb_bp_yes                          0x00000001
+#endif /* __marb_bp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
new file mode 100644
index 000000000000..505b7a16d878
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
@@ -0,0 +1,212 @@
+#ifndef __mmu_defs_asm_h
+#define __mmu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/mmu/doc/mmu_regs.r
+ *     id:           mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
+ *     last modfied: Mon Apr 11 17:03:20 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
+ *      id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mm_cfg, scope mmu, type rw */
+#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
+#define reg_mmu_rw_mm_cfg___seg_0___width 1
+#define reg_mmu_rw_mm_cfg___seg_0___bit 0
+#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
+#define reg_mmu_rw_mm_cfg___seg_1___width 1
+#define reg_mmu_rw_mm_cfg___seg_1___bit 1
+#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
+#define reg_mmu_rw_mm_cfg___seg_2___width 1
+#define reg_mmu_rw_mm_cfg___seg_2___bit 2
+#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
+#define reg_mmu_rw_mm_cfg___seg_3___width 1
+#define reg_mmu_rw_mm_cfg___seg_3___bit 3
+#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
+#define reg_mmu_rw_mm_cfg___seg_4___width 1
+#define reg_mmu_rw_mm_cfg___seg_4___bit 4
+#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
+#define reg_mmu_rw_mm_cfg___seg_5___width 1
+#define reg_mmu_rw_mm_cfg___seg_5___bit 5
+#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
+#define reg_mmu_rw_mm_cfg___seg_6___width 1
+#define reg_mmu_rw_mm_cfg___seg_6___bit 6
+#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
+#define reg_mmu_rw_mm_cfg___seg_7___width 1
+#define reg_mmu_rw_mm_cfg___seg_7___bit 7
+#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
+#define reg_mmu_rw_mm_cfg___seg_8___width 1
+#define reg_mmu_rw_mm_cfg___seg_8___bit 8
+#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
+#define reg_mmu_rw_mm_cfg___seg_9___width 1
+#define reg_mmu_rw_mm_cfg___seg_9___bit 9
+#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
+#define reg_mmu_rw_mm_cfg___seg_a___width 1
+#define reg_mmu_rw_mm_cfg___seg_a___bit 10
+#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
+#define reg_mmu_rw_mm_cfg___seg_b___width 1
+#define reg_mmu_rw_mm_cfg___seg_b___bit 11
+#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
+#define reg_mmu_rw_mm_cfg___seg_c___width 1
+#define reg_mmu_rw_mm_cfg___seg_c___bit 12
+#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
+#define reg_mmu_rw_mm_cfg___seg_d___width 1
+#define reg_mmu_rw_mm_cfg___seg_d___bit 13
+#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
+#define reg_mmu_rw_mm_cfg___seg_e___width 1
+#define reg_mmu_rw_mm_cfg___seg_e___bit 14
+#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
+#define reg_mmu_rw_mm_cfg___seg_f___width 1
+#define reg_mmu_rw_mm_cfg___seg_f___bit 15
+#define reg_mmu_rw_mm_cfg___inv___lsb 16
+#define reg_mmu_rw_mm_cfg___inv___width 1
+#define reg_mmu_rw_mm_cfg___inv___bit 16
+#define reg_mmu_rw_mm_cfg___ex___lsb 17
+#define reg_mmu_rw_mm_cfg___ex___width 1
+#define reg_mmu_rw_mm_cfg___ex___bit 17
+#define reg_mmu_rw_mm_cfg___acc___lsb 18
+#define reg_mmu_rw_mm_cfg___acc___width 1
+#define reg_mmu_rw_mm_cfg___acc___bit 18
+#define reg_mmu_rw_mm_cfg___we___lsb 19
+#define reg_mmu_rw_mm_cfg___we___width 1
+#define reg_mmu_rw_mm_cfg___we___bit 19
+#define reg_mmu_rw_mm_cfg_offset 0
+
+/* Register rw_mm_kbase_lo, scope mmu, type rw */
+#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
+#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
+#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
+#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
+#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
+#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
+#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
+#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
+#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
+#define reg_mmu_rw_mm_kbase_lo_offset 4
+
+/* Register rw_mm_kbase_hi, scope mmu, type rw */
+#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
+#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
+#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
+#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
+#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
+#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
+#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
+#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
+#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
+#define reg_mmu_rw_mm_kbase_hi_offset 8
+
+/* Register r_mm_cause, scope mmu, type r */
+#define reg_mmu_r_mm_cause___pid___lsb 0
+#define reg_mmu_r_mm_cause___pid___width 8
+#define reg_mmu_r_mm_cause___op___lsb 8
+#define reg_mmu_r_mm_cause___op___width 2
+#define reg_mmu_r_mm_cause___vpn___lsb 13
+#define reg_mmu_r_mm_cause___vpn___width 19
+#define reg_mmu_r_mm_cause_offset 12
+
+/* Register rw_mm_tlb_sel, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
+#define reg_mmu_rw_mm_tlb_sel___idx___width 4
+#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
+#define reg_mmu_rw_mm_tlb_sel___set___width 2
+#define reg_mmu_rw_mm_tlb_sel_offset 16
+
+/* Register rw_mm_tlb_lo, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
+#define reg_mmu_rw_mm_tlb_lo___x___width 1
+#define reg_mmu_rw_mm_tlb_lo___x___bit 0
+#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
+#define reg_mmu_rw_mm_tlb_lo___w___width 1
+#define reg_mmu_rw_mm_tlb_lo___w___bit 1
+#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
+#define reg_mmu_rw_mm_tlb_lo___k___width 1
+#define reg_mmu_rw_mm_tlb_lo___k___bit 2
+#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
+#define reg_mmu_rw_mm_tlb_lo___v___width 1
+#define reg_mmu_rw_mm_tlb_lo___v___bit 3
+#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
+#define reg_mmu_rw_mm_tlb_lo___g___width 1
+#define reg_mmu_rw_mm_tlb_lo___g___bit 4
+#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
+#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
+#define reg_mmu_rw_mm_tlb_lo_offset 20
+
+/* Register rw_mm_tlb_hi, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
+#define reg_mmu_rw_mm_tlb_hi___pid___width 8
+#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
+#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
+#define reg_mmu_rw_mm_tlb_hi_offset 24
+
+
+/* Constants */
+#define regk_mmu_execute                          0x00000000
+#define regk_mmu_flush                            0x00000003
+#define regk_mmu_linear                           0x00000001
+#define regk_mmu_no                               0x00000000
+#define regk_mmu_off                              0x00000000
+#define regk_mmu_on                               0x00000001
+#define regk_mmu_page                             0x00000000
+#define regk_mmu_read                             0x00000001
+#define regk_mmu_write                            0x00000002
+#define regk_mmu_yes                              0x00000001
+#endif /* __mmu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
new file mode 100644
index 000000000000..339500bf3bc0
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
@@ -0,0 +1,7 @@
+#define RW_MM_CFG       0
+#define RW_MM_KBASE_LO  1
+#define RW_MM_KBASE_HI  2
+#define R_MM_CAUSE      3
+#define RW_MM_TLB_SEL   4
+#define RW_MM_TLB_LO    5
+#define RW_MM_TLB_HI    6
diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
new file mode 100644
index 000000000000..13c725e4c774
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
@@ -0,0 +1,632 @@
+#ifndef __pinmux_defs_asm_h
+#define __pinmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:11 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *      id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa, scope pinmux, type rw */
+#define reg_pinmux_rw_pa___pa0___lsb 0
+#define reg_pinmux_rw_pa___pa0___width 1
+#define reg_pinmux_rw_pa___pa0___bit 0
+#define reg_pinmux_rw_pa___pa1___lsb 1
+#define reg_pinmux_rw_pa___pa1___width 1
+#define reg_pinmux_rw_pa___pa1___bit 1
+#define reg_pinmux_rw_pa___pa2___lsb 2
+#define reg_pinmux_rw_pa___pa2___width 1
+#define reg_pinmux_rw_pa___pa2___bit 2
+#define reg_pinmux_rw_pa___pa3___lsb 3
+#define reg_pinmux_rw_pa___pa3___width 1
+#define reg_pinmux_rw_pa___pa3___bit 3
+#define reg_pinmux_rw_pa___pa4___lsb 4
+#define reg_pinmux_rw_pa___pa4___width 1
+#define reg_pinmux_rw_pa___pa4___bit 4
+#define reg_pinmux_rw_pa___pa5___lsb 5
+#define reg_pinmux_rw_pa___pa5___width 1
+#define reg_pinmux_rw_pa___pa5___bit 5
+#define reg_pinmux_rw_pa___pa6___lsb 6
+#define reg_pinmux_rw_pa___pa6___width 1
+#define reg_pinmux_rw_pa___pa6___bit 6
+#define reg_pinmux_rw_pa___pa7___lsb 7
+#define reg_pinmux_rw_pa___pa7___width 1
+#define reg_pinmux_rw_pa___pa7___bit 7
+#define reg_pinmux_rw_pa___csp2_n___lsb 8
+#define reg_pinmux_rw_pa___csp2_n___width 1
+#define reg_pinmux_rw_pa___csp2_n___bit 8
+#define reg_pinmux_rw_pa___csp3_n___lsb 9
+#define reg_pinmux_rw_pa___csp3_n___width 1
+#define reg_pinmux_rw_pa___csp3_n___bit 9
+#define reg_pinmux_rw_pa___csp5_n___lsb 10
+#define reg_pinmux_rw_pa___csp5_n___width 1
+#define reg_pinmux_rw_pa___csp5_n___bit 10
+#define reg_pinmux_rw_pa___csp6_n___lsb 11
+#define reg_pinmux_rw_pa___csp6_n___width 1
+#define reg_pinmux_rw_pa___csp6_n___bit 11
+#define reg_pinmux_rw_pa___hsh4___lsb 12
+#define reg_pinmux_rw_pa___hsh4___width 1
+#define reg_pinmux_rw_pa___hsh4___bit 12
+#define reg_pinmux_rw_pa___hsh5___lsb 13
+#define reg_pinmux_rw_pa___hsh5___width 1
+#define reg_pinmux_rw_pa___hsh5___bit 13
+#define reg_pinmux_rw_pa___hsh6___lsb 14
+#define reg_pinmux_rw_pa___hsh6___width 1
+#define reg_pinmux_rw_pa___hsh6___bit 14
+#define reg_pinmux_rw_pa___hsh7___lsb 15
+#define reg_pinmux_rw_pa___hsh7___width 1
+#define reg_pinmux_rw_pa___hsh7___bit 15
+#define reg_pinmux_rw_pa_offset 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+#define reg_pinmux_rw_hwprot___ser1___lsb 0
+#define reg_pinmux_rw_hwprot___ser1___width 1
+#define reg_pinmux_rw_hwprot___ser1___bit 0
+#define reg_pinmux_rw_hwprot___ser2___lsb 1
+#define reg_pinmux_rw_hwprot___ser2___width 1
+#define reg_pinmux_rw_hwprot___ser2___bit 1
+#define reg_pinmux_rw_hwprot___ser3___lsb 2
+#define reg_pinmux_rw_hwprot___ser3___width 1
+#define reg_pinmux_rw_hwprot___ser3___bit 2
+#define reg_pinmux_rw_hwprot___sser0___lsb 3
+#define reg_pinmux_rw_hwprot___sser0___width 1
+#define reg_pinmux_rw_hwprot___sser0___bit 3
+#define reg_pinmux_rw_hwprot___sser1___lsb 4
+#define reg_pinmux_rw_hwprot___sser1___width 1
+#define reg_pinmux_rw_hwprot___sser1___bit 4
+#define reg_pinmux_rw_hwprot___ata0___lsb 5
+#define reg_pinmux_rw_hwprot___ata0___width 1
+#define reg_pinmux_rw_hwprot___ata0___bit 5
+#define reg_pinmux_rw_hwprot___ata1___lsb 6
+#define reg_pinmux_rw_hwprot___ata1___width 1
+#define reg_pinmux_rw_hwprot___ata1___bit 6
+#define reg_pinmux_rw_hwprot___ata2___lsb 7
+#define reg_pinmux_rw_hwprot___ata2___width 1
+#define reg_pinmux_rw_hwprot___ata2___bit 7
+#define reg_pinmux_rw_hwprot___ata3___lsb 8
+#define reg_pinmux_rw_hwprot___ata3___width 1
+#define reg_pinmux_rw_hwprot___ata3___bit 8
+#define reg_pinmux_rw_hwprot___ata___lsb 9
+#define reg_pinmux_rw_hwprot___ata___width 1
+#define reg_pinmux_rw_hwprot___ata___bit 9
+#define reg_pinmux_rw_hwprot___eth1___lsb 10
+#define reg_pinmux_rw_hwprot___eth1___width 1
+#define reg_pinmux_rw_hwprot___eth1___bit 10
+#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
+#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
+#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
+#define reg_pinmux_rw_hwprot___timer___lsb 12
+#define reg_pinmux_rw_hwprot___timer___width 1
+#define reg_pinmux_rw_hwprot___timer___bit 12
+#define reg_pinmux_rw_hwprot___p21___lsb 13
+#define reg_pinmux_rw_hwprot___p21___width 1
+#define reg_pinmux_rw_hwprot___p21___bit 13
+#define reg_pinmux_rw_hwprot_offset 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_gio___pb0___lsb 0
+#define reg_pinmux_rw_pb_gio___pb0___width 1
+#define reg_pinmux_rw_pb_gio___pb0___bit 0
+#define reg_pinmux_rw_pb_gio___pb1___lsb 1
+#define reg_pinmux_rw_pb_gio___pb1___width 1
+#define reg_pinmux_rw_pb_gio___pb1___bit 1
+#define reg_pinmux_rw_pb_gio___pb2___lsb 2
+#define reg_pinmux_rw_pb_gio___pb2___width 1
+#define reg_pinmux_rw_pb_gio___pb2___bit 2
+#define reg_pinmux_rw_pb_gio___pb3___lsb 3
+#define reg_pinmux_rw_pb_gio___pb3___width 1
+#define reg_pinmux_rw_pb_gio___pb3___bit 3
+#define reg_pinmux_rw_pb_gio___pb4___lsb 4
+#define reg_pinmux_rw_pb_gio___pb4___width 1
+#define reg_pinmux_rw_pb_gio___pb4___bit 4
+#define reg_pinmux_rw_pb_gio___pb5___lsb 5
+#define reg_pinmux_rw_pb_gio___pb5___width 1
+#define reg_pinmux_rw_pb_gio___pb5___bit 5
+#define reg_pinmux_rw_pb_gio___pb6___lsb 6
+#define reg_pinmux_rw_pb_gio___pb6___width 1
+#define reg_pinmux_rw_pb_gio___pb6___bit 6
+#define reg_pinmux_rw_pb_gio___pb7___lsb 7
+#define reg_pinmux_rw_pb_gio___pb7___width 1
+#define reg_pinmux_rw_pb_gio___pb7___bit 7
+#define reg_pinmux_rw_pb_gio___pb8___lsb 8
+#define reg_pinmux_rw_pb_gio___pb8___width 1
+#define reg_pinmux_rw_pb_gio___pb8___bit 8
+#define reg_pinmux_rw_pb_gio___pb9___lsb 9
+#define reg_pinmux_rw_pb_gio___pb9___width 1
+#define reg_pinmux_rw_pb_gio___pb9___bit 9
+#define reg_pinmux_rw_pb_gio___pb10___lsb 10
+#define reg_pinmux_rw_pb_gio___pb10___width 1
+#define reg_pinmux_rw_pb_gio___pb10___bit 10
+#define reg_pinmux_rw_pb_gio___pb11___lsb 11
+#define reg_pinmux_rw_pb_gio___pb11___width 1
+#define reg_pinmux_rw_pb_gio___pb11___bit 11
+#define reg_pinmux_rw_pb_gio___pb12___lsb 12
+#define reg_pinmux_rw_pb_gio___pb12___width 1
+#define reg_pinmux_rw_pb_gio___pb12___bit 12
+#define reg_pinmux_rw_pb_gio___pb13___lsb 13
+#define reg_pinmux_rw_pb_gio___pb13___width 1
+#define reg_pinmux_rw_pb_gio___pb13___bit 13
+#define reg_pinmux_rw_pb_gio___pb14___lsb 14
+#define reg_pinmux_rw_pb_gio___pb14___width 1
+#define reg_pinmux_rw_pb_gio___pb14___bit 14
+#define reg_pinmux_rw_pb_gio___pb15___lsb 15
+#define reg_pinmux_rw_pb_gio___pb15___width 1
+#define reg_pinmux_rw_pb_gio___pb15___bit 15
+#define reg_pinmux_rw_pb_gio___pb16___lsb 16
+#define reg_pinmux_rw_pb_gio___pb16___width 1
+#define reg_pinmux_rw_pb_gio___pb16___bit 16
+#define reg_pinmux_rw_pb_gio___pb17___lsb 17
+#define reg_pinmux_rw_pb_gio___pb17___width 1
+#define reg_pinmux_rw_pb_gio___pb17___bit 17
+#define reg_pinmux_rw_pb_gio_offset 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_iop___pb0___lsb 0
+#define reg_pinmux_rw_pb_iop___pb0___width 1
+#define reg_pinmux_rw_pb_iop___pb0___bit 0
+#define reg_pinmux_rw_pb_iop___pb1___lsb 1
+#define reg_pinmux_rw_pb_iop___pb1___width 1
+#define reg_pinmux_rw_pb_iop___pb1___bit 1
+#define reg_pinmux_rw_pb_iop___pb2___lsb 2
+#define reg_pinmux_rw_pb_iop___pb2___width 1
+#define reg_pinmux_rw_pb_iop___pb2___bit 2
+#define reg_pinmux_rw_pb_iop___pb3___lsb 3
+#define reg_pinmux_rw_pb_iop___pb3___width 1
+#define reg_pinmux_rw_pb_iop___pb3___bit 3
+#define reg_pinmux_rw_pb_iop___pb4___lsb 4
+#define reg_pinmux_rw_pb_iop___pb4___width 1
+#define reg_pinmux_rw_pb_iop___pb4___bit 4
+#define reg_pinmux_rw_pb_iop___pb5___lsb 5
+#define reg_pinmux_rw_pb_iop___pb5___width 1
+#define reg_pinmux_rw_pb_iop___pb5___bit 5
+#define reg_pinmux_rw_pb_iop___pb6___lsb 6
+#define reg_pinmux_rw_pb_iop___pb6___width 1
+#define reg_pinmux_rw_pb_iop___pb6___bit 6
+#define reg_pinmux_rw_pb_iop___pb7___lsb 7
+#define reg_pinmux_rw_pb_iop___pb7___width 1
+#define reg_pinmux_rw_pb_iop___pb7___bit 7
+#define reg_pinmux_rw_pb_iop___pb8___lsb 8
+#define reg_pinmux_rw_pb_iop___pb8___width 1
+#define reg_pinmux_rw_pb_iop___pb8___bit 8
+#define reg_pinmux_rw_pb_iop___pb9___lsb 9
+#define reg_pinmux_rw_pb_iop___pb9___width 1
+#define reg_pinmux_rw_pb_iop___pb9___bit 9
+#define reg_pinmux_rw_pb_iop___pb10___lsb 10
+#define reg_pinmux_rw_pb_iop___pb10___width 1
+#define reg_pinmux_rw_pb_iop___pb10___bit 10
+#define reg_pinmux_rw_pb_iop___pb11___lsb 11
+#define reg_pinmux_rw_pb_iop___pb11___width 1
+#define reg_pinmux_rw_pb_iop___pb11___bit 11
+#define reg_pinmux_rw_pb_iop___pb12___lsb 12
+#define reg_pinmux_rw_pb_iop___pb12___width 1
+#define reg_pinmux_rw_pb_iop___pb12___bit 12
+#define reg_pinmux_rw_pb_iop___pb13___lsb 13
+#define reg_pinmux_rw_pb_iop___pb13___width 1
+#define reg_pinmux_rw_pb_iop___pb13___bit 13
+#define reg_pinmux_rw_pb_iop___pb14___lsb 14
+#define reg_pinmux_rw_pb_iop___pb14___width 1
+#define reg_pinmux_rw_pb_iop___pb14___bit 14
+#define reg_pinmux_rw_pb_iop___pb15___lsb 15
+#define reg_pinmux_rw_pb_iop___pb15___width 1
+#define reg_pinmux_rw_pb_iop___pb15___bit 15
+#define reg_pinmux_rw_pb_iop___pb16___lsb 16
+#define reg_pinmux_rw_pb_iop___pb16___width 1
+#define reg_pinmux_rw_pb_iop___pb16___bit 16
+#define reg_pinmux_rw_pb_iop___pb17___lsb 17
+#define reg_pinmux_rw_pb_iop___pb17___width 1
+#define reg_pinmux_rw_pb_iop___pb17___bit 17
+#define reg_pinmux_rw_pb_iop_offset 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_gio___pc0___lsb 0
+#define reg_pinmux_rw_pc_gio___pc0___width 1
+#define reg_pinmux_rw_pc_gio___pc0___bit 0
+#define reg_pinmux_rw_pc_gio___pc1___lsb 1
+#define reg_pinmux_rw_pc_gio___pc1___width 1
+#define reg_pinmux_rw_pc_gio___pc1___bit 1
+#define reg_pinmux_rw_pc_gio___pc2___lsb 2
+#define reg_pinmux_rw_pc_gio___pc2___width 1
+#define reg_pinmux_rw_pc_gio___pc2___bit 2
+#define reg_pinmux_rw_pc_gio___pc3___lsb 3
+#define reg_pinmux_rw_pc_gio___pc3___width 1
+#define reg_pinmux_rw_pc_gio___pc3___bit 3
+#define reg_pinmux_rw_pc_gio___pc4___lsb 4
+#define reg_pinmux_rw_pc_gio___pc4___width 1
+#define reg_pinmux_rw_pc_gio___pc4___bit 4
+#define reg_pinmux_rw_pc_gio___pc5___lsb 5
+#define reg_pinmux_rw_pc_gio___pc5___width 1
+#define reg_pinmux_rw_pc_gio___pc5___bit 5
+#define reg_pinmux_rw_pc_gio___pc6___lsb 6
+#define reg_pinmux_rw_pc_gio___pc6___width 1
+#define reg_pinmux_rw_pc_gio___pc6___bit 6
+#define reg_pinmux_rw_pc_gio___pc7___lsb 7
+#define reg_pinmux_rw_pc_gio___pc7___width 1
+#define reg_pinmux_rw_pc_gio___pc7___bit 7
+#define reg_pinmux_rw_pc_gio___pc8___lsb 8
+#define reg_pinmux_rw_pc_gio___pc8___width 1
+#define reg_pinmux_rw_pc_gio___pc8___bit 8
+#define reg_pinmux_rw_pc_gio___pc9___lsb 9
+#define reg_pinmux_rw_pc_gio___pc9___width 1
+#define reg_pinmux_rw_pc_gio___pc9___bit 9
+#define reg_pinmux_rw_pc_gio___pc10___lsb 10
+#define reg_pinmux_rw_pc_gio___pc10___width 1
+#define reg_pinmux_rw_pc_gio___pc10___bit 10
+#define reg_pinmux_rw_pc_gio___pc11___lsb 11
+#define reg_pinmux_rw_pc_gio___pc11___width 1
+#define reg_pinmux_rw_pc_gio___pc11___bit 11
+#define reg_pinmux_rw_pc_gio___pc12___lsb 12
+#define reg_pinmux_rw_pc_gio___pc12___width 1
+#define reg_pinmux_rw_pc_gio___pc12___bit 12
+#define reg_pinmux_rw_pc_gio___pc13___lsb 13
+#define reg_pinmux_rw_pc_gio___pc13___width 1
+#define reg_pinmux_rw_pc_gio___pc13___bit 13
+#define reg_pinmux_rw_pc_gio___pc14___lsb 14
+#define reg_pinmux_rw_pc_gio___pc14___width 1
+#define reg_pinmux_rw_pc_gio___pc14___bit 14
+#define reg_pinmux_rw_pc_gio___pc15___lsb 15
+#define reg_pinmux_rw_pc_gio___pc15___width 1
+#define reg_pinmux_rw_pc_gio___pc15___bit 15
+#define reg_pinmux_rw_pc_gio___pc16___lsb 16
+#define reg_pinmux_rw_pc_gio___pc16___width 1
+#define reg_pinmux_rw_pc_gio___pc16___bit 16
+#define reg_pinmux_rw_pc_gio___pc17___lsb 17
+#define reg_pinmux_rw_pc_gio___pc17___width 1
+#define reg_pinmux_rw_pc_gio___pc17___bit 17
+#define reg_pinmux_rw_pc_gio_offset 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_iop___pc0___lsb 0
+#define reg_pinmux_rw_pc_iop___pc0___width 1
+#define reg_pinmux_rw_pc_iop___pc0___bit 0
+#define reg_pinmux_rw_pc_iop___pc1___lsb 1
+#define reg_pinmux_rw_pc_iop___pc1___width 1
+#define reg_pinmux_rw_pc_iop___pc1___bit 1
+#define reg_pinmux_rw_pc_iop___pc2___lsb 2
+#define reg_pinmux_rw_pc_iop___pc2___width 1
+#define reg_pinmux_rw_pc_iop___pc2___bit 2
+#define reg_pinmux_rw_pc_iop___pc3___lsb 3
+#define reg_pinmux_rw_pc_iop___pc3___width 1
+#define reg_pinmux_rw_pc_iop___pc3___bit 3
+#define reg_pinmux_rw_pc_iop___pc4___lsb 4
+#define reg_pinmux_rw_pc_iop___pc4___width 1
+#define reg_pinmux_rw_pc_iop___pc4___bit 4
+#define reg_pinmux_rw_pc_iop___pc5___lsb 5
+#define reg_pinmux_rw_pc_iop___pc5___width 1
+#define reg_pinmux_rw_pc_iop___pc5___bit 5
+#define reg_pinmux_rw_pc_iop___pc6___lsb 6
+#define reg_pinmux_rw_pc_iop___pc6___width 1
+#define reg_pinmux_rw_pc_iop___pc6___bit 6
+#define reg_pinmux_rw_pc_iop___pc7___lsb 7
+#define reg_pinmux_rw_pc_iop___pc7___width 1
+#define reg_pinmux_rw_pc_iop___pc7___bit 7
+#define reg_pinmux_rw_pc_iop___pc8___lsb 8
+#define reg_pinmux_rw_pc_iop___pc8___width 1
+#define reg_pinmux_rw_pc_iop___pc8___bit 8
+#define reg_pinmux_rw_pc_iop___pc9___lsb 9
+#define reg_pinmux_rw_pc_iop___pc9___width 1
+#define reg_pinmux_rw_pc_iop___pc9___bit 9
+#define reg_pinmux_rw_pc_iop___pc10___lsb 10
+#define reg_pinmux_rw_pc_iop___pc10___width 1
+#define reg_pinmux_rw_pc_iop___pc10___bit 10
+#define reg_pinmux_rw_pc_iop___pc11___lsb 11
+#define reg_pinmux_rw_pc_iop___pc11___width 1
+#define reg_pinmux_rw_pc_iop___pc11___bit 11
+#define reg_pinmux_rw_pc_iop___pc12___lsb 12
+#define reg_pinmux_rw_pc_iop___pc12___width 1
+#define reg_pinmux_rw_pc_iop___pc12___bit 12
+#define reg_pinmux_rw_pc_iop___pc13___lsb 13
+#define reg_pinmux_rw_pc_iop___pc13___width 1
+#define reg_pinmux_rw_pc_iop___pc13___bit 13
+#define reg_pinmux_rw_pc_iop___pc14___lsb 14
+#define reg_pinmux_rw_pc_iop___pc14___width 1
+#define reg_pinmux_rw_pc_iop___pc14___bit 14
+#define reg_pinmux_rw_pc_iop___pc15___lsb 15
+#define reg_pinmux_rw_pc_iop___pc15___width 1
+#define reg_pinmux_rw_pc_iop___pc15___bit 15
+#define reg_pinmux_rw_pc_iop___pc16___lsb 16
+#define reg_pinmux_rw_pc_iop___pc16___width 1
+#define reg_pinmux_rw_pc_iop___pc16___bit 16
+#define reg_pinmux_rw_pc_iop___pc17___lsb 17
+#define reg_pinmux_rw_pc_iop___pc17___width 1
+#define reg_pinmux_rw_pc_iop___pc17___bit 17
+#define reg_pinmux_rw_pc_iop_offset 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_gio___pd0___lsb 0
+#define reg_pinmux_rw_pd_gio___pd0___width 1
+#define reg_pinmux_rw_pd_gio___pd0___bit 0
+#define reg_pinmux_rw_pd_gio___pd1___lsb 1
+#define reg_pinmux_rw_pd_gio___pd1___width 1
+#define reg_pinmux_rw_pd_gio___pd1___bit 1
+#define reg_pinmux_rw_pd_gio___pd2___lsb 2
+#define reg_pinmux_rw_pd_gio___pd2___width 1
+#define reg_pinmux_rw_pd_gio___pd2___bit 2
+#define reg_pinmux_rw_pd_gio___pd3___lsb 3
+#define reg_pinmux_rw_pd_gio___pd3___width 1
+#define reg_pinmux_rw_pd_gio___pd3___bit 3
+#define reg_pinmux_rw_pd_gio___pd4___lsb 4
+#define reg_pinmux_rw_pd_gio___pd4___width 1
+#define reg_pinmux_rw_pd_gio___pd4___bit 4
+#define reg_pinmux_rw_pd_gio___pd5___lsb 5
+#define reg_pinmux_rw_pd_gio___pd5___width 1
+#define reg_pinmux_rw_pd_gio___pd5___bit 5
+#define reg_pinmux_rw_pd_gio___pd6___lsb 6
+#define reg_pinmux_rw_pd_gio___pd6___width 1
+#define reg_pinmux_rw_pd_gio___pd6___bit 6
+#define reg_pinmux_rw_pd_gio___pd7___lsb 7
+#define reg_pinmux_rw_pd_gio___pd7___width 1
+#define reg_pinmux_rw_pd_gio___pd7___bit 7
+#define reg_pinmux_rw_pd_gio___pd8___lsb 8
+#define reg_pinmux_rw_pd_gio___pd8___width 1
+#define reg_pinmux_rw_pd_gio___pd8___bit 8
+#define reg_pinmux_rw_pd_gio___pd9___lsb 9
+#define reg_pinmux_rw_pd_gio___pd9___width 1
+#define reg_pinmux_rw_pd_gio___pd9___bit 9
+#define reg_pinmux_rw_pd_gio___pd10___lsb 10
+#define reg_pinmux_rw_pd_gio___pd10___width 1
+#define reg_pinmux_rw_pd_gio___pd10___bit 10
+#define reg_pinmux_rw_pd_gio___pd11___lsb 11
+#define reg_pinmux_rw_pd_gio___pd11___width 1
+#define reg_pinmux_rw_pd_gio___pd11___bit 11
+#define reg_pinmux_rw_pd_gio___pd12___lsb 12
+#define reg_pinmux_rw_pd_gio___pd12___width 1
+#define reg_pinmux_rw_pd_gio___pd12___bit 12
+#define reg_pinmux_rw_pd_gio___pd13___lsb 13
+#define reg_pinmux_rw_pd_gio___pd13___width 1
+#define reg_pinmux_rw_pd_gio___pd13___bit 13
+#define reg_pinmux_rw_pd_gio___pd14___lsb 14
+#define reg_pinmux_rw_pd_gio___pd14___width 1
+#define reg_pinmux_rw_pd_gio___pd14___bit 14
+#define reg_pinmux_rw_pd_gio___pd15___lsb 15
+#define reg_pinmux_rw_pd_gio___pd15___width 1
+#define reg_pinmux_rw_pd_gio___pd15___bit 15
+#define reg_pinmux_rw_pd_gio___pd16___lsb 16
+#define reg_pinmux_rw_pd_gio___pd16___width 1
+#define reg_pinmux_rw_pd_gio___pd16___bit 16
+#define reg_pinmux_rw_pd_gio___pd17___lsb 17
+#define reg_pinmux_rw_pd_gio___pd17___width 1
+#define reg_pinmux_rw_pd_gio___pd17___bit 17
+#define reg_pinmux_rw_pd_gio_offset 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_iop___pd0___lsb 0
+#define reg_pinmux_rw_pd_iop___pd0___width 1
+#define reg_pinmux_rw_pd_iop___pd0___bit 0
+#define reg_pinmux_rw_pd_iop___pd1___lsb 1
+#define reg_pinmux_rw_pd_iop___pd1___width 1
+#define reg_pinmux_rw_pd_iop___pd1___bit 1
+#define reg_pinmux_rw_pd_iop___pd2___lsb 2
+#define reg_pinmux_rw_pd_iop___pd2___width 1
+#define reg_pinmux_rw_pd_iop___pd2___bit 2
+#define reg_pinmux_rw_pd_iop___pd3___lsb 3
+#define reg_pinmux_rw_pd_iop___pd3___width 1
+#define reg_pinmux_rw_pd_iop___pd3___bit 3
+#define reg_pinmux_rw_pd_iop___pd4___lsb 4
+#define reg_pinmux_rw_pd_iop___pd4___width 1
+#define reg_pinmux_rw_pd_iop___pd4___bit 4
+#define reg_pinmux_rw_pd_iop___pd5___lsb 5
+#define reg_pinmux_rw_pd_iop___pd5___width 1
+#define reg_pinmux_rw_pd_iop___pd5___bit 5
+#define reg_pinmux_rw_pd_iop___pd6___lsb 6
+#define reg_pinmux_rw_pd_iop___pd6___width 1
+#define reg_pinmux_rw_pd_iop___pd6___bit 6
+#define reg_pinmux_rw_pd_iop___pd7___lsb 7
+#define reg_pinmux_rw_pd_iop___pd7___width 1
+#define reg_pinmux_rw_pd_iop___pd7___bit 7
+#define reg_pinmux_rw_pd_iop___pd8___lsb 8
+#define reg_pinmux_rw_pd_iop___pd8___width 1
+#define reg_pinmux_rw_pd_iop___pd8___bit 8
+#define reg_pinmux_rw_pd_iop___pd9___lsb 9
+#define reg_pinmux_rw_pd_iop___pd9___width 1
+#define reg_pinmux_rw_pd_iop___pd9___bit 9
+#define reg_pinmux_rw_pd_iop___pd10___lsb 10
+#define reg_pinmux_rw_pd_iop___pd10___width 1
+#define reg_pinmux_rw_pd_iop___pd10___bit 10
+#define reg_pinmux_rw_pd_iop___pd11___lsb 11
+#define reg_pinmux_rw_pd_iop___pd11___width 1
+#define reg_pinmux_rw_pd_iop___pd11___bit 11
+#define reg_pinmux_rw_pd_iop___pd12___lsb 12
+#define reg_pinmux_rw_pd_iop___pd12___width 1
+#define reg_pinmux_rw_pd_iop___pd12___bit 12
+#define reg_pinmux_rw_pd_iop___pd13___lsb 13
+#define reg_pinmux_rw_pd_iop___pd13___width 1
+#define reg_pinmux_rw_pd_iop___pd13___bit 13
+#define reg_pinmux_rw_pd_iop___pd14___lsb 14
+#define reg_pinmux_rw_pd_iop___pd14___width 1
+#define reg_pinmux_rw_pd_iop___pd14___bit 14
+#define reg_pinmux_rw_pd_iop___pd15___lsb 15
+#define reg_pinmux_rw_pd_iop___pd15___width 1
+#define reg_pinmux_rw_pd_iop___pd15___bit 15
+#define reg_pinmux_rw_pd_iop___pd16___lsb 16
+#define reg_pinmux_rw_pd_iop___pd16___width 1
+#define reg_pinmux_rw_pd_iop___pd16___bit 16
+#define reg_pinmux_rw_pd_iop___pd17___lsb 17
+#define reg_pinmux_rw_pd_iop___pd17___width 1
+#define reg_pinmux_rw_pd_iop___pd17___bit 17
+#define reg_pinmux_rw_pd_iop_offset 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_gio___pe0___lsb 0
+#define reg_pinmux_rw_pe_gio___pe0___width 1
+#define reg_pinmux_rw_pe_gio___pe0___bit 0
+#define reg_pinmux_rw_pe_gio___pe1___lsb 1
+#define reg_pinmux_rw_pe_gio___pe1___width 1
+#define reg_pinmux_rw_pe_gio___pe1___bit 1
+#define reg_pinmux_rw_pe_gio___pe2___lsb 2
+#define reg_pinmux_rw_pe_gio___pe2___width 1
+#define reg_pinmux_rw_pe_gio___pe2___bit 2
+#define reg_pinmux_rw_pe_gio___pe3___lsb 3
+#define reg_pinmux_rw_pe_gio___pe3___width 1
+#define reg_pinmux_rw_pe_gio___pe3___bit 3
+#define reg_pinmux_rw_pe_gio___pe4___lsb 4
+#define reg_pinmux_rw_pe_gio___pe4___width 1
+#define reg_pinmux_rw_pe_gio___pe4___bit 4
+#define reg_pinmux_rw_pe_gio___pe5___lsb 5
+#define reg_pinmux_rw_pe_gio___pe5___width 1
+#define reg_pinmux_rw_pe_gio___pe5___bit 5
+#define reg_pinmux_rw_pe_gio___pe6___lsb 6
+#define reg_pinmux_rw_pe_gio___pe6___width 1
+#define reg_pinmux_rw_pe_gio___pe6___bit 6
+#define reg_pinmux_rw_pe_gio___pe7___lsb 7
+#define reg_pinmux_rw_pe_gio___pe7___width 1
+#define reg_pinmux_rw_pe_gio___pe7___bit 7
+#define reg_pinmux_rw_pe_gio___pe8___lsb 8
+#define reg_pinmux_rw_pe_gio___pe8___width 1
+#define reg_pinmux_rw_pe_gio___pe8___bit 8
+#define reg_pinmux_rw_pe_gio___pe9___lsb 9
+#define reg_pinmux_rw_pe_gio___pe9___width 1
+#define reg_pinmux_rw_pe_gio___pe9___bit 9
+#define reg_pinmux_rw_pe_gio___pe10___lsb 10
+#define reg_pinmux_rw_pe_gio___pe10___width 1
+#define reg_pinmux_rw_pe_gio___pe10___bit 10
+#define reg_pinmux_rw_pe_gio___pe11___lsb 11
+#define reg_pinmux_rw_pe_gio___pe11___width 1
+#define reg_pinmux_rw_pe_gio___pe11___bit 11
+#define reg_pinmux_rw_pe_gio___pe12___lsb 12
+#define reg_pinmux_rw_pe_gio___pe12___width 1
+#define reg_pinmux_rw_pe_gio___pe12___bit 12
+#define reg_pinmux_rw_pe_gio___pe13___lsb 13
+#define reg_pinmux_rw_pe_gio___pe13___width 1
+#define reg_pinmux_rw_pe_gio___pe13___bit 13
+#define reg_pinmux_rw_pe_gio___pe14___lsb 14
+#define reg_pinmux_rw_pe_gio___pe14___width 1
+#define reg_pinmux_rw_pe_gio___pe14___bit 14
+#define reg_pinmux_rw_pe_gio___pe15___lsb 15
+#define reg_pinmux_rw_pe_gio___pe15___width 1
+#define reg_pinmux_rw_pe_gio___pe15___bit 15
+#define reg_pinmux_rw_pe_gio___pe16___lsb 16
+#define reg_pinmux_rw_pe_gio___pe16___width 1
+#define reg_pinmux_rw_pe_gio___pe16___bit 16
+#define reg_pinmux_rw_pe_gio___pe17___lsb 17
+#define reg_pinmux_rw_pe_gio___pe17___width 1
+#define reg_pinmux_rw_pe_gio___pe17___bit 17
+#define reg_pinmux_rw_pe_gio_offset 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_iop___pe0___lsb 0
+#define reg_pinmux_rw_pe_iop___pe0___width 1
+#define reg_pinmux_rw_pe_iop___pe0___bit 0
+#define reg_pinmux_rw_pe_iop___pe1___lsb 1
+#define reg_pinmux_rw_pe_iop___pe1___width 1
+#define reg_pinmux_rw_pe_iop___pe1___bit 1
+#define reg_pinmux_rw_pe_iop___pe2___lsb 2
+#define reg_pinmux_rw_pe_iop___pe2___width 1
+#define reg_pinmux_rw_pe_iop___pe2___bit 2
+#define reg_pinmux_rw_pe_iop___pe3___lsb 3
+#define reg_pinmux_rw_pe_iop___pe3___width 1
+#define reg_pinmux_rw_pe_iop___pe3___bit 3
+#define reg_pinmux_rw_pe_iop___pe4___lsb 4
+#define reg_pinmux_rw_pe_iop___pe4___width 1
+#define reg_pinmux_rw_pe_iop___pe4___bit 4
+#define reg_pinmux_rw_pe_iop___pe5___lsb 5
+#define reg_pinmux_rw_pe_iop___pe5___width 1
+#define reg_pinmux_rw_pe_iop___pe5___bit 5
+#define reg_pinmux_rw_pe_iop___pe6___lsb 6
+#define reg_pinmux_rw_pe_iop___pe6___width 1
+#define reg_pinmux_rw_pe_iop___pe6___bit 6
+#define reg_pinmux_rw_pe_iop___pe7___lsb 7
+#define reg_pinmux_rw_pe_iop___pe7___width 1
+#define reg_pinmux_rw_pe_iop___pe7___bit 7
+#define reg_pinmux_rw_pe_iop___pe8___lsb 8
+#define reg_pinmux_rw_pe_iop___pe8___width 1
+#define reg_pinmux_rw_pe_iop___pe8___bit 8
+#define reg_pinmux_rw_pe_iop___pe9___lsb 9
+#define reg_pinmux_rw_pe_iop___pe9___width 1
+#define reg_pinmux_rw_pe_iop___pe9___bit 9
+#define reg_pinmux_rw_pe_iop___pe10___lsb 10
+#define reg_pinmux_rw_pe_iop___pe10___width 1
+#define reg_pinmux_rw_pe_iop___pe10___bit 10
+#define reg_pinmux_rw_pe_iop___pe11___lsb 11
+#define reg_pinmux_rw_pe_iop___pe11___width 1
+#define reg_pinmux_rw_pe_iop___pe11___bit 11
+#define reg_pinmux_rw_pe_iop___pe12___lsb 12
+#define reg_pinmux_rw_pe_iop___pe12___width 1
+#define reg_pinmux_rw_pe_iop___pe12___bit 12
+#define reg_pinmux_rw_pe_iop___pe13___lsb 13
+#define reg_pinmux_rw_pe_iop___pe13___width 1
+#define reg_pinmux_rw_pe_iop___pe13___bit 13
+#define reg_pinmux_rw_pe_iop___pe14___lsb 14
+#define reg_pinmux_rw_pe_iop___pe14___width 1
+#define reg_pinmux_rw_pe_iop___pe14___bit 14
+#define reg_pinmux_rw_pe_iop___pe15___lsb 15
+#define reg_pinmux_rw_pe_iop___pe15___width 1
+#define reg_pinmux_rw_pe_iop___pe15___bit 15
+#define reg_pinmux_rw_pe_iop___pe16___lsb 16
+#define reg_pinmux_rw_pe_iop___pe16___width 1
+#define reg_pinmux_rw_pe_iop___pe16___bit 16
+#define reg_pinmux_rw_pe_iop___pe17___lsb 17
+#define reg_pinmux_rw_pe_iop___pe17___width 1
+#define reg_pinmux_rw_pe_iop___pe17___bit 17
+#define reg_pinmux_rw_pe_iop_offset 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
+#define reg_pinmux_rw_usb_phy___en_usb0___width 1
+#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
+#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
+#define reg_pinmux_rw_usb_phy___en_usb1___width 1
+#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
+#define reg_pinmux_rw_usb_phy_offset 40
+
+
+/* Constants */
+#define regk_pinmux_no                            0x00000000
+#define regk_pinmux_rw_hwprot_default             0x00000000
+#define regk_pinmux_rw_pa_default                 0x00000000
+#define regk_pinmux_rw_pb_gio_default             0x00000000
+#define regk_pinmux_rw_pb_iop_default             0x00000000
+#define regk_pinmux_rw_pc_gio_default             0x00000000
+#define regk_pinmux_rw_pc_iop_default             0x00000000
+#define regk_pinmux_rw_pd_gio_default             0x00000000
+#define regk_pinmux_rw_pd_iop_default             0x00000000
+#define regk_pinmux_rw_pe_gio_default             0x00000000
+#define regk_pinmux_rw_pe_iop_default             0x00000000
+#define regk_pinmux_rw_usb_phy_default            0x00000000
+#define regk_pinmux_yes                           0x00000001
+#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
new file mode 100644
index 000000000000..76959b70cd2c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
@@ -0,0 +1,96 @@
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ *   file:            ../../mod/fakereg.rmap
+ *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ *     last modified: Wed Feb 11 20:53:25 2004
+ *   file:            ../../rtl/global.rmap
+ *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ *     last modified: Mon Aug 18 17:08:23 2003
+ *   file:            ../../mod/modreg.rmap
+ *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ *     last modified: Fri Feb 20 16:40:04 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
+ *      id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+#define regi_artpec_mod                           0xb7044000
+#define regi_ata                                  0xb0032000
+#define regi_ata_mod                              0xb7006000
+#define regi_barber                               0xb701a000
+#define regi_bif_core                             0xb0014000
+#define regi_bif_dma                              0xb0016000
+#define regi_bif_slave                            0xb0018000
+#define regi_bif_slave_ext                        0xac000000
+#define regi_bus_master                           0xb703c000
+#define regi_config                               0xb003c000
+#define regi_dma0                                 0xb0000000
+#define regi_dma1                                 0xb0002000
+#define regi_dma2                                 0xb0004000
+#define regi_dma3                                 0xb0006000
+#define regi_dma4                                 0xb0008000
+#define regi_dma5                                 0xb000a000
+#define regi_dma6                                 0xb000c000
+#define regi_dma7                                 0xb000e000
+#define regi_dma8                                 0xb0010000
+#define regi_dma9                                 0xb0012000
+#define regi_eth0                                 0xb0034000
+#define regi_eth1                                 0xb0036000
+#define regi_eth_mod                              0xb7004000
+#define regi_eth_mod1                             0xb701c000
+#define regi_eth_strmod                           0xb7008000
+#define regi_eth_strmod1                          0xb7032000
+#define regi_ext_dma                              0xb703a000
+#define regi_ext_mem                              0xb7046000
+#define regi_gen_io                               0xb7016000
+#define regi_gio                                  0xb001a000
+#define regi_hook                                 0xb7000000
+#define regi_iop                                  0xb0020000
+#define regi_irq                                  0xb001c000
+#define regi_irq_nmi                              0xb701e000
+#define regi_marb                                 0xb003e000
+#define regi_marb_bp0                             0xb003e240
+#define regi_marb_bp1                             0xb003e280
+#define regi_marb_bp2                             0xb003e2c0
+#define regi_marb_bp3                             0xb003e300
+#define regi_nand_mod                             0xb7014000
+#define regi_p21                                  0xb002e000
+#define regi_p21_mod                              0xb7042000
+#define regi_pci_mod                              0xb7010000
+#define regi_pin_test                             0xb7018000
+#define regi_pinmux                               0xb0038000
+#define regi_sdram_chk                            0xb703e000
+#define regi_sdram_mod                            0xb7012000
+#define regi_ser0                                 0xb0026000
+#define regi_ser1                                 0xb0028000
+#define regi_ser2                                 0xb002a000
+#define regi_ser3                                 0xb002c000
+#define regi_ser_mod0                             0xb7020000
+#define regi_ser_mod1                             0xb7022000
+#define regi_ser_mod2                             0xb7024000
+#define regi_ser_mod3                             0xb7026000
+#define regi_smif_stat                            0xb700e000
+#define regi_sser0                                0xb0022000
+#define regi_sser1                                0xb0024000
+#define regi_sser_mod0                            0xb700a000
+#define regi_sser_mod1                            0xb700c000
+#define regi_strcop                               0xb0030000
+#define regi_strmux                               0xb003a000
+#define regi_strmux_tst                           0xb7040000
+#define regi_tap                                  0xb7002000
+#define regi_timer                                0xb001e000
+#define regi_timer_mod                            0xb7034000
+#define regi_trace                                0xb0040000
+#define regi_usb0                                 0xb7028000
+#define regi_usb1                                 0xb702a000
+#define regi_usb2                                 0xb702c000
+#define regi_usb3                                 0xb702e000
+#define regi_usb_dev                              0xb7030000
+#define regi_utmi_mod0                            0xb7036000
+#define regi_utmi_mod1                            0xb7038000
+#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
new file mode 100644
index 000000000000..10246f49fb28
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
@@ -0,0 +1,142 @@
+#ifndef __rt_trace_defs_asm_h
+#define __rt_trace_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/rt_trace/rtl/rt_regs.r
+ *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
+ *     last modfied: Mon Apr 11 16:09:14 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
+ *      id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope rt_trace, type rw */
+#define reg_rt_trace_rw_cfg___en___lsb 0
+#define reg_rt_trace_rw_cfg___en___width 1
+#define reg_rt_trace_rw_cfg___en___bit 0
+#define reg_rt_trace_rw_cfg___mode___lsb 1
+#define reg_rt_trace_rw_cfg___mode___width 1
+#define reg_rt_trace_rw_cfg___mode___bit 1
+#define reg_rt_trace_rw_cfg___owner___lsb 2
+#define reg_rt_trace_rw_cfg___owner___width 1
+#define reg_rt_trace_rw_cfg___owner___bit 2
+#define reg_rt_trace_rw_cfg___wp___lsb 3
+#define reg_rt_trace_rw_cfg___wp___width 1
+#define reg_rt_trace_rw_cfg___wp___bit 3
+#define reg_rt_trace_rw_cfg___stall___lsb 4
+#define reg_rt_trace_rw_cfg___stall___width 1
+#define reg_rt_trace_rw_cfg___stall___bit 4
+#define reg_rt_trace_rw_cfg___wp_start___lsb 8
+#define reg_rt_trace_rw_cfg___wp_start___width 7
+#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
+#define reg_rt_trace_rw_cfg___wp_stop___width 7
+#define reg_rt_trace_rw_cfg_offset 0
+
+/* Register rw_tap_ctrl, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
+#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
+#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
+#define reg_rt_trace_rw_tap_ctrl_offset 4
+
+/* Register r_tap_stat, scope rt_trace, type r */
+#define reg_rt_trace_r_tap_stat___dav___lsb 0
+#define reg_rt_trace_r_tap_stat___dav___width 1
+#define reg_rt_trace_r_tap_stat___dav___bit 0
+#define reg_rt_trace_r_tap_stat___empty___lsb 1
+#define reg_rt_trace_r_tap_stat___empty___width 1
+#define reg_rt_trace_r_tap_stat___empty___bit 1
+#define reg_rt_trace_r_tap_stat_offset 8
+
+/* Register rw_tap_data, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_data_offset 12
+
+/* Register rw_tap_hdata, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_hdata___op___lsb 0
+#define reg_rt_trace_rw_tap_hdata___op___width 4
+#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
+#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
+#define reg_rt_trace_rw_tap_hdata_offset 16
+
+/* Register r_redir, scope rt_trace, type r */
+#define reg_rt_trace_r_redir_offset 20
+
+
+/* Constants */
+#define regk_rt_trace_brk                         0x0000000c
+#define regk_rt_trace_dbg                         0x00000003
+#define regk_rt_trace_dbgdi                       0x00000004
+#define regk_rt_trace_dbgdo                       0x00000005
+#define regk_rt_trace_gmode                       0x00000000
+#define regk_rt_trace_no                          0x00000000
+#define regk_rt_trace_nop                         0x00000000
+#define regk_rt_trace_normal                      0x00000000
+#define regk_rt_trace_rdmem                       0x00000007
+#define regk_rt_trace_rdmemb                      0x00000009
+#define regk_rt_trace_rdpreg                      0x00000002
+#define regk_rt_trace_rdreg                       0x00000001
+#define regk_rt_trace_rdsreg                      0x00000003
+#define regk_rt_trace_redir                       0x00000006
+#define regk_rt_trace_ret                         0x0000000b
+#define regk_rt_trace_rw_cfg_default              0x00000000
+#define regk_rt_trace_trcfg                       0x00000001
+#define regk_rt_trace_wp                          0x00000001
+#define regk_rt_trace_wp0                         0x00000001
+#define regk_rt_trace_wp1                         0x00000002
+#define regk_rt_trace_wp2                         0x00000004
+#define regk_rt_trace_wp3                         0x00000008
+#define regk_rt_trace_wp4                         0x00000010
+#define regk_rt_trace_wp5                         0x00000020
+#define regk_rt_trace_wp6                         0x00000040
+#define regk_rt_trace_wrmem                       0x00000008
+#define regk_rt_trace_wrmemb                      0x0000000a
+#define regk_rt_trace_wrpreg                      0x00000005
+#define regk_rt_trace_wrreg                       0x00000004
+#define regk_rt_trace_wrsreg                      0x00000006
+#define regk_rt_trace_yes                         0x00000001
+#endif /* __rt_trace_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
new file mode 100644
index 000000000000..4a2808bdf390
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
@@ -0,0 +1,359 @@
+#ifndef __ser_defs_asm_h
+#define __ser_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ser/rtl/ser_regs.r
+ *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
+ *     last modfied: Mon Apr 11 16:09:21 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
+ *      id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tr_ctrl, scope ser, type rw */
+#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
+#define reg_ser_rw_tr_ctrl___base_freq___width 3
+#define reg_ser_rw_tr_ctrl___en___lsb 3
+#define reg_ser_rw_tr_ctrl___en___width 1
+#define reg_ser_rw_tr_ctrl___en___bit 3
+#define reg_ser_rw_tr_ctrl___par___lsb 4
+#define reg_ser_rw_tr_ctrl___par___width 2
+#define reg_ser_rw_tr_ctrl___par_en___lsb 6
+#define reg_ser_rw_tr_ctrl___par_en___width 1
+#define reg_ser_rw_tr_ctrl___par_en___bit 6
+#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
+#define reg_ser_rw_tr_ctrl___data_bits___width 1
+#define reg_ser_rw_tr_ctrl___data_bits___bit 7
+#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
+#define reg_ser_rw_tr_ctrl___stop_bits___width 1
+#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
+#define reg_ser_rw_tr_ctrl___stop___lsb 9
+#define reg_ser_rw_tr_ctrl___stop___width 1
+#define reg_ser_rw_tr_ctrl___stop___bit 9
+#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
+#define reg_ser_rw_tr_ctrl___rts_delay___width 3
+#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
+#define reg_ser_rw_tr_ctrl___rts_setup___width 1
+#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
+#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
+#define reg_ser_rw_tr_ctrl___auto_rts___width 1
+#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
+#define reg_ser_rw_tr_ctrl___txd___lsb 15
+#define reg_ser_rw_tr_ctrl___txd___width 1
+#define reg_ser_rw_tr_ctrl___txd___bit 15
+#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
+#define reg_ser_rw_tr_ctrl___auto_cts___width 1
+#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
+#define reg_ser_rw_tr_ctrl_offset 0
+
+/* Register rw_tr_dma_en, scope ser, type rw */
+#define reg_ser_rw_tr_dma_en___en___lsb 0
+#define reg_ser_rw_tr_dma_en___en___width 1
+#define reg_ser_rw_tr_dma_en___en___bit 0
+#define reg_ser_rw_tr_dma_en_offset 4
+
+/* Register rw_rec_ctrl, scope ser, type rw */
+#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
+#define reg_ser_rw_rec_ctrl___base_freq___width 3
+#define reg_ser_rw_rec_ctrl___en___lsb 3
+#define reg_ser_rw_rec_ctrl___en___width 1
+#define reg_ser_rw_rec_ctrl___en___bit 3
+#define reg_ser_rw_rec_ctrl___par___lsb 4
+#define reg_ser_rw_rec_ctrl___par___width 2
+#define reg_ser_rw_rec_ctrl___par_en___lsb 6
+#define reg_ser_rw_rec_ctrl___par_en___width 1
+#define reg_ser_rw_rec_ctrl___par_en___bit 6
+#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
+#define reg_ser_rw_rec_ctrl___data_bits___width 1
+#define reg_ser_rw_rec_ctrl___data_bits___bit 7
+#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
+#define reg_ser_rw_rec_ctrl___dma_mode___width 1
+#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
+#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
+#define reg_ser_rw_rec_ctrl___dma_err___width 1
+#define reg_ser_rw_rec_ctrl___dma_err___bit 9
+#define reg_ser_rw_rec_ctrl___sampling___lsb 10
+#define reg_ser_rw_rec_ctrl___sampling___width 1
+#define reg_ser_rw_rec_ctrl___sampling___bit 10
+#define reg_ser_rw_rec_ctrl___timeout___lsb 11
+#define reg_ser_rw_rec_ctrl___timeout___width 3
+#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
+#define reg_ser_rw_rec_ctrl___auto_eop___width 1
+#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
+#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
+#define reg_ser_rw_rec_ctrl___half_duplex___width 1
+#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
+#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
+#define reg_ser_rw_rec_ctrl___rts_n___width 1
+#define reg_ser_rw_rec_ctrl___rts_n___bit 16
+#define reg_ser_rw_rec_ctrl___loopback___lsb 17
+#define reg_ser_rw_rec_ctrl___loopback___width 1
+#define reg_ser_rw_rec_ctrl___loopback___bit 17
+#define reg_ser_rw_rec_ctrl_offset 8
+
+/* Register rw_tr_baud_div, scope ser, type rw */
+#define reg_ser_rw_tr_baud_div___div___lsb 0
+#define reg_ser_rw_tr_baud_div___div___width 16
+#define reg_ser_rw_tr_baud_div_offset 12
+
+/* Register rw_rec_baud_div, scope ser, type rw */
+#define reg_ser_rw_rec_baud_div___div___lsb 0
+#define reg_ser_rw_rec_baud_div___div___width 16
+#define reg_ser_rw_rec_baud_div_offset 16
+
+/* Register rw_xoff, scope ser, type rw */
+#define reg_ser_rw_xoff___chr___lsb 0
+#define reg_ser_rw_xoff___chr___width 8
+#define reg_ser_rw_xoff___automatic___lsb 8
+#define reg_ser_rw_xoff___automatic___width 1
+#define reg_ser_rw_xoff___automatic___bit 8
+#define reg_ser_rw_xoff_offset 20
+
+/* Register rw_xoff_clr, scope ser, type rw */
+#define reg_ser_rw_xoff_clr___clr___lsb 0
+#define reg_ser_rw_xoff_clr___clr___width 1
+#define reg_ser_rw_xoff_clr___clr___bit 0
+#define reg_ser_rw_xoff_clr_offset 24
+
+/* Register rw_dout, scope ser, type rw */
+#define reg_ser_rw_dout___data___lsb 0
+#define reg_ser_rw_dout___data___width 8
+#define reg_ser_rw_dout_offset 28
+
+/* Register rs_stat_din, scope ser, type rs */
+#define reg_ser_rs_stat_din___data___lsb 0
+#define reg_ser_rs_stat_din___data___width 8
+#define reg_ser_rs_stat_din___dav___lsb 16
+#define reg_ser_rs_stat_din___dav___width 1
+#define reg_ser_rs_stat_din___dav___bit 16
+#define reg_ser_rs_stat_din___framing_err___lsb 17
+#define reg_ser_rs_stat_din___framing_err___width 1
+#define reg_ser_rs_stat_din___framing_err___bit 17
+#define reg_ser_rs_stat_din___par_err___lsb 18
+#define reg_ser_rs_stat_din___par_err___width 1
+#define reg_ser_rs_stat_din___par_err___bit 18
+#define reg_ser_rs_stat_din___orun___lsb 19
+#define reg_ser_rs_stat_din___orun___width 1
+#define reg_ser_rs_stat_din___orun___bit 19
+#define reg_ser_rs_stat_din___rec_err___lsb 20
+#define reg_ser_rs_stat_din___rec_err___width 1
+#define reg_ser_rs_stat_din___rec_err___bit 20
+#define reg_ser_rs_stat_din___rxd___lsb 21
+#define reg_ser_rs_stat_din___rxd___width 1
+#define reg_ser_rs_stat_din___rxd___bit 21
+#define reg_ser_rs_stat_din___tr_idle___lsb 22
+#define reg_ser_rs_stat_din___tr_idle___width 1
+#define reg_ser_rs_stat_din___tr_idle___bit 22
+#define reg_ser_rs_stat_din___tr_empty___lsb 23
+#define reg_ser_rs_stat_din___tr_empty___width 1
+#define reg_ser_rs_stat_din___tr_empty___bit 23
+#define reg_ser_rs_stat_din___tr_rdy___lsb 24
+#define reg_ser_rs_stat_din___tr_rdy___width 1
+#define reg_ser_rs_stat_din___tr_rdy___bit 24
+#define reg_ser_rs_stat_din___cts_n___lsb 25
+#define reg_ser_rs_stat_din___cts_n___width 1
+#define reg_ser_rs_stat_din___cts_n___bit 25
+#define reg_ser_rs_stat_din___xoff_detect___lsb 26
+#define reg_ser_rs_stat_din___xoff_detect___width 1
+#define reg_ser_rs_stat_din___xoff_detect___bit 26
+#define reg_ser_rs_stat_din___rts_n___lsb 27
+#define reg_ser_rs_stat_din___rts_n___width 1
+#define reg_ser_rs_stat_din___rts_n___bit 27
+#define reg_ser_rs_stat_din___txd___lsb 28
+#define reg_ser_rs_stat_din___txd___width 1
+#define reg_ser_rs_stat_din___txd___bit 28
+#define reg_ser_rs_stat_din_offset 32
+
+/* Register r_stat_din, scope ser, type r */
+#define reg_ser_r_stat_din___data___lsb 0
+#define reg_ser_r_stat_din___data___width 8
+#define reg_ser_r_stat_din___dav___lsb 16
+#define reg_ser_r_stat_din___dav___width 1
+#define reg_ser_r_stat_din___dav___bit 16
+#define reg_ser_r_stat_din___framing_err___lsb 17
+#define reg_ser_r_stat_din___framing_err___width 1
+#define reg_ser_r_stat_din___framing_err___bit 17
+#define reg_ser_r_stat_din___par_err___lsb 18
+#define reg_ser_r_stat_din___par_err___width 1
+#define reg_ser_r_stat_din___par_err___bit 18
+#define reg_ser_r_stat_din___orun___lsb 19
+#define reg_ser_r_stat_din___orun___width 1
+#define reg_ser_r_stat_din___orun___bit 19
+#define reg_ser_r_stat_din___rec_err___lsb 20
+#define reg_ser_r_stat_din___rec_err___width 1
+#define reg_ser_r_stat_din___rec_err___bit 20
+#define reg_ser_r_stat_din___rxd___lsb 21
+#define reg_ser_r_stat_din___rxd___width 1
+#define reg_ser_r_stat_din___rxd___bit 21
+#define reg_ser_r_stat_din___tr_idle___lsb 22
+#define reg_ser_r_stat_din___tr_idle___width 1
+#define reg_ser_r_stat_din___tr_idle___bit 22
+#define reg_ser_r_stat_din___tr_empty___lsb 23
+#define reg_ser_r_stat_din___tr_empty___width 1
+#define reg_ser_r_stat_din___tr_empty___bit 23
+#define reg_ser_r_stat_din___tr_rdy___lsb 24
+#define reg_ser_r_stat_din___tr_rdy___width 1
+#define reg_ser_r_stat_din___tr_rdy___bit 24
+#define reg_ser_r_stat_din___cts_n___lsb 25
+#define reg_ser_r_stat_din___cts_n___width 1
+#define reg_ser_r_stat_din___cts_n___bit 25
+#define reg_ser_r_stat_din___xoff_detect___lsb 26
+#define reg_ser_r_stat_din___xoff_detect___width 1
+#define reg_ser_r_stat_din___xoff_detect___bit 26
+#define reg_ser_r_stat_din___rts_n___lsb 27
+#define reg_ser_r_stat_din___rts_n___width 1
+#define reg_ser_r_stat_din___rts_n___bit 27
+#define reg_ser_r_stat_din___txd___lsb 28
+#define reg_ser_r_stat_din___txd___width 1
+#define reg_ser_r_stat_din___txd___bit 28
+#define reg_ser_r_stat_din_offset 36
+
+/* Register rw_rec_eop, scope ser, type rw */
+#define reg_ser_rw_rec_eop___set___lsb 0
+#define reg_ser_rw_rec_eop___set___width 1
+#define reg_ser_rw_rec_eop___set___bit 0
+#define reg_ser_rw_rec_eop_offset 40
+
+/* Register rw_intr_mask, scope ser, type rw */
+#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
+#define reg_ser_rw_intr_mask___tr_rdy___width 1
+#define reg_ser_rw_intr_mask___tr_rdy___bit 0
+#define reg_ser_rw_intr_mask___tr_empty___lsb 1
+#define reg_ser_rw_intr_mask___tr_empty___width 1
+#define reg_ser_rw_intr_mask___tr_empty___bit 1
+#define reg_ser_rw_intr_mask___tr_idle___lsb 2
+#define reg_ser_rw_intr_mask___tr_idle___width 1
+#define reg_ser_rw_intr_mask___tr_idle___bit 2
+#define reg_ser_rw_intr_mask___dav___lsb 3
+#define reg_ser_rw_intr_mask___dav___width 1
+#define reg_ser_rw_intr_mask___dav___bit 3
+#define reg_ser_rw_intr_mask_offset 44
+
+/* Register rw_ack_intr, scope ser, type rw */
+#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
+#define reg_ser_rw_ack_intr___tr_rdy___width 1
+#define reg_ser_rw_ack_intr___tr_rdy___bit 0
+#define reg_ser_rw_ack_intr___tr_empty___lsb 1
+#define reg_ser_rw_ack_intr___tr_empty___width 1
+#define reg_ser_rw_ack_intr___tr_empty___bit 1
+#define reg_ser_rw_ack_intr___tr_idle___lsb 2
+#define reg_ser_rw_ack_intr___tr_idle___width 1
+#define reg_ser_rw_ack_intr___tr_idle___bit 2
+#define reg_ser_rw_ack_intr___dav___lsb 3
+#define reg_ser_rw_ack_intr___dav___width 1
+#define reg_ser_rw_ack_intr___dav___bit 3
+#define reg_ser_rw_ack_intr_offset 48
+
+/* Register r_intr, scope ser, type r */
+#define reg_ser_r_intr___tr_rdy___lsb 0
+#define reg_ser_r_intr___tr_rdy___width 1
+#define reg_ser_r_intr___tr_rdy___bit 0
+#define reg_ser_r_intr___tr_empty___lsb 1
+#define reg_ser_r_intr___tr_empty___width 1
+#define reg_ser_r_intr___tr_empty___bit 1
+#define reg_ser_r_intr___tr_idle___lsb 2
+#define reg_ser_r_intr___tr_idle___width 1
+#define reg_ser_r_intr___tr_idle___bit 2
+#define reg_ser_r_intr___dav___lsb 3
+#define reg_ser_r_intr___dav___width 1
+#define reg_ser_r_intr___dav___bit 3
+#define reg_ser_r_intr_offset 52
+
+/* Register r_masked_intr, scope ser, type r */
+#define reg_ser_r_masked_intr___tr_rdy___lsb 0
+#define reg_ser_r_masked_intr___tr_rdy___width 1
+#define reg_ser_r_masked_intr___tr_rdy___bit 0
+#define reg_ser_r_masked_intr___tr_empty___lsb 1
+#define reg_ser_r_masked_intr___tr_empty___width 1
+#define reg_ser_r_masked_intr___tr_empty___bit 1
+#define reg_ser_r_masked_intr___tr_idle___lsb 2
+#define reg_ser_r_masked_intr___tr_idle___width 1
+#define reg_ser_r_masked_intr___tr_idle___bit 2
+#define reg_ser_r_masked_intr___dav___lsb 3
+#define reg_ser_r_masked_intr___dav___width 1
+#define reg_ser_r_masked_intr___dav___bit 3
+#define reg_ser_r_masked_intr_offset 56
+
+
+/* Constants */
+#define regk_ser_active                           0x00000000
+#define regk_ser_bits1                            0x00000000
+#define regk_ser_bits2                            0x00000001
+#define regk_ser_bits7                            0x00000001
+#define regk_ser_bits8                            0x00000000
+#define regk_ser_del0_5                           0x00000000
+#define regk_ser_del1                             0x00000001
+#define regk_ser_del1_5                           0x00000002
+#define regk_ser_del2                             0x00000003
+#define regk_ser_del2_5                           0x00000004
+#define regk_ser_del3                             0x00000005
+#define regk_ser_del3_5                           0x00000006
+#define regk_ser_del4                             0x00000007
+#define regk_ser_even                             0x00000000
+#define regk_ser_ext                              0x00000001
+#define regk_ser_f100                             0x00000007
+#define regk_ser_f29_493                          0x00000004
+#define regk_ser_f32                              0x00000005
+#define regk_ser_f32_768                          0x00000006
+#define regk_ser_ignore                           0x00000001
+#define regk_ser_inactive                         0x00000001
+#define regk_ser_majority                         0x00000001
+#define regk_ser_mark                             0x00000002
+#define regk_ser_middle                           0x00000000
+#define regk_ser_no                               0x00000000
+#define regk_ser_odd                              0x00000001
+#define regk_ser_off                              0x00000000
+#define regk_ser_rw_intr_mask_default             0x00000000
+#define regk_ser_rw_rec_baud_div_default          0x00000000
+#define regk_ser_rw_rec_ctrl_default              0x00010000
+#define regk_ser_rw_tr_baud_div_default           0x00000000
+#define regk_ser_rw_tr_ctrl_default               0x00008000
+#define regk_ser_rw_tr_dma_en_default             0x00000000
+#define regk_ser_rw_xoff_default                  0x00000000
+#define regk_ser_space                            0x00000003
+#define regk_ser_stop                             0x00000000
+#define regk_ser_yes                              0x00000001
+#endif /* __ser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
new file mode 100644
index 000000000000..27d4d91b3abd
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
@@ -0,0 +1,462 @@
+#ifndef __sser_defs_asm_h
+#define __sser_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/syncser/rtl/sser_regs.r
+ *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
+ *     last modfied: Mon Apr 11 16:09:48 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
+ *      id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope sser, type rw */
+#define reg_sser_rw_cfg___clk_div___lsb 0
+#define reg_sser_rw_cfg___clk_div___width 16
+#define reg_sser_rw_cfg___base_freq___lsb 16
+#define reg_sser_rw_cfg___base_freq___width 3
+#define reg_sser_rw_cfg___gate_clk___lsb 19
+#define reg_sser_rw_cfg___gate_clk___width 1
+#define reg_sser_rw_cfg___gate_clk___bit 19
+#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
+#define reg_sser_rw_cfg___clkgate_ctrl___width 1
+#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
+#define reg_sser_rw_cfg___clkgate_in___lsb 21
+#define reg_sser_rw_cfg___clkgate_in___width 1
+#define reg_sser_rw_cfg___clkgate_in___bit 21
+#define reg_sser_rw_cfg___clk_dir___lsb 22
+#define reg_sser_rw_cfg___clk_dir___width 1
+#define reg_sser_rw_cfg___clk_dir___bit 22
+#define reg_sser_rw_cfg___clk_od_mode___lsb 23
+#define reg_sser_rw_cfg___clk_od_mode___width 1
+#define reg_sser_rw_cfg___clk_od_mode___bit 23
+#define reg_sser_rw_cfg___out_clk_pol___lsb 24
+#define reg_sser_rw_cfg___out_clk_pol___width 1
+#define reg_sser_rw_cfg___out_clk_pol___bit 24
+#define reg_sser_rw_cfg___out_clk_src___lsb 25
+#define reg_sser_rw_cfg___out_clk_src___width 2
+#define reg_sser_rw_cfg___clk_in_sel___lsb 27
+#define reg_sser_rw_cfg___clk_in_sel___width 1
+#define reg_sser_rw_cfg___clk_in_sel___bit 27
+#define reg_sser_rw_cfg___hold_pol___lsb 28
+#define reg_sser_rw_cfg___hold_pol___width 1
+#define reg_sser_rw_cfg___hold_pol___bit 28
+#define reg_sser_rw_cfg___prepare___lsb 29
+#define reg_sser_rw_cfg___prepare___width 1
+#define reg_sser_rw_cfg___prepare___bit 29
+#define reg_sser_rw_cfg___en___lsb 30
+#define reg_sser_rw_cfg___en___width 1
+#define reg_sser_rw_cfg___en___bit 30
+#define reg_sser_rw_cfg_offset 0
+
+/* Register rw_frm_cfg, scope sser, type rw */
+#define reg_sser_rw_frm_cfg___wordrate___lsb 0
+#define reg_sser_rw_frm_cfg___wordrate___width 10
+#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
+#define reg_sser_rw_frm_cfg___rec_delay___width 3
+#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
+#define reg_sser_rw_frm_cfg___tr_delay___width 3
+#define reg_sser_rw_frm_cfg___early_wend___lsb 16
+#define reg_sser_rw_frm_cfg___early_wend___width 1
+#define reg_sser_rw_frm_cfg___early_wend___bit 16
+#define reg_sser_rw_frm_cfg___level___lsb 17
+#define reg_sser_rw_frm_cfg___level___width 2
+#define reg_sser_rw_frm_cfg___type___lsb 19
+#define reg_sser_rw_frm_cfg___type___width 1
+#define reg_sser_rw_frm_cfg___type___bit 19
+#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
+#define reg_sser_rw_frm_cfg___clk_pol___width 1
+#define reg_sser_rw_frm_cfg___clk_pol___bit 20
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
+#define reg_sser_rw_frm_cfg___clk_src___lsb 22
+#define reg_sser_rw_frm_cfg___clk_src___width 1
+#define reg_sser_rw_frm_cfg___clk_src___bit 22
+#define reg_sser_rw_frm_cfg___out_off___lsb 23
+#define reg_sser_rw_frm_cfg___out_off___width 1
+#define reg_sser_rw_frm_cfg___out_off___bit 23
+#define reg_sser_rw_frm_cfg___out_on___lsb 24
+#define reg_sser_rw_frm_cfg___out_on___width 1
+#define reg_sser_rw_frm_cfg___out_on___bit 24
+#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
+#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
+#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
+#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
+#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
+#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
+#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
+#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
+#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
+#define reg_sser_rw_frm_cfg___status_pin_use___width 2
+#define reg_sser_rw_frm_cfg_offset 4
+
+/* Register rw_tr_cfg, scope sser, type rw */
+#define reg_sser_rw_tr_cfg___tr_en___lsb 0
+#define reg_sser_rw_tr_cfg___tr_en___width 1
+#define reg_sser_rw_tr_cfg___tr_en___bit 0
+#define reg_sser_rw_tr_cfg___stop___lsb 1
+#define reg_sser_rw_tr_cfg___stop___width 1
+#define reg_sser_rw_tr_cfg___stop___bit 1
+#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
+#define reg_sser_rw_tr_cfg___urun_stop___width 1
+#define reg_sser_rw_tr_cfg___urun_stop___bit 2
+#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
+#define reg_sser_rw_tr_cfg___eop_stop___width 1
+#define reg_sser_rw_tr_cfg___eop_stop___bit 3
+#define reg_sser_rw_tr_cfg___sample_size___lsb 4
+#define reg_sser_rw_tr_cfg___sample_size___width 6
+#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
+#define reg_sser_rw_tr_cfg___sh_dir___width 1
+#define reg_sser_rw_tr_cfg___sh_dir___bit 10
+#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
+#define reg_sser_rw_tr_cfg___clk_pol___width 1
+#define reg_sser_rw_tr_cfg___clk_pol___bit 11
+#define reg_sser_rw_tr_cfg___clk_src___lsb 12
+#define reg_sser_rw_tr_cfg___clk_src___width 1
+#define reg_sser_rw_tr_cfg___clk_src___bit 12
+#define reg_sser_rw_tr_cfg___use_dma___lsb 13
+#define reg_sser_rw_tr_cfg___use_dma___width 1
+#define reg_sser_rw_tr_cfg___use_dma___bit 13
+#define reg_sser_rw_tr_cfg___mode___lsb 14
+#define reg_sser_rw_tr_cfg___mode___width 2
+#define reg_sser_rw_tr_cfg___frm_src___lsb 16
+#define reg_sser_rw_tr_cfg___frm_src___width 1
+#define reg_sser_rw_tr_cfg___frm_src___bit 16
+#define reg_sser_rw_tr_cfg___use60958___lsb 17
+#define reg_sser_rw_tr_cfg___use60958___width 1
+#define reg_sser_rw_tr_cfg___use60958___bit 17
+#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
+#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
+#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
+#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
+#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
+#define reg_sser_rw_tr_cfg___use_md___lsb 21
+#define reg_sser_rw_tr_cfg___use_md___width 1
+#define reg_sser_rw_tr_cfg___use_md___bit 21
+#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
+#define reg_sser_rw_tr_cfg___dual_i2s___width 1
+#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
+#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
+#define reg_sser_rw_tr_cfg___data_pin_use___width 2
+#define reg_sser_rw_tr_cfg___od_mode___lsb 25
+#define reg_sser_rw_tr_cfg___od_mode___width 1
+#define reg_sser_rw_tr_cfg___od_mode___bit 25
+#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
+#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
+#define reg_sser_rw_tr_cfg_offset 8
+
+/* Register rw_rec_cfg, scope sser, type rw */
+#define reg_sser_rw_rec_cfg___rec_en___lsb 0
+#define reg_sser_rw_rec_cfg___rec_en___width 1
+#define reg_sser_rw_rec_cfg___rec_en___bit 0
+#define reg_sser_rw_rec_cfg___force_eop___lsb 1
+#define reg_sser_rw_rec_cfg___force_eop___width 1
+#define reg_sser_rw_rec_cfg___force_eop___bit 1
+#define reg_sser_rw_rec_cfg___stop___lsb 2
+#define reg_sser_rw_rec_cfg___stop___width 1
+#define reg_sser_rw_rec_cfg___stop___bit 2
+#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
+#define reg_sser_rw_rec_cfg___orun_stop___width 1
+#define reg_sser_rw_rec_cfg___orun_stop___bit 3
+#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
+#define reg_sser_rw_rec_cfg___eop_stop___width 1
+#define reg_sser_rw_rec_cfg___eop_stop___bit 4
+#define reg_sser_rw_rec_cfg___sample_size___lsb 5
+#define reg_sser_rw_rec_cfg___sample_size___width 6
+#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
+#define reg_sser_rw_rec_cfg___sh_dir___width 1
+#define reg_sser_rw_rec_cfg___sh_dir___bit 11
+#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
+#define reg_sser_rw_rec_cfg___clk_pol___width 1
+#define reg_sser_rw_rec_cfg___clk_pol___bit 12
+#define reg_sser_rw_rec_cfg___clk_src___lsb 13
+#define reg_sser_rw_rec_cfg___clk_src___width 1
+#define reg_sser_rw_rec_cfg___clk_src___bit 13
+#define reg_sser_rw_rec_cfg___use_dma___lsb 14
+#define reg_sser_rw_rec_cfg___use_dma___width 1
+#define reg_sser_rw_rec_cfg___use_dma___bit 14
+#define reg_sser_rw_rec_cfg___mode___lsb 15
+#define reg_sser_rw_rec_cfg___mode___width 2
+#define reg_sser_rw_rec_cfg___frm_src___lsb 17
+#define reg_sser_rw_rec_cfg___frm_src___width 2
+#define reg_sser_rw_rec_cfg___use60958___lsb 19
+#define reg_sser_rw_rec_cfg___use60958___width 1
+#define reg_sser_rw_rec_cfg___use60958___bit 19
+#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
+#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
+#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
+#define reg_sser_rw_rec_cfg___slave2_en___width 1
+#define reg_sser_rw_rec_cfg___slave2_en___bit 25
+#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
+#define reg_sser_rw_rec_cfg___slave3_en___width 1
+#define reg_sser_rw_rec_cfg___slave3_en___bit 26
+#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
+#define reg_sser_rw_rec_cfg___fifo_thr___width 2
+#define reg_sser_rw_rec_cfg_offset 12
+
+/* Register rw_tr_data, scope sser, type rw */
+#define reg_sser_rw_tr_data___data___lsb 0
+#define reg_sser_rw_tr_data___data___width 16
+#define reg_sser_rw_tr_data___md___lsb 16
+#define reg_sser_rw_tr_data___md___width 1
+#define reg_sser_rw_tr_data___md___bit 16
+#define reg_sser_rw_tr_data_offset 16
+
+/* Register r_rec_data, scope sser, type r */
+#define reg_sser_r_rec_data___data___lsb 0
+#define reg_sser_r_rec_data___data___width 16
+#define reg_sser_r_rec_data___md___lsb 16
+#define reg_sser_r_rec_data___md___width 1
+#define reg_sser_r_rec_data___md___bit 16
+#define reg_sser_r_rec_data___ext_clk___lsb 17
+#define reg_sser_r_rec_data___ext_clk___width 1
+#define reg_sser_r_rec_data___ext_clk___bit 17
+#define reg_sser_r_rec_data___status_in___lsb 18
+#define reg_sser_r_rec_data___status_in___width 1
+#define reg_sser_r_rec_data___status_in___bit 18
+#define reg_sser_r_rec_data___frame_in___lsb 19
+#define reg_sser_r_rec_data___frame_in___width 1
+#define reg_sser_r_rec_data___frame_in___bit 19
+#define reg_sser_r_rec_data___din___lsb 20
+#define reg_sser_r_rec_data___din___width 1
+#define reg_sser_r_rec_data___din___bit 20
+#define reg_sser_r_rec_data___data_in___lsb 21
+#define reg_sser_r_rec_data___data_in___width 1
+#define reg_sser_r_rec_data___data_in___bit 21
+#define reg_sser_r_rec_data___clk_in___lsb 22
+#define reg_sser_r_rec_data___clk_in___width 1
+#define reg_sser_r_rec_data___clk_in___bit 22
+#define reg_sser_r_rec_data_offset 20
+
+/* Register rw_extra, scope sser, type rw */
+#define reg_sser_rw_extra___clkoff_cycles___lsb 0
+#define reg_sser_rw_extra___clkoff_cycles___width 20
+#define reg_sser_rw_extra___clkoff_en___lsb 20
+#define reg_sser_rw_extra___clkoff_en___width 1
+#define reg_sser_rw_extra___clkoff_en___bit 20
+#define reg_sser_rw_extra___clkon_en___lsb 21
+#define reg_sser_rw_extra___clkon_en___width 1
+#define reg_sser_rw_extra___clkon_en___bit 21
+#define reg_sser_rw_extra___dout_delay___lsb 22
+#define reg_sser_rw_extra___dout_delay___width 5
+#define reg_sser_rw_extra_offset 24
+
+/* Register rw_intr_mask, scope sser, type rw */
+#define reg_sser_rw_intr_mask___trdy___lsb 0
+#define reg_sser_rw_intr_mask___trdy___width 1
+#define reg_sser_rw_intr_mask___trdy___bit 0
+#define reg_sser_rw_intr_mask___rdav___lsb 1
+#define reg_sser_rw_intr_mask___rdav___width 1
+#define reg_sser_rw_intr_mask___rdav___bit 1
+#define reg_sser_rw_intr_mask___tidle___lsb 2
+#define reg_sser_rw_intr_mask___tidle___width 1
+#define reg_sser_rw_intr_mask___tidle___bit 2
+#define reg_sser_rw_intr_mask___rstop___lsb 3
+#define reg_sser_rw_intr_mask___rstop___width 1
+#define reg_sser_rw_intr_mask___rstop___bit 3
+#define reg_sser_rw_intr_mask___urun___lsb 4
+#define reg_sser_rw_intr_mask___urun___width 1
+#define reg_sser_rw_intr_mask___urun___bit 4
+#define reg_sser_rw_intr_mask___orun___lsb 5
+#define reg_sser_rw_intr_mask___orun___width 1
+#define reg_sser_rw_intr_mask___orun___bit 5
+#define reg_sser_rw_intr_mask___md_rec___lsb 6
+#define reg_sser_rw_intr_mask___md_rec___width 1
+#define reg_sser_rw_intr_mask___md_rec___bit 6
+#define reg_sser_rw_intr_mask___md_sent___lsb 7
+#define reg_sser_rw_intr_mask___md_sent___width 1
+#define reg_sser_rw_intr_mask___md_sent___bit 7
+#define reg_sser_rw_intr_mask___r958err___lsb 8
+#define reg_sser_rw_intr_mask___r958err___width 1
+#define reg_sser_rw_intr_mask___r958err___bit 8
+#define reg_sser_rw_intr_mask_offset 28
+
+/* Register rw_ack_intr, scope sser, type rw */
+#define reg_sser_rw_ack_intr___trdy___lsb 0
+#define reg_sser_rw_ack_intr___trdy___width 1
+#define reg_sser_rw_ack_intr___trdy___bit 0
+#define reg_sser_rw_ack_intr___rdav___lsb 1
+#define reg_sser_rw_ack_intr___rdav___width 1
+#define reg_sser_rw_ack_intr___rdav___bit 1
+#define reg_sser_rw_ack_intr___tidle___lsb 2
+#define reg_sser_rw_ack_intr___tidle___width 1
+#define reg_sser_rw_ack_intr___tidle___bit 2
+#define reg_sser_rw_ack_intr___rstop___lsb 3
+#define reg_sser_rw_ack_intr___rstop___width 1
+#define reg_sser_rw_ack_intr___rstop___bit 3
+#define reg_sser_rw_ack_intr___urun___lsb 4
+#define reg_sser_rw_ack_intr___urun___width 1
+#define reg_sser_rw_ack_intr___urun___bit 4
+#define reg_sser_rw_ack_intr___orun___lsb 5
+#define reg_sser_rw_ack_intr___orun___width 1
+#define reg_sser_rw_ack_intr___orun___bit 5
+#define reg_sser_rw_ack_intr___md_rec___lsb 6
+#define reg_sser_rw_ack_intr___md_rec___width 1
+#define reg_sser_rw_ack_intr___md_rec___bit 6
+#define reg_sser_rw_ack_intr___md_sent___lsb 7
+#define reg_sser_rw_ack_intr___md_sent___width 1
+#define reg_sser_rw_ack_intr___md_sent___bit 7
+#define reg_sser_rw_ack_intr___r958err___lsb 8
+#define reg_sser_rw_ack_intr___r958err___width 1
+#define reg_sser_rw_ack_intr___r958err___bit 8
+#define reg_sser_rw_ack_intr_offset 32
+
+/* Register r_intr, scope sser, type r */
+#define reg_sser_r_intr___trdy___lsb 0
+#define reg_sser_r_intr___trdy___width 1
+#define reg_sser_r_intr___trdy___bit 0
+#define reg_sser_r_intr___rdav___lsb 1
+#define reg_sser_r_intr___rdav___width 1
+#define reg_sser_r_intr___rdav___bit 1
+#define reg_sser_r_intr___tidle___lsb 2
+#define reg_sser_r_intr___tidle___width 1
+#define reg_sser_r_intr___tidle___bit 2
+#define reg_sser_r_intr___rstop___lsb 3
+#define reg_sser_r_intr___rstop___width 1
+#define reg_sser_r_intr___rstop___bit 3
+#define reg_sser_r_intr___urun___lsb 4
+#define reg_sser_r_intr___urun___width 1
+#define reg_sser_r_intr___urun___bit 4
+#define reg_sser_r_intr___orun___lsb 5
+#define reg_sser_r_intr___orun___width 1
+#define reg_sser_r_intr___orun___bit 5
+#define reg_sser_r_intr___md_rec___lsb 6
+#define reg_sser_r_intr___md_rec___width 1
+#define reg_sser_r_intr___md_rec___bit 6
+#define reg_sser_r_intr___md_sent___lsb 7
+#define reg_sser_r_intr___md_sent___width 1
+#define reg_sser_r_intr___md_sent___bit 7
+#define reg_sser_r_intr___r958err___lsb 8
+#define reg_sser_r_intr___r958err___width 1
+#define reg_sser_r_intr___r958err___bit 8
+#define reg_sser_r_intr_offset 36
+
+/* Register r_masked_intr, scope sser, type r */
+#define reg_sser_r_masked_intr___trdy___lsb 0
+#define reg_sser_r_masked_intr___trdy___width 1
+#define reg_sser_r_masked_intr___trdy___bit 0
+#define reg_sser_r_masked_intr___rdav___lsb 1
+#define reg_sser_r_masked_intr___rdav___width 1
+#define reg_sser_r_masked_intr___rdav___bit 1
+#define reg_sser_r_masked_intr___tidle___lsb 2
+#define reg_sser_r_masked_intr___tidle___width 1
+#define reg_sser_r_masked_intr___tidle___bit 2
+#define reg_sser_r_masked_intr___rstop___lsb 3
+#define reg_sser_r_masked_intr___rstop___width 1
+#define reg_sser_r_masked_intr___rstop___bit 3
+#define reg_sser_r_masked_intr___urun___lsb 4
+#define reg_sser_r_masked_intr___urun___width 1
+#define reg_sser_r_masked_intr___urun___bit 4
+#define reg_sser_r_masked_intr___orun___lsb 5
+#define reg_sser_r_masked_intr___orun___width 1
+#define reg_sser_r_masked_intr___orun___bit 5
+#define reg_sser_r_masked_intr___md_rec___lsb 6
+#define reg_sser_r_masked_intr___md_rec___width 1
+#define reg_sser_r_masked_intr___md_rec___bit 6
+#define reg_sser_r_masked_intr___md_sent___lsb 7
+#define reg_sser_r_masked_intr___md_sent___width 1
+#define reg_sser_r_masked_intr___md_sent___bit 7
+#define reg_sser_r_masked_intr___r958err___lsb 8
+#define reg_sser_r_masked_intr___r958err___width 1
+#define reg_sser_r_masked_intr___r958err___bit 8
+#define reg_sser_r_masked_intr_offset 40
+
+
+/* Constants */
+#define regk_sser_both                            0x00000002
+#define regk_sser_bulk                            0x00000001
+#define regk_sser_clk100                          0x00000000
+#define regk_sser_clk_in                          0x00000000
+#define regk_sser_const0                          0x00000003
+#define regk_sser_dout                            0x00000002
+#define regk_sser_edge                            0x00000000
+#define regk_sser_ext                             0x00000001
+#define regk_sser_ext_clk                         0x00000001
+#define regk_sser_f100                            0x00000000
+#define regk_sser_f29_493                         0x00000004
+#define regk_sser_f32                             0x00000005
+#define regk_sser_f32_768                         0x00000006
+#define regk_sser_frm                             0x00000003
+#define regk_sser_gio0                            0x00000000
+#define regk_sser_gio1                            0x00000001
+#define regk_sser_hispeed                         0x00000001
+#define regk_sser_hold                            0x00000002
+#define regk_sser_in                              0x00000000
+#define regk_sser_inf                             0x00000003
+#define regk_sser_intern                          0x00000000
+#define regk_sser_intern_clk                      0x00000001
+#define regk_sser_intern_tb                       0x00000000
+#define regk_sser_iso                             0x00000000
+#define regk_sser_level                           0x00000001
+#define regk_sser_lospeed                         0x00000000
+#define regk_sser_lsbfirst                        0x00000000
+#define regk_sser_msbfirst                        0x00000001
+#define regk_sser_neg                             0x00000001
+#define regk_sser_neg_lo                          0x00000000
+#define regk_sser_no                              0x00000000
+#define regk_sser_no_clk                          0x00000007
+#define regk_sser_nojitter                        0x00000002
+#define regk_sser_out                             0x00000001
+#define regk_sser_pos                             0x00000000
+#define regk_sser_pos_hi                          0x00000001
+#define regk_sser_rec                             0x00000000
+#define regk_sser_rw_cfg_default                  0x00000000
+#define regk_sser_rw_extra_default                0x00000000
+#define regk_sser_rw_frm_cfg_default              0x00000000
+#define regk_sser_rw_intr_mask_default            0x00000000
+#define regk_sser_rw_rec_cfg_default              0x00000000
+#define regk_sser_rw_tr_cfg_default               0x01800000
+#define regk_sser_rw_tr_data_default              0x00000000
+#define regk_sser_thr16                           0x00000001
+#define regk_sser_thr32                           0x00000002
+#define regk_sser_thr8                            0x00000000
+#define regk_sser_tr                              0x00000001
+#define regk_sser_ts_out                          0x00000003
+#define regk_sser_tx_bulk                         0x00000002
+#define regk_sser_wiresave                        0x00000002
+#define regk_sser_yes                             0x00000001
+#endif /* __sser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
new file mode 100644
index 000000000000..55083e6aec93
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
@@ -0,0 +1,84 @@
+#ifndef __strcop_defs_asm_h
+#define __strcop_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strcop/rtl/strcop_regs.r
+ *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
+ *     last modfied: Mon Apr 11 16:09:38 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
+ *      id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope strcop, type rw */
+#define reg_strcop_rw_cfg___td3___lsb 0
+#define reg_strcop_rw_cfg___td3___width 1
+#define reg_strcop_rw_cfg___td3___bit 0
+#define reg_strcop_rw_cfg___td2___lsb 1
+#define reg_strcop_rw_cfg___td2___width 1
+#define reg_strcop_rw_cfg___td2___bit 1
+#define reg_strcop_rw_cfg___td1___lsb 2
+#define reg_strcop_rw_cfg___td1___width 1
+#define reg_strcop_rw_cfg___td1___bit 2
+#define reg_strcop_rw_cfg___ipend___lsb 3
+#define reg_strcop_rw_cfg___ipend___width 1
+#define reg_strcop_rw_cfg___ipend___bit 3
+#define reg_strcop_rw_cfg___ignore_sync___lsb 4
+#define reg_strcop_rw_cfg___ignore_sync___width 1
+#define reg_strcop_rw_cfg___ignore_sync___bit 4
+#define reg_strcop_rw_cfg___en___lsb 5
+#define reg_strcop_rw_cfg___en___width 1
+#define reg_strcop_rw_cfg___en___bit 5
+#define reg_strcop_rw_cfg_offset 0
+
+
+/* Constants */
+#define regk_strcop_big                           0x00000001
+#define regk_strcop_d                             0x00000001
+#define regk_strcop_e                             0x00000000
+#define regk_strcop_little                        0x00000000
+#define regk_strcop_rw_cfg_default                0x00000002
+#endif /* __strcop_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
new file mode 100644
index 000000000000..69b299920f71
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
@@ -0,0 +1,100 @@
+#ifndef __strmux_defs_asm_h
+#define __strmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
+ *     last modfied: Mon Apr 11 16:09:43 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *      id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope strmux, type rw */
+#define reg_strmux_rw_cfg___dma0___lsb 0
+#define reg_strmux_rw_cfg___dma0___width 3
+#define reg_strmux_rw_cfg___dma1___lsb 3
+#define reg_strmux_rw_cfg___dma1___width 3
+#define reg_strmux_rw_cfg___dma2___lsb 6
+#define reg_strmux_rw_cfg___dma2___width 3
+#define reg_strmux_rw_cfg___dma3___lsb 9
+#define reg_strmux_rw_cfg___dma3___width 3
+#define reg_strmux_rw_cfg___dma4___lsb 12
+#define reg_strmux_rw_cfg___dma4___width 3
+#define reg_strmux_rw_cfg___dma5___lsb 15
+#define reg_strmux_rw_cfg___dma5___width 3
+#define reg_strmux_rw_cfg___dma6___lsb 18
+#define reg_strmux_rw_cfg___dma6___width 3
+#define reg_strmux_rw_cfg___dma7___lsb 21
+#define reg_strmux_rw_cfg___dma7___width 3
+#define reg_strmux_rw_cfg___dma8___lsb 24
+#define reg_strmux_rw_cfg___dma8___width 3
+#define reg_strmux_rw_cfg___dma9___lsb 27
+#define reg_strmux_rw_cfg___dma9___width 3
+#define reg_strmux_rw_cfg_offset 0
+
+
+/* Constants */
+#define regk_strmux_ata                           0x00000003
+#define regk_strmux_eth0                          0x00000001
+#define regk_strmux_eth1                          0x00000004
+#define regk_strmux_ext0                          0x00000001
+#define regk_strmux_ext1                          0x00000001
+#define regk_strmux_ext2                          0x00000001
+#define regk_strmux_ext3                          0x00000001
+#define regk_strmux_iop0                          0x00000002
+#define regk_strmux_iop1                          0x00000001
+#define regk_strmux_off                           0x00000000
+#define regk_strmux_p21                           0x00000004
+#define regk_strmux_rw_cfg_default                0x00000000
+#define regk_strmux_ser0                          0x00000002
+#define regk_strmux_ser1                          0x00000002
+#define regk_strmux_ser2                          0x00000004
+#define regk_strmux_ser3                          0x00000003
+#define regk_strmux_sser0                         0x00000003
+#define regk_strmux_sser1                         0x00000003
+#define regk_strmux_strcop                        0x00000002
+#endif /* __strmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
new file mode 100644
index 000000000000..43146021fc16
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
@@ -0,0 +1,229 @@
+#ifndef __timer_defs_asm_h
+#define __timer_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/timer/rtl/timer_regs.r
+ *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:53 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
+ *      id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tmr0_div, scope timer, type rw */
+#define reg_timer_rw_tmr0_div_offset 0
+
+/* Register r_tmr0_data, scope timer, type r */
+#define reg_timer_r_tmr0_data_offset 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr0_ctrl___op___lsb 0
+#define reg_timer_rw_tmr0_ctrl___op___width 2
+#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr0_ctrl___freq___width 3
+#define reg_timer_rw_tmr0_ctrl_offset 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+#define reg_timer_rw_tmr1_div_offset 16
+
+/* Register r_tmr1_data, scope timer, type r */
+#define reg_timer_r_tmr1_data_offset 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr1_ctrl___op___lsb 0
+#define reg_timer_rw_tmr1_ctrl___op___width 2
+#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr1_ctrl___freq___width 3
+#define reg_timer_rw_tmr1_ctrl_offset 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+#define reg_timer_rs_cnt_data___tmr___lsb 0
+#define reg_timer_rs_cnt_data___tmr___width 24
+#define reg_timer_rs_cnt_data___cnt___lsb 24
+#define reg_timer_rs_cnt_data___cnt___width 8
+#define reg_timer_rs_cnt_data_offset 32
+
+/* Register r_cnt_data, scope timer, type r */
+#define reg_timer_r_cnt_data___tmr___lsb 0
+#define reg_timer_r_cnt_data___tmr___width 24
+#define reg_timer_r_cnt_data___cnt___lsb 24
+#define reg_timer_r_cnt_data___cnt___width 8
+#define reg_timer_r_cnt_data_offset 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+#define reg_timer_rw_cnt_cfg___clk___lsb 0
+#define reg_timer_rw_cnt_cfg___clk___width 2
+#define reg_timer_rw_cnt_cfg_offset 40
+
+/* Register rw_trig, scope timer, type rw */
+#define reg_timer_rw_trig_offset 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+#define reg_timer_rw_trig_cfg___tmr___lsb 0
+#define reg_timer_rw_trig_cfg___tmr___width 2
+#define reg_timer_rw_trig_cfg_offset 52
+
+/* Register r_time, scope timer, type r */
+#define reg_timer_r_time_offset 56
+
+/* Register rw_out, scope timer, type rw */
+#define reg_timer_rw_out___tmr___lsb 0
+#define reg_timer_rw_out___tmr___width 2
+#define reg_timer_rw_out_offset 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+#define reg_timer_rw_wd_ctrl___cnt___lsb 0
+#define reg_timer_rw_wd_ctrl___cnt___width 8
+#define reg_timer_rw_wd_ctrl___cmd___lsb 8
+#define reg_timer_rw_wd_ctrl___cmd___width 1
+#define reg_timer_rw_wd_ctrl___cmd___bit 8
+#define reg_timer_rw_wd_ctrl___key___lsb 9
+#define reg_timer_rw_wd_ctrl___key___width 7
+#define reg_timer_rw_wd_ctrl_offset 64
+
+/* Register r_wd_stat, scope timer, type r */
+#define reg_timer_r_wd_stat___cnt___lsb 0
+#define reg_timer_r_wd_stat___cnt___width 8
+#define reg_timer_r_wd_stat___cmd___lsb 8
+#define reg_timer_r_wd_stat___cmd___width 1
+#define reg_timer_r_wd_stat___cmd___bit 8
+#define reg_timer_r_wd_stat_offset 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+#define reg_timer_rw_intr_mask___tmr0___lsb 0
+#define reg_timer_rw_intr_mask___tmr0___width 1
+#define reg_timer_rw_intr_mask___tmr0___bit 0
+#define reg_timer_rw_intr_mask___tmr1___lsb 1
+#define reg_timer_rw_intr_mask___tmr1___width 1
+#define reg_timer_rw_intr_mask___tmr1___bit 1
+#define reg_timer_rw_intr_mask___cnt___lsb 2
+#define reg_timer_rw_intr_mask___cnt___width 1
+#define reg_timer_rw_intr_mask___cnt___bit 2
+#define reg_timer_rw_intr_mask___trig___lsb 3
+#define reg_timer_rw_intr_mask___trig___width 1
+#define reg_timer_rw_intr_mask___trig___bit 3
+#define reg_timer_rw_intr_mask_offset 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+#define reg_timer_rw_ack_intr___tmr0___lsb 0
+#define reg_timer_rw_ack_intr___tmr0___width 1
+#define reg_timer_rw_ack_intr___tmr0___bit 0
+#define reg_timer_rw_ack_intr___tmr1___lsb 1
+#define reg_timer_rw_ack_intr___tmr1___width 1
+#define reg_timer_rw_ack_intr___tmr1___bit 1
+#define reg_timer_rw_ack_intr___cnt___lsb 2
+#define reg_timer_rw_ack_intr___cnt___width 1
+#define reg_timer_rw_ack_intr___cnt___bit 2
+#define reg_timer_rw_ack_intr___trig___lsb 3
+#define reg_timer_rw_ack_intr___trig___width 1
+#define reg_timer_rw_ack_intr___trig___bit 3
+#define reg_timer_rw_ack_intr_offset 76
+
+/* Register r_intr, scope timer, type r */
+#define reg_timer_r_intr___tmr0___lsb 0
+#define reg_timer_r_intr___tmr0___width 1
+#define reg_timer_r_intr___tmr0___bit 0
+#define reg_timer_r_intr___tmr1___lsb 1
+#define reg_timer_r_intr___tmr1___width 1
+#define reg_timer_r_intr___tmr1___bit 1
+#define reg_timer_r_intr___cnt___lsb 2
+#define reg_timer_r_intr___cnt___width 1
+#define reg_timer_r_intr___cnt___bit 2
+#define reg_timer_r_intr___trig___lsb 3
+#define reg_timer_r_intr___trig___width 1
+#define reg_timer_r_intr___trig___bit 3
+#define reg_timer_r_intr_offset 80
+
+/* Register r_masked_intr, scope timer, type r */
+#define reg_timer_r_masked_intr___tmr0___lsb 0
+#define reg_timer_r_masked_intr___tmr0___width 1
+#define reg_timer_r_masked_intr___tmr0___bit 0
+#define reg_timer_r_masked_intr___tmr1___lsb 1
+#define reg_timer_r_masked_intr___tmr1___width 1
+#define reg_timer_r_masked_intr___tmr1___bit 1
+#define reg_timer_r_masked_intr___cnt___lsb 2
+#define reg_timer_r_masked_intr___cnt___width 1
+#define reg_timer_r_masked_intr___cnt___bit 2
+#define reg_timer_r_masked_intr___trig___lsb 3
+#define reg_timer_r_masked_intr___trig___width 1
+#define reg_timer_r_masked_intr___trig___bit 3
+#define reg_timer_r_masked_intr_offset 84
+
+/* Register rw_test, scope timer, type rw */
+#define reg_timer_rw_test___dis___lsb 0
+#define reg_timer_rw_test___dis___width 1
+#define reg_timer_rw_test___dis___bit 0
+#define reg_timer_rw_test___en___lsb 1
+#define reg_timer_rw_test___en___width 1
+#define reg_timer_rw_test___en___bit 1
+#define reg_timer_rw_test_offset 88
+
+
+/* Constants */
+#define regk_timer_ext                            0x00000001
+#define regk_timer_f100                           0x00000007
+#define regk_timer_f29_493                        0x00000004
+#define regk_timer_f32                            0x00000005
+#define regk_timer_f32_768                        0x00000006
+#define regk_timer_hold                           0x00000001
+#define regk_timer_ld                             0x00000000
+#define regk_timer_no                             0x00000000
+#define regk_timer_off                            0x00000000
+#define regk_timer_run                            0x00000002
+#define regk_timer_rw_cnt_cfg_default             0x00000000
+#define regk_timer_rw_intr_mask_default           0x00000000
+#define regk_timer_rw_out_default                 0x00000000
+#define regk_timer_rw_test_default                0x00000000
+#define regk_timer_rw_tmr0_ctrl_default           0x00000000
+#define regk_timer_rw_tmr1_ctrl_default           0x00000000
+#define regk_timer_rw_trig_cfg_default            0x00000000
+#define regk_timer_start                          0x00000001
+#define regk_timer_stop                           0x00000000
+#define regk_timer_time                           0x00000001
+#define regk_timer_tmr0                           0x00000002
+#define regk_timer_tmr1                           0x00000003
+#define regk_timer_yes                            0x00000001
+#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h
new file mode 100644
index 000000000000..43b6643ff0d3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ata_defs.h
@@ -0,0 +1,222 @@
+#ifndef __ata_defs_h
+#define __ata_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ata/rtl/ata_regs.r
+ *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
+ *     last modfied: Mon Apr 11 16:06:25 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
+ *      id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ata */
+
+/* Register rw_ctrl0, scope ata, type rw */
+typedef struct {
+  unsigned int pio_hold  : 6;
+  unsigned int pio_strb  : 6;
+  unsigned int pio_setup : 6;
+  unsigned int dma_hold  : 6;
+  unsigned int dma_strb  : 6;
+  unsigned int rst       : 1;
+  unsigned int en        : 1;
+} reg_ata_rw_ctrl0;
+#define REG_RD_ADDR_ata_rw_ctrl0 12
+#define REG_WR_ADDR_ata_rw_ctrl0 12
+
+/* Register rw_ctrl1, scope ata, type rw */
+typedef struct {
+  unsigned int udma_tcyc : 4;
+  unsigned int udma_tdvs : 4;
+  unsigned int dummy1    : 24;
+} reg_ata_rw_ctrl1;
+#define REG_RD_ADDR_ata_rw_ctrl1 16
+#define REG_WR_ADDR_ata_rw_ctrl1 16
+
+/* Register rw_ctrl2, scope ata, type rw */
+typedef struct {
+  unsigned int data     : 16;
+  unsigned int dummy1   : 3;
+  unsigned int dma_size : 1;
+  unsigned int multi    : 1;
+  unsigned int hsh      : 2;
+  unsigned int trf_mode : 1;
+  unsigned int rw       : 1;
+  unsigned int addr     : 3;
+  unsigned int cs0      : 1;
+  unsigned int cs1      : 1;
+  unsigned int sel      : 2;
+} reg_ata_rw_ctrl2;
+#define REG_RD_ADDR_ata_rw_ctrl2 0
+#define REG_WR_ADDR_ata_rw_ctrl2 0
+
+/* Register rs_stat_data, scope ata, type rs */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dav  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 14;
+} reg_ata_rs_stat_data;
+#define REG_RD_ADDR_ata_rs_stat_data 4
+
+/* Register r_stat_data, scope ata, type r */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dav  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 14;
+} reg_ata_r_stat_data;
+#define REG_RD_ADDR_ata_r_stat_data 8
+
+/* Register rw_trf_cnt, scope ata, type rw */
+typedef struct {
+  unsigned int cnt : 17;
+  unsigned int dummy1 : 15;
+} reg_ata_rw_trf_cnt;
+#define REG_RD_ADDR_ata_rw_trf_cnt 20
+#define REG_WR_ADDR_ata_rw_trf_cnt 20
+
+/* Register r_stat_misc, scope ata, type r */
+typedef struct {
+  unsigned int crc : 16;
+  unsigned int dummy1 : 16;
+} reg_ata_r_stat_misc;
+#define REG_RD_ADDR_ata_r_stat_misc 24
+
+/* Register rw_intr_mask, scope ata, type rw */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_rw_intr_mask;
+#define REG_RD_ADDR_ata_rw_intr_mask 28
+#define REG_WR_ADDR_ata_rw_intr_mask 28
+
+/* Register rw_ack_intr, scope ata, type rw */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_rw_ack_intr;
+#define REG_RD_ADDR_ata_rw_ack_intr 32
+#define REG_WR_ADDR_ata_rw_ack_intr 32
+
+/* Register r_intr, scope ata, type r */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_r_intr;
+#define REG_RD_ADDR_ata_r_intr 36
+
+/* Register r_masked_intr, scope ata, type r */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_r_masked_intr;
+#define REG_RD_ADDR_ata_r_masked_intr 40
+
+
+/* Constants */
+enum {
+  regk_ata_active                          = 0x00000001,
+  regk_ata_byte                            = 0x00000001,
+  regk_ata_data                            = 0x00000001,
+  regk_ata_dma                             = 0x00000001,
+  regk_ata_inactive                        = 0x00000000,
+  regk_ata_no                              = 0x00000000,
+  regk_ata_nodata                          = 0x00000000,
+  regk_ata_pio                             = 0x00000000,
+  regk_ata_rd                              = 0x00000001,
+  regk_ata_reg                             = 0x00000000,
+  regk_ata_rw_ctrl0_default                = 0x00000000,
+  regk_ata_rw_ctrl2_default                = 0x00000000,
+  regk_ata_rw_intr_mask_default            = 0x00000000,
+  regk_ata_udma                            = 0x00000002,
+  regk_ata_word                            = 0x00000000,
+  regk_ata_wr                              = 0x00000000,
+  regk_ata_yes                             = 0x00000001
+};
+#endif /* __ata_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
new file mode 100644
index 000000000000..a56608b50359
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
@@ -0,0 +1,284 @@
+#ifndef __bif_core_defs_h
+#define __bif_core_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_core_regs.r
+ *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
+ *      id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_core */
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw        : 6;
+  unsigned int ew        : 3;
+  unsigned int zw        : 3;
+  unsigned int aw        : 2;
+  unsigned int dw        : 2;
+  unsigned int ewb       : 2;
+  unsigned int bw        : 1;
+  unsigned int wr_extend : 1;
+  unsigned int erc_en    : 1;
+  unsigned int mode      : 1;
+  unsigned int dummy1    : 10;
+} reg_bif_core_rw_grp1_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
+#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw        : 6;
+  unsigned int ew        : 3;
+  unsigned int zw        : 3;
+  unsigned int aw        : 2;
+  unsigned int dw        : 2;
+  unsigned int ewb       : 2;
+  unsigned int bw        : 1;
+  unsigned int wr_extend : 1;
+  unsigned int erc_en    : 1;
+  unsigned int mode      : 1;
+  unsigned int dummy1    : 10;
+} reg_bif_core_rw_grp2_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
+#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw         : 6;
+  unsigned int ew         : 3;
+  unsigned int zw         : 3;
+  unsigned int aw         : 2;
+  unsigned int dw         : 2;
+  unsigned int ewb        : 2;
+  unsigned int bw         : 1;
+  unsigned int wr_extend  : 1;
+  unsigned int erc_en     : 1;
+  unsigned int mode       : 1;
+  unsigned int dummy1     : 2;
+  unsigned int gated_csp0 : 2;
+  unsigned int gated_csp1 : 2;
+  unsigned int gated_csp2 : 2;
+  unsigned int gated_csp3 : 2;
+} reg_bif_core_rw_grp3_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
+#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw         : 6;
+  unsigned int ew         : 3;
+  unsigned int zw         : 3;
+  unsigned int aw         : 2;
+  unsigned int dw         : 2;
+  unsigned int ewb        : 2;
+  unsigned int bw         : 1;
+  unsigned int wr_extend  : 1;
+  unsigned int erc_en     : 1;
+  unsigned int mode       : 1;
+  unsigned int dummy1     : 4;
+  unsigned int gated_csp4 : 2;
+  unsigned int gated_csp5 : 2;
+  unsigned int gated_csp6 : 2;
+} reg_bif_core_rw_grp4_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
+#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+typedef struct {
+  unsigned int bank_sel : 5;
+  unsigned int ca       : 3;
+  unsigned int type     : 1;
+  unsigned int bw       : 1;
+  unsigned int sh       : 3;
+  unsigned int wmm      : 1;
+  unsigned int sh16     : 1;
+  unsigned int grp_sel  : 5;
+  unsigned int dummy1   : 12;
+} reg_bif_core_rw_sdram_cfg_grp0;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+typedef struct {
+  unsigned int bank_sel : 5;
+  unsigned int ca       : 3;
+  unsigned int type     : 1;
+  unsigned int bw       : 1;
+  unsigned int sh       : 3;
+  unsigned int wmm      : 1;
+  unsigned int sh16     : 1;
+  unsigned int dummy1   : 17;
+} reg_bif_core_rw_sdram_cfg_grp1;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+typedef struct {
+  unsigned int cl    : 3;
+  unsigned int rcd   : 3;
+  unsigned int rp    : 3;
+  unsigned int rc    : 2;
+  unsigned int dpl   : 2;
+  unsigned int pde   : 1;
+  unsigned int ref   : 2;
+  unsigned int cpd   : 1;
+  unsigned int sdcke : 1;
+  unsigned int sdclk : 1;
+  unsigned int dummy1 : 13;
+} reg_bif_core_rw_sdram_timing;
+#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
+#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+typedef struct {
+  unsigned int cmd      : 3;
+  unsigned int mrs_data : 15;
+  unsigned int dummy1   : 14;
+} reg_bif_core_rw_sdram_cmd;
+#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
+#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+typedef struct {
+  unsigned int ok : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_core_rs_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+typedef struct {
+  unsigned int ok : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_core_r_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
+
+
+/* Constants */
+enum {
+  regk_bif_core_bank2                      = 0x00000000,
+  regk_bif_core_bank4                      = 0x00000001,
+  regk_bif_core_bit10                      = 0x0000000a,
+  regk_bif_core_bit11                      = 0x0000000b,
+  regk_bif_core_bit12                      = 0x0000000c,
+  regk_bif_core_bit13                      = 0x0000000d,
+  regk_bif_core_bit14                      = 0x0000000e,
+  regk_bif_core_bit15                      = 0x0000000f,
+  regk_bif_core_bit16                      = 0x00000010,
+  regk_bif_core_bit17                      = 0x00000011,
+  regk_bif_core_bit18                      = 0x00000012,
+  regk_bif_core_bit19                      = 0x00000013,
+  regk_bif_core_bit20                      = 0x00000014,
+  regk_bif_core_bit21                      = 0x00000015,
+  regk_bif_core_bit22                      = 0x00000016,
+  regk_bif_core_bit23                      = 0x00000017,
+  regk_bif_core_bit24                      = 0x00000018,
+  regk_bif_core_bit25                      = 0x00000019,
+  regk_bif_core_bit26                      = 0x0000001a,
+  regk_bif_core_bit27                      = 0x0000001b,
+  regk_bif_core_bit28                      = 0x0000001c,
+  regk_bif_core_bit29                      = 0x0000001d,
+  regk_bif_core_bit9                       = 0x00000009,
+  regk_bif_core_bw16                       = 0x00000001,
+  regk_bif_core_bw32                       = 0x00000000,
+  regk_bif_core_bwe                        = 0x00000000,
+  regk_bif_core_cwe                        = 0x00000001,
+  regk_bif_core_e15us                      = 0x00000001,
+  regk_bif_core_e7800ns                    = 0x00000002,
+  regk_bif_core_grp0                       = 0x00000000,
+  regk_bif_core_grp1                       = 0x00000001,
+  regk_bif_core_mrs                        = 0x00000003,
+  regk_bif_core_no                         = 0x00000000,
+  regk_bif_core_none                       = 0x00000000,
+  regk_bif_core_nop                        = 0x00000000,
+  regk_bif_core_off                        = 0x00000000,
+  regk_bif_core_pre                        = 0x00000002,
+  regk_bif_core_r_sdram_ref_stat_default   = 0x00000001,
+  regk_bif_core_rd                         = 0x00000002,
+  regk_bif_core_ref                        = 0x00000001,
+  regk_bif_core_rs_sdram_ref_stat_default  = 0x00000001,
+  regk_bif_core_rw_grp1_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp2_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp3_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp4_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_sdram_cfg_grp1_default  = 0x00000000,
+  regk_bif_core_slf                        = 0x00000004,
+  regk_bif_core_wr                         = 0x00000001,
+  regk_bif_core_yes                        = 0x00000001
+};
+#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
new file mode 100644
index 000000000000..b931c1aab679
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
@@ -0,0 +1,473 @@
+#ifndef __bif_dma_defs_h
+#define __bif_dma_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_dma_regs.r
+ *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
+ *      id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_dma */
+
+/* Register rw_ch0_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw         : 2;
+  unsigned int burst_len  : 1;
+  unsigned int cont       : 1;
+  unsigned int end_pad    : 1;
+  unsigned int cnt        : 1;
+  unsigned int dreq_pin   : 3;
+  unsigned int dreq_mode  : 2;
+  unsigned int tc_in_pin  : 3;
+  unsigned int tc_in_mode : 2;
+  unsigned int bus_mode   : 2;
+  unsigned int rate_en    : 1;
+  unsigned int wr_all     : 1;
+  unsigned int dummy1     : 12;
+} reg_bif_dma_rw_ch0_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
+#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
+
+/* Register rw_ch0_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch0_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
+#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
+
+/* Register rw_ch0_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch0_start;
+#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
+#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
+
+/* Register rw_ch0_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch0_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
+#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
+
+/* Register r_ch0_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch0_stat;
+#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
+
+/* Register rw_ch1_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw          : 2;
+  unsigned int burst_len   : 1;
+  unsigned int cont        : 1;
+  unsigned int end_discard : 1;
+  unsigned int cnt         : 1;
+  unsigned int dreq_pin    : 3;
+  unsigned int dreq_mode   : 2;
+  unsigned int tc_in_pin   : 3;
+  unsigned int tc_in_mode  : 2;
+  unsigned int bus_mode    : 2;
+  unsigned int rate_en     : 1;
+  unsigned int dummy1      : 13;
+} reg_bif_dma_rw_ch1_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
+#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
+
+/* Register rw_ch1_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch1_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
+#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
+
+/* Register rw_ch1_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch1_start;
+#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
+#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
+
+/* Register rw_ch1_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch1_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
+#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
+
+/* Register r_ch1_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch1_stat;
+#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
+
+/* Register rw_ch2_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw         : 2;
+  unsigned int burst_len  : 1;
+  unsigned int cont       : 1;
+  unsigned int end_pad    : 1;
+  unsigned int cnt        : 1;
+  unsigned int dreq_pin   : 3;
+  unsigned int dreq_mode  : 2;
+  unsigned int tc_in_pin  : 3;
+  unsigned int tc_in_mode : 2;
+  unsigned int bus_mode   : 2;
+  unsigned int rate_en    : 1;
+  unsigned int wr_all     : 1;
+  unsigned int dummy1     : 12;
+} reg_bif_dma_rw_ch2_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
+#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
+
+/* Register rw_ch2_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch2_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
+#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
+
+/* Register rw_ch2_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch2_start;
+#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
+#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
+
+/* Register rw_ch2_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch2_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
+#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
+
+/* Register r_ch2_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch2_stat;
+#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
+
+/* Register rw_ch3_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw          : 2;
+  unsigned int burst_len   : 1;
+  unsigned int cont        : 1;
+  unsigned int end_discard : 1;
+  unsigned int cnt         : 1;
+  unsigned int dreq_pin    : 3;
+  unsigned int dreq_mode   : 2;
+  unsigned int tc_in_pin   : 3;
+  unsigned int tc_in_mode  : 2;
+  unsigned int bus_mode    : 2;
+  unsigned int rate_en     : 1;
+  unsigned int dummy1      : 13;
+} reg_bif_dma_rw_ch3_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
+#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
+
+/* Register rw_ch3_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch3_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
+#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
+
+/* Register rw_ch3_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch3_start;
+#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
+#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
+
+/* Register rw_ch3_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch3_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
+#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
+
+/* Register r_ch3_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch3_stat;
+#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
+
+/* Register rw_intr_mask, scope bif_dma, type rw */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_rw_intr_mask;
+#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
+#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
+
+/* Register rw_ack_intr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_rw_ack_intr;
+#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
+#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
+
+/* Register r_intr, scope bif_dma, type r */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_r_intr;
+#define REG_RD_ADDR_bif_dma_r_intr 136
+
+/* Register r_masked_intr, scope bif_dma, type r */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_r_masked_intr;
+#define REG_RD_ADDR_bif_dma_r_masked_intr 140
+
+/* Register rw_pin0_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin0_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
+#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
+
+/* Register rw_pin1_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin1_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
+#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
+
+/* Register rw_pin2_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin2_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
+#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
+
+/* Register rw_pin3_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin3_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
+#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
+
+/* Register rw_pin4_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin4_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
+#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
+
+/* Register rw_pin5_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin5_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
+#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
+
+/* Register rw_pin6_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin6_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
+#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
+
+/* Register rw_pin7_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin7_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
+#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
+
+/* Register r_pin_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int pin0 : 1;
+  unsigned int pin1 : 1;
+  unsigned int pin2 : 1;
+  unsigned int pin3 : 1;
+  unsigned int pin4 : 1;
+  unsigned int pin5 : 1;
+  unsigned int pin6 : 1;
+  unsigned int pin7 : 1;
+  unsigned int dummy1 : 24;
+} reg_bif_dma_r_pin_stat;
+#define REG_RD_ADDR_bif_dma_r_pin_stat 192
+
+
+/* Constants */
+enum {
+  regk_bif_dma_as_master                   = 0x00000001,
+  regk_bif_dma_as_slave                    = 0x00000001,
+  regk_bif_dma_burst1                      = 0x00000000,
+  regk_bif_dma_burst8                      = 0x00000001,
+  regk_bif_dma_bw16                        = 0x00000001,
+  regk_bif_dma_bw32                        = 0x00000002,
+  regk_bif_dma_bw8                         = 0x00000000,
+  regk_bif_dma_dack                        = 0x00000006,
+  regk_bif_dma_dack_inv                    = 0x00000007,
+  regk_bif_dma_force                       = 0x00000001,
+  regk_bif_dma_hi                          = 0x00000003,
+  regk_bif_dma_inv                         = 0x00000003,
+  regk_bif_dma_lo                          = 0x00000002,
+  regk_bif_dma_master                      = 0x00000001,
+  regk_bif_dma_no                          = 0x00000000,
+  regk_bif_dma_norm                        = 0x00000002,
+  regk_bif_dma_off                         = 0x00000000,
+  regk_bif_dma_rw_ch0_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch0_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch1_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch1_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch2_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch2_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch3_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch3_start_default        = 0x00000000,
+  regk_bif_dma_rw_intr_mask_default        = 0x00000000,
+  regk_bif_dma_rw_pin0_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin1_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin2_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin3_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin4_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin5_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin6_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin7_cfg_default         = 0x00000000,
+  regk_bif_dma_slave                       = 0x00000002,
+  regk_bif_dma_sreq                        = 0x00000006,
+  regk_bif_dma_sreq_inv                    = 0x00000007,
+  regk_bif_dma_tc                          = 0x00000004,
+  regk_bif_dma_tc_inv                      = 0x00000005,
+  regk_bif_dma_yes                         = 0x00000001
+};
+#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
new file mode 100644
index 000000000000..d18fc3c9f569
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
@@ -0,0 +1,249 @@
+#ifndef __bif_slave_defs_h
+#define __bif_slave_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_slave_regs.r
+ *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
+ *     last modfied: Mon Apr 11 16:06:34 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
+ *      id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_slave */
+
+/* Register rw_slave_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int slave_id     : 3;
+  unsigned int use_slave_id : 1;
+  unsigned int boot_rdy     : 1;
+  unsigned int loopback     : 1;
+  unsigned int dis          : 1;
+  unsigned int dummy1       : 25;
+} reg_bif_slave_rw_slave_cfg;
+#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
+#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
+
+/* Register r_slave_mode, scope bif_slave, type r */
+typedef struct {
+  unsigned int ch0_mode : 1;
+  unsigned int ch1_mode : 1;
+  unsigned int ch2_mode : 1;
+  unsigned int ch3_mode : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_slave_r_slave_mode;
+#define REG_RD_ADDR_bif_slave_r_slave_mode 4
+
+/* Register rw_ch0_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch0_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
+#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
+
+/* Register rw_ch1_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch1_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
+#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
+
+/* Register rw_ch2_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch2_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
+#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
+
+/* Register rw_ch3_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch3_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
+#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
+
+/* Register rw_arb_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int brin_mode   : 1;
+  unsigned int brout_mode  : 3;
+  unsigned int bg_mode     : 3;
+  unsigned int release     : 2;
+  unsigned int acquire     : 1;
+  unsigned int settle_time : 2;
+  unsigned int dram_ctrl   : 1;
+  unsigned int dummy1      : 19;
+} reg_bif_slave_rw_arb_cfg;
+#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
+#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
+
+/* Register r_arb_stat, scope bif_slave, type r */
+typedef struct {
+  unsigned int init_mode : 1;
+  unsigned int mode      : 1;
+  unsigned int brin      : 1;
+  unsigned int brout     : 1;
+  unsigned int bg        : 1;
+  unsigned int dummy1    : 27;
+} reg_bif_slave_r_arb_stat;
+#define REG_RD_ADDR_bif_slave_r_arb_stat 36
+
+/* Register rw_intr_mask, scope bif_slave, type rw */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_rw_intr_mask;
+#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
+#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
+
+/* Register rw_ack_intr, scope bif_slave, type rw */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_rw_ack_intr;
+#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
+#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
+
+/* Register r_intr, scope bif_slave, type r */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_r_intr;
+#define REG_RD_ADDR_bif_slave_r_intr 72
+
+/* Register r_masked_intr, scope bif_slave, type r */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_r_masked_intr;
+#define REG_RD_ADDR_bif_slave_r_masked_intr 76
+
+
+/* Constants */
+enum {
+  regk_bif_slave_active_hi                 = 0x00000003,
+  regk_bif_slave_active_lo                 = 0x00000002,
+  regk_bif_slave_addr                      = 0x00000000,
+  regk_bif_slave_always                    = 0x00000001,
+  regk_bif_slave_at_idle                   = 0x00000002,
+  regk_bif_slave_burst_end                 = 0x00000003,
+  regk_bif_slave_dma                       = 0x00000001,
+  regk_bif_slave_hi                        = 0x00000003,
+  regk_bif_slave_inv                       = 0x00000001,
+  regk_bif_slave_lo                        = 0x00000002,
+  regk_bif_slave_local                     = 0x00000001,
+  regk_bif_slave_master                    = 0x00000000,
+  regk_bif_slave_mode_reg                  = 0x00000001,
+  regk_bif_slave_no                        = 0x00000000,
+  regk_bif_slave_norm                      = 0x00000000,
+  regk_bif_slave_on_access                 = 0x00000000,
+  regk_bif_slave_rw_arb_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch0_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch1_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch2_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch3_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_intr_mask_default      = 0x00000000,
+  regk_bif_slave_rw_slave_cfg_default      = 0x00000000,
+  regk_bif_slave_shared                    = 0x00000000,
+  regk_bif_slave_slave                     = 0x00000001,
+  regk_bif_slave_t0ns                      = 0x00000003,
+  regk_bif_slave_t10ns                     = 0x00000002,
+  regk_bif_slave_t20ns                     = 0x00000003,
+  regk_bif_slave_t30ns                     = 0x00000002,
+  regk_bif_slave_t40ns                     = 0x00000001,
+  regk_bif_slave_t50ns                     = 0x00000000,
+  regk_bif_slave_yes                       = 0x00000001,
+  regk_bif_slave_z                         = 0x00000004
+};
+#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h
new file mode 100644
index 000000000000..45457a4e3817
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/config_defs.h
@@ -0,0 +1,142 @@
+#ifndef __config_defs_h
+#define __config_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../rtl/config_regs.r
+ *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ *     last modfied: Thu Mar  4 12:34:39 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
+ *      id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope config */
+
+/* Register r_bootsel, scope config, type r */
+typedef struct {
+  unsigned int boot_mode   : 3;
+  unsigned int full_duplex : 1;
+  unsigned int user        : 1;
+  unsigned int pll         : 1;
+  unsigned int flash_bw    : 1;
+  unsigned int dummy1      : 25;
+} reg_config_r_bootsel;
+#define REG_RD_ADDR_config_r_bootsel 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+typedef struct {
+  unsigned int pll          : 1;
+  unsigned int cpu          : 1;
+  unsigned int iop          : 1;
+  unsigned int dma01_eth0   : 1;
+  unsigned int dma23        : 1;
+  unsigned int dma45        : 1;
+  unsigned int dma67        : 1;
+  unsigned int dma89_strcop : 1;
+  unsigned int bif          : 1;
+  unsigned int fix_io       : 1;
+  unsigned int dummy1       : 22;
+} reg_config_rw_clk_ctrl;
+#define REG_RD_ADDR_config_rw_clk_ctrl 4
+#define REG_WR_ADDR_config_rw_clk_ctrl 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+typedef struct {
+  unsigned int usb_susp : 1;
+  unsigned int phyrst_n : 1;
+  unsigned int dummy1   : 30;
+} reg_config_rw_pad_ctrl;
+#define REG_RD_ADDR_config_rw_pad_ctrl 8
+#define REG_WR_ADDR_config_rw_pad_ctrl 8
+
+
+/* Constants */
+enum {
+  regk_config_bw16                         = 0x00000000,
+  regk_config_bw32                         = 0x00000001,
+  regk_config_master                       = 0x00000005,
+  regk_config_nand                         = 0x00000003,
+  regk_config_net_rx                       = 0x00000001,
+  regk_config_net_tx_rx                    = 0x00000002,
+  regk_config_no                           = 0x00000000,
+  regk_config_none                         = 0x00000007,
+  regk_config_nor                          = 0x00000000,
+  regk_config_rw_clk_ctrl_default          = 0x00000002,
+  regk_config_rw_pad_ctrl_default          = 0x00000000,
+  regk_config_ser                          = 0x00000004,
+  regk_config_slave                        = 0x00000006,
+  regk_config_yes                          = 0x00000001
+};
+#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
new file mode 100644
index 000000000000..8370aee8a14a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
@@ -0,0 +1,41 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/crisp/doc/cpu_vect.r
+version . */
+
+#ifndef _______INST_CRISP_DOC_CPU_VECT_R
+#define _______INST_CRISP_DOC_CPU_VECT_R
+#define NMI_INTR_VECT   0x00
+#define RESERVED_1_INTR_VECT    0x01
+#define RESERVED_2_INTR_VECT    0x02
+#define SINGLE_STEP_INTR_VECT   0x03
+#define INSTR_TLB_REFILL_INTR_VECT      0x04
+#define INSTR_TLB_INV_INTR_VECT 0x05
+#define INSTR_TLB_ACC_INTR_VECT 0x06
+#define TLB_EX_INTR_VECT        0x07
+#define DATA_TLB_REFILL_INTR_VECT       0x08
+#define DATA_TLB_INV_INTR_VECT  0x09
+#define DATA_TLB_ACC_INTR_VECT  0x0a
+#define DATA_TLB_WE_INTR_VECT   0x0b
+#define HW_BP_INTR_VECT 0x0c
+#define RESERVED_D_INTR_VECT    0x0d
+#define RESERVED_E_INTR_VECT    0x0e
+#define RESERVED_F_INTR_VECT    0x0f
+#define BREAK_0_INTR_VECT       0x10
+#define BREAK_1_INTR_VECT       0x11
+#define BREAK_2_INTR_VECT       0x12
+#define BREAK_3_INTR_VECT       0x13
+#define BREAK_4_INTR_VECT       0x14
+#define BREAK_5_INTR_VECT       0x15
+#define BREAK_6_INTR_VECT       0x16
+#define BREAK_7_INTR_VECT       0x17
+#define BREAK_8_INTR_VECT       0x18
+#define BREAK_9_INTR_VECT       0x19
+#define BREAK_10_INTR_VECT      0x1a
+#define BREAK_11_INTR_VECT      0x1b
+#define BREAK_12_INTR_VECT      0x1c
+#define BREAK_13_INTR_VECT      0x1d
+#define BREAK_14_INTR_VECT      0x1e
+#define BREAK_15_INTR_VECT      0x1f
+#define MULTIPLE_INTR_VECT      0x30
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h
new file mode 100644
index 000000000000..c31832d3d6be
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma.h
@@ -0,0 +1,128 @@
+/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ *
+ * DMA C definitions and help macros
+ *
+ */
+
+#ifndef dma_h
+#define dma_h
+
+/* registers */ /* Really needed, since both are listed in sw.list? */
+#include "dma_defs.h"
+
+
+/* descriptors */
+
+// ------------------------------------------------------------ dma_descr_group
+typedef struct dma_descr_group {
+  struct dma_descr_group       *next;
+  unsigned                      eol        : 1;
+  unsigned                      tol        : 1;
+  unsigned                      bol        : 1;
+  unsigned                                 : 1;
+  unsigned                      intr       : 1;
+  unsigned                                 : 2;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md         : 16;
+  struct dma_descr_group       *up;
+  union {
+    struct dma_descr_context   *context;
+    struct dma_descr_group     *group;
+  }                             down;
+} dma_descr_group;
+
+// ---------------------------------------------------------- dma_descr_context
+typedef struct dma_descr_context {
+  struct dma_descr_context     *next;
+  unsigned                      eol        : 1;
+  unsigned                                 : 3;
+  unsigned                      intr       : 1;
+  unsigned                                 : 1;
+  unsigned                      store_mode : 1;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md0        : 16;
+  unsigned                      md1;
+  unsigned                      md2;
+  unsigned                      md3;
+  unsigned                      md4;
+  struct dma_descr_data        *saved_data;
+  char                         *saved_data_buf;
+} dma_descr_context;
+
+// ------------------------------------------------------------- dma_descr_data
+typedef struct dma_descr_data {
+  struct dma_descr_data        *next;
+  char                         *buf;
+  unsigned                      eol        : 1;
+  unsigned                                 : 2;
+  unsigned                      out_eop    : 1;
+  unsigned                      intr       : 1;
+  unsigned                      wait       : 1;
+  unsigned                                 : 2;
+  unsigned                                 : 3;
+  unsigned                      in_eop     : 1;
+  unsigned                                 : 4;
+  unsigned                      md         : 16;
+  char                         *after;
+} dma_descr_data;
+
+// --------------------------------------------------------------------- macros
+
+// enable DMA channel
+#define DMA_ENABLE( inst ) \
+   do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
+        e.en = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, e); } while( 0 )
+
+// reset DMA channel
+#define DMA_RESET( inst ) \
+   do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
+        r.en = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, r); } while( 0 )
+
+// stop DMA channel
+#define DMA_STOP( inst ) \
+   do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
+        s.stop = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, s); } while( 0 )
+
+// continue DMA channel operation
+#define DMA_CONTINUE( inst ) \
+   do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
+        c.stop = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, c); } while( 0 )
+
+// give stream command
+#define DMA_WR_CMD( inst, cmd_par ) \
+   do { reg_dma_rw_stream_cmd r = {0}; \
+        do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
+        r.cmd = (cmd_par); \
+        REG_WR( dma, inst, rw_stream_cmd, r ); \
+      } while( 0 )
+
+// load: g,c,d:burst
+#define DMA_START_GROUP( inst, group_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_g ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+
+// load: c,d:burst
+#define DMA_START_CONTEXT( inst, ctx_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+
+// if the DMA is at the end of the data list, the last data descr is reloaded
+#define DMA_CONTINUE_DATA( inst ) \
+do { reg_dma_rw_cmd c = {0}; \
+     c.cont_data = regk_dma_yes;\
+     REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h
new file mode 100644
index 000000000000..48ac8cef7ebe
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma_defs.h
@@ -0,0 +1,436 @@
+#ifndef __dma_defs_h
+#define __dma_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
+ *     last modfied: Mon Apr 11 16:06:51 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *      id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope dma */
+
+/* Register rw_data, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data;
+#define REG_RD_ADDR_dma_rw_data 0
+#define REG_WR_ADDR_dma_rw_data 0
+
+/* Register rw_data_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_next;
+#define REG_RD_ADDR_dma_rw_data_next 4
+#define REG_WR_ADDR_dma_rw_data_next 4
+
+/* Register rw_data_buf, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_buf;
+#define REG_RD_ADDR_dma_rw_data_buf 8
+#define REG_WR_ADDR_dma_rw_data_buf 8
+
+/* Register rw_data_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol     : 1;
+  unsigned int dummy1  : 2;
+  unsigned int out_eop : 1;
+  unsigned int intr    : 1;
+  unsigned int wait    : 1;
+  unsigned int dummy2  : 26;
+} reg_dma_rw_data_ctrl;
+#define REG_RD_ADDR_dma_rw_data_ctrl 12
+#define REG_WR_ADDR_dma_rw_data_ctrl 12
+
+/* Register rw_data_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 3;
+  unsigned int in_eop : 1;
+  unsigned int dummy2 : 28;
+} reg_dma_rw_data_stat;
+#define REG_RD_ADDR_dma_rw_data_stat 16
+#define REG_WR_ADDR_dma_rw_data_stat 16
+
+/* Register rw_data_md, scope dma, type rw */
+typedef struct {
+  unsigned int md : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_data_md;
+#define REG_RD_ADDR_dma_rw_data_md 20
+#define REG_WR_ADDR_dma_rw_data_md 20
+
+/* Register rw_data_md_s, scope dma, type rw */
+typedef struct {
+  unsigned int md_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_data_md_s;
+#define REG_RD_ADDR_dma_rw_data_md_s 24
+#define REG_WR_ADDR_dma_rw_data_md_s 24
+
+/* Register rw_data_after, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_after;
+#define REG_RD_ADDR_dma_rw_data_after 28
+#define REG_WR_ADDR_dma_rw_data_after 28
+
+/* Register rw_ctxt, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt;
+#define REG_RD_ADDR_dma_rw_ctxt 32
+#define REG_WR_ADDR_dma_rw_ctxt 32
+
+/* Register rw_ctxt_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_next;
+#define REG_RD_ADDR_dma_rw_ctxt_next 36
+#define REG_WR_ADDR_dma_rw_ctxt_next 36
+
+/* Register rw_ctxt_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol        : 1;
+  unsigned int dummy1     : 3;
+  unsigned int intr       : 1;
+  unsigned int dummy2     : 1;
+  unsigned int store_mode : 1;
+  unsigned int en         : 1;
+  unsigned int dummy3     : 24;
+} reg_dma_rw_ctxt_ctrl;
+#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
+#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
+
+/* Register rw_ctxt_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 7;
+  unsigned int dis : 1;
+  unsigned int dummy2 : 24;
+} reg_dma_rw_ctxt_stat;
+#define REG_RD_ADDR_dma_rw_ctxt_stat 44
+#define REG_WR_ADDR_dma_rw_ctxt_stat 44
+
+/* Register rw_ctxt_md0, scope dma, type rw */
+typedef struct {
+  unsigned int md0 : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_ctxt_md0;
+#define REG_RD_ADDR_dma_rw_ctxt_md0 48
+#define REG_WR_ADDR_dma_rw_ctxt_md0 48
+
+/* Register rw_ctxt_md0_s, scope dma, type rw */
+typedef struct {
+  unsigned int md0_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_ctxt_md0_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
+#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
+
+/* Register rw_ctxt_md1, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md1;
+#define REG_RD_ADDR_dma_rw_ctxt_md1 56
+#define REG_WR_ADDR_dma_rw_ctxt_md1 56
+
+/* Register rw_ctxt_md1_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md1_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
+#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
+
+/* Register rw_ctxt_md2, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md2;
+#define REG_RD_ADDR_dma_rw_ctxt_md2 64
+#define REG_WR_ADDR_dma_rw_ctxt_md2 64
+
+/* Register rw_ctxt_md2_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md2_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
+#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
+
+/* Register rw_ctxt_md3, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md3;
+#define REG_RD_ADDR_dma_rw_ctxt_md3 72
+#define REG_WR_ADDR_dma_rw_ctxt_md3 72
+
+/* Register rw_ctxt_md3_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md3_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
+#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
+
+/* Register rw_ctxt_md4, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md4;
+#define REG_RD_ADDR_dma_rw_ctxt_md4 80
+#define REG_WR_ADDR_dma_rw_ctxt_md4 80
+
+/* Register rw_ctxt_md4_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md4_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
+#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
+
+/* Register rw_saved_data, scope dma, type rw */
+typedef unsigned int reg_dma_rw_saved_data;
+#define REG_RD_ADDR_dma_rw_saved_data 88
+#define REG_WR_ADDR_dma_rw_saved_data 88
+
+/* Register rw_saved_data_buf, scope dma, type rw */
+typedef unsigned int reg_dma_rw_saved_data_buf;
+#define REG_RD_ADDR_dma_rw_saved_data_buf 92
+#define REG_WR_ADDR_dma_rw_saved_data_buf 92
+
+/* Register rw_group, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group;
+#define REG_RD_ADDR_dma_rw_group 96
+#define REG_WR_ADDR_dma_rw_group 96
+
+/* Register rw_group_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_next;
+#define REG_RD_ADDR_dma_rw_group_next 100
+#define REG_WR_ADDR_dma_rw_group_next 100
+
+/* Register rw_group_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol  : 1;
+  unsigned int tol  : 1;
+  unsigned int bol  : 1;
+  unsigned int dummy1 : 1;
+  unsigned int intr : 1;
+  unsigned int dummy2 : 2;
+  unsigned int en   : 1;
+  unsigned int dummy3 : 24;
+} reg_dma_rw_group_ctrl;
+#define REG_RD_ADDR_dma_rw_group_ctrl 104
+#define REG_WR_ADDR_dma_rw_group_ctrl 104
+
+/* Register rw_group_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 7;
+  unsigned int dis : 1;
+  unsigned int dummy2 : 24;
+} reg_dma_rw_group_stat;
+#define REG_RD_ADDR_dma_rw_group_stat 108
+#define REG_WR_ADDR_dma_rw_group_stat 108
+
+/* Register rw_group_md, scope dma, type rw */
+typedef struct {
+  unsigned int md : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_group_md;
+#define REG_RD_ADDR_dma_rw_group_md 112
+#define REG_WR_ADDR_dma_rw_group_md 112
+
+/* Register rw_group_md_s, scope dma, type rw */
+typedef struct {
+  unsigned int md_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_group_md_s;
+#define REG_RD_ADDR_dma_rw_group_md_s 116
+#define REG_WR_ADDR_dma_rw_group_md_s 116
+
+/* Register rw_group_up, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_up;
+#define REG_RD_ADDR_dma_rw_group_up 120
+#define REG_WR_ADDR_dma_rw_group_up 120
+
+/* Register rw_group_down, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_down;
+#define REG_RD_ADDR_dma_rw_group_down 124
+#define REG_WR_ADDR_dma_rw_group_down 124
+
+/* Register rw_cmd, scope dma, type rw */
+typedef struct {
+  unsigned int cont_data : 1;
+  unsigned int dummy1    : 31;
+} reg_dma_rw_cmd;
+#define REG_RD_ADDR_dma_rw_cmd 128
+#define REG_WR_ADDR_dma_rw_cmd 128
+
+/* Register rw_cfg, scope dma, type rw */
+typedef struct {
+  unsigned int en   : 1;
+  unsigned int stop : 1;
+  unsigned int dummy1 : 30;
+} reg_dma_rw_cfg;
+#define REG_RD_ADDR_dma_rw_cfg 132
+#define REG_WR_ADDR_dma_rw_cfg 132
+
+/* Register rw_stat, scope dma, type rw */
+typedef struct {
+  unsigned int mode           : 5;
+  unsigned int list_state     : 3;
+  unsigned int stream_cmd_src : 8;
+  unsigned int dummy1         : 8;
+  unsigned int buf            : 8;
+} reg_dma_rw_stat;
+#define REG_RD_ADDR_dma_rw_stat 136
+#define REG_WR_ADDR_dma_rw_stat 136
+
+/* Register rw_intr_mask, scope dma, type rw */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_rw_intr_mask;
+#define REG_RD_ADDR_dma_rw_intr_mask 140
+#define REG_WR_ADDR_dma_rw_intr_mask 140
+
+/* Register rw_ack_intr, scope dma, type rw */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_rw_ack_intr;
+#define REG_RD_ADDR_dma_rw_ack_intr 144
+#define REG_WR_ADDR_dma_rw_ack_intr 144
+
+/* Register r_intr, scope dma, type r */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_r_intr;
+#define REG_RD_ADDR_dma_r_intr 148
+
+/* Register r_masked_intr, scope dma, type r */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_r_masked_intr;
+#define REG_RD_ADDR_dma_r_masked_intr 152
+
+/* Register rw_stream_cmd, scope dma, type rw */
+typedef struct {
+  unsigned int cmd  : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n    : 8;
+  unsigned int dummy2 : 7;
+  unsigned int busy : 1;
+} reg_dma_rw_stream_cmd;
+#define REG_RD_ADDR_dma_rw_stream_cmd 156
+#define REG_WR_ADDR_dma_rw_stream_cmd 156
+
+
+/* Constants */
+enum {
+  regk_dma_ack_pkt                         = 0x00000100,
+  regk_dma_anytime                         = 0x00000001,
+  regk_dma_array                           = 0x00000008,
+  regk_dma_burst                           = 0x00000020,
+  regk_dma_client                          = 0x00000002,
+  regk_dma_copy_next                       = 0x00000010,
+  regk_dma_copy_up                         = 0x00000020,
+  regk_dma_data_at_eol                     = 0x00000001,
+  regk_dma_dis_c                           = 0x00000010,
+  regk_dma_dis_g                           = 0x00000020,
+  regk_dma_idle                            = 0x00000001,
+  regk_dma_intern                          = 0x00000004,
+  regk_dma_load_c                          = 0x00000200,
+  regk_dma_load_c_n                        = 0x00000280,
+  regk_dma_load_c_next                     = 0x00000240,
+  regk_dma_load_d                          = 0x00000140,
+  regk_dma_load_g                          = 0x00000300,
+  regk_dma_load_g_down                     = 0x000003c0,
+  regk_dma_load_g_next                     = 0x00000340,
+  regk_dma_load_g_up                       = 0x00000380,
+  regk_dma_next_en                         = 0x00000010,
+  regk_dma_next_pkt                        = 0x00000010,
+  regk_dma_no                              = 0x00000000,
+  regk_dma_only_at_wait                    = 0x00000000,
+  regk_dma_restore                         = 0x00000020,
+  regk_dma_rst                             = 0x00000001,
+  regk_dma_running                         = 0x00000004,
+  regk_dma_rw_cfg_default                  = 0x00000000,
+  regk_dma_rw_cmd_default                  = 0x00000000,
+  regk_dma_rw_intr_mask_default            = 0x00000000,
+  regk_dma_rw_stat_default                 = 0x00000101,
+  regk_dma_rw_stream_cmd_default           = 0x00000000,
+  regk_dma_save_down                       = 0x00000020,
+  regk_dma_save_up                         = 0x00000020,
+  regk_dma_set_reg                         = 0x00000050,
+  regk_dma_set_w_size1                     = 0x00000190,
+  regk_dma_set_w_size2                     = 0x000001a0,
+  regk_dma_set_w_size4                     = 0x000001c0,
+  regk_dma_stopped                         = 0x00000002,
+  regk_dma_store_c                         = 0x00000002,
+  regk_dma_store_descr                     = 0x00000000,
+  regk_dma_store_g                         = 0x00000004,
+  regk_dma_store_md                        = 0x00000001,
+  regk_dma_sw                              = 0x00000008,
+  regk_dma_update_down                     = 0x00000020,
+  regk_dma_yes                             = 0x00000001
+};
+#endif /* __dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h
new file mode 100644
index 000000000000..1196d7cc783f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h
@@ -0,0 +1,384 @@
+#ifndef __eth_defs_h
+#define __eth_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/eth/rtl/eth_regs.r
+ *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
+ *     last modfied: Mon Apr 11 16:07:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r
+ *      id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope eth */
+
+/* Register rw_ma0_lo, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_eth_rw_ma0_lo;
+#define REG_RD_ADDR_eth_rw_ma0_lo 0
+#define REG_WR_ADDR_eth_rw_ma0_lo 0
+
+/* Register rw_ma0_hi, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 16;
+  unsigned int dummy1 : 16;
+} reg_eth_rw_ma0_hi;
+#define REG_RD_ADDR_eth_rw_ma0_hi 4
+#define REG_WR_ADDR_eth_rw_ma0_hi 4
+
+/* Register rw_ma1_lo, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_eth_rw_ma1_lo;
+#define REG_RD_ADDR_eth_rw_ma1_lo 8
+#define REG_WR_ADDR_eth_rw_ma1_lo 8
+
+/* Register rw_ma1_hi, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 16;
+  unsigned int dummy1 : 16;
+} reg_eth_rw_ma1_hi;
+#define REG_RD_ADDR_eth_rw_ma1_hi 12
+#define REG_WR_ADDR_eth_rw_ma1_hi 12
+
+/* Register rw_ga_lo, scope eth, type rw */
+typedef struct {
+  unsigned int table : 32;
+} reg_eth_rw_ga_lo;
+#define REG_RD_ADDR_eth_rw_ga_lo 16
+#define REG_WR_ADDR_eth_rw_ga_lo 16
+
+/* Register rw_ga_hi, scope eth, type rw */
+typedef struct {
+  unsigned int table : 32;
+} reg_eth_rw_ga_hi;
+#define REG_RD_ADDR_eth_rw_ga_hi 20
+#define REG_WR_ADDR_eth_rw_ga_hi 20
+
+/* Register rw_gen_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int en            : 1;
+  unsigned int phy           : 2;
+  unsigned int protocol      : 1;
+  unsigned int loopback      : 1;
+  unsigned int flow_ctrl_dis : 1;
+  unsigned int dummy1        : 26;
+} reg_eth_rw_gen_ctrl;
+#define REG_RD_ADDR_eth_rw_gen_ctrl 24
+#define REG_WR_ADDR_eth_rw_gen_ctrl 24
+
+/* Register rw_rec_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int ma0        : 1;
+  unsigned int ma1        : 1;
+  unsigned int individual : 1;
+  unsigned int broadcast  : 1;
+  unsigned int undersize  : 1;
+  unsigned int oversize   : 1;
+  unsigned int bad_crc    : 1;
+  unsigned int duplex     : 1;
+  unsigned int max_size   : 1;
+  unsigned int dummy1     : 23;
+} reg_eth_rw_rec_ctrl;
+#define REG_RD_ADDR_eth_rw_rec_ctrl 28
+#define REG_WR_ADDR_eth_rw_rec_ctrl 28
+
+/* Register rw_tr_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int crc        : 1;
+  unsigned int pad        : 1;
+  unsigned int retry      : 1;
+  unsigned int ignore_col : 1;
+  unsigned int cancel     : 1;
+  unsigned int hsh_delay  : 1;
+  unsigned int ignore_crs : 1;
+  unsigned int dummy1     : 25;
+} reg_eth_rw_tr_ctrl;
+#define REG_RD_ADDR_eth_rw_tr_ctrl 32
+#define REG_WR_ADDR_eth_rw_tr_ctrl 32
+
+/* Register rw_clr_err, scope eth, type rw */
+typedef struct {
+  unsigned int clr : 1;
+  unsigned int dummy1 : 31;
+} reg_eth_rw_clr_err;
+#define REG_RD_ADDR_eth_rw_clr_err 36
+#define REG_WR_ADDR_eth_rw_clr_err 36
+
+/* Register rw_mgm_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int mdio   : 1;
+  unsigned int mdoe   : 1;
+  unsigned int mdc    : 1;
+  unsigned int phyclk : 1;
+  unsigned int txdata : 4;
+  unsigned int txen   : 1;
+  unsigned int dummy1 : 23;
+} reg_eth_rw_mgm_ctrl;
+#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
+#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
+
+/* Register r_stat, scope eth, type r */
+typedef struct {
+  unsigned int mdio    : 1;
+  unsigned int exc_col : 1;
+  unsigned int urun    : 1;
+  unsigned int phyclk  : 1;
+  unsigned int txdata  : 4;
+  unsigned int txen    : 1;
+  unsigned int col     : 1;
+  unsigned int crs     : 1;
+  unsigned int txclk   : 1;
+  unsigned int rxdata  : 4;
+  unsigned int rxer    : 1;
+  unsigned int rxdv    : 1;
+  unsigned int rxclk   : 1;
+  unsigned int dummy1  : 13;
+} reg_eth_r_stat;
+#define REG_RD_ADDR_eth_r_stat 44
+
+/* Register rs_rec_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int crc_err    : 8;
+  unsigned int align_err  : 8;
+  unsigned int oversize   : 8;
+  unsigned int congestion : 8;
+} reg_eth_rs_rec_cnt;
+#define REG_RD_ADDR_eth_rs_rec_cnt 48
+
+/* Register r_rec_cnt, scope eth, type r */
+typedef struct {
+  unsigned int crc_err    : 8;
+  unsigned int align_err  : 8;
+  unsigned int oversize   : 8;
+  unsigned int congestion : 8;
+} reg_eth_r_rec_cnt;
+#define REG_RD_ADDR_eth_r_rec_cnt 52
+
+/* Register rs_tr_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int single_col : 8;
+  unsigned int mult_col   : 8;
+  unsigned int late_col   : 8;
+  unsigned int deferred   : 8;
+} reg_eth_rs_tr_cnt;
+#define REG_RD_ADDR_eth_rs_tr_cnt 56
+
+/* Register r_tr_cnt, scope eth, type r */
+typedef struct {
+  unsigned int single_col : 8;
+  unsigned int mult_col   : 8;
+  unsigned int late_col   : 8;
+  unsigned int deferred   : 8;
+} reg_eth_r_tr_cnt;
+#define REG_RD_ADDR_eth_r_tr_cnt 60
+
+/* Register rs_phy_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int carrier_loss : 8;
+  unsigned int sqe_err      : 8;
+  unsigned int dummy1       : 16;
+} reg_eth_rs_phy_cnt;
+#define REG_RD_ADDR_eth_rs_phy_cnt 64
+
+/* Register r_phy_cnt, scope eth, type r */
+typedef struct {
+  unsigned int carrier_loss : 8;
+  unsigned int sqe_err      : 8;
+  unsigned int dummy1       : 16;
+} reg_eth_r_phy_cnt;
+#define REG_RD_ADDR_eth_r_phy_cnt 68
+
+/* Register rw_test_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int snmp_inc : 1;
+  unsigned int snmp     : 1;
+  unsigned int backoff  : 1;
+  unsigned int dummy1   : 29;
+} reg_eth_rw_test_ctrl;
+#define REG_RD_ADDR_eth_rw_test_ctrl 72
+#define REG_WR_ADDR_eth_rw_test_ctrl 72
+
+/* Register rw_intr_mask, scope eth, type rw */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_rw_intr_mask;
+#define REG_RD_ADDR_eth_rw_intr_mask 76
+#define REG_WR_ADDR_eth_rw_intr_mask 76
+
+/* Register rw_ack_intr, scope eth, type rw */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_rw_ack_intr;
+#define REG_RD_ADDR_eth_rw_ack_intr 80
+#define REG_WR_ADDR_eth_rw_ack_intr 80
+
+/* Register r_intr, scope eth, type r */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_r_intr;
+#define REG_RD_ADDR_eth_r_intr 84
+
+/* Register r_masked_intr, scope eth, type r */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_r_masked_intr;
+#define REG_RD_ADDR_eth_r_masked_intr 88
+
+
+/* Constants */
+enum {
+  regk_eth_discard                         = 0x00000000,
+  regk_eth_ether                           = 0x00000000,
+  regk_eth_full                            = 0x00000001,
+  regk_eth_half                            = 0x00000000,
+  regk_eth_hsh                             = 0x00000001,
+  regk_eth_mii                             = 0x00000001,
+  regk_eth_mii_clk                         = 0x00000000,
+  regk_eth_mii_rec                         = 0x00000002,
+  regk_eth_no                              = 0x00000000,
+  regk_eth_rec                             = 0x00000001,
+  regk_eth_rw_ga_hi_default                = 0x00000000,
+  regk_eth_rw_ga_lo_default                = 0x00000000,
+  regk_eth_rw_gen_ctrl_default             = 0x00000000,
+  regk_eth_rw_intr_mask_default            = 0x00000000,
+  regk_eth_rw_ma0_hi_default               = 0x00000000,
+  regk_eth_rw_ma0_lo_default               = 0x00000000,
+  regk_eth_rw_ma1_hi_default               = 0x00000000,
+  regk_eth_rw_ma1_lo_default               = 0x00000000,
+  regk_eth_rw_mgm_ctrl_default             = 0x00000000,
+  regk_eth_rw_test_ctrl_default            = 0x00000000,
+  regk_eth_size1518                        = 0x00000000,
+  regk_eth_size1522                        = 0x00000001,
+  regk_eth_yes                             = 0x00000001
+};
+#endif /* __eth_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
new file mode 100644
index 000000000000..c47b5ca48ece
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
@@ -0,0 +1,369 @@
+#ifndef __extmem_defs_h
+#define __extmem_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ext_mem/mod/extmem_regs.r
+ *     id:           extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
+ *     last modfied: Tue Mar 30 22:26:21 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
+ *      id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope extmem */
+
+/* Register rw_cse0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_cse0_cfg;
+#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
+#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
+
+/* Register rw_cse1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_cse1_cfg;
+#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
+#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
+
+/* Register rw_csr0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csr0_cfg;
+#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
+#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
+
+/* Register rw_csr1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csr1_cfg;
+#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
+#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
+
+/* Register rw_csp0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp0_cfg;
+#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
+#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
+
+/* Register rw_csp1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp1_cfg;
+#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
+#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
+
+/* Register rw_csp2_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp2_cfg;
+#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
+#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
+
+/* Register rw_csp3_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp3_cfg;
+#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
+#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
+
+/* Register rw_csp4_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp4_cfg;
+#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
+#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
+
+/* Register rw_csp5_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp5_cfg;
+#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
+#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
+
+/* Register rw_csp6_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp6_cfg;
+#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
+#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
+
+/* Register rw_css_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_css_cfg;
+#define REG_RD_ADDR_extmem_rw_css_cfg 44
+#define REG_WR_ADDR_extmem_rw_css_cfg 44
+
+/* Register rw_status_handle, scope extmem, type rw */
+typedef struct {
+  unsigned int h : 32;
+} reg_extmem_rw_status_handle;
+#define REG_RD_ADDR_extmem_rw_status_handle 48
+#define REG_WR_ADDR_extmem_rw_status_handle 48
+
+/* Register rw_wait_pin, scope extmem, type rw */
+typedef struct {
+  unsigned int val   : 16;
+  unsigned int dummy1 : 15;
+  unsigned int start : 1;
+} reg_extmem_rw_wait_pin;
+#define REG_RD_ADDR_extmem_rw_wait_pin 52
+#define REG_WR_ADDR_extmem_rw_wait_pin 52
+
+/* Register rw_gated_csp, scope extmem, type rw */
+typedef struct {
+  unsigned int dummy1 : 31;
+  unsigned int en : 1;
+} reg_extmem_rw_gated_csp;
+#define REG_RD_ADDR_extmem_rw_gated_csp 56
+#define REG_WR_ADDR_extmem_rw_gated_csp 56
+
+
+/* Constants */
+enum {
+  regk_extmem_b16                          = 0x00000001,
+  regk_extmem_b32                          = 0x00000000,
+  regk_extmem_bwe                          = 0x00000000,
+  regk_extmem_cwe                          = 0x00000001,
+  regk_extmem_no                           = 0x00000000,
+  regk_extmem_rw_cse0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_cse1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp2_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp3_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp4_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp5_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp6_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csr0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csr1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_css_cfg_default           = 0x000006cf,
+  regk_extmem_s128KB                       = 0x00000000,
+  regk_extmem_s16MB                        = 0x00000005,
+  regk_extmem_s1MB                         = 0x00000001,
+  regk_extmem_s2MB                         = 0x00000002,
+  regk_extmem_s32MB                        = 0x00000006,
+  regk_extmem_s4MB                         = 0x00000003,
+  regk_extmem_s64MB                        = 0x00000007,
+  regk_extmem_s8MB                         = 0x00000004,
+  regk_extmem_yes                          = 0x00000001
+};
+#endif /* __extmem_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h
new file mode 100644
index 000000000000..3e9a0b25366f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/gio_defs.h
@@ -0,0 +1,295 @@
+#ifndef __gio_defs_h
+#define __gio_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/gio/rtl/gio_regs.r
+ *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ *     last modfied: Mon Apr 11 16:07:47 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
+ *      id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope gio */
+
+/* Register rw_pa_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_pa_dout;
+#define REG_RD_ADDR_gio_rw_pa_dout 0
+#define REG_WR_ADDR_gio_rw_pa_dout 0
+
+/* Register r_pa_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_r_pa_din;
+#define REG_RD_ADDR_gio_r_pa_din 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_pa_oe;
+#define REG_RD_ADDR_gio_rw_pa_oe 8
+#define REG_WR_ADDR_gio_rw_pa_oe 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 3;
+  unsigned int pa1 : 3;
+  unsigned int pa2 : 3;
+  unsigned int pa3 : 3;
+  unsigned int pa4 : 3;
+  unsigned int pa5 : 3;
+  unsigned int pa6 : 3;
+  unsigned int pa7 : 3;
+  unsigned int dummy1 : 8;
+} reg_gio_rw_intr_cfg;
+#define REG_RD_ADDR_gio_rw_intr_cfg 12
+#define REG_WR_ADDR_gio_rw_intr_cfg 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_intr_mask;
+#define REG_RD_ADDR_gio_rw_intr_mask 16
+#define REG_WR_ADDR_gio_rw_intr_mask 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_ack_intr;
+#define REG_RD_ADDR_gio_rw_ack_intr 20
+#define REG_WR_ADDR_gio_rw_ack_intr 20
+
+/* Register r_intr, scope gio, type r */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_r_intr;
+#define REG_RD_ADDR_gio_r_intr 24
+
+/* Register r_masked_intr, scope gio, type r */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_r_masked_intr;
+#define REG_RD_ADDR_gio_r_masked_intr 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pb_dout;
+#define REG_RD_ADDR_gio_rw_pb_dout 32
+#define REG_WR_ADDR_gio_rw_pb_dout 32
+
+/* Register r_pb_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pb_din;
+#define REG_RD_ADDR_gio_r_pb_din 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pb_oe;
+#define REG_RD_ADDR_gio_rw_pb_oe 40
+#define REG_WR_ADDR_gio_rw_pb_oe 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pc_dout;
+#define REG_RD_ADDR_gio_rw_pc_dout 48
+#define REG_WR_ADDR_gio_rw_pc_dout 48
+
+/* Register r_pc_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pc_din;
+#define REG_RD_ADDR_gio_r_pc_din 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pc_oe;
+#define REG_RD_ADDR_gio_rw_pc_oe 56
+#define REG_WR_ADDR_gio_rw_pc_oe 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pd_dout;
+#define REG_RD_ADDR_gio_rw_pd_dout 64
+#define REG_WR_ADDR_gio_rw_pd_dout 64
+
+/* Register r_pd_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pd_din;
+#define REG_RD_ADDR_gio_r_pd_din 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pd_oe;
+#define REG_RD_ADDR_gio_rw_pd_oe 72
+#define REG_WR_ADDR_gio_rw_pd_oe 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pe_dout;
+#define REG_RD_ADDR_gio_rw_pe_dout 80
+#define REG_WR_ADDR_gio_rw_pe_dout 80
+
+/* Register r_pe_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pe_din;
+#define REG_RD_ADDR_gio_r_pe_din 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pe_oe;
+#define REG_RD_ADDR_gio_rw_pe_oe 88
+#define REG_WR_ADDR_gio_rw_pe_oe 88
+
+
+/* Constants */
+enum {
+  regk_gio_anyedge                         = 0x00000007,
+  regk_gio_hi                              = 0x00000001,
+  regk_gio_lo                              = 0x00000002,
+  regk_gio_negedge                         = 0x00000006,
+  regk_gio_no                              = 0x00000000,
+  regk_gio_off                             = 0x00000000,
+  regk_gio_posedge                         = 0x00000005,
+  regk_gio_rw_intr_cfg_default             = 0x00000000,
+  regk_gio_rw_intr_mask_default            = 0x00000000,
+  regk_gio_rw_pa_oe_default                = 0x00000000,
+  regk_gio_rw_pb_oe_default                = 0x00000000,
+  regk_gio_rw_pc_oe_default                = 0x00000000,
+  regk_gio_rw_pd_oe_default                = 0x00000000,
+  regk_gio_rw_pe_oe_default                = 0x00000000,
+  regk_gio_set                             = 0x00000003,
+  regk_gio_yes                             = 0x00000001
+};
+#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h
new file mode 100644
index 000000000000..5c1b28fb205d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect.h
@@ -0,0 +1,39 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+version . */
+
+#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define MEMARB_INTR_VECT        0x31
+#define GEN_IO_INTR_VECT        0x32
+#define IOP0_INTR_VECT  0x33
+#define IOP1_INTR_VECT  0x34
+#define IOP2_INTR_VECT  0x35
+#define IOP3_INTR_VECT  0x36
+#define DMA0_INTR_VECT  0x37
+#define DMA1_INTR_VECT  0x38
+#define DMA2_INTR_VECT  0x39
+#define DMA3_INTR_VECT  0x3a
+#define DMA4_INTR_VECT  0x3b
+#define DMA5_INTR_VECT  0x3c
+#define DMA6_INTR_VECT  0x3d
+#define DMA7_INTR_VECT  0x3e
+#define DMA8_INTR_VECT  0x3f
+#define DMA9_INTR_VECT  0x40
+#define ATA_INTR_VECT   0x41
+#define SSER0_INTR_VECT 0x42
+#define SSER1_INTR_VECT 0x43
+#define SER0_INTR_VECT  0x44
+#define SER1_INTR_VECT  0x45
+#define SER2_INTR_VECT  0x46
+#define SER3_INTR_VECT  0x47
+#define P21_INTR_VECT   0x48
+#define ETH0_INTR_VECT  0x49
+#define ETH1_INTR_VECT  0x4a
+#define TIMER_INTR_VECT 0x4b
+#define BIF_ARB_INTR_VECT       0x4c
+#define BIF_DMA_INTR_VECT       0x4d
+#define EXT_INTR_VECT   0x4e
+#define IPI_INTR_VECT   0x4f
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
new file mode 100644
index 000000000000..535aaf1b4b52
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
@@ -0,0 +1,225 @@
+#ifndef __intr_vect_defs_h
+#define __intr_vect_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
+ *     last modfied: Mon Apr 11 16:08:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *      id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope intr_vect */
+
+/* Register rw_mask, scope intr_vect, type rw */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_rw_mask;
+#define REG_RD_ADDR_intr_vect_rw_mask 0
+#define REG_WR_ADDR_intr_vect_rw_mask 0
+
+/* Register r_vect, scope intr_vect, type r */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_r_vect;
+#define REG_RD_ADDR_intr_vect_r_vect 4
+
+/* Register r_masked_vect, scope intr_vect, type r */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_r_masked_vect;
+#define REG_RD_ADDR_intr_vect_r_masked_vect 8
+
+/* Register r_nmi, scope intr_vect, type r */
+typedef struct {
+  unsigned int ext      : 1;
+  unsigned int watchdog : 1;
+  unsigned int dummy1   : 30;
+} reg_intr_vect_r_nmi;
+#define REG_RD_ADDR_intr_vect_r_nmi 12
+
+/* Register r_guru, scope intr_vect, type r */
+typedef struct {
+  unsigned int jtag : 1;
+  unsigned int dummy1 : 31;
+} reg_intr_vect_r_guru;
+#define REG_RD_ADDR_intr_vect_r_guru 16
+
+/* Register rw_ipi, scope intr_vect, type rw */
+typedef struct
+{
+  unsigned int vector;
+} reg_intr_vect_rw_ipi;
+#define REG_RD_ADDR_intr_vect_rw_ipi 20
+#define REG_WR_ADDR_intr_vect_rw_ipi 20
+
+/* Constants */
+enum {
+  regk_intr_vect_off                       = 0x00000000,
+  regk_intr_vect_on                        = 0x00000001,
+  regk_intr_vect_rw_mask_default           = 0x00000000
+};
+#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile
new file mode 100644
index 000000000000..a90056a095e3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/Makefile
@@ -0,0 +1,146 @@
+# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
+# Makefile to generate or copy the latest register definitions
+# and related datastructures and helpermacros.
+# The offical place for these files is probably at:
+RELEASE ?= r1_alfa5
+IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
+
+IOPROCDIR = /n/asic/design/io/io_proc/rtl
+
+IOPROCINCL_FILES =
+IOPROCINCL_FILES2=
+IOPROCINCL_FILES += iop_crc_par_defs.h
+IOPROCINCL_FILES += iop_dmc_in_defs.h
+IOPROCINCL_FILES += iop_dmc_out_defs.h
+IOPROCINCL_FILES += iop_fifo_in_defs.h
+IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
+IOPROCINCL_FILES += iop_fifo_out_defs.h
+IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
+IOPROCINCL_FILES += iop_mpu_defs.h
+IOPROCINCL_FILES2+= iop_mpu_macros.h
+IOPROCINCL_FILES2+= iop_reg_space.h
+IOPROCINCL_FILES += iop_sap_in_defs.h
+IOPROCINCL_FILES += iop_sap_out_defs.h
+IOPROCINCL_FILES += iop_scrc_in_defs.h
+IOPROCINCL_FILES += iop_scrc_out_defs.h
+IOPROCINCL_FILES += iop_spu_defs.h
+# in guiness/
+IOPROCINCL_FILES += iop_sw_cfg_defs.h
+IOPROCINCL_FILES += iop_sw_cpu_defs.h
+IOPROCINCL_FILES += iop_sw_mpu_defs.h
+IOPROCINCL_FILES += iop_sw_spu_defs.h
+#
+IOPROCINCL_FILES += iop_timer_grp_defs.h
+IOPROCINCL_FILES += iop_trigger_grp_defs.h
+# in guiness/
+IOPROCINCL_FILES += iop_version_defs.h
+
+IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
+IOPROCASMINCL_FILES+= iop_reg_space_asm.h
+
+
+IOPROCREGDESC =
+IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
+#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
+
+
+RDES2C = /n/asic/bin/rdes2c
+RDES2C = /n/asic/design/tools/rdesc/rdes2c
+RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
+RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
+
+## all    - Just print help - you probably want to do 'make gen'
+all: help
+
+## help   - This help
+help:
+        @grep '^## ' Makefile
+
+## gen    - Generate include files
+gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
+        echo "INCL: $(IOPROCINCL_FILES)"
+        echo "INCL2: $(IOPROCINCL_FILES2)"
+        echo "ASMINCL: $(IOPROCASMINCL_FILES)"
+
+# From the official location...
+iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
+        cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+
+## copy   - Copy files from official location
+copy:
+        @echo "## Copying and fixing iop files ##"
+        @for HFILE in $(IOPROCINCL_FILES); do \
+                echo "  $$HFILE"; \
+                cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+        done
+        @for HFILE in $(IOPROCINCL_FILES2); do \
+                echo "  $$HFILE"; \
+                cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+        done
+        @echo "## Copying and fixing iop asm files ##"
+        @for HFILE in $(IOPROCASMINCL_FILES); do \
+                echo "  $$HFILE"; \
+                cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
+        done
+
+# I/O processor files:
+## iop    - Generate I/O processor include files
+iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
+iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
+        $(RDES2C) $<
+iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
+        $(RDES2C) $<
+%_defs.h: $(IOPROCDIR)/%.r
+        $(RDES2C) $<
+%_defs_asm.h: $(IOPROCDIR)/%.r
+        $(RDES2C) -asm $<
+iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
+        $(RDES2C) -asm $<
+
+## doc    - Generate .axw files from register description.
+doc: $(IOPROCREGDESC)
+        for RDES in $^; do \
+                $(RDES2TXT) $$RDES; \
+        done
+
+.PHONY: axw
+## %.axw  - Generate the specified .axw file (doesn't work for all files
+##          due to inconsistent naming of .r files.
+%.axw: axw
+        @for RDES in $(IOPROCREGDESC); do \
+                if echo "$$RDES" | grep $* ; then \
+                  $(RDES2TXT) $$RDES; \
+                fi \
+        done
+
+.PHONY: clean
+## clean  - Remove .h files and .axw files.
+clean:
+        rm -rf $(IOPROCINCL_FILES) *.axw
+
+.PHONY: cleandoc
+## cleandoc  - Remove .axw files.
+cleandoc:
+        rm -rf *.axw
+
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
new file mode 100644
index 000000000000..a4b58000c164
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
@@ -0,0 +1,171 @@
+#ifndef __iop_crc_par_defs_asm_h
+#define __iop_crc_par_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
+ *      id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_cfg___mode___lsb 0
+#define reg_iop_crc_par_rw_cfg___mode___width 1
+#define reg_iop_crc_par_rw_cfg___mode___bit 0
+#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
+#define reg_iop_crc_par_rw_cfg___crc_out___width 1
+#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
+#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
+#define reg_iop_crc_par_rw_cfg___rev_out___width 1
+#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
+#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
+#define reg_iop_crc_par_rw_cfg___inv_out___width 1
+#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
+#define reg_iop_crc_par_rw_cfg___trig___lsb 4
+#define reg_iop_crc_par_rw_cfg___trig___width 2
+#define reg_iop_crc_par_rw_cfg___poly___lsb 6
+#define reg_iop_crc_par_rw_cfg___poly___width 3
+#define reg_iop_crc_par_rw_cfg_offset 0
+
+/* Register rw_init_crc, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_init_crc_offset 4
+
+/* Register rw_correct_crc, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_correct_crc_offset 8
+
+/* Register rw_ctrl, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_ctrl___en___lsb 0
+#define reg_iop_crc_par_rw_ctrl___en___width 1
+#define reg_iop_crc_par_rw_ctrl___en___bit 0
+#define reg_iop_crc_par_rw_ctrl_offset 12
+
+/* Register rw_set_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
+#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
+#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
+#define reg_iop_crc_par_rw_set_last_offset 16
+
+/* Register rw_wr1byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr1byte___data___width 8
+#define reg_iop_crc_par_rw_wr1byte_offset 20
+
+/* Register rw_wr2byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr2byte___data___width 16
+#define reg_iop_crc_par_rw_wr2byte_offset 24
+
+/* Register rw_wr3byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr3byte___data___width 24
+#define reg_iop_crc_par_rw_wr3byte_offset 28
+
+/* Register rw_wr4byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr4byte___data___width 32
+#define reg_iop_crc_par_rw_wr4byte_offset 32
+
+/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
+#define reg_iop_crc_par_rw_wr1byte_last_offset 36
+
+/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
+#define reg_iop_crc_par_rw_wr2byte_last_offset 40
+
+/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
+#define reg_iop_crc_par_rw_wr3byte_last_offset 44
+
+/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
+#define reg_iop_crc_par_rw_wr4byte_last_offset 48
+
+/* Register r_stat, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_stat___err___lsb 0
+#define reg_iop_crc_par_r_stat___err___width 1
+#define reg_iop_crc_par_r_stat___err___bit 0
+#define reg_iop_crc_par_r_stat___busy___lsb 1
+#define reg_iop_crc_par_r_stat___busy___width 1
+#define reg_iop_crc_par_r_stat___busy___bit 1
+#define reg_iop_crc_par_r_stat_offset 52
+
+/* Register r_sh_reg, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_sh_reg_offset 56
+
+/* Register r_crc, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_crc_offset 60
+
+/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
+#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
+#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
+
+
+/* Constants */
+#define regk_iop_crc_par_calc                     0x00000001
+#define regk_iop_crc_par_ccitt                    0x00000002
+#define regk_iop_crc_par_check                    0x00000000
+#define regk_iop_crc_par_crc16                    0x00000001
+#define regk_iop_crc_par_crc32                    0x00000000
+#define regk_iop_crc_par_crc5                     0x00000003
+#define regk_iop_crc_par_crc5_11                  0x00000004
+#define regk_iop_crc_par_dif_in                   0x00000002
+#define regk_iop_crc_par_hi                       0x00000000
+#define regk_iop_crc_par_neg                      0x00000002
+#define regk_iop_crc_par_no                       0x00000000
+#define regk_iop_crc_par_pos                      0x00000001
+#define regk_iop_crc_par_pos_neg                  0x00000003
+#define regk_iop_crc_par_rw_cfg_default           0x00000000
+#define regk_iop_crc_par_rw_ctrl_default          0x00000000
+#define regk_iop_crc_par_yes                      0x00000001
+#endif /* __iop_crc_par_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
new file mode 100644
index 000000000000..e7d539feccb1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
@@ -0,0 +1,321 @@
+#ifndef __iop_dmc_in_defs_asm_h
+#define __iop_dmc_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
+ *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
+ *      id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
+#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
+#define reg_iop_dmc_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
+#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
+#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
+#define reg_iop_dmc_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
+#define reg_iop_dmc_in_r_stat___dif_en___width 1
+#define reg_iop_dmc_in_r_stat___dif_en___bit 0
+#define reg_iop_dmc_in_r_stat_offset 8
+
+/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
+#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
+#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
+#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
+#define reg_iop_dmc_in_rw_stream_cmd_offset 12
+
+/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
+
+/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
+
+/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
+#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
+#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
+#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
+
+/* Register r_stream_stat, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
+#define reg_iop_dmc_in_r_stream_stat___sth___width 7
+#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
+#define reg_iop_dmc_in_r_stream_stat___full___width 1
+#define reg_iop_dmc_in_r_stream_stat___full___bit 16
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
+#define reg_iop_dmc_in_r_stream_stat_offset 28
+
+/* Register r_data_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_data_descr___stat___width 8
+#define reg_iop_dmc_in_r_data_descr___md___lsb 16
+#define reg_iop_dmc_in_r_data_descr___md___width 16
+#define reg_iop_dmc_in_r_data_descr_offset 32
+
+/* Register r_ctxt_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
+#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
+#define reg_iop_dmc_in_r_ctxt_descr_offset 36
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
+
+/* Register r_group_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_group_descr___stat___width 8
+#define reg_iop_dmc_in_r_group_descr___md___lsb 16
+#define reg_iop_dmc_in_r_group_descr___md___width 16
+#define reg_iop_dmc_in_r_group_descr_offset 56
+
+/* Register rw_data_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
+#define reg_iop_dmc_in_rw_data_descr___md___width 16
+#define reg_iop_dmc_in_rw_data_descr_offset 60
+
+/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
+#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
+
+/* Register rw_group_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
+#define reg_iop_dmc_in_rw_group_descr___md___width 16
+#define reg_iop_dmc_in_rw_group_descr_offset 84
+
+/* Register rw_intr_mask, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
+#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
+#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
+#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
+#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
+#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
+#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
+#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
+#define reg_iop_dmc_in_rw_intr_mask___full___width 1
+#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
+#define reg_iop_dmc_in_rw_intr_mask_offset 88
+
+/* Register rw_ack_intr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
+#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
+#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
+#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
+#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
+#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
+#define reg_iop_dmc_in_rw_ack_intr___full___width 1
+#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
+#define reg_iop_dmc_in_rw_ack_intr_offset 92
+
+/* Register r_intr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_intr___data_md___lsb 0
+#define reg_iop_dmc_in_r_intr___data_md___width 1
+#define reg_iop_dmc_in_r_intr___data_md___bit 0
+#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_r_intr___group_md___lsb 2
+#define reg_iop_dmc_in_r_intr___group_md___width 1
+#define reg_iop_dmc_in_r_intr___group_md___bit 2
+#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_r_intr___sth___lsb 4
+#define reg_iop_dmc_in_r_intr___sth___width 1
+#define reg_iop_dmc_in_r_intr___sth___bit 4
+#define reg_iop_dmc_in_r_intr___full___lsb 5
+#define reg_iop_dmc_in_r_intr___full___width 1
+#define reg_iop_dmc_in_r_intr___full___bit 5
+#define reg_iop_dmc_in_r_intr_offset 96
+
+/* Register r_masked_intr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
+#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
+#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
+#define reg_iop_dmc_in_r_masked_intr___sth___width 1
+#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
+#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
+#define reg_iop_dmc_in_r_masked_intr___full___width 1
+#define reg_iop_dmc_in_r_masked_intr___full___bit 5
+#define reg_iop_dmc_in_r_masked_intr_offset 100
+
+
+/* Constants */
+#define regk_iop_dmc_in_ack_pkt                   0x00000100
+#define regk_iop_dmc_in_array                     0x00000008
+#define regk_iop_dmc_in_burst                     0x00000020
+#define regk_iop_dmc_in_copy_next                 0x00000010
+#define regk_iop_dmc_in_copy_up                   0x00000020
+#define regk_iop_dmc_in_dis_c                     0x00000010
+#define regk_iop_dmc_in_dis_g                     0x00000020
+#define regk_iop_dmc_in_lim1                      0x00000000
+#define regk_iop_dmc_in_lim16                     0x00000004
+#define regk_iop_dmc_in_lim2                      0x00000001
+#define regk_iop_dmc_in_lim32                     0x00000005
+#define regk_iop_dmc_in_lim4                      0x00000002
+#define regk_iop_dmc_in_lim64                     0x00000006
+#define regk_iop_dmc_in_lim8                      0x00000003
+#define regk_iop_dmc_in_load_c                    0x00000200
+#define regk_iop_dmc_in_load_c_n                  0x00000280
+#define regk_iop_dmc_in_load_c_next               0x00000240
+#define regk_iop_dmc_in_load_d                    0x00000140
+#define regk_iop_dmc_in_load_g                    0x00000300
+#define regk_iop_dmc_in_load_g_down               0x000003c0
+#define regk_iop_dmc_in_load_g_next               0x00000340
+#define regk_iop_dmc_in_load_g_up                 0x00000380
+#define regk_iop_dmc_in_next_en                   0x00000010
+#define regk_iop_dmc_in_next_pkt                  0x00000010
+#define regk_iop_dmc_in_no                        0x00000000
+#define regk_iop_dmc_in_restore                   0x00000020
+#define regk_iop_dmc_in_rw_cfg_default            0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_default     0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_md1_default  0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_md2_default  0x00000000
+#define regk_iop_dmc_in_rw_data_descr_default     0x00000000
+#define regk_iop_dmc_in_rw_group_descr_default    0x00000000
+#define regk_iop_dmc_in_rw_intr_mask_default      0x00000000
+#define regk_iop_dmc_in_rw_stream_ctrl_default    0x00000000
+#define regk_iop_dmc_in_save_down                 0x00000020
+#define regk_iop_dmc_in_save_up                   0x00000020
+#define regk_iop_dmc_in_set_reg                   0x00000050
+#define regk_iop_dmc_in_set_w_size1               0x00000190
+#define regk_iop_dmc_in_set_w_size2               0x000001a0
+#define regk_iop_dmc_in_set_w_size4               0x000001c0
+#define regk_iop_dmc_in_store_c                   0x00000002
+#define regk_iop_dmc_in_store_descr               0x00000000
+#define regk_iop_dmc_in_store_g                   0x00000004
+#define regk_iop_dmc_in_store_md                  0x00000001
+#define regk_iop_dmc_in_update_down               0x00000020
+#define regk_iop_dmc_in_yes                       0x00000001
+#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
new file mode 100644
index 000000000000..9fe1a8054371
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
@@ -0,0 +1,349 @@
+#ifndef __iop_dmc_out_defs_asm_h
+#define __iop_dmc_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
+ *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
+ *      id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
+#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
+#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
+#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
+#define reg_iop_dmc_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
+#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
+#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
+#define reg_iop_dmc_out_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
+#define reg_iop_dmc_out_r_stat___dif_en___width 1
+#define reg_iop_dmc_out_r_stat___dif_en___bit 0
+#define reg_iop_dmc_out_r_stat_offset 8
+
+/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
+#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
+#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
+#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
+#define reg_iop_dmc_out_rw_stream_cmd_offset 12
+
+/* Register rs_stream_data, scope iop_dmc_out, type rs */
+#define reg_iop_dmc_out_rs_stream_data_offset 16
+
+/* Register r_stream_data, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stream_data_offset 20
+
+/* Register r_stream_stat, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
+#define reg_iop_dmc_out_r_stream_stat___dth___width 7
+#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
+#define reg_iop_dmc_out_r_stream_stat___dv___width 1
+#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
+#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
+#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
+#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
+#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
+#define reg_iop_dmc_out_r_stream_stat___last___width 1
+#define reg_iop_dmc_out_r_stream_stat___last___bit 18
+#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
+#define reg_iop_dmc_out_r_stream_stat___size___width 3
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
+#define reg_iop_dmc_out_r_stream_stat_offset 24
+
+/* Register r_data_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_data_descr___stat___width 8
+#define reg_iop_dmc_out_r_data_descr___md___lsb 16
+#define reg_iop_dmc_out_r_data_descr___md___width 16
+#define reg_iop_dmc_out_r_data_descr_offset 28
+
+/* Register r_ctxt_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
+#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
+#define reg_iop_dmc_out_r_ctxt_descr_offset 32
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
+
+/* Register r_group_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_group_descr___stat___width 8
+#define reg_iop_dmc_out_r_group_descr___md___lsb 16
+#define reg_iop_dmc_out_r_group_descr___md___width 16
+#define reg_iop_dmc_out_r_group_descr_offset 52
+
+/* Register rw_data_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
+#define reg_iop_dmc_out_rw_data_descr___md___width 16
+#define reg_iop_dmc_out_rw_data_descr_offset 56
+
+/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
+#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
+
+/* Register rw_group_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
+#define reg_iop_dmc_out_rw_group_descr___md___width 16
+#define reg_iop_dmc_out_rw_group_descr_offset 80
+
+/* Register rw_intr_mask, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
+#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
+#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
+#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
+#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
+#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
+#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
+#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
+#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
+#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
+#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
+#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
+#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
+#define reg_iop_dmc_out_rw_intr_mask_offset 84
+
+/* Register rw_ack_intr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
+#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
+#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
+#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
+#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
+#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
+#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
+#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
+#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
+#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
+#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_rw_ack_intr_offset 88
+
+/* Register r_intr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_intr___data_md___lsb 0
+#define reg_iop_dmc_out_r_intr___data_md___width 1
+#define reg_iop_dmc_out_r_intr___data_md___bit 0
+#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_r_intr___group_md___lsb 2
+#define reg_iop_dmc_out_r_intr___group_md___width 1
+#define reg_iop_dmc_out_r_intr___group_md___bit 2
+#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_r_intr___dth___lsb 4
+#define reg_iop_dmc_out_r_intr___dth___width 1
+#define reg_iop_dmc_out_r_intr___dth___bit 4
+#define reg_iop_dmc_out_r_intr___dv___lsb 5
+#define reg_iop_dmc_out_r_intr___dv___width 1
+#define reg_iop_dmc_out_r_intr___dv___bit 5
+#define reg_iop_dmc_out_r_intr___last_data___lsb 6
+#define reg_iop_dmc_out_r_intr___last_data___width 1
+#define reg_iop_dmc_out_r_intr___last_data___bit 6
+#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_r_intr___trf_lim___width 1
+#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_r_intr_offset 92
+
+/* Register r_masked_intr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
+#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
+#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
+#define reg_iop_dmc_out_r_masked_intr___dth___width 1
+#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
+#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
+#define reg_iop_dmc_out_r_masked_intr___dv___width 1
+#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
+#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
+#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
+#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_r_masked_intr_offset 96
+
+
+/* Constants */
+#define regk_iop_dmc_out_ack_pkt                  0x00000100
+#define regk_iop_dmc_out_array                    0x00000008
+#define regk_iop_dmc_out_burst                    0x00000020
+#define regk_iop_dmc_out_copy_next                0x00000010
+#define regk_iop_dmc_out_copy_up                  0x00000020
+#define regk_iop_dmc_out_dis_c                    0x00000010
+#define regk_iop_dmc_out_dis_g                    0x00000020
+#define regk_iop_dmc_out_lim1                     0x00000000
+#define regk_iop_dmc_out_lim16                    0x00000004
+#define regk_iop_dmc_out_lim2                     0x00000001
+#define regk_iop_dmc_out_lim32                    0x00000005
+#define regk_iop_dmc_out_lim4                     0x00000002
+#define regk_iop_dmc_out_lim64                    0x00000006
+#define regk_iop_dmc_out_lim8                     0x00000003
+#define regk_iop_dmc_out_load_c                   0x00000200
+#define regk_iop_dmc_out_load_c_n                 0x00000280
+#define regk_iop_dmc_out_load_c_next              0x00000240
+#define regk_iop_dmc_out_load_d                   0x00000140
+#define regk_iop_dmc_out_load_g                   0x00000300
+#define regk_iop_dmc_out_load_g_down              0x000003c0
+#define regk_iop_dmc_out_load_g_next              0x00000340
+#define regk_iop_dmc_out_load_g_up                0x00000380
+#define regk_iop_dmc_out_next_en                  0x00000010
+#define regk_iop_dmc_out_next_pkt                 0x00000010
+#define regk_iop_dmc_out_no                       0x00000000
+#define regk_iop_dmc_out_restore                  0x00000020
+#define regk_iop_dmc_out_rw_cfg_default           0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_default    0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_md1_default  0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_md2_default  0x00000000
+#define regk_iop_dmc_out_rw_data_descr_default    0x00000000
+#define regk_iop_dmc_out_rw_group_descr_default   0x00000000
+#define regk_iop_dmc_out_rw_intr_mask_default     0x00000000
+#define regk_iop_dmc_out_save_down                0x00000020
+#define regk_iop_dmc_out_save_up                  0x00000020
+#define regk_iop_dmc_out_set_reg                  0x00000050
+#define regk_iop_dmc_out_set_w_size1              0x00000190
+#define regk_iop_dmc_out_set_w_size2              0x000001a0
+#define regk_iop_dmc_out_set_w_size4              0x000001c0
+#define regk_iop_dmc_out_store_c                  0x00000002
+#define regk_iop_dmc_out_store_descr              0x00000000
+#define regk_iop_dmc_out_store_g                  0x00000004
+#define regk_iop_dmc_out_store_md                 0x00000001
+#define regk_iop_dmc_out_update_down              0x00000020
+#define regk_iop_dmc_out_yes                      0x00000001
+#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
new file mode 100644
index 000000000000..974dee082f9f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
@@ -0,0 +1,234 @@
+#ifndef __iop_fifo_in_defs_asm_h
+#define __iop_fifo_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:07 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
+ *      id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
+#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
+#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
+#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
+#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
+#define reg_iop_fifo_in_rw_cfg___trig___width 2
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
+#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
+#define reg_iop_fifo_in_rw_cfg___mode___width 2
+#define reg_iop_fifo_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
+#define reg_iop_fifo_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_in_r_stat___last___lsb 4
+#define reg_iop_fifo_in_r_stat___last___width 8
+#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_in_r_stat_offset 8
+
+/* Register rs_rd1byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd1byte___data___width 8
+#define reg_iop_fifo_in_rs_rd1byte_offset 12
+
+/* Register r_rd1byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd1byte___data___width 8
+#define reg_iop_fifo_in_r_rd1byte_offset 16
+
+/* Register rs_rd2byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd2byte___data___width 16
+#define reg_iop_fifo_in_rs_rd2byte_offset 20
+
+/* Register r_rd2byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd2byte___data___width 16
+#define reg_iop_fifo_in_r_rd2byte_offset 24
+
+/* Register rs_rd3byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd3byte___data___width 24
+#define reg_iop_fifo_in_rs_rd3byte_offset 28
+
+/* Register r_rd3byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd3byte___data___width 24
+#define reg_iop_fifo_in_r_rd3byte_offset 32
+
+/* Register rs_rd4byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd4byte___data___width 32
+#define reg_iop_fifo_in_rs_rd4byte_offset 36
+
+/* Register r_rd4byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd4byte___data___width 32
+#define reg_iop_fifo_in_r_rd4byte_offset 40
+
+/* Register rw_set_last, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_set_last_offset 44
+
+/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
+#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
+#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
+
+/* Register rw_intr_mask, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
+#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
+#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
+#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_in_rw_intr_mask_offset 52
+
+/* Register rw_ack_intr, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
+#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
+#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
+#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_in_rw_ack_intr_offset 56
+
+/* Register r_intr, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_intr___urun___lsb 0
+#define reg_iop_fifo_in_r_intr___urun___width 1
+#define reg_iop_fifo_in_r_intr___urun___bit 0
+#define reg_iop_fifo_in_r_intr___last_data___lsb 1
+#define reg_iop_fifo_in_r_intr___last_data___width 1
+#define reg_iop_fifo_in_r_intr___last_data___bit 1
+#define reg_iop_fifo_in_r_intr___dav___lsb 2
+#define reg_iop_fifo_in_r_intr___dav___width 1
+#define reg_iop_fifo_in_r_intr___dav___bit 2
+#define reg_iop_fifo_in_r_intr___avail___lsb 3
+#define reg_iop_fifo_in_r_intr___avail___width 1
+#define reg_iop_fifo_in_r_intr___avail___bit 3
+#define reg_iop_fifo_in_r_intr___orun___lsb 4
+#define reg_iop_fifo_in_r_intr___orun___width 1
+#define reg_iop_fifo_in_r_intr___orun___bit 4
+#define reg_iop_fifo_in_r_intr_offset 60
+
+/* Register r_masked_intr, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_in_r_masked_intr___urun___width 1
+#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_in_r_masked_intr___dav___width 1
+#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
+#define reg_iop_fifo_in_r_masked_intr___avail___width 1
+#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
+#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_in_r_masked_intr___orun___width 1
+#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_in_r_masked_intr_offset 64
+
+
+/* Constants */
+#define regk_iop_fifo_in_dif_in                   0x00000002
+#define regk_iop_fifo_in_hi                       0x00000000
+#define regk_iop_fifo_in_neg                      0x00000002
+#define regk_iop_fifo_in_no                       0x00000000
+#define regk_iop_fifo_in_order16                  0x00000001
+#define regk_iop_fifo_in_order24                  0x00000002
+#define regk_iop_fifo_in_order32                  0x00000003
+#define regk_iop_fifo_in_order8                   0x00000000
+#define regk_iop_fifo_in_pos                      0x00000001
+#define regk_iop_fifo_in_pos_neg                  0x00000003
+#define regk_iop_fifo_in_rw_cfg_default           0x00000024
+#define regk_iop_fifo_in_rw_ctrl_default          0x00000000
+#define regk_iop_fifo_in_rw_intr_mask_default     0x00000000
+#define regk_iop_fifo_in_rw_set_last_default      0x00000000
+#define regk_iop_fifo_in_rw_strb_dif_in_default   0x00000000
+#define regk_iop_fifo_in_size16                   0x00000002
+#define regk_iop_fifo_in_size24                   0x00000001
+#define regk_iop_fifo_in_size32                   0x00000000
+#define regk_iop_fifo_in_size8                    0x00000003
+#define regk_iop_fifo_in_yes                      0x00000001
+#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
new file mode 100644
index 000000000000..e00fab0c9335
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
@@ -0,0 +1,155 @@
+#ifndef __iop_fifo_in_extra_defs_asm_h
+#define __iop_fifo_in_extra_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:08 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *      id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
+
+/* Register r_stat, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
+#define reg_iop_fifo_in_extra_r_stat___last___width 8
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_in_extra_r_stat_offset 4
+
+/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
+#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
+#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
+
+/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
+
+/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
+
+/* Register r_intr, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_r_intr___urun___width 1
+#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_r_intr___dav___width 1
+#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_r_intr___avail___width 1
+#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_r_intr___orun___width 1
+#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_r_intr_offset 20
+
+/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
+
+
+/* Constants */
+#define regk_iop_fifo_in_extra_fifo_in            0x00000002
+#define regk_iop_fifo_in_extra_no                 0x00000000
+#define regk_iop_fifo_in_extra_rw_intr_mask_default  0x00000000
+#define regk_iop_fifo_in_extra_yes                0x00000001
+#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
new file mode 100644
index 000000000000..9ec5f4a826df
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
@@ -0,0 +1,254 @@
+#ifndef __iop_fifo_out_defs_asm_h
+#define __iop_fifo_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:09 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
+ *      id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
+#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
+#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
+#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
+#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
+#define reg_iop_fifo_out_rw_cfg___trig___width 2
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
+#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
+#define reg_iop_fifo_out_rw_cfg___mode___width 2
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
+#define reg_iop_fifo_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
+#define reg_iop_fifo_out_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_out_r_stat___last___lsb 4
+#define reg_iop_fifo_out_r_stat___last___width 8
+#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
+#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
+#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
+#define reg_iop_fifo_out_r_stat_offset 8
+
+/* Register rw_wr1byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr1byte___data___width 8
+#define reg_iop_fifo_out_rw_wr1byte_offset 12
+
+/* Register rw_wr2byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr2byte___data___width 16
+#define reg_iop_fifo_out_rw_wr2byte_offset 16
+
+/* Register rw_wr3byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr3byte___data___width 24
+#define reg_iop_fifo_out_rw_wr3byte_offset 20
+
+/* Register rw_wr4byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr4byte___data___width 32
+#define reg_iop_fifo_out_rw_wr4byte_offset 24
+
+/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
+#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
+
+/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
+#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
+
+/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
+#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
+
+/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
+#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
+
+/* Register rw_set_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_set_last_offset 44
+
+/* Register rs_rd_data, scope iop_fifo_out, type rs */
+#define reg_iop_fifo_out_rs_rd_data_offset 48
+
+/* Register r_rd_data, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_rd_data_offset 52
+
+/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
+
+/* Register rw_intr_mask, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
+#define reg_iop_fifo_out_rw_intr_mask___free___width 1
+#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
+#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_out_rw_intr_mask_offset 60
+
+/* Register rw_ack_intr, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
+#define reg_iop_fifo_out_rw_ack_intr___free___width 1
+#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
+#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_out_rw_ack_intr_offset 64
+
+/* Register r_intr, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_intr___urun___lsb 0
+#define reg_iop_fifo_out_r_intr___urun___width 1
+#define reg_iop_fifo_out_r_intr___urun___bit 0
+#define reg_iop_fifo_out_r_intr___last_data___lsb 1
+#define reg_iop_fifo_out_r_intr___last_data___width 1
+#define reg_iop_fifo_out_r_intr___last_data___bit 1
+#define reg_iop_fifo_out_r_intr___dav___lsb 2
+#define reg_iop_fifo_out_r_intr___dav___width 1
+#define reg_iop_fifo_out_r_intr___dav___bit 2
+#define reg_iop_fifo_out_r_intr___free___lsb 3
+#define reg_iop_fifo_out_r_intr___free___width 1
+#define reg_iop_fifo_out_r_intr___free___bit 3
+#define reg_iop_fifo_out_r_intr___orun___lsb 4
+#define reg_iop_fifo_out_r_intr___orun___width 1
+#define reg_iop_fifo_out_r_intr___orun___bit 4
+#define reg_iop_fifo_out_r_intr_offset 68
+
+/* Register r_masked_intr, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_out_r_masked_intr___urun___width 1
+#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_out_r_masked_intr___dav___width 1
+#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
+#define reg_iop_fifo_out_r_masked_intr___free___width 1
+#define reg_iop_fifo_out_r_masked_intr___free___bit 3
+#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_out_r_masked_intr___orun___width 1
+#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_out_r_masked_intr_offset 72
+
+
+/* Constants */
+#define regk_iop_fifo_out_hi                      0x00000000
+#define regk_iop_fifo_out_neg                     0x00000002
+#define regk_iop_fifo_out_no                      0x00000000
+#define regk_iop_fifo_out_order16                 0x00000001
+#define regk_iop_fifo_out_order24                 0x00000002
+#define regk_iop_fifo_out_order32                 0x00000003
+#define regk_iop_fifo_out_order8                  0x00000000
+#define regk_iop_fifo_out_pos                     0x00000001
+#define regk_iop_fifo_out_pos_neg                 0x00000003
+#define regk_iop_fifo_out_rw_cfg_default          0x00000024
+#define regk_iop_fifo_out_rw_ctrl_default         0x00000000
+#define regk_iop_fifo_out_rw_intr_mask_default    0x00000000
+#define regk_iop_fifo_out_rw_set_last_default     0x00000000
+#define regk_iop_fifo_out_rw_strb_dif_out_default  0x00000000
+#define regk_iop_fifo_out_rw_wr1byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr1byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr2byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr2byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr3byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr3byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr4byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr4byte_last_default  0x00000000
+#define regk_iop_fifo_out_size16                  0x00000002
+#define regk_iop_fifo_out_size24                  0x00000001
+#define regk_iop_fifo_out_size32                  0x00000000
+#define regk_iop_fifo_out_size8                   0x00000003
+#define regk_iop_fifo_out_yes                     0x00000001
+#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
new file mode 100644
index 000000000000..0f84a50cf77c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
@@ -0,0 +1,158 @@
+#ifndef __iop_fifo_out_extra_defs_asm_h
+#define __iop_fifo_out_extra_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:10 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *      id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
+#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
+
+/* Register r_rd_data, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_rd_data_offset 4
+
+/* Register r_stat, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
+#define reg_iop_fifo_out_extra_r_stat___last___width 8
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
+#define reg_iop_fifo_out_extra_r_stat_offset 8
+
+/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
+
+/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
+
+/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
+
+/* Register r_intr, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_r_intr___urun___width 1
+#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_r_intr___dav___width 1
+#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_r_intr___free___width 1
+#define reg_iop_fifo_out_extra_r_intr___free___bit 3
+#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_r_intr___orun___width 1
+#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_r_intr_offset 24
+
+/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
+
+
+/* Constants */
+#define regk_iop_fifo_out_extra_no                0x00000000
+#define regk_iop_fifo_out_extra_rw_intr_mask_default  0x00000000
+#define regk_iop_fifo_out_extra_yes               0x00000001
+#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
new file mode 100644
index 000000000000..80490c82cc29
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
@@ -0,0 +1,177 @@
+#ifndef __iop_mpu_defs_asm_h
+#define __iop_mpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_mpu.r
+ *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
+ *      id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_mpu_rw_r 4
+/* Register rw_r, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_r_offset 0
+
+/* Register rw_ctrl, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_ctrl___en___lsb 0
+#define reg_iop_mpu_rw_ctrl___en___width 1
+#define reg_iop_mpu_rw_ctrl___en___bit 0
+#define reg_iop_mpu_rw_ctrl_offset 128
+
+/* Register r_pc, scope iop_mpu, type r */
+#define reg_iop_mpu_r_pc___addr___lsb 0
+#define reg_iop_mpu_r_pc___addr___width 12
+#define reg_iop_mpu_r_pc_offset 132
+
+/* Register r_stat, scope iop_mpu, type r */
+#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
+#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
+#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
+#define reg_iop_mpu_r_stat___intr_busy___lsb 1
+#define reg_iop_mpu_r_stat___intr_busy___width 1
+#define reg_iop_mpu_r_stat___intr_busy___bit 1
+#define reg_iop_mpu_r_stat___intr_vect___lsb 2
+#define reg_iop_mpu_r_stat___intr_vect___width 16
+#define reg_iop_mpu_r_stat_offset 136
+
+/* Register rw_instr, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_instr_offset 140
+
+/* Register rw_immediate, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_immediate_offset 144
+
+/* Register r_trace, scope iop_mpu, type r */
+#define reg_iop_mpu_r_trace___intr_vect___lsb 0
+#define reg_iop_mpu_r_trace___intr_vect___width 16
+#define reg_iop_mpu_r_trace___pc___lsb 16
+#define reg_iop_mpu_r_trace___pc___width 12
+#define reg_iop_mpu_r_trace___en___lsb 28
+#define reg_iop_mpu_r_trace___en___width 1
+#define reg_iop_mpu_r_trace___en___bit 28
+#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
+#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
+#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
+#define reg_iop_mpu_r_trace___intr_busy___lsb 30
+#define reg_iop_mpu_r_trace___intr_busy___width 1
+#define reg_iop_mpu_r_trace___intr_busy___bit 30
+#define reg_iop_mpu_r_trace_offset 148
+
+/* Register r_wr_stat, scope iop_mpu, type r */
+#define reg_iop_mpu_r_wr_stat___r0___lsb 0
+#define reg_iop_mpu_r_wr_stat___r0___width 1
+#define reg_iop_mpu_r_wr_stat___r0___bit 0
+#define reg_iop_mpu_r_wr_stat___r1___lsb 1
+#define reg_iop_mpu_r_wr_stat___r1___width 1
+#define reg_iop_mpu_r_wr_stat___r1___bit 1
+#define reg_iop_mpu_r_wr_stat___r2___lsb 2
+#define reg_iop_mpu_r_wr_stat___r2___width 1
+#define reg_iop_mpu_r_wr_stat___r2___bit 2
+#define reg_iop_mpu_r_wr_stat___r3___lsb 3
+#define reg_iop_mpu_r_wr_stat___r3___width 1
+#define reg_iop_mpu_r_wr_stat___r3___bit 3
+#define reg_iop_mpu_r_wr_stat___r4___lsb 4
+#define reg_iop_mpu_r_wr_stat___r4___width 1
+#define reg_iop_mpu_r_wr_stat___r4___bit 4
+#define reg_iop_mpu_r_wr_stat___r5___lsb 5
+#define reg_iop_mpu_r_wr_stat___r5___width 1
+#define reg_iop_mpu_r_wr_stat___r5___bit 5
+#define reg_iop_mpu_r_wr_stat___r6___lsb 6
+#define reg_iop_mpu_r_wr_stat___r6___width 1
+#define reg_iop_mpu_r_wr_stat___r6___bit 6
+#define reg_iop_mpu_r_wr_stat___r7___lsb 7
+#define reg_iop_mpu_r_wr_stat___r7___width 1
+#define reg_iop_mpu_r_wr_stat___r7___bit 7
+#define reg_iop_mpu_r_wr_stat___r8___lsb 8
+#define reg_iop_mpu_r_wr_stat___r8___width 1
+#define reg_iop_mpu_r_wr_stat___r8___bit 8
+#define reg_iop_mpu_r_wr_stat___r9___lsb 9
+#define reg_iop_mpu_r_wr_stat___r9___width 1
+#define reg_iop_mpu_r_wr_stat___r9___bit 9
+#define reg_iop_mpu_r_wr_stat___r10___lsb 10
+#define reg_iop_mpu_r_wr_stat___r10___width 1
+#define reg_iop_mpu_r_wr_stat___r10___bit 10
+#define reg_iop_mpu_r_wr_stat___r11___lsb 11
+#define reg_iop_mpu_r_wr_stat___r11___width 1
+#define reg_iop_mpu_r_wr_stat___r11___bit 11
+#define reg_iop_mpu_r_wr_stat___r12___lsb 12
+#define reg_iop_mpu_r_wr_stat___r12___width 1
+#define reg_iop_mpu_r_wr_stat___r12___bit 12
+#define reg_iop_mpu_r_wr_stat___r13___lsb 13
+#define reg_iop_mpu_r_wr_stat___r13___width 1
+#define reg_iop_mpu_r_wr_stat___r13___bit 13
+#define reg_iop_mpu_r_wr_stat___r14___lsb 14
+#define reg_iop_mpu_r_wr_stat___r14___width 1
+#define reg_iop_mpu_r_wr_stat___r14___bit 14
+#define reg_iop_mpu_r_wr_stat___r15___lsb 15
+#define reg_iop_mpu_r_wr_stat___r15___width 1
+#define reg_iop_mpu_r_wr_stat___r15___bit 15
+#define reg_iop_mpu_r_wr_stat_offset 152
+
+#define STRIDE_iop_mpu_rw_thread 4
+/* Register rw_thread, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_thread___addr___lsb 0
+#define reg_iop_mpu_rw_thread___addr___width 12
+#define reg_iop_mpu_rw_thread_offset 156
+
+#define STRIDE_iop_mpu_rw_intr 4
+/* Register rw_intr, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_intr___addr___lsb 0
+#define reg_iop_mpu_rw_intr___addr___width 12
+#define reg_iop_mpu_rw_intr_offset 196
+
+
+/* Constants */
+#define regk_iop_mpu_no                           0x00000000
+#define regk_iop_mpu_r_pc_default                 0x00000000
+#define regk_iop_mpu_rw_ctrl_default              0x00000000
+#define regk_iop_mpu_rw_intr_size                 0x00000010
+#define regk_iop_mpu_rw_r_size                    0x00000010
+#define regk_iop_mpu_rw_thread_default            0x00000000
+#define regk_iop_mpu_rw_thread_size               0x00000004
+#define regk_iop_mpu_yes                          0x00000001
+#endif /* __iop_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
new file mode 100644
index 000000000000..a20b8857b4d0
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
@@ -0,0 +1,44 @@
+/* Autogenerated Changes here will be lost!
+ * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
+ */
+#define iop_version 0
+#define iop_fifo_in0_extra 64
+#define iop_fifo_in1_extra 128
+#define iop_fifo_out0_extra 192
+#define iop_fifo_out1_extra 256
+#define iop_trigger_grp0 320
+#define iop_trigger_grp1 384
+#define iop_trigger_grp2 448
+#define iop_trigger_grp3 512
+#define iop_trigger_grp4 576
+#define iop_trigger_grp5 640
+#define iop_trigger_grp6 704
+#define iop_trigger_grp7 768
+#define iop_crc_par0 896
+#define iop_crc_par1 1024
+#define iop_dmc_in0 1152
+#define iop_dmc_in1 1280
+#define iop_dmc_out0 1408
+#define iop_dmc_out1 1536
+#define iop_fifo_in0 1664
+#define iop_fifo_in1 1792
+#define iop_fifo_out0 1920
+#define iop_fifo_out1 2048
+#define iop_scrc_in0 2176
+#define iop_scrc_in1 2304
+#define iop_scrc_out0 2432
+#define iop_scrc_out1 2560
+#define iop_timer_grp0 2688
+#define iop_timer_grp1 2816
+#define iop_timer_grp2 2944
+#define iop_timer_grp3 3072
+#define iop_sap_in 3328
+#define iop_sap_out 3584
+#define iop_spu0 3840
+#define iop_spu1 4096
+#define iop_sw_cfg 4352
+#define iop_sw_cpu 4608
+#define iop_sw_mpu 4864
+#define iop_sw_spu0 5120
+#define iop_sw_spu1 5376
+#define iop_mpu 5632
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
new file mode 100644
index 000000000000..a4a10ff300b3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
@@ -0,0 +1,182 @@
+#ifndef __iop_sap_in_defs_asm_h
+#define __iop_sap_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
+ *      id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_bus0_sync, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
+#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
+#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
+#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
+#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
+#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
+#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
+#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
+#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
+#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
+#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
+#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
+#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
+#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
+#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
+#define reg_iop_sap_in_rw_bus0_sync_offset 0
+
+/* Register rw_bus1_sync, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
+#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
+#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
+#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
+#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
+#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
+#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
+#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
+#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
+#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
+#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
+#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
+#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
+#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
+#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
+#define reg_iop_sap_in_rw_bus1_sync_offset 4
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_gio___sync_sel___width 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_gio___sync_edge___width 2
+#define reg_iop_sap_in_rw_gio___delay___lsb 7
+#define reg_iop_sap_in_rw_gio___delay___width 1
+#define reg_iop_sap_in_rw_gio___delay___bit 7
+#define reg_iop_sap_in_rw_gio___logic___lsb 8
+#define reg_iop_sap_in_rw_gio___logic___width 2
+#define reg_iop_sap_in_rw_gio_offset 8
+
+
+/* Constants */
+#define regk_iop_sap_in_and                       0x00000002
+#define regk_iop_sap_in_ext_clk200                0x00000003
+#define regk_iop_sap_in_gio1                      0x00000000
+#define regk_iop_sap_in_gio13                     0x00000005
+#define regk_iop_sap_in_gio18                     0x00000003
+#define regk_iop_sap_in_gio19                     0x00000004
+#define regk_iop_sap_in_gio21                     0x00000006
+#define regk_iop_sap_in_gio23                     0x00000005
+#define regk_iop_sap_in_gio29                     0x00000007
+#define regk_iop_sap_in_gio5                      0x00000004
+#define regk_iop_sap_in_gio6                      0x00000001
+#define regk_iop_sap_in_gio7                      0x00000002
+#define regk_iop_sap_in_inv                       0x00000001
+#define regk_iop_sap_in_neg                       0x00000002
+#define regk_iop_sap_in_no                        0x00000000
+#define regk_iop_sap_in_no_del_ext_clk200         0x00000001
+#define regk_iop_sap_in_none                      0x00000000
+#define regk_iop_sap_in_or                        0x00000003
+#define regk_iop_sap_in_pos                       0x00000001
+#define regk_iop_sap_in_pos_neg                   0x00000003
+#define regk_iop_sap_in_rw_bus0_sync_default      0x02020202
+#define regk_iop_sap_in_rw_bus1_sync_default      0x02020202
+#define regk_iop_sap_in_rw_gio_default            0x00000002
+#define regk_iop_sap_in_rw_gio_size               0x00000020
+#define regk_iop_sap_in_timer_grp0_tmr3           0x00000006
+#define regk_iop_sap_in_timer_grp1_tmr3           0x00000004
+#define regk_iop_sap_in_timer_grp2_tmr3           0x00000005
+#define regk_iop_sap_in_timer_grp3_tmr3           0x00000007
+#define regk_iop_sap_in_tmr_clk200                0x00000000
+#define regk_iop_sap_in_two_clk200                0x00000002
+#define regk_iop_sap_in_yes                       0x00000001
+#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
new file mode 100644
index 000000000000..0ec727f92a25
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
@@ -0,0 +1,346 @@
+#ifndef __iop_sap_out_defs_asm_h
+#define __iop_sap_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
+ *      id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
+#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
+#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
+#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
+#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
+#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
+#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated_offset 0
+
+/* Register rw_bus0, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
+#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
+#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
+#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
+#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
+#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
+#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
+#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
+#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
+#define reg_iop_sap_out_rw_bus0_offset 4
+
+/* Register rw_bus1, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
+#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
+#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
+#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
+#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
+#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
+#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
+#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
+#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
+#define reg_iop_sap_out_rw_bus1_offset 8
+
+/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
+
+/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
+
+/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
+
+/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
+#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
+#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
+#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
+#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
+#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
+#define reg_iop_sap_out_rw_gio___out_logic___width 1
+#define reg_iop_sap_out_rw_gio___out_logic___bit 10
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
+#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
+#define reg_iop_sap_out_rw_gio___oe_logic___width 2
+#define reg_iop_sap_out_rw_gio_offset 28
+
+
+/* Constants */
+#define regk_iop_sap_out_and                      0x00000002
+#define regk_iop_sap_out_clk0                     0x00000000
+#define regk_iop_sap_out_clk1                     0x00000001
+#define regk_iop_sap_out_clk12                    0x00000002
+#define regk_iop_sap_out_clk2                     0x00000002
+#define regk_iop_sap_out_clk200                   0x00000001
+#define regk_iop_sap_out_clk3                     0x00000003
+#define regk_iop_sap_out_ext                      0x00000003
+#define regk_iop_sap_out_gated                    0x00000004
+#define regk_iop_sap_out_gio1                     0x00000000
+#define regk_iop_sap_out_gio13                    0x00000002
+#define regk_iop_sap_out_gio13_clk                0x0000000c
+#define regk_iop_sap_out_gio15                    0x00000001
+#define regk_iop_sap_out_gio18                    0x00000003
+#define regk_iop_sap_out_gio18_clk                0x0000000d
+#define regk_iop_sap_out_gio1_clk                 0x00000008
+#define regk_iop_sap_out_gio21_clk                0x0000000e
+#define regk_iop_sap_out_gio23                    0x00000002
+#define regk_iop_sap_out_gio29_clk                0x0000000f
+#define regk_iop_sap_out_gio31                    0x00000003
+#define regk_iop_sap_out_gio5                     0x00000001
+#define regk_iop_sap_out_gio5_clk                 0x00000009
+#define regk_iop_sap_out_gio6_clk                 0x0000000a
+#define regk_iop_sap_out_gio7                     0x00000000
+#define regk_iop_sap_out_gio7_clk                 0x0000000b
+#define regk_iop_sap_out_gio_in13                 0x00000001
+#define regk_iop_sap_out_gio_in21                 0x00000002
+#define regk_iop_sap_out_gio_in29                 0x00000003
+#define regk_iop_sap_out_gio_in5                  0x00000000
+#define regk_iop_sap_out_inv                      0x00000001
+#define regk_iop_sap_out_nand                     0x00000003
+#define regk_iop_sap_out_no                       0x00000000
+#define regk_iop_sap_out_none                     0x00000000
+#define regk_iop_sap_out_rw_bus0_default          0x00000000
+#define regk_iop_sap_out_rw_bus0_hi_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus0_lo_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus1_default          0x00000000
+#define regk_iop_sap_out_rw_bus1_hi_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus1_lo_oe_default    0x00000000
+#define regk_iop_sap_out_rw_gen_gated_default     0x00000000
+#define regk_iop_sap_out_rw_gio_default           0x00000000
+#define regk_iop_sap_out_rw_gio_size              0x00000020
+#define regk_iop_sap_out_spu0_gio0                0x00000002
+#define regk_iop_sap_out_spu0_gio1                0x00000003
+#define regk_iop_sap_out_spu0_gio12               0x00000004
+#define regk_iop_sap_out_spu0_gio13               0x00000004
+#define regk_iop_sap_out_spu0_gio14               0x00000004
+#define regk_iop_sap_out_spu0_gio15               0x00000004
+#define regk_iop_sap_out_spu0_gio2                0x00000002
+#define regk_iop_sap_out_spu0_gio3                0x00000003
+#define regk_iop_sap_out_spu0_gio4                0x00000002
+#define regk_iop_sap_out_spu0_gio5                0x00000003
+#define regk_iop_sap_out_spu0_gio6                0x00000002
+#define regk_iop_sap_out_spu0_gio7                0x00000003
+#define regk_iop_sap_out_spu1_gio0                0x00000005
+#define regk_iop_sap_out_spu1_gio1                0x00000006
+#define regk_iop_sap_out_spu1_gio12               0x00000007
+#define regk_iop_sap_out_spu1_gio13               0x00000007
+#define regk_iop_sap_out_spu1_gio14               0x00000007
+#define regk_iop_sap_out_spu1_gio15               0x00000007
+#define regk_iop_sap_out_spu1_gio2                0x00000005
+#define regk_iop_sap_out_spu1_gio3                0x00000006
+#define regk_iop_sap_out_spu1_gio4                0x00000005
+#define regk_iop_sap_out_spu1_gio5                0x00000006
+#define regk_iop_sap_out_spu1_gio6                0x00000005
+#define regk_iop_sap_out_spu1_gio7                0x00000006
+#define regk_iop_sap_out_timer_grp0_tmr2          0x00000004
+#define regk_iop_sap_out_timer_grp1_tmr2          0x00000005
+#define regk_iop_sap_out_timer_grp2_tmr2          0x00000006
+#define regk_iop_sap_out_timer_grp3_tmr2          0x00000007
+#define regk_iop_sap_out_tmr                      0x00000005
+#define regk_iop_sap_out_yes                      0x00000001
+#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
new file mode 100644
index 000000000000..2cf5721597fc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
@@ -0,0 +1,111 @@
+#ifndef __iop_scrc_in_defs_asm_h
+#define __iop_scrc_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
+ *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
+ *      id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
+#define reg_iop_scrc_in_rw_cfg___trig___width 2
+#define reg_iop_scrc_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_scrc_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_scrc_in, type r */
+#define reg_iop_scrc_in_r_stat___err___lsb 0
+#define reg_iop_scrc_in_r_stat___err___width 1
+#define reg_iop_scrc_in_r_stat___err___bit 0
+#define reg_iop_scrc_in_r_stat_offset 8
+
+/* Register rw_init_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_init_crc_offset 12
+
+/* Register rs_computed_crc, scope iop_scrc_in, type rs */
+#define reg_iop_scrc_in_rs_computed_crc_offset 16
+
+/* Register r_computed_crc, scope iop_scrc_in, type r */
+#define reg_iop_scrc_in_r_computed_crc_offset 20
+
+/* Register rw_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_crc_offset 24
+
+/* Register rw_correct_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_correct_crc_offset 28
+
+/* Register rw_wr1bit, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
+#define reg_iop_scrc_in_rw_wr1bit___data___width 2
+#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
+#define reg_iop_scrc_in_rw_wr1bit___last___width 2
+#define reg_iop_scrc_in_rw_wr1bit_offset 32
+
+
+/* Constants */
+#define regk_iop_scrc_in_dif_in                   0x00000002
+#define regk_iop_scrc_in_hi                       0x00000000
+#define regk_iop_scrc_in_neg                      0x00000002
+#define regk_iop_scrc_in_no                       0x00000000
+#define regk_iop_scrc_in_pos                      0x00000001
+#define regk_iop_scrc_in_pos_neg                  0x00000003
+#define regk_iop_scrc_in_r_computed_crc_default   0x00000000
+#define regk_iop_scrc_in_rs_computed_crc_default  0x00000000
+#define regk_iop_scrc_in_rw_cfg_default           0x00000000
+#define regk_iop_scrc_in_rw_ctrl_default          0x00000000
+#define regk_iop_scrc_in_rw_init_crc_default      0x00000000
+#define regk_iop_scrc_in_set0                     0x00000000
+#define regk_iop_scrc_in_set1                     0x00000001
+#define regk_iop_scrc_in_yes                      0x00000001
+#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
new file mode 100644
index 000000000000..640a25725f20
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
@@ -0,0 +1,105 @@
+#ifndef __iop_scrc_out_defs_asm_h
+#define __iop_scrc_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
+ *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
+ *      id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
+#define reg_iop_scrc_out_rw_cfg___trig___width 2
+#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
+#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
+#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
+#define reg_iop_scrc_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
+#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
+#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
+#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
+#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
+#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
+#define reg_iop_scrc_out_rw_ctrl_offset 4
+
+/* Register rw_init_crc, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_init_crc_offset 8
+
+/* Register rw_crc, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_crc_offset 12
+
+/* Register rw_data, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_data___val___lsb 0
+#define reg_iop_scrc_out_rw_data___val___width 1
+#define reg_iop_scrc_out_rw_data___val___bit 0
+#define reg_iop_scrc_out_rw_data_offset 16
+
+/* Register r_computed_crc, scope iop_scrc_out, type r */
+#define reg_iop_scrc_out_r_computed_crc_offset 20
+
+
+/* Constants */
+#define regk_iop_scrc_out_crc                     0x00000001
+#define regk_iop_scrc_out_data                    0x00000000
+#define regk_iop_scrc_out_dif                     0x00000001
+#define regk_iop_scrc_out_hi                      0x00000000
+#define regk_iop_scrc_out_neg                     0x00000002
+#define regk_iop_scrc_out_no                      0x00000000
+#define regk_iop_scrc_out_pos                     0x00000001
+#define regk_iop_scrc_out_pos_neg                 0x00000003
+#define regk_iop_scrc_out_reg                     0x00000000
+#define regk_iop_scrc_out_rw_cfg_default          0x00000000
+#define regk_iop_scrc_out_rw_crc_default          0x00000000
+#define regk_iop_scrc_out_rw_ctrl_default         0x00000000
+#define regk_iop_scrc_out_rw_data_default         0x00000000
+#define regk_iop_scrc_out_rw_init_crc_default     0x00000000
+#define regk_iop_scrc_out_yes                     0x00000001
+#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
new file mode 100644
index 000000000000..bb402c1aa761
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
@@ -0,0 +1,573 @@
+#ifndef __iop_spu_defs_asm_h
+#define __iop_spu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
+ *      id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_spu_rw_r 4
+/* Register rw_r, scope iop_spu, type rw */
+#define reg_iop_spu_rw_r_offset 0
+
+/* Register rw_seq_pc, scope iop_spu, type rw */
+#define reg_iop_spu_rw_seq_pc___addr___lsb 0
+#define reg_iop_spu_rw_seq_pc___addr___width 12
+#define reg_iop_spu_rw_seq_pc_offset 64
+
+/* Register rw_fsm_pc, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
+#define reg_iop_spu_rw_fsm_pc___addr___width 12
+#define reg_iop_spu_rw_fsm_pc_offset 68
+
+/* Register rw_ctrl, scope iop_spu, type rw */
+#define reg_iop_spu_rw_ctrl___fsm___lsb 0
+#define reg_iop_spu_rw_ctrl___fsm___width 1
+#define reg_iop_spu_rw_ctrl___fsm___bit 0
+#define reg_iop_spu_rw_ctrl___en___lsb 1
+#define reg_iop_spu_rw_ctrl___en___width 1
+#define reg_iop_spu_rw_ctrl___en___bit 1
+#define reg_iop_spu_rw_ctrl_offset 72
+
+/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
+#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
+#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
+#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
+#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
+#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
+#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
+#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
+
+/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
+#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
+#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
+#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
+#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
+#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
+#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
+#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
+
+/* Register rw_gio_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_offset 84
+
+/* Register rw_bus0_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_bus0_out_offset 88
+
+/* Register rw_bus1_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_bus1_out_offset 92
+
+/* Register r_gio_in, scope iop_spu, type r */
+#define reg_iop_spu_r_gio_in_offset 96
+
+/* Register r_bus0_in, scope iop_spu, type r */
+#define reg_iop_spu_r_bus0_in_offset 100
+
+/* Register r_bus1_in, scope iop_spu, type r */
+#define reg_iop_spu_r_bus1_in_offset 104
+
+/* Register rw_gio_out_set, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_set_offset 108
+
+/* Register rw_gio_out_clr, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_clr_offset 112
+
+/* Register rs_wr_stat, scope iop_spu, type rs */
+#define reg_iop_spu_rs_wr_stat___r0___lsb 0
+#define reg_iop_spu_rs_wr_stat___r0___width 1
+#define reg_iop_spu_rs_wr_stat___r0___bit 0
+#define reg_iop_spu_rs_wr_stat___r1___lsb 1
+#define reg_iop_spu_rs_wr_stat___r1___width 1
+#define reg_iop_spu_rs_wr_stat___r1___bit 1
+#define reg_iop_spu_rs_wr_stat___r2___lsb 2
+#define reg_iop_spu_rs_wr_stat___r2___width 1
+#define reg_iop_spu_rs_wr_stat___r2___bit 2
+#define reg_iop_spu_rs_wr_stat___r3___lsb 3
+#define reg_iop_spu_rs_wr_stat___r3___width 1
+#define reg_iop_spu_rs_wr_stat___r3___bit 3
+#define reg_iop_spu_rs_wr_stat___r4___lsb 4
+#define reg_iop_spu_rs_wr_stat___r4___width 1
+#define reg_iop_spu_rs_wr_stat___r4___bit 4
+#define reg_iop_spu_rs_wr_stat___r5___lsb 5
+#define reg_iop_spu_rs_wr_stat___r5___width 1
+#define reg_iop_spu_rs_wr_stat___r5___bit 5
+#define reg_iop_spu_rs_wr_stat___r6___lsb 6
+#define reg_iop_spu_rs_wr_stat___r6___width 1
+#define reg_iop_spu_rs_wr_stat___r6___bit 6
+#define reg_iop_spu_rs_wr_stat___r7___lsb 7
+#define reg_iop_spu_rs_wr_stat___r7___width 1
+#define reg_iop_spu_rs_wr_stat___r7___bit 7
+#define reg_iop_spu_rs_wr_stat___r8___lsb 8
+#define reg_iop_spu_rs_wr_stat___r8___width 1
+#define reg_iop_spu_rs_wr_stat___r8___bit 8
+#define reg_iop_spu_rs_wr_stat___r9___lsb 9
+#define reg_iop_spu_rs_wr_stat___r9___width 1
+#define reg_iop_spu_rs_wr_stat___r9___bit 9
+#define reg_iop_spu_rs_wr_stat___r10___lsb 10
+#define reg_iop_spu_rs_wr_stat___r10___width 1
+#define reg_iop_spu_rs_wr_stat___r10___bit 10
+#define reg_iop_spu_rs_wr_stat___r11___lsb 11
+#define reg_iop_spu_rs_wr_stat___r11___width 1
+#define reg_iop_spu_rs_wr_stat___r11___bit 11
+#define reg_iop_spu_rs_wr_stat___r12___lsb 12
+#define reg_iop_spu_rs_wr_stat___r12___width 1
+#define reg_iop_spu_rs_wr_stat___r12___bit 12
+#define reg_iop_spu_rs_wr_stat___r13___lsb 13
+#define reg_iop_spu_rs_wr_stat___r13___width 1
+#define reg_iop_spu_rs_wr_stat___r13___bit 13
+#define reg_iop_spu_rs_wr_stat___r14___lsb 14
+#define reg_iop_spu_rs_wr_stat___r14___width 1
+#define reg_iop_spu_rs_wr_stat___r14___bit 14
+#define reg_iop_spu_rs_wr_stat___r15___lsb 15
+#define reg_iop_spu_rs_wr_stat___r15___width 1
+#define reg_iop_spu_rs_wr_stat___r15___bit 15
+#define reg_iop_spu_rs_wr_stat_offset 116
+
+/* Register r_wr_stat, scope iop_spu, type r */
+#define reg_iop_spu_r_wr_stat___r0___lsb 0
+#define reg_iop_spu_r_wr_stat___r0___width 1
+#define reg_iop_spu_r_wr_stat___r0___bit 0
+#define reg_iop_spu_r_wr_stat___r1___lsb 1
+#define reg_iop_spu_r_wr_stat___r1___width 1
+#define reg_iop_spu_r_wr_stat___r1___bit 1
+#define reg_iop_spu_r_wr_stat___r2___lsb 2
+#define reg_iop_spu_r_wr_stat___r2___width 1
+#define reg_iop_spu_r_wr_stat___r2___bit 2
+#define reg_iop_spu_r_wr_stat___r3___lsb 3
+#define reg_iop_spu_r_wr_stat___r3___width 1
+#define reg_iop_spu_r_wr_stat___r3___bit 3
+#define reg_iop_spu_r_wr_stat___r4___lsb 4
+#define reg_iop_spu_r_wr_stat___r4___width 1
+#define reg_iop_spu_r_wr_stat___r4___bit 4
+#define reg_iop_spu_r_wr_stat___r5___lsb 5
+#define reg_iop_spu_r_wr_stat___r5___width 1
+#define reg_iop_spu_r_wr_stat___r5___bit 5
+#define reg_iop_spu_r_wr_stat___r6___lsb 6
+#define reg_iop_spu_r_wr_stat___r6___width 1
+#define reg_iop_spu_r_wr_stat___r6___bit 6
+#define reg_iop_spu_r_wr_stat___r7___lsb 7
+#define reg_iop_spu_r_wr_stat___r7___width 1
+#define reg_iop_spu_r_wr_stat___r7___bit 7
+#define reg_iop_spu_r_wr_stat___r8___lsb 8
+#define reg_iop_spu_r_wr_stat___r8___width 1
+#define reg_iop_spu_r_wr_stat___r8___bit 8
+#define reg_iop_spu_r_wr_stat___r9___lsb 9
+#define reg_iop_spu_r_wr_stat___r9___width 1
+#define reg_iop_spu_r_wr_stat___r9___bit 9
+#define reg_iop_spu_r_wr_stat___r10___lsb 10
+#define reg_iop_spu_r_wr_stat___r10___width 1
+#define reg_iop_spu_r_wr_stat___r10___bit 10
+#define reg_iop_spu_r_wr_stat___r11___lsb 11
+#define reg_iop_spu_r_wr_stat___r11___width 1
+#define reg_iop_spu_r_wr_stat___r11___bit 11
+#define reg_iop_spu_r_wr_stat___r12___lsb 12
+#define reg_iop_spu_r_wr_stat___r12___width 1
+#define reg_iop_spu_r_wr_stat___r12___bit 12
+#define reg_iop_spu_r_wr_stat___r13___lsb 13
+#define reg_iop_spu_r_wr_stat___r13___width 1
+#define reg_iop_spu_r_wr_stat___r13___bit 13
+#define reg_iop_spu_r_wr_stat___r14___lsb 14
+#define reg_iop_spu_r_wr_stat___r14___width 1
+#define reg_iop_spu_r_wr_stat___r14___bit 14
+#define reg_iop_spu_r_wr_stat___r15___lsb 15
+#define reg_iop_spu_r_wr_stat___r15___width 1
+#define reg_iop_spu_r_wr_stat___r15___bit 15
+#define reg_iop_spu_r_wr_stat_offset 120
+
+/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
+#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
+
+/* Register r_stat_in, scope iop_spu, type r */
+#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
+#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
+#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
+#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
+#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
+#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
+#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
+#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
+#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
+#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
+#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
+#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
+#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
+#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
+#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
+#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
+#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
+#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
+#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
+#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
+#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
+#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
+#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
+#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
+#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
+#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
+#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
+#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
+#define reg_iop_spu_r_stat_in___sync_clk12___width 1
+#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
+#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
+#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
+#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
+#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
+#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
+#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
+#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
+#define reg_iop_spu_r_stat_in___mc_busy___width 1
+#define reg_iop_spu_r_stat_in___mc_busy___bit 30
+#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
+#define reg_iop_spu_r_stat_in___mc_owned___width 1
+#define reg_iop_spu_r_stat_in___mc_owned___bit 31
+#define reg_iop_spu_r_stat_in_offset 128
+
+/* Register r_trigger_in, scope iop_spu, type r */
+#define reg_iop_spu_r_trigger_in_offset 132
+
+/* Register r_special_stat, scope iop_spu, type r */
+#define reg_iop_spu_r_special_stat___c_flag___lsb 0
+#define reg_iop_spu_r_special_stat___c_flag___width 1
+#define reg_iop_spu_r_special_stat___c_flag___bit 0
+#define reg_iop_spu_r_special_stat___v_flag___lsb 1
+#define reg_iop_spu_r_special_stat___v_flag___width 1
+#define reg_iop_spu_r_special_stat___v_flag___bit 1
+#define reg_iop_spu_r_special_stat___z_flag___lsb 2
+#define reg_iop_spu_r_special_stat___z_flag___width 1
+#define reg_iop_spu_r_special_stat___z_flag___bit 2
+#define reg_iop_spu_r_special_stat___n_flag___lsb 3
+#define reg_iop_spu_r_special_stat___n_flag___width 1
+#define reg_iop_spu_r_special_stat___n_flag___bit 3
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
+#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
+#define reg_iop_spu_r_special_stat___fsm_in0___width 1
+#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
+#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
+#define reg_iop_spu_r_special_stat___fsm_in1___width 1
+#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
+#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
+#define reg_iop_spu_r_special_stat___fsm_in2___width 1
+#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
+#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
+#define reg_iop_spu_r_special_stat___fsm_in3___width 1
+#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
+#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
+#define reg_iop_spu_r_special_stat___fsm_in4___width 1
+#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
+#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
+#define reg_iop_spu_r_special_stat___fsm_in5___width 1
+#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
+#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
+#define reg_iop_spu_r_special_stat___fsm_in6___width 1
+#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
+#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
+#define reg_iop_spu_r_special_stat___fsm_in7___width 1
+#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
+#define reg_iop_spu_r_special_stat___event0___lsb 16
+#define reg_iop_spu_r_special_stat___event0___width 1
+#define reg_iop_spu_r_special_stat___event0___bit 16
+#define reg_iop_spu_r_special_stat___event1___lsb 17
+#define reg_iop_spu_r_special_stat___event1___width 1
+#define reg_iop_spu_r_special_stat___event1___bit 17
+#define reg_iop_spu_r_special_stat___event2___lsb 18
+#define reg_iop_spu_r_special_stat___event2___width 1
+#define reg_iop_spu_r_special_stat___event2___bit 18
+#define reg_iop_spu_r_special_stat___event3___lsb 19
+#define reg_iop_spu_r_special_stat___event3___width 1
+#define reg_iop_spu_r_special_stat___event3___bit 19
+#define reg_iop_spu_r_special_stat_offset 136
+
+/* Register rw_reg_access, scope iop_spu, type rw */
+#define reg_iop_spu_rw_reg_access___addr___lsb 0
+#define reg_iop_spu_rw_reg_access___addr___width 13
+#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
+#define reg_iop_spu_rw_reg_access___imm_hi___width 16
+#define reg_iop_spu_rw_reg_access_offset 140
+
+#define STRIDE_iop_spu_rw_event_cfg 4
+/* Register rw_event_cfg, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_cfg___addr___lsb 0
+#define reg_iop_spu_rw_event_cfg___addr___width 12
+#define reg_iop_spu_rw_event_cfg___src___lsb 12
+#define reg_iop_spu_rw_event_cfg___src___width 2
+#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
+#define reg_iop_spu_rw_event_cfg___eq_en___width 1
+#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
+#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
+#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
+#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
+#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
+#define reg_iop_spu_rw_event_cfg___gt_en___width 1
+#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
+#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
+#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
+#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
+#define reg_iop_spu_rw_event_cfg_offset 144
+
+#define STRIDE_iop_spu_rw_event_mask 4
+/* Register rw_event_mask, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_mask_offset 160
+
+#define STRIDE_iop_spu_rw_event_val 4
+/* Register rw_event_val, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_val_offset 176
+
+/* Register rw_event_ret, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_ret___addr___lsb 0
+#define reg_iop_spu_rw_event_ret___addr___width 12
+#define reg_iop_spu_rw_event_ret_offset 192
+
+/* Register r_trace, scope iop_spu, type r */
+#define reg_iop_spu_r_trace___fsm___lsb 0
+#define reg_iop_spu_r_trace___fsm___width 1
+#define reg_iop_spu_r_trace___fsm___bit 0
+#define reg_iop_spu_r_trace___en___lsb 1
+#define reg_iop_spu_r_trace___en___width 1
+#define reg_iop_spu_r_trace___en___bit 1
+#define reg_iop_spu_r_trace___c_flag___lsb 2
+#define reg_iop_spu_r_trace___c_flag___width 1
+#define reg_iop_spu_r_trace___c_flag___bit 2
+#define reg_iop_spu_r_trace___v_flag___lsb 3
+#define reg_iop_spu_r_trace___v_flag___width 1
+#define reg_iop_spu_r_trace___v_flag___bit 3
+#define reg_iop_spu_r_trace___z_flag___lsb 4
+#define reg_iop_spu_r_trace___z_flag___width 1
+#define reg_iop_spu_r_trace___z_flag___bit 4
+#define reg_iop_spu_r_trace___n_flag___lsb 5
+#define reg_iop_spu_r_trace___n_flag___width 1
+#define reg_iop_spu_r_trace___n_flag___bit 5
+#define reg_iop_spu_r_trace___seq_addr___lsb 6
+#define reg_iop_spu_r_trace___seq_addr___width 12
+#define reg_iop_spu_r_trace___fsm_addr___lsb 20
+#define reg_iop_spu_r_trace___fsm_addr___width 12
+#define reg_iop_spu_r_trace_offset 196
+
+/* Register r_fsm_trace, scope iop_spu, type r */
+#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
+#define reg_iop_spu_r_fsm_trace___fsm___width 1
+#define reg_iop_spu_r_fsm_trace___fsm___bit 0
+#define reg_iop_spu_r_fsm_trace___en___lsb 1
+#define reg_iop_spu_r_fsm_trace___en___width 1
+#define reg_iop_spu_r_fsm_trace___en___bit 1
+#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
+#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
+#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
+#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
+#define reg_iop_spu_r_fsm_trace___inp0___width 1
+#define reg_iop_spu_r_fsm_trace___inp0___bit 3
+#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
+#define reg_iop_spu_r_fsm_trace___inp1___width 1
+#define reg_iop_spu_r_fsm_trace___inp1___bit 4
+#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
+#define reg_iop_spu_r_fsm_trace___inp2___width 1
+#define reg_iop_spu_r_fsm_trace___inp2___bit 5
+#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
+#define reg_iop_spu_r_fsm_trace___inp3___width 1
+#define reg_iop_spu_r_fsm_trace___inp3___bit 6
+#define reg_iop_spu_r_fsm_trace___event0___lsb 7
+#define reg_iop_spu_r_fsm_trace___event0___width 1
+#define reg_iop_spu_r_fsm_trace___event0___bit 7
+#define reg_iop_spu_r_fsm_trace___event1___lsb 8
+#define reg_iop_spu_r_fsm_trace___event1___width 1
+#define reg_iop_spu_r_fsm_trace___event1___bit 8
+#define reg_iop_spu_r_fsm_trace___event2___lsb 9
+#define reg_iop_spu_r_fsm_trace___event2___width 1
+#define reg_iop_spu_r_fsm_trace___event2___bit 9
+#define reg_iop_spu_r_fsm_trace___event3___lsb 10
+#define reg_iop_spu_r_fsm_trace___event3___width 1
+#define reg_iop_spu_r_fsm_trace___event3___bit 10
+#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
+#define reg_iop_spu_r_fsm_trace___gio_out___width 8
+#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
+#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
+#define reg_iop_spu_r_fsm_trace_offset 200
+
+#define STRIDE_iop_spu_rw_brp 4
+/* Register rw_brp, scope iop_spu, type rw */
+#define reg_iop_spu_rw_brp___addr___lsb 0
+#define reg_iop_spu_rw_brp___addr___width 12
+#define reg_iop_spu_rw_brp___fsm___lsb 12
+#define reg_iop_spu_rw_brp___fsm___width 1
+#define reg_iop_spu_rw_brp___fsm___bit 12
+#define reg_iop_spu_rw_brp___en___lsb 13
+#define reg_iop_spu_rw_brp___en___width 1
+#define reg_iop_spu_rw_brp___en___bit 13
+#define reg_iop_spu_rw_brp_offset 204
+
+
+/* Constants */
+#define regk_iop_spu_attn_hi                      0x00000005
+#define regk_iop_spu_attn_lo                      0x00000005
+#define regk_iop_spu_attn_r0                      0x00000000
+#define regk_iop_spu_attn_r1                      0x00000001
+#define regk_iop_spu_attn_r10                     0x00000002
+#define regk_iop_spu_attn_r11                     0x00000003
+#define regk_iop_spu_attn_r12                     0x00000004
+#define regk_iop_spu_attn_r13                     0x00000005
+#define regk_iop_spu_attn_r14                     0x00000006
+#define regk_iop_spu_attn_r15                     0x00000007
+#define regk_iop_spu_attn_r2                      0x00000002
+#define regk_iop_spu_attn_r3                      0x00000003
+#define regk_iop_spu_attn_r4                      0x00000004
+#define regk_iop_spu_attn_r5                      0x00000005
+#define regk_iop_spu_attn_r6                      0x00000006
+#define regk_iop_spu_attn_r7                      0x00000007
+#define regk_iop_spu_attn_r8                      0x00000000
+#define regk_iop_spu_attn_r9                      0x00000001
+#define regk_iop_spu_c                            0x00000000
+#define regk_iop_spu_flag                         0x00000002
+#define regk_iop_spu_gio_in                       0x00000000
+#define regk_iop_spu_gio_out                      0x00000005
+#define regk_iop_spu_gio_out0                     0x00000008
+#define regk_iop_spu_gio_out1                     0x00000009
+#define regk_iop_spu_gio_out2                     0x0000000a
+#define regk_iop_spu_gio_out3                     0x0000000b
+#define regk_iop_spu_gio_out4                     0x0000000c
+#define regk_iop_spu_gio_out5                     0x0000000d
+#define regk_iop_spu_gio_out6                     0x0000000e
+#define regk_iop_spu_gio_out7                     0x0000000f
+#define regk_iop_spu_n                            0x00000003
+#define regk_iop_spu_no                           0x00000000
+#define regk_iop_spu_r0                           0x00000008
+#define regk_iop_spu_r1                           0x00000009
+#define regk_iop_spu_r10                          0x0000000a
+#define regk_iop_spu_r11                          0x0000000b
+#define regk_iop_spu_r12                          0x0000000c
+#define regk_iop_spu_r13                          0x0000000d
+#define regk_iop_spu_r14                          0x0000000e
+#define regk_iop_spu_r15                          0x0000000f
+#define regk_iop_spu_r2                           0x0000000a
+#define regk_iop_spu_r3                           0x0000000b
+#define regk_iop_spu_r4                           0x0000000c
+#define regk_iop_spu_r5                           0x0000000d
+#define regk_iop_spu_r6                           0x0000000e
+#define regk_iop_spu_r7                           0x0000000f
+#define regk_iop_spu_r8                           0x00000008
+#define regk_iop_spu_r9                           0x00000009
+#define regk_iop_spu_reg_hi                       0x00000002
+#define regk_iop_spu_reg_lo                       0x00000002
+#define regk_iop_spu_rw_brp_default               0x00000000
+#define regk_iop_spu_rw_brp_size                  0x00000004
+#define regk_iop_spu_rw_ctrl_default              0x00000000
+#define regk_iop_spu_rw_event_cfg_size            0x00000004
+#define regk_iop_spu_rw_event_mask_size           0x00000004
+#define regk_iop_spu_rw_event_val_size            0x00000004
+#define regk_iop_spu_rw_gio_out_default           0x00000000
+#define regk_iop_spu_rw_r_size                    0x00000010
+#define regk_iop_spu_rw_reg_access_default        0x00000000
+#define regk_iop_spu_stat_in                      0x00000002
+#define regk_iop_spu_statin_hi                    0x00000004
+#define regk_iop_spu_statin_lo                    0x00000004
+#define regk_iop_spu_trig                         0x00000003
+#define regk_iop_spu_trigger                      0x00000006
+#define regk_iop_spu_v                            0x00000001
+#define regk_iop_spu_wsts_gioout_spec             0x00000001
+#define regk_iop_spu_xor                          0x00000003
+#define regk_iop_spu_xor_bus0_r2_0                0x00000000
+#define regk_iop_spu_xor_bus0m_r2_0               0x00000002
+#define regk_iop_spu_xor_bus1_r3_0                0x00000001
+#define regk_iop_spu_xor_bus1m_r3_0               0x00000003
+#define regk_iop_spu_yes                          0x00000001
+#define regk_iop_spu_z                            0x00000002
+#endif /* __iop_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
new file mode 100644
index 000000000000..3be60f9b024c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
@@ -0,0 +1,1052 @@
+#ifndef __iop_sw_cfg_defs_asm_h
+#define __iop_sw_cfg_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *      id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
+
+/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
+
+/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
+
+/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
+
+/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
+
+/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
+
+/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
+
+/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
+
+/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
+
+/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
+
+/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
+
+/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
+
+/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
+
+/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
+
+/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
+
+/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
+
+/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
+
+/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
+
+/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
+
+/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
+
+/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
+
+/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
+
+/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
+#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
+#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
+
+/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
+#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
+
+/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
+#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
+#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
+
+/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
+#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_mask_offset 152
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
+#define reg_iop_sw_cfg_rw_pinmapping_offset 160
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
+
+/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
+#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
+
+/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
+#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
+
+/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
+
+/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
+
+/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
+#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
+
+/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
+#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
+
+
+/* Constants */
+#define regk_iop_sw_cfg_a                         0x00000001
+#define regk_iop_sw_cfg_b                         0x00000002
+#define regk_iop_sw_cfg_bus0                      0x00000000
+#define regk_iop_sw_cfg_bus0_rot16                0x00000004
+#define regk_iop_sw_cfg_bus0_rot24                0x00000006
+#define regk_iop_sw_cfg_bus0_rot8                 0x00000002
+#define regk_iop_sw_cfg_bus1                      0x00000001
+#define regk_iop_sw_cfg_bus1_rot16                0x00000005
+#define regk_iop_sw_cfg_bus1_rot24                0x00000007
+#define regk_iop_sw_cfg_bus1_rot8                 0x00000003
+#define regk_iop_sw_cfg_clk12                     0x00000000
+#define regk_iop_sw_cfg_cpu                       0x00000000
+#define regk_iop_sw_cfg_dmc0                      0x00000000
+#define regk_iop_sw_cfg_dmc1                      0x00000001
+#define regk_iop_sw_cfg_gated_clk0                0x00000010
+#define regk_iop_sw_cfg_gated_clk1                0x00000011
+#define regk_iop_sw_cfg_gated_clk2                0x00000012
+#define regk_iop_sw_cfg_gated_clk3                0x00000013
+#define regk_iop_sw_cfg_gio0                      0x00000004
+#define regk_iop_sw_cfg_gio1                      0x00000001
+#define regk_iop_sw_cfg_gio2                      0x00000005
+#define regk_iop_sw_cfg_gio3                      0x00000002
+#define regk_iop_sw_cfg_gio4                      0x00000006
+#define regk_iop_sw_cfg_gio5                      0x00000003
+#define regk_iop_sw_cfg_gio6                      0x00000007
+#define regk_iop_sw_cfg_gio7                      0x00000004
+#define regk_iop_sw_cfg_gio_in0                   0x00000000
+#define regk_iop_sw_cfg_gio_in1                   0x00000001
+#define regk_iop_sw_cfg_gio_in10                  0x00000002
+#define regk_iop_sw_cfg_gio_in11                  0x00000003
+#define regk_iop_sw_cfg_gio_in14                  0x00000004
+#define regk_iop_sw_cfg_gio_in15                  0x00000005
+#define regk_iop_sw_cfg_gio_in18                  0x00000002
+#define regk_iop_sw_cfg_gio_in19                  0x00000003
+#define regk_iop_sw_cfg_gio_in20                  0x00000004
+#define regk_iop_sw_cfg_gio_in21                  0x00000005
+#define regk_iop_sw_cfg_gio_in26                  0x00000006
+#define regk_iop_sw_cfg_gio_in27                  0x00000007
+#define regk_iop_sw_cfg_gio_in28                  0x00000006
+#define regk_iop_sw_cfg_gio_in29                  0x00000007
+#define regk_iop_sw_cfg_gio_in4                   0x00000000
+#define regk_iop_sw_cfg_gio_in5                   0x00000001
+#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
+#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000001
+#define regk_iop_sw_cfg_last_timer_grp2_tmr2      0x00000002
+#define regk_iop_sw_cfg_last_timer_grp2_tmr3      0x00000003
+#define regk_iop_sw_cfg_last_timer_grp3_tmr2      0x00000002
+#define regk_iop_sw_cfg_last_timer_grp3_tmr3      0x00000003
+#define regk_iop_sw_cfg_mpu                       0x00000001
+#define regk_iop_sw_cfg_none                      0x00000000
+#define regk_iop_sw_cfg_par0                      0x00000000
+#define regk_iop_sw_cfg_par1                      0x00000001
+#define regk_iop_sw_cfg_pdp_out0                  0x00000002
+#define regk_iop_sw_cfg_pdp_out0_hi               0x00000001
+#define regk_iop_sw_cfg_pdp_out0_hi_rot8          0x00000005
+#define regk_iop_sw_cfg_pdp_out0_lo               0x00000000
+#define regk_iop_sw_cfg_pdp_out0_lo_rot8          0x00000004
+#define regk_iop_sw_cfg_pdp_out1                  0x00000003
+#define regk_iop_sw_cfg_pdp_out1_hi               0x00000003
+#define regk_iop_sw_cfg_pdp_out1_hi_rot8          0x00000005
+#define regk_iop_sw_cfg_pdp_out1_lo               0x00000002
+#define regk_iop_sw_cfg_pdp_out1_lo_rot8          0x00000004
+#define regk_iop_sw_cfg_rw_bus0_mask_default      0x00000000
+#define regk_iop_sw_cfg_rw_bus0_oe_mask_default   0x00000000
+#define regk_iop_sw_cfg_rw_bus1_mask_default      0x00000000
+#define regk_iop_sw_cfg_rw_bus1_oe_mask_default   0x00000000
+#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
+#define regk_iop_sw_cfg_rw_crc_par0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_crc_par1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
+#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_pdp0_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_pdp1_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_pinmapping_default     0x55555555
+#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
+#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
+#define regk_iop_sw_cfg_rw_spu0_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_spu0_owner_default     0x00000000
+#define regk_iop_sw_cfg_rw_spu1_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_spu1_owner_default     0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp2_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp3_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
+#define regk_iop_sw_cfg_sdp_out0                  0x00000008
+#define regk_iop_sw_cfg_sdp_out1                  0x00000009
+#define regk_iop_sw_cfg_size16                    0x00000002
+#define regk_iop_sw_cfg_size24                    0x00000003
+#define regk_iop_sw_cfg_size32                    0x00000004
+#define regk_iop_sw_cfg_size8                     0x00000001
+#define regk_iop_sw_cfg_spu0                      0x00000002
+#define regk_iop_sw_cfg_spu0_bus_out0_hi          0x00000006
+#define regk_iop_sw_cfg_spu0_bus_out0_lo          0x00000006
+#define regk_iop_sw_cfg_spu0_bus_out1_hi          0x00000007
+#define regk_iop_sw_cfg_spu0_bus_out1_lo          0x00000007
+#define regk_iop_sw_cfg_spu0_g0                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g1                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g2                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g3                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g4                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g5                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g6                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g7                   0x0000000e
+#define regk_iop_sw_cfg_spu0_gio0                 0x00000000
+#define regk_iop_sw_cfg_spu0_gio1                 0x00000001
+#define regk_iop_sw_cfg_spu0_gio2                 0x00000000
+#define regk_iop_sw_cfg_spu0_gio5                 0x00000005
+#define regk_iop_sw_cfg_spu0_gio6                 0x00000006
+#define regk_iop_sw_cfg_spu0_gio7                 0x00000007
+#define regk_iop_sw_cfg_spu0_gio_out0             0x00000008
+#define regk_iop_sw_cfg_spu0_gio_out1             0x00000009
+#define regk_iop_sw_cfg_spu0_gio_out2             0x0000000a
+#define regk_iop_sw_cfg_spu0_gio_out3             0x0000000b
+#define regk_iop_sw_cfg_spu0_gio_out4             0x0000000c
+#define regk_iop_sw_cfg_spu0_gio_out5             0x0000000d
+#define regk_iop_sw_cfg_spu0_gio_out6             0x0000000e
+#define regk_iop_sw_cfg_spu0_gio_out7             0x0000000f
+#define regk_iop_sw_cfg_spu0_gioout0              0x00000000
+#define regk_iop_sw_cfg_spu0_gioout1              0x00000000
+#define regk_iop_sw_cfg_spu0_gioout10             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout11             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout12             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout13             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout14             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout15             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout16             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout17             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout18             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout19             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout2              0x00000002
+#define regk_iop_sw_cfg_spu0_gioout20             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout21             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout22             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout23             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout24             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout25             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout26             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout27             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout28             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout29             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout3              0x00000002
+#define regk_iop_sw_cfg_spu0_gioout30             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout31             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout4              0x00000004
+#define regk_iop_sw_cfg_spu0_gioout5              0x00000004
+#define regk_iop_sw_cfg_spu0_gioout6              0x00000006
+#define regk_iop_sw_cfg_spu0_gioout7              0x00000006
+#define regk_iop_sw_cfg_spu0_gioout8              0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout9              0x0000000e
+#define regk_iop_sw_cfg_spu1                      0x00000003
+#define regk_iop_sw_cfg_spu1_bus_out0_hi          0x00000006
+#define regk_iop_sw_cfg_spu1_bus_out0_lo          0x00000006
+#define regk_iop_sw_cfg_spu1_bus_out1_hi          0x00000007
+#define regk_iop_sw_cfg_spu1_bus_out1_lo          0x00000007
+#define regk_iop_sw_cfg_spu1_g0                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g1                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g2                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g3                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g4                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g5                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g6                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g7                   0x0000000f
+#define regk_iop_sw_cfg_spu1_gio0                 0x00000002
+#define regk_iop_sw_cfg_spu1_gio1                 0x00000003
+#define regk_iop_sw_cfg_spu1_gio2                 0x00000002
+#define regk_iop_sw_cfg_spu1_gio5                 0x00000005
+#define regk_iop_sw_cfg_spu1_gio6                 0x00000006
+#define regk_iop_sw_cfg_spu1_gio7                 0x00000007
+#define regk_iop_sw_cfg_spu1_gio_out0             0x00000008
+#define regk_iop_sw_cfg_spu1_gio_out1             0x00000009
+#define regk_iop_sw_cfg_spu1_gio_out2             0x0000000a
+#define regk_iop_sw_cfg_spu1_gio_out3             0x0000000b
+#define regk_iop_sw_cfg_spu1_gio_out4             0x0000000c
+#define regk_iop_sw_cfg_spu1_gio_out5             0x0000000d
+#define regk_iop_sw_cfg_spu1_gio_out6             0x0000000e
+#define regk_iop_sw_cfg_spu1_gio_out7             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout0              0x00000001
+#define regk_iop_sw_cfg_spu1_gioout1              0x00000001
+#define regk_iop_sw_cfg_spu1_gioout10             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout11             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout12             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout13             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout14             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout15             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout16             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout17             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout18             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout19             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout2              0x00000003
+#define regk_iop_sw_cfg_spu1_gioout20             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout21             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout22             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout23             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout24             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout25             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout26             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout27             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout28             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout29             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout3              0x00000003
+#define regk_iop_sw_cfg_spu1_gioout30             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout31             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout4              0x00000005
+#define regk_iop_sw_cfg_spu1_gioout5              0x00000005
+#define regk_iop_sw_cfg_spu1_gioout6              0x00000007
+#define regk_iop_sw_cfg_spu1_gioout7              0x00000007
+#define regk_iop_sw_cfg_spu1_gioout8              0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout9              0x0000000f
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000001
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp2_tmr0      0x00000003
+#define regk_iop_sw_cfg_strb_timer_grp2_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp3_tmr0      0x00000003
+#define regk_iop_sw_cfg_strb_timer_grp3_tmr1      0x00000002
+#define regk_iop_sw_cfg_timer_grp0                0x00000000
+#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp0_strb0          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb1          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb2          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb3          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000004
+#define regk_iop_sw_cfg_timer_grp0_tmr1           0x00000004
+#define regk_iop_sw_cfg_timer_grp1                0x00000000
+#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp1_strb0          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb1          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb2          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb3          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000005
+#define regk_iop_sw_cfg_timer_grp1_tmr1           0x00000005
+#define regk_iop_sw_cfg_timer_grp2                0x00000000
+#define regk_iop_sw_cfg_timer_grp2_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp2_strb0          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb1          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb2          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb3          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_tmr0           0x00000006
+#define regk_iop_sw_cfg_timer_grp2_tmr1           0x00000006
+#define regk_iop_sw_cfg_timer_grp3                0x00000000
+#define regk_iop_sw_cfg_timer_grp3_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp3_strb0          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb1          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb2          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb3          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_tmr0           0x00000007
+#define regk_iop_sw_cfg_timer_grp3_tmr1           0x00000007
+#define regk_iop_sw_cfg_trig0_0                   0x00000000
+#define regk_iop_sw_cfg_trig0_1                   0x00000000
+#define regk_iop_sw_cfg_trig0_2                   0x00000000
+#define regk_iop_sw_cfg_trig0_3                   0x00000000
+#define regk_iop_sw_cfg_trig1_0                   0x00000000
+#define regk_iop_sw_cfg_trig1_1                   0x00000000
+#define regk_iop_sw_cfg_trig1_2                   0x00000000
+#define regk_iop_sw_cfg_trig1_3                   0x00000000
+#define regk_iop_sw_cfg_trig2_0                   0x00000000
+#define regk_iop_sw_cfg_trig2_1                   0x00000000
+#define regk_iop_sw_cfg_trig2_2                   0x00000000
+#define regk_iop_sw_cfg_trig2_3                   0x00000000
+#define regk_iop_sw_cfg_trig3_0                   0x00000000
+#define regk_iop_sw_cfg_trig3_1                   0x00000000
+#define regk_iop_sw_cfg_trig3_2                   0x00000000
+#define regk_iop_sw_cfg_trig3_3                   0x00000000
+#define regk_iop_sw_cfg_trig4_0                   0x00000001
+#define regk_iop_sw_cfg_trig4_1                   0x00000001
+#define regk_iop_sw_cfg_trig4_2                   0x00000001
+#define regk_iop_sw_cfg_trig4_3                   0x00000001
+#define regk_iop_sw_cfg_trig5_0                   0x00000001
+#define regk_iop_sw_cfg_trig5_1                   0x00000001
+#define regk_iop_sw_cfg_trig5_2                   0x00000001
+#define regk_iop_sw_cfg_trig5_3                   0x00000001
+#define regk_iop_sw_cfg_trig6_0                   0x00000001
+#define regk_iop_sw_cfg_trig6_1                   0x00000001
+#define regk_iop_sw_cfg_trig6_2                   0x00000001
+#define regk_iop_sw_cfg_trig6_3                   0x00000001
+#define regk_iop_sw_cfg_trig7_0                   0x00000001
+#define regk_iop_sw_cfg_trig7_1                   0x00000001
+#define regk_iop_sw_cfg_trig7_2                   0x00000001
+#define regk_iop_sw_cfg_trig7_3                   0x00000001
+#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
new file mode 100644
index 000000000000..db347bcba025
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
@@ -0,0 +1,1758 @@
+#ifndef __iop_sw_cpu_defs_asm_h
+#define __iop_sw_cpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *      id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_cpu_rw_mc_data___val___width 32
+#define reg_iop_sw_cpu_rw_mc_data_offset 4
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_addr_offset 8
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+#define reg_iop_sw_cpu_rs_mc_data_offset 12
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_data_offset 16
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_cpu_r_mc_stat_offset 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
+
+/* Register r_bus0_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_bus0_in_offset 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
+
+/* Register r_bus1_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_bus1_in_offset 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_gio_in_offset 80
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
+#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_r_intr0_offset 92
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_r_masked_intr0_offset 96
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
+#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_r_intr1_offset 108
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_r_masked_intr1_offset 112
+
+/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
+#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
+
+/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
+
+/* Register r_intr2, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_intr2_offset 124
+
+/* Register r_masked_intr2, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_masked_intr2_offset 128
+
+/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
+#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
+
+/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
+
+/* Register r_intr3, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
+#define reg_iop_sw_cpu_r_intr3_offset 140
+
+/* Register r_masked_intr3, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
+#define reg_iop_sw_cpu_r_masked_intr3_offset 144
+
+
+/* Constants */
+#define regk_iop_sw_cpu_copy                      0x00000000
+#define regk_iop_sw_cpu_no                        0x00000000
+#define regk_iop_sw_cpu_rd                        0x00000002
+#define regk_iop_sw_cpu_reg_copy                  0x00000001
+#define regk_iop_sw_cpu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr2_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr3_mask_default     0x00000000
+#define regk_iop_sw_cpu_wr                        0x00000003
+#define regk_iop_sw_cpu_yes                       0x00000001
+#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
new file mode 100644
index 000000000000..ee7dc0435b59
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
@@ -0,0 +1,1776 @@
+#ifndef __iop_sw_mpu_defs_asm_h
+#define __iop_sw_mpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *      id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
+#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_mpu_rw_mc_data___val___width 32
+#define reg_iop_sw_mpu_rw_mc_data_offset 8
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_addr_offset 12
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+#define reg_iop_sw_mpu_rs_mc_data_offset 16
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_data_offset 20
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_mpu_r_mc_stat_offset 24
+
+/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
+
+/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
+
+/* Register r_bus0_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_bus0_in_offset 44
+
+/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
+
+/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
+
+/* Register r_bus1_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_bus1_in_offset 64
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_gio_in_offset 84
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_r_cpu_intr_offset 92
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp0_offset 104
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp1_offset 120
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp2_offset 136
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp3_offset 152
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
+
+
+/* Constants */
+#define regk_iop_sw_mpu_copy                      0x00000000
+#define regk_iop_sw_mpu_cpu                       0x00000000
+#define regk_iop_sw_mpu_mpu                       0x00000001
+#define regk_iop_sw_mpu_no                        0x00000000
+#define regk_iop_sw_mpu_nop                       0x00000000
+#define regk_iop_sw_mpu_rd                        0x00000002
+#define regk_iop_sw_mpu_reg_copy                  0x00000001
+#define regk_iop_sw_mpu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp0_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp1_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp2_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp3_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_sw_cfg_owner_default   0x00000000
+#define regk_iop_sw_mpu_set                       0x00000001
+#define regk_iop_sw_mpu_spu0                      0x00000002
+#define regk_iop_sw_mpu_spu1                      0x00000003
+#define regk_iop_sw_mpu_wr                        0x00000003
+#define regk_iop_sw_mpu_yes                       0x00000001
+#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
new file mode 100644
index 000000000000..0929f144cfa1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
@@ -0,0 +1,691 @@
+#ifndef __iop_sw_spu_defs_asm_h
+#define __iop_sw_spu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *      id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_spu_rw_mc_data___val___width 32
+#define reg_iop_sw_spu_rw_mc_data_offset 4
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_addr_offset 8
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+#define reg_iop_sw_spu_rs_mc_data_offset 12
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_data_offset 16
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_spu_r_mc_stat_offset 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
+
+/* Register r_bus0_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_bus0_in_offset 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
+
+/* Register r_bus1_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_bus1_in_offset 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_gio_in_offset 80
+
+/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
+
+/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
+
+/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
+
+/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
+
+/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
+
+/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
+
+/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
+
+/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_cpu_intr_offset 148
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_cpu_intr_offset 152
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
+#define reg_iop_sw_spu_r_hw_intr_offset 156
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_mpu_intr_offset 160
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
+#define reg_iop_sw_spu_r_mpu_intr_offset 164
+
+
+/* Constants */
+#define regk_iop_sw_spu_copy                      0x00000000
+#define regk_iop_sw_spu_no                        0x00000000
+#define regk_iop_sw_spu_nop                       0x00000000
+#define regk_iop_sw_spu_rd                        0x00000002
+#define regk_iop_sw_spu_reg_copy                  0x00000001
+#define regk_iop_sw_spu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_spu_set                       0x00000001
+#define regk_iop_sw_spu_wr                        0x00000003
+#define regk_iop_sw_spu_yes                       0x00000001
+#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
new file mode 100644
index 000000000000..7129a9a4bedc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
@@ -0,0 +1,237 @@
+#ifndef __iop_timer_grp_defs_asm_h
+#define __iop_timer_grp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
+ *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
+ *      id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
+#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
+#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
+#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
+#define reg_iop_timer_grp_rw_cfg___trig___width 2
+#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
+#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
+#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
+#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
+#define reg_iop_timer_grp_rw_cfg_offset 0
+
+/* Register rw_half_period, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
+#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
+#define reg_iop_timer_grp_rw_half_period_offset 4
+
+/* Register rw_half_period_len, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_half_period_len_offset 8
+
+#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
+/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
+#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
+#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
+#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
+#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
+#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
+#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
+#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
+#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
+#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
+
+#define STRIDE_iop_timer_grp_rw_tmr_len 4
+/* Register rw_tmr_len, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
+#define reg_iop_timer_grp_rw_tmr_len___val___width 16
+#define reg_iop_timer_grp_rw_tmr_len_offset 44
+
+/* Register rw_cmd, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
+#define reg_iop_timer_grp_rw_cmd___rst___width 4
+#define reg_iop_timer_grp_rw_cmd___en___lsb 4
+#define reg_iop_timer_grp_rw_cmd___en___width 4
+#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
+#define reg_iop_timer_grp_rw_cmd___dis___width 4
+#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
+#define reg_iop_timer_grp_rw_cmd___strb___width 4
+#define reg_iop_timer_grp_rw_cmd_offset 60
+
+/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
+
+#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
+/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
+#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
+#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
+#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
+
+#define STRIDE_iop_timer_grp_r_tmr_cnt 8
+/* Register r_tmr_cnt, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
+#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
+#define reg_iop_timer_grp_r_tmr_cnt_offset 72
+
+/* Register rw_intr_mask, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
+#define reg_iop_timer_grp_rw_intr_mask_offset 100
+
+/* Register rw_ack_intr, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
+#define reg_iop_timer_grp_rw_ack_intr_offset 104
+
+/* Register r_intr, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_r_intr___tmr0___width 1
+#define reg_iop_timer_grp_r_intr___tmr0___bit 0
+#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_r_intr___tmr1___width 1
+#define reg_iop_timer_grp_r_intr___tmr1___bit 1
+#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_r_intr___tmr2___width 1
+#define reg_iop_timer_grp_r_intr___tmr2___bit 2
+#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_r_intr___tmr3___width 1
+#define reg_iop_timer_grp_r_intr___tmr3___bit 3
+#define reg_iop_timer_grp_r_intr_offset 108
+
+/* Register r_masked_intr, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
+#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
+#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
+#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
+#define reg_iop_timer_grp_r_masked_intr_offset 112
+
+
+/* Constants */
+#define regk_iop_timer_grp_clk200                 0x00000000
+#define regk_iop_timer_grp_clk_gen                0x00000002
+#define regk_iop_timer_grp_complete               0x00000002
+#define regk_iop_timer_grp_div_clk200             0x00000001
+#define regk_iop_timer_grp_div_clk_gen            0x00000003
+#define regk_iop_timer_grp_ext                    0x00000001
+#define regk_iop_timer_grp_hi                     0x00000000
+#define regk_iop_timer_grp_long_period            0x00000001
+#define regk_iop_timer_grp_neg                    0x00000002
+#define regk_iop_timer_grp_no                     0x00000000
+#define regk_iop_timer_grp_once                   0x00000003
+#define regk_iop_timer_grp_pause                  0x00000001
+#define regk_iop_timer_grp_pos                    0x00000001
+#define regk_iop_timer_grp_pos_neg                0x00000003
+#define regk_iop_timer_grp_pulse                  0x00000000
+#define regk_iop_timer_grp_r_tmr_cnt_size         0x00000004
+#define regk_iop_timer_grp_rs_tmr_cnt_size        0x00000004
+#define regk_iop_timer_grp_rw_cfg_default         0x00000002
+#define regk_iop_timer_grp_rw_intr_mask_default   0x00000000
+#define regk_iop_timer_grp_rw_tmr_cfg_default0    0x00018000
+#define regk_iop_timer_grp_rw_tmr_cfg_default1    0x0001a900
+#define regk_iop_timer_grp_rw_tmr_cfg_default2    0x0001d200
+#define regk_iop_timer_grp_rw_tmr_cfg_default3    0x0001fb00
+#define regk_iop_timer_grp_rw_tmr_cfg_size        0x00000004
+#define regk_iop_timer_grp_rw_tmr_len_default     0x00000000
+#define regk_iop_timer_grp_rw_tmr_len_size        0x00000004
+#define regk_iop_timer_grp_short_period           0x00000000
+#define regk_iop_timer_grp_stop                   0x00000000
+#define regk_iop_timer_grp_tmr                    0x00000004
+#define regk_iop_timer_grp_toggle                 0x00000001
+#define regk_iop_timer_grp_yes                    0x00000001
+#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
new file mode 100644
index 000000000000..1005d9db80dc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
@@ -0,0 +1,157 @@
+#ifndef __iop_trigger_grp_defs_asm_h
+#define __iop_trigger_grp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *      id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_trigger_grp_rw_cfg 4
+/* Register rw_cfg, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
+#define reg_iop_trigger_grp_rw_cfg___action___width 2
+#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
+#define reg_iop_trigger_grp_rw_cfg___once___width 1
+#define reg_iop_trigger_grp_rw_cfg___once___bit 2
+#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
+#define reg_iop_trigger_grp_rw_cfg___trig___width 3
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
+#define reg_iop_trigger_grp_rw_cfg_offset 0
+
+/* Register rw_cmd, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
+#define reg_iop_trigger_grp_rw_cmd___dis___width 4
+#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
+#define reg_iop_trigger_grp_rw_cmd___en___width 4
+#define reg_iop_trigger_grp_rw_cmd_offset 16
+
+/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
+#define reg_iop_trigger_grp_rw_intr_mask_offset 20
+
+/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
+#define reg_iop_trigger_grp_rw_ack_intr_offset 24
+
+/* Register r_intr, scope iop_trigger_grp, type r */
+#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_r_intr___trig0___width 1
+#define reg_iop_trigger_grp_r_intr___trig0___bit 0
+#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_r_intr___trig1___width 1
+#define reg_iop_trigger_grp_r_intr___trig1___bit 1
+#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_r_intr___trig2___width 1
+#define reg_iop_trigger_grp_r_intr___trig2___bit 2
+#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_r_intr___trig3___width 1
+#define reg_iop_trigger_grp_r_intr___trig3___bit 3
+#define reg_iop_trigger_grp_r_intr_offset 28
+
+/* Register r_masked_intr, scope iop_trigger_grp, type r */
+#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
+#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
+#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
+#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
+#define reg_iop_trigger_grp_r_masked_intr_offset 32
+
+
+/* Constants */
+#define regk_iop_trigger_grp_fall                 0x00000002
+#define regk_iop_trigger_grp_fall_lo              0x00000006
+#define regk_iop_trigger_grp_no                   0x00000000
+#define regk_iop_trigger_grp_off                  0x00000000
+#define regk_iop_trigger_grp_pulse                0x00000000
+#define regk_iop_trigger_grp_rise                 0x00000001
+#define regk_iop_trigger_grp_rise_fall            0x00000003
+#define regk_iop_trigger_grp_rise_fall_hi         0x00000007
+#define regk_iop_trigger_grp_rise_fall_lo         0x00000004
+#define regk_iop_trigger_grp_rise_hi              0x00000005
+#define regk_iop_trigger_grp_rw_cfg_default       0x000000c0
+#define regk_iop_trigger_grp_rw_cfg_size          0x00000004
+#define regk_iop_trigger_grp_rw_intr_mask_default  0x00000000
+#define regk_iop_trigger_grp_toggle               0x00000003
+#define regk_iop_trigger_grp_yes                  0x00000001
+#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
new file mode 100644
index 000000000000..e13feb20a7e3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
@@ -0,0 +1,64 @@
+#ifndef __iop_version_defs_asm_h
+#define __iop_version_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
+ *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
+ *     last modfied: Mon Apr 11 16:08:44 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
+ *      id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+                         STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_version, scope iop_version, type r */
+#define reg_iop_version_r_version___nr___lsb 0
+#define reg_iop_version_r_version___nr___width 8
+#define reg_iop_version_r_version_offset 0
+
+
+/* Constants */
+#define regk_iop_version_v1_0                     0x00000001
+#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
new file mode 100644
index 000000000000..90e4785b6474
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
@@ -0,0 +1,232 @@
+#ifndef __iop_crc_par_defs_h
+#define __iop_crc_par_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
+ *      id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_crc_par */
+
+/* Register rw_cfg, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int mode    : 1;
+  unsigned int crc_out : 1;
+  unsigned int rev_out : 1;
+  unsigned int inv_out : 1;
+  unsigned int trig    : 2;
+  unsigned int poly    : 3;
+  unsigned int dummy1  : 23;
+} reg_iop_crc_par_rw_cfg;
+#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
+#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
+
+/* Register rw_init_crc, scope iop_crc_par, type rw */
+typedef unsigned int reg_iop_crc_par_rw_init_crc;
+#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
+#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
+
+/* Register rw_correct_crc, scope iop_crc_par, type rw */
+typedef unsigned int reg_iop_crc_par_rw_correct_crc;
+#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
+#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
+
+/* Register rw_ctrl, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_crc_par_rw_ctrl;
+#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
+#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
+
+/* Register rw_set_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int tr_dif : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_crc_par_rw_set_last;
+#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
+#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
+
+/* Register rw_wr1byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_crc_par_rw_wr1byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
+#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
+
+/* Register rw_wr2byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_crc_par_rw_wr2byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
+#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
+
+/* Register rw_wr3byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_crc_par_rw_wr3byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
+#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
+
+/* Register rw_wr4byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_crc_par_rw_wr4byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
+#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
+
+/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_crc_par_rw_wr1byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
+#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
+
+/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_crc_par_rw_wr2byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
+#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
+
+/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_crc_par_rw_wr3byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
+#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
+
+/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_crc_par_rw_wr4byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
+#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
+
+/* Register r_stat, scope iop_crc_par, type r */
+typedef struct {
+  unsigned int err  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 30;
+} reg_iop_crc_par_r_stat;
+#define REG_RD_ADDR_iop_crc_par_r_stat 52
+
+/* Register r_sh_reg, scope iop_crc_par, type r */
+typedef unsigned int reg_iop_crc_par_r_sh_reg;
+#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
+
+/* Register r_crc, scope iop_crc_par, type r */
+typedef unsigned int reg_iop_crc_par_r_crc;
+#define REG_RD_ADDR_iop_crc_par_r_crc 60
+
+/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_crc_par_rw_strb_rec_dif_in;
+#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
+#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
+
+
+/* Constants */
+enum {
+  regk_iop_crc_par_calc                    = 0x00000001,
+  regk_iop_crc_par_ccitt                   = 0x00000002,
+  regk_iop_crc_par_check                   = 0x00000000,
+  regk_iop_crc_par_crc16                   = 0x00000001,
+  regk_iop_crc_par_crc32                   = 0x00000000,
+  regk_iop_crc_par_crc5                    = 0x00000003,
+  regk_iop_crc_par_crc5_11                 = 0x00000004,
+  regk_iop_crc_par_dif_in                  = 0x00000002,
+  regk_iop_crc_par_hi                      = 0x00000000,
+  regk_iop_crc_par_neg                     = 0x00000002,
+  regk_iop_crc_par_no                      = 0x00000000,
+  regk_iop_crc_par_pos                     = 0x00000001,
+  regk_iop_crc_par_pos_neg                 = 0x00000003,
+  regk_iop_crc_par_rw_cfg_default          = 0x00000000,
+  regk_iop_crc_par_rw_ctrl_default         = 0x00000000,
+  regk_iop_crc_par_yes                     = 0x00000001
+};
+#endif /* __iop_crc_par_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
new file mode 100644
index 000000000000..76aec6e37f3e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
@@ -0,0 +1,325 @@
+#ifndef __iop_dmc_in_defs_h
+#define __iop_dmc_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
+ *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
+ *      id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_dmc_in */
+
+/* Register rw_cfg, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int sth_intr     : 3;
+  unsigned int last_dis_dif : 1;
+  unsigned int dummy1       : 28;
+} reg_iop_dmc_in_rw_cfg;
+#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
+#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dif_en     : 1;
+  unsigned int dif_dis    : 1;
+  unsigned int stream_clr : 1;
+  unsigned int dummy1     : 29;
+} reg_iop_dmc_in_rw_ctrl;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int dif_en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_dmc_in_r_stat;
+#define REG_RD_ADDR_iop_dmc_in_r_stat 8
+
+/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int cmd : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n   : 8;
+  unsigned int dummy2 : 8;
+} reg_iop_dmc_in_rw_stream_cmd;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
+
+/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
+
+/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
+
+/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int eop     : 1;
+  unsigned int wait    : 1;
+  unsigned int keep_md : 1;
+  unsigned int size    : 3;
+  unsigned int dummy1  : 26;
+} reg_iop_dmc_in_rw_stream_ctrl;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
+
+/* Register r_stream_stat, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int sth            : 7;
+  unsigned int dummy1         : 9;
+  unsigned int full           : 1;
+  unsigned int last_pkt       : 1;
+  unsigned int data_md_valid  : 1;
+  unsigned int ctxt_md_valid  : 1;
+  unsigned int group_md_valid : 1;
+  unsigned int stream_busy    : 1;
+  unsigned int cmd_rdy        : 1;
+  unsigned int dummy2         : 9;
+} reg_iop_dmc_in_r_stream_stat;
+#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
+
+/* Register r_data_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_in_r_data_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
+
+/* Register r_ctxt_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md0  : 16;
+} reg_iop_dmc_in_r_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
+typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
+typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
+
+/* Register r_group_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_in_r_group_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
+
+/* Register rw_data_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_in_rw_data_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
+#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
+
+/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md0 : 16;
+} reg_iop_dmc_in_rw_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
+
+/* Register rw_group_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_in_rw_group_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
+#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
+
+/* Register rw_intr_mask, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_rw_intr_mask;
+#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
+#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
+
+/* Register rw_ack_intr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_rw_ack_intr;
+#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
+#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
+
+/* Register r_intr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_r_intr;
+#define REG_RD_ADDR_iop_dmc_in_r_intr 96
+
+/* Register r_masked_intr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_r_masked_intr;
+#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
+
+
+/* Constants */
+enum {
+  regk_iop_dmc_in_ack_pkt                  = 0x00000100,
+  regk_iop_dmc_in_array                    = 0x00000008,
+  regk_iop_dmc_in_burst                    = 0x00000020,
+  regk_iop_dmc_in_copy_next                = 0x00000010,
+  regk_iop_dmc_in_copy_up                  = 0x00000020,
+  regk_iop_dmc_in_dis_c                    = 0x00000010,
+  regk_iop_dmc_in_dis_g                    = 0x00000020,
+  regk_iop_dmc_in_lim1                     = 0x00000000,
+  regk_iop_dmc_in_lim16                    = 0x00000004,
+  regk_iop_dmc_in_lim2                     = 0x00000001,
+  regk_iop_dmc_in_lim32                    = 0x00000005,
+  regk_iop_dmc_in_lim4                     = 0x00000002,
+  regk_iop_dmc_in_lim64                    = 0x00000006,
+  regk_iop_dmc_in_lim8                     = 0x00000003,
+  regk_iop_dmc_in_load_c                   = 0x00000200,
+  regk_iop_dmc_in_load_c_n                 = 0x00000280,
+  regk_iop_dmc_in_load_c_next              = 0x00000240,
+  regk_iop_dmc_in_load_d                   = 0x00000140,
+  regk_iop_dmc_in_load_g                   = 0x00000300,
+  regk_iop_dmc_in_load_g_down              = 0x000003c0,
+  regk_iop_dmc_in_load_g_next              = 0x00000340,
+  regk_iop_dmc_in_load_g_up                = 0x00000380,
+  regk_iop_dmc_in_next_en                  = 0x00000010,
+  regk_iop_dmc_in_next_pkt                 = 0x00000010,
+  regk_iop_dmc_in_no                       = 0x00000000,
+  regk_iop_dmc_in_restore                  = 0x00000020,
+  regk_iop_dmc_in_rw_cfg_default           = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_default    = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
+  regk_iop_dmc_in_rw_data_descr_default    = 0x00000000,
+  regk_iop_dmc_in_rw_group_descr_default   = 0x00000000,
+  regk_iop_dmc_in_rw_intr_mask_default     = 0x00000000,
+  regk_iop_dmc_in_rw_stream_ctrl_default   = 0x00000000,
+  regk_iop_dmc_in_save_down                = 0x00000020,
+  regk_iop_dmc_in_save_up                  = 0x00000020,
+  regk_iop_dmc_in_set_reg                  = 0x00000050,
+  regk_iop_dmc_in_set_w_size1              = 0x00000190,
+  regk_iop_dmc_in_set_w_size2              = 0x000001a0,
+  regk_iop_dmc_in_set_w_size4              = 0x000001c0,
+  regk_iop_dmc_in_store_c                  = 0x00000002,
+  regk_iop_dmc_in_store_descr              = 0x00000000,
+  regk_iop_dmc_in_store_g                  = 0x00000004,
+  regk_iop_dmc_in_store_md                 = 0x00000001,
+  regk_iop_dmc_in_update_down              = 0x00000020,
+  regk_iop_dmc_in_yes                      = 0x00000001
+};
+#endif /* __iop_dmc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
new file mode 100644
index 000000000000..938a0d4c4604
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
@@ -0,0 +1,326 @@
+#ifndef __iop_dmc_out_defs_h
+#define __iop_dmc_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
+ *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
+ *      id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_dmc_out */
+
+/* Register rw_cfg, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int trf_lim         : 16;
+  unsigned int last_at_trf_lim : 1;
+  unsigned int dth_intr        : 3;
+  unsigned int dummy1          : 12;
+} reg_iop_dmc_out_rw_cfg;
+#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
+#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dif_en  : 1;
+  unsigned int dif_dis : 1;
+  unsigned int dummy1  : 30;
+} reg_iop_dmc_out_rw_ctrl;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
+
+/* Register r_stat, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int dif_en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_dmc_out_r_stat;
+#define REG_RD_ADDR_iop_dmc_out_r_stat 8
+
+/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int cmd : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n   : 8;
+  unsigned int dummy2 : 8;
+} reg_iop_dmc_out_rw_stream_cmd;
+#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
+#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
+
+/* Register rs_stream_data, scope iop_dmc_out, type rs */
+typedef unsigned int reg_iop_dmc_out_rs_stream_data;
+#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
+
+/* Register r_stream_data, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_stream_data;
+#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
+
+/* Register r_stream_stat, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int dth            : 7;
+  unsigned int dummy1         : 9;
+  unsigned int dv             : 1;
+  unsigned int all_avail      : 1;
+  unsigned int last           : 1;
+  unsigned int size           : 3;
+  unsigned int data_md_valid  : 1;
+  unsigned int ctxt_md_valid  : 1;
+  unsigned int group_md_valid : 1;
+  unsigned int stream_busy    : 1;
+  unsigned int cmd_rdy        : 1;
+  unsigned int cmd_rq         : 1;
+  unsigned int dummy2         : 4;
+} reg_iop_dmc_out_r_stream_stat;
+#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
+
+/* Register r_data_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_out_r_data_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
+
+/* Register r_ctxt_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md0  : 16;
+} reg_iop_dmc_out_r_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
+
+/* Register r_group_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_out_r_group_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
+
+/* Register rw_data_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_out_rw_data_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
+#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
+
+/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md0 : 16;
+} reg_iop_dmc_out_rw_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
+typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
+typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
+
+/* Register rw_group_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_out_rw_group_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
+#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
+
+/* Register rw_intr_mask, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_rw_intr_mask;
+#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
+#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
+
+/* Register rw_ack_intr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_rw_ack_intr;
+#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
+#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
+
+/* Register r_intr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_r_intr;
+#define REG_RD_ADDR_iop_dmc_out_r_intr 92
+
+/* Register r_masked_intr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_r_masked_intr;
+#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
+
+
+/* Constants */
+enum {
+  regk_iop_dmc_out_ack_pkt                 = 0x00000100,
+  regk_iop_dmc_out_array                   = 0x00000008,
+  regk_iop_dmc_out_burst                   = 0x00000020,
+  regk_iop_dmc_out_copy_next               = 0x00000010,
+  regk_iop_dmc_out_copy_up                 = 0x00000020,
+  regk_iop_dmc_out_dis_c                   = 0x00000010,
+  regk_iop_dmc_out_dis_g                   = 0x00000020,
+  regk_iop_dmc_out_lim1                    = 0x00000000,
+  regk_iop_dmc_out_lim16                   = 0x00000004,
+  regk_iop_dmc_out_lim2                    = 0x00000001,
+  regk_iop_dmc_out_lim32                   = 0x00000005,
+  regk_iop_dmc_out_lim4                    = 0x00000002,
+  regk_iop_dmc_out_lim64                   = 0x00000006,
+  regk_iop_dmc_out_lim8                    = 0x00000003,
+  regk_iop_dmc_out_load_c                  = 0x00000200,
+  regk_iop_dmc_out_load_c_n                = 0x00000280,
+  regk_iop_dmc_out_load_c_next             = 0x00000240,
+  regk_iop_dmc_out_load_d                  = 0x00000140,
+  regk_iop_dmc_out_load_g                  = 0x00000300,
+  regk_iop_dmc_out_load_g_down             = 0x000003c0,
+  regk_iop_dmc_out_load_g_next             = 0x00000340,
+  regk_iop_dmc_out_load_g_up               = 0x00000380,
+  regk_iop_dmc_out_next_en                 = 0x00000010,
+  regk_iop_dmc_out_next_pkt                = 0x00000010,
+  regk_iop_dmc_out_no                      = 0x00000000,
+  regk_iop_dmc_out_restore                 = 0x00000020,
+  regk_iop_dmc_out_rw_cfg_default          = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_default   = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
+  regk_iop_dmc_out_rw_data_descr_default   = 0x00000000,
+  regk_iop_dmc_out_rw_group_descr_default  = 0x00000000,
+  regk_iop_dmc_out_rw_intr_mask_default    = 0x00000000,
+  regk_iop_dmc_out_save_down               = 0x00000020,
+  regk_iop_dmc_out_save_up                 = 0x00000020,
+  regk_iop_dmc_out_set_reg                 = 0x00000050,
+  regk_iop_dmc_out_set_w_size1             = 0x00000190,
+  regk_iop_dmc_out_set_w_size2             = 0x000001a0,
+  regk_iop_dmc_out_set_w_size4             = 0x000001c0,
+  regk_iop_dmc_out_store_c                 = 0x00000002,
+  regk_iop_dmc_out_store_descr             = 0x00000000,
+  regk_iop_dmc_out_store_g                 = 0x00000004,
+  regk_iop_dmc_out_store_md                = 0x00000001,
+  regk_iop_dmc_out_update_down             = 0x00000020,
+  regk_iop_dmc_out_yes                     = 0x00000001
+};
+#endif /* __iop_dmc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
new file mode 100644
index 000000000000..e0c982b263fa
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
@@ -0,0 +1,255 @@
+#ifndef __iop_fifo_in_defs_h
+#define __iop_fifo_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:07 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
+ *      id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_in */
+
+/* Register rw_cfg, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int avail_lim       : 3;
+  unsigned int byte_order      : 2;
+  unsigned int trig            : 2;
+  unsigned int last_dis_dif_in : 1;
+  unsigned int mode            : 2;
+  unsigned int dummy1          : 22;
+} reg_iop_fifo_in_rw_cfg;
+#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
+#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int dif_in_en  : 1;
+  unsigned int dif_out_en : 1;
+  unsigned int dummy1     : 30;
+} reg_iop_fifo_in_rw_ctrl;
+#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int avail_bytes : 4;
+  unsigned int last        : 8;
+  unsigned int dif_in_en   : 1;
+  unsigned int dif_out_en  : 1;
+  unsigned int dummy1      : 18;
+} reg_iop_fifo_in_r_stat;
+#define REG_RD_ADDR_iop_fifo_in_r_stat 8
+
+/* Register rs_rd1byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_in_rs_rd1byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
+
+/* Register r_rd1byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_in_r_rd1byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
+
+/* Register rs_rd2byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_in_rs_rd2byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
+
+/* Register r_rd2byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_in_r_rd2byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
+
+/* Register rs_rd3byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_in_rs_rd3byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
+
+/* Register r_rd3byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_in_r_rd3byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
+
+/* Register rs_rd4byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_in_rs_rd4byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
+
+/* Register r_rd4byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_in_r_rd4byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
+
+/* Register rw_set_last, scope iop_fifo_in, type rw */
+typedef unsigned int reg_iop_fifo_in_rw_set_last;
+#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
+#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
+
+/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_fifo_in_rw_strb_dif_in;
+#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
+#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
+
+/* Register rw_intr_mask, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
+#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
+
+/* Register rw_ack_intr, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
+#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
+
+/* Register r_intr, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_r_intr;
+#define REG_RD_ADDR_iop_fifo_in_r_intr 60
+
+/* Register r_masked_intr, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_in_dif_in                  = 0x00000002,
+  regk_iop_fifo_in_hi                      = 0x00000000,
+  regk_iop_fifo_in_neg                     = 0x00000002,
+  regk_iop_fifo_in_no                      = 0x00000000,
+  regk_iop_fifo_in_order16                 = 0x00000001,
+  regk_iop_fifo_in_order24                 = 0x00000002,
+  regk_iop_fifo_in_order32                 = 0x00000003,
+  regk_iop_fifo_in_order8                  = 0x00000000,
+  regk_iop_fifo_in_pos                     = 0x00000001,
+  regk_iop_fifo_in_pos_neg                 = 0x00000003,
+  regk_iop_fifo_in_rw_cfg_default          = 0x00000024,
+  regk_iop_fifo_in_rw_ctrl_default         = 0x00000000,
+  regk_iop_fifo_in_rw_intr_mask_default    = 0x00000000,
+  regk_iop_fifo_in_rw_set_last_default     = 0x00000000,
+  regk_iop_fifo_in_rw_strb_dif_in_default  = 0x00000000,
+  regk_iop_fifo_in_size16                  = 0x00000002,
+  regk_iop_fifo_in_size24                  = 0x00000001,
+  regk_iop_fifo_in_size32                  = 0x00000000,
+  regk_iop_fifo_in_size8                   = 0x00000003,
+  regk_iop_fifo_in_yes                     = 0x00000001
+};
+#endif /* __iop_fifo_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
new file mode 100644
index 000000000000..798ac95870e9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
@@ -0,0 +1,164 @@
+#ifndef __iop_fifo_in_extra_defs_h
+#define __iop_fifo_in_extra_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:08 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *      id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_in_extra */
+
+/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
+typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
+
+/* Register r_stat, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int avail_bytes : 4;
+  unsigned int last        : 8;
+  unsigned int dif_in_en   : 1;
+  unsigned int dif_out_en  : 1;
+  unsigned int dummy1      : 18;
+} reg_iop_fifo_in_extra_r_stat;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
+
+/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_fifo_in_extra_rw_strb_dif_in;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
+
+/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
+
+/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
+
+/* Register r_intr, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_r_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
+
+/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_in_extra_fifo_in           = 0x00000002,
+  regk_iop_fifo_in_extra_no                = 0x00000000,
+  regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
+  regk_iop_fifo_in_extra_yes               = 0x00000001
+};
+#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
new file mode 100644
index 000000000000..833e10f02526
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
@@ -0,0 +1,278 @@
+#ifndef __iop_fifo_out_defs_h
+#define __iop_fifo_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:09 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
+ *      id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_out */
+
+/* Register rw_cfg, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int free_lim         : 3;
+  unsigned int byte_order       : 2;
+  unsigned int trig             : 2;
+  unsigned int last_dis_dif_in  : 1;
+  unsigned int mode             : 2;
+  unsigned int delay_out_last   : 1;
+  unsigned int last_dis_dif_out : 1;
+  unsigned int dummy1           : 20;
+} reg_iop_fifo_out_rw_cfg;
+#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
+#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int dif_in_en  : 1;
+  unsigned int dif_out_en : 1;
+  unsigned int dummy1     : 30;
+} reg_iop_fifo_out_rw_ctrl;
+#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
+
+/* Register r_stat, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int avail_bytes    : 4;
+  unsigned int last           : 8;
+  unsigned int dif_in_en      : 1;
+  unsigned int dif_out_en     : 1;
+  unsigned int zero_data_last : 1;
+  unsigned int dummy1         : 17;
+} reg_iop_fifo_out_r_stat;
+#define REG_RD_ADDR_iop_fifo_out_r_stat 8
+
+/* Register rw_wr1byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_out_rw_wr1byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
+#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
+
+/* Register rw_wr2byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_out_rw_wr2byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
+#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
+
+/* Register rw_wr3byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_out_rw_wr3byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
+#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
+
+/* Register rw_wr4byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_out_rw_wr4byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
+#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
+
+/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_out_rw_wr1byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
+#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
+
+/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_out_rw_wr2byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
+#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
+
+/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_out_rw_wr3byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
+#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
+
+/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_out_rw_wr4byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
+#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
+
+/* Register rw_set_last, scope iop_fifo_out, type rw */
+typedef unsigned int reg_iop_fifo_out_rw_set_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
+#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
+
+/* Register rs_rd_data, scope iop_fifo_out, type rs */
+typedef unsigned int reg_iop_fifo_out_rs_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
+
+/* Register r_rd_data, scope iop_fifo_out, type r */
+typedef unsigned int reg_iop_fifo_out_r_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
+
+/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
+typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
+#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
+#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
+
+/* Register rw_intr_mask, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
+#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
+
+/* Register rw_ack_intr, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
+#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
+
+/* Register r_intr, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_r_intr;
+#define REG_RD_ADDR_iop_fifo_out_r_intr 68
+
+/* Register r_masked_intr, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_out_hi                     = 0x00000000,
+  regk_iop_fifo_out_neg                    = 0x00000002,
+  regk_iop_fifo_out_no                     = 0x00000000,
+  regk_iop_fifo_out_order16                = 0x00000001,
+  regk_iop_fifo_out_order24                = 0x00000002,
+  regk_iop_fifo_out_order32                = 0x00000003,
+  regk_iop_fifo_out_order8                 = 0x00000000,
+  regk_iop_fifo_out_pos                    = 0x00000001,
+  regk_iop_fifo_out_pos_neg                = 0x00000003,
+  regk_iop_fifo_out_rw_cfg_default         = 0x00000024,
+  regk_iop_fifo_out_rw_ctrl_default        = 0x00000000,
+  regk_iop_fifo_out_rw_intr_mask_default   = 0x00000000,
+  regk_iop_fifo_out_rw_set_last_default    = 0x00000000,
+  regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr1byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr2byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr3byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr4byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
+  regk_iop_fifo_out_size16                 = 0x00000002,
+  regk_iop_fifo_out_size24                 = 0x00000001,
+  regk_iop_fifo_out_size32                 = 0x00000000,
+  regk_iop_fifo_out_size8                  = 0x00000003,
+  regk_iop_fifo_out_yes                    = 0x00000001
+};
+#endif /* __iop_fifo_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
new file mode 100644
index 000000000000..4a840aae84ee
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
@@ -0,0 +1,164 @@
+#ifndef __iop_fifo_out_extra_defs_h
+#define __iop_fifo_out_extra_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:10 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *      id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_out_extra */
+
+/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
+typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
+
+/* Register r_rd_data, scope iop_fifo_out_extra, type r */
+typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
+
+/* Register r_stat, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int avail_bytes    : 4;
+  unsigned int last           : 8;
+  unsigned int dif_in_en      : 1;
+  unsigned int dif_out_en     : 1;
+  unsigned int zero_data_last : 1;
+  unsigned int dummy1         : 17;
+} reg_iop_fifo_out_extra_r_stat;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
+
+/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
+typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
+
+/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
+
+/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
+
+/* Register r_intr, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_r_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
+
+/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_out_extra_no               = 0x00000000,
+  regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
+  regk_iop_fifo_out_extra_yes              = 0x00000001
+};
+#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
new file mode 100644
index 000000000000..c2b0ba1be60f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
@@ -0,0 +1,190 @@
+#ifndef __iop_mpu_defs_h
+#define __iop_mpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_mpu.r
+ *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
+ *      id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_mpu */
+
+#define STRIDE_iop_mpu_rw_r 4
+/* Register rw_r, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_r;
+#define REG_RD_ADDR_iop_mpu_rw_r 0
+#define REG_WR_ADDR_iop_mpu_rw_r 0
+
+/* Register rw_ctrl, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_mpu_rw_ctrl;
+#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
+#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
+
+/* Register r_pc, scope iop_mpu, type r */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_r_pc;
+#define REG_RD_ADDR_iop_mpu_r_pc 132
+
+/* Register r_stat, scope iop_mpu, type r */
+typedef struct {
+  unsigned int instr_reg_busy : 1;
+  unsigned int intr_busy      : 1;
+  unsigned int intr_vect      : 16;
+  unsigned int dummy1         : 14;
+} reg_iop_mpu_r_stat;
+#define REG_RD_ADDR_iop_mpu_r_stat 136
+
+/* Register rw_instr, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_instr;
+#define REG_RD_ADDR_iop_mpu_rw_instr 140
+#define REG_WR_ADDR_iop_mpu_rw_instr 140
+
+/* Register rw_immediate, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_immediate;
+#define REG_RD_ADDR_iop_mpu_rw_immediate 144
+#define REG_WR_ADDR_iop_mpu_rw_immediate 144
+
+/* Register r_trace, scope iop_mpu, type r */
+typedef struct {
+  unsigned int intr_vect      : 16;
+  unsigned int pc             : 12;
+  unsigned int en             : 1;
+  unsigned int instr_reg_busy : 1;
+  unsigned int intr_busy      : 1;
+  unsigned int dummy1         : 1;
+} reg_iop_mpu_r_trace;
+#define REG_RD_ADDR_iop_mpu_r_trace 148
+
+/* Register r_wr_stat, scope iop_mpu, type r */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_mpu_r_wr_stat;
+#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
+
+#define STRIDE_iop_mpu_rw_thread 4
+/* Register rw_thread, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_rw_thread;
+#define REG_RD_ADDR_iop_mpu_rw_thread 156
+#define REG_WR_ADDR_iop_mpu_rw_thread 156
+
+#define STRIDE_iop_mpu_rw_intr 4
+/* Register rw_intr, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_rw_intr;
+#define REG_RD_ADDR_iop_mpu_rw_intr 196
+#define REG_WR_ADDR_iop_mpu_rw_intr 196
+
+
+/* Constants */
+enum {
+  regk_iop_mpu_no                          = 0x00000000,
+  regk_iop_mpu_r_pc_default                = 0x00000000,
+  regk_iop_mpu_rw_ctrl_default             = 0x00000000,
+  regk_iop_mpu_rw_intr_size                = 0x00000010,
+  regk_iop_mpu_rw_r_size                   = 0x00000010,
+  regk_iop_mpu_rw_thread_default           = 0x00000000,
+  regk_iop_mpu_rw_thread_size              = 0x00000004,
+  regk_iop_mpu_yes                         = 0x00000001
+};
+#endif /* __iop_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
new file mode 100644
index 000000000000..2ec897ced166
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
@@ -0,0 +1,764 @@
+/* ************************************************************************* */
+/* This file is autogenerated by IOPASM Version 1.2                          */
+/* DO NOT EDIT THIS FILE - All changes will be lost!                         */
+/* ************************************************************************* */
+
+
+
+#ifndef __IOP_MPU_MACROS_H__
+#define __IOP_MPU_MACROS_H__
+
+
+/* ************************************************************************* */
+/*                           REGISTER DEFINITIONS                            */
+/* ************************************************************************* */
+#define MPU_R0 (0x0)
+#define MPU_R1 (0x1)
+#define MPU_R2 (0x2)
+#define MPU_R3 (0x3)
+#define MPU_R4 (0x4)
+#define MPU_R5 (0x5)
+#define MPU_R6 (0x6)
+#define MPU_R7 (0x7)
+#define MPU_R8 (0x8)
+#define MPU_R9 (0x9)
+#define MPU_R10 (0xa)
+#define MPU_R11 (0xb)
+#define MPU_R12 (0xc)
+#define MPU_R13 (0xd)
+#define MPU_R14 (0xe)
+#define MPU_R15 (0xf)
+#define MPU_PC (0x2)
+#define MPU_WSTS (0x3)
+#define MPU_JADDR (0x4)
+#define MPU_IRP (0x5)
+#define MPU_SRP (0x6)
+#define MPU_T0 (0x8)
+#define MPU_T1 (0x9)
+#define MPU_T2 (0xa)
+#define MPU_T3 (0xb)
+#define MPU_I0 (0x10)
+#define MPU_I1 (0x11)
+#define MPU_I2 (0x12)
+#define MPU_I3 (0x13)
+#define MPU_I4 (0x14)
+#define MPU_I5 (0x15)
+#define MPU_I6 (0x16)
+#define MPU_I7 (0x17)
+#define MPU_I8 (0x18)
+#define MPU_I9 (0x19)
+#define MPU_I10 (0x1a)
+#define MPU_I11 (0x1b)
+#define MPU_I12 (0x1c)
+#define MPU_I13 (0x1d)
+#define MPU_I14 (0x1e)
+#define MPU_I15 (0x1f)
+#define MPU_P2 (0x2)
+#define MPU_P3 (0x3)
+#define MPU_P5 (0x5)
+#define MPU_P6 (0x6)
+#define MPU_P8 (0x8)
+#define MPU_P9 (0x9)
+#define MPU_P10 (0xa)
+#define MPU_P11 (0xb)
+#define MPU_P16 (0x10)
+#define MPU_P17 (0x12)
+#define MPU_P18 (0x12)
+#define MPU_P19 (0x13)
+#define MPU_P20 (0x14)
+#define MPU_P21 (0x15)
+#define MPU_P22 (0x16)
+#define MPU_P23 (0x17)
+#define MPU_P24 (0x18)
+#define MPU_P25 (0x19)
+#define MPU_P26 (0x1a)
+#define MPU_P27 (0x1b)
+#define MPU_P28 (0x1c)
+#define MPU_P29 (0x1d)
+#define MPU_P30 (0x1e)
+#define MPU_P31 (0x1f)
+#define MPU_P1 (0x1)
+#define MPU_REGA (0x1)
+
+
+
+/* ************************************************************************* */
+/*                              ADDRESS MACROS                               */
+/* ************************************************************************* */
+#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
+#define MK_BYTE_ADDR(ADDR) (ADDR)
+
+
+
+/* ************************************************************************* */
+/*                            INSTRUCTION MACROS                             */
+/* ************************************************************************* */
+#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 21)\
+                                | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 21)\
+                                | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_DI() (0x40000001)
+
+#define MPU_EI() (0x40000003)
+
+#define MPU_HALT() (0x40000002)
+
+#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JNT() (0x61000000)
+
+#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_NOP() (0x40000000)
+
+#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 16) - 1)) << 0)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                | ((N & ((1 << 5) - 1)) << 16)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_RET() (0x63003000)
+
+#define MPU_RETI() (0x63602800)
+
+#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
+                             | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
+                             | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
+                                      | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
+                                      | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+
+#endif /* end of __IOP_MPU_MACROS_H__ */
+/* End of iop_mpu_macros.h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
new file mode 100644
index 000000000000..756550f5d6cb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
@@ -0,0 +1,44 @@
+/* Autogenerated Changes here will be lost!
+ * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
+ */
+#define regi_iop_version (regi_iop + 0)
+#define regi_iop_fifo_in0_extra (regi_iop + 64)
+#define regi_iop_fifo_in1_extra (regi_iop + 128)
+#define regi_iop_fifo_out0_extra (regi_iop + 192)
+#define regi_iop_fifo_out1_extra (regi_iop + 256)
+#define regi_iop_trigger_grp0 (regi_iop + 320)
+#define regi_iop_trigger_grp1 (regi_iop + 384)
+#define regi_iop_trigger_grp2 (regi_iop + 448)
+#define regi_iop_trigger_grp3 (regi_iop + 512)
+#define regi_iop_trigger_grp4 (regi_iop + 576)
+#define regi_iop_trigger_grp5 (regi_iop + 640)
+#define regi_iop_trigger_grp6 (regi_iop + 704)
+#define regi_iop_trigger_grp7 (regi_iop + 768)
+#define regi_iop_crc_par0 (regi_iop + 896)
+#define regi_iop_crc_par1 (regi_iop + 1024)
+#define regi_iop_dmc_in0 (regi_iop + 1152)
+#define regi_iop_dmc_in1 (regi_iop + 1280)
+#define regi_iop_dmc_out0 (regi_iop + 1408)
+#define regi_iop_dmc_out1 (regi_iop + 1536)
+#define regi_iop_fifo_in0 (regi_iop + 1664)
+#define regi_iop_fifo_in1 (regi_iop + 1792)
+#define regi_iop_fifo_out0 (regi_iop + 1920)
+#define regi_iop_fifo_out1 (regi_iop + 2048)
+#define regi_iop_scrc_in0 (regi_iop + 2176)
+#define regi_iop_scrc_in1 (regi_iop + 2304)
+#define regi_iop_scrc_out0 (regi_iop + 2432)
+#define regi_iop_scrc_out1 (regi_iop + 2560)
+#define regi_iop_timer_grp0 (regi_iop + 2688)
+#define regi_iop_timer_grp1 (regi_iop + 2816)
+#define regi_iop_timer_grp2 (regi_iop + 2944)
+#define regi_iop_timer_grp3 (regi_iop + 3072)
+#define regi_iop_sap_in (regi_iop + 3328)
+#define regi_iop_sap_out (regi_iop + 3584)
+#define regi_iop_spu0 (regi_iop + 3840)
+#define regi_iop_spu1 (regi_iop + 4096)
+#define regi_iop_sw_cfg (regi_iop + 4352)
+#define regi_iop_sw_cpu (regi_iop + 4608)
+#define regi_iop_sw_mpu (regi_iop + 4864)
+#define regi_iop_sw_spu0 (regi_iop + 5120)
+#define regi_iop_sw_spu1 (regi_iop + 5376)
+#define regi_iop_mpu (regi_iop + 5632)
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
new file mode 100644
index 000000000000..5548ac10074f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
@@ -0,0 +1,179 @@
+#ifndef __iop_sap_in_defs_h
+#define __iop_sap_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
+ *      id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_in */
+
+/* Register rw_bus0_sync, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int byte0_sel     : 2;
+  unsigned int byte0_ext_src : 3;
+  unsigned int byte0_edge    : 2;
+  unsigned int byte0_delay   : 1;
+  unsigned int byte1_sel     : 2;
+  unsigned int byte1_ext_src : 3;
+  unsigned int byte1_edge    : 2;
+  unsigned int byte1_delay   : 1;
+  unsigned int byte2_sel     : 2;
+  unsigned int byte2_ext_src : 3;
+  unsigned int byte2_edge    : 2;
+  unsigned int byte2_delay   : 1;
+  unsigned int byte3_sel     : 2;
+  unsigned int byte3_ext_src : 3;
+  unsigned int byte3_edge    : 2;
+  unsigned int byte3_delay   : 1;
+} reg_iop_sap_in_rw_bus0_sync;
+#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
+#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
+
+/* Register rw_bus1_sync, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int byte0_sel     : 2;
+  unsigned int byte0_ext_src : 3;
+  unsigned int byte0_edge    : 2;
+  unsigned int byte0_delay   : 1;
+  unsigned int byte1_sel     : 2;
+  unsigned int byte1_ext_src : 3;
+  unsigned int byte1_edge    : 2;
+  unsigned int byte1_delay   : 1;
+  unsigned int byte2_sel     : 2;
+  unsigned int byte2_ext_src : 3;
+  unsigned int byte2_edge    : 2;
+  unsigned int byte2_delay   : 1;
+  unsigned int byte3_sel     : 2;
+  unsigned int byte3_ext_src : 3;
+  unsigned int byte3_edge    : 2;
+  unsigned int byte3_delay   : 1;
+} reg_iop_sap_in_rw_bus1_sync;
+#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
+#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int sync_sel     : 2;
+  unsigned int sync_ext_src : 3;
+  unsigned int sync_edge    : 2;
+  unsigned int delay        : 1;
+  unsigned int logic        : 2;
+  unsigned int dummy1       : 22;
+} reg_iop_sap_in_rw_gio;
+#define REG_RD_ADDR_iop_sap_in_rw_gio 8
+#define REG_WR_ADDR_iop_sap_in_rw_gio 8
+
+
+/* Constants */
+enum {
+  regk_iop_sap_in_and                      = 0x00000002,
+  regk_iop_sap_in_ext_clk200               = 0x00000003,
+  regk_iop_sap_in_gio1                     = 0x00000000,
+  regk_iop_sap_in_gio13                    = 0x00000005,
+  regk_iop_sap_in_gio18                    = 0x00000003,
+  regk_iop_sap_in_gio19                    = 0x00000004,
+  regk_iop_sap_in_gio21                    = 0x00000006,
+  regk_iop_sap_in_gio23                    = 0x00000005,
+  regk_iop_sap_in_gio29                    = 0x00000007,
+  regk_iop_sap_in_gio5                     = 0x00000004,
+  regk_iop_sap_in_gio6                     = 0x00000001,
+  regk_iop_sap_in_gio7                     = 0x00000002,
+  regk_iop_sap_in_inv                      = 0x00000001,
+  regk_iop_sap_in_neg                      = 0x00000002,
+  regk_iop_sap_in_no                       = 0x00000000,
+  regk_iop_sap_in_no_del_ext_clk200        = 0x00000001,
+  regk_iop_sap_in_none                     = 0x00000000,
+  regk_iop_sap_in_or                       = 0x00000003,
+  regk_iop_sap_in_pos                      = 0x00000001,
+  regk_iop_sap_in_pos_neg                  = 0x00000003,
+  regk_iop_sap_in_rw_bus0_sync_default     = 0x02020202,
+  regk_iop_sap_in_rw_bus1_sync_default     = 0x02020202,
+  regk_iop_sap_in_rw_gio_default           = 0x00000002,
+  regk_iop_sap_in_rw_gio_size              = 0x00000020,
+  regk_iop_sap_in_timer_grp0_tmr3          = 0x00000006,
+  regk_iop_sap_in_timer_grp1_tmr3          = 0x00000004,
+  regk_iop_sap_in_timer_grp2_tmr3          = 0x00000005,
+  regk_iop_sap_in_timer_grp3_tmr3          = 0x00000007,
+  regk_iop_sap_in_tmr_clk200               = 0x00000000,
+  regk_iop_sap_in_two_clk200               = 0x00000002,
+  regk_iop_sap_in_yes                      = 0x00000001
+};
+#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
new file mode 100644
index 000000000000..273936996183
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
@@ -0,0 +1,306 @@
+#ifndef __iop_sap_out_defs_h
+#define __iop_sap_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
+ *      id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_out */
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int clk0_src       : 2;
+  unsigned int clk0_gate_src  : 2;
+  unsigned int clk0_force_src : 3;
+  unsigned int clk1_src       : 2;
+  unsigned int clk1_gate_src  : 2;
+  unsigned int clk1_force_src : 3;
+  unsigned int clk2_src       : 2;
+  unsigned int clk2_gate_src  : 2;
+  unsigned int clk2_force_src : 3;
+  unsigned int clk3_src       : 2;
+  unsigned int clk3_gate_src  : 2;
+  unsigned int clk3_force_src : 3;
+  unsigned int dummy1         : 4;
+} reg_iop_sap_out_rw_gen_gated;
+#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
+#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
+
+/* Register rw_bus0, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sap_out_rw_bus0;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
+#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
+
+/* Register rw_bus1, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sap_out_rw_bus1;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
+#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
+
+/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_clk_ext   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte0_logic     : 2;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_clk_ext   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte1_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus0_lo_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
+#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
+
+/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_clk_ext   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte2_logic     : 2;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_clk_ext   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int byte3_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus0_hi_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
+#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
+
+/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_clk_ext   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte0_logic     : 2;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_clk_ext   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte1_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus1_lo_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
+#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
+
+/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_clk_ext   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte2_logic     : 2;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_clk_ext   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int byte3_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus1_hi_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
+#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int out_clk_sel   : 3;
+  unsigned int out_clk_ext   : 4;
+  unsigned int out_gated_clk : 2;
+  unsigned int out_clk_inv   : 1;
+  unsigned int out_logic     : 1;
+  unsigned int oe_clk_sel    : 3;
+  unsigned int oe_clk_ext    : 3;
+  unsigned int oe_gated_clk  : 2;
+  unsigned int oe_clk_inv    : 1;
+  unsigned int oe_logic      : 2;
+  unsigned int dummy1        : 10;
+} reg_iop_sap_out_rw_gio;
+#define REG_RD_ADDR_iop_sap_out_rw_gio 28
+#define REG_WR_ADDR_iop_sap_out_rw_gio 28
+
+
+/* Constants */
+enum {
+  regk_iop_sap_out_and                     = 0x00000002,
+  regk_iop_sap_out_clk0                    = 0x00000000,
+  regk_iop_sap_out_clk1                    = 0x00000001,
+  regk_iop_sap_out_clk12                   = 0x00000002,
+  regk_iop_sap_out_clk2                    = 0x00000002,
+  regk_iop_sap_out_clk200                  = 0x00000001,
+  regk_iop_sap_out_clk3                    = 0x00000003,
+  regk_iop_sap_out_ext                     = 0x00000003,
+  regk_iop_sap_out_gated                   = 0x00000004,
+  regk_iop_sap_out_gio1                    = 0x00000000,
+  regk_iop_sap_out_gio13                   = 0x00000002,
+  regk_iop_sap_out_gio13_clk               = 0x0000000c,
+  regk_iop_sap_out_gio15                   = 0x00000001,
+  regk_iop_sap_out_gio18                   = 0x00000003,
+  regk_iop_sap_out_gio18_clk               = 0x0000000d,
+  regk_iop_sap_out_gio1_clk                = 0x00000008,
+  regk_iop_sap_out_gio21_clk               = 0x0000000e,
+  regk_iop_sap_out_gio23                   = 0x00000002,
+  regk_iop_sap_out_gio29_clk               = 0x0000000f,
+  regk_iop_sap_out_gio31                   = 0x00000003,
+  regk_iop_sap_out_gio5                    = 0x00000001,
+  regk_iop_sap_out_gio5_clk                = 0x00000009,
+  regk_iop_sap_out_gio6_clk                = 0x0000000a,
+  regk_iop_sap_out_gio7                    = 0x00000000,
+  regk_iop_sap_out_gio7_clk                = 0x0000000b,
+  regk_iop_sap_out_gio_in13                = 0x00000001,
+  regk_iop_sap_out_gio_in21                = 0x00000002,
+  regk_iop_sap_out_gio_in29                = 0x00000003,
+  regk_iop_sap_out_gio_in5                 = 0x00000000,
+  regk_iop_sap_out_inv                     = 0x00000001,
+  regk_iop_sap_out_nand                    = 0x00000003,
+  regk_iop_sap_out_no                      = 0x00000000,
+  regk_iop_sap_out_none                    = 0x00000000,
+  regk_iop_sap_out_rw_bus0_default         = 0x00000000,
+  regk_iop_sap_out_rw_bus0_hi_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus0_lo_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus1_default         = 0x00000000,
+  regk_iop_sap_out_rw_bus1_hi_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus1_lo_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_gen_gated_default    = 0x00000000,
+  regk_iop_sap_out_rw_gio_default          = 0x00000000,
+  regk_iop_sap_out_rw_gio_size             = 0x00000020,
+  regk_iop_sap_out_spu0_gio0               = 0x00000002,
+  regk_iop_sap_out_spu0_gio1               = 0x00000003,
+  regk_iop_sap_out_spu0_gio12              = 0x00000004,
+  regk_iop_sap_out_spu0_gio13              = 0x00000004,
+  regk_iop_sap_out_spu0_gio14              = 0x00000004,
+  regk_iop_sap_out_spu0_gio15              = 0x00000004,
+  regk_iop_sap_out_spu0_gio2               = 0x00000002,
+  regk_iop_sap_out_spu0_gio3               = 0x00000003,
+  regk_iop_sap_out_spu0_gio4               = 0x00000002,
+  regk_iop_sap_out_spu0_gio5               = 0x00000003,
+  regk_iop_sap_out_spu0_gio6               = 0x00000002,
+  regk_iop_sap_out_spu0_gio7               = 0x00000003,
+  regk_iop_sap_out_spu1_gio0               = 0x00000005,
+  regk_iop_sap_out_spu1_gio1               = 0x00000006,
+  regk_iop_sap_out_spu1_gio12              = 0x00000007,
+  regk_iop_sap_out_spu1_gio13              = 0x00000007,
+  regk_iop_sap_out_spu1_gio14              = 0x00000007,
+  regk_iop_sap_out_spu1_gio15              = 0x00000007,
+  regk_iop_sap_out_spu1_gio2               = 0x00000005,
+  regk_iop_sap_out_spu1_gio3               = 0x00000006,
+  regk_iop_sap_out_spu1_gio4               = 0x00000005,
+  regk_iop_sap_out_spu1_gio5               = 0x00000006,
+  regk_iop_sap_out_spu1_gio6               = 0x00000005,
+  regk_iop_sap_out_spu1_gio7               = 0x00000006,
+  regk_iop_sap_out_timer_grp0_tmr2         = 0x00000004,
+  regk_iop_sap_out_timer_grp1_tmr2         = 0x00000005,
+  regk_iop_sap_out_timer_grp2_tmr2         = 0x00000006,
+  regk_iop_sap_out_timer_grp3_tmr2         = 0x00000007,
+  regk_iop_sap_out_tmr                     = 0x00000005,
+  regk_iop_sap_out_yes                     = 0x00000001
+};
+#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
new file mode 100644
index 000000000000..4f0a9a81e737
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
@@ -0,0 +1,160 @@
+#ifndef __iop_scrc_in_defs_h
+#define __iop_scrc_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
+ *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
+ *      id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_scrc_in */
+
+/* Register rw_cfg, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int trig : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_scrc_in_rw_cfg;
+#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
+#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int dif_in_en : 1;
+  unsigned int dummy1    : 31;
+} reg_iop_scrc_in_rw_ctrl;
+#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_scrc_in, type r */
+typedef struct {
+  unsigned int err : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_scrc_in_r_stat;
+#define REG_RD_ADDR_iop_scrc_in_r_stat 8
+
+/* Register rw_init_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_init_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
+#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
+
+/* Register rs_computed_crc, scope iop_scrc_in, type rs */
+typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
+#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
+
+/* Register r_computed_crc, scope iop_scrc_in, type r */
+typedef unsigned int reg_iop_scrc_in_r_computed_crc;
+#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
+
+/* Register rw_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
+#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
+
+/* Register rw_correct_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
+#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
+
+/* Register rw_wr1bit, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int data : 2;
+  unsigned int last : 2;
+  unsigned int dummy1 : 28;
+} reg_iop_scrc_in_rw_wr1bit;
+#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
+#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
+
+
+/* Constants */
+enum {
+  regk_iop_scrc_in_dif_in                  = 0x00000002,
+  regk_iop_scrc_in_hi                      = 0x00000000,
+  regk_iop_scrc_in_neg                     = 0x00000002,
+  regk_iop_scrc_in_no                      = 0x00000000,
+  regk_iop_scrc_in_pos                     = 0x00000001,
+  regk_iop_scrc_in_pos_neg                 = 0x00000003,
+  regk_iop_scrc_in_r_computed_crc_default  = 0x00000000,
+  regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
+  regk_iop_scrc_in_rw_cfg_default          = 0x00000000,
+  regk_iop_scrc_in_rw_ctrl_default         = 0x00000000,
+  regk_iop_scrc_in_rw_init_crc_default     = 0x00000000,
+  regk_iop_scrc_in_set0                    = 0x00000000,
+  regk_iop_scrc_in_set1                    = 0x00000001,
+  regk_iop_scrc_in_yes                     = 0x00000001
+};
+#endif /* __iop_scrc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
new file mode 100644
index 000000000000..fd1d6ea1d484
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
@@ -0,0 +1,146 @@
+#ifndef __iop_scrc_out_defs_h
+#define __iop_scrc_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
+ *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
+ *      id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_scrc_out */
+
+/* Register rw_cfg, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int trig    : 2;
+  unsigned int inv_crc : 1;
+  unsigned int dummy1  : 29;
+} reg_iop_scrc_out_rw_cfg;
+#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
+#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int strb_src : 1;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 30;
+} reg_iop_scrc_out_rw_ctrl;
+#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
+
+/* Register rw_init_crc, scope iop_scrc_out, type rw */
+typedef unsigned int reg_iop_scrc_out_rw_init_crc;
+#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
+#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
+
+/* Register rw_crc, scope iop_scrc_out, type rw */
+typedef unsigned int reg_iop_scrc_out_rw_crc;
+#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
+#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
+
+/* Register rw_data, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int val : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_scrc_out_rw_data;
+#define REG_RD_ADDR_iop_scrc_out_rw_data 16
+#define REG_WR_ADDR_iop_scrc_out_rw_data 16
+
+/* Register r_computed_crc, scope iop_scrc_out, type r */
+typedef unsigned int reg_iop_scrc_out_r_computed_crc;
+#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
+
+
+/* Constants */
+enum {
+  regk_iop_scrc_out_crc                    = 0x00000001,
+  regk_iop_scrc_out_data                   = 0x00000000,
+  regk_iop_scrc_out_dif                    = 0x00000001,
+  regk_iop_scrc_out_hi                     = 0x00000000,
+  regk_iop_scrc_out_neg                    = 0x00000002,
+  regk_iop_scrc_out_no                     = 0x00000000,
+  regk_iop_scrc_out_pos                    = 0x00000001,
+  regk_iop_scrc_out_pos_neg                = 0x00000003,
+  regk_iop_scrc_out_reg                    = 0x00000000,
+  regk_iop_scrc_out_rw_cfg_default         = 0x00000000,
+  regk_iop_scrc_out_rw_crc_default         = 0x00000000,
+  regk_iop_scrc_out_rw_ctrl_default        = 0x00000000,
+  regk_iop_scrc_out_rw_data_default        = 0x00000000,
+  regk_iop_scrc_out_rw_init_crc_default    = 0x00000000,
+  regk_iop_scrc_out_yes                    = 0x00000001
+};
+#endif /* __iop_scrc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
new file mode 100644
index 000000000000..0fda26e2f06f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
@@ -0,0 +1,453 @@
+#ifndef __iop_spu_defs_h
+#define __iop_spu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
+ *      id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_spu */
+
+#define STRIDE_iop_spu_rw_r 4
+/* Register rw_r, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_r;
+#define REG_RD_ADDR_iop_spu_rw_r 0
+#define REG_WR_ADDR_iop_spu_rw_r 0
+
+/* Register rw_seq_pc, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_seq_pc;
+#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
+#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
+
+/* Register rw_fsm_pc, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_fsm_pc;
+#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
+#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
+
+/* Register rw_ctrl, scope iop_spu, type rw */
+typedef struct {
+  unsigned int fsm : 1;
+  unsigned int en  : 1;
+  unsigned int dummy1 : 30;
+} reg_iop_spu_rw_ctrl;
+#define REG_RD_ADDR_iop_spu_rw_ctrl 72
+#define REG_WR_ADDR_iop_spu_rw_ctrl 72
+
+/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
+typedef struct {
+  unsigned int val0 : 5;
+  unsigned int src0 : 3;
+  unsigned int val1 : 5;
+  unsigned int src1 : 3;
+  unsigned int val2 : 5;
+  unsigned int src2 : 3;
+  unsigned int val3 : 5;
+  unsigned int src3 : 3;
+} reg_iop_spu_rw_fsm_inputs3_0;
+#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
+#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
+
+/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
+typedef struct {
+  unsigned int val4 : 5;
+  unsigned int src4 : 3;
+  unsigned int val5 : 5;
+  unsigned int src5 : 3;
+  unsigned int val6 : 5;
+  unsigned int src6 : 3;
+  unsigned int val7 : 5;
+  unsigned int src7 : 3;
+} reg_iop_spu_rw_fsm_inputs7_4;
+#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
+#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
+
+/* Register rw_gio_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out;
+#define REG_RD_ADDR_iop_spu_rw_gio_out 84
+#define REG_WR_ADDR_iop_spu_rw_gio_out 84
+
+/* Register rw_bus0_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_bus0_out;
+#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
+#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
+
+/* Register rw_bus1_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_bus1_out;
+#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
+#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
+
+/* Register r_gio_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_gio_in;
+#define REG_RD_ADDR_iop_spu_r_gio_in 96
+
+/* Register r_bus0_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_bus0_in;
+#define REG_RD_ADDR_iop_spu_r_bus0_in 100
+
+/* Register r_bus1_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_bus1_in;
+#define REG_RD_ADDR_iop_spu_r_bus1_in 104
+
+/* Register rw_gio_out_set, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out_set;
+#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
+#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
+
+/* Register rw_gio_out_clr, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out_clr;
+#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
+#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
+
+/* Register rs_wr_stat, scope iop_spu, type rs */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_spu_rs_wr_stat;
+#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
+
+/* Register r_wr_stat, scope iop_spu, type r */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_spu_r_wr_stat;
+#define REG_RD_ADDR_iop_spu_r_wr_stat 120
+
+/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
+#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
+
+/* Register r_stat_in, scope iop_spu, type r */
+typedef struct {
+  unsigned int timer_grp_lo    : 4;
+  unsigned int fifo_out_last   : 1;
+  unsigned int fifo_out_rdy    : 1;
+  unsigned int fifo_out_all    : 1;
+  unsigned int fifo_in_rdy     : 1;
+  unsigned int dmc_out_all     : 1;
+  unsigned int dmc_out_dth     : 1;
+  unsigned int dmc_out_eop     : 1;
+  unsigned int dmc_out_dv      : 1;
+  unsigned int dmc_out_last    : 1;
+  unsigned int dmc_out_cmd_rq  : 1;
+  unsigned int dmc_out_cmd_rdy : 1;
+  unsigned int pcrc_correct    : 1;
+  unsigned int timer_grp_hi    : 4;
+  unsigned int dmc_in_sth      : 1;
+  unsigned int dmc_in_full     : 1;
+  unsigned int dmc_in_cmd_rdy  : 1;
+  unsigned int spu_gio_out     : 4;
+  unsigned int sync_clk12      : 1;
+  unsigned int scrc_out_data   : 1;
+  unsigned int scrc_in_err     : 1;
+  unsigned int mc_busy         : 1;
+  unsigned int mc_owned        : 1;
+} reg_iop_spu_r_stat_in;
+#define REG_RD_ADDR_iop_spu_r_stat_in 128
+
+/* Register r_trigger_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_trigger_in;
+#define REG_RD_ADDR_iop_spu_r_trigger_in 132
+
+/* Register r_special_stat, scope iop_spu, type r */
+typedef struct {
+  unsigned int c_flag         : 1;
+  unsigned int v_flag         : 1;
+  unsigned int z_flag         : 1;
+  unsigned int n_flag         : 1;
+  unsigned int xor_bus0_r2_0  : 1;
+  unsigned int xor_bus1_r3_0  : 1;
+  unsigned int xor_bus0m_r2_0 : 1;
+  unsigned int xor_bus1m_r3_0 : 1;
+  unsigned int fsm_in0        : 1;
+  unsigned int fsm_in1        : 1;
+  unsigned int fsm_in2        : 1;
+  unsigned int fsm_in3        : 1;
+  unsigned int fsm_in4        : 1;
+  unsigned int fsm_in5        : 1;
+  unsigned int fsm_in6        : 1;
+  unsigned int fsm_in7        : 1;
+  unsigned int event0         : 1;
+  unsigned int event1         : 1;
+  unsigned int event2         : 1;
+  unsigned int event3         : 1;
+  unsigned int dummy1         : 12;
+} reg_iop_spu_r_special_stat;
+#define REG_RD_ADDR_iop_spu_r_special_stat 136
+
+/* Register rw_reg_access, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr   : 13;
+  unsigned int dummy1 : 3;
+  unsigned int imm_hi : 16;
+} reg_iop_spu_rw_reg_access;
+#define REG_RD_ADDR_iop_spu_rw_reg_access 140
+#define REG_WR_ADDR_iop_spu_rw_reg_access 140
+
+#define STRIDE_iop_spu_rw_event_cfg 4
+/* Register rw_event_cfg, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr   : 12;
+  unsigned int src    : 2;
+  unsigned int eq_en  : 1;
+  unsigned int eq_inv : 1;
+  unsigned int gt_en  : 1;
+  unsigned int gt_inv : 1;
+  unsigned int dummy1 : 14;
+} reg_iop_spu_rw_event_cfg;
+#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
+#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
+
+#define STRIDE_iop_spu_rw_event_mask 4
+/* Register rw_event_mask, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_event_mask;
+#define REG_RD_ADDR_iop_spu_rw_event_mask 160
+#define REG_WR_ADDR_iop_spu_rw_event_mask 160
+
+#define STRIDE_iop_spu_rw_event_val 4
+/* Register rw_event_val, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_event_val;
+#define REG_RD_ADDR_iop_spu_rw_event_val 176
+#define REG_WR_ADDR_iop_spu_rw_event_val 176
+
+/* Register rw_event_ret, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_event_ret;
+#define REG_RD_ADDR_iop_spu_rw_event_ret 192
+#define REG_WR_ADDR_iop_spu_rw_event_ret 192
+
+/* Register r_trace, scope iop_spu, type r */
+typedef struct {
+  unsigned int fsm      : 1;
+  unsigned int en       : 1;
+  unsigned int c_flag   : 1;
+  unsigned int v_flag   : 1;
+  unsigned int z_flag   : 1;
+  unsigned int n_flag   : 1;
+  unsigned int seq_addr : 12;
+  unsigned int dummy1   : 2;
+  unsigned int fsm_addr : 12;
+} reg_iop_spu_r_trace;
+#define REG_RD_ADDR_iop_spu_r_trace 196
+
+/* Register r_fsm_trace, scope iop_spu, type r */
+typedef struct {
+  unsigned int fsm      : 1;
+  unsigned int en       : 1;
+  unsigned int tmr_done : 1;
+  unsigned int inp0     : 1;
+  unsigned int inp1     : 1;
+  unsigned int inp2     : 1;
+  unsigned int inp3     : 1;
+  unsigned int event0   : 1;
+  unsigned int event1   : 1;
+  unsigned int event2   : 1;
+  unsigned int event3   : 1;
+  unsigned int gio_out  : 8;
+  unsigned int dummy1   : 1;
+  unsigned int fsm_addr : 12;
+} reg_iop_spu_r_fsm_trace;
+#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
+
+#define STRIDE_iop_spu_rw_brp 4
+/* Register rw_brp, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int fsm  : 1;
+  unsigned int en   : 1;
+  unsigned int dummy1 : 18;
+} reg_iop_spu_rw_brp;
+#define REG_RD_ADDR_iop_spu_rw_brp 204
+#define REG_WR_ADDR_iop_spu_rw_brp 204
+
+
+/* Constants */
+enum {
+  regk_iop_spu_attn_hi                     = 0x00000005,
+  regk_iop_spu_attn_lo                     = 0x00000005,
+  regk_iop_spu_attn_r0                     = 0x00000000,
+  regk_iop_spu_attn_r1                     = 0x00000001,
+  regk_iop_spu_attn_r10                    = 0x00000002,
+  regk_iop_spu_attn_r11                    = 0x00000003,
+  regk_iop_spu_attn_r12                    = 0x00000004,
+  regk_iop_spu_attn_r13                    = 0x00000005,
+  regk_iop_spu_attn_r14                    = 0x00000006,
+  regk_iop_spu_attn_r15                    = 0x00000007,
+  regk_iop_spu_attn_r2                     = 0x00000002,
+  regk_iop_spu_attn_r3                     = 0x00000003,
+  regk_iop_spu_attn_r4                     = 0x00000004,
+  regk_iop_spu_attn_r5                     = 0x00000005,
+  regk_iop_spu_attn_r6                     = 0x00000006,
+  regk_iop_spu_attn_r7                     = 0x00000007,
+  regk_iop_spu_attn_r8                     = 0x00000000,
+  regk_iop_spu_attn_r9                     = 0x00000001,
+  regk_iop_spu_c                           = 0x00000000,
+  regk_iop_spu_flag                        = 0x00000002,
+  regk_iop_spu_gio_in                      = 0x00000000,
+  regk_iop_spu_gio_out                     = 0x00000005,
+  regk_iop_spu_gio_out0                    = 0x00000008,
+  regk_iop_spu_gio_out1                    = 0x00000009,
+  regk_iop_spu_gio_out2                    = 0x0000000a,
+  regk_iop_spu_gio_out3                    = 0x0000000b,
+  regk_iop_spu_gio_out4                    = 0x0000000c,
+  regk_iop_spu_gio_out5                    = 0x0000000d,
+  regk_iop_spu_gio_out6                    = 0x0000000e,
+  regk_iop_spu_gio_out7                    = 0x0000000f,
+  regk_iop_spu_n                           = 0x00000003,
+  regk_iop_spu_no                          = 0x00000000,
+  regk_iop_spu_r0                          = 0x00000008,
+  regk_iop_spu_r1                          = 0x00000009,
+  regk_iop_spu_r10                         = 0x0000000a,
+  regk_iop_spu_r11                         = 0x0000000b,
+  regk_iop_spu_r12                         = 0x0000000c,
+  regk_iop_spu_r13                         = 0x0000000d,
+  regk_iop_spu_r14                         = 0x0000000e,
+  regk_iop_spu_r15                         = 0x0000000f,
+  regk_iop_spu_r2                          = 0x0000000a,
+  regk_iop_spu_r3                          = 0x0000000b,
+  regk_iop_spu_r4                          = 0x0000000c,
+  regk_iop_spu_r5                          = 0x0000000d,
+  regk_iop_spu_r6                          = 0x0000000e,
+  regk_iop_spu_r7                          = 0x0000000f,
+  regk_iop_spu_r8                          = 0x00000008,
+  regk_iop_spu_r9                          = 0x00000009,
+  regk_iop_spu_reg_hi                      = 0x00000002,
+  regk_iop_spu_reg_lo                      = 0x00000002,
+  regk_iop_spu_rw_brp_default              = 0x00000000,
+  regk_iop_spu_rw_brp_size                 = 0x00000004,
+  regk_iop_spu_rw_ctrl_default             = 0x00000000,
+  regk_iop_spu_rw_event_cfg_size           = 0x00000004,
+  regk_iop_spu_rw_event_mask_size          = 0x00000004,
+  regk_iop_spu_rw_event_val_size           = 0x00000004,
+  regk_iop_spu_rw_gio_out_default          = 0x00000000,
+  regk_iop_spu_rw_r_size                   = 0x00000010,
+  regk_iop_spu_rw_reg_access_default       = 0x00000000,
+  regk_iop_spu_stat_in                     = 0x00000002,
+  regk_iop_spu_statin_hi                   = 0x00000004,
+  regk_iop_spu_statin_lo                   = 0x00000004,
+  regk_iop_spu_trig                        = 0x00000003,
+  regk_iop_spu_trigger                     = 0x00000006,
+  regk_iop_spu_v                           = 0x00000001,
+  regk_iop_spu_wsts_gioout_spec            = 0x00000001,
+  regk_iop_spu_xor                         = 0x00000003,
+  regk_iop_spu_xor_bus0_r2_0               = 0x00000000,
+  regk_iop_spu_xor_bus0m_r2_0              = 0x00000002,
+  regk_iop_spu_xor_bus1_r3_0               = 0x00000001,
+  regk_iop_spu_xor_bus1m_r3_0              = 0x00000003,
+  regk_iop_spu_yes                         = 0x00000001,
+  regk_iop_spu_z                           = 0x00000002
+};
+#endif /* __iop_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
new file mode 100644
index 000000000000..d7b6d75884d2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
@@ -0,0 +1,1042 @@
+#ifndef __iop_sw_cfg_defs_h
+#define __iop_sw_cfg_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *      id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cfg */
+
+/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_crc_par0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
+#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
+
+/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_crc_par1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
+#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
+
+/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
+
+/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
+
+/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
+
+/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
+
+/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
+
+/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
+
+/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
+
+/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
+
+/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
+
+/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
+
+/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
+
+/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
+
+/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
+
+/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
+
+/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
+
+/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
+
+/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_spu0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
+
+/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_spu1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
+
+/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp2_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
+
+/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp3_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp2_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp3_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp4_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp5_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp6_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp7_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
+
+/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cfg_rw_bus0_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
+
+/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cfg_rw_bus0_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
+
+/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cfg_rw_bus1_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
+
+/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cfg_rw_bus1_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_byte0 : 2;
+  unsigned int bus0_byte1 : 2;
+  unsigned int bus0_byte2 : 2;
+  unsigned int bus0_byte3 : 2;
+  unsigned int bus1_byte0 : 2;
+  unsigned int bus1_byte1 : 2;
+  unsigned int bus1_byte2 : 2;
+  unsigned int bus1_byte3 : 2;
+  unsigned int gio3_0     : 2;
+  unsigned int gio7_4     : 2;
+  unsigned int gio11_8    : 2;
+  unsigned int gio15_12   : 2;
+  unsigned int gio19_16   : 2;
+  unsigned int gio23_20   : 2;
+  unsigned int gio27_24   : 2;
+  unsigned int gio31_28   : 2;
+} reg_iop_sw_cfg_rw_pinmapping;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
+#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_lo    : 3;
+  unsigned int bus0_hi    : 3;
+  unsigned int bus0_lo_oe : 3;
+  unsigned int bus0_hi_oe : 3;
+  unsigned int bus1_lo    : 3;
+  unsigned int bus1_hi    : 3;
+  unsigned int bus1_lo_oe : 3;
+  unsigned int bus1_hi_oe : 3;
+  unsigned int dummy1     : 8;
+} reg_iop_sw_cfg_rw_bus_out_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio0    : 4;
+  unsigned int gio0_oe : 2;
+  unsigned int gio1    : 4;
+  unsigned int gio1_oe : 2;
+  unsigned int gio2    : 4;
+  unsigned int gio2_oe : 2;
+  unsigned int gio3    : 4;
+  unsigned int gio3_oe : 2;
+  unsigned int dummy1  : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio4    : 4;
+  unsigned int gio4_oe : 2;
+  unsigned int gio5    : 4;
+  unsigned int gio5_oe : 2;
+  unsigned int gio6    : 4;
+  unsigned int gio6_oe : 2;
+  unsigned int gio7    : 4;
+  unsigned int gio7_oe : 2;
+  unsigned int dummy1  : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio8     : 4;
+  unsigned int gio8_oe  : 2;
+  unsigned int gio9     : 4;
+  unsigned int gio9_oe  : 2;
+  unsigned int gio10    : 4;
+  unsigned int gio10_oe : 2;
+  unsigned int gio11    : 4;
+  unsigned int gio11_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio12    : 4;
+  unsigned int gio12_oe : 2;
+  unsigned int gio13    : 4;
+  unsigned int gio13_oe : 2;
+  unsigned int gio14    : 4;
+  unsigned int gio14_oe : 2;
+  unsigned int gio15    : 4;
+  unsigned int gio15_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio16    : 4;
+  unsigned int gio16_oe : 2;
+  unsigned int gio17    : 4;
+  unsigned int gio17_oe : 2;
+  unsigned int gio18    : 4;
+  unsigned int gio18_oe : 2;
+  unsigned int gio19    : 4;
+  unsigned int gio19_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio20    : 4;
+  unsigned int gio20_oe : 2;
+  unsigned int gio21    : 4;
+  unsigned int gio21_oe : 2;
+  unsigned int gio22    : 4;
+  unsigned int gio22_oe : 2;
+  unsigned int gio23    : 4;
+  unsigned int gio23_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio24    : 4;
+  unsigned int gio24_oe : 2;
+  unsigned int gio25    : 4;
+  unsigned int gio25_oe : 2;
+  unsigned int gio26    : 4;
+  unsigned int gio26_oe : 2;
+  unsigned int gio27    : 4;
+  unsigned int gio27_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio28    : 4;
+  unsigned int gio28_oe : 2;
+  unsigned int gio29    : 4;
+  unsigned int gio29_oe : 2;
+  unsigned int gio30    : 4;
+  unsigned int gio30_oe : 2;
+  unsigned int gio31    : 4;
+  unsigned int gio31_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
+
+/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_in : 2;
+  unsigned int bus1_in : 2;
+  unsigned int dummy1  : 28;
+} reg_iop_sw_cfg_rw_spu0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
+
+/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_in : 2;
+  unsigned int bus1_in : 2;
+  unsigned int dummy1  : 28;
+} reg_iop_sw_cfg_rw_spu1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
+
+/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp2_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
+
+/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp3_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int grp0_dis : 1;
+  unsigned int grp0_en  : 1;
+  unsigned int grp1_dis : 1;
+  unsigned int grp1_en  : 1;
+  unsigned int grp2_dis : 1;
+  unsigned int grp2_en  : 1;
+  unsigned int grp3_dis : 1;
+  unsigned int grp3_en  : 1;
+  unsigned int grp4_dis : 1;
+  unsigned int grp4_en  : 1;
+  unsigned int grp5_dis : 1;
+  unsigned int grp5_en  : 1;
+  unsigned int grp6_dis : 1;
+  unsigned int grp6_en  : 1;
+  unsigned int grp7_dis : 1;
+  unsigned int grp7_en  : 1;
+  unsigned int dummy1   : 16;
+} reg_iop_sw_cfg_rw_trigger_grps_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
+
+/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int dmc0_usr : 1;
+  unsigned int out_strb : 5;
+  unsigned int in_src   : 3;
+  unsigned int in_size  : 3;
+  unsigned int in_last  : 2;
+  unsigned int in_strb  : 4;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 13;
+} reg_iop_sw_cfg_rw_pdp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
+#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
+
+/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int dmc1_usr : 1;
+  unsigned int out_strb : 5;
+  unsigned int in_src   : 3;
+  unsigned int in_size  : 3;
+  unsigned int in_last  : 2;
+  unsigned int in_strb  : 4;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 13;
+} reg_iop_sw_cfg_rw_pdp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
+#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int sdp_out0_strb : 3;
+  unsigned int sdp_out1_strb : 3;
+  unsigned int sdp_in0_data  : 3;
+  unsigned int sdp_in0_last  : 2;
+  unsigned int sdp_in0_strb  : 3;
+  unsigned int sdp_in1_data  : 3;
+  unsigned int sdp_in1_last  : 2;
+  unsigned int sdp_in1_strb  : 3;
+  unsigned int dummy1        : 10;
+} reg_iop_sw_cfg_rw_sdp_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
+#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
+
+
+/* Constants */
+enum {
+  regk_iop_sw_cfg_a                        = 0x00000001,
+  regk_iop_sw_cfg_b                        = 0x00000002,
+  regk_iop_sw_cfg_bus0                     = 0x00000000,
+  regk_iop_sw_cfg_bus0_rot16               = 0x00000004,
+  regk_iop_sw_cfg_bus0_rot24               = 0x00000006,
+  regk_iop_sw_cfg_bus0_rot8                = 0x00000002,
+  regk_iop_sw_cfg_bus1                     = 0x00000001,
+  regk_iop_sw_cfg_bus1_rot16               = 0x00000005,
+  regk_iop_sw_cfg_bus1_rot24               = 0x00000007,
+  regk_iop_sw_cfg_bus1_rot8                = 0x00000003,
+  regk_iop_sw_cfg_clk12                    = 0x00000000,
+  regk_iop_sw_cfg_cpu                      = 0x00000000,
+  regk_iop_sw_cfg_dmc0                     = 0x00000000,
+  regk_iop_sw_cfg_dmc1                     = 0x00000001,
+  regk_iop_sw_cfg_gated_clk0               = 0x00000010,
+  regk_iop_sw_cfg_gated_clk1               = 0x00000011,
+  regk_iop_sw_cfg_gated_clk2               = 0x00000012,
+  regk_iop_sw_cfg_gated_clk3               = 0x00000013,
+  regk_iop_sw_cfg_gio0                     = 0x00000004,
+  regk_iop_sw_cfg_gio1                     = 0x00000001,
+  regk_iop_sw_cfg_gio2                     = 0x00000005,
+  regk_iop_sw_cfg_gio3                     = 0x00000002,
+  regk_iop_sw_cfg_gio4                     = 0x00000006,
+  regk_iop_sw_cfg_gio5                     = 0x00000003,
+  regk_iop_sw_cfg_gio6                     = 0x00000007,
+  regk_iop_sw_cfg_gio7                     = 0x00000004,
+  regk_iop_sw_cfg_gio_in0                  = 0x00000000,
+  regk_iop_sw_cfg_gio_in1                  = 0x00000001,
+  regk_iop_sw_cfg_gio_in10                 = 0x00000002,
+  regk_iop_sw_cfg_gio_in11                 = 0x00000003,
+  regk_iop_sw_cfg_gio_in14                 = 0x00000004,
+  regk_iop_sw_cfg_gio_in15                 = 0x00000005,
+  regk_iop_sw_cfg_gio_in18                 = 0x00000002,
+  regk_iop_sw_cfg_gio_in19                 = 0x00000003,
+  regk_iop_sw_cfg_gio_in20                 = 0x00000004,
+  regk_iop_sw_cfg_gio_in21                 = 0x00000005,
+  regk_iop_sw_cfg_gio_in26                 = 0x00000006,
+  regk_iop_sw_cfg_gio_in27                 = 0x00000007,
+  regk_iop_sw_cfg_gio_in28                 = 0x00000006,
+  regk_iop_sw_cfg_gio_in29                 = 0x00000007,
+  regk_iop_sw_cfg_gio_in4                  = 0x00000000,
+  regk_iop_sw_cfg_gio_in5                  = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp0_tmr2     = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp1_tmr2     = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp2_tmr2     = 0x00000002,
+  regk_iop_sw_cfg_last_timer_grp2_tmr3     = 0x00000003,
+  regk_iop_sw_cfg_last_timer_grp3_tmr2     = 0x00000002,
+  regk_iop_sw_cfg_last_timer_grp3_tmr3     = 0x00000003,
+  regk_iop_sw_cfg_mpu                      = 0x00000001,
+  regk_iop_sw_cfg_none                     = 0x00000000,
+  regk_iop_sw_cfg_par0                     = 0x00000000,
+  regk_iop_sw_cfg_par1                     = 0x00000001,
+  regk_iop_sw_cfg_pdp_out0                 = 0x00000002,
+  regk_iop_sw_cfg_pdp_out0_hi              = 0x00000001,
+  regk_iop_sw_cfg_pdp_out0_hi_rot8         = 0x00000005,
+  regk_iop_sw_cfg_pdp_out0_lo              = 0x00000000,
+  regk_iop_sw_cfg_pdp_out0_lo_rot8         = 0x00000004,
+  regk_iop_sw_cfg_pdp_out1                 = 0x00000003,
+  regk_iop_sw_cfg_pdp_out1_hi              = 0x00000003,
+  regk_iop_sw_cfg_pdp_out1_hi_rot8         = 0x00000005,
+  regk_iop_sw_cfg_pdp_out1_lo              = 0x00000002,
+  regk_iop_sw_cfg_pdp_out1_lo_rot8         = 0x00000004,
+  regk_iop_sw_cfg_rw_bus0_mask_default     = 0x00000000,
+  regk_iop_sw_cfg_rw_bus0_oe_mask_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_bus1_mask_default     = 0x00000000,
+  regk_iop_sw_cfg_rw_bus1_oe_mask_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_bus_out_cfg_default   = 0x00000000,
+  regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_mask_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_oe_mask_default   = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_pdp0_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_pdp1_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_pinmapping_default    = 0x55555555,
+  regk_iop_sw_cfg_rw_sap_in_owner_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_sdp_cfg_default       = 0x00000000,
+  regk_iop_sw_cfg_rw_spu0_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_spu0_owner_default    = 0x00000000,
+  regk_iop_sw_cfg_rw_spu1_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_spu1_owner_default    = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_sdp_out0                 = 0x00000008,
+  regk_iop_sw_cfg_sdp_out1                 = 0x00000009,
+  regk_iop_sw_cfg_size16                   = 0x00000002,
+  regk_iop_sw_cfg_size24                   = 0x00000003,
+  regk_iop_sw_cfg_size32                   = 0x00000004,
+  regk_iop_sw_cfg_size8                    = 0x00000001,
+  regk_iop_sw_cfg_spu0                     = 0x00000002,
+  regk_iop_sw_cfg_spu0_bus_out0_hi         = 0x00000006,
+  regk_iop_sw_cfg_spu0_bus_out0_lo         = 0x00000006,
+  regk_iop_sw_cfg_spu0_bus_out1_hi         = 0x00000007,
+  regk_iop_sw_cfg_spu0_bus_out1_lo         = 0x00000007,
+  regk_iop_sw_cfg_spu0_g0                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g1                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g2                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g3                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g4                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g5                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g6                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g7                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gio0                = 0x00000000,
+  regk_iop_sw_cfg_spu0_gio1                = 0x00000001,
+  regk_iop_sw_cfg_spu0_gio2                = 0x00000000,
+  regk_iop_sw_cfg_spu0_gio5                = 0x00000005,
+  regk_iop_sw_cfg_spu0_gio6                = 0x00000006,
+  regk_iop_sw_cfg_spu0_gio7                = 0x00000007,
+  regk_iop_sw_cfg_spu0_gio_out0            = 0x00000008,
+  regk_iop_sw_cfg_spu0_gio_out1            = 0x00000009,
+  regk_iop_sw_cfg_spu0_gio_out2            = 0x0000000a,
+  regk_iop_sw_cfg_spu0_gio_out3            = 0x0000000b,
+  regk_iop_sw_cfg_spu0_gio_out4            = 0x0000000c,
+  regk_iop_sw_cfg_spu0_gio_out5            = 0x0000000d,
+  regk_iop_sw_cfg_spu0_gio_out6            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gio_out7            = 0x0000000f,
+  regk_iop_sw_cfg_spu0_gioout0             = 0x00000000,
+  regk_iop_sw_cfg_spu0_gioout1             = 0x00000000,
+  regk_iop_sw_cfg_spu0_gioout10            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout11            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout12            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout13            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout14            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout15            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout16            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout17            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout18            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout19            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout2             = 0x00000002,
+  regk_iop_sw_cfg_spu0_gioout20            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout21            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout22            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout23            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout24            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout25            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout26            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout27            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout28            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout29            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout3             = 0x00000002,
+  regk_iop_sw_cfg_spu0_gioout30            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout31            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout4             = 0x00000004,
+  regk_iop_sw_cfg_spu0_gioout5             = 0x00000004,
+  regk_iop_sw_cfg_spu0_gioout6             = 0x00000006,
+  regk_iop_sw_cfg_spu0_gioout7             = 0x00000006,
+  regk_iop_sw_cfg_spu0_gioout8             = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout9             = 0x0000000e,
+  regk_iop_sw_cfg_spu1                     = 0x00000003,
+  regk_iop_sw_cfg_spu1_bus_out0_hi         = 0x00000006,
+  regk_iop_sw_cfg_spu1_bus_out0_lo         = 0x00000006,
+  regk_iop_sw_cfg_spu1_bus_out1_hi         = 0x00000007,
+  regk_iop_sw_cfg_spu1_bus_out1_lo         = 0x00000007,
+  regk_iop_sw_cfg_spu1_g0                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g1                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g2                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g3                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g4                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g5                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g6                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g7                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gio0                = 0x00000002,
+  regk_iop_sw_cfg_spu1_gio1                = 0x00000003,
+  regk_iop_sw_cfg_spu1_gio2                = 0x00000002,
+  regk_iop_sw_cfg_spu1_gio5                = 0x00000005,
+  regk_iop_sw_cfg_spu1_gio6                = 0x00000006,
+  regk_iop_sw_cfg_spu1_gio7                = 0x00000007,
+  regk_iop_sw_cfg_spu1_gio_out0            = 0x00000008,
+  regk_iop_sw_cfg_spu1_gio_out1            = 0x00000009,
+  regk_iop_sw_cfg_spu1_gio_out2            = 0x0000000a,
+  regk_iop_sw_cfg_spu1_gio_out3            = 0x0000000b,
+  regk_iop_sw_cfg_spu1_gio_out4            = 0x0000000c,
+  regk_iop_sw_cfg_spu1_gio_out5            = 0x0000000d,
+  regk_iop_sw_cfg_spu1_gio_out6            = 0x0000000e,
+  regk_iop_sw_cfg_spu1_gio_out7            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout0             = 0x00000001,
+  regk_iop_sw_cfg_spu1_gioout1             = 0x00000001,
+  regk_iop_sw_cfg_spu1_gioout10            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout11            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout12            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout13            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout14            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout15            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout16            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout17            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout18            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout19            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout2             = 0x00000003,
+  regk_iop_sw_cfg_spu1_gioout20            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout21            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout22            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout23            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout24            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout25            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout26            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout27            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout28            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout29            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout3             = 0x00000003,
+  regk_iop_sw_cfg_spu1_gioout30            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout31            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout4             = 0x00000005,
+  regk_iop_sw_cfg_spu1_gioout5             = 0x00000005,
+  regk_iop_sw_cfg_spu1_gioout6             = 0x00000007,
+  regk_iop_sw_cfg_spu1_gioout7             = 0x00000007,
+  regk_iop_sw_cfg_spu1_gioout8             = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout9             = 0x0000000f,
+  regk_iop_sw_cfg_strb_timer_grp0_tmr0     = 0x00000001,
+  regk_iop_sw_cfg_strb_timer_grp0_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp1_tmr0     = 0x00000001,
+  regk_iop_sw_cfg_strb_timer_grp1_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp2_tmr0     = 0x00000003,
+  regk_iop_sw_cfg_strb_timer_grp2_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp3_tmr0     = 0x00000003,
+  regk_iop_sw_cfg_strb_timer_grp3_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_timer_grp0               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp0_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp0_strb0         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb1         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb2         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb3         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_tmr0          = 0x00000004,
+  regk_iop_sw_cfg_timer_grp0_tmr1          = 0x00000004,
+  regk_iop_sw_cfg_timer_grp1               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp1_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp1_strb0         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb1         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb2         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb3         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_tmr0          = 0x00000005,
+  regk_iop_sw_cfg_timer_grp1_tmr1          = 0x00000005,
+  regk_iop_sw_cfg_timer_grp2               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp2_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp2_strb0         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb1         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb2         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb3         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_tmr0          = 0x00000006,
+  regk_iop_sw_cfg_timer_grp2_tmr1          = 0x00000006,
+  regk_iop_sw_cfg_timer_grp3               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp3_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp3_strb0         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb1         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb2         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb3         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_tmr0          = 0x00000007,
+  regk_iop_sw_cfg_timer_grp3_tmr1          = 0x00000007,
+  regk_iop_sw_cfg_trig0_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig4_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_3                  = 0x00000001
+};
+#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
new file mode 100644
index 000000000000..5fed844b19e2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
@@ -0,0 +1,853 @@
+#ifndef __iop_sw_cpu_defs_h
+#define __iop_sw_cpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *      id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cpu */
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_cpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_cpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
+
+/* Register r_bus0_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
+
+/* Register r_bus1_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_rw_intr0_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_rw_ack_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_r_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_r_masked_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_rw_intr1_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_rw_ack_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_r_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_r_masked_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
+
+/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_rw_intr2_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
+
+/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0  : 1;
+  unsigned int mpu_1  : 1;
+  unsigned int mpu_2  : 1;
+  unsigned int mpu_3  : 1;
+  unsigned int mpu_4  : 1;
+  unsigned int mpu_5  : 1;
+  unsigned int mpu_6  : 1;
+  unsigned int mpu_7  : 1;
+  unsigned int spu0_0 : 1;
+  unsigned int spu0_1 : 1;
+  unsigned int spu0_2 : 1;
+  unsigned int spu0_3 : 1;
+  unsigned int spu0_4 : 1;
+  unsigned int spu0_5 : 1;
+  unsigned int spu0_6 : 1;
+  unsigned int spu0_7 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_cpu_rw_ack_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
+
+/* Register r_intr2, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_r_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
+
+/* Register r_masked_intr2, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_r_masked_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
+
+/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_rw_intr3_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
+
+/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16 : 1;
+  unsigned int mpu_17 : 1;
+  unsigned int mpu_18 : 1;
+  unsigned int mpu_19 : 1;
+  unsigned int mpu_20 : 1;
+  unsigned int mpu_21 : 1;
+  unsigned int mpu_22 : 1;
+  unsigned int mpu_23 : 1;
+  unsigned int spu1_0 : 1;
+  unsigned int spu1_1 : 1;
+  unsigned int spu1_2 : 1;
+  unsigned int spu1_3 : 1;
+  unsigned int spu1_4 : 1;
+  unsigned int spu1_5 : 1;
+  unsigned int spu1_6 : 1;
+  unsigned int spu1_7 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_cpu_rw_ack_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
+
+/* Register r_intr3, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_r_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
+
+/* Register r_masked_intr3, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_r_masked_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
+
+
+/* Constants */
+enum {
+  regk_iop_sw_cpu_copy                     = 0x00000000,
+  regk_iop_sw_cpu_no                       = 0x00000000,
+  regk_iop_sw_cpu_rd                       = 0x00000002,
+  regk_iop_sw_cpu_reg_copy                 = 0x00000001,
+  regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_cpu_rw_intr0_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr1_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr2_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr3_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_wr                       = 0x00000003,
+  regk_iop_sw_cpu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
new file mode 100644
index 000000000000..da718f2a8cad
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
@@ -0,0 +1,893 @@
+#ifndef __iop_sw_mpu_defs_h
+#define __iop_sw_mpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *      id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_mpu */
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_mpu_rw_sw_cfg_owner;
+#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_mpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_mpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
+
+/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
+
+/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
+
+/* Register r_bus0_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
+
+/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
+
+/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
+
+/* Register r_bus1_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int intr16 : 1;
+  unsigned int intr17 : 1;
+  unsigned int intr18 : 1;
+  unsigned int intr19 : 1;
+  unsigned int intr20 : 1;
+  unsigned int intr21 : 1;
+  unsigned int intr22 : 1;
+  unsigned int intr23 : 1;
+  unsigned int intr24 : 1;
+  unsigned int intr25 : 1;
+  unsigned int intr26 : 1;
+  unsigned int intr27 : 1;
+  unsigned int intr28 : 1;
+  unsigned int intr29 : 1;
+  unsigned int intr30 : 1;
+  unsigned int intr31 : 1;
+} reg_iop_sw_mpu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
+#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int intr16 : 1;
+  unsigned int intr17 : 1;
+  unsigned int intr18 : 1;
+  unsigned int intr19 : 1;
+  unsigned int intr20 : 1;
+  unsigned int intr21 : 1;
+  unsigned int intr22 : 1;
+  unsigned int intr23 : 1;
+  unsigned int intr24 : 1;
+  unsigned int intr25 : 1;
+  unsigned int intr26 : 1;
+  unsigned int intr27 : 1;
+  unsigned int intr28 : 1;
+  unsigned int intr29 : 1;
+  unsigned int intr30 : 1;
+  unsigned int intr31 : 1;
+} reg_iop_sw_mpu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp0_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr0 : 1;
+  unsigned int spu1_intr0 : 1;
+  unsigned int dummy1     : 6;
+  unsigned int spu0_intr1 : 1;
+  unsigned int spu1_intr1 : 1;
+  unsigned int dummy2     : 6;
+  unsigned int spu0_intr2 : 1;
+  unsigned int spu1_intr2 : 1;
+  unsigned int dummy3     : 6;
+  unsigned int spu0_intr3 : 1;
+  unsigned int spu1_intr3 : 1;
+  unsigned int dummy4     : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp1_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr4 : 1;
+  unsigned int spu1_intr4 : 1;
+  unsigned int dummy1     : 6;
+  unsigned int spu0_intr5 : 1;
+  unsigned int spu1_intr5 : 1;
+  unsigned int dummy2     : 6;
+  unsigned int spu0_intr6 : 1;
+  unsigned int spu1_intr6 : 1;
+  unsigned int dummy3     : 6;
+  unsigned int spu0_intr7 : 1;
+  unsigned int spu1_intr7 : 1;
+  unsigned int dummy4     : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp2_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr8  : 1;
+  unsigned int spu1_intr8  : 1;
+  unsigned int dummy1      : 6;
+  unsigned int spu0_intr9  : 1;
+  unsigned int spu1_intr9  : 1;
+  unsigned int dummy2      : 6;
+  unsigned int spu0_intr10 : 1;
+  unsigned int spu1_intr10 : 1;
+  unsigned int dummy3      : 6;
+  unsigned int spu0_intr11 : 1;
+  unsigned int spu1_intr11 : 1;
+  unsigned int dummy4      : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp3_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr12 : 1;
+  unsigned int spu1_intr12 : 1;
+  unsigned int dummy1      : 6;
+  unsigned int spu0_intr13 : 1;
+  unsigned int spu1_intr13 : 1;
+  unsigned int dummy2      : 6;
+  unsigned int spu0_intr14 : 1;
+  unsigned int spu1_intr14 : 1;
+  unsigned int dummy3      : 6;
+  unsigned int spu0_intr15 : 1;
+  unsigned int spu1_intr15 : 1;
+  unsigned int dummy4      : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
+
+
+/* Constants */
+enum {
+  regk_iop_sw_mpu_copy                     = 0x00000000,
+  regk_iop_sw_mpu_cpu                      = 0x00000000,
+  regk_iop_sw_mpu_mpu                      = 0x00000001,
+  regk_iop_sw_mpu_no                       = 0x00000000,
+  regk_iop_sw_mpu_nop                      = 0x00000000,
+  regk_iop_sw_mpu_rd                       = 0x00000002,
+  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
+  regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
+  regk_iop_sw_mpu_set                      = 0x00000001,
+  regk_iop_sw_mpu_spu0                     = 0x00000002,
+  regk_iop_sw_mpu_spu1                     = 0x00000003,
+  regk_iop_sw_mpu_wr                       = 0x00000003,
+  regk_iop_sw_mpu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
new file mode 100644
index 000000000000..b59dde4bd0d1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
@@ -0,0 +1,552 @@
+#ifndef __iop_sw_spu_defs_h
+#define __iop_sw_spu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_spu */
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_spu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+typedef unsigned int reg_iop_sw_spu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_spu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
+
+/* Register r_bus0_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
+
+/* Register r_bus1_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
+
+/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
+
+/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
+
+/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
+
+/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
+
+/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
+
+/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
+
+/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
+
+/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
+#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sw_spu_r_hw_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
+#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int intr0            : 1;
+  unsigned int intr1            : 1;
+  unsigned int intr2            : 1;
+  unsigned int intr3            : 1;
+  unsigned int intr4            : 1;
+  unsigned int intr5            : 1;
+  unsigned int intr6            : 1;
+  unsigned int intr7            : 1;
+  unsigned int intr8            : 1;
+  unsigned int intr9            : 1;
+  unsigned int intr10           : 1;
+  unsigned int intr11           : 1;
+  unsigned int intr12           : 1;
+  unsigned int intr13           : 1;
+  unsigned int intr14           : 1;
+  unsigned int intr15           : 1;
+  unsigned int other_spu_intr0  : 1;
+  unsigned int other_spu_intr1  : 1;
+  unsigned int other_spu_intr2  : 1;
+  unsigned int other_spu_intr3  : 1;
+  unsigned int other_spu_intr4  : 1;
+  unsigned int other_spu_intr5  : 1;
+  unsigned int other_spu_intr6  : 1;
+  unsigned int other_spu_intr7  : 1;
+  unsigned int other_spu_intr8  : 1;
+  unsigned int other_spu_intr9  : 1;
+  unsigned int other_spu_intr10 : 1;
+  unsigned int other_spu_intr11 : 1;
+  unsigned int other_spu_intr12 : 1;
+  unsigned int other_spu_intr13 : 1;
+  unsigned int other_spu_intr14 : 1;
+  unsigned int other_spu_intr15 : 1;
+} reg_iop_sw_spu_r_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
+
+
+/* Constants */
+enum {
+  regk_iop_sw_spu_copy                     = 0x00000000,
+  regk_iop_sw_spu_no                       = 0x00000000,
+  regk_iop_sw_spu_nop                      = 0x00000000,
+  regk_iop_sw_spu_rd                       = 0x00000002,
+  regk_iop_sw_spu_reg_copy                 = 0x00000001,
+  regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_spu_set                      = 0x00000001,
+  regk_iop_sw_spu_wr                       = 0x00000003,
+  regk_iop_sw_spu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
new file mode 100644
index 000000000000..c994114f3b51
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
@@ -0,0 +1,249 @@
+#ifndef __iop_timer_grp_defs_h
+#define __iop_timer_grp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
+ *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
+ *      id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_timer_grp */
+
+/* Register rw_cfg, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int clk_src     : 1;
+  unsigned int trig        : 2;
+  unsigned int clk_gen_div : 8;
+  unsigned int clk_div     : 8;
+  unsigned int dummy1      : 13;
+} reg_iop_timer_grp_rw_cfg;
+#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
+#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
+
+/* Register rw_half_period, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int quota_lo     : 15;
+  unsigned int quota_hi     : 15;
+  unsigned int quota_hi_sel : 1;
+  unsigned int dummy1       : 1;
+} reg_iop_timer_grp_rw_half_period;
+#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
+#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
+
+/* Register rw_half_period_len, scope iop_timer_grp, type rw */
+typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
+#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
+#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
+
+#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
+/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int clk_src         : 3;
+  unsigned int strb            : 2;
+  unsigned int run_mode        : 2;
+  unsigned int out_mode        : 1;
+  unsigned int active_on_tmr   : 2;
+  unsigned int inv             : 1;
+  unsigned int en_by_tmr       : 2;
+  unsigned int dis_by_tmr      : 2;
+  unsigned int en_only_by_reg  : 1;
+  unsigned int dis_only_by_reg : 1;
+  unsigned int rst_at_en_strb  : 1;
+  unsigned int dummy1          : 14;
+} reg_iop_timer_grp_rw_tmr_cfg;
+#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
+#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
+
+#define STRIDE_iop_timer_grp_rw_tmr_len 4
+/* Register rw_tmr_len, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rw_tmr_len;
+#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
+#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
+
+/* Register rw_cmd, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int rst  : 4;
+  unsigned int en   : 4;
+  unsigned int dis  : 4;
+  unsigned int strb : 4;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rw_cmd;
+#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
+#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
+
+/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
+typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
+#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
+
+#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
+/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rs_tmr_cnt;
+#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
+
+#define STRIDE_iop_timer_grp_r_tmr_cnt 8
+/* Register r_tmr_cnt, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_r_tmr_cnt;
+#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
+
+/* Register rw_intr_mask, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_rw_intr_mask;
+#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
+#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
+
+/* Register rw_ack_intr, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_rw_ack_intr;
+#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
+#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
+
+/* Register r_intr, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_r_intr;
+#define REG_RD_ADDR_iop_timer_grp_r_intr 108
+
+/* Register r_masked_intr, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_r_masked_intr;
+#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
+
+
+/* Constants */
+enum {
+  regk_iop_timer_grp_clk200                = 0x00000000,
+  regk_iop_timer_grp_clk_gen               = 0x00000002,
+  regk_iop_timer_grp_complete              = 0x00000002,
+  regk_iop_timer_grp_div_clk200            = 0x00000001,
+  regk_iop_timer_grp_div_clk_gen           = 0x00000003,
+  regk_iop_timer_grp_ext                   = 0x00000001,
+  regk_iop_timer_grp_hi                    = 0x00000000,
+  regk_iop_timer_grp_long_period           = 0x00000001,
+  regk_iop_timer_grp_neg                   = 0x00000002,
+  regk_iop_timer_grp_no                    = 0x00000000,
+  regk_iop_timer_grp_once                  = 0x00000003,
+  regk_iop_timer_grp_pause                 = 0x00000001,
+  regk_iop_timer_grp_pos                   = 0x00000001,
+  regk_iop_timer_grp_pos_neg               = 0x00000003,
+  regk_iop_timer_grp_pulse                 = 0x00000000,
+  regk_iop_timer_grp_r_tmr_cnt_size        = 0x00000004,
+  regk_iop_timer_grp_rs_tmr_cnt_size       = 0x00000004,
+  regk_iop_timer_grp_rw_cfg_default        = 0x00000002,
+  regk_iop_timer_grp_rw_intr_mask_default  = 0x00000000,
+  regk_iop_timer_grp_rw_tmr_cfg_default0   = 0x00018000,
+  regk_iop_timer_grp_rw_tmr_cfg_default1   = 0x0001a900,
+  regk_iop_timer_grp_rw_tmr_cfg_default2   = 0x0001d200,
+  regk_iop_timer_grp_rw_tmr_cfg_default3   = 0x0001fb00,
+  regk_iop_timer_grp_rw_tmr_cfg_size       = 0x00000004,
+  regk_iop_timer_grp_rw_tmr_len_default    = 0x00000000,
+  regk_iop_timer_grp_rw_tmr_len_size       = 0x00000004,
+  regk_iop_timer_grp_short_period          = 0x00000000,
+  regk_iop_timer_grp_stop                  = 0x00000000,
+  regk_iop_timer_grp_tmr                   = 0x00000004,
+  regk_iop_timer_grp_toggle                = 0x00000001,
+  regk_iop_timer_grp_yes                   = 0x00000001
+};
+#endif /* __iop_timer_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
new file mode 100644
index 000000000000..36e44282399d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
@@ -0,0 +1,170 @@
+#ifndef __iop_trigger_grp_defs_h
+#define __iop_trigger_grp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *      id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_trigger_grp */
+
+#define STRIDE_iop_trigger_grp_rw_cfg 4
+/* Register rw_cfg, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int action          : 2;
+  unsigned int once            : 1;
+  unsigned int trig            : 3;
+  unsigned int en_only_by_reg  : 1;
+  unsigned int dis_only_by_reg : 1;
+  unsigned int dummy1          : 24;
+} reg_iop_trigger_grp_rw_cfg;
+#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
+#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
+
+/* Register rw_cmd, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int dis : 4;
+  unsigned int en  : 4;
+  unsigned int dummy1 : 24;
+} reg_iop_trigger_grp_rw_cmd;
+#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
+#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
+
+/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_rw_intr_mask;
+#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
+#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
+
+/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_rw_ack_intr;
+#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
+#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
+
+/* Register r_intr, scope iop_trigger_grp, type r */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_r_intr;
+#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
+
+/* Register r_masked_intr, scope iop_trigger_grp, type r */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_r_masked_intr;
+#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
+
+
+/* Constants */
+enum {
+  regk_iop_trigger_grp_fall                = 0x00000002,
+  regk_iop_trigger_grp_fall_lo             = 0x00000006,
+  regk_iop_trigger_grp_no                  = 0x00000000,
+  regk_iop_trigger_grp_off                 = 0x00000000,
+  regk_iop_trigger_grp_pulse               = 0x00000000,
+  regk_iop_trigger_grp_rise                = 0x00000001,
+  regk_iop_trigger_grp_rise_fall           = 0x00000003,
+  regk_iop_trigger_grp_rise_fall_hi        = 0x00000007,
+  regk_iop_trigger_grp_rise_fall_lo        = 0x00000004,
+  regk_iop_trigger_grp_rise_hi             = 0x00000005,
+  regk_iop_trigger_grp_rw_cfg_default      = 0x000000c0,
+  regk_iop_trigger_grp_rw_cfg_size         = 0x00000004,
+  regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
+  regk_iop_trigger_grp_toggle              = 0x00000003,
+  regk_iop_trigger_grp_yes                 = 0x00000001
+};
+#endif /* __iop_trigger_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
new file mode 100644
index 000000000000..b8d6a910c71c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
@@ -0,0 +1,99 @@
+#ifndef __iop_version_defs_h
+#define __iop_version_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
+ *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
+ *     last modfied: Mon Apr 11 16:08:44 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
+ *      id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_version */
+
+/* Register r_version, scope iop_version, type r */
+typedef struct {
+  unsigned int nr : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_version_r_version;
+#define REG_RD_ADDR_iop_version_r_version 0
+
+
+/* Constants */
+enum {
+  regk_iop_version_v1_0                    = 0x00000001
+};
+#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
new file mode 100644
index 000000000000..7b167e3c0572
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
@@ -0,0 +1,104 @@
+#ifndef __irq_nmi_defs_h
+#define __irq_nmi_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../mod/irq_nmi.r
+ *     id:           <not found>
+ *     last modfied: Thu Jan 22 09:22:43 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
+ *      id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope irq_nmi */
+
+/* Register rw_cmd, scope irq_nmi, type rw */
+typedef struct {
+  unsigned int delay : 16;
+  unsigned int op    : 2;
+  unsigned int dummy1 : 14;
+} reg_irq_nmi_rw_cmd;
+#define REG_RD_ADDR_irq_nmi_rw_cmd 0
+#define REG_WR_ADDR_irq_nmi_rw_cmd 0
+
+
+/* Constants */
+enum {
+  regk_irq_nmi_ack_irq                     = 0x00000002,
+  regk_irq_nmi_ack_nmi                     = 0x00000003,
+  regk_irq_nmi_irq                         = 0x00000000,
+  regk_irq_nmi_nmi                         = 0x00000001
+};
+#endif /* __irq_nmi_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
new file mode 100644
index 000000000000..a11fdd3cd907
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
@@ -0,0 +1,205 @@
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Fri Nov  7 15:36:04 2003
+ *
+ *   by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+  unsigned int read         : 1;
+  unsigned int write        : 1;
+  unsigned int read_excl    : 1;
+  unsigned int pri_write    : 1;
+  unsigned int us_read      : 1;
+  unsigned int us_write     : 1;
+  unsigned int us_read_excl : 1;
+  unsigned int us_pri_write : 1;
+  unsigned int dummy1       : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+  unsigned int wrap : 1;
+  unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_break_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_addr;
+#define REG_RD_ADDR_marb_bp_r_break_addr 20
+
+/* Register r_break_op, scope marb_bp, type r */
+typedef struct {
+  unsigned int read         : 1;
+  unsigned int write        : 1;
+  unsigned int read_excl    : 1;
+  unsigned int pri_write    : 1;
+  unsigned int us_read      : 1;
+  unsigned int us_write     : 1;
+  unsigned int us_read_excl : 1;
+  unsigned int us_pri_write : 1;
+  unsigned int dummy1       : 24;
+} reg_marb_bp_r_break_op;
+#define REG_RD_ADDR_marb_bp_r_break_op 24
+
+/* Register r_break_clients, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_clients;
+#define REG_RD_ADDR_marb_bp_r_break_clients 28
+
+/* Register r_break_first_client, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_first_client;
+#define REG_RD_ADDR_marb_bp_r_break_first_client 32
+
+/* Register r_break_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_size;
+#define REG_RD_ADDR_marb_bp_r_break_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+  regk_marb_bp_no                          = 0x00000000,
+  regk_marb_bp_rw_op_default               = 0x00000000,
+  regk_marb_bp_rw_options_default          = 0x00000000,
+  regk_marb_bp_yes                         = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h
new file mode 100644
index 000000000000..71e8af0bb3a4
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_defs.h
@@ -0,0 +1,475 @@
+#ifndef __marb_defs_h
+#define __marb_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb */
+
+#define STRIDE_marb_rw_int_slots 4
+/* Register rw_int_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_int_slots;
+#define REG_RD_ADDR_marb_rw_int_slots 0
+#define REG_WR_ADDR_marb_rw_int_slots 0
+
+#define STRIDE_marb_rw_ext_slots 4
+/* Register rw_ext_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_ext_slots;
+#define REG_RD_ADDR_marb_rw_ext_slots 256
+#define REG_WR_ADDR_marb_rw_ext_slots 256
+
+#define STRIDE_marb_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_regs_slots;
+#define REG_RD_ADDR_marb_rw_regs_slots 512
+#define REG_WR_ADDR_marb_rw_regs_slots 512
+
+/* Register rw_intr_mask, scope marb, type rw */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_intr_mask;
+#define REG_RD_ADDR_marb_rw_intr_mask 528
+#define REG_WR_ADDR_marb_rw_intr_mask 528
+
+/* Register rw_ack_intr, scope marb, type rw */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_ack_intr;
+#define REG_RD_ADDR_marb_rw_ack_intr 532
+#define REG_WR_ADDR_marb_rw_ack_intr 532
+
+/* Register r_intr, scope marb, type r */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_r_intr;
+#define REG_RD_ADDR_marb_r_intr 536
+
+/* Register r_masked_intr, scope marb, type r */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_r_masked_intr;
+#define REG_RD_ADDR_marb_r_masked_intr 540
+
+/* Register rw_stop_mask, scope marb, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_rw_stop_mask;
+#define REG_RD_ADDR_marb_rw_stop_mask 544
+#define REG_WR_ADDR_marb_rw_stop_mask 544
+
+/* Register r_stopped, scope marb, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_r_stopped;
+#define REG_RD_ADDR_marb_r_stopped 548
+
+/* Register rw_no_snoop, scope marb, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_rw_no_snoop;
+#define REG_RD_ADDR_marb_rw_no_snoop 832
+#define REG_WR_ADDR_marb_rw_no_snoop 832
+
+/* Register rw_no_snoop_rq, scope marb, type rw */
+typedef struct {
+  unsigned int dummy1 : 10;
+  unsigned int cpui : 1;
+  unsigned int cpud : 1;
+  unsigned int dummy2 : 20;
+} reg_marb_rw_no_snoop_rq;
+#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
+#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
+
+
+/* Constants */
+enum {
+  regk_marb_cpud                           = 0x0000000b,
+  regk_marb_cpui                           = 0x0000000a,
+  regk_marb_dma0                           = 0x00000000,
+  regk_marb_dma1                           = 0x00000001,
+  regk_marb_dma2                           = 0x00000002,
+  regk_marb_dma3                           = 0x00000003,
+  regk_marb_dma4                           = 0x00000004,
+  regk_marb_dma5                           = 0x00000005,
+  regk_marb_dma6                           = 0x00000006,
+  regk_marb_dma7                           = 0x00000007,
+  regk_marb_dma8                           = 0x00000008,
+  regk_marb_dma9                           = 0x00000009,
+  regk_marb_iop                            = 0x0000000c,
+  regk_marb_no                             = 0x00000000,
+  regk_marb_r_stopped_default              = 0x00000000,
+  regk_marb_rw_ext_slots_default           = 0x00000000,
+  regk_marb_rw_ext_slots_size              = 0x00000040,
+  regk_marb_rw_int_slots_default           = 0x00000000,
+  regk_marb_rw_int_slots_size              = 0x00000040,
+  regk_marb_rw_intr_mask_default           = 0x00000000,
+  regk_marb_rw_no_snoop_default            = 0x00000000,
+  regk_marb_rw_no_snoop_rq_default         = 0x00000000,
+  regk_marb_rw_regs_slots_default          = 0x00000000,
+  regk_marb_rw_regs_slots_size             = 0x00000004,
+  regk_marb_rw_stop_mask_default           = 0x00000000,
+  regk_marb_slave                          = 0x0000000d,
+  regk_marb_yes                            = 0x00000001
+};
+#endif /* __marb_defs_h */
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+  unsigned int rd         : 1;
+  unsigned int wr         : 1;
+  unsigned int rd_excl    : 1;
+  unsigned int pri_wr     : 1;
+  unsigned int us_rd      : 1;
+  unsigned int us_wr      : 1;
+  unsigned int us_rd_excl : 1;
+  unsigned int us_pri_wr  : 1;
+  unsigned int dummy1     : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+  unsigned int wrap : 1;
+  unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_brk_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_addr;
+#define REG_RD_ADDR_marb_bp_r_brk_addr 20
+
+/* Register r_brk_op, scope marb_bp, type r */
+typedef struct {
+  unsigned int rd         : 1;
+  unsigned int wr         : 1;
+  unsigned int rd_excl    : 1;
+  unsigned int pri_wr     : 1;
+  unsigned int us_rd      : 1;
+  unsigned int us_wr      : 1;
+  unsigned int us_rd_excl : 1;
+  unsigned int us_pri_wr  : 1;
+  unsigned int dummy1     : 24;
+} reg_marb_bp_r_brk_op;
+#define REG_RD_ADDR_marb_bp_r_brk_op 24
+
+/* Register r_brk_clients, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_clients;
+#define REG_RD_ADDR_marb_bp_r_brk_clients 28
+
+/* Register r_brk_first_client, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_first_client;
+#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
+
+/* Register r_brk_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_size;
+#define REG_RD_ADDR_marb_bp_r_brk_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+  regk_marb_bp_no                          = 0x00000000,
+  regk_marb_bp_rw_op_default               = 0x00000000,
+  regk_marb_bp_rw_options_default          = 0x00000000,
+  regk_marb_bp_yes                         = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
new file mode 100644
index 000000000000..9d91c2de1b07
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
@@ -0,0 +1,357 @@
+#ifndef __pinmux_defs_h
+#define __pinmux_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:11 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *      id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope pinmux */
+
+/* Register rw_pa, scope pinmux, type rw */
+typedef struct {
+  unsigned int pa0    : 1;
+  unsigned int pa1    : 1;
+  unsigned int pa2    : 1;
+  unsigned int pa3    : 1;
+  unsigned int pa4    : 1;
+  unsigned int pa5    : 1;
+  unsigned int pa6    : 1;
+  unsigned int pa7    : 1;
+  unsigned int csp2_n : 1;
+  unsigned int csp3_n : 1;
+  unsigned int csp5_n : 1;
+  unsigned int csp6_n : 1;
+  unsigned int hsh4   : 1;
+  unsigned int hsh5   : 1;
+  unsigned int hsh6   : 1;
+  unsigned int hsh7   : 1;
+  unsigned int dummy1 : 16;
+} reg_pinmux_rw_pa;
+#define REG_RD_ADDR_pinmux_rw_pa 0
+#define REG_WR_ADDR_pinmux_rw_pa 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+typedef struct {
+  unsigned int ser1     : 1;
+  unsigned int ser2     : 1;
+  unsigned int ser3     : 1;
+  unsigned int sser0    : 1;
+  unsigned int sser1    : 1;
+  unsigned int ata0     : 1;
+  unsigned int ata1     : 1;
+  unsigned int ata2     : 1;
+  unsigned int ata3     : 1;
+  unsigned int ata      : 1;
+  unsigned int eth1     : 1;
+  unsigned int eth1_mgm : 1;
+  unsigned int timer    : 1;
+  unsigned int p21      : 1;
+  unsigned int dummy1   : 18;
+} reg_pinmux_rw_hwprot;
+#define REG_RD_ADDR_pinmux_rw_hwprot 4
+#define REG_WR_ADDR_pinmux_rw_hwprot 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pb0  : 1;
+  unsigned int pb1  : 1;
+  unsigned int pb2  : 1;
+  unsigned int pb3  : 1;
+  unsigned int pb4  : 1;
+  unsigned int pb5  : 1;
+  unsigned int pb6  : 1;
+  unsigned int pb7  : 1;
+  unsigned int pb8  : 1;
+  unsigned int pb9  : 1;
+  unsigned int pb10 : 1;
+  unsigned int pb11 : 1;
+  unsigned int pb12 : 1;
+  unsigned int pb13 : 1;
+  unsigned int pb14 : 1;
+  unsigned int pb15 : 1;
+  unsigned int pb16 : 1;
+  unsigned int pb17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_gio;
+#define REG_RD_ADDR_pinmux_rw_pb_gio 8
+#define REG_WR_ADDR_pinmux_rw_pb_gio 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pb0  : 1;
+  unsigned int pb1  : 1;
+  unsigned int pb2  : 1;
+  unsigned int pb3  : 1;
+  unsigned int pb4  : 1;
+  unsigned int pb5  : 1;
+  unsigned int pb6  : 1;
+  unsigned int pb7  : 1;
+  unsigned int pb8  : 1;
+  unsigned int pb9  : 1;
+  unsigned int pb10 : 1;
+  unsigned int pb11 : 1;
+  unsigned int pb12 : 1;
+  unsigned int pb13 : 1;
+  unsigned int pb14 : 1;
+  unsigned int pb15 : 1;
+  unsigned int pb16 : 1;
+  unsigned int pb17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_iop;
+#define REG_RD_ADDR_pinmux_rw_pb_iop 12
+#define REG_WR_ADDR_pinmux_rw_pb_iop 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pc0  : 1;
+  unsigned int pc1  : 1;
+  unsigned int pc2  : 1;
+  unsigned int pc3  : 1;
+  unsigned int pc4  : 1;
+  unsigned int pc5  : 1;
+  unsigned int pc6  : 1;
+  unsigned int pc7  : 1;
+  unsigned int pc8  : 1;
+  unsigned int pc9  : 1;
+  unsigned int pc10 : 1;
+  unsigned int pc11 : 1;
+  unsigned int pc12 : 1;
+  unsigned int pc13 : 1;
+  unsigned int pc14 : 1;
+  unsigned int pc15 : 1;
+  unsigned int pc16 : 1;
+  unsigned int pc17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_gio;
+#define REG_RD_ADDR_pinmux_rw_pc_gio 16
+#define REG_WR_ADDR_pinmux_rw_pc_gio 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pc0  : 1;
+  unsigned int pc1  : 1;
+  unsigned int pc2  : 1;
+  unsigned int pc3  : 1;
+  unsigned int pc4  : 1;
+  unsigned int pc5  : 1;
+  unsigned int pc6  : 1;
+  unsigned int pc7  : 1;
+  unsigned int pc8  : 1;
+  unsigned int pc9  : 1;
+  unsigned int pc10 : 1;
+  unsigned int pc11 : 1;
+  unsigned int pc12 : 1;
+  unsigned int pc13 : 1;
+  unsigned int pc14 : 1;
+  unsigned int pc15 : 1;
+  unsigned int pc16 : 1;
+  unsigned int pc17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_iop;
+#define REG_RD_ADDR_pinmux_rw_pc_iop 20
+#define REG_WR_ADDR_pinmux_rw_pc_iop 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pd0  : 1;
+  unsigned int pd1  : 1;
+  unsigned int pd2  : 1;
+  unsigned int pd3  : 1;
+  unsigned int pd4  : 1;
+  unsigned int pd5  : 1;
+  unsigned int pd6  : 1;
+  unsigned int pd7  : 1;
+  unsigned int pd8  : 1;
+  unsigned int pd9  : 1;
+  unsigned int pd10 : 1;
+  unsigned int pd11 : 1;
+  unsigned int pd12 : 1;
+  unsigned int pd13 : 1;
+  unsigned int pd14 : 1;
+  unsigned int pd15 : 1;
+  unsigned int pd16 : 1;
+  unsigned int pd17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_gio;
+#define REG_RD_ADDR_pinmux_rw_pd_gio 24
+#define REG_WR_ADDR_pinmux_rw_pd_gio 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pd0  : 1;
+  unsigned int pd1  : 1;
+  unsigned int pd2  : 1;
+  unsigned int pd3  : 1;
+  unsigned int pd4  : 1;
+  unsigned int pd5  : 1;
+  unsigned int pd6  : 1;
+  unsigned int pd7  : 1;
+  unsigned int pd8  : 1;
+  unsigned int pd9  : 1;
+  unsigned int pd10 : 1;
+  unsigned int pd11 : 1;
+  unsigned int pd12 : 1;
+  unsigned int pd13 : 1;
+  unsigned int pd14 : 1;
+  unsigned int pd15 : 1;
+  unsigned int pd16 : 1;
+  unsigned int pd17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_iop;
+#define REG_RD_ADDR_pinmux_rw_pd_iop 28
+#define REG_WR_ADDR_pinmux_rw_pd_iop 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pe0  : 1;
+  unsigned int pe1  : 1;
+  unsigned int pe2  : 1;
+  unsigned int pe3  : 1;
+  unsigned int pe4  : 1;
+  unsigned int pe5  : 1;
+  unsigned int pe6  : 1;
+  unsigned int pe7  : 1;
+  unsigned int pe8  : 1;
+  unsigned int pe9  : 1;
+  unsigned int pe10 : 1;
+  unsigned int pe11 : 1;
+  unsigned int pe12 : 1;
+  unsigned int pe13 : 1;
+  unsigned int pe14 : 1;
+  unsigned int pe15 : 1;
+  unsigned int pe16 : 1;
+  unsigned int pe17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_gio;
+#define REG_RD_ADDR_pinmux_rw_pe_gio 32
+#define REG_WR_ADDR_pinmux_rw_pe_gio 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pe0  : 1;
+  unsigned int pe1  : 1;
+  unsigned int pe2  : 1;
+  unsigned int pe3  : 1;
+  unsigned int pe4  : 1;
+  unsigned int pe5  : 1;
+  unsigned int pe6  : 1;
+  unsigned int pe7  : 1;
+  unsigned int pe8  : 1;
+  unsigned int pe9  : 1;
+  unsigned int pe10 : 1;
+  unsigned int pe11 : 1;
+  unsigned int pe12 : 1;
+  unsigned int pe13 : 1;
+  unsigned int pe14 : 1;
+  unsigned int pe15 : 1;
+  unsigned int pe16 : 1;
+  unsigned int pe17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_iop;
+#define REG_RD_ADDR_pinmux_rw_pe_iop 36
+#define REG_WR_ADDR_pinmux_rw_pe_iop 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+typedef struct {
+  unsigned int en_usb0 : 1;
+  unsigned int en_usb1 : 1;
+  unsigned int dummy1  : 30;
+} reg_pinmux_rw_usb_phy;
+#define REG_RD_ADDR_pinmux_rw_usb_phy 40
+#define REG_WR_ADDR_pinmux_rw_usb_phy 40
+
+
+/* Constants */
+enum {
+  regk_pinmux_no                           = 0x00000000,
+  regk_pinmux_rw_hwprot_default            = 0x00000000,
+  regk_pinmux_rw_pa_default                = 0x00000000,
+  regk_pinmux_rw_pb_gio_default            = 0x00000000,
+  regk_pinmux_rw_pb_iop_default            = 0x00000000,
+  regk_pinmux_rw_pc_gio_default            = 0x00000000,
+  regk_pinmux_rw_pc_iop_default            = 0x00000000,
+  regk_pinmux_rw_pd_gio_default            = 0x00000000,
+  regk_pinmux_rw_pd_iop_default            = 0x00000000,
+  regk_pinmux_rw_pe_gio_default            = 0x00000000,
+  regk_pinmux_rw_pe_iop_default            = 0x00000000,
+  regk_pinmux_rw_usb_phy_default           = 0x00000000,
+  regk_pinmux_yes                          = 0x00000001
+};
+#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/hwregs/reg_map.h
new file mode 100644
index 000000000000..e31502838ec6
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_map.h
@@ -0,0 +1,103 @@
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ *   file:            ../../mod/fakereg.rmap
+ *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ *     last modified: Wed Feb 11 20:53:25 2004
+ *   file:            ../../rtl/global.rmap
+ *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ *     last modified: Mon Aug 18 17:08:23 2003
+ *   file:            ../../mod/modreg.rmap
+ *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ *     last modified: Fri Feb 20 16:40:04 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
+ *      id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+typedef enum {
+  regi_ata                                 = 0xb0032000,
+  regi_bif_core                            = 0xb0014000,
+  regi_bif_dma                             = 0xb0016000,
+  regi_bif_slave                           = 0xb0018000,
+  regi_config                              = 0xb003c000,
+  regi_dma0                                = 0xb0000000,
+  regi_dma1                                = 0xb0002000,
+  regi_dma2                                = 0xb0004000,
+  regi_dma3                                = 0xb0006000,
+  regi_dma4                                = 0xb0008000,
+  regi_dma5                                = 0xb000a000,
+  regi_dma6                                = 0xb000c000,
+  regi_dma7                                = 0xb000e000,
+  regi_dma8                                = 0xb0010000,
+  regi_dma9                                = 0xb0012000,
+  regi_eth0                                = 0xb0034000,
+  regi_eth1                                = 0xb0036000,
+  regi_gio                                 = 0xb001a000,
+  regi_iop                                 = 0xb0020000,
+  regi_iop_version                         = 0xb0020000,
+  regi_iop_fifo_in0_extra                  = 0xb0020040,
+  regi_iop_fifo_in1_extra                  = 0xb0020080,
+  regi_iop_fifo_out0_extra                 = 0xb00200c0,
+  regi_iop_fifo_out1_extra                 = 0xb0020100,
+  regi_iop_trigger_grp0                    = 0xb0020140,
+  regi_iop_trigger_grp1                    = 0xb0020180,
+  regi_iop_trigger_grp2                    = 0xb00201c0,
+  regi_iop_trigger_grp3                    = 0xb0020200,
+  regi_iop_trigger_grp4                    = 0xb0020240,
+  regi_iop_trigger_grp5                    = 0xb0020280,
+  regi_iop_trigger_grp6                    = 0xb00202c0,
+  regi_iop_trigger_grp7                    = 0xb0020300,
+  regi_iop_crc_par0                        = 0xb0020380,
+  regi_iop_crc_par1                        = 0xb0020400,
+  regi_iop_dmc_in0                         = 0xb0020480,
+  regi_iop_dmc_in1                         = 0xb0020500,
+  regi_iop_dmc_out0                        = 0xb0020580,
+  regi_iop_dmc_out1                        = 0xb0020600,
+  regi_iop_fifo_in0                        = 0xb0020680,
+  regi_iop_fifo_in1                        = 0xb0020700,
+  regi_iop_fifo_out0                       = 0xb0020780,
+  regi_iop_fifo_out1                       = 0xb0020800,
+  regi_iop_scrc_in0                        = 0xb0020880,
+  regi_iop_scrc_in1                        = 0xb0020900,
+  regi_iop_scrc_out0                       = 0xb0020980,
+  regi_iop_scrc_out1                       = 0xb0020a00,
+  regi_iop_timer_grp0                      = 0xb0020a80,
+  regi_iop_timer_grp1                      = 0xb0020b00,
+  regi_iop_timer_grp2                      = 0xb0020b80,
+  regi_iop_timer_grp3                      = 0xb0020c00,
+  regi_iop_sap_in                          = 0xb0020d00,
+  regi_iop_sap_out                         = 0xb0020e00,
+  regi_iop_spu0                            = 0xb0020f00,
+  regi_iop_spu1                            = 0xb0021000,
+  regi_iop_sw_cfg                          = 0xb0021100,
+  regi_iop_sw_cpu                          = 0xb0021200,
+  regi_iop_sw_mpu                          = 0xb0021300,
+  regi_iop_sw_spu0                         = 0xb0021400,
+  regi_iop_sw_spu1                         = 0xb0021500,
+  regi_iop_mpu                             = 0xb0021600,
+  regi_irq                                 = 0xb001c000,
+  regi_irq2                                = 0xb005c000,
+  regi_marb                                = 0xb003e000,
+  regi_marb_bp0                            = 0xb003e240,
+  regi_marb_bp1                            = 0xb003e280,
+  regi_marb_bp2                            = 0xb003e2c0,
+  regi_marb_bp3                            = 0xb003e300,
+  regi_pinmux                              = 0xb0038000,
+  regi_ser0                                = 0xb0026000,
+  regi_ser1                                = 0xb0028000,
+  regi_ser2                                = 0xb002a000,
+  regi_ser3                                = 0xb002c000,
+  regi_sser0                               = 0xb0022000,
+  regi_sser1                               = 0xb0024000,
+  regi_strcop                              = 0xb0030000,
+  regi_strmux                              = 0xb003a000,
+  regi_timer                               = 0xb001e000,
+  regi_timer2                              = 0xb005e000,
+  regi_trace                               = 0xb0040000,
+} reg_scope_instances;
+#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
new file mode 100644
index 000000000000..44e60233c68f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
@@ -0,0 +1,15 @@
+/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ *
+ * Read/write register macros used by *_defs.h
+ */
+
+#ifndef reg_rdwr_h
+#define reg_rdwr_h
+
+
+#define REG_READ(type, addr) *((volatile type *) (addr))
+
+#define REG_WRITE(type, addr, val) \
+   do { *((volatile type *) (addr)) = (val); } while(0)
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
new file mode 100644
index 000000000000..d9f0e924fb23
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
@@ -0,0 +1,173 @@
+#ifndef __rt_trace_defs_h
+#define __rt_trace_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/rt_trace/rtl/rt_regs.r
+ *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
+ *     last modfied: Mon Apr 11 16:09:14 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
+ *      id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope rt_trace */
+
+/* Register rw_cfg, scope rt_trace, type rw */
+typedef struct {
+  unsigned int en       : 1;
+  unsigned int mode     : 1;
+  unsigned int owner    : 1;
+  unsigned int wp       : 1;
+  unsigned int stall    : 1;
+  unsigned int dummy1   : 3;
+  unsigned int wp_start : 7;
+  unsigned int dummy2   : 1;
+  unsigned int wp_stop  : 7;
+  unsigned int dummy3   : 9;
+} reg_rt_trace_rw_cfg;
+#define REG_RD_ADDR_rt_trace_rw_cfg 0
+#define REG_WR_ADDR_rt_trace_rw_cfg 0
+
+/* Register rw_tap_ctrl, scope rt_trace, type rw */
+typedef struct {
+  unsigned int ack_data : 1;
+  unsigned int ack_guru : 1;
+  unsigned int dummy1   : 30;
+} reg_rt_trace_rw_tap_ctrl;
+#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
+#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
+
+/* Register r_tap_stat, scope rt_trace, type r */
+typedef struct {
+  unsigned int dav   : 1;
+  unsigned int empty : 1;
+  unsigned int dummy1 : 30;
+} reg_rt_trace_r_tap_stat;
+#define REG_RD_ADDR_rt_trace_r_tap_stat 8
+
+/* Register rw_tap_data, scope rt_trace, type rw */
+typedef unsigned int reg_rt_trace_rw_tap_data;
+#define REG_RD_ADDR_rt_trace_rw_tap_data 12
+#define REG_WR_ADDR_rt_trace_rw_tap_data 12
+
+/* Register rw_tap_hdata, scope rt_trace, type rw */
+typedef struct {
+  unsigned int op     : 4;
+  unsigned int sub_op : 4;
+  unsigned int dummy1 : 24;
+} reg_rt_trace_rw_tap_hdata;
+#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
+#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
+
+/* Register r_redir, scope rt_trace, type r */
+typedef unsigned int reg_rt_trace_r_redir;
+#define REG_RD_ADDR_rt_trace_r_redir 20
+
+
+/* Constants */
+enum {
+  regk_rt_trace_brk                        = 0x0000000c,
+  regk_rt_trace_dbg                        = 0x00000003,
+  regk_rt_trace_dbgdi                      = 0x00000004,
+  regk_rt_trace_dbgdo                      = 0x00000005,
+  regk_rt_trace_gmode                      = 0x00000000,
+  regk_rt_trace_no                         = 0x00000000,
+  regk_rt_trace_nop                        = 0x00000000,
+  regk_rt_trace_normal                     = 0x00000000,
+  regk_rt_trace_rdmem                      = 0x00000007,
+  regk_rt_trace_rdmemb                     = 0x00000009,
+  regk_rt_trace_rdpreg                     = 0x00000002,
+  regk_rt_trace_rdreg                      = 0x00000001,
+  regk_rt_trace_rdsreg                     = 0x00000003,
+  regk_rt_trace_redir                      = 0x00000006,
+  regk_rt_trace_ret                        = 0x0000000b,
+  regk_rt_trace_rw_cfg_default             = 0x00000000,
+  regk_rt_trace_trcfg                      = 0x00000001,
+  regk_rt_trace_wp                         = 0x00000001,
+  regk_rt_trace_wp0                        = 0x00000001,
+  regk_rt_trace_wp1                        = 0x00000002,
+  regk_rt_trace_wp2                        = 0x00000004,
+  regk_rt_trace_wp3                        = 0x00000008,
+  regk_rt_trace_wp4                        = 0x00000010,
+  regk_rt_trace_wp5                        = 0x00000020,
+  regk_rt_trace_wp6                        = 0x00000040,
+  regk_rt_trace_wrmem                      = 0x00000008,
+  regk_rt_trace_wrmemb                     = 0x0000000a,
+  regk_rt_trace_wrpreg                     = 0x00000005,
+  regk_rt_trace_wrreg                      = 0x00000004,
+  regk_rt_trace_wrsreg                     = 0x00000006,
+  regk_rt_trace_yes                        = 0x00000001
+};
+#endif /* __rt_trace_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h
new file mode 100644
index 000000000000..01c2fab97d43
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ser_defs.h
@@ -0,0 +1,308 @@
+#ifndef __ser_defs_h
+#define __ser_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ser/rtl/ser_regs.r
+ *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
+ *     last modfied: Mon Apr 11 16:09:21 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
+ *      id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ser */
+
+/* Register rw_tr_ctrl, scope ser, type rw */
+typedef struct {
+  unsigned int base_freq : 3;
+  unsigned int en        : 1;
+  unsigned int par       : 2;
+  unsigned int par_en    : 1;
+  unsigned int data_bits : 1;
+  unsigned int stop_bits : 1;
+  unsigned int stop      : 1;
+  unsigned int rts_delay : 3;
+  unsigned int rts_setup : 1;
+  unsigned int auto_rts  : 1;
+  unsigned int txd       : 1;
+  unsigned int auto_cts  : 1;
+  unsigned int dummy1    : 15;
+} reg_ser_rw_tr_ctrl;
+#define REG_RD_ADDR_ser_rw_tr_ctrl 0
+#define REG_WR_ADDR_ser_rw_tr_ctrl 0
+
+/* Register rw_tr_dma_en, scope ser, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_tr_dma_en;
+#define REG_RD_ADDR_ser_rw_tr_dma_en 4
+#define REG_WR_ADDR_ser_rw_tr_dma_en 4
+
+/* Register rw_rec_ctrl, scope ser, type rw */
+typedef struct {
+  unsigned int base_freq   : 3;
+  unsigned int en          : 1;
+  unsigned int par         : 2;
+  unsigned int par_en      : 1;
+  unsigned int data_bits   : 1;
+  unsigned int dma_mode    : 1;
+  unsigned int dma_err     : 1;
+  unsigned int sampling    : 1;
+  unsigned int timeout     : 3;
+  unsigned int auto_eop    : 1;
+  unsigned int half_duplex : 1;
+  unsigned int rts_n       : 1;
+  unsigned int loopback    : 1;
+  unsigned int dummy1      : 14;
+} reg_ser_rw_rec_ctrl;
+#define REG_RD_ADDR_ser_rw_rec_ctrl 8
+#define REG_WR_ADDR_ser_rw_rec_ctrl 8
+
+/* Register rw_tr_baud_div, scope ser, type rw */
+typedef struct {
+  unsigned int div : 16;
+  unsigned int dummy1 : 16;
+} reg_ser_rw_tr_baud_div;
+#define REG_RD_ADDR_ser_rw_tr_baud_div 12
+#define REG_WR_ADDR_ser_rw_tr_baud_div 12
+
+/* Register rw_rec_baud_div, scope ser, type rw */
+typedef struct {
+  unsigned int div : 16;
+  unsigned int dummy1 : 16;
+} reg_ser_rw_rec_baud_div;
+#define REG_RD_ADDR_ser_rw_rec_baud_div 16
+#define REG_WR_ADDR_ser_rw_rec_baud_div 16
+
+/* Register rw_xoff, scope ser, type rw */
+typedef struct {
+  unsigned int chr       : 8;
+  unsigned int automatic : 1;
+  unsigned int dummy1    : 23;
+} reg_ser_rw_xoff;
+#define REG_RD_ADDR_ser_rw_xoff 20
+#define REG_WR_ADDR_ser_rw_xoff 20
+
+/* Register rw_xoff_clr, scope ser, type rw */
+typedef struct {
+  unsigned int clr : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_xoff_clr;
+#define REG_RD_ADDR_ser_rw_xoff_clr 24
+#define REG_WR_ADDR_ser_rw_xoff_clr 24
+
+/* Register rw_dout, scope ser, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_ser_rw_dout;
+#define REG_RD_ADDR_ser_rw_dout 28
+#define REG_WR_ADDR_ser_rw_dout 28
+
+/* Register rs_stat_din, scope ser, type rs */
+typedef struct {
+  unsigned int data        : 8;
+  unsigned int dummy1      : 8;
+  unsigned int dav         : 1;
+  unsigned int framing_err : 1;
+  unsigned int par_err     : 1;
+  unsigned int orun        : 1;
+  unsigned int rec_err     : 1;
+  unsigned int rxd         : 1;
+  unsigned int tr_idle     : 1;
+  unsigned int tr_empty    : 1;
+  unsigned int tr_rdy      : 1;
+  unsigned int cts_n       : 1;
+  unsigned int xoff_detect : 1;
+  unsigned int rts_n       : 1;
+  unsigned int txd         : 1;
+  unsigned int dummy2      : 3;
+} reg_ser_rs_stat_din;
+#define REG_RD_ADDR_ser_rs_stat_din 32
+
+/* Register r_stat_din, scope ser, type r */
+typedef struct {
+  unsigned int data        : 8;
+  unsigned int dummy1      : 8;
+  unsigned int dav         : 1;
+  unsigned int framing_err : 1;
+  unsigned int par_err     : 1;
+  unsigned int orun        : 1;
+  unsigned int rec_err     : 1;
+  unsigned int rxd         : 1;
+  unsigned int tr_idle     : 1;
+  unsigned int tr_empty    : 1;
+  unsigned int tr_rdy      : 1;
+  unsigned int cts_n       : 1;
+  unsigned int xoff_detect : 1;
+  unsigned int rts_n       : 1;
+  unsigned int txd         : 1;
+  unsigned int dummy2      : 3;
+} reg_ser_r_stat_din;
+#define REG_RD_ADDR_ser_r_stat_din 36
+
+/* Register rw_rec_eop, scope ser, type rw */
+typedef struct {
+  unsigned int set : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_rec_eop;
+#define REG_RD_ADDR_ser_rw_rec_eop 40
+#define REG_WR_ADDR_ser_rw_rec_eop 40
+
+/* Register rw_intr_mask, scope ser, type rw */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_rw_intr_mask;
+#define REG_RD_ADDR_ser_rw_intr_mask 44
+#define REG_WR_ADDR_ser_rw_intr_mask 44
+
+/* Register rw_ack_intr, scope ser, type rw */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_rw_ack_intr;
+#define REG_RD_ADDR_ser_rw_ack_intr 48
+#define REG_WR_ADDR_ser_rw_ack_intr 48
+
+/* Register r_intr, scope ser, type r */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_r_intr;
+#define REG_RD_ADDR_ser_r_intr 52
+
+/* Register r_masked_intr, scope ser, type r */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_r_masked_intr;
+#define REG_RD_ADDR_ser_r_masked_intr 56
+
+
+/* Constants */
+enum {
+  regk_ser_active                          = 0x00000000,
+  regk_ser_bits1                           = 0x00000000,
+  regk_ser_bits2                           = 0x00000001,
+  regk_ser_bits7                           = 0x00000001,
+  regk_ser_bits8                           = 0x00000000,
+  regk_ser_del0_5                          = 0x00000000,
+  regk_ser_del1                            = 0x00000001,
+  regk_ser_del1_5                          = 0x00000002,
+  regk_ser_del2                            = 0x00000003,
+  regk_ser_del2_5                          = 0x00000004,
+  regk_ser_del3                            = 0x00000005,
+  regk_ser_del3_5                          = 0x00000006,
+  regk_ser_del4                            = 0x00000007,
+  regk_ser_even                            = 0x00000000,
+  regk_ser_ext                             = 0x00000001,
+  regk_ser_f100                            = 0x00000007,
+  regk_ser_f29_493                         = 0x00000004,
+  regk_ser_f32                             = 0x00000005,
+  regk_ser_f32_768                         = 0x00000006,
+  regk_ser_ignore                          = 0x00000001,
+  regk_ser_inactive                        = 0x00000001,
+  regk_ser_majority                        = 0x00000001,
+  regk_ser_mark                            = 0x00000002,
+  regk_ser_middle                          = 0x00000000,
+  regk_ser_no                              = 0x00000000,
+  regk_ser_odd                             = 0x00000001,
+  regk_ser_off                             = 0x00000000,
+  regk_ser_rw_intr_mask_default            = 0x00000000,
+  regk_ser_rw_rec_baud_div_default         = 0x00000000,
+  regk_ser_rw_rec_ctrl_default             = 0x00010000,
+  regk_ser_rw_tr_baud_div_default          = 0x00000000,
+  regk_ser_rw_tr_ctrl_default              = 0x00008000,
+  regk_ser_rw_tr_dma_en_default            = 0x00000000,
+  regk_ser_rw_xoff_default                 = 0x00000000,
+  regk_ser_space                           = 0x00000003,
+  regk_ser_stop                            = 0x00000000,
+  regk_ser_yes                             = 0x00000001
+};
+#endif /* __ser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h
new file mode 100644
index 000000000000..8d1dab218b91
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/sser_defs.h
@@ -0,0 +1,331 @@
+#ifndef __sser_defs_h
+#define __sser_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/syncser/rtl/sser_regs.r
+ *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
+ *     last modfied: Mon Apr 11 16:09:48 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
+ *      id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope sser */
+
+/* Register rw_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int clk_div      : 16;
+  unsigned int base_freq    : 3;
+  unsigned int gate_clk     : 1;
+  unsigned int clkgate_ctrl : 1;
+  unsigned int clkgate_in   : 1;
+  unsigned int clk_dir      : 1;
+  unsigned int clk_od_mode  : 1;
+  unsigned int out_clk_pol  : 1;
+  unsigned int out_clk_src  : 2;
+  unsigned int clk_in_sel   : 1;
+  unsigned int hold_pol     : 1;
+  unsigned int prepare      : 1;
+  unsigned int en           : 1;
+  unsigned int dummy1       : 1;
+} reg_sser_rw_cfg;
+#define REG_RD_ADDR_sser_rw_cfg 0
+#define REG_WR_ADDR_sser_rw_cfg 0
+
+/* Register rw_frm_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int wordrate       : 10;
+  unsigned int rec_delay      : 3;
+  unsigned int tr_delay       : 3;
+  unsigned int early_wend     : 1;
+  unsigned int level          : 2;
+  unsigned int type           : 1;
+  unsigned int clk_pol        : 1;
+  unsigned int fr_in_rxclk    : 1;
+  unsigned int clk_src        : 1;
+  unsigned int out_off        : 1;
+  unsigned int out_on         : 1;
+  unsigned int frame_pin_dir  : 1;
+  unsigned int frame_pin_use  : 2;
+  unsigned int status_pin_dir : 1;
+  unsigned int status_pin_use : 2;
+  unsigned int dummy1         : 1;
+} reg_sser_rw_frm_cfg;
+#define REG_RD_ADDR_sser_rw_frm_cfg 4
+#define REG_WR_ADDR_sser_rw_frm_cfg 4
+
+/* Register rw_tr_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int tr_en          : 1;
+  unsigned int stop           : 1;
+  unsigned int urun_stop      : 1;
+  unsigned int eop_stop       : 1;
+  unsigned int sample_size    : 6;
+  unsigned int sh_dir         : 1;
+  unsigned int clk_pol        : 1;
+  unsigned int clk_src        : 1;
+  unsigned int use_dma        : 1;
+  unsigned int mode           : 2;
+  unsigned int frm_src        : 1;
+  unsigned int use60958       : 1;
+  unsigned int iec60958_ckdiv : 2;
+  unsigned int rate_ctrl      : 1;
+  unsigned int use_md         : 1;
+  unsigned int dual_i2s       : 1;
+  unsigned int data_pin_use   : 2;
+  unsigned int od_mode        : 1;
+  unsigned int bulk_wspace    : 2;
+  unsigned int dummy1         : 4;
+} reg_sser_rw_tr_cfg;
+#define REG_RD_ADDR_sser_rw_tr_cfg 8
+#define REG_WR_ADDR_sser_rw_tr_cfg 8
+
+/* Register rw_rec_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int rec_en          : 1;
+  unsigned int force_eop       : 1;
+  unsigned int stop            : 1;
+  unsigned int orun_stop       : 1;
+  unsigned int eop_stop        : 1;
+  unsigned int sample_size     : 6;
+  unsigned int sh_dir          : 1;
+  unsigned int clk_pol         : 1;
+  unsigned int clk_src         : 1;
+  unsigned int use_dma         : 1;
+  unsigned int mode            : 2;
+  unsigned int frm_src         : 2;
+  unsigned int use60958        : 1;
+  unsigned int iec60958_ui_len : 5;
+  unsigned int slave2_en       : 1;
+  unsigned int slave3_en       : 1;
+  unsigned int fifo_thr        : 2;
+  unsigned int dummy1          : 3;
+} reg_sser_rw_rec_cfg;
+#define REG_RD_ADDR_sser_rw_rec_cfg 12
+#define REG_WR_ADDR_sser_rw_rec_cfg 12
+
+/* Register rw_tr_data, scope sser, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int md   : 1;
+  unsigned int dummy1 : 15;
+} reg_sser_rw_tr_data;
+#define REG_RD_ADDR_sser_rw_tr_data 16
+#define REG_WR_ADDR_sser_rw_tr_data 16
+
+/* Register r_rec_data, scope sser, type r */
+typedef struct {
+  unsigned int data      : 16;
+  unsigned int md        : 1;
+  unsigned int ext_clk   : 1;
+  unsigned int status_in : 1;
+  unsigned int frame_in  : 1;
+  unsigned int din       : 1;
+  unsigned int data_in   : 1;
+  unsigned int clk_in    : 1;
+  unsigned int dummy1    : 9;
+} reg_sser_r_rec_data;
+#define REG_RD_ADDR_sser_r_rec_data 20
+
+/* Register rw_extra, scope sser, type rw */
+typedef struct {
+  unsigned int clkoff_cycles : 20;
+  unsigned int clkoff_en     : 1;
+  unsigned int clkon_en      : 1;
+  unsigned int dout_delay    : 5;
+  unsigned int dummy1        : 5;
+} reg_sser_rw_extra;
+#define REG_RD_ADDR_sser_rw_extra 24
+#define REG_WR_ADDR_sser_rw_extra 24
+
+/* Register rw_intr_mask, scope sser, type rw */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_rw_intr_mask;
+#define REG_RD_ADDR_sser_rw_intr_mask 28
+#define REG_WR_ADDR_sser_rw_intr_mask 28
+
+/* Register rw_ack_intr, scope sser, type rw */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_rw_ack_intr;
+#define REG_RD_ADDR_sser_rw_ack_intr 32
+#define REG_WR_ADDR_sser_rw_ack_intr 32
+
+/* Register r_intr, scope sser, type r */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_r_intr;
+#define REG_RD_ADDR_sser_r_intr 36
+
+/* Register r_masked_intr, scope sser, type r */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_r_masked_intr;
+#define REG_RD_ADDR_sser_r_masked_intr 40
+
+
+/* Constants */
+enum {
+  regk_sser_both                           = 0x00000002,
+  regk_sser_bulk                           = 0x00000001,
+  regk_sser_clk100                         = 0x00000000,
+  regk_sser_clk_in                         = 0x00000000,
+  regk_sser_const0                         = 0x00000003,
+  regk_sser_dout                           = 0x00000002,
+  regk_sser_edge                           = 0x00000000,
+  regk_sser_ext                            = 0x00000001,
+  regk_sser_ext_clk                        = 0x00000001,
+  regk_sser_f100                           = 0x00000000,
+  regk_sser_f29_493                        = 0x00000004,
+  regk_sser_f32                            = 0x00000005,
+  regk_sser_f32_768                        = 0x00000006,
+  regk_sser_frm                            = 0x00000003,
+  regk_sser_gio0                           = 0x00000000,
+  regk_sser_gio1                           = 0x00000001,
+  regk_sser_hispeed                        = 0x00000001,
+  regk_sser_hold                           = 0x00000002,
+  regk_sser_in                             = 0x00000000,
+  regk_sser_inf                            = 0x00000003,
+  regk_sser_intern                         = 0x00000000,
+  regk_sser_intern_clk                     = 0x00000001,
+  regk_sser_intern_tb                      = 0x00000000,
+  regk_sser_iso                            = 0x00000000,
+  regk_sser_level                          = 0x00000001,
+  regk_sser_lospeed                        = 0x00000000,
+  regk_sser_lsbfirst                       = 0x00000000,
+  regk_sser_msbfirst                       = 0x00000001,
+  regk_sser_neg                            = 0x00000001,
+  regk_sser_neg_lo                         = 0x00000000,
+  regk_sser_no                             = 0x00000000,
+  regk_sser_no_clk                         = 0x00000007,
+  regk_sser_nojitter                       = 0x00000002,
+  regk_sser_out                            = 0x00000001,
+  regk_sser_pos                            = 0x00000000,
+  regk_sser_pos_hi                         = 0x00000001,
+  regk_sser_rec                            = 0x00000000,
+  regk_sser_rw_cfg_default                 = 0x00000000,
+  regk_sser_rw_extra_default               = 0x00000000,
+  regk_sser_rw_frm_cfg_default             = 0x00000000,
+  regk_sser_rw_intr_mask_default           = 0x00000000,
+  regk_sser_rw_rec_cfg_default             = 0x00000000,
+  regk_sser_rw_tr_cfg_default              = 0x01800000,
+  regk_sser_rw_tr_data_default             = 0x00000000,
+  regk_sser_thr16                          = 0x00000001,
+  regk_sser_thr32                          = 0x00000002,
+  regk_sser_thr8                           = 0x00000000,
+  regk_sser_tr                             = 0x00000001,
+  regk_sser_ts_out                         = 0x00000003,
+  regk_sser_tx_bulk                        = 0x00000002,
+  regk_sser_wiresave                       = 0x00000002,
+  regk_sser_yes                            = 0x00000001
+};
+#endif /* __sser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h
new file mode 100644
index 000000000000..35131ba466f3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop.h
@@ -0,0 +1,57 @@
+// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
+
+// Streamcop meta-data configuration structs
+
+struct strcop_meta_out {
+        unsigned char  csumsel  : 3;
+        unsigned char  ciphsel  : 3;
+        unsigned char  ciphconf : 2;
+        unsigned char  hashsel  : 3;
+        unsigned char  hashconf : 1;
+        unsigned char  hashmode : 1;
+        unsigned char  decrypt  : 1;
+        unsigned char  dlkey    : 1;
+        unsigned char  cbcmode  : 1;
+};
+
+struct strcop_meta_in {
+        unsigned char  dmasel     : 3;
+        unsigned char  sync       : 1;
+        unsigned char  res1       : 5;
+        unsigned char  res2;
+};
+
+// Source definitions
+
+enum {
+        src_none = 0,
+        src_dma  = 1,
+        src_des  = 2,
+        src_sha1 = 3,
+        src_csum = 4,
+        src_aes  = 5,
+        src_md5  = 6,
+        src_res  = 7
+};
+
+// Cipher definitions
+
+enum {
+        ciph_des = 0,
+        ciph_3des = 1,
+        ciph_aes = 2
+};
+
+// Hash definitions
+
+enum {
+        hash_sha1 = 0,
+        hash_md5 = 1
+};
+
+enum {
+        hash_noiv = 0,
+        hash_iv = 1
+};
+
+
diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
new file mode 100644
index 000000000000..bd145a49b2c4
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
@@ -0,0 +1,109 @@
+#ifndef __strcop_defs_h
+#define __strcop_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strcop/rtl/strcop_regs.r
+ *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
+ *     last modfied: Mon Apr 11 16:09:38 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
+ *      id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strcop */
+
+/* Register rw_cfg, scope strcop, type rw */
+typedef struct {
+  unsigned int td3         : 1;
+  unsigned int td2         : 1;
+  unsigned int td1         : 1;
+  unsigned int ipend       : 1;
+  unsigned int ignore_sync : 1;
+  unsigned int en          : 1;
+  unsigned int dummy1      : 26;
+} reg_strcop_rw_cfg;
+#define REG_RD_ADDR_strcop_rw_cfg 0
+#define REG_WR_ADDR_strcop_rw_cfg 0
+
+
+/* Constants */
+enum {
+  regk_strcop_big                          = 0x00000001,
+  regk_strcop_d                            = 0x00000001,
+  regk_strcop_e                            = 0x00000000,
+  regk_strcop_little                       = 0x00000000,
+  regk_strcop_rw_cfg_default               = 0x00000002
+};
+#endif /* __strcop_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
new file mode 100644
index 000000000000..67474855c499
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
@@ -0,0 +1,127 @@
+#ifndef __strmux_defs_h
+#define __strmux_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
+ *     last modfied: Mon Apr 11 16:09:43 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *      id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strmux */
+
+/* Register rw_cfg, scope strmux, type rw */
+typedef struct {
+  unsigned int dma0 : 3;
+  unsigned int dma1 : 3;
+  unsigned int dma2 : 3;
+  unsigned int dma3 : 3;
+  unsigned int dma4 : 3;
+  unsigned int dma5 : 3;
+  unsigned int dma6 : 3;
+  unsigned int dma7 : 3;
+  unsigned int dma8 : 3;
+  unsigned int dma9 : 3;
+  unsigned int dummy1 : 2;
+} reg_strmux_rw_cfg;
+#define REG_RD_ADDR_strmux_rw_cfg 0
+#define REG_WR_ADDR_strmux_rw_cfg 0
+
+
+/* Constants */
+enum {
+  regk_strmux_ata                          = 0x00000003,
+  regk_strmux_eth0                         = 0x00000001,
+  regk_strmux_eth1                         = 0x00000004,
+  regk_strmux_ext0                         = 0x00000001,
+  regk_strmux_ext1                         = 0x00000001,
+  regk_strmux_ext2                         = 0x00000001,
+  regk_strmux_ext3                         = 0x00000001,
+  regk_strmux_iop0                         = 0x00000002,
+  regk_strmux_iop1                         = 0x00000001,
+  regk_strmux_off                          = 0x00000000,
+  regk_strmux_p21                          = 0x00000004,
+  regk_strmux_rw_cfg_default               = 0x00000000,
+  regk_strmux_ser0                         = 0x00000002,
+  regk_strmux_ser1                         = 0x00000002,
+  regk_strmux_ser2                         = 0x00000004,
+  regk_strmux_ser3                         = 0x00000003,
+  regk_strmux_sser0                        = 0x00000003,
+  regk_strmux_sser1                        = 0x00000003,
+  regk_strmux_strcop                       = 0x00000002
+};
+#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h
new file mode 100644
index 000000000000..ffe49625ae36
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/supp_reg.h
@@ -0,0 +1,78 @@
+#ifndef __SUPP_REG_H__
+#define __SUPP_REG_H__
+
+/* Macros for reading and writing support/special registers. */
+
+#ifndef STRINGIFYFY
+#define STRINGIFYFY(i) #i
+#endif
+
+#ifndef STRINGIFY
+#define STRINGIFY(i) STRINGIFYFY(i)
+#endif
+
+#define SPEC_REG_BZ     "BZ"
+#define SPEC_REG_VR     "VR"
+#define SPEC_REG_PID    "PID"
+#define SPEC_REG_SRS    "SRS"
+#define SPEC_REG_WZ     "WZ"
+#define SPEC_REG_EXS    "EXS"
+#define SPEC_REG_EDA    "EDA"
+#define SPEC_REG_MOF    "MOF"
+#define SPEC_REG_DZ     "DZ"
+#define SPEC_REG_EBP    "EBP"
+#define SPEC_REG_ERP    "ERP"
+#define SPEC_REG_SRP    "SRP"
+#define SPEC_REG_NRP    "NRP"
+#define SPEC_REG_CCS    "CCS"
+#define SPEC_REG_USP    "USP"
+#define SPEC_REG_SPC    "SPC"
+
+#define RW_MM_CFG       0
+#define RW_MM_KBASE_LO  1
+#define RW_MM_KBASE_HI  2
+#define RW_MM_CAUSE     3
+#define RW_MM_TLB_SEL   4
+#define RW_MM_TLB_LO    5
+#define RW_MM_TLB_HI    6
+#define RW_MM_TLB_PGD   7
+
+#define BANK_GC         0
+#define BANK_IM         1
+#define BANK_DM         2
+#define BANK_BP         3
+
+#define RW_GC_CFG       0
+#define RW_GC_CCS       1
+#define RW_GC_SRS       2
+#define RW_GC_NRP       3
+#define RW_GC_EXS       4
+#define RW_GC_R0        8
+#define RW_GC_R1        9
+
+#define SPEC_REG_WR(r,v) \
+__asm__ __volatile__ ("move %0, $" r : : "r" (v));
+
+#define SPEC_REG_RD(r,v) \
+__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
+
+#define NOP() \
+        __asm__ __volatile__ ("nop");
+
+#define SUPP_BANK_SEL(b)                \
+        SPEC_REG_WR(SPEC_REG_SRS,b);    \
+        NOP();                          \
+        NOP();                          \
+        NOP();
+
+#define SUPP_REG_WR(r,v) \
+__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t"       \
+                      "nop\n\t"                                 \
+                      "nop\n\t"                                 \
+                      "nop\n\t"                                 \
+                      : : "r" (v));
+
+#define SUPP_REG_RD(r,v) \
+__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
+
+#endif /* __SUPP_REG_H__ */
diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/hwregs/timer_defs.h
new file mode 100644
index 000000000000..20c8c89ec076
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/timer_defs.h
@@ -0,0 +1,266 @@
+#ifndef __timer_defs_h
+#define __timer_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/timer/rtl/timer_regs.r
+ *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:53 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
+ *      id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+            (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+             (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope timer */
+
+/* Register rw_tmr0_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr0_div;
+#define REG_RD_ADDR_timer_rw_tmr0_div 0
+#define REG_WR_ADDR_timer_rw_tmr0_div 0
+
+/* Register r_tmr0_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr0_data;
+#define REG_RD_ADDR_timer_r_tmr0_data 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int op   : 2;
+  unsigned int freq : 3;
+  unsigned int dummy1 : 27;
+} reg_timer_rw_tmr0_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
+#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr1_div;
+#define REG_RD_ADDR_timer_rw_tmr1_div 16
+#define REG_WR_ADDR_timer_rw_tmr1_div 16
+
+/* Register r_tmr1_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr1_data;
+#define REG_RD_ADDR_timer_r_tmr1_data 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int op   : 2;
+  unsigned int freq : 3;
+  unsigned int dummy1 : 27;
+} reg_timer_rw_tmr1_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
+#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+typedef struct {
+  unsigned int tmr : 24;
+  unsigned int cnt : 8;
+} reg_timer_rs_cnt_data;
+#define REG_RD_ADDR_timer_rs_cnt_data 32
+
+/* Register r_cnt_data, scope timer, type r */
+typedef struct {
+  unsigned int tmr : 24;
+  unsigned int cnt : 8;
+} reg_timer_r_cnt_data;
+#define REG_RD_ADDR_timer_r_cnt_data 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+typedef struct {
+  unsigned int clk : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_cnt_cfg;
+#define REG_RD_ADDR_timer_rw_cnt_cfg 40
+#define REG_WR_ADDR_timer_rw_cnt_cfg 40
+
+/* Register rw_trig, scope timer, type rw */
+typedef unsigned int reg_timer_rw_trig;
+#define REG_RD_ADDR_timer_rw_trig 48
+#define REG_WR_ADDR_timer_rw_trig 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+typedef struct {
+  unsigned int tmr : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_trig_cfg;
+#define REG_RD_ADDR_timer_rw_trig_cfg 52
+#define REG_WR_ADDR_timer_rw_trig_cfg 52
+
+/* Register r_time, scope timer, type r */
+typedef unsigned int reg_timer_r_time;
+#define REG_RD_ADDR_timer_r_time 56
+
+/* Register rw_out, scope timer, type rw */
+typedef struct {
+  unsigned int tmr : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_out;
+#define REG_RD_ADDR_timer_rw_out 60
+#define REG_WR_ADDR_timer_rw_out 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int cnt : 8;
+  unsigned int cmd : 1;
+  unsigned int key : 7;
+  unsigned int dummy1 : 16;
+} reg_timer_rw_wd_ctrl;
+#define REG_RD_ADDR_timer_rw_wd_ctrl 64
+#define REG_WR_ADDR_timer_rw_wd_ctrl 64
+
+/* Register r_wd_stat, scope timer, type r */
+typedef struct {
+  unsigned int cnt : 8;
+  unsigned int cmd : 1;
+  unsigned int dummy1 : 23;
+} reg_timer_r_wd_stat;
+#define REG_RD_ADDR_timer_r_wd_stat 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_rw_intr_mask;
+#define REG_RD_ADDR_timer_rw_intr_mask 72
+#define REG_WR_ADDR_timer_rw_intr_mask 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_rw_ack_intr;
+#define REG_RD_ADDR_timer_rw_ack_intr 76
+#define REG_WR_ADDR_timer_rw_ack_intr 76
+
+/* Register r_intr, scope timer, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_r_intr;
+#define REG_RD_ADDR_timer_r_intr 80
+
+/* Register r_masked_intr, scope timer, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_r_masked_intr;
+#define REG_RD_ADDR_timer_r_masked_intr 84
+
+/* Register rw_test, scope timer, type rw */
+typedef struct {
+  unsigned int dis : 1;
+  unsigned int en  : 1;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_test;
+#define REG_RD_ADDR_timer_rw_test 88
+#define REG_WR_ADDR_timer_rw_test 88
+
+
+/* Constants */
+enum {
+  regk_timer_ext                           = 0x00000001,
+  regk_timer_f100                          = 0x00000007,
+  regk_timer_f29_493                       = 0x00000004,
+  regk_timer_f32                           = 0x00000005,
+  regk_timer_f32_768                       = 0x00000006,
+  regk_timer_hold                          = 0x00000001,
+  regk_timer_ld                            = 0x00000000,
+  regk_timer_no                            = 0x00000000,
+  regk_timer_off                           = 0x00000000,
+  regk_timer_run                           = 0x00000002,
+  regk_timer_rw_cnt_cfg_default            = 0x00000000,
+  regk_timer_rw_intr_mask_default          = 0x00000000,
+  regk_timer_rw_out_default                = 0x00000000,
+  regk_timer_rw_test_default               = 0x00000000,
+  regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
+  regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
+  regk_timer_rw_trig_cfg_default           = 0x00000000,
+  regk_timer_start                         = 0x00000001,
+  regk_timer_stop                          = 0x00000000,
+  regk_timer_time                          = 0x00000001,
+  regk_timer_tmr0                          = 0x00000002,
+  regk_timer_tmr1                          = 0x00000003,
+  regk_timer_yes                           = 0x00000001
+};
+#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/ide.h b/include/asm-cris/arch-v32/ide.h
new file mode 100644
index 000000000000..24f5604f566a
--- /dev/null
+++ b/include/asm-cris/arch-v32/ide.h
@@ -0,0 +1,61 @@
+/*
+ *  linux/include/asm-cris/ide.h
+ *
+ *  Copyright (C) 2000-2004  Axis Communications AB
+ *
+ *  Authors:    Bjorn Wesen, Mikael Starvik
+ *
+ */
+
+/*
+ *  This file contains the ETRAX FS specific IDE code.
+ */
+
+#ifndef __ASMCRIS_IDE_H
+#define __ASMCRIS_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/arch/hwregs/intr_vect.h>
+#include <asm/arch/hwregs/ata_defs.h>
+#include <asm/io.h>
+#include <asm-generic/ide_iops.h>
+
+
+/* ETRAX FS can support 4 IDE busses on the same pins (serialized) */
+
+#define MAX_HWIFS       4
+
+extern __inline__ int ide_default_irq(unsigned long base)
+{
+        /* all IDE busses share the same IRQ,
+         * this has the side-effect that ide-probe.c will cluster our 4 interfaces
+         * together in a hwgroup, and will serialize accesses. this is good, because
+         * we can't access more than one interface at the same time on ETRAX100.
+         */
+        return ATA_INTR_VECT;
+}
+
+extern __inline__ unsigned long ide_default_io_base(int index)
+{
+        reg_ata_rw_ctrl2 ctrl2 = {.sel = index};
+        /* we have no real I/O base address per interface, since all go through the
+         * same register. but in a bitfield in that register, we have the i/f number.
+         * so we can use the io_base to remember that bitfield.
+         */
+        ctrl2.sel = index;
+
+        return REG_TYPE_CONV(unsigned long, reg_ata_rw_ctrl2, ctrl2);
+}
+
+/* some configuration options we don't need */
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#define IDE_ARCH_ACK_INTR
+#define ide_ack_intr(hwif)      (hwif)->hw.ack_intr(hwif)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h
new file mode 100644
index 000000000000..c0ada33bf90f
--- /dev/null
+++ b/include/asm-cris/arch-v32/intmem.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_INTMEM_H
+#define _ASM_CRIS_INTMEM_H
+
+void* crisv32_intmem_alloc(unsigned size, unsigned align);
+void crisv32_intmem_free(void* addr);
+void* crisv32_intmem_phys_to_virt(unsigned long addr);
+unsigned long crisv32_intmem_virt_to_phys(void *addr);
+
+#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h
new file mode 100644
index 000000000000..4c80263ec634
--- /dev/null
+++ b/include/asm-cris/arch-v32/io.h
@@ -0,0 +1,98 @@
+#ifndef _ASM_ARCH_CRIS_IO_H
+#define _ASM_ARCH_CRIS_IO_H
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/gio_defs.h>
+#include <linux/config.h>
+
+enum crisv32_io_dir
+{
+  crisv32_io_dir_in = 0,
+  crisv32_io_dir_out = 1
+};
+
+struct crisv32_ioport
+{
+  unsigned long* oe;
+  unsigned long* data;
+  unsigned long* data_in;
+  unsigned int pin_count;
+};
+
+struct crisv32_iopin
+{
+  struct crisv32_ioport* port;
+  int bit;
+};
+
+extern struct crisv32_ioport crisv32_ioports[];
+
+extern struct crisv32_iopin crisv32_led1_green;
+extern struct crisv32_iopin crisv32_led1_red;
+extern struct crisv32_iopin crisv32_led2_green;
+extern struct crisv32_iopin crisv32_led2_red;
+extern struct crisv32_iopin crisv32_led3_green;
+extern struct crisv32_iopin crisv32_led3_red;
+
+extern inline void crisv32_io_set(struct crisv32_iopin* iopin,
+                           int val)
+{
+        if (val)
+                *iopin->port->data |= iopin->bit;
+        else
+                *iopin->port->data &= ~iopin->bit;
+}
+
+extern inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
+                               enum crisv32_io_dir dir)
+{
+        if (dir == crisv32_io_dir_in)
+                *iopin->port->oe &= ~iopin->bit;
+        else
+                *iopin->port->oe |= iopin->bit;
+}
+
+extern inline int crisv32_io_rd(struct crisv32_iopin* iopin)
+{
+        return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
+}
+
+int crisv32_io_get(struct crisv32_iopin* iopin,
+                   unsigned int port, unsigned int pin);
+int crisv32_io_get_name(struct crisv32_iopin* iopin,
+                         char* name);
+
+#define LED_OFF    0x00
+#define LED_GREEN  0x01
+#define LED_RED    0x02
+#define LED_ORANGE (LED_GREEN | LED_RED)
+
+#define LED_NETWORK_SET(x)                          \
+        do {                                        \
+                LED_NETWORK_SET_G((x) & LED_GREEN); \
+                LED_NETWORK_SET_R((x) & LED_RED);   \
+        } while (0)
+#define LED_ACTIVE_SET(x)                           \
+        do {                                        \
+                LED_ACTIVE_SET_G((x) & LED_GREEN);  \
+                LED_ACTIVE_SET_R((x) & LED_RED);    \
+        } while (0)
+
+#define LED_NETWORK_SET_G(x) \
+        crisv32_io_set(&crisv32_led1_green, !(x));
+#define LED_NETWORK_SET_R(x) \
+        crisv32_io_set(&crisv32_led1_red, !(x));
+#define LED_ACTIVE_SET_G(x) \
+        crisv32_io_set(&crisv32_led2_green, !(x));
+#define LED_ACTIVE_SET_R(x) \
+        crisv32_io_set(&crisv32_led2_red, !(x));
+#define LED_DISK_WRITE(x) \
+         do{\
+                crisv32_io_set(&crisv32_led3_green, !(x)); \
+                crisv32_io_set(&crisv32_led3_red, !(x));   \
+        }while(0)
+#define LED_DISK_READ(x) \
+        crisv32_io_set(&crisv32_led3_green, !(x));
+
+#endif
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h
new file mode 100644
index 000000000000..d35aa8174c2f
--- /dev/null
+++ b/include/asm-cris/arch-v32/irq.h
@@ -0,0 +1,120 @@
+#ifndef _ASM_ARCH_IRQ_H
+#define _ASM_ARCH_IRQ_H
+
+#include <linux/config.h>
+#include "hwregs/intr_vect.h"
+
+/* Number of non-cpu interrupts. */
+#define NR_IRQS 0x50 /* Exceptions + IRQs */
+#define NR_REAL_IRQS 0x20 /* IRQs */
+#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
+
+#ifndef __ASSEMBLY__
+/* Global IRQ vector. */
+typedef void (*irqvectptr)(void);
+
+struct etrax_interrupt_vector {
+        irqvectptr v[256];
+};
+
+extern struct etrax_interrupt_vector *etrax_irv;        /* head.S */
+
+void mask_irq(int irq);
+void unmask_irq(int irq);
+
+void set_exception_vector(int n, irqvectptr addr);
+
+/* Save registers so that they match pt_regs. */
+#define SAVE_ALL \
+        "subq 12,$sp\n\t"       \
+        "move $erp,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move $srp,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move $ccs,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move $spc,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move $mof,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move $srs,[$sp]\n\t"   \
+        "subq 4,$sp\n\t"        \
+        "move.d $acr,[$sp]\n\t" \
+        "subq 14*4,$sp\n\t"     \
+        "movem $r13,[$sp]\n\t"  \
+        "subq 4,$sp\n\t"        \
+        "move.d $r10,[$sp]\n"
+
+#define STR2(x) #x
+#define STR(x) STR2(x)
+
+#define IRQ_NAME2(nr) nr##_interrupt(void)
+#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
+
+/*
+ * The reason for setting the S-bit when debugging the kernel is that we want
+ * hardware breakpoints to remain active while we are in an exception handler.
+ * Note that we cannot simply copy S1, since we may come here from user-space,
+ * or any context where the S-bit wasn't set.
+ */
+#ifdef CONFIG_ETRAX_KGDB
+#define KGDB_FIXUP \
+        "move $ccs, $r10\n\t"           \
+        "or.d (1<<9), $r10\n\t"         \
+        "move $r10, $ccs\n\t"
+#else
+#define KGDB_FIXUP ""
+#endif
+
+/*
+ * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
+ * and jump to ret_from_intr which is found in entry.S.
+ *
+ * The reason for blocking the IRQ is to allow an sti() before the handler,
+ * which will acknowledge the interrupt, is run. The actual blocking is made
+ * by crisv32_do_IRQ.
+ */
+#define BUILD_IRQ(nr, mask)             \
+void IRQ_NAME(nr);                      \
+__asm__ (                               \
+        ".text\n\t"                     \
+        "IRQ" #nr "_interrupt:\n\t"     \
+        SAVE_ALL                        \
+        KGDB_FIXUP                      \
+        "move.d "#nr",$r10\n\t"         \
+        "move.d $sp,$r12\n\t"           \
+        "jsr crisv32_do_IRQ\n\t"        \
+        "moveq 1, $r11\n\t"             \
+        "jump ret_from_intr\n\t"        \
+        "nop\n\t");
+/*
+ * This is subtle. The timer interrupt is crucial and it should not be disabled
+ * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
+ * would have been BLOCK'ed, and then softirq's are run before we return here to
+ * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
+ * and the watchdog will kill us.
+ *
+ * Furthermore, if a lot of other irq's occur before we return here, the
+ * multiple_irq handler is run and it prioritizes the timer interrupt. However
+ * if we had BLOCK'edit here, we would not get the multiple_irq at all.
+ *
+ * The non-blocking here is based on the knowledge that the timer interrupt is
+ * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not
+ * be an sti() before the timer irq handler is run to acknowledge the interrupt.
+ */
+#define BUILD_TIMER_IRQ(nr, mask)       \
+void IRQ_NAME(nr);                      \
+__asm__ (                               \
+        ".text\n\t"                     \
+        "IRQ" #nr "_interrupt:\n\t"     \
+        SAVE_ALL                        \
+        KGDB_FIXUP                      \
+        "move.d "#nr",$r10\n\t"         \
+        "move.d $sp,$r12\n\t"           \
+        "jsr crisv32_do_IRQ\n\t"        \
+        "moveq 0,$r11\n\t"              \
+        "jump ret_from_intr\n\t"        \
+        "nop\n\t");
+
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_ARCH_IRQ_H */
diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h
new file mode 100644
index 000000000000..f1f81725e57b
--- /dev/null
+++ b/include/asm-cris/arch-v32/juliette.h
@@ -0,0 +1,326 @@
+#ifndef _ASM_JULIETTE_H
+#define _ASM_JULIETTE_H
+
+/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */
+
+#define JULIOCTYPE 42
+
+/* supported ioctl _IOC_NR's */
+
+#define JULSTARTDMA      0x1        /* start a picture asynchronously */
+
+/* set parameters */
+
+#define SETDEFAULT        0x2 /* CCD/VIDEO/SS1M */
+#define SETPARAMETERS     0x3 /* CCD/VIDEO      */
+#define SETSIZE           0x4 /* CCD/VIDEO/SS1M */
+#define SETCOMPRESSION    0x5 /* CCD/VIDEO/SS1M */
+#define SETCOLORLEVEL     0x6 /* CCD/VIDEO      */
+#define SETBRIGHTNESS     0x7 /* CCD            */
+#define SETROTATION       0x8 /* CCD            */
+#define SETTEXT           0x9 /* CCD/VIDEO/SS1M */
+#define SETCLOCK          0xa /* CCD/VIDEO/SS1M */
+#define SETDATE           0xb /* CCD/VIDEO/SS1M */
+#define SETTIMEFORMAT     0xc /* CCD/VIDEO/SS1M */
+#define SETDATEFORMAT     0xd /*     VIDEO      */
+#define SETTEXTALIGNMENT  0xe /*     VIDEO      */
+#define SETFPS            0xf /* CCD/VIDEO/SS1M */
+#define SETVGA           0xff /*     VIDEO      */
+#define SETCOMMENT       0xfe /* CCD/VIDEO      */
+
+/* get parameters */
+
+#define GETDRIVERTYPE    0x10 /* CCD/VIDEO/SS1M */
+#define GETNBROFCAMERAS  0x11 /* CCD/VIDEO/SS1M */
+#define GETPARAMETERS    0x12 /* CCD/VIDEO/SS1M */
+#define GETBUFFERSIZE    0x13 /* CCD/VIDEO/SS1M */
+#define GETVIDEOTYPE     0x14 /*     VIDEO/SS1M */
+#define GETVIDEOSIGNAL   0x15 /*     VIDEO      */
+#define GETMODULATION    0x16 /*     VIDEO      */
+#define GETDCYVALUES     0xa0 /* CCD      /SS1M */
+#define GETDCYWIDTH      0xa1 /* CCD      /SS1M */
+#define GETDCYHEIGHT     0xa2 /* CCD      /SS1M */
+#define GETSIZE          0xa3 /* CCD/VIDEO      */
+#define GETCOMPRESSION   0xa4 /* CCD/VIDEO      */
+
+/* detect and get parameters */
+
+#define DETECTMODULATION  0x17 /*     VIDEO      */
+#define DETECTVIDEOTYPE   0x18 /*     VIDEO      */
+#define DETECTVIDEOSIGNAL 0x19 /*     VIDEO      */
+
+/* configure default parameters */
+
+#define CONFIGUREDEFAULT  0x20 /* CCD/VIDEO/SS1M */
+#define DEFSIZE           0x21 /* CCD/VIDEO/SS1M */
+#define DEFCOMPRESSION    0x22 /* CCD/VIDEO/SS1M */
+#define DEFCOLORLEVEL     0x23 /* CCD/VIDEO      */
+#define DEFBRIGHTNESS     0x24 /* CCD            */
+#define DEFROTATION       0x25 /* CCD            */
+#define DEFWHITEBALANCE   0x26 /* CCD            */
+#define DEFEXPOSURE       0x27 /* CCD            */
+#define DEFAUTOEXPWINDOW  0x28 /* CCD            */
+#define DEFTEXT           0x29 /* CCD/VIDEO/SS1M */
+#define DEFCLOCK          0x2a /* CCD/VIDEO/SS1M */
+#define DEFDATE           0x2b /* CCD/VIDEO/SS1M */
+#define DEFTIMEFORMAT     0x2c /* CCD/VIDEO/SS1M */
+#define DEFDATEFORMAT     0x2d /*     VIDEO      */
+#define DEFTEXTALIGNMENT  0x2e /*     VIDEO      */
+#define DEFFPS            0x2f /* CCD/VIDEO/SS1M */
+#define DEFTEXTSTRING     0x30 /* CCD/VIDEO/SS1M */
+#define DEFHEADERINFO     0x31 /* CCD/VIDEO/SS1M */
+#define DEFWEXAR          0x32 /* CCD            */
+#define DEFLINEDELAY      0x33 /* CCD            */
+#define DEFDISABLEDVIDEO  0x34 /*     VIDEO      */
+#define DEFVIDEOTYPE      0x35 /*     VIDEO      */
+#define DEFMODULATION     0x36 /*     VIDEO      */
+#define DEFXOFFSET        0x37 /*     VIDEO      */
+#define DEFYOFFSET        0x38 /*     VIDEO      */
+#define DEFYCMODE         0x39 /*     VIDEO      */
+#define DEFVCRMODE        0x3a /*     VIDEO      */
+#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */
+#define DEFWCDS           0x3c /* CCD            */
+#define DEFVGA            0x3d /*     VIDEO      */
+#define DEFCOMMENT        0x3e /* CCD/VIDEO      */
+#define DEFCOMMENTSIZE    0x3f /* CCD/VIDEO      */
+#define DEFCOMMENTTEXT    0x50 /* CCD/VIDEO      */
+#define DEFSTOREDCYTEXT   0x51 /*     VIDEO      */
+
+
+#define JULABORTDMA       0x70 /* Abort current DMA transfer */
+
+/* juliette general i/o port */
+
+#define JIO_READBITS      0x40 /* read and return current port bits */
+#define JIO_SETBITS       0x41 /* set bits marked by 1 in the argument */
+#define JIO_CLRBITS       0x42 /* clr bits marked by 1 in the argument */
+#define JIO_READDIR       0x43 /* read direction, 0=input 1=output */
+#define JIO_SETINPUT      0x44 /* set direction, 0=unchanged 1=input
+                                  returns current dir */
+#define JIO_SETOUTPUT     0x45 /* set direction, 0=unchanged 1=output
+                                  returns current dir */
+
+/**** YumYum internal adresses ****/
+
+/* Juliette buffer addresses */
+
+#define BUFFER1_VIDEO   0x1100
+#define BUFFER2_VIDEO   0x2800
+#define ACDC_BUFF_VIDEO 0x0aaa
+#define BUFFER1         0x1700
+#define BUFFER2         0x2b01
+#define ACDC_BUFFER     0x1200
+#define BUFFER1_SS1M    0x1100
+#define BUFFER2_SS1M    0x2800
+#define ACDC_BUFF_SS1M  0x0900
+
+/* Juliette parameter memory addresses */
+
+#define PA_BUFFER_CNT     0x3f09 /* CCD/VIDEO */
+#define PA_CCD_BUFFER     0x3f10 /* CCD       */
+#define PA_VIDEO_BUFFER   0x3f10 /*     VIDEO */
+#define PA_DCT_BUFFER     0x3f11 /* CCD/VIDEO */
+#define PA_TEMP           0x3f12 /* CCD/VIDEO */
+#define PA_VIDEOLINE_RD   0x3f13 /*     VIDEO */
+#define PA_VIDEOLINE_WR   0x3f14 /*     VIDEO */
+#define PA_VI_HDELAY0     0x3f15 /*     VIDEO */
+#define PA_VI_VDELAY0     0x3f16 /*     VIDEO */
+#define PA_VI_HDELAY1     0x3f17 /*     VIDEO */
+#define PA_VI_VDELAY1     0x3f18 /*     VIDEO */
+#define PA_VI_HDELAY2     0x3f19 /*     VIDEO */
+#define PA_VI_VDELAY2     0x3f1a /*     VIDEO */
+#define PA_VI_HDELAY3     0x3f1b /*     VIDEO */
+#define PA_VI_VDELAY3     0x3f1c /*     VIDEO */
+#define PA_VI_CTRL        0x3f20 /*     VIDEO */
+#define PA_JPEG_CTRL      0x3f22 /* CCD/VIDEO */
+#define PA_BUFFER_SIZE    0x3f24 /* CCD/VIDEO */
+#define PA_PAL_NTSC       0x3f25 /*     VIDEO */
+#define PA_MACROBLOCKS    0x3f26 /* CCD/VIDEO */
+#define PA_COLOR          0x3f27 /*     VIDEO */
+#define PA_MEMCH1CNT2     0x3f28 /* CCD/VIDEO */
+#define PA_MEMCH1CNT3     0x3f29 /*     VIDEO */
+#define PA_MEMCH1STR2     0x3f2a /* CCD/VIDEO */
+#define PA_MEMCH1STR3     0x3f2b /*     VIDEO */
+#define PA_BUFFERS        0x3f2c /* CCD/VIDEO */
+#define PA_PROGRAM        0x3f2d /* CCD/VIDEO */
+#define PA_ROTATION       0x3f2e /* CCD       */
+#define PA_PC             0x3f30 /* CCD/VIDEO */
+#define PA_PC2            0x3f31 /*     VIDEO */
+#define PA_ODD_LINE       0x3f32 /*     VIDEO */
+#define PA_EXP_DELAY      0x3f34 /* CCD       */
+#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */
+#define PA_DRAM_PTR1_L    0x3f36 /* CCD/VIDEO */
+#define PA_CLPOB_CNT      0x3f37 /* CCD       */
+#define PA_DRAM_PTR1_H    0x3f38 /* CCD/VIDEO */
+#define PA_DRAM_PTR2_L    0x3f3a /*     VIDEO */
+#define PA_DRAM_PTR2_H    0x3f3c /*     VIDEO */
+#define PA_CCD_LINE_CNT   0x3f3f /* CCD       */
+#define PA_VIDEO_LINE_CNT 0x3f3f /*     VIDEO */
+#define PA_TEXT           0x3f41 /* CCD/VIDEO */
+#define PA_CAMERA_CHANGED 0x3f42 /*     VIDEO */
+#define PA_TEXTALIGNMENT  0x3f43 /*     VIDEO */
+#define PA_DISABLED       0x3f44 /*     VIDEO */
+#define PA_MACROBLOCKTEXT 0x3f45 /*     VIDEO */
+#define PA_VGA            0x3f46 /*     VIDEO */
+#define PA_ZERO           0x3ffe /*     VIDEO */
+#define PA_NULL           0x3fff /* CCD/VIDEO */
+
+typedef enum {
+        jpeg  = 0,
+        dummy = 1
+} request_type;
+
+typedef enum {
+        hugesize  = 0,
+        fullsize  = 1,
+        halfsize  = 2,
+        fieldsize = 3
+} size_type;
+
+typedef enum {
+        min       = 0,
+        low       = 1,
+        medium    = 2,
+        high      = 3,
+        very_high = 4,
+        very_low  = 5,
+        q1        = 6,
+        q2        = 7,
+        q3        = 8,
+        q4        = 9,
+        q5        = 10,
+        q6        = 11
+} compr_type;
+
+typedef enum {
+        deg_0   = 0,
+        deg_180 = 1,
+        deg_90  = 2,
+        deg_270 = 3
+} rotation_type;
+
+typedef enum {
+        auto_white    = 0,
+        hold          = 1,
+        fixed_outdoor = 2,
+        fixed_indoor  = 3,
+        fixed_fluor   = 4
+} white_balance_type;
+
+typedef enum {
+        auto_exp  = 0,
+        fixed_exp = 1
+} exposure_type;
+
+typedef enum {
+        no_window = 0,
+        center    = 1,
+        top       = 2,
+        lower     = 3,
+        left      = 4,
+        right     = 5,
+        spot      = 6,
+        cw        = 7
+} exp_window_type;
+
+typedef enum {
+        h_24 = 0,
+        h_12 = 1,
+        h_24P = 2
+} hour_type;
+
+typedef enum {
+        standard = 0,
+        YYYY_MM_DD = 1,
+        Www_Mmm_DD_YYYY = 2,
+        Www_DD_MM_YYYY = 3
+} date_type;
+
+typedef enum {
+        left_align = 0,
+        center_align = 1,
+        right_align = 2
+} alignment_type;
+
+typedef enum {
+        off = 0,
+        on  = 1,
+        no  = 0,
+        yes = 1
+} enable_type;
+
+typedef enum {
+         disabled = 0,
+         enabled  = 1,
+         extended = 2
+} comment_type;
+
+typedef enum {
+        pal  = 0,
+        ntsc = 1
+} video_type;
+
+typedef enum {
+        pal_bghi_ntsc_m              = 0,
+        ntsc_4_43_50hz_pal_4_43_60hz = 1,
+        pal_n_ntsc_4_43_60hz         = 2,
+        ntsc_n_pal_m                 = 3,
+        secam_pal_4_43_60hz          = 4
+} modulation_type;
+
+typedef enum {
+        cam0 = 0,
+        cam1 = 1,
+        cam2 = 2,
+        cam3 = 3,
+        quad = 32
+} camera_type;
+
+typedef enum {
+        video_driver = 0,
+        ccd_driver   = 1
+} driver_type;
+
+struct jul_param {
+        request_type req_type;
+        size_type size;
+        compr_type compression;
+        rotation_type rotation;
+        int color_level;
+        int brightness;
+        white_balance_type white_balance;
+        exposure_type exposure;
+        exp_window_type auto_exp_window;
+        hour_type time_format;
+        date_type date_format;
+        alignment_type text_alignment;
+        enable_type text;
+        enable_type clock;
+        enable_type date;
+        enable_type fps;
+        enable_type vga;
+        enable_type comment;
+};
+
+struct video_param {
+        enable_type disabled;
+        modulation_type modulation;
+        video_type video;
+        enable_type signal;
+        enable_type vcr;
+        int xoffset;
+        int yoffset;
+};
+
+/* The juliette_request structure is used during the JULSTARTDMA asynchronous
+ * picture-taking ioctl call as an argument to specify a buffer which will get
+ * the final picture.
+ */
+
+struct juliette_request {
+        char *buf;              /* Pointer to the buffer to hold picture data */
+        unsigned int buflen;    /* Length of the above buffer */
+        unsigned int size;      /* Resulting length, 0 if the picture is not ready */
+};
+
+#endif
diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h
new file mode 100644
index 000000000000..d29df5644d3e
--- /dev/null
+++ b/include/asm-cris/arch-v32/memmap.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_INTMEM_START (0x38000000)
+#define MEM_INTMEM_SIZE (0x00020000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h
new file mode 100644
index 000000000000..6bcdc3fdf7dc
--- /dev/null
+++ b/include/asm-cris/arch-v32/mmu.h
@@ -0,0 +1,111 @@
+#ifndef _ASM_CRIS_ARCH_MMU_H
+#define _ASM_CRIS_ARCH_MMU_H
+
+/* MMU context type. */
+typedef struct
+{
+  unsigned int page_id;
+} mm_context_t;
+
+/* Kernel memory segments. */
+#define KSEG_F 0xf0000000UL
+#define KSEG_E 0xe0000000UL
+#define KSEG_D 0xd0000000UL
+#define KSEG_C 0xc0000000UL
+#define KSEG_B 0xb0000000UL
+#define KSEG_A 0xa0000000UL
+#define KSEG_9 0x90000000UL
+#define KSEG_8 0x80000000UL
+#define KSEG_7 0x70000000UL
+#define KSEG_6 0x60000000UL
+#define KSEG_5 0x50000000UL
+#define KSEG_4 0x40000000UL
+#define KSEG_3 0x30000000UL
+#define KSEG_2 0x20000000UL
+#define KSEG_1 0x10000000UL
+#define KSEG_0 0x00000000UL
+
+/*
+ * CRISv32 PTE bits:
+ *
+ *  Bit:  31-13  12-5     4        3       2        1        0
+ *       +-----+------+--------+-------+--------+-------+---------+
+ *       | pfn | zero | global | valid | kernel | write | execute |
+ *       +-----+------+--------+-------+--------+-------+---------+
+ */
+
+/*
+ * Defines for accessing the bits. Also define some synonyms for use with
+ * the software-based defined bits below.
+ */
+#define _PAGE_EXECUTE       (1 << 0)    /* Execution bit. */
+#define _PAGE_WE            (1 << 1)    /* Write bit. */
+#define _PAGE_SILENT_WRITE  (1 << 1)    /* Same as above. */
+#define _PAGE_KERNEL        (1 << 2)    /* Kernel mode page. */
+#define _PAGE_VALID         (1 << 3)    /* Page is valid. */
+#define _PAGE_SILENT_READ   (1 << 3)    /* Same as above. */
+#define _PAGE_GLOBAL        (1 << 4)    /* Global page. */
+
+/*
+ * The hardware doesn't care about these bits, but the kernel uses them in
+ * software.
+ */
+#define _PAGE_PRESENT   (1 << 5)   /* Page is present in memory. */
+#define _PAGE_FILE      (1 << 6)   /* 1=pagecache, 0=swap (when !present) */
+#define _PAGE_ACCESSED  (1 << 6)   /* Simulated in software using valid bit. */
+#define _PAGE_MODIFIED  (1 << 7)   /* Simulated in software using we bit. */
+#define _PAGE_READ      (1 << 8)   /* Read enabled. */
+#define _PAGE_WRITE     (1 << 9)   /* Write enabled. */
+
+/* Define some higher level generic page attributes. */
+#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_TABLE     (_PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
+
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
+                                 _PAGE_ACCESSED)
+#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
+                                  _PAGE_ACCESSED | _PAGE_EXECUTE)
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | __READABLE)
+#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
+
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | __READABLE)
+#define PAGE_COPY_EXEC  __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
+#define PAGE_KERNEL     __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
+                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
+                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
+                                       _PAGE_PRESENT | __READABLE)
+
+#define _KERNPG_TABLE   (_PAGE_TABLE | _PAGE_KERNEL)
+
+/* CRISv32 can do page protection for execute.
+ * Write permissions imply read permissions.
+ * Note that the numbers are in Execute-Write-Read order!
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY_EXEC
+#define __P101  PAGE_READONLY_EXEC
+#define __P110  PAGE_COPY_EXEC
+#define __P111  PAGE_COPY_EXEC
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY_EXEC
+#define __S101  PAGE_READONLY_EXEC
+#define __S110  PAGE_SHARED_EXEC
+#define __S111  PAGE_SHARED_EXEC
+
+#define PTE_FILE_MAX_BITS       25
+
+#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h
new file mode 100644
index 000000000000..597419b033f9
--- /dev/null
+++ b/include/asm-cris/arch-v32/offset.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_OFFSETS_H__
+#define __ASM_OFFSETS_H__
+/*
+ * DO NOT MODIFY.
+ *
+ * This file was generated by arch/cris/Makefile
+ *
+ */
+
+#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
+#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
+#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
+#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
+#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
+#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
+#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
+#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
+#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
+#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
+#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
+
+#define TI_task 0 /* offsetof(struct thread_info, task) */
+#define TI_flags 8 /* offsetof(struct thread_info, flags) */
+#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
+
+#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
+#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
+#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
+
+#define TASK_pid 149 /* offsetof(struct task_struct, pid) */
+
+#define LCLONE_VM 256 /* CLONE_VM */
+#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
+
+#endif
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h
new file mode 100644
index 000000000000..77827bc17cca
--- /dev/null
+++ b/include/asm-cris/arch-v32/page.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_CRIS_ARCH_PAGE_H
+#define _ASM_CRIS_ARCH_PAGE_H
+
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+
+#define PAGE_OFFSET KSEG_C      /* kseg_c is mapped to physical ram. */
+
+/*
+ * Macros to convert between physical and virtual addresses. By stripiing a
+ * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
+ * DRAM really resides. DRAM is virtually at 0xc.
+ */
+#ifndef CONFIG_ETRAXFS_SIM
+#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
+#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
+#else
+#define __pa(x) ((unsigned long)(x) & 0x3fffffff)
+#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000))
+#endif
+
+#define VM_STACK_DEFAULT_FLAGS  (VM_READ | VM_WRITE | \
+                                 VM_MAYREAD | VM_MAYWRITE)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h
new file mode 100644
index 000000000000..08cb7ff7e4e7
--- /dev/null
+++ b/include/asm-cris/arch-v32/pgtable.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_ARCH_PGTABLE_H
+#define _ASM_CRIS_ARCH_PGTABLE_H
+
+/* Define the kernels virtual memory area. */
+#define VMALLOC_START           KSEG_D
+#define VMALLOC_END             KSEG_E
+#define VMALLOC_VMADDR(x)       ((unsigned long)(x))
+
+#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h
new file mode 100644
index 000000000000..a66dc9970919
--- /dev/null
+++ b/include/asm-cris/arch-v32/pinmux.h
@@ -0,0 +1,39 @@
+#ifndef _ASM_CRIS_ARCH_PINMUX_H
+#define _ASM_CRIS_ARCH_PINMUX_H
+
+#define PORT_B 0
+#define PORT_C 1
+#define PORT_D 2
+#define PORT_E 3
+
+enum pin_mode
+{
+  pinmux_none = 0,
+  pinmux_fixed,
+  pinmux_gpio,
+  pinmux_iop
+};
+
+enum fixed_function
+{
+  pinmux_ser1,
+  pinmux_ser2,
+  pinmux_ser3,
+  pinmux_sser0,
+  pinmux_sser1,
+  pinmux_ata0,
+  pinmux_ata1,
+  pinmux_ata2,
+  pinmux_ata3,
+  pinmux_ata,
+  pinmux_eth1,
+  pinmux_timer
+};
+
+int crisv32_pinmux_init(void);
+int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
+int crisv32_pinmux_alloc_fixed(enum fixed_function function);
+int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
+void crisv32_pinmux_dump(void);
+
+#endif
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h
new file mode 100644
index 000000000000..8c939bf27987
--- /dev/null
+++ b/include/asm-cris/arch-v32/processor.h
@@ -0,0 +1,60 @@
+#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
+#define _ASM_CRIS_ARCH_PROCESSOR_H
+
+#include <linux/config.h>
+
+/* Return current instruction pointer. */
+#define current_text_addr() \
+        ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
+
+/*
+ * Since CRIS doesn't do hardware task-switching this hasn't really anything to
+ * do with the proccessor itself, it's just here for legacy reasons. This is
+ * used when task-switching using _resume defined in entry.S. The offsets here
+ * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
+ * changed as well.
+ */
+struct thread_struct {
+        unsigned long ksp;      /* Kernel stack pointer. */
+        unsigned long usp;      /* User stack pointer. */
+        unsigned long ccs;      /* Saved flags register. */
+};
+
+/*
+ * User-space process size. This is hardcoded into a few places, so don't
+ * changed it unless everything's clear!
+ */
+#ifndef CONFIG_ETRAXFS_SIM
+#define TASK_SIZE       (0xB0000000UL)
+#else
+#define TASK_SIZE       (0xA0000000UL)
+#endif
+
+/* CCS I=1, enable interrupts. */
+#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) }
+
+#define KSTK_EIP(tsk)           \
+({                              \
+        unsigned long eip = 0;  \
+        unsigned long regs = (unsigned long)user_regs(tsk); \
+        if (regs > PAGE_SIZE && virt_addr_valid(regs))      \
+                eip = ((struct pt_regs *)regs)->erp;        \
+        eip; \
+})
+
+/*
+ * Give the thread a program location, set user-mode and switch user
+ * stackpointer.
+ */
+#define start_thread(regs, ip, usp) \
+do { \
+        set_fs(USER_DS); \
+        regs->erp = ip; \
+        regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
+        wrusp(usp); \
+} while(0)
+
+/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
+#define arch_fixup(regs) {};
+
+#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h
new file mode 100644
index 000000000000..516cc7062d94
--- /dev/null
+++ b/include/asm-cris/arch-v32/ptrace.h
@@ -0,0 +1,114 @@
+#ifndef _CRIS_ARCH_PTRACE_H
+#define _CRIS_ARCH_PTRACE_H
+
+/* Register numbers in the ptrace system call interface */
+
+#define PT_ORIG_R10  0
+#define PT_R0        1
+#define PT_R1        2
+#define PT_R2        3
+#define PT_R3        4
+#define PT_R4        5
+#define PT_R5        6
+#define PT_R6        7
+#define PT_R7        8
+#define PT_R8        9
+#define PT_R9        10
+#define PT_R10       11
+#define PT_R11       12
+#define PT_R12       13
+#define PT_R13       14
+#define PT_ACR       15
+#define PT_SRS       16
+#define PT_MOF       17
+#define PT_SPC       18
+#define PT_CCS       19
+#define PT_SRP       20
+#define PT_ERP       21    /* This is actually the debugged process' PC */
+#define PT_EXS       22
+#define PT_EDA       23
+#define PT_USP       24    /* special case - USP is not in the pt_regs */
+#define PT_PPC       25    /* special case - pseudo PC */
+#define PT_BP        26    /* Base number for BP registers. */
+#define PT_BP_CTRL   26    /* BP control register. */
+#define PT_MAX       40
+
+/* Condition code bit numbers. */
+#define C_CCS_BITNR 0
+#define V_CCS_BITNR 1
+#define Z_CCS_BITNR 2
+#define N_CCS_BITNR 3
+#define X_CCS_BITNR 4
+#define I_CCS_BITNR 5
+#define U_CCS_BITNR 6
+#define P_CCS_BITNR 7
+#define R_CCS_BITNR 8
+#define S_CCS_BITNR 9
+#define M_CCS_BITNR 30
+#define Q_CCS_BITNR 31
+#define CCS_SHIFT   10 /* Shift count for each level in CCS */
+
+/* pt_regs not only specifices the format in the user-struct during
+ * ptrace but is also the frame format used in the kernel prologue/epilogues
+ * themselves
+ */
+
+struct pt_regs {
+        unsigned long orig_r10;
+        /* pushed by movem r13, [sp] in SAVE_ALL. */
+        unsigned long r0;
+        unsigned long r1;
+        unsigned long r2;
+        unsigned long r3;
+        unsigned long r4;
+        unsigned long r5;
+        unsigned long r6;
+        unsigned long r7;
+        unsigned long r8;
+        unsigned long r9;
+        unsigned long r10;
+        unsigned long r11;
+        unsigned long r12;
+        unsigned long r13;
+        unsigned long acr;
+        unsigned long srs;
+        unsigned long mof;
+        unsigned long spc;
+        unsigned long ccs;
+        unsigned long srp;
+        unsigned long erp; /* This is actually the debugged process' PC */
+        /* For debugging purposes; saved only when needed. */
+        unsigned long exs;
+        unsigned long eda;
+};
+
+/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
+ * when doing a context-switch. it is used (apart from in resume) when a new
+ * thread is made and we need to make _resume (which is starting it for the
+ * first time) realise what is going on.
+ *
+ * Actually, the use is very close to the thread struct (TSS) in that both the
+ * switch_stack and the TSS are used to keep thread stuff when switching in
+ * _resume.
+ */
+
+struct switch_stack {
+        unsigned long r0;
+        unsigned long r1;
+        unsigned long r2;
+        unsigned long r3;
+        unsigned long r4;
+        unsigned long r5;
+        unsigned long r6;
+        unsigned long r7;
+        unsigned long r8;
+        unsigned long r9;
+        unsigned long return_ip; /* ip that _resume will return to */
+};
+
+#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
+#define instruction_pointer(regs) ((regs)->erp)
+extern void show_regs(struct pt_regs *);
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h
new file mode 100644
index 000000000000..52df72a62232
--- /dev/null
+++ b/include/asm-cris/arch-v32/spinlock.h
@@ -0,0 +1,163 @@
+#ifndef __ASM_ARCH_SPINLOCK_H
+#define __ASM_ARCH_SPINLOCK_H
+
+#include <asm/system.h>
+
+#define RW_LOCK_BIAS 0x01000000
+#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
+#define spin_lock_init(x)       do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
+
+#define spin_is_locked(x)       (*(volatile signed char *)(&(x)->lock) <= 0)
+#define spin_unlock_wait(x)     do { barrier(); } while(spin_is_locked(x))
+
+extern void cris_spin_unlock(void *l, int val);
+extern void cris_spin_lock(void *l);
+extern int cris_spin_trylock(void* l);
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+        __asm__ volatile ("move.d %1,%0" \
+                          : "=m" (lock->lock) \
+                          : "r" (1) \
+                          : "memory");
+}
+
+static inline int _raw_spin_trylock(spinlock_t *lock)
+{
+        return cris_spin_trylock((void*)&lock->lock);
+}
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+        cris_spin_lock((void*)&lock->lock);
+}
+
+static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
+{
+  _raw_spin_lock(lock);
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+typedef struct {
+        spinlock_t lock;
+        volatile int counter;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 }
+
+#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0)
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define read_can_lock(x) ((int)(x)->counter >= 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define write_can_lock(x) ((x)->counter == 0)
+
+#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
+
+/* read_lock, read_unlock are pretty straightforward.  Of course it somehow
+ * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
+
+static  __inline__ void _raw_read_lock(rwlock_t *rw)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        _raw_spin_lock(&rw->lock);
+
+        rw->counter++;
+
+        _raw_spin_unlock(&rw->lock);
+        local_irq_restore(flags);
+}
+
+static  __inline__ void _raw_read_unlock(rwlock_t *rw)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        _raw_spin_lock(&rw->lock);
+
+        rw->counter--;
+
+        _raw_spin_unlock(&rw->lock);
+        local_irq_restore(flags);
+}
+
+/* write_lock is less trivial.  We optimistically grab the lock and check
+ * if we surprised any readers.  If so we release the lock and wait till
+ * they're all gone before trying again
+ *
+ * Also note that we don't use the _irqsave / _irqrestore suffixes here.
+ * If we're called with interrupts enabled and we've got readers (or other
+ * writers) in interrupt handlers someone fucked up and we'd dead-lock
+ * sooner or later anyway.   prumpf */
+
+static  __inline__ void _raw_write_lock(rwlock_t *rw)
+{
+retry:
+        _raw_spin_lock(&rw->lock);
+
+        if(rw->counter != 0) {
+                /* this basically never happens */
+                _raw_spin_unlock(&rw->lock);
+
+                while(rw->counter != 0);
+
+                goto retry;
+        }
+
+        /* got it.  now leave without unlocking */
+        rw->counter = -1; /* remember we are locked */
+}
+
+/* write_unlock is absolutely trivial - we don't have to wait for anything */
+
+static  __inline__ void _raw_write_unlock(rwlock_t *rw)
+{
+        rw->counter = 0;
+        _raw_spin_unlock(&rw->lock);
+}
+
+static  __inline__ int _raw_write_trylock(rwlock_t *rw)
+{
+        _raw_spin_lock(&rw->lock);
+        if (rw->counter != 0) {
+                /* this basically never happens */
+                _raw_spin_unlock(&rw->lock);
+
+                return 0;
+        }
+
+        /* got it.  now leave without unlocking */
+        rw->counter = -1; /* remember we are locked */
+        return 1;
+}
+
+static __inline__ int is_read_locked(rwlock_t *rw)
+{
+        return rw->counter > 0;
+}
+
+static __inline__ int is_write_locked(rwlock_t *rw)
+{
+        return rw->counter < 0;
+}
+
+#endif /* __ASM_ARCH_SPINLOCK_H */
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h
new file mode 100644
index 000000000000..b9afbb95e0bb
--- /dev/null
+++ b/include/asm-cris/arch-v32/system.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_CRIS_ARCH_SYSTEM_H
+#define _ASM_CRIS_ARCH_SYSTEM_H
+
+#include <linux/config.h>
+
+/* Read the CPU version register. */
+extern inline unsigned long rdvr(void)
+{
+        unsigned char vr;
+
+        __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
+        return vr;
+}
+
+#define cris_machine_name "crisv32"
+
+/* Read the user-mode stack pointer. */
+extern inline unsigned long rdusp(void)
+{
+        unsigned long usp;
+
+        __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
+        return usp;
+}
+
+/* Read the current stack pointer. */
+extern inline unsigned long rdsp(void)
+{
+        unsigned long sp;
+
+        __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
+        return sp;
+}
+
+/* Write the user-mode stack pointer. */
+#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
+
+#define nop() __asm__ __volatile__ ("nop");
+
+#define xchg(ptr,x) \
+        ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr))))
+
+#define tas(ptr) (xchg((ptr),1))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/* Used for interrupt control. */
+#define local_save_flags(x) \
+        __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory");
+
+#define local_irq_restore(x) \
+        __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory");
+
+#define local_irq_disable()  __asm__ __volatile__ ("di" : : : "memory");
+#define local_irq_enable()   __asm__ __volatile__ ("ei" : : : "memory");
+
+#define irqs_disabled()         \
+({                              \
+        unsigned long flags;    \
+                                \
+        local_save_flags(flags);\
+        !(flags & (1 << I_CCS_BITNR));  \
+})
+
+/* Used for spinlocks, etc. */
+#define local_irq_save(x) \
+        __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
+
+#ifdef CONFIG_SMP
+typedef struct {
+        volatile unsigned int lock __attribute__ ((aligned(4)));
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} spinlock_t;
+#endif
+
+#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h
new file mode 100644
index 000000000000..a7a182307da0
--- /dev/null
+++ b/include/asm-cris/arch-v32/thread_info.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
+#define _ASM_CRIS_ARCH_THREAD_INFO_H
+
+/* Return a thread_info struct. */
+extern inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+
+        __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
+        return ti;
+}
+
+#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h
new file mode 100644
index 000000000000..4d0fd23b21e9
--- /dev/null
+++ b/include/asm-cris/arch-v32/timex.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_CRIS_ARCH_TIMEX_H
+#define _ASM_CRIS_ARCH_TIMEX_H
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/timer_defs.h>
+
+/*
+ * The clock runs at 100MHz, we divide it by 1000000. If you change anything
+ * here you must check time.c as well.
+ */
+
+#define CLOCK_TICK_RATE 100000000       /* Underlying frequency of the HZ timer */
+
+/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
+#define TIMER0_FREQ (CLOCK_TICK_RATE)
+#define TIMER0_DIV (TIMER0_FREQ/(HZ))
+
+/* Convert the value in step of 10 ns to 1us without overflow: */
+#define GET_JIFFIES_USEC() \
+  ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 )
+
+extern unsigned long get_ns_in_jiffie(void);
+
+extern inline unsigned long get_us_in_jiffie_highres(void)
+{
+        return get_ns_in_jiffie() / 1000;
+}
+
+#endif
+
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h
new file mode 100644
index 000000000000..4effb1253660
--- /dev/null
+++ b/include/asm-cris/arch-v32/tlb.h
@@ -0,0 +1,14 @@
+#ifndef _CRIS_ARCH_TLB_H
+#define _CRIS_ARCH_TLB_H
+
+/*
+ * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
+ * to store the "process" it belongs to (=> fast mm context switch). The
+ * last page_id is never used so we can make TLB entries that never matches.
+ */
+#define NUM_TLB_ENTRIES 64
+#define NUM_PAGEID 256
+#define INVALID_PAGEID 255
+#define NO_CONTEXT -1
+
+#endif /* _CRIS_ARCH_TLB_H */
diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h
new file mode 100644
index 000000000000..055a0bdbe835
--- /dev/null
+++ b/include/asm-cris/arch-v32/uaccess.h
@@ -0,0 +1,748 @@
+/*
+ * Authors:    Hans-Peter Nilsson (hp@axis.com)
+ *
+ */
+#ifndef _CRIS_ARCH_UACCESS_H
+#define _CRIS_ARCH_UACCESS_H
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ *
+ * Note that PC at a fault is the address *at* the faulting
+ * instruction for CRISv32.
+ */
+#define __put_user_asm(x, addr, err, op)                        \
+        __asm__ __volatile__(                                   \
+                "2:     "op" %1,[%2]\n"                         \
+                "4:\n"                                          \
+                "       .section .fixup,\"ax\"\n"               \
+                "3:     move.d %3,%0\n"                         \
+                "       jump 4b\n"                              \
+                "       nop\n"                                  \
+                "       .previous\n"                            \
+                "       .section __ex_table,\"a\"\n"            \
+                "       .dword 2b,3b\n"                         \
+                "       .previous\n"                            \
+                : "=r" (err)                                    \
+                : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
+
+#define __put_user_asm_64(x, addr, err) do {                    \
+        int dummy_for_put_user_asm_64_;                         \
+        __asm__ __volatile__(                                   \
+                "2:     move.d %M2,[%1+]\n"                     \
+                "4:     move.d %H2,[%1]\n"                      \
+                "5:\n"                                          \
+                "       .section .fixup,\"ax\"\n"               \
+                "3:     move.d %4,%0\n"                         \
+                "       jump 5b\n"                              \
+                "       .previous\n"                            \
+                "       .section __ex_table,\"a\"\n"            \
+                "       .dword 2b,3b\n"                         \
+                "       .dword 4b,3b\n"                         \
+                "       .previous\n"                            \
+                : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \
+                : "r" (x), "1" (addr), "g" (-EFAULT),           \
+                  "0" (err));                                   \
+        } while (0)
+
+/* See comment before __put_user_asm.  */
+
+#define __get_user_asm(x, addr, err, op)                \
+        __asm__ __volatile__(                           \
+                "2:     "op" [%2],%1\n"                 \
+                "4:\n"                                  \
+                "       .section .fixup,\"ax\"\n"       \
+                "3:     move.d %3,%0\n"                 \
+                "       jump 4b\n"                      \
+                "       moveq 0,%1\n"                   \
+                "       .previous\n"                    \
+                "       .section __ex_table,\"a\"\n"    \
+                "       .dword 2b,3b\n"                 \
+                "       .previous\n"                    \
+                : "=r" (err), "=r" (x)                  \
+                : "r" (addr), "g" (-EFAULT), "0" (err))
+
+#define __get_user_asm_64(x, addr, err) do {            \
+        int dummy_for_get_user_asm_64_;                 \
+        __asm__ __volatile__(                           \
+                "2:     move.d [%2+],%M1\n"             \
+                "4:     move.d [%2],%H1\n"              \
+                "5:\n"                                  \
+                "       .section .fixup,\"ax\"\n"       \
+                "3:     move.d %4,%0\n"                 \
+                "       jump 5b\n"                      \
+                "       moveq 0,%1\n"                   \
+                "       .previous\n"                    \
+                "       .section __ex_table,\"a\"\n"    \
+                "       .dword 2b,3b\n"                 \
+                "       .dword 4b,3b\n"                 \
+                "       .previous\n"                    \
+                : "=r" (err), "=r" (x),                 \
+                  "=b" (dummy_for_get_user_asm_64_)     \
+                : "2" (addr), "g" (-EFAULT), "0" (err));\
+        } while (0)
+
+/*
+ * Copy a null terminated string from userspace.
+ *
+ * Must return:
+ * -EFAULT              for an exception
+ * count                if we hit the buffer limit
+ * bytes copied         if we hit a null byte
+ * (without the null byte)
+ */
+extern inline long
+__do_strncpy_from_user(char *dst, const char *src, long count)
+{
+        long res;
+
+        if (count == 0)
+                return 0;
+
+        /*
+         * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
+         *  So do we.
+         *
+         *  This code is deduced from:
+         *
+         *      char tmp2;
+         *      long tmp1, tmp3;
+         *      tmp1 = count;
+         *      while ((*dst++ = (tmp2 = *src++)) != 0
+         *             && --tmp1)
+         *        ;
+         *
+         *      res = count - tmp1;
+         *
+         *  with tweaks.
+         */
+
+        __asm__ __volatile__ (
+                "       move.d %3,%0\n"
+                "5:     move.b [%2+],$acr\n"
+                "1:     beq 2f\n"
+                "       move.b $acr,[%1+]\n"
+
+                "       subq 1,%0\n"
+                "2:     bne 1b\n"
+                "       move.b [%2+],$acr\n"
+
+                "       sub.d %3,%0\n"
+                "       neg.d %0,%0\n"
+                "3:\n"
+                "       .section .fixup,\"ax\"\n"
+                "4:     move.d %7,%0\n"
+                "       jump 3b\n"
+                "       nop\n"
+
+                /* The address for a fault at the first move is trivial.
+                   The address for a fault at the second move is that of
+                   the preceding branch insn, since the move insn is in
+                   its delay-slot.  That address is also a branch
+                   target.  Just so you don't get confused...  */
+                "       .previous\n"
+                "       .section __ex_table,\"a\"\n"
+                "       .dword 5b,4b\n"
+                "       .dword 2b,4b\n"
+                "       .previous"
+                : "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
+                : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
+                : "acr");
+
+        return res;
+}
+
+/* A few copy asms to build up the more complex ones from.
+
+   Note again, a post-increment is performed regardless of whether a bus
+   fault occurred in that instruction, and PC for a faulted insn is the
+   address for the insn, or for the preceding branch when in a delay-slot.  */
+
+#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm__ __volatile__ (                          \
+                        COPY                            \
+                "1:\n"                                  \
+                "       .section .fixup,\"ax\"\n"       \
+                        FIXUP                           \
+                "       .previous\n"                    \
+                "       .section __ex_table,\"a\"\n"    \
+                        TENTRY                          \
+                "       .previous\n"                    \
+                : "=b" (to), "=b" (from), "=r" (ret)    \
+                : "0" (to), "1" (from), "2" (ret)       \
+                : "acr", "memory")
+
+#define __asm_copy_from_user_1(to, from, ret) \
+        __asm_copy_user_cont(to, from, ret,     \
+                "2:     move.b [%1+],$acr\n"    \
+                "       move.b $acr,[%0+]\n",   \
+                "3:     addq 1,%2\n"            \
+                "       jump 1b\n"              \
+                "       clear.b [%0+]\n",       \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_user_cont(to, from, ret,             \
+                        COPY                            \
+                "2:     move.w [%1+],$acr\n"            \
+                "       move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "3:     addq 2,%2\n"                    \
+                "       jump 1b\n"                      \
+                "       clear.w [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_from_user_2(to, from, ret) \
+        __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_3(to, from, ret)           \
+        __asm_copy_from_user_2x_cont(to, from, ret,     \
+                "4:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "5:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_user_cont(to, from, ret,             \
+                        COPY                            \
+                "2:     move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "3:     addq 4,%2\n"                    \
+                "       jump 1b\n"                      \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_from_user_4(to, from, ret) \
+        __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_5(to, from, ret) \
+        __asm_copy_from_user_4x_cont(to, from, ret,     \
+                "4:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "5:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_4x_cont(to, from, ret,     \
+                        COPY                            \
+                "4:     move.w [%1+],$acr\n"            \
+                "       move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "5:     addq 2,%2\n"                    \
+                "       clear.w [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_from_user_6(to, from, ret) \
+        __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_7(to, from, ret) \
+        __asm_copy_from_user_6x_cont(to, from, ret,     \
+                "6:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "7:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_4x_cont(to, from, ret,     \
+                        COPY                            \
+                "4:     move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "5:     addq 4,%2\n"                    \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_from_user_8(to, from, ret) \
+        __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_9(to, from, ret) \
+        __asm_copy_from_user_8x_cont(to, from, ret,     \
+                "6:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "7:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_8x_cont(to, from, ret,     \
+                        COPY                            \
+                "6:     move.w [%1+],$acr\n"            \
+                "       move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "7:     addq 2,%2\n"                    \
+                "       clear.w [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_from_user_10(to, from, ret) \
+        __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_11(to, from, ret)          \
+        __asm_copy_from_user_10x_cont(to, from, ret,    \
+                "8:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "9:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_8x_cont(to, from, ret,     \
+                        COPY                            \
+                "6:     move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "7:     addq 4,%2\n"                    \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_from_user_12(to, from, ret) \
+        __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_13(to, from, ret) \
+        __asm_copy_from_user_12x_cont(to, from, ret,    \
+                "8:     move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "9:     addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_12x_cont(to, from, ret,    \
+                        COPY                            \
+                "8:     move.w [%1+],$acr\n"            \
+                "       move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "9:     addq 2,%2\n"                    \
+                "       clear.w [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_from_user_14(to, from, ret) \
+        __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_15(to, from, ret) \
+        __asm_copy_from_user_14x_cont(to, from, ret,    \
+                "10:    move.b [%1+],$acr\n"            \
+                "       move.b $acr,[%0+]\n",           \
+                "11:    addq 1,%2\n"                    \
+                "       clear.b [%0+]\n",               \
+                "       .dword 10b,11b\n")
+
+#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_12x_cont(to, from, ret,    \
+                        COPY                            \
+                "8:     move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "9:     addq 4,%2\n"                    \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_from_user_16(to, from, ret) \
+        __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_16x_cont(to, from, ret,    \
+                        COPY                            \
+                "10:    move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "11:    addq 4,%2\n"                    \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 10b,11b\n")
+
+#define __asm_copy_from_user_20(to, from, ret) \
+        __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_from_user_20x_cont(to, from, ret,    \
+                        COPY                            \
+                "12:    move.d [%1+],$acr\n"            \
+                "       move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "13:    addq 4,%2\n"                    \
+                "       clear.d [%0+]\n",               \
+                        TENTRY                          \
+                "       .dword 12b,13b\n")
+
+#define __asm_copy_from_user_24(to, from, ret) \
+        __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
+
+/* And now, the to-user ones.  */
+
+#define __asm_copy_to_user_1(to, from, ret)     \
+        __asm_copy_user_cont(to, from, ret,     \
+                "       move.b [%1+],$acr\n"    \
+                "2:     move.b $acr,[%0+]\n",   \
+                "3:     jump 1b\n"              \
+                "       addq 1,%2\n",           \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_user_cont(to, from, ret,             \
+                        COPY                            \
+                "       move.w [%1+],$acr\n"            \
+                "2:     move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "3:     jump 1b\n"                      \
+                "       addq 2,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_to_user_2(to, from, ret) \
+        __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_3(to, from, ret) \
+        __asm_copy_to_user_2x_cont(to, from, ret,       \
+                "       move.b [%1+],$acr\n"            \
+                "4:     move.b $acr,[%0+]\n",           \
+                "5:     addq 1,%2\n",                   \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_user_cont(to, from, ret,             \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "2:     move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "3:     jump 1b\n"                      \
+                "       addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 2b,3b\n")
+
+#define __asm_copy_to_user_4(to, from, ret) \
+        __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_5(to, from, ret) \
+        __asm_copy_to_user_4x_cont(to, from, ret,       \
+                "       move.b [%1+],$acr\n"            \
+                "4:     move.b $acr,[%0+]\n",           \
+                "5:     addq 1,%2\n",                   \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_4x_cont(to, from, ret,       \
+                        COPY                            \
+                "       move.w [%1+],$acr\n"            \
+                "4:     move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "5:     addq 2,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_to_user_6(to, from, ret) \
+        __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_7(to, from, ret) \
+        __asm_copy_to_user_6x_cont(to, from, ret,       \
+                "       move.b [%1+],$acr\n"            \
+                "6:     move.b $acr,[%0+]\n",           \
+                "7:     addq 1,%2\n",                   \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_4x_cont(to, from, ret,       \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "4:     move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "5:     addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 4b,5b\n")
+
+#define __asm_copy_to_user_8(to, from, ret) \
+        __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_9(to, from, ret) \
+        __asm_copy_to_user_8x_cont(to, from, ret,       \
+                "       move.b [%1+],$acr\n"            \
+                "6:     move.b $acr,[%0+]\n",           \
+                "7:     addq 1,%2\n",                   \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_8x_cont(to, from, ret,       \
+                        COPY                            \
+                "       move.w [%1+],$acr\n"            \
+                "6:     move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "7:     addq 2,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_to_user_10(to, from, ret) \
+        __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_11(to, from, ret) \
+        __asm_copy_to_user_10x_cont(to, from, ret,      \
+                "       move.b [%1+],$acr\n"            \
+                "8:     move.b $acr,[%0+]\n",           \
+                "9:     addq 1,%2\n",                   \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_8x_cont(to, from, ret,       \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "6:     move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "7:     addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 6b,7b\n")
+
+#define __asm_copy_to_user_12(to, from, ret) \
+        __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_13(to, from, ret) \
+        __asm_copy_to_user_12x_cont(to, from, ret,      \
+                "       move.b [%1+],$acr\n"            \
+                "8:     move.b $acr,[%0+]\n",           \
+                "9:     addq 1,%2\n",                   \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_12x_cont(to, from, ret,      \
+                        COPY                            \
+                "       move.w [%1+],$acr\n"            \
+                "8:     move.w $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "9:     addq 2,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_to_user_14(to, from, ret)    \
+        __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_15(to, from, ret) \
+        __asm_copy_to_user_14x_cont(to, from, ret,      \
+                "       move.b [%1+],$acr\n"            \
+                "10:    move.b $acr,[%0+]\n",           \
+                "11:    addq 1,%2\n",                   \
+                "       .dword 10b,11b\n")
+
+#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_12x_cont(to, from, ret,      \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "8:     move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "9:     addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 8b,9b\n")
+
+#define __asm_copy_to_user_16(to, from, ret) \
+        __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_16x_cont(to, from, ret,      \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "10:    move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "11:    addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 10b,11b\n")
+
+#define __asm_copy_to_user_20(to, from, ret) \
+        __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+        __asm_copy_to_user_20x_cont(to, from, ret,      \
+                        COPY                            \
+                "       move.d [%1+],$acr\n"            \
+                "12:    move.d $acr,[%0+]\n",           \
+                        FIXUP                           \
+                "13:    addq 4,%2\n",                   \
+                        TENTRY                          \
+                "       .dword 12b,13b\n")
+
+#define __asm_copy_to_user_24(to, from, ret)    \
+        __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
+
+/* Define a few clearing asms with exception handlers.  */
+
+/* This frame-asm is like the __asm_copy_user_cont one, but has one less
+   input.  */
+
+#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm__ __volatile__ (                          \
+                        CLEAR                           \
+                "1:\n"                                  \
+                "       .section .fixup,\"ax\"\n"       \
+                        FIXUP                           \
+                "       .previous\n"                    \
+                "       .section __ex_table,\"a\"\n"    \
+                        TENTRY                          \
+                "       .previous"                      \
+                : "=b" (to), "=r" (ret)                 \
+                : "0" (to), "1" (ret)                   \
+                : "memory")
+
+#define __asm_clear_1(to, ret) \
+        __asm_clear(to, ret,                    \
+                "2:     clear.b [%0+]\n",       \
+                "3:     jump 1b\n"              \
+                "       addq 1,%1\n",           \
+                "       .dword 2b,3b\n")
+
+#define __asm_clear_2(to, ret) \
+        __asm_clear(to, ret,                    \
+                "2:     clear.w [%0+]\n",       \
+                "3:     jump 1b\n"              \
+                "       addq 2,%1\n",           \
+                "       .dword 2b,3b\n")
+
+#define __asm_clear_3(to, ret) \
+     __asm_clear(to, ret,                       \
+                 "2:    clear.w [%0+]\n"        \
+                 "3:    clear.b [%0+]\n",       \
+                 "4:    addq 2,%1\n"            \
+                 "5:    jump 1b\n"              \
+                 "      addq 1,%1\n",           \
+                 "      .dword 2b,4b\n"         \
+                 "      .dword 3b,5b\n")
+
+#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear(to, ret,                            \
+                        CLEAR                           \
+                "2:     clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "3:     jump 1b\n"                      \
+                "       addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 2b,3b\n")
+
+#define __asm_clear_4(to, ret) \
+        __asm_clear_4x_cont(to, ret, "", "", "")
+
+#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear_4x_cont(to, ret,                    \
+                        CLEAR                           \
+                "4:     clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "5:     addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 4b,5b\n")
+
+#define __asm_clear_8(to, ret) \
+        __asm_clear_8x_cont(to, ret, "", "", "")
+
+#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear_8x_cont(to, ret,                    \
+                        CLEAR                           \
+                "6:     clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "7:     addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 6b,7b\n")
+
+#define __asm_clear_12(to, ret) \
+        __asm_clear_12x_cont(to, ret, "", "", "")
+
+#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear_12x_cont(to, ret,                   \
+                        CLEAR                           \
+                "8:     clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "9:     addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 8b,9b\n")
+
+#define __asm_clear_16(to, ret) \
+        __asm_clear_16x_cont(to, ret, "", "", "")
+
+#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear_16x_cont(to, ret,                   \
+                        CLEAR                           \
+                "10:    clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "11:    addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 10b,11b\n")
+
+#define __asm_clear_20(to, ret) \
+        __asm_clear_20x_cont(to, ret, "", "", "")
+
+#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+        __asm_clear_20x_cont(to, ret,                   \
+                        CLEAR                           \
+                "12:    clear.d [%0+]\n",               \
+                        FIXUP                           \
+                "13:    addq 4,%1\n",                   \
+                        TENTRY                          \
+                "       .dword 12b,13b\n")
+
+#define __asm_clear_24(to, ret) \
+        __asm_clear_24x_cont(to, ret, "", "", "")
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return length of string in userspace including terminating 0
+ * or 0 for error.  Return a value greater than N if too long.
+ */
+
+extern inline long
+strnlen_user(const char *s, long n)
+{
+        long res, tmp1;
+
+        if (!access_ok(VERIFY_READ, s, 0))
+                return 0;
+
+        /*
+         * This code is deduced from:
+         *
+         *      tmp1 = n;
+         *      while (tmp1-- > 0 && *s++)
+         *        ;
+         *
+         *      res = n - tmp1;
+         *
+         *  (with tweaks).
+         */
+
+        __asm__ __volatile__ (
+                "       move.d %1,$acr\n"
+                "       cmpq 0,$acr\n"
+                "0:\n"
+                "       ble 1f\n"
+                "       subq 1,$acr\n"
+
+                "4:     test.b [%0+]\n"
+                "       bne 0b\n"
+                "       cmpq 0,$acr\n"
+                "1:\n"
+                "       move.d %1,%0\n"
+                "       sub.d $acr,%0\n"
+                "2:\n"
+                "       .section .fixup,\"ax\"\n"
+
+                "3:     jump 2b\n"
+                "       clear.d %0\n"
+
+                "       .previous\n"
+                "       .section __ex_table,\"a\"\n"
+                "       .dword 4b,3b\n"
+                "       .previous\n"
+                : "=r" (res), "=r" (tmp1)
+                : "0" (s), "1" (n)
+                : "acr");
+
+        return res;
+}
+
+#endif
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h
new file mode 100644
index 000000000000..5d369d4439d9
--- /dev/null
+++ b/include/asm-cris/arch-v32/unistd.h
@@ -0,0 +1,148 @@
+#ifndef _ASM_CRIS_ARCH_UNISTD_H_
+#define _ASM_CRIS_ARCH_UNISTD_H_
+
+/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
+/*
+ * Don't remove the .ifnc tests; they are an insurance against
+ * any hard-to-spot gcc register allocation bugs.
+ */
+#define _syscall0(type,name) \
+type name(void) \
+{ \
+  register long __a __asm__ ("r10"); \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall1(type,name,type1,arg1) \
+type name(type1 arg1) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2) \
+type name(type1 arg1,type2 arg2) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a), "r" (__b)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
+type name(type1 arg1,type2 arg2,type3 arg3) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a), "r" (__b), \
+                          "r" (__c), "r" (__d)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+          type5,arg5) \
+type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __e __asm__ ("mof") = (long) arg5; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a), "r" (__b), \
+                          "r" (__c), "r" (__d), "h" (__e)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+          type5,arg5,type6,arg6) \
+type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __e __asm__ ("mof") = (long) arg5; \
+  register long __f __asm__ ("srp") = (long) arg6; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
+                        ".err\n\t" \
+                        ".endif\n\t" \
+                        "break 13" \
+                        : "=r" (__a) \
+                        : "r" (__n_), "0" (__a), "r" (__b), \
+                          "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#endif
diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h
new file mode 100644
index 000000000000..03fa1f3c3c00
--- /dev/null
+++ b/include/asm-cris/arch-v32/user.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CRIS_ARCH_USER_H
+#define _ASM_CRIS_ARCH_USER_H
+
+/* User-mode register used for core dumps. */
+
+struct user_regs_struct {
+        unsigned long r0;       /* General registers. */
+        unsigned long r1;
+        unsigned long r2;
+        unsigned long r3;
+        unsigned long r4;
+        unsigned long r5;
+        unsigned long r6;
+        unsigned long r7;
+        unsigned long r8;
+        unsigned long r9;
+        unsigned long r10;
+        unsigned long r11;
+        unsigned long r12;
+        unsigned long r13;
+        unsigned long sp;       /* R14, Stack pointer. */
+        unsigned long acr;      /* R15, Address calculation register. */
+        unsigned long bz;       /* P0, Constant zero (8-bits). */
+        unsigned long vr;       /* P1, Version register (8-bits). */
+        unsigned long pid;      /* P2, Process ID (8-bits). */
+        unsigned long srs;      /* P3, Support register select (8-bits). */
+        unsigned long wz;       /* P4, Constant zero (16-bits). */
+        unsigned long exs;      /* P5, Exception status. */
+        unsigned long eda;      /* P6, Exception data address. */
+        unsigned long mof;      /* P7, Multiply overflow regiter. */
+        unsigned long dz;       /* P8, Constant zero (32-bits). */
+        unsigned long ebp;      /* P9, Exception base pointer. */
+        unsigned long erp;      /* P10, Exception return pointer. */
+        unsigned long srp;      /* P11, Subroutine return pointer. */
+        unsigned long nrp;      /* P12, NMI return pointer. */
+        unsigned long ccs;      /* P13, Condition code stack. */
+        unsigned long usp;      /* P14, User mode stack pointer. */
+        unsigned long spc;      /* P15, Single step PC. */
+};
+
+#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h
index b3dfea5a71e4..70605b09e8b7 100644
--- a/include/asm-cris/atomic.h
+++ b/include/asm-cris/atomic.h
@@ -4,21 +4,14 @@
 #define __ASM_CRIS_ATOMIC__
 
 #include <asm/system.h>
+#include <asm/arch/atomic.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
  * resource counting etc..
  */
 
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-
-#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x)
-
-typedef struct { int counter; } atomic_t;
+typedef struct { volatile int counter; } atomic_t;
 
 #define ATOMIC_INIT(i)  { (i) }
 
@@ -30,29 +23,26 @@ typedef struct { int counter; } atomic_t;
 extern __inline__ void atomic_add(int i, volatile atomic_t *v)
 {
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         v->counter += i;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
 }
 
 extern __inline__ void atomic_sub(int i, volatile atomic_t *v)
 {
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         v->counter -= i;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
 }
 
 extern __inline__ int atomic_add_return(int i, volatile atomic_t *v)
 {
         unsigned long flags;
         int retval;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = (v->counter += i);
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
@@ -62,10 +52,9 @@ extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v)
 {
         unsigned long flags;
         int retval;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = (v->counter -= i);
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
@@ -73,39 +62,35 @@ extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v)
 {
         int retval;
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = (v->counter -= i) == 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
 extern __inline__ void atomic_inc(volatile atomic_t *v)
 {
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         (v->counter)++;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
 }
 
 extern __inline__ void atomic_dec(volatile atomic_t *v)
 {
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         (v->counter)--;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
 }
 
 extern __inline__ int atomic_inc_return(volatile atomic_t *v)
 {
         unsigned long flags;
         int retval;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = (v->counter)++;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
@@ -113,20 +98,18 @@ extern __inline__ int atomic_dec_return(volatile atomic_t *v)
 {
         unsigned long flags;
         int retval;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = (v->counter)--;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 extern __inline__ int atomic_dec_and_test(volatile atomic_t *v)
 {
         int retval;
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = --(v->counter) == 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
@@ -134,10 +117,9 @@ extern __inline__ int atomic_inc_and_test(volatile atomic_t *v)
 {
         int retval;
         unsigned long flags;
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(v, flags);
         retval = ++(v->counter) == 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(v, flags);
         return retval;
 }
 
diff --git a/include/asm-cris/auxvec.h b/include/asm-cris/auxvec.h
new file mode 100644
index 000000000000..cb30b01bf19f
--- /dev/null
+++ b/include/asm-cris/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMCRIS_AUXVEC_H
+#define __ASMCRIS_AUXVEC_H
+
+#endif
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h
index 600bb8715d89..7a8d3114e682 100644
--- a/include/asm-cris/axisflashmap.h
+++ b/include/asm-cris/axisflashmap.h
@@ -40,4 +40,7 @@ struct partitiontable_entry {
 #define PARTITION_TYPE_KERNEL 0x0002
 #define PARTITION_TYPE_JFFS   0x0003
 
+/* The master mtd for the entire flash. */
+extern struct mtd_info* axisflash_mtd;
+
 #endif
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h
index d7861115d731..e3da57f97964 100644
--- a/include/asm-cris/bitops.h
+++ b/include/asm-cris/bitops.h
@@ -16,6 +16,7 @@
 
 #include <asm/arch/bitops.h>
 #include <asm/system.h>
+#include <asm/atomic.h>
 #include <linux/compiler.h>
 
 /*
@@ -88,7 +89,7 @@ struct __dummy { unsigned long a[100]; };
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_set_bit(int nr, void *addr)
+extern inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned long flags;
@@ -96,15 +97,15 @@ extern inline int test_and_set_bit(int nr, void *addr)
         
         adr += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(addr, flags);
         retval = (mask & *adr) != 0;
         *adr |= mask;
+        cris_atomic_restore(addr, flags);
         local_irq_restore(flags);
         return retval;
 }
 
-extern inline int __test_and_set_bit(int nr, void *addr)
+extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned int *adr = (unsigned int *)addr;
@@ -131,7 +132,7 @@ extern inline int __test_and_set_bit(int nr, void *addr)
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_clear_bit(int nr, void *addr)
+extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned long flags;
@@ -139,11 +140,10 @@ extern inline int test_and_clear_bit(int nr, void *addr)
         
         adr += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(addr, flags);
         retval = (mask & *adr) != 0;
         *adr &= ~mask;
-        local_irq_restore(flags);
+        cris_atomic_restore(addr, flags);
         return retval;
 }
 
@@ -157,7 +157,7 @@ extern inline int test_and_clear_bit(int nr, void *addr)
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 
-extern inline int __test_and_clear_bit(int nr, void *addr)
+extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned int *adr = (unsigned int *)addr;
@@ -177,24 +177,23 @@ extern inline int __test_and_clear_bit(int nr, void *addr)
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_change_bit(int nr, void *addr)
+extern inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned long flags;
         unsigned int *adr = (unsigned int *)addr;
         adr += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(addr, flags);
         retval = (mask & *adr) != 0;
         *adr ^= mask;
-        local_irq_restore(flags);
+        cris_atomic_restore(addr, flags);
         return retval;
 }
 
 /* WARNING: non atomic and it can be reordered! */
 
-extern inline int __test_and_change_bit(int nr, void *addr)
+extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
 {
         unsigned int mask, retval;
         unsigned int *adr = (unsigned int *)addr;
@@ -215,7 +214,7 @@ extern inline int __test_and_change_bit(int nr, void *addr)
  * This routine doesn't need to be atomic.
  */
 
-extern inline int test_bit(int nr, const void *addr)
+extern inline int test_bit(int nr, const volatile unsigned long *addr)
 {
         unsigned int mask;
         unsigned int *adr = (unsigned int *)addr;
@@ -259,7 +258,7 @@ extern inline int test_bit(int nr, const void *addr)
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
-extern inline int find_next_zero_bit (void * addr, int size, int offset)
+extern inline int find_next_zero_bit (const unsigned long * addr, int size, int offset)
 {
         unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
         unsigned long result = offset & ~31UL;
@@ -301,7 +300,7 @@ extern inline int find_next_zero_bit (void * addr, int size, int offset)
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
-static __inline__ int find_next_bit(void *addr, int size, int offset)
+static __inline__ int find_next_bit(const unsigned long *addr, int size, int offset)
 {
         unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
         unsigned long result = offset & ~31UL;
@@ -367,7 +366,7 @@ found_middle:
 #define minix_test_bit(nr,addr) test_bit(nr,addr)
 #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
 
-extern inline int sched_find_first_bit(unsigned long *b)
+extern inline int sched_find_first_bit(const unsigned long *b)
 {
         if (unlikely(b[0]))
                 return __ffs(b[0]);
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 0d770f60127a..0b5c3fdaefe1 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -1,125 +1,179 @@
+/* DMA mapping. Nothing tricky here, just virt_to_phys */
+
 #ifndef _ASM_CRIS_DMA_MAPPING_H
 #define _ASM_CRIS_DMA_MAPPING_H
 
-#include "scatterlist.h"
+#include <linux/mm.h>
+#include <linux/kernel.h>
 
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-        BUG();
-        return 0;
-}
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/scatterlist.h>
 
-static inline int
-dma_set_mask(struct device *dev, u64 dma_mask)
-{
-        BUG();
-        return 1;
-}
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+
+#ifdef CONFIG_PCI
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, int flag);
 
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+#else
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   int flag)
+                   int flag)
 {
-        BUG();
-        return NULL;
+        BUG();
+        return NULL;
 }
 
 static inline void
 dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-                    dma_addr_t dma_handle)
+                    dma_addr_t dma_handle)
 {
-        BUG();
+        BUG();
 }
-
+#endif
 static inline dma_addr_t
-dma_map_single(struct device *dev, void *cpu_addr, size_t size,
+dma_map_single(struct device *dev, void *ptr, size_t size,
                enum dma_data_direction direction)
 {
-        BUG();
-        return 0;
+        BUG_ON(direction == DMA_NONE);
+        return virt_to_phys(ptr);
 }
 
 static inline void
 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                  enum dma_data_direction direction)
 {
-        BUG();
+        BUG_ON(direction == DMA_NONE);
+}
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+           enum dma_data_direction direction)
+{
+        printk("Map sg\n");
+        return nents;
 }
 
 static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-             unsigned long offset, size_t size,
-             enum dma_data_direction direction)
+dma_map_page(struct device *dev, struct page *page, unsigned long offset,
+             size_t size, enum dma_data_direction direction)
 {
-        BUG();
-        return 0;
+        BUG_ON(direction == DMA_NONE);
+        return page_to_phys(page) + offset;
 }
 
 static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
                enum dma_data_direction direction)
 {
-        BUG();
+        BUG_ON(direction == DMA_NONE);
 }
 
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-           enum dma_data_direction direction)
-{
-        BUG();
-        return 1;
-}
 
 static inline void
 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
              enum dma_data_direction direction)
 {
-        BUG();
+        BUG_ON(direction == DMA_NONE);
 }
 
 static inline void
-dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
-                enum dma_data_direction direction)
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
+                        enum dma_data_direction direction)
 {
-        BUG();
 }
 
 static inline void
-dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
-            enum dma_data_direction direction)
+dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
+                        enum dma_data_direction direction)
 {
-        BUG();
 }
 
-/* Now for the API extensions over the pci_ one */
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                              unsigned long offset, size_t size,
+                              enum dma_data_direction direction)
+{
+}
 
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d)    (1)
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction direction)
+{
+}
 
-static inline int
-dma_get_cache_alignment(void)
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
+                    enum dma_data_direction direction)
 {
-        /* no easy way to get cache size on all processors, so return
-         * the maximum possible, to be safe */
-        return (1 << L1_CACHE_SHIFT_MAX);
 }
 
 static inline void
-dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
-                      unsigned long offset, size_t size,
-                      enum dma_data_direction direction)
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
+                    enum dma_data_direction direction)
 {
-        BUG();
 }
 
+static inline int
+dma_mapping_error(dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+static inline int
+dma_supported(struct device *dev, u64 mask)
+{
+        /*
+         * we fall back to GFP_DMA when the mask isn't all 1s,
+         * so we can't guarantee allocations that must be
+         * within a tighter range than GFP_DMA..
+         */
+        if(mask < 0x00ffffff)
+                return 0;
+
+        return 1;
+}
+
+static inline int
+dma_set_mask(struct device *dev, u64 mask)
+{
+        if(!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+static inline int
+dma_get_cache_alignment(void)
+{
+        return (1 << L1_CACHE_SHIFT_MAX);
+}
+
+#define dma_is_consistent(d)    (1)
+
 static inline void
 dma_cache_sync(void *vaddr, size_t size,
                enum dma_data_direction direction)
 {
-        BUG();
 }
 
-#endif
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+                            dma_addr_t device_addr, size_t size, int flags);
+
+extern void
+dma_release_declared_memory(struct device *dev);
 
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+                                  dma_addr_t device_addr, size_t size);
+
+#endif
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h
index c229fac35cdc..6f188dc56138 100644
--- a/include/asm-cris/dma.h
+++ b/include/asm-cris/dma.h
@@ -10,4 +10,12 @@
 
 #define MAX_DMA_ADDRESS PAGE_OFFSET
 
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
 #endif /* _ASM_DMA_H */
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
index d37fd5c4a567..87a60bd8e667 100644
--- a/include/asm-cris/elf.h
+++ b/include/asm-cris/elf.h
@@ -8,6 +8,27 @@
 #include <asm/arch/elf.h>
 #include <asm/user.h>
 
+#define R_CRIS_NONE             0
+#define R_CRIS_8                1
+#define R_CRIS_16               2
+#define R_CRIS_32               3
+#define R_CRIS_8_PCREL          4
+#define R_CRIS_16_PCREL         5
+#define R_CRIS_32_PCREL         6
+#define R_CRIS_GNU_VTINHERIT    7
+#define R_CRIS_GNU_VTENTRY      8
+#define R_CRIS_COPY             9
+#define R_CRIS_GLOB_DAT         10
+#define R_CRIS_JUMP_SLOT        11
+#define R_CRIS_RELATIVE         12
+#define R_CRIS_16_GOT           13
+#define R_CRIS_32_GOT           14
+#define R_CRIS_16_GOTPLT        15
+#define R_CRIS_32_GOTPLT        16
+#define R_CRIS_32_GOTREL        17
+#define R_CRIS_32_PLT_GOTREL    18
+#define R_CRIS_32_PLT_PCREL     19
+
 typedef unsigned long elf_greg_t;
 
 /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
@@ -19,17 +40,29 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef unsigned long elf_fpregset_t;
 
 /*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ( (x)->e_machine == EM_CRIS )
-
-/*
  * These are used to set parameters in the core dumps.
  */
 #define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB;
+#define ELF_DATA        ELFDATA2LSB
 #define ELF_ARCH        EM_CRIS
 
+/* The master for these definitions is {binutils}/include/elf/cris.h:  */
+/* User symbols in this file have a leading underscore.  */
+#define EF_CRIS_UNDERSCORE              0x00000001
+
+/* This is a mask for different incompatible machine variants.  */
+#define EF_CRIS_VARIANT_MASK            0x0000000e
+
+/* Variant 0; may contain v0..10 object.  */
+#define EF_CRIS_VARIANT_ANY_V0_V10      0x00000000
+
+/* Variant 1; contains v32 object.  */
+#define EF_CRIS_VARIANT_V32             0x00000002
+
+/* Variant 2; contains object compatible with v32 and v10.  */
+#define EF_CRIS_VARIANT_COMMON_V10_V32  0x00000004
+/* End of excerpt from {binutils}/include/elf/cris.h.  */
+
 #define USE_ELF_CORE_DUMP
 
 #define ELF_EXEC_PAGESIZE       8192
diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-cris/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h
index cf04af9635cc..80ee10f70d43 100644
--- a/include/asm-cris/etraxgpio.h
+++ b/include/asm-cris/etraxgpio.h
@@ -13,7 +13,7 @@
          are enabled.
  *
  *
- * For ETRAX 200 (ARCH_V32):
+ * For ETRAX FS (ARCH_V32):
  * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
  * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
  * /dev/gpioc  minor 2, 18 bit GPIO, each bit can change direction
@@ -39,10 +39,10 @@
 #define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
-#define GPIO_MINOR_C 2
-#define GPIO_MINOR_D 3
-#define GPIO_MINOR_E 4
-#define GPIO_MINOR_LEDS 5
+#define GPIO_MINOR_LEDS 2
+#define GPIO_MINOR_C 3
+#define GPIO_MINOR_D 4
+#define GPIO_MINOR_E 5
 #define GPIO_MINOR_LAST 5
 #endif
 
diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h
index 61c563242b51..46ab12db5739 100644
--- a/include/asm-cris/fcntl.h
+++ b/include/asm-cris/fcntl.h
@@ -1,90 +1 @@
-#ifndef _CRIS_FCNTL_H
-#define _CRIS_FCNTL_H
-
-/* verbatim copy of i386 version */
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get f_flags */
-#define F_SETFD         2       /* set f_flags */
-#define F_GETFL         3       /* more flags (cloexec) */
-#define F_SETFL         4
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64      12      /*  using 'struct flock64' */
-#define F_SETLK64      13
-#define F_SETLKW64     14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS   16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND      32      /* This is a mandatory flock */
-#define LOCK_READ      64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE     128     /* ... Which allows concurrent write operations */
-#define LOCK_RW        192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE  1024
-
-#endif
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-cris/futex.h b/include/asm-cris/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-cris/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h
index f4d136228ee1..1c13dd3faac3 100644
--- a/include/asm-cris/hardirq.h
+++ b/include/asm-cris/hardirq.h
@@ -1,18 +1,17 @@
 #ifndef __ASM_HARDIRQ_H
 #define __ASM_HARDIRQ_H
 
-/* only non-SMP supported */
-
 #include <linux/threads.h>
 #include <linux/cache.h>
 
-/* entry.S is sensitive to the offsets of these fields */
 typedef struct {
         unsigned int __softirq_pending;
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
 
+void ack_bad_irq(unsigned int irq);
+
 #define HARDIRQ_BITS    8
 
 /*
diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h
new file mode 100644
index 000000000000..341536a234e9
--- /dev/null
+++ b/include/asm-cris/hw_irq.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_HW_IRQ_H
+#define _ASM_HW_IRQ_H
+
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
+
+#endif
+
diff --git a/include/asm-cris/ide.h b/include/asm-cris/ide.h
new file mode 100644
index 000000000000..a894f66665f8
--- /dev/null
+++ b/include/asm-cris/ide.h
@@ -0,0 +1 @@
+#include <asm/arch/ide.h>
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h
index 1d2b51701e8d..16e791b3c721 100644
--- a/include/asm-cris/io.h
+++ b/include/asm-cris/io.h
@@ -3,6 +3,21 @@
 
 #include <asm/page.h>   /* for __va, __pa */
 #include <asm/arch/io.h>
+#include <linux/kernel.h>
+
+struct cris_io_operations
+{
+        u32 (*read_mem)(void *addr, int size);
+        void (*write_mem)(u32 val, int size, void *addr);
+        u32 (*read_io)(u32 port, void *addr, int size, int count);
+        void (*write_io)(u32 port, void *addr, int size, int count);
+};
+
+#ifdef CONFIG_PCI
+extern struct cris_io_operations *cris_iops;
+#else
+#define cris_iops ((struct cris_io_operations*)NULL)
+#endif
 
 /*
  * Change virtual addresses to physical addresses and vv.
@@ -18,14 +33,17 @@ extern inline void * phys_to_virt(unsigned long address)
         return __va(address);
 }
 
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
 
-extern inline void * ioremap (unsigned long offset, unsigned long size)
+extern inline void __iomem * ioremap (unsigned long offset, unsigned long size)
 {
         return __ioremap(offset, size, 0);
 }
 
-extern void iounmap(void *addr);
+extern void iounmap(volatile void * __iomem addr);
+
+extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
 
 /*
  * IO bus memory addresses are also 1:1 with the physical address
@@ -39,9 +57,32 @@ extern void iounmap(void *addr);
  * differently. On the CRIS architecture, we just read/write the
  * memory location directly.
  */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
+#ifdef CONFIG_PCI
+#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
+#else
+#define PCI_SPACE(x) 0
+#endif
+static inline unsigned char readb(const volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                return cris_iops->read_mem((void*)addr, 1);
+        else
+                return *(volatile unsigned char __force *) addr;
+}
+static inline unsigned short readw(const volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                return cris_iops->read_mem((void*)addr, 2);
+        else
+                return *(volatile unsigned short __force *) addr;
+}
+static inline unsigned int readl(const volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                return cris_iops->read_mem((void*)addr, 4);
+        else
+                return *(volatile unsigned int __force *) addr;
+}
 #define readb_relaxed(addr) readb(addr)
 #define readw_relaxed(addr) readw(addr)
 #define readl_relaxed(addr) readl(addr)
@@ -49,9 +90,27 @@ extern void iounmap(void *addr);
 #define __raw_readw readw
 #define __raw_readl readl
 
-#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
+static inline void writeb(unsigned char b, volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                cris_iops->write_mem(b, 1, (void*)addr);
+        else
+                *(volatile unsigned char __force *) addr = b;
+}
+static inline void writew(unsigned short b, volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                cris_iops->write_mem(b, 2, (void*)addr);
+        else
+                *(volatile unsigned short __force *) addr = b;
+}
+static inline void writel(unsigned int b, volatile void __iomem *addr)
+{
+        if (PCI_SPACE(addr) && cris_iops)
+                cris_iops->write_mem(b, 4, (void*)addr);
+        else
+                *(volatile unsigned int __force *) addr = b;
+}
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
@@ -66,25 +125,25 @@ extern void iounmap(void *addr);
  * Again, CRIS does not require mem IO specific function.
  */
 
-#define eth_io_copy_and_sum(a,b,c,d)    eth_copy_and_sum((a),(void *)(b),(c),(d))
+#define eth_io_copy_and_sum(a,b,c,d)    eth_copy_and_sum((a),(void __force *)(b),(c),(d))
 
 /* The following is junk needed for the arch-independent code but which
  * we never use in the CRIS port
  */
 
 #define IO_SPACE_LIMIT 0xffff
-#define inb(x) (0)
-#define inw(x) (0)
-#define inl(x) (0)
-#define outb(x,y)
-#define outw(x,y)
-#define outl(x,y)
-#define insb(x,y,z)
-#define insw(x,y,z)
-#define insl(x,y,z)
-#define outsb(x,y,z)
-#define outsw(x,y,z)
-#define outsl(x,y,z)
+#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
+#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
+#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
+#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
+#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
+#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
+#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1)
+#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1)
+#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1)
+#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count)
+#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count)
+#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count)
 
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h
index 87f342517bb1..4fab5c3b2e15 100644
--- a/include/asm-cris/irq.h
+++ b/include/asm-cris/irq.h
@@ -1,6 +1,11 @@
 #ifndef _ASM_IRQ_H
 #define _ASM_IRQ_H
 
+/*
+ * IRQ line status macro IRQ_PER_CPU is used
+ */
+#define ARCH_HAS_IRQ_PER_CPU
+
 #include <asm/arch/irq.h>
 
 extern __inline__ int irq_canonicalize(int irq)
@@ -8,16 +13,6 @@ extern __inline__ int irq_canonicalize(int irq)
   return irq; 
 }
 
-extern void disable_irq(unsigned int);
-extern void enable_irq(unsigned int);
-
-#define disable_irq_nosync      disable_irq
-#define enable_irq_nosync       enable_irq
-
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
-
 #endif  /* _ASM_IRQ_H */
 
 
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h
index eec0974c2417..492988cb9077 100644
--- a/include/asm-cris/kmap_types.h
+++ b/include/asm-cris/kmap_types.h
@@ -17,8 +17,8 @@ enum km_type {
         KM_PTE1,
         KM_IRQ0,
         KM_IRQ1,
-        KM_CRYPTO_USER,
-        KM_CRYPTO_SOFTIRQ,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
         KM_TYPE_NR
 };
 
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h
index f9308c5bbd99..e6e659dc757b 100644
--- a/include/asm-cris/mmu_context.h
+++ b/include/asm-cris/mmu_context.h
@@ -15,7 +15,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  * registers like cr3 on the i386
  */
 
-extern volatile pgd_t *current_pgd;   /* defined in arch/cris/mm/fault.c */
+extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */
 
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h
index c767da1ef8f5..c99c478c482f 100644
--- a/include/asm-cris/page.h
+++ b/include/asm-cris/page.h
@@ -29,18 +29,15 @@
  */
 #ifndef __ASSEMBLY__
 typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 #endif
 
 #define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((x).pmd)
 #define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
 
 #define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
@@ -73,23 +70,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 #ifndef __ASSEMBLY__
 
-#define BUG() do { \
-  printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
-} while (0)
-
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
 #endif /* __ASSEMBLY__ */
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
@@ -97,5 +77,7 @@ static inline int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _CRIS_PAGE_H */
 
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h
index c61041531889..2064bc1de074 100644
--- a/include/asm-cris/pci.h
+++ b/include/asm-cris/pci.h
@@ -1,13 +1,105 @@
 #ifndef __ASM_CRIS_PCI_H
 #define __ASM_CRIS_PCI_H
 
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+#include <linux/mm.h>           /* for struct page */
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+#define pcibios_assign_all_busses(void) 1
+
+extern unsigned long pci_mem_start;
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x10000000
+
+#define PCIBIOS_MIN_CARDBUS_IO  0x4000
+
+void pcibios_config_init(void);
+struct pci_bus * pcibios_scan_root(int bus);
+int pcibios_assign_resources(void);
+
+void pcibios_set_master(struct pci_dev *dev);
+void pcibios_penalize_isa_irq(int irq);
+struct irq_routing_table *pcibios_get_irq_routing_table(void);
+int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
+
+/* Dynamic DMA mapping stuff.
+ * i386 has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
 #include <asm/scatterlist.h>
-#include <asm-generic/pci-dma-compat.h>
+#include <linux/string.h>
+#include <asm/io.h>
 
-/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code
- * includes it even if CONFIG_PCI is not set.
+struct pci_dev;
+
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
  */
-#define PCI_DMA_BUS_IS_PHYS       (1)
+#define PCI_DMA_BUS_IS_PHYS     (1)
 
-#endif /* __ASM_CRIS_PCI_H */
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+/* This is always fine. */
+#define pci_dac_dma_supported(pci_dev, mask)    (1)
 
+static inline dma64_addr_t
+pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
+{
+        return ((dma64_addr_t) page_to_phys(page) +
+                (dma64_addr_t) offset);
+}
+
+static inline struct page *
+pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
+{
+        return pfn_to_page(dma_addr >> PAGE_SHIFT);
+}
+
+static inline unsigned long
+pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
+{
+        return (dma_addr & ~PAGE_MASK);
+}
+
+static inline void
+pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
+{
+}
+
+static inline void
+pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
+{
+}
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+                               enum pci_mmap_state mmap_state, int write_combine);
+
+
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+
+#endif /* __KERNEL__ */
+
+/* implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+#endif /* __ASM_CRIS_PCI_H */
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h
index b202e62ed6e0..a131776edf41 100644
--- a/include/asm-cris/pgalloc.h
+++ b/include/asm-cris/pgalloc.h
@@ -47,16 +47,6 @@ extern inline void pte_free(struct page *pte)
 
 #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
 
-/*
- * We don't have any real pmd's, and this code never triggers because
- * the pgd will always be present..
- */
-
-#define pmd_alloc_one(mm, addr)    ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(x)                do { } while (0)
-#define __pmd_free_tlb(tlb,x)      do { } while (0)
-#define pgd_populate(mm, pmd, pte) BUG()
-
 #define check_pgt_cache()          do { } while (0)
 
 #endif
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h
index f7042944b073..a9143bed99db 100644
--- a/include/asm-cris/pgtable.h
+++ b/include/asm-cris/pgtable.h
@@ -5,7 +5,8 @@
 #ifndef _CRIS_PGTABLE_H
 #define _CRIS_PGTABLE_H
 
-#include <asm-generic/4level-fixup.h>
+#include <asm/page.h>
+#include <asm-generic/pgtable-nopmd.h>
 
 #ifndef __ASSEMBLY__
 #include <linux/config.h>
@@ -41,22 +42,14 @@ extern void paging_init(void);
  * but the define is needed for a generic inline function.)
  */
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
+#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
 
-/* PMD_SHIFT determines the size of the area a second-level page table can
+/* PGDIR_SHIFT determines the size of the area a second-level page table can
  * map. It is equal to the page size times the number of PTE's that fit in
  * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
  */
 
-#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-2))
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map.
- * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
- */
-
-#define PGDIR_SHIFT     PMD_SHIFT
+#define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-2))
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
@@ -67,7 +60,6 @@ extern void paging_init(void);
  * divide it by 4 (shift by 2).
  */
 #define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-2))
-#define PTRS_PER_PMD    1
 #define PTRS_PER_PGD    (1UL << (PAGE_SHIFT-2))
 
 /* calculate how many PGD entries a user-level program can use
@@ -105,7 +97,7 @@ extern unsigned long empty_zero_page;
 #define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
 #define pte_clear(mm,addr,xp)   do { pte_val(*(xp)) = 0; } while (0)
 
-#define pmd_none(x)     (!pmd_val(x))
+#define pmd_none(x)     (!pmd_val(x))
 /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
  * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
  */
@@ -116,16 +108,6 @@ extern unsigned long empty_zero_page;
 #ifndef __ASSEMBLY__
 
 /*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-extern inline int pgd_none(pgd_t pgd)           { return 0; }
-extern inline int pgd_bad(pgd_t pgd)            { return 0; }
-extern inline int pgd_present(pgd_t pgd)        { return 1; }
-extern inline void pgd_clear(pgd_t * pgdp)      { }
-
-/*
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
@@ -275,7 +257,7 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
 #define pmd_page_kernel(pmd)    ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 
 /* to find an entry in a page-table-directory. */
-#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 
 /* to find an entry in a page-table-directory */
 extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
@@ -286,12 +268,6 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
-/* Find an entry in the second-level page table.. */
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address) \
         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -308,8 +284,6 @@ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
 
@@ -348,5 +322,7 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma,
 #define pte_to_pgoff(x) (pte_val(x) >> 6)
 #define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE)
 
+typedef pte_t *pte_addr_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* _CRIS_PGTABLE_H */
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h
index 623bdf06d911..0dc218117bd8 100644
--- a/include/asm-cris/processor.h
+++ b/include/asm-cris/processor.h
@@ -55,15 +55,6 @@ unsigned long get_wchan(struct task_struct *p);
 
 #define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
 
-/*
- * Free current thread data structures etc..
- */
-
-extern inline void exit_thread(void)
-{
-        /* Nothing needs to be done.  */
-}
-
 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 
 /* Free all resources held by a thread. */
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h
index 7a8c2880e487..1ec69a7ea836 100644
--- a/include/asm-cris/ptrace.h
+++ b/include/asm-cris/ptrace.h
@@ -9,4 +9,6 @@
 #define PTRACE_SETREGS            13
 #endif
 
+#define profile_pc(regs) instruction_pointer(regs)
+
 #endif /* _CRIS_PTRACE_H */
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h
index 605aa7eaaaf8..8ed7636ab311 100644
--- a/include/asm-cris/semaphore.h
+++ b/include/asm-cris/semaphore.h
@@ -72,10 +72,9 @@ extern inline void down(struct semaphore * sem)
         might_sleep();
 
         /* atomically decrement the semaphores count, and if its negative, we wait */
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(sem, flags);
         failed = --(sem->count.counter) < 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(sem, flags);
         if(failed) {
                 __down(sem);
         }
@@ -95,10 +94,9 @@ extern inline int down_interruptible(struct semaphore * sem)
         might_sleep();
 
         /* atomically decrement the semaphores count, and if its negative, we wait */
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(sem, flags);
         failed = --(sem->count.counter) < 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(sem, flags);
         if(failed)
                 failed = __down_interruptible(sem);
         return(failed);
@@ -109,13 +107,13 @@ extern inline int down_trylock(struct semaphore * sem)
         unsigned long flags;
         int failed;
 
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(sem, flags);
         failed = --(sem->count.counter) < 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(sem, flags);
         if(failed)
                 failed = __down_trylock(sem);
         return(failed);
+
 }
 
 /*
@@ -130,10 +128,9 @@ extern inline void up(struct semaphore * sem)
         int wakeup;
 
         /* atomically increment the semaphores count, and if it was negative, we wake people */
-        local_save_flags(flags);
-        local_irq_disable();
+        cris_atomic_save(sem, flags);
         wakeup = ++(sem->count.counter) <= 0;
-        local_irq_restore(flags);
+        cris_atomic_restore(sem, flags);
         if(wakeup) {
                 __up(sem);
         }
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h
index c2f4feaa041d..dca5ef1d8c97 100644
--- a/include/asm-cris/smp.h
+++ b/include/asm-cris/smp.h
@@ -1,4 +1,11 @@
 #ifndef __ASM_SMP_H
 #define __ASM_SMP_H
 
+#include <linux/cpumask.h>
+
+extern cpumask_t phys_cpu_present_map;
+#define cpu_possible_map phys_cpu_present_map
+
+#define __smp_processor_id() (current_thread_info()->cpu)
+
 #endif
diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h
index f159b4f165f7..8b1da3e58c55 100644
--- a/include/asm-cris/socket.h
+++ b/include/asm-cris/socket.h
@@ -16,6 +16,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h
new file mode 100644
index 000000000000..2e8ba8afc7af
--- /dev/null
+++ b/include/asm-cris/spinlock.h
@@ -0,0 +1 @@
+#include <asm/arch/spinlock.h>
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h
new file mode 100644
index 000000000000..f930b6e00663
--- /dev/null
+++ b/include/asm-cris/sync_serial.h
@@ -0,0 +1,106 @@
+/*
+ * ioctl defines for synchronous serial port driver
+ *
+ * Copyright (c) 2001-2003 Axis Communications AB
+ *
+ * Author: Mikael Starvik
+ *
+ */
+
+#ifndef SYNC_SERIAL_H
+#define SYNC_SERIAL_H
+
+#include <linux/ioctl.h>
+
+#define SSP_SPEED      _IOR('S', 0, unsigned int)
+#define SSP_MODE       _IOR('S', 1, unsigned int)
+#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
+#define SSP_IPOLARITY  _IOR('S', 3, unsigned int)
+#define SSP_OPOLARITY  _IOR('S', 4, unsigned int)
+#define SSP_SPI        _IOR('S', 5, unsigned int)
+#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
+
+/* Values for SSP_SPEED */
+#define SSP150        0
+#define SSP300        1
+#define SSP600        2
+#define SSP1200       3
+#define SSP2400       4
+#define SSP4800       5
+#define SSP9600       6
+#define SSP19200      7
+#define SSP28800      8
+#define SSP57600      9
+#define SSP115200    10
+#define SSP230400    11
+#define SSP460800    12
+#define SSP921600    13
+#define SSP3125000   14
+#define CODEC        15
+
+#define FREQ_4MHz   0
+#define FREQ_2MHz   1
+#define FREQ_1MHz   2
+#define FREQ_512kHz 3
+#define FREQ_256kHz 4
+#define FREQ_128kHz 5
+#define FREQ_64kHz  6
+#define FREQ_32kHz  7
+
+/* Used by application to set CODEC divider, word rate and frame rate */
+#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
+
+/* Used by driver to extract speed */
+#define GET_SPEED(x) (x & 0xff)
+#define GET_FREQ(x) ((x & 0xff00) >> 8)
+#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
+#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
+
+/* Values for SSP_MODE */
+#define MASTER_OUTPUT 0
+#define SLAVE_OUTPUT  1
+#define MASTER_INPUT  2
+#define SLAVE_INPUT   3
+#define MASTER_BIDIR  4
+#define SLAVE_BIDIR   5
+
+/* Values for SSP_FRAME_SYNC */
+#define NORMAL_SYNC                1
+#define EARLY_SYNC                 2
+
+#define BIT_SYNC                   4
+#define WORD_SYNC                  8
+#define EXTENDED_SYNC           0x10
+
+#define SYNC_OFF                0x20
+#define SYNC_ON                 0x40
+#define WORD_SIZE_8             0x80
+#define WORD_SIZE_12           0x100
+#define WORD_SIZE_16           0x200
+#define WORD_SIZE_24           0x400
+#define WORD_SIZE_32           0x800
+#define BIT_ORDER_LSB         0x1000
+#define BIT_ORDER_MSB         0x2000
+#define FLOW_CONTROL_ENABLE   0x4000
+#define FLOW_CONTROL_DISABLE  0x8000
+#define CLOCK_GATED          0x10000
+#define CLOCK_NOT_GATED      0x20000
+
+/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
+#define CLOCK_NORMAL         1
+#define CLOCK_INVERT         2
+#define CLOCK_INEGEDGE       CLOCK_NORMAL
+#define CLOCK_IPOSEDGE       CLOCK_INVERT
+#define FRAME_NORMAL         4
+#define FRAME_INVERT         8
+#define STATUS_NORMAL      0x10
+#define STATUS_INVERT      0x20
+
+/* Values for SSP_SPI */
+#define SPI_MASTER           0
+#define SPI_SLAVE            1
+
+/* Values for SSP_INBUFCHUNK */
+/* plain integer with the size of DMA chunks */
+
+#endif
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
index 16d9a491fdb3..be0836d2f282 100644
--- a/include/asm-cris/termbits.h
+++ b/include/asm-cris/termbits.h
@@ -152,7 +152,7 @@ struct termios {
 #define  B921600   0010005
 #define  B1843200  0010006
 #define  B6250000  0010007
-/* etrax 200 supports this as well */
+/* ETRAX FS supports this as well */
 #define  B12500000 0010010
 #define CIBAUD    002003600000  /* input baud rate (used in v32) */
 /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h
index 53193feb0826..cef0140fc104 100644
--- a/include/asm-cris/thread_info.h
+++ b/include/asm-cris/thread_info.h
@@ -31,7 +31,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
         mm_segment_t            addr_limit;     /* thread address space:
                                                    0-0xBFFFFFFF for user-thead
@@ -43,7 +43,7 @@ struct thread_info {
 
 #endif
 
-#define PREEMPT_ACTIVE          0x4000000
+#define PREEMPT_ACTIVE          0x10000000
 
 /*
  * macros/functions for gaining access to the thread information structure
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h
index 375c41af47de..3fb069a37717 100644
--- a/include/asm-cris/timex.h
+++ b/include/asm-cris/timex.h
@@ -14,7 +14,7 @@
  * used so it does not matter.
  */
 
-typedef unsigned int cycles_t;
+typedef unsigned long long cycles_t;
 
 extern inline cycles_t get_cycles(void)
 {
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h
index 1781fe1a32f6..6ed7d9ae90db 100644
--- a/include/asm-cris/tlbflush.h
+++ b/include/asm-cris/tlbflush.h
@@ -18,13 +18,26 @@
  *
  */
 
+extern void __flush_tlb_all(void);
+extern void __flush_tlb_mm(struct mm_struct *mm);
+extern void __flush_tlb_page(struct vm_area_struct *vma,
+                           unsigned long addr);
+
+#ifdef CONFIG_SMP
 extern void flush_tlb_all(void);
 extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_page(struct vm_area_struct *vma, 
                            unsigned long addr);
-extern void flush_tlb_range(struct vm_area_struct *vma,
-                            unsigned long start,
-                            unsigned long end);
+#else
+#define flush_tlb_all __flush_tlb_all
+#define flush_tlb_mm __flush_tlb_mm
+#define flush_tlb_page __flush_tlb_page
+#endif
+
+static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
+{
+        flush_tlb_mm(vma->vm_mm);
+}
 
 extern inline void flush_tlb_pgtables(struct mm_struct *mm,
                                       unsigned long start, unsigned long end)
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h
index 41a0d450ba1d..84557c9bac93 100644
--- a/include/asm-cris/types.h
+++ b/include/asm-cris/types.h
@@ -52,8 +52,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h
index 6db17221fd9e..7d50086eb5ea 100644
--- a/include/asm-cris/uaccess.h
+++ b/include/asm-cris/uaccess.h
@@ -91,13 +91,6 @@
 #define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
 #define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
-
 #include <asm/arch/uaccess.h>
 
 /*
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
index e80bf276b101..28232ad2ff34 100644
--- a/include/asm-cris/unistd.h
+++ b/include/asm-cris/unistd.h
@@ -288,8 +288,15 @@
 #define __NR_mq_timedreceive    (__NR_mq_open+3)
 #define __NR_mq_notify          (__NR_mq_open+4)
 #define __NR_mq_getsetattr      (__NR_mq_open+5)
- 
-#define NR_syscalls 283
+#define __NR_sys_kexec_load     283
+#define __NR_waitid             284
+/* #define __NR_sys_setaltroot  285 */
+#define __NR_add_key            286
+#define __NR_request_key        287
+#define __NR_keyctl             288
+
+#define NR_syscalls 289
+
 
 
 #ifdef __KERNEL__
diff --git a/include/asm-frv/auxvec.h b/include/asm-frv/auxvec.h
new file mode 100644
index 000000000000..07710778fa10
--- /dev/null
+++ b/include/asm-frv/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __FRV_AUXVEC_H
+#define __FRV_AUXVEC_H
+
+#endif
diff --git a/include/asm-frv/emergency-restart.h b/include/asm-frv/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-frv/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-frv/fcntl.h b/include/asm-frv/fcntl.h
index d61b999f9973..46ab12db5739 100644
--- a/include/asm-frv/fcntl.h
+++ b/include/asm-frv/fcntl.h
@@ -1,88 +1 @@
-#ifndef _ASM_FCNTL_H
-#define _ASM_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-#endif /* _ASM_FCNTL_H */
-
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-frv/futex.h b/include/asm-frv/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-frv/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-frv/page.h b/include/asm-frv/page.h
index f7914f1782b0..4feba567e7fd 100644
--- a/include/asm-frv/page.h
+++ b/include/asm-frv/page.h
@@ -45,21 +45,6 @@ typedef struct { unsigned long	pgprot;	} pgprot_t;
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
 
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size) __attribute_const__;
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size - 1) >> (PAGE_SHIFT - 1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #define devmem_is_allowed(pfn)  1
 
 #define __pa(vaddr)             virt_to_phys((void *) vaddr)
@@ -102,4 +87,6 @@ extern unsigned long max_pfn;
 #define WANT_PAGE_VIRTUAL       1
 #endif
 
+#include <asm-generic/page.h>
+
 #endif /* _ASM_PAGE_H */
diff --git a/include/asm-frv/pci.h b/include/asm-frv/pci.h
index a6a469231f62..b4efe5e3591a 100644
--- a/include/asm-frv/pci.h
+++ b/include/asm-frv/pci.h
@@ -57,6 +57,16 @@ extern void pci_free_consistent(struct pci_dev *hwdev, size_t size,
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 /*
  *      These are pretty much arbitary with the CoMEM implementation.
  *      We have the whole address space to ourselves.
diff --git a/include/asm-frv/socket.h b/include/asm-frv/socket.h
index c3be17c7de4b..7177f8b9817c 100644
--- a/include/asm-frv/socket.h
+++ b/include/asm-frv/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-frv/thread_info.h b/include/asm-frv/thread_info.h
index b80a97f50af6..c8cba7836f0d 100644
--- a/include/asm-frv/thread_info.h
+++ b/include/asm-frv/thread_info.h
@@ -33,7 +33,7 @@ struct thread_info {
         unsigned long           flags;          /* low level flags */
         unsigned long           status;         /* thread-synchronous flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count;  /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
         mm_segment_t            addr_limit;     /* thread address space:
                                                    0-0xBFFFFFFF for user-thead
diff --git a/include/asm-frv/types.h b/include/asm-frv/types.h
index 1a5b6546bb41..50605df6d8ac 100644
--- a/include/asm-frv/types.h
+++ b/include/asm-frv/types.h
@@ -65,8 +65,6 @@ typedef u64 u_quad_t;
 
 typedef u32 dma_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-frv/uaccess.h b/include/asm-frv/uaccess.h
index 32dc52e883e5..991b50fbba24 100644
--- a/include/asm-frv/uaccess.h
+++ b/include/asm-frv/uaccess.h
@@ -67,12 +67,6 @@ static inline int ___range_ok(unsigned long addr, unsigned long size)
 #define access_ok(type,addr,size) (__range_ok((addr), (size)) == 0)
 #define __access_ok(addr,size) (__range_ok((addr), (size)) == 0)
 
-/* this function will go away soon - use access_ok() / __range_ok() instead */
-static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-{
-        return __range_ok(addr, size);
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-generic/emergency-restart.h b/include/asm-generic/emergency-restart.h
new file mode 100644
index 000000000000..0d68a1eae985
--- /dev/null
+++ b/include/asm-generic/emergency-restart.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_GENERIC_EMERGENCY_RESTART_H
+#define _ASM_GENERIC_EMERGENCY_RESTART_H
+
+static inline void machine_emergency_restart(void)
+{
+        machine_restart(NULL);
+}
+
+#endif /* _ASM_GENERIC_EMERGENCY_RESTART_H */
diff --git a/include/asm-generic/fcntl.h b/include/asm-generic/fcntl.h
new file mode 100644
index 000000000000..b663520dcdc4
--- /dev/null
+++ b/include/asm-generic/fcntl.h
@@ -0,0 +1,149 @@
+#ifndef _ASM_GENERIC_FCNTL_H
+#define _ASM_GENERIC_FCNTL_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_ACCMODE       00000003
+#define O_RDONLY        00000000
+#define O_WRONLY        00000001
+#define O_RDWR          00000002
+#ifndef O_CREAT
+#define O_CREAT         00000100        /* not fcntl */
+#endif
+#ifndef O_EXCL
+#define O_EXCL          00000200        /* not fcntl */
+#endif
+#ifndef O_NOCTTY
+#define O_NOCTTY        00000400        /* not fcntl */
+#endif
+#ifndef O_TRUNC
+#define O_TRUNC         00001000        /* not fcntl */
+#endif
+#ifndef O_APPEND
+#define O_APPEND        00002000
+#endif
+#ifndef O_NONBLOCK
+#define O_NONBLOCK      00004000
+#endif
+#ifndef O_SYNC
+#define O_SYNC          00010000
+#endif
+#ifndef FASYNC
+#define FASYNC          00020000        /* fcntl, for BSD compatibility */
+#endif
+#ifndef O_DIRECT
+#define O_DIRECT        00040000        /* direct disk access hint */
+#endif
+#ifndef O_LARGEFILE
+#define O_LARGEFILE     00100000
+#endif
+#ifndef O_DIRECTORY
+#define O_DIRECTORY     00200000        /* must be a directory */
+#endif
+#ifndef O_NOFOLLOW
+#define O_NOFOLLOW      00400000        /* don't follow links */
+#endif
+#ifndef O_NOATIME
+#define O_NOATIME       01000000
+#endif
+#ifndef O_NDELAY
+#define O_NDELAY        O_NONBLOCK
+#endif
+
+#define F_DUPFD         0       /* dup */
+#define F_GETFD         1       /* get close_on_exec */
+#define F_SETFD         2       /* set/clear close_on_exec */
+#define F_GETFL         3       /* get file->f_flags */
+#define F_SETFL         4       /* set file->f_flags */
+#ifndef F_GETLK
+#define F_GETLK         5
+#define F_SETLK         6
+#define F_SETLKW        7
+#endif
+#ifndef F_SETOWN
+#define F_SETOWN        8       /* for sockets. */
+#define F_GETOWN        9       /* for sockets. */
+#endif
+#ifndef F_SETSIG
+#define F_SETSIG        10      /* for sockets. */
+#define F_GETSIG        11      /* for sockets. */
+#endif
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#ifndef F_RDLCK
+#define F_RDLCK         0
+#define F_WRLCK         1
+#define F_UNLCK         2
+#endif
+
+/* for old implementation of bsd flock () */
+#ifndef F_EXLCK
+#define F_EXLCK         4       /* or 3 */
+#define F_SHLCK         8       /* or 4 */
+#endif
+
+/* for leases */
+#ifndef F_INPROGRESS
+#define F_INPROGRESS    16
+#endif
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH         1       /* shared lock */
+#define LOCK_EX         2       /* exclusive lock */
+#define LOCK_NB         4       /* or'd with one of the above to prevent
+                                   blocking */
+#define LOCK_UN         8       /* remove lock */
+
+#define LOCK_MAND       32      /* This is a mandatory flock ... */
+#define LOCK_READ       64      /* which allows concurrent read operations */
+#define LOCK_WRITE      128     /* which allows concurrent write operations */
+#define LOCK_RW         192     /* which allows concurrent read & write ops */
+
+#define F_LINUX_SPECIFIC_BASE   1024
+
+#ifndef HAVE_ARCH_STRUCT_FLOCK
+#ifndef __ARCH_FLOCK_PAD
+#define __ARCH_FLOCK_PAD
+#endif
+
+struct flock {
+        short   l_type;
+        short   l_whence;
+        off_t   l_start;
+        off_t   l_len;
+        pid_t   l_pid;
+        __ARCH_FLOCK_PAD
+};
+#endif
+
+#ifndef CONFIG_64BIT
+
+#ifndef F_GETLK64
+#define F_GETLK64       12      /*  using 'struct flock64' */
+#define F_SETLK64       13
+#define F_SETLKW64      14
+#endif
+
+#ifndef HAVE_ARCH_STRUCT_FLOCK64
+#ifndef __ARCH_FLOCK64_PAD
+#define __ARCH_FLOCK64_PAD
+#endif
+
+struct flock64 {
+        short  l_type;
+        short  l_whence;
+        loff_t l_start;
+        loff_t l_len;
+        pid_t  l_pid;
+        __ARCH_FLOCK64_PAD
+};
+#endif
+#endif /* !CONFIG_64BIT */
+
+#endif /* _ASM_GENERIC_FCNTL_H */
diff --git a/include/asm-generic/hdreg.h b/include/asm-generic/hdreg.h
deleted file mode 100644
index 7051fba8bcf9..000000000000
--- a/include/asm-generic/hdreg.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#warning <asm/hdreg.h> is obsolete, please do not use it
-
-#ifndef __ASM_GENERIC_HDREG_H
-#define __ASM_GENERIC_HDREG_H
-
-typedef unsigned long ide_ioreg_t;
-
-#endif /* __ASM_GENERIC_HDREG_H */
diff --git a/include/asm-generic/page.h b/include/asm-generic/page.h
new file mode 100644
index 000000000000..a96b5d986b6e
--- /dev/null
+++ b/include/asm-generic/page.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_GENERIC_PAGE_H
+#define _ASM_GENERIC_PAGE_H
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+
+/* Pure 2^n version of get_order */
+static __inline__ __attribute_const__ int get_order(unsigned long size)
+{
+        int order;
+
+        size = (size - 1) >> (PAGE_SHIFT - 1);
+        order = -1;
+        do {
+                size >>= 1;
+                order++;
+        } while (size);
+        return order;
+}
+
+#endif  /* __ASSEMBLY__ */
+#endif  /* __KERNEL__ */
+
+#endif  /* _ASM_GENERIC_PAGE_H */
diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index 9d4cc47bde39..ee1d8b5d8168 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -22,6 +22,14 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
         region->end = res->end;
 }
 
+static inline void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region)
+{
+        res->start = region->start;
+        res->end = region->end;
+}
+
 #define pcibios_scan_all_fns(a, b)      0
 
 #ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
diff --git a/include/asm-generic/percpu.h b/include/asm-generic/percpu.h
index 3b709b84934f..9044aeb37828 100644
--- a/include/asm-generic/percpu.h
+++ b/include/asm-generic/percpu.h
@@ -29,7 +29,7 @@ do {								\
 #define DEFINE_PER_CPU(type, name) \
     __typeof__(type) per_cpu__##name
 
-#define per_cpu(var, cpu)                       (*((void)cpu, &per_cpu__##var))
+#define per_cpu(var, cpu)                       (*((void)(cpu), &per_cpu__##var))
 #define __get_cpu_var(var)                      per_cpu__##var
 
 #endif  /* SMP */
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 1f4ec7b70270..f86c1e549466 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -101,6 +101,22 @@ do {				  					  \
 })
 #endif
 
+#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
+#define ptep_get_and_clear_full(__mm, __address, __ptep, __full)        \
+({                                                                      \
+        pte_t __pte;                                                    \
+        __pte = ptep_get_and_clear((__mm), (__address), (__ptep));      \
+        __pte;                                                          \
+})
+#endif
+
+#ifndef __HAVE_ARCH_PTE_CLEAR_FULL
+#define pte_clear_full(__mm, __address, __ptep, __full)                 \
+do {                                                                    \
+        pte_clear((__mm), (__address), (__ptep));                       \
+} while (0)
+#endif
+
 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
 #define ptep_clear_flush(__vma, __address, __ptep)                      \
 ({                                                                      \
@@ -125,6 +141,9 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
 
 #ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
 #define page_test_and_clear_dirty(page) (0)
+#define pte_maybe_dirty(pte)            pte_dirty(pte)
+#else
+#define pte_maybe_dirty(pte)            (1)
 #endif
 
 #ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 195ccdc069e6..886dbd116899 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -11,5 +11,7 @@ extern char _sinittext[], _einittext[];
 extern char _sextratext[] __attribute__((weak));
 extern char _eextratext[] __attribute__((weak));
 extern char _end[];
+extern char __per_cpu_start[], __per_cpu_end[];
+extern char __kprobes_text_start[], __kprobes_text_end[];
 
 #endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-generic/topology.h b/include/asm-generic/topology.h
index ec96e8b0f190..5d9d70cd17fc 100644
--- a/include/asm-generic/topology.h
+++ b/include/asm-generic/topology.h
@@ -41,8 +41,15 @@
 #ifndef node_to_first_cpu
 #define node_to_first_cpu(node) (0)
 #endif
+#ifndef pcibus_to_node
+#define pcibus_to_node(node)    (-1)
+#endif
+
 #ifndef pcibus_to_cpumask
-#define pcibus_to_cpumask(bus)  (cpu_online_map)
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
 #endif
 
 #endif /* _ASM_GENERIC_TOPOLOGY_H */
diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h
index 6c90f0f36eec..4dc8ddb401c1 100644
--- a/include/asm-generic/unaligned.h
+++ b/include/asm-generic/unaligned.h
@@ -16,9 +16,9 @@
  * The main single-value unaligned transfer routines.
  */
 #define get_unaligned(ptr) \
-        ((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr))))
+        __get_unaligned((ptr), sizeof(*(ptr)))
 #define put_unaligned(x,ptr) \
-        __put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr)))
+        __put_unaligned((__u64)(x), (ptr), sizeof(*(ptr)))
 
 /*
  * This function doesn't actually exist.  The idea is that when
@@ -36,19 +36,19 @@ struct __una_u16 { __u16 x __attribute__((packed)); };
  * Elemental unaligned loads 
  */
 
-static inline unsigned long __uldq(const __u64 *addr)
+static inline __u64 __uldq(const __u64 *addr)
 {
         const struct __una_u64 *ptr = (const struct __una_u64 *) addr;
         return ptr->x;
 }
 
-static inline unsigned long __uldl(const __u32 *addr)
+static inline __u32 __uldl(const __u32 *addr)
 {
         const struct __una_u32 *ptr = (const struct __una_u32 *) addr;
         return ptr->x;
 }
 
-static inline unsigned long __uldw(const __u16 *addr)
+static inline __u16 __uldw(const __u16 *addr)
 {
         const struct __una_u16 *ptr = (const struct __una_u16 *) addr;
         return ptr->x;
@@ -78,7 +78,7 @@ static inline void __ustw(__u16 val, __u16 *addr)
 
 #define __get_unaligned(ptr, size) ({           \
         const void *__gu_p = ptr;               \
-        unsigned long val;                      \
+        __typeof__(*(ptr)) val;                 \
         switch (size) {                         \
         case 1:                                 \
                 val = *(const __u8 *)__gu_p;    \
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 99cef06a364a..6f857be2b644 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -6,6 +6,9 @@
 #define VMLINUX_SYMBOL(_sym_) _sym_
 #endif
 
+/* Align . to a 8 byte boundary equals to maximum function alignment. */
+#define ALIGN_FUNCTION()  . = ALIGN(8)
+
 #define RODATA                                                          \
         .rodata           : AT(ADDR(.rodata) - LOAD_OFFSET) {           \
                 *(.rodata) *(.rodata.*)                                 \
@@ -73,18 +76,30 @@
         }
 
 #define SECURITY_INIT                                                   \
-        .security_initcall.init : {                                     \
+        .security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) { \
                 VMLINUX_SYMBOL(__security_initcall_start) = .;          \
                 *(.security_initcall.init)                              \
                 VMLINUX_SYMBOL(__security_initcall_end) = .;            \
         }
 
+/* sched.text is aling to function alignment to secure we have same
+ * address even at second ld pass when generating System.map */
 #define SCHED_TEXT                                                      \
+                ALIGN_FUNCTION();                                       \
                 VMLINUX_SYMBOL(__sched_text_start) = .;                 \
                 *(.sched.text)                                          \
                 VMLINUX_SYMBOL(__sched_text_end) = .;
 
+/* spinlock.text is aling to function alignment to secure we have same
+ * address even at second ld pass when generating System.map */
 #define LOCK_TEXT                                                       \
+                ALIGN_FUNCTION();                                       \
                 VMLINUX_SYMBOL(__lock_text_start) = .;                  \
                 *(.spinlock.text)                                       \
                 VMLINUX_SYMBOL(__lock_text_end) = .;
+
+#define KPROBES_TEXT                                                    \
+                ALIGN_FUNCTION();                                       \
+                VMLINUX_SYMBOL(__kprobes_text_start) = .;               \
+                *(.kprobes.text)                                        \
+                VMLINUX_SYMBOL(__kprobes_text_end) = .;
diff --git a/include/asm-h8300/auxvec.h b/include/asm-h8300/auxvec.h
new file mode 100644
index 000000000000..1d36fe38b088
--- /dev/null
+++ b/include/asm-h8300/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMH8300_AUXVEC_H
+#define __ASMH8300_AUXVEC_H
+
+#endif
diff --git a/include/asm-h8300/emergency-restart.h b/include/asm-h8300/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-h8300/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-h8300/fcntl.h b/include/asm-h8300/fcntl.h
index 355350a57bf9..1952cb2e3b06 100644
--- a/include/asm-h8300/fcntl.h
+++ b/include/asm-h8300/fcntl.h
@@ -1,87 +1,11 @@
 #ifndef _H8300_FCNTL_H
 #define _H8300_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE         0003
-#define O_RDONLY            00
-#define O_WRONLY            01
-#define O_RDWR              02
-#define O_CREAT           0100  /* not fcntl */
-#define O_EXCL            0200  /* not fcntl */
-#define O_NOCTTY          0400  /* not fcntl */
-#define O_TRUNC          01000  /* not fcntl */
-#define O_APPEND         02000
-#define O_NONBLOCK       04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC          010000
-#define FASYNC          020000  /* fcntl, for BSD compatibility */
 #define O_DIRECTORY     040000  /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
 #define O_LARGEFILE     0400000
-#define O_NOATIME       01000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
+#include <asm-generic/fcntl.h>
 
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif /* _H8300_FCNTL_H */
diff --git a/include/asm-h8300/futex.h b/include/asm-h8300/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-h8300/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-h8300/hdreg.h b/include/asm-h8300/hdreg.h
deleted file mode 100644
index 36d0c06687d8..000000000000
--- a/include/asm-h8300/hdreg.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- *  linux/include/asm-h8300/hdreg.h
- *
- *  Copyright (C) 1994-1996  Linus Torvalds & authors
- */
-
-#warning this file is obsolete, please do not use it
-
-#ifndef _H8300_HDREG_H
-#define _H8300_HDREG_H
-
-typedef unsigned int   q40ide_ioreg_t;
-typedef unsigned char * ide_ioreg_t;
-
-#endif /* _H8300_HDREG_H */
diff --git a/include/asm-h8300/page.h b/include/asm-h8300/page.h
index e3b7960d445b..e8c02b8c2d99 100644
--- a/include/asm-h8300/page.h
+++ b/include/asm-h8300/page.h
@@ -54,20 +54,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 extern unsigned long memory_start;
 extern unsigned long memory_end;
 
@@ -101,4 +87,6 @@ extern unsigned long memory_end;
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _H8300_PAGE_H */
diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h
index d032729b19df..5edad5b70fd5 100644
--- a/include/asm-h8300/pci.h
+++ b/include/asm-h8300/pci.h
@@ -15,7 +15,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-extern inline void pcibios_penalize_isa_irq(int irq)
+extern inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
diff --git a/include/asm-h8300/socket.h b/include/asm-h8300/socket.h
index af33b8525dcf..d98cf85bafc1 100644
--- a/include/asm-h8300/socket.h
+++ b/include/asm-h8300/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-h8300/thread_info.h b/include/asm-h8300/thread_info.h
index b07c9344776f..bfcc755c3bb1 100644
--- a/include/asm-h8300/thread_info.h
+++ b/include/asm-h8300/thread_info.h
@@ -23,7 +23,7 @@ struct thread_info {
         struct exec_domain *exec_domain;        /* execution domain */
         unsigned long      flags;               /* low level flags */
         int                cpu;                 /* cpu we're on */
-        int                preempt_count;       /* 0 => preemptable, <0 => BUG*/
+        int                preempt_count;       /* 0 => preemptable, <0 => BUG */
         struct restart_block restart_block;
 };
 
diff --git a/include/asm-h8300/types.h b/include/asm-h8300/types.h
index 21f4fc07ac0e..bf91e0d4dde7 100644
--- a/include/asm-h8300/types.h
+++ b/include/asm-h8300/types.h
@@ -58,8 +58,6 @@ typedef u32 dma_addr_t;
 #define HAVE_SECTOR_T
 typedef u64 sector_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-h8300/uaccess.h b/include/asm-h8300/uaccess.h
index 1480f307a474..ebe58c6c8387 100644
--- a/include/asm-h8300/uaccess.h
+++ b/include/asm-h8300/uaccess.h
@@ -24,12 +24,6 @@ static inline int __access_ok(unsigned long addr, unsigned long size)
         return(RANGE_CHECK_OK(addr, size, 0L, (unsigned long)&_ramend));
 }
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void *addr, unsigned long size)
-{
-        return access_ok(type,addr,size)?0:-EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-i386/acpi.h b/include/asm-i386/acpi.h
index c976c1dadece..df4ed323aa4d 100644
--- a/include/asm-i386/acpi.h
+++ b/include/asm-i386/acpi.h
@@ -28,6 +28,8 @@
 
 #ifdef __KERNEL__
 
+#include <acpi/pdc_intel.h>
+
 #include <asm/system.h>         /* defines cmpxchg */
 
 #define COMPILER_DEPENDENT_INT64   long long
@@ -101,13 +103,7 @@ __acpi_release_global_lock (unsigned int *lock)
         :"=r"(n_hi), "=r"(n_lo)     \
         :"0"(n_hi), "1"(n_lo))
 
-/*
- * Refer Intel ACPI _PDC support document for bit definitions
- */
-#define ACPI_PDC_EST_CAPABILITY_SMP     0xa
-#define ACPI_PDC_EST_CAPABILITY_MSR     0x1
-
-#ifdef CONFIG_ACPI_BOOT 
+#ifdef CONFIG_ACPI 
 extern int acpi_lapic;
 extern int acpi_ioapic;
 extern int acpi_noirq;
@@ -150,13 +146,6 @@ static inline void check_acpi_pci(void) { }
 
 #endif
 
-#else   /* CONFIG_ACPI_BOOT */
-#  define acpi_lapic 0
-#  define acpi_ioapic 0
-
-#endif
-
-#ifdef CONFIG_ACPI_PCI
 static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
 static inline void acpi_disable_pci(void) 
 {
@@ -164,11 +153,16 @@ static inline void acpi_disable_pci(void)
         acpi_noirq_set();
 }
 extern int acpi_irq_balance_set(char *str);
-#else
+
+#else   /* !CONFIG_ACPI */
+
+#define acpi_lapic 0
+#define acpi_ioapic 0
 static inline void acpi_noirq_set(void) { }
 static inline void acpi_disable_pci(void) { }
-static inline int acpi_irq_balance_set(char *str) { return 0; }
-#endif
+
+#endif  /* !CONFIG_ACPI */
+
 
 #ifdef CONFIG_ACPI_SLEEP
 
@@ -185,6 +179,8 @@ extern void acpi_reserve_bootmem(void);
 
 extern u8 x86_acpiid_to_apicid[];
 
+#define ARCH_HAS_POWER_PDC_INIT 1
+
 #endif /*__KERNEL__*/
 
 #endif /*_ASM_ACPI_H*/
diff --git a/include/asm-i386/agp.h b/include/asm-i386/agp.h
index b82f5f3ab887..9075083bab76 100644
--- a/include/asm-i386/agp.h
+++ b/include/asm-i386/agp.h
@@ -19,7 +19,7 @@ int unmap_page_from_agp(struct page *page);
 /* Could use CLFLUSH here if the cpu supports it. But then it would
    need to be called for each cacheline of the whole page so it may not be 
    worth it. Would need a page for it. */
-#define flush_agp_cache() asm volatile("wbinvd":::"memory")
+#define flush_agp_cache() wbinvd()
 
 /* Convert a physical address to an address suitable for the GART. */
 #define phys_to_gart(x) (x)
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h
index a5810cf7b578..6a1b1882285c 100644
--- a/include/asm-i386/apic.h
+++ b/include/asm-i386/apic.h
@@ -5,6 +5,7 @@
 #include <linux/pm.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
+#include <asm/processor.h>
 #include <asm/system.h>
 
 #define Dprintk(x...)
@@ -16,8 +17,20 @@
 #define APIC_VERBOSE 1
 #define APIC_DEBUG   2
 
+extern int enable_local_apic;
 extern int apic_verbosity;
 
+static inline void lapic_disable(void)
+{
+        enable_local_apic = -1;
+        clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
+}
+
+static inline void lapic_enable(void)
+{
+        enable_local_apic = 1;
+}
+
 /*
  * Define the default level of output to be very little
  * This can be turned up by using apic=verbose for more
@@ -87,7 +100,7 @@ extern void (*wait_timer_tick)(void);
 extern int get_maxlvt(void);
 extern void clear_local_APIC(void);
 extern void connect_bsp_APIC (void);
-extern void disconnect_bsp_APIC (void);
+extern void disconnect_bsp_APIC (int virt_wire_setup);
 extern void disable_local_APIC (void);
 extern void lapic_shutdown (void);
 extern int verify_local_APIC (void);
diff --git a/include/asm-i386/apicdef.h b/include/asm-i386/apicdef.h
index c689554ad5b9..03185cef8e0a 100644
--- a/include/asm-i386/apicdef.h
+++ b/include/asm-i386/apicdef.h
@@ -16,6 +16,7 @@
 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
+#define                 APIC_XAPIC(x)           ((x) >= 0x14)
 #define         APIC_TASKPRI    0x80
 #define                 APIC_TPRI_MASK          0xFF
 #define         APIC_ARBPRI     0x90
@@ -86,11 +87,12 @@
 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
 #define                 APIC_INPUT_POLARITY             (1<<13)
 #define                 APIC_SEND_PENDING               (1<<12)
+#define                 APIC_MODE_MASK                  0x700
 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
 #define                         APIC_MODE_FIXED         0x0
 #define                         APIC_MODE_NMI           0x4
-#define                         APIC_MODE_EXINT         0x7
+#define                         APIC_MODE_EXTINT        0x7
 #define         APIC_LVT1       0x360
 #define         APIC_LVTERR     0x370
 #define         APIC_TMICT      0x380
@@ -108,11 +110,7 @@
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 
-#ifdef CONFIG_NUMA
- #define MAX_IO_APICS 32
-#else
- #define MAX_IO_APICS 8
-#endif
+#define MAX_IO_APICS 64
 
 /*
  * the local APIC register structure, memory mapped. Not terribly well
diff --git a/include/asm-i386/auxvec.h b/include/asm-i386/auxvec.h
new file mode 100644
index 000000000000..395e13016bfb
--- /dev/null
+++ b/include/asm-i386/auxvec.h
@@ -0,0 +1,11 @@
+#ifndef __ASMi386_AUXVEC_H
+#define __ASMi386_AUXVEC_H
+
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them, start the x86-specific ones at 32.
+ */
+#define AT_SYSINFO              32
+#define AT_SYSINFO_EHDR         33
+
+#endif
diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h
index 9db0b712d57a..ddf1739dc7fd 100644
--- a/include/asm-i386/bitops.h
+++ b/include/asm-i386/bitops.h
@@ -311,6 +311,20 @@ static inline int find_first_zero_bit(const unsigned long *addr, unsigned size)
 int find_next_zero_bit(const unsigned long *addr, int size, int offset);
 
 /**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        __asm__("bsfl %1,%0"
+                :"=r" (word)
+                :"rm" (word));
+        return word;
+}
+
+/**
  * find_first_bit - find the first set bit in a memory region
  * @addr: The address to start the search at
  * @size: The maximum size to search
@@ -320,22 +334,15 @@ int find_next_zero_bit(const unsigned long *addr, int size, int offset);
  */
 static inline int find_first_bit(const unsigned long *addr, unsigned size)
 {
-        int d0, d1;
-        int res;
-
-        /* This looks at memory. Mark it volatile to tell gcc not to move it around */
-        __asm__ __volatile__(
-                "xorl %%eax,%%eax\n\t"
-                "repe; scasl\n\t"
-                "jz 1f\n\t"
-                "leal -4(%%edi),%%edi\n\t"
-                "bsfl (%%edi),%%eax\n"
-                "1:\tsubl %%ebx,%%edi\n\t"
-                "shll $3,%%edi\n\t"
-                "addl %%edi,%%eax"
-                :"=a" (res), "=&c" (d0), "=&D" (d1)
-                :"1" ((size + 31) >> 5), "2" (addr), "b" (addr) : "memory");
-        return res;
+        int x = 0;
+
+        while (x < size) {
+                unsigned long val = *addr++;
+                if (val)
+                        return __ffs(val) + x;
+                x += (sizeof(*addr)<<3);
+        }
+        return x;
 }
 
 /**
@@ -360,20 +367,6 @@ static inline unsigned long ffz(unsigned long word)
         return word;
 }
 
-/**
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-        __asm__("bsfl %1,%0"
-                :"=r" (word)
-                :"rm" (word));
-        return word;
-}
-
 /*
  * fls: find last bit set.
  */
diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h
index 6789fc275da3..ea54540638d2 100644
--- a/include/asm-i386/bugs.h
+++ b/include/asm-i386/bugs.h
@@ -118,7 +118,10 @@ static void __init check_hlt(void)
                 printk("disabled\n");
                 return;
         }
-        __asm__ __volatile__("hlt ; hlt ; hlt ; hlt");
+        halt();
+        halt();
+        halt();
+        halt();
         printk("OK.\n");
 }
 
diff --git a/include/asm-i386/checksum.h b/include/asm-i386/checksum.h
index 641342002bcd..67d3630c4e89 100644
--- a/include/asm-i386/checksum.h
+++ b/include/asm-i386/checksum.h
@@ -3,6 +3,8 @@
 
 #include <linux/in6.h>
 
+#include <asm/uaccess.h>
+
 /*
  * computes the checksum of a memory block at buff, length len,
  * and adds in "sum" (32-bit)
@@ -81,7 +83,7 @@ static inline unsigned short ip_fast_csum(unsigned char * iph,
             "adcl $0, %0        ;\n"
             "notl %0            ;\n"
 "2:                             ;\n"
-        /* Since the input registers which are loaded with iph and ipl
+        /* Since the input registers which are loaded with iph and ihl
            are modified, we must also specify them as outputs, or gcc
            will assume they contain their original values. */
         : "=r" (sum), "=r" (iph), "=r" (ihl)
diff --git a/include/asm-i386/cpu.h b/include/asm-i386/cpu.h
index 002740b21951..e7252c216ca8 100644
--- a/include/asm-i386/cpu.h
+++ b/include/asm-i386/cpu.h
@@ -5,6 +5,7 @@
 #include <linux/cpu.h>
 #include <linux/topology.h>
 #include <linux/nodemask.h>
+#include <linux/percpu.h>
 
 #include <asm/node.h>
 
@@ -16,4 +17,5 @@ extern int arch_register_cpu(int num);
 extern void arch_unregister_cpu(int);
 #endif
 
+DECLARE_PER_CPU(int, cpu_state);
 #endif /* _ASM_I386_CPU_H_ */
diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h
index 11e67811a990..6df1a53c190e 100644
--- a/include/asm-i386/desc.h
+++ b/include/asm-i386/desc.h
@@ -27,8 +27,18 @@ struct Xgt_desc_struct {
 
 extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS];
 
-#define load_TR_desc() __asm__ __volatile__("ltr %%ax"::"a" (GDT_ENTRY_TSS*8))
-#define load_LDT_desc() __asm__ __volatile__("lldt %%ax"::"a" (GDT_ENTRY_LDT*8))
+#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8))
+#define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8))
+
+#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr))
+#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr))
+#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
+#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
+
+#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
+#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
+#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
+#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
 
 /*
  * This is the ldt that every process will get unless we need
@@ -39,14 +49,14 @@ extern void set_intr_gate(unsigned int irq, void * addr);
 
 #define _set_tssldt_desc(n,addr,limit,type) \
 __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
-        "movw %%ax,2(%2)\n\t" \
-        "rorl $16,%%eax\n\t" \
-        "movb %%al,4(%2)\n\t" \
+        "movw %w1,2(%2)\n\t" \
+        "rorl $16,%1\n\t" \
+        "movb %b1,4(%2)\n\t" \
         "movb %4,5(%2)\n\t" \
         "movb $0,6(%2)\n\t" \
-        "movb %%ah,7(%2)\n\t" \
-        "rorl $16,%%eax" \
-        : "=m"(*(n)) : "a" (addr), "r"(n), "ir"(limit), "i"(type))
+        "movb %h1,7(%2)\n\t" \
+        "rorl $16,%1" \
+        : "=m"(*(n)) : "q" (addr), "r"(n), "ir"(limit), "i"(type))
 
 static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
 {
@@ -86,6 +96,13 @@ static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
         (info)->seg_not_present == 1    && \
         (info)->useable         == 0    )
 
+static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 entry_b)
+{
+        __u32 *lp = (__u32 *)((char *)ldt + entry*8);
+        *lp = entry_a;
+        *(lp+1) = entry_b;
+}
+
 #if TLS_SIZE != 24
 # error update this code.
 #endif
diff --git a/include/asm-i386/elf.h b/include/asm-i386/elf.h
index 130bdc8c68cf..fa11117d3cfa 100644
--- a/include/asm-i386/elf.h
+++ b/include/asm-i386/elf.h
@@ -9,6 +9,7 @@
 #include <asm/user.h>
 #include <asm/processor.h>
 #include <asm/system.h>         /* for savesegment */
+#include <asm/auxvec.h>
 
 #include <linux/utsname.h>
 
@@ -109,13 +110,6 @@ typedef struct user_fxsr_struct elf_fpxregset_t;
 
 #define ELF_PLATFORM  (system_utsname.machine)
 
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#define AT_SYSINFO              32
-#define AT_SYSINFO_EHDR         33
-
 #ifdef __KERNEL__
 #define SET_PERSONALITY(ex, ibcs2) do { } while (0)
 
diff --git a/include/asm-i386/emergency-restart.h b/include/asm-i386/emergency-restart.h
new file mode 100644
index 000000000000..680c39563345
--- /dev/null
+++ b/include/asm-i386/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+extern void machine_emergency_restart(void);
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-i386/fcntl.h b/include/asm-i386/fcntl.h
index 511cde94a3ed..46ab12db5739 100644
--- a/include/asm-i386/fcntl.h
+++ b/include/asm-i386/fcntl.h
@@ -1,88 +1 @@
-#ifndef _I386_FCNTL_H
-#define _I386_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-
-#endif
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-i386/fixmap.h b/include/asm-i386/fixmap.h
index c94cac958389..cfb1c61d3b9c 100644
--- a/include/asm-i386/fixmap.h
+++ b/include/asm-i386/fixmap.h
@@ -76,7 +76,7 @@ enum fixed_addresses {
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
 #endif
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
         FIX_ACPI_BEGIN,
         FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
 #endif
diff --git a/include/asm-i386/futex.h b/include/asm-i386/futex.h
new file mode 100644
index 000000000000..44b9db806474
--- /dev/null
+++ b/include/asm-i386/futex.h
@@ -0,0 +1,108 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+
+#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile (                                          \
+"1:     " insn "\n"                                             \
+"2:     .section .fixup,\"ax\"\n\
+3:      mov     %3, %1\n\
+        jmp     2b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align  8\n\
+        .long   1b,3b\n\
+        .previous"                                              \
+        : "=r" (oldval), "=r" (ret), "=m" (*uaddr)              \
+        : "i" (-EFAULT), "m" (*uaddr), "0" (oparg), "1" (0))
+
+#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile (                                          \
+"1:     movl    %2, %0\n\
+        movl    %0, %3\n"                                       \
+        insn "\n"                                               \
+"2:     " LOCK_PREFIX "cmpxchgl %3, %2\n\
+        jnz     1b\n\
+3:      .section .fixup,\"ax\"\n\
+4:      mov     %5, %1\n\
+        jmp     3b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align  8\n\
+        .long   1b,4b,2b,4b\n\
+        .previous"                                              \
+        : "=&a" (oldval), "=&r" (ret), "=m" (*uaddr),           \
+          "=&r" (tem)                                           \
+        : "r" (oparg), "i" (-EFAULT), "m" (*uaddr), "1" (0))
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        if (op == FUTEX_OP_SET)
+                __futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
+        else {
+#ifndef CONFIG_X86_BSWAP
+                if (boot_cpu_data.x86 == 3)
+                        ret = -ENOSYS;
+                else
+#endif
+                switch (op) {
+                case FUTEX_OP_ADD:
+                        __futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret,
+                                           oldval, uaddr, oparg);
+                        break;
+                case FUTEX_OP_OR:
+                        __futex_atomic_op2("orl %4, %3", ret, oldval, uaddr,
+                                           oparg);
+                        break;
+                case FUTEX_OP_ANDN:
+                        __futex_atomic_op2("andl %4, %3", ret, oldval, uaddr,
+                                           ~oparg);
+                        break;
+                case FUTEX_OP_XOR:
+                        __futex_atomic_op2("xorl %4, %3", ret, oldval, uaddr,
+                                           oparg);
+                        break;
+                default:
+                        ret = -ENOSYS;
+                }
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-i386/genapic.h b/include/asm-i386/genapic.h
index fc813b2e8274..b3783a32abee 100644
--- a/include/asm-i386/genapic.h
+++ b/include/asm-i386/genapic.h
@@ -78,7 +78,6 @@ struct genapic {
         .int_delivery_mode = INT_DELIVERY_MODE, \
         .int_dest_mode = INT_DEST_MODE, \
         .no_balance_irq = NO_BALANCE_IRQ, \
-        .no_ioapic_check = NO_IOAPIC_CHECK, \
         .ESR_DISABLE = esr_disable, \
         .apic_destination_logical = APIC_DEST_LOGICAL, \
         APICFUNC(apic_id_registered), \
diff --git a/include/asm-i386/hdreg.h b/include/asm-i386/hdreg.h
deleted file mode 100644
index 5989bbc97cbf..000000000000
--- a/include/asm-i386/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#warning this file is obsolete, please do not use it
diff --git a/include/asm-i386/highmem.h b/include/asm-i386/highmem.h
index 1df42bf347df..0fd331306b60 100644
--- a/include/asm-i386/highmem.h
+++ b/include/asm-i386/highmem.h
@@ -70,6 +70,7 @@ void *kmap(struct page *page);
 void kunmap(struct page *page);
 void *kmap_atomic(struct page *page, enum km_type type);
 void kunmap_atomic(void *kvaddr, enum km_type type);
+void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
 struct page *kmap_atomic_to_page(void *ptr);
 
 #define flush_cache_kmaps()     do { } while (0)
diff --git a/include/asm-i386/i387.h b/include/asm-i386/i387.h
index f6feb98a9397..6747006743f9 100644
--- a/include/asm-i386/i387.h
+++ b/include/asm-i386/i387.h
@@ -19,10 +19,21 @@
 
 extern void mxcsr_feature_mask_init(void);
 extern void init_fpu(struct task_struct *);
+
 /*
  * FPU lazy state save handling...
  */
-extern void restore_fpu( struct task_struct *tsk );
+
+/*
+ * The "nop" is needed to make the instructions the same
+ * length.
+ */
+#define restore_fpu(tsk)                        \
+        alternative_input(                      \
+                "nop ; frstor %1",              \
+                "fxrstor %1",                   \
+                X86_FEATURE_FXSR,               \
+                "m" ((tsk)->thread.i387.fxsave))
 
 extern void kernel_fpu_begin(void);
 #define kernel_fpu_end() do { stts(); preempt_enable(); } while(0)
@@ -32,13 +43,12 @@ extern void kernel_fpu_begin(void);
  */
 static inline void __save_init_fpu( struct task_struct *tsk )
 {
-        if ( cpu_has_fxsr ) {
-                asm volatile( "fxsave %0 ; fnclex"
-                              : "=m" (tsk->thread.i387.fxsave) );
-        } else {
-                asm volatile( "fnsave %0 ; fwait"
-                              : "=m" (tsk->thread.i387.fsave) );
-        }
+        alternative_input(
+                "fnsave %1 ; fwait ;" GENERIC_NOP2,
+                "fxsave %1 ; fnclex",
+                X86_FEATURE_FXSR,
+                "m" (tsk->thread.i387.fxsave)
+                :"memory");
         tsk->thread_info->status &= ~TS_USEDFPU;
 }
 
diff --git a/include/asm-i386/i8253.h b/include/asm-i386/i8253.h
new file mode 100644
index 000000000000..015d8df07690
--- /dev/null
+++ b/include/asm-i386/i8253.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_I8253_H__
+#define __ASM_I8253_H__
+
+extern spinlock_t i8253_lock;
+
+#endif  /* __ASM_I8253_H__ */
diff --git a/include/asm-i386/ide.h b/include/asm-i386/ide.h
index 859ebf4da632..79dfab87135d 100644
--- a/include/asm-i386/ide.h
+++ b/include/asm-i386/ide.h
@@ -41,13 +41,17 @@ static __inline__ int ide_default_irq(unsigned long base)
 
 static __inline__ unsigned long ide_default_io_base(int index)
 {
+        if (pci_find_device(PCI_ANY_ID, PCI_ANY_ID, NULL) == NULL) {
+                switch(index) {
+                        case 2: return 0x1e8;
+                        case 3: return 0x168;
+                        case 4: return 0x1e0;
+                        case 5: return 0x160;
+                }
+        }
         switch (index) {
                 case 0: return 0x1f0;
                 case 1: return 0x170;
-                case 2: return 0x1e8;
-                case 3: return 0x168;
-                case 4: return 0x1e0;
-                case 5: return 0x160;
                 default:
                         return 0;
         }
diff --git a/include/asm-i386/io_apic.h b/include/asm-i386/io_apic.h
index 002c203ccd6a..51c4e5fe6062 100644
--- a/include/asm-i386/io_apic.h
+++ b/include/asm-i386/io_apic.h
@@ -195,12 +195,12 @@ extern int skip_ioapic_setup;
  */
 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 extern int io_apic_get_unique_id (int ioapic, int apic_id);
 extern int io_apic_get_version (int ioapic);
 extern int io_apic_get_redir_entries (int ioapic);
 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
-#endif /*CONFIG_ACPI_BOOT*/
+#endif /* CONFIG_ACPI */
 
 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
 
diff --git a/include/asm-i386/irq.h b/include/asm-i386/irq.h
index 05b9e61b0a72..270f1986b19f 100644
--- a/include/asm-i386/irq.h
+++ b/include/asm-i386/irq.h
@@ -29,13 +29,19 @@ extern void release_vm86_irqs(struct task_struct *);
 
 #ifdef CONFIG_4KSTACKS
   extern void irq_ctx_init(int cpu);
+  extern void irq_ctx_exit(int cpu);
 # define __ARCH_HAS_DO_SOFTIRQ
 #else
 # define irq_ctx_init(cpu) do { } while (0)
+# define irq_ctx_exit(cpu) do { } while (0)
 #endif
 
 #ifdef CONFIG_IRQBALANCE
 extern int irqbalance_disable(char *str);
 #endif
 
+#ifdef CONFIG_HOTPLUG_CPU
+extern void fixup_irqs(cpumask_t map);
+#endif
+
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-i386/kdebug.h b/include/asm-i386/kdebug.h
index de6498b0d493..316138e89910 100644
--- a/include/asm-i386/kdebug.h
+++ b/include/asm-i386/kdebug.h
@@ -18,7 +18,7 @@ struct die_args {
 };
 
 /* Note - you should never unregister because that can race with NMIs.
-   If you really want to do it first unregister - then synchronize_kernel - then free.
+   If you really want to do it first unregister - then synchronize_sched - then free.
   */
 int register_die_notifier(struct notifier_block *nb);
 extern struct notifier_block *i386die_chain;
@@ -41,9 +41,16 @@ enum die_val {
         DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
+static inline int notify_die(enum die_val val, const char *str,
+                        struct pt_regs *regs, long err, int trap, int sig)
 {
-        struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
+        struct die_args args = {
+                .regs = regs,
+                .str = str,
+                .err = err,
+                .trapnr = trap,
+                .signr = sig
+        };
         return notifier_call_chain(&i386die_chain, val, &args);
 }
 
diff --git a/include/asm-i386/kexec.h b/include/asm-i386/kexec.h
new file mode 100644
index 000000000000..6ed2a03e37b3
--- /dev/null
+++ b/include/asm-i386/kexec.h
@@ -0,0 +1,33 @@
+#ifndef _I386_KEXEC_H
+#define _I386_KEXEC_H
+
+#include <asm/fixmap.h>
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
+ * calculation for the amount of memory directly mappable into the
+ * kernel memory space.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_386
+
+#define MAX_NOTE_BYTES 1024
+typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
+
+extern note_buf_t crash_notes[];
+
+#endif /* _I386_KEXEC_H */
diff --git a/include/asm-i386/kprobes.h b/include/asm-i386/kprobes.h
index 4092f68d123a..8b6d3a90cd78 100644
--- a/include/asm-i386/kprobes.h
+++ b/include/asm-i386/kprobes.h
@@ -39,6 +39,9 @@ typedef u8 kprobe_opcode_t;
         : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
 
 #define JPROBE_ENTRY(pentry)    (kprobe_opcode_t *)pentry
+#define ARCH_SUPPORTS_KRETPROBES
+
+void kretprobe_trampoline(void);
 
 /* Architecture specific copy of original instruction*/
 struct arch_specific_insn {
diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h
index 2339868270ef..ba936d4daedb 100644
--- a/include/asm-i386/mach-bigsmp/mach_apic.h
+++ b/include/asm-i386/mach-bigsmp/mach_apic.h
@@ -14,8 +14,6 @@
 #define NO_BALANCE_IRQ (1)
 #define esr_disable (1)
 
-#define NO_IOAPIC_CHECK (0)
-
 static inline int apic_id_registered(void)
 {
         return (1);
diff --git a/include/asm-i386/mach-default/do_timer.h b/include/asm-i386/mach-default/do_timer.h
index 03dd13a48a8c..56211414fc95 100644
--- a/include/asm-i386/mach-default/do_timer.h
+++ b/include/asm-i386/mach-default/do_timer.h
@@ -1,6 +1,7 @@
 /* defines for inline arch setup functions */
 
 #include <asm/apic.h>
+#include <asm/i8259.h>
 
 /**
  * do_timer_interrupt_hook - hook into timer tick
diff --git a/include/asm-i386/mach-default/mach_apic.h b/include/asm-i386/mach-default/mach_apic.h
index 627f1cd084ba..3ef6292db780 100644
--- a/include/asm-i386/mach-default/mach_apic.h
+++ b/include/asm-i386/mach-default/mach_apic.h
@@ -19,8 +19,6 @@ static inline cpumask_t target_cpus(void)
 #define NO_BALANCE_IRQ (0)
 #define esr_disable (0)
 
-#define NO_IOAPIC_CHECK (0)
-
 #define INT_DELIVERY_MODE dest_LowestPrio
 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
 
diff --git a/include/asm-i386/mach-default/mach_ipi.h b/include/asm-i386/mach-default/mach_ipi.h
index 6f2b17a20089..cc756a67cd63 100644
--- a/include/asm-i386/mach-default/mach_ipi.h
+++ b/include/asm-i386/mach-default/mach_ipi.h
@@ -4,11 +4,34 @@
 void send_IPI_mask_bitmask(cpumask_t mask, int vector);
 void __send_IPI_shortcut(unsigned int shortcut, int vector);
 
+extern int no_broadcast;
+
 static inline void send_IPI_mask(cpumask_t mask, int vector)
 {
         send_IPI_mask_bitmask(mask, vector);
 }
 
+static inline void __local_send_IPI_allbutself(int vector)
+{
+        if (no_broadcast) {
+                cpumask_t mask = cpu_online_map;
+                int this_cpu = get_cpu();
+
+                cpu_clear(this_cpu, mask);
+                send_IPI_mask(mask, vector);
+                put_cpu();
+        } else
+                __send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
+}
+
+static inline void __local_send_IPI_all(int vector)
+{
+        if (no_broadcast)
+                send_IPI_mask(cpu_online_map, vector);
+        else
+                __send_IPI_shortcut(APIC_DEST_ALLINC, vector);
+}
+
 static inline void send_IPI_allbutself(int vector)
 {
         /*
@@ -18,13 +41,13 @@ static inline void send_IPI_allbutself(int vector)
         if (!(num_online_cpus() > 1))
                 return;
 
-        __send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
+        __local_send_IPI_allbutself(vector);
         return;
 }
 
 static inline void send_IPI_all(int vector)
 {
-        __send_IPI_shortcut(APIC_DEST_ALLINC, vector);
+        __local_send_IPI_all(vector);
 }
 
 #endif /* __ASM_MACH_IPI_H */
diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-i386/mach-es7000/mach_apic.h
index ceab2c464b13..b5f3f0d0b2bc 100644
--- a/include/asm-i386/mach-es7000/mach_apic.h
+++ b/include/asm-i386/mach-es7000/mach_apic.h
@@ -38,8 +38,6 @@ static inline cpumask_t target_cpus(void)
 #define WAKE_SECONDARY_VIA_INIT
 #endif
 
-#define NO_IOAPIC_CHECK (1)
-
 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
 { 
         return 0;
diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h
index 85809e0898d7..28a84f6185a7 100644
--- a/include/asm-i386/mach-es7000/mach_mpparse.h
+++ b/include/asm-i386/mach-es7000/mach_mpparse.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_MACH_MPPARSE_H
 #define __ASM_MACH_MPPARSE_H
 
+#include <linux/acpi.h>
+
 static inline void mpc_oem_bus_info(struct mpc_config_bus *m, char *name, 
                                 struct mpc_config_translation *translation)
 {
@@ -12,8 +14,9 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
 {
 }
 
-extern int parse_unisys_oem (char *oemptr, int oem_entries);
-extern int find_unisys_acpi_oem_table(unsigned long *oem_addr, int *length);
+extern int parse_unisys_oem (char *oemptr);
+extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
+extern void setup_unisys();
 
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                 char *productid)
@@ -22,18 +25,33 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                 struct mp_config_oemtable *oem_table = 
                         (struct mp_config_oemtable *)mpc->mpc_oemptr;
                 if (!strncmp(oem, "UNISYS", 6))
-                        return parse_unisys_oem((char *)oem_table, oem_table->oem_length);
+                        return parse_unisys_oem((char *)oem_table);
         }
         return 0;
 }
 
+static inline int es7000_check_dsdt()
+{
+        struct acpi_table_header *header = NULL;
+        if(!acpi_get_table_header_early(ACPI_DSDT, &header))
+                acpi_table_print(header, 0);
+        if (!strncmp(header->oem_id, "UNISYS", 6))
+                return 1;
+        return 0;
+}
+
 /* Hook from generic ACPI tables.c */
 static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         unsigned long oem_addr; 
-        int oem_entries;
-        if (!find_unisys_acpi_oem_table(&oem_addr, &oem_entries))
-                return parse_unisys_oem((char *)oem_addr, oem_entries);
+        if (!find_unisys_acpi_oem_table(&oem_addr)) {
+                if (es7000_check_dsdt())
+                        return parse_unisys_oem((char *)oem_addr);
+                else {
+                        setup_unisys();
+                        return 1;
+                }
+        }
         return 0;
 }
 
diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-i386/mach-generic/mach_apic.h
index ab36d02ebede..d9dc039da94a 100644
--- a/include/asm-i386/mach-generic/mach_apic.h
+++ b/include/asm-i386/mach-generic/mach_apic.h
@@ -5,7 +5,6 @@
 
 #define esr_disable (genapic->ESR_DISABLE)
 #define NO_BALANCE_IRQ (genapic->no_balance_irq)
-#define NO_IOAPIC_CHECK (genapic->no_ioapic_check)
 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
 #define INT_DEST_MODE (genapic->int_dest_mode)
 #undef APIC_DEST_LOGICAL
@@ -29,4 +28,6 @@
 #define enable_apic_mode (genapic->enable_apic_mode)
 #define phys_pkg_id (genapic->phys_pkg_id)
 
+extern void generic_bigsmp_probe(void);
+
 #endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-numaq/mach_apic.h b/include/asm-i386/mach-numaq/mach_apic.h
index e1a04494764a..9d158095da82 100644
--- a/include/asm-i386/mach-numaq/mach_apic.h
+++ b/include/asm-i386/mach-numaq/mach_apic.h
@@ -17,8 +17,6 @@ static inline cpumask_t target_cpus(void)
 #define NO_BALANCE_IRQ (1)
 #define esr_disable (1)
 
-#define NO_IOAPIC_CHECK (0)
-
 #define INT_DELIVERY_MODE dest_LowestPrio
 #define INT_DEST_MODE 0     /* physical delivery on LOCAL quad */
  
diff --git a/include/asm-i386/mach-summit/mach_apic.h b/include/asm-i386/mach-summit/mach_apic.h
index 74e9cbc8c01b..3d6d12937e1f 100644
--- a/include/asm-i386/mach-summit/mach_apic.h
+++ b/include/asm-i386/mach-summit/mach_apic.h
@@ -7,8 +7,6 @@
 #define esr_disable (1)
 #define NO_BALANCE_IRQ (0)
 
-#define NO_IOAPIC_CHECK (1)     /* Don't check I/O APIC ID for xAPIC */
-
 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  * The low nibble is a 4-bit bitmap. */
 #define XAPIC_DEST_CPUS_SHIFT   4
diff --git a/include/asm-i386/mach-visws/do_timer.h b/include/asm-i386/mach-visws/do_timer.h
index 33acd50fd9a8..92d638fc8b11 100644
--- a/include/asm-i386/mach-visws/do_timer.h
+++ b/include/asm-i386/mach-visws/do_timer.h
@@ -1,6 +1,7 @@
 /* defines for inline arch setup functions */
 
 #include <asm/fixmap.h>
+#include <asm/i8259.h>
 #include "cobalt.h"
 
 static inline void do_timer_interrupt_hook(struct pt_regs *regs)
diff --git a/include/asm-i386/mach-visws/mach_apic.h b/include/asm-i386/mach-visws/mach_apic.h
index 4e6cdfb8b091..de438c7147a8 100644
--- a/include/asm-i386/mach-visws/mach_apic.h
+++ b/include/asm-i386/mach-visws/mach_apic.h
@@ -9,8 +9,6 @@
 #define no_balance_irq (0)
 #define esr_disable (0)
 
-#define NO_IOAPIC_CHECK (0)
-
 #define INT_DELIVERY_MODE dest_LowestPrio
 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
 
diff --git a/include/asm-i386/mmzone.h b/include/asm-i386/mmzone.h
index 13830ae67cac..516421300ea2 100644
--- a/include/asm-i386/mmzone.h
+++ b/include/asm-i386/mmzone.h
@@ -8,21 +8,43 @@
 
 #include <asm/smp.h>
 
-#ifdef CONFIG_DISCONTIGMEM
-
 #ifdef CONFIG_NUMA
-        #ifdef CONFIG_X86_NUMAQ
-                #include <asm/numaq.h>
-        #else   /* summit or generic arch */
-                #include <asm/srat.h>
-        #endif
+extern struct pglist_data *node_data[];
+#define NODE_DATA(nid)  (node_data[nid])
+
+#ifdef CONFIG_X86_NUMAQ
+        #include <asm/numaq.h>
+#else   /* summit or generic arch */
+        #include <asm/srat.h>
+#endif
+
+extern int get_memcfg_numa_flat(void );
+/*
+ * This allows any one NUMA architecture to be compiled
+ * for, and still fall back to the flat function if it
+ * fails.
+ */
+static inline void get_memcfg_numa(void)
+{
+#ifdef CONFIG_X86_NUMAQ
+        if (get_memcfg_numaq())
+                return;
+#elif CONFIG_ACPI_SRAT
+        if (get_memcfg_from_srat())
+                return;
+#endif
+
+        get_memcfg_numa_flat();
+}
+
+extern int early_pfn_to_nid(unsigned long pfn);
+
 #else /* !CONFIG_NUMA */
-        #define get_memcfg_numa get_memcfg_numa_flat
-        #define get_zholes_size(n) (0)
+#define get_memcfg_numa get_memcfg_numa_flat
+#define get_zholes_size(n) (0)
 #endif /* CONFIG_NUMA */
 
-extern struct pglist_data *node_data[];
-#define NODE_DATA(nid)          (node_data[nid])
+#ifdef CONFIG_DISCONTIGMEM
 
 /*
  * generic node memory support, the following assumptions apply:
@@ -48,26 +70,6 @@ static inline int pfn_to_nid(unsigned long pfn)
 #endif
 }
 
-/*
- * Following are macros that are specific to this numa platform.
- */
-#define reserve_bootmem(addr, size) \
-        reserve_bootmem_node(NODE_DATA(0), (addr), (size))
-#define alloc_bootmem(x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_low(x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
-#define alloc_bootmem_pages(x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_low_pages(x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
-#define alloc_bootmem_node(ignore, x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_pages_node(ignore, x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_low_pages_node(ignore, x) \
-        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
-
 #define node_localnr(pfn, nid)          ((pfn) - node_data[nid]->node_start_pfn)
 
 /*
@@ -79,7 +81,6 @@ static inline int pfn_to_nid(unsigned long pfn)
  */
 #define kvaddr_to_nid(kaddr)    pfn_to_nid(__pa(kaddr) >> PAGE_SHIFT)
 
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)                                               \
 ({                                                                      \
@@ -100,7 +101,7 @@ static inline int pfn_to_nid(unsigned long pfn)
 ({                                                                      \
         unsigned long __pfn = pfn;                                      \
         int __node  = pfn_to_nid(__pfn);                                \
-        &node_mem_map(__node)[node_localnr(__pfn,__node)];              \
+        &NODE_DATA(__node)->node_mem_map[node_localnr(__pfn,__node)];   \
 })
 
 #define page_to_pfn(pg)                                                 \
@@ -122,26 +123,32 @@ static inline int pfn_valid(int pfn)
                 return (pfn < node_end_pfn(nid));
         return 0;
 }
-#endif
+#endif /* CONFIG_X86_NUMAQ */
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
 
-extern int get_memcfg_numa_flat(void );
 /*
- * This allows any one NUMA architecture to be compiled
- * for, and still fall back to the flat function if it
- * fails.
+ * Following are macros that are specific to this numa platform.
  */
-static inline void get_memcfg_numa(void)
-{
-#ifdef CONFIG_X86_NUMAQ
-        if (get_memcfg_numaq())
-                return;
-#elif CONFIG_ACPI_SRAT
-        if (get_memcfg_from_srat())
-                return;
-#endif
+#define reserve_bootmem(addr, size) \
+        reserve_bootmem_node(NODE_DATA(0), (addr), (size))
+#define alloc_bootmem(x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_low(x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
+#define alloc_bootmem_pages(x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_low_pages(x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
+#define alloc_bootmem_node(ignore, x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_pages_node(ignore, x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_low_pages_node(ignore, x) \
+        __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
 
-        get_memcfg_numa_flat();
-}
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
 
-#endif /* CONFIG_DISCONTIGMEM */
 #endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-i386/mpspec.h b/include/asm-i386/mpspec.h
index d9fafba075bc..64a0b8e6afeb 100644
--- a/include/asm-i386/mpspec.h
+++ b/include/asm-i386/mpspec.h
@@ -11,6 +11,7 @@ extern int mp_bus_id_to_local [MAX_MP_BUSSES];
 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
 
+extern unsigned int def_to_bigsmp;
 extern unsigned int boot_cpu_physical_apicid;
 extern int smp_found_config;
 extern void find_smp_config (void);
@@ -26,14 +27,14 @@ extern unsigned long mp_lapic_addr;
 extern int pic_mode;
 extern int using_apic_timer;
 
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 extern void mp_register_lapic (u8 id, u8 enabled);
 extern void mp_register_lapic_address (u64 address);
 extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
 extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
 extern void mp_config_acpi_legacy_irqs (void);
 extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
-#endif /*CONFIG_ACPI_BOOT*/
+#endif /* CONFIG_ACPI */
 
 #define PHYSID_ARRAY_SIZE       BITS_TO_LONGS(MAX_APICS)
 
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index c76fce8badbb..62b76cd96957 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -47,6 +47,21 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
                      : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
         ret__; })
 
+/* rdmsr with exception handling */
+#define rdmsr_safe(msr,a,b) ({ int ret__;                                               \
+        asm volatile("2: rdmsr ; xorl %0,%0\n"                                          \
+                     "1:\n\t"                                                           \
+                     ".section .fixup,\"ax\"\n\t"                                       \
+                     "3:  movl %4,%0 ; jmp 1b\n\t"                                      \
+                     ".previous\n\t"                                                    \
+                     ".section __ex_table,\"a\"\n"                                      \
+                     "   .align 4\n\t"                                                  \
+                     "   .long  2b,3b\n\t"                                              \
+                     ".previous"                                                        \
+                     : "=r" (ret__), "=a" (*(a)), "=d" (*(b))                           \
+                     : "c" (msr), "i" (-EFAULT));\
+        ret__; })
+
 #define rdtsc(low,high) \
      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
 
diff --git a/include/asm-i386/page.h b/include/asm-i386/page.h
index ed13969fa2d6..73296d9924fb 100644
--- a/include/asm-i386/page.h
+++ b/include/asm-i386/page.h
@@ -103,29 +103,20 @@ typedef struct { unsigned long pgprot; } pgprot_t;
  */
 extern unsigned int __VMALLOC_RESERVE;
 
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 extern int sysctl_legacy_va_layout;
 
+extern int page_is_ram(unsigned long pagenr);
+
 #endif /* __ASSEMBLY__ */
 
 #ifdef __ASSEMBLY__
 #define __PAGE_OFFSET           (0xC0000000)
+#define __PHYSICAL_START        CONFIG_PHYSICAL_START
 #else
 #define __PAGE_OFFSET           (0xC0000000UL)
+#define __PHYSICAL_START        ((unsigned long)CONFIG_PHYSICAL_START)
 #endif
+#define __KERNEL_START          (__PAGE_OFFSET + __PHYSICAL_START)
 
 
 #define PAGE_OFFSET             ((unsigned long)__PAGE_OFFSET)
@@ -134,11 +125,11 @@ extern int sysctl_legacy_va_layout;
 #define __pa(x)                 ((unsigned long)(x)-PAGE_OFFSET)
 #define __va(x)                 ((void *)((unsigned long)(x)+PAGE_OFFSET))
 #define pfn_to_kaddr(pfn)      __va((pfn) << PAGE_SHIFT)
-#ifndef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_FLATMEM
 #define pfn_to_page(pfn)        (mem_map + (pfn))
 #define page_to_pfn(page)       ((unsigned long)((page) - mem_map))
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
-#endif /* !CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_FLATMEM */
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 
 #define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
@@ -150,4 +141,6 @@ extern int sysctl_legacy_va_layout;
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _I386_PAGE_H */
diff --git a/include/asm-i386/param.h b/include/asm-i386/param.h
index b6440526e42a..fa02e67ea86b 100644
--- a/include/asm-i386/param.h
+++ b/include/asm-i386/param.h
@@ -1,8 +1,10 @@
+#include <linux/config.h>
+
 #ifndef _ASMi386_PARAM_H
 #define _ASMi386_PARAM_H
 
 #ifdef __KERNEL__
-# define HZ             1000            /* Internal kernel timer frequency */
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
 # define USER_HZ        100             /* .. some user interfaces are in "ticks" */
 # define CLOCKS_PER_SEC         (USER_HZ)       /* like times() */
 #endif
diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h
index fb749b85a739..78c85985aee3 100644
--- a/include/asm-i386/pci.h
+++ b/include/asm-i386/pci.h
@@ -27,7 +27,7 @@ void pcibios_config_init(void);
 struct pci_bus * pcibios_scan_root(int bus);
 
 void pcibios_set_master(struct pci_dev *dev);
-void pcibios_penalize_isa_irq(int irq);
+void pcibios_penalize_isa_irq(int irq, int active);
 struct irq_routing_table *pcibios_get_irq_routing_table(void);
 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
 
@@ -99,6 +99,16 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 #endif /* __KERNEL__ */
 
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h
index d609f9c2c1f0..2e3f4a344a2d 100644
--- a/include/asm-i386/pgtable-3level.h
+++ b/include/asm-i386/pgtable-3level.h
@@ -64,7 +64,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
 #define set_pmd(pmdptr,pmdval) \
                 set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
 #define set_pud(pudptr,pudval) \
-                set_64bit((unsigned long long *)(pudptr),pud_val(pudval))
+                (*(pudptr) = (pudval))
 
 /*
  * Pentium-II erratum A13: in PAE mode we explicitly have to flush
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index 8d60c2b4b003..47bc1ffa3d4c 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -86,9 +86,7 @@ void paging_init(void);
 #endif
 
 /*
- * The 4MB page is guessing..  Detailed in the infamous "Chapter H"
- * of the Pentium details, but assuming intel did the straightforward
- * thing, this bit set in the page directory entry just means that
+ * _PAGE_PSE set in the page directory entry just means that
  * the page directory entry points directly to a 4MB-aligned block of
  * memory. 
  */
@@ -119,8 +117,10 @@ void paging_init(void);
 #define _PAGE_UNUSED2   0x400
 #define _PAGE_UNUSED3   0x800
 
-#define _PAGE_FILE      0x040   /* set:pagecache unset:swap */
-#define _PAGE_PROTNONE  0x080   /* If not present */
+/* If _PAGE_PRESENT is clear, we use these: */
+#define _PAGE_FILE      0x040   /* nonlinear file mapping, saved PTE; unset:swap */
+#define _PAGE_PROTNONE  0x080   /* if the user mapped it with PROT_NONE;
+                                   pte_present gives true */
 #ifdef CONFIG_X86_PAE
 #define _PAGE_NX        (1ULL<<_PAGE_BIT_NX)
 #else
@@ -215,11 +215,13 @@ extern unsigned long pg0[];
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
+#define __LARGE_PTE (_PAGE_PSE | _PAGE_PRESENT)
 static inline int pte_user(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
 static inline int pte_read(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
 static inline int pte_dirty(pte_t pte)          { return (pte).pte_low & _PAGE_DIRTY; }
 static inline int pte_young(pte_t pte)          { return (pte).pte_low & _PAGE_ACCESSED; }
 static inline int pte_write(pte_t pte)          { return (pte).pte_low & _PAGE_RW; }
+static inline int pte_huge(pte_t pte)           { return ((pte).pte_low & __LARGE_PTE) == __LARGE_PTE; }
 
 /*
  * The following only works if pte_present() is not true.
@@ -236,6 +238,7 @@ static inline pte_t pte_mkexec(pte_t pte)	{ (pte).pte_low |= _PAGE_USER; return
 static inline pte_t pte_mkdirty(pte_t pte)      { (pte).pte_low |= _PAGE_DIRTY; return pte; }
 static inline pte_t pte_mkyoung(pte_t pte)      { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
 static inline pte_t pte_mkwrite(pte_t pte)      { (pte).pte_low |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkhuge(pte_t pte)       { (pte).pte_low |= __LARGE_PTE; return pte; }
 
 #ifdef CONFIG_X86_PAE
 # include <asm/pgtable-3level.h>
@@ -257,12 +260,39 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned
         return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low);
 }
 
+static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
+{
+        pte_t pte;
+        if (full) {
+                pte = *ptep;
+                *ptep = __pte(0);
+        } else {
+                pte = ptep_get_and_clear(mm, addr, ptep);
+        }
+        return pte;
+}
+
 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         clear_bit(_PAGE_BIT_RW, &ptep->pte_low);
 }
 
 /*
+ * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
+ *
+ *  dst - pointer to pgd range anwhere on a pgd page
+ *  src - ""
+ *  count - the number of pgds to copy.
+ *
+ * dst and src can be on the same page, but the range must not overlap,
+ * and must not cross a page boundary.
+ */
+static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
+{
+       memcpy(dst, src, count * sizeof(pgd_t));
+}
+
+/*
  * Macro to mark a page protection value as "uncacheable".  On processors which do not support
  * it, this is a no-op.
  */
@@ -275,7 +305,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
  */
 
 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
-#define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
@@ -398,9 +427,9 @@ extern void noexec_setup(const char *str);
 
 #endif /* !__ASSEMBLY__ */
 
-#ifndef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_FLATMEM
 #define kern_addr_valid(addr)   (1)
-#endif /* !CONFIG_DISCONTIGMEM */
+#endif /* CONFIG_FLATMEM */
 
 #define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
                 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
@@ -415,6 +444,7 @@ extern void noexec_setup(const char *str);
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 #define __HAVE_ARCH_PTE_SAME
 #include <asm-generic/pgtable.h>
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 359bb0151742..37bef8ed7bed 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -29,7 +29,7 @@ struct desc_struct {
 };
 
 #define desc_empty(desc) \
-                (!((desc)->a + (desc)->b))
+                (!((desc)->a | (desc)->b))
 
 #define desc_equal(desc1, desc2) \
                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
@@ -203,9 +203,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
         return edx;
 }
 
-#define load_cr3(pgdir) \
-        asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
-
+#define load_cr3(pgdir) write_cr3(__pa(pgdir))
 
 /*
  * Intel CPU features in CR4
@@ -232,22 +230,20 @@ extern unsigned long mmu_cr4_features;
 
 static inline void set_in_cr4 (unsigned long mask)
 {
+        unsigned cr4;
         mmu_cr4_features |= mask;
-        __asm__("movl %%cr4,%%eax\n\t"
-                "orl %0,%%eax\n\t"
-                "movl %%eax,%%cr4\n"
-                : : "irg" (mask)
-                :"ax");
+        cr4 = read_cr4();
+        cr4 |= mask;
+        write_cr4(cr4);
 }
 
 static inline void clear_in_cr4 (unsigned long mask)
 {
+        unsigned cr4;
         mmu_cr4_features &= ~mask;
-        __asm__("movl %%cr4,%%eax\n\t"
-                "andl %0,%%eax\n\t"
-                "movl %%eax,%%cr4\n"
-                : : "irg" (~mask)
-                :"ax");
+        cr4 = read_cr4();
+        cr4 &= ~mask;
+        write_cr4(cr4);
 }
 
 /*
@@ -281,6 +277,11 @@ static inline void clear_in_cr4 (unsigned long mask)
         outb((data), 0x23); \
 } while (0)
 
+static inline void serialize_cpu(void)
+{
+         __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
+}
+
 static inline void __monitor(const void *eax, unsigned long ecx,
                 unsigned long edx)
 {
@@ -454,6 +455,7 @@ struct thread_struct {
         unsigned int            saved_fs, saved_gs;
 /* IO permissions */
         unsigned long   *io_bitmap_ptr;
+        unsigned long   iopl;
 /* max allowed port in the bitmap, in bytes: */
         unsigned long   io_bitmap_max;
 };
@@ -474,7 +476,6 @@ struct thread_struct {
         .esp0           = sizeof(init_stack) + (long)&init_stack,       \
         .ss0            = __KERNEL_DS,                                  \
         .ss1            = __KERNEL_CS,                                  \
-        .ldt            = GDT_ENTRY_LDT,                                \
         .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 }
@@ -501,12 +502,31 @@ static inline void load_esp0(struct tss_struct *tss, struct thread_struct *threa
 } while (0)
 
 /*
- * This special macro can be used to load a debugging register
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register)                             \
+                __asm__("movl %%db" #register ", %0"            \
+                        :"=r" (var))
+#define set_debugreg(value, register)                   \
+                __asm__("movl %0,%%db" #register                \
+                        : /* no output */                       \
+                        :"r" (value))
+
+/*
+ * Set IOPL bits in EFLAGS from given mask
  */
-#define loaddebug(thread,register) \
-               __asm__("movl %0,%%db" #register  \
-                       : /* no output */ \
-                       :"r" ((thread)->debugreg[register]))
+static inline void set_iopl_mask(unsigned mask)
+{
+        unsigned int reg;
+        __asm__ __volatile__ ("pushfl;"
+                              "popl %0;"
+                              "andl %1, %0;"
+                              "orl %2, %0;"
+                              "pushl %0;"
+                              "popfl"
+                                : "=&r" (reg)
+                                : "i" (~X86_EFLAGS_IOPL), "r" (mask));
+}
 
 /* Forward declaration, a strange C thing */
 struct task_struct;
@@ -687,5 +707,15 @@ extern void select_idle_routine(const struct cpuinfo_x86 *c);
 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 
 extern unsigned long boot_option_idle_override;
+extern void enable_sep_cpu(void);
+extern int sysenter_setup(void);
+
+#ifdef CONFIG_MTRR
+extern void mtrr_ap_init(void);
+extern void mtrr_bp_init(void);
+#else
+#define mtrr_ap_init() do {} while (0)
+#define mtrr_bp_init() do {} while (0)
+#endif
 
 #endif /* __ASM_I386_PROCESSOR_H */
diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h
index 8618914b3521..7e0f2945d17d 100644
--- a/include/asm-i386/ptrace.h
+++ b/include/asm-i386/ptrace.h
@@ -55,15 +55,33 @@ struct pt_regs {
 #define PTRACE_SET_THREAD_AREA    26
 
 #ifdef __KERNEL__
+
+#include <asm/vm86.h>
+
 struct task_struct;
 extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code);
-#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs))
+
+/*
+ * user_mode_vm(regs) determines whether a register set came from user mode.
+ * This is true if V8086 mode was enabled OR if the register set was from
+ * protected mode with RPL-3 CS value.  This tricky test checks that with
+ * one comparison.  Many places in the kernel can bypass this full check
+ * if they have already ruled out V8086 mode, so user_mode(regs) can be used.
+ */
+static inline int user_mode(struct pt_regs *regs)
+{
+        return (regs->xcs & 3) != 0;
+}
+static inline int user_mode_vm(struct pt_regs *regs)
+{
+        return ((regs->xcs & 3) | (regs->eflags & VM_MASK)) != 0;
+}
 #define instruction_pointer(regs) ((regs)->eip)
 #if defined(CONFIG_SMP) && defined(CONFIG_FRAME_POINTER)
 extern unsigned long profile_pc(struct pt_regs *regs);
 #else
 #define profile_pc(regs) instruction_pointer(regs)
 #endif
-#endif
+#endif /* __KERNEL__ */
 
 #endif
diff --git a/include/asm-i386/serial.h b/include/asm-i386/serial.h
index 21ddecc77c77..e1ecfccb743b 100644
--- a/include/asm-i386/serial.h
+++ b/include/asm-i386/serial.h
@@ -22,109 +22,9 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#define HUB6_FLAGS 0
-#endif
-
-#define MCA_COM_FLAGS   (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
-
-/*
- * The following define the access methods for the HUB6 card. All
- * access is through two ports for all 24 possible chips. The card is
- * selected through the high 2 bits, the port on that card with the
- * "middle" 3 bits, and the register on that port with the bottom
- * 3 bits.
- *
- * While the access port and interrupt is configurable, the default
- * port locations are 0x302 for the port control register, and 0x303
- * for the data read/write register. Normally, the interrupt is at irq3
- * but can be anything from 3 to 7 inclusive. Note that using 3 will
- * require disabling com2.
- */
-
-#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
-
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif
-
-/* You can have up to four HUB6's in the system, but I've only
- * included two cards here for a total of twelve ports.
- */
-#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
-#define HUB6_SERIAL_PORT_DFNS           \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
-#else
-#define HUB6_SERIAL_PORT_DFNS
-#endif
-
-#ifdef CONFIG_MCA
-#define MCA_SERIAL_PORT_DFNS                    \
-        { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
-#else
-#define MCA_SERIAL_PORT_DFNS
-#endif
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS         \
-        HUB6_SERIAL_PORT_DFNS           \
-        MCA_SERIAL_PORT_DFNS
-
diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h
index 7a32184d54bf..826a8ca50ac8 100644
--- a/include/asm-i386/setup.h
+++ b/include/asm-i386/setup.h
@@ -44,7 +44,7 @@ extern unsigned char boot_params[PARAM_SIZE];
 #define EFI_SYSTAB ((efi_system_table_t *) *((unsigned long *)(PARAM+0x1c4)))
 #define EFI_MEMDESC_SIZE (*((unsigned long *) (PARAM+0x1c8)))
 #define EFI_MEMDESC_VERSION (*((unsigned long *) (PARAM+0x1cc)))
-#define EFI_MEMMAP ((efi_memory_desc_t *) *((unsigned long *)(PARAM+0x1d0)))
+#define EFI_MEMMAP ((void *) *((unsigned long *)(PARAM+0x1d0)))
 #define EFI_MEMMAP_SIZE (*((unsigned long *) (PARAM+0x1d4)))
 #define MOUNT_ROOT_RDONLY (*(unsigned short *) (PARAM+0x1F2))
 #define RAMDISK_FLAGS (*(unsigned short *) (PARAM+0x1F8))
diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h
index e03a206dfa36..13250199976d 100644
--- a/include/asm-i386/smp.h
+++ b/include/asm-i386/smp.h
@@ -37,25 +37,29 @@ extern int smp_num_siblings;
 extern cpumask_t cpu_sibling_map[];
 extern cpumask_t cpu_core_map[];
 
-extern void smp_flush_tlb(void);
-extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
-extern void smp_invalidate_rcv(void);           /* Process an NMI */
 extern void (*mtrr_hook) (void);
 extern void zap_low_mappings (void);
+extern void lock_ipi_call_lock(void);
+extern void unlock_ipi_call_lock(void);
 
 #define MAX_APICID 256
 extern u8 x86_cpu_to_apicid[];
 
+#ifdef CONFIG_HOTPLUG_CPU
+extern void cpu_exit_clear(void);
+extern void cpu_uninit(void);
+#endif
+
 /*
  * This function is needed by all SMP systems. It must _always_ be valid
  * from the initial startup. We map APIC_BASE very early in page_setup(),
  * so this is correct in the x86 case.
  */
-#define __smp_processor_id() (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
 
 extern cpumask_t cpu_callout_map;
 extern cpumask_t cpu_callin_map;
-#define cpu_possible_map cpu_callout_map
+extern cpumask_t cpu_possible_map;
 
 /* We don't mark CPUs online until __cpu_up(), so we need another measure */
 static inline int num_booting_cpus(void)
@@ -83,6 +87,9 @@ static __inline int logical_smp_processor_id(void)
 }
 
 #endif
+
+extern int __cpu_disable(void);
+extern void __cpu_die(unsigned int cpu);
 #endif /* !__ASSEMBLY__ */
 
 #define NO_PROC_ID              0xFF            /* No processor magic marker */
diff --git a/include/asm-i386/socket.h b/include/asm-i386/socket.h
index 07f6b38ad140..802ae76195b7 100644
--- a/include/asm-i386/socket.h
+++ b/include/asm-i386/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-i386/sparsemem.h b/include/asm-i386/sparsemem.h
new file mode 100644
index 000000000000..cfeed990585f
--- /dev/null
+++ b/include/asm-i386/sparsemem.h
@@ -0,0 +1,31 @@
+#ifndef _I386_SPARSEMEM_H
+#define _I386_SPARSEMEM_H
+#ifdef CONFIG_SPARSEMEM
+
+/*
+ * generic non-linear memory support:
+ *
+ * 1) we will not split memory into more chunks than will fit into the
+ *    flags field of the struct page
+ */
+
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSADDR_BITS            2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#ifdef CONFIG_X86_PAE
+#define SECTION_SIZE_BITS       30
+#define MAX_PHYSADDR_BITS       36
+#define MAX_PHYSMEM_BITS        36
+#else
+#define SECTION_SIZE_BITS       26
+#define MAX_PHYSADDR_BITS       32
+#define MAX_PHYSMEM_BITS        32
+#endif
+
+/* XXX: FIXME -- wli */
+#define kern_addr_valid(kaddr)  (0)
+
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _I386_SPARSEMEM_H */
diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h
index 6a78ac58c194..02c8f5d22065 100644
--- a/include/asm-i386/string.h
+++ b/include/asm-i386/string.h
@@ -116,7 +116,8 @@ __asm__ __volatile__(
         "orb $1,%%al\n"
         "3:"
         :"=a" (__res), "=&S" (d0), "=&D" (d1)
-                     :"1" (cs),"2" (ct));
+        :"1" (cs),"2" (ct)
+        :"memory");
 return __res;
 }
 
@@ -138,8 +139,9 @@ __asm__ __volatile__(
         "3:\tsbbl %%eax,%%eax\n\t"
         "orb $1,%%al\n"
         "4:"
-                     :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
-                     :"1" (cs),"2" (ct),"3" (count));
+        :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
+        :"1" (cs),"2" (ct),"3" (count)
+        :"memory");
 return __res;
 }
 
@@ -158,7 +160,9 @@ __asm__ __volatile__(
         "movl $1,%1\n"
         "2:\tmovl %1,%0\n\t"
         "decl %0"
-        :"=a" (__res), "=&S" (d0) : "1" (s),"0" (c));
+        :"=a" (__res), "=&S" (d0)
+        :"1" (s),"0" (c)
+        :"memory");
 return __res;
 }
 
@@ -175,7 +179,9 @@ __asm__ __volatile__(
         "leal -1(%%esi),%0\n"
         "2:\ttestb %%al,%%al\n\t"
         "jne 1b"
-        :"=g" (__res), "=&S" (d0), "=&a" (d1) :"0" (0),"1" (s),"2" (c));
+        :"=g" (__res), "=&S" (d0), "=&a" (d1)
+        :"0" (0),"1" (s),"2" (c)
+        :"memory");
 return __res;
 }
 
@@ -189,7 +195,9 @@ __asm__ __volatile__(
         "scasb\n\t"
         "notl %0\n\t"
         "decl %0"
-        :"=c" (__res), "=&D" (d0) :"1" (s),"a" (0), "0" (0xffffffffu));
+        :"=c" (__res), "=&D" (d0)
+        :"1" (s),"a" (0), "0" (0xffffffffu)
+        :"memory");
 return __res;
 }
 
@@ -333,7 +341,9 @@ __asm__ __volatile__(
         "je 1f\n\t"
         "movl $1,%0\n"
         "1:\tdecl %0"
-        :"=D" (__res), "=&c" (d0) : "a" (c),"0" (cs),"1" (count));
+        :"=D" (__res), "=&c" (d0)
+        :"a" (c),"0" (cs),"1" (count)
+        :"memory");
 return __res;
 }
 
@@ -369,7 +379,7 @@ __asm__ __volatile__(
         "je 2f\n\t"
         "stosb\n"
         "2:"
-        : "=&c" (d0), "=&D" (d1)
+        :"=&c" (d0), "=&D" (d1)
         :"a" (c), "q" (count), "0" (count/4), "1" ((long) s)
         :"memory");
 return (s);     
@@ -392,7 +402,8 @@ __asm__ __volatile__(
         "jne 1b\n"
         "3:\tsubl %2,%0"
         :"=a" (__res), "=&d" (d0)
-        :"c" (s),"1" (count));
+        :"c" (s),"1" (count)
+        :"memory");
 return __res;
 }
 /* end of additional stuff */
@@ -473,7 +484,8 @@ static inline void * memscan(void * addr, int c, size_t size)
                 "dec %%edi\n"
                 "1:"
                 : "=D" (addr), "=c" (size)
-                : "0" (addr), "1" (size), "a" (c));
+                : "0" (addr), "1" (size), "a" (c)
+                : "memory");
         return addr;
 }
 
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index 3db717a244f0..acd5c26b69ba 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -14,8 +14,7 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc
 
 #define switch_to(prev,next,last) do {                                  \
         unsigned long esi,edi;                                          \
-        asm volatile("pushfl\n\t"                                       \
-                     "pushl %%ebp\n\t"                                  \
+        asm volatile("pushl %%ebp\n\t"                                  \
                      "movl %%esp,%0\n\t"        /* save ESP */          \
                      "movl %5,%%esp\n\t"        /* restore ESP */       \
                      "movl $1f,%1\n\t"          /* save EIP */          \
@@ -23,7 +22,6 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc
                      "jmp __switch_to\n"                                \
                      "1:\t"                                             \
                      "popl %%ebp\n\t"                                   \
-                     "popfl"                                            \
                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
                       "=a" (last),"=S" (esi),"=D" (edi)                 \
                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
@@ -93,13 +91,13 @@ static inline unsigned long _get_base(char * addr)
                 ".align 4\n\t"                  \
                 ".long 1b,3b\n"                 \
                 ".previous"                     \
-                : :"m" (value))
+                : :"rm" (value))
 
 /*
  * Save a segment register away
  */
 #define savesegment(seg, value) \
-        asm volatile("mov %%" #seg ",%0":"=m" (value))
+        asm volatile("mov %%" #seg ",%0":"=rm" (value))
 
 /*
  * Clear and set 'TS' bit respectively
@@ -107,13 +105,33 @@ static inline unsigned long _get_base(char * addr)
 #define clts() __asm__ __volatile__ ("clts")
 #define read_cr0() ({ \
         unsigned int __dummy; \
-        __asm__( \
+        __asm__ __volatile__( \
                 "movl %%cr0,%0\n\t" \
                 :"=r" (__dummy)); \
         __dummy; \
 })
 #define write_cr0(x) \
-        __asm__("movl %0,%%cr0": :"r" (x));
+        __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
+
+#define read_cr2() ({ \
+        unsigned int __dummy; \
+        __asm__ __volatile__( \
+                "movl %%cr2,%0\n\t" \
+                :"=r" (__dummy)); \
+        __dummy; \
+})
+#define write_cr2(x) \
+        __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
+
+#define read_cr3() ({ \
+        unsigned int __dummy; \
+        __asm__ ( \
+                "movl %%cr3,%0\n\t" \
+                :"=r" (__dummy)); \
+        __dummy; \
+})
+#define write_cr3(x) \
+        __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
 
 #define read_cr4() ({ \
         unsigned int __dummy; \
@@ -123,7 +141,7 @@ static inline unsigned long _get_base(char * addr)
         __dummy; \
 })
 #define write_cr4(x) \
-        __asm__("movl %0,%%cr4": :"r" (x));
+        __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
 #define stts() write_cr0(8 | read_cr0())
 
 #endif  /* __KERNEL__ */
@@ -447,6 +465,8 @@ struct alt_instr {
 #define local_irq_enable()      __asm__ __volatile__("sti": : :"memory")
 /* used in the idle loop; sti takes one instruction cycle to complete */
 #define safe_halt()             __asm__ __volatile__("sti; hlt": : :"memory")
+/* used when interrupts are already enabled or to shutdown the processor */
+#define halt()                  __asm__ __volatile__("hlt": : :"memory")
 
 #define irqs_disabled()                 \
 ({                                      \
diff --git a/include/asm-i386/thread_info.h b/include/asm-i386/thread_info.h
index 2cd57271801d..e2cb9fa6f563 100644
--- a/include/asm-i386/thread_info.h
+++ b/include/asm-i386/thread_info.h
@@ -31,7 +31,7 @@ struct thread_info {
         unsigned long           flags;          /* low level flags */
         unsigned long           status;         /* thread-synchronous flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
 
         mm_segment_t            addr_limit;     /* thread address space:
@@ -139,6 +139,7 @@ register unsigned long current_stack_pointer asm("esp") __attribute_used__;
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_SINGLESTEP          4       /* restore singlestep on return to user mode */
 #define TIF_IRET                5       /* return with iret */
+#define TIF_SYSCALL_EMU         6       /* syscall emulation active */
 #define TIF_SYSCALL_AUDIT       7       /* syscall auditing active */
 #define TIF_SECCOMP             8       /* secure computing */
 #define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling TIF_NEED_RESCHED */
@@ -150,13 +151,15 @@ register unsigned long current_stack_pointer asm("esp") __attribute_used__;
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
 #define _TIF_IRET               (1<<TIF_IRET)
+#define _TIF_SYSCALL_EMU        (1<<TIF_SYSCALL_EMU)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK \
-  (0x0000FFFF & ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|_TIF_SECCOMP))
+  (0x0000FFFF & ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|\
+                  _TIF_SECCOMP|_TIF_SYSCALL_EMU))
 /* work to do on any return to u-space */
 #define _TIF_ALLWORK_MASK       (0x0000FFFF & ~_TIF_SECCOMP)
 
diff --git a/include/asm-i386/timer.h b/include/asm-i386/timer.h
index c34709849839..aed16437479d 100644
--- a/include/asm-i386/timer.h
+++ b/include/asm-i386/timer.h
@@ -1,6 +1,7 @@
 #ifndef _ASMi386_TIMER_H
 #define _ASMi386_TIMER_H
 #include <linux/init.h>
+#include <linux/pm.h>
 
 /**
  * struct timer_ops - used to define a timer source
@@ -22,6 +23,9 @@ struct timer_opts {
         unsigned long (*get_offset)(void);
         unsigned long long (*monotonic_clock)(void);
         void (*delay)(unsigned long);
+        unsigned long (*read_timer)(void);
+        int (*suspend)(pm_message_t state);
+        int (*resume)(void);
 };
 
 struct init_timer_opts {
@@ -52,6 +56,7 @@ extern struct init_timer_opts timer_cyclone_init;
 #endif
 
 extern unsigned long calibrate_tsc(void);
+extern unsigned long read_timer_tsc(void);
 extern void init_cpu_khz(void);
 extern int recalibrate_cpu_khz(void);
 #ifdef CONFIG_HPET_TIMER
diff --git a/include/asm-i386/timex.h b/include/asm-i386/timex.h
index b41e484c3445..292b5a68f627 100644
--- a/include/asm-i386/timex.h
+++ b/include/asm-i386/timex.h
@@ -47,6 +47,9 @@ static inline cycles_t get_cycles (void)
         return ret;
 }
 
-extern unsigned long cpu_khz;
+extern unsigned int cpu_khz;
+
+extern int read_current_timer(unsigned long *timer_value);
+#define ARCH_HAS_READ_CURRENT_TIMER     1
 
 #endif
diff --git a/include/asm-i386/tlbflush.h b/include/asm-i386/tlbflush.h
index f22fab0cea26..ab216e1370ef 100644
--- a/include/asm-i386/tlbflush.h
+++ b/include/asm-i386/tlbflush.h
@@ -22,16 +22,18 @@
  */
 #define __flush_tlb_global()                                            \
         do {                                                            \
-                unsigned int tmpreg;                                    \
+                unsigned int tmpreg, cr4, cr4_orig;                     \
                                                                         \
                 __asm__ __volatile__(                                   \
-                        "movl %1, %%cr4;  # turn off PGE     \n"        \
+                        "movl %%cr4, %2;  # turn off PGE     \n"        \
+                        "movl %2, %1;                        \n"        \
+                        "andl %3, %1;                        \n"        \
+                        "movl %1, %%cr4;                     \n"        \
                         "movl %%cr3, %0;                     \n"        \
                         "movl %0, %%cr3;  # flush TLB        \n"        \
                         "movl %2, %%cr4;  # turn PGE back on \n"        \
-                        : "=&r" (tmpreg)                                \
-                        : "r" (mmu_cr4_features & ~X86_CR4_PGE),        \
-                          "r" (mmu_cr4_features)                        \
+                        : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
+                        : "i" (~X86_CR4_PGE)                            \
                         : "memory");                                    \
         } while (0)
 
diff --git a/include/asm-i386/topology.h b/include/asm-i386/topology.h
index 98f9e6850cba..2461b731781e 100644
--- a/include/asm-i386/topology.h
+++ b/include/asm-i386/topology.h
@@ -60,12 +60,8 @@ static inline int node_to_first_cpu(int node)
         return first_cpu(mask);
 }
 
-/* Returns the number of the node containing PCI bus number 'busnr' */
-static inline cpumask_t __pcibus_to_cpumask(int busnr)
-{
-        return node_to_cpumask(mp_bus_id_to_node[busnr]);
-}
-#define pcibus_to_cpumask(bus)  __pcibus_to_cpumask(bus->number)
+#define pcibus_to_node(bus) mp_bus_id_to_node[(bus)->number]
+#define pcibus_to_cpumask(bus) node_to_cpumask(pcibus_to_node(bus))
 
 /* sched_domains SD_NODE_INIT for NUMAQ machines */
 #define SD_NODE_INIT (struct sched_domain) {            \
@@ -78,11 +74,14 @@ static inline cpumask_t __pcibus_to_cpumask(int busnr)
         .imbalance_pct          = 125,                  \
         .cache_hot_time         = (10*1000000),         \
         .cache_nice_tries       = 1,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 1,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
         .per_cpu_gain           = 100,                  \
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_WAKE_IDLE          \
+                                | SD_BALANCE_FORK       \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h
index 901b77c42b8a..ced00fe8fe61 100644
--- a/include/asm-i386/types.h
+++ b/include/asm-i386/types.h
@@ -63,8 +63,6 @@ typedef u64 sector_t;
 #define HAVE_SECTOR_T
 #endif
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-i386/uaccess.h b/include/asm-i386/uaccess.h
index 886867aea947..89ab7e2bc5aa 100644
--- a/include/asm-i386/uaccess.h
+++ b/include/asm-i386/uaccess.h
@@ -83,30 +83,6 @@ extern struct movsl_mask {
  */
 #define access_ok(type,addr,size) (likely(__range_ok(addr,size) == 0))
 
-/**
- * verify_area: - Obsolete/deprecated and will go away soon,
- * use access_ok() instead.
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * This function has been replaced by access_ok().
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns zero if the memory block may be valid, -EFAULT
- * if it is definitely invalid.
- *
- * See access_ok() for more details.
- */
-static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h
index 61bcc1b1e3f4..a7cb377745bf 100644
--- a/include/asm-i386/unistd.h
+++ b/include/asm-i386/unistd.h
@@ -256,7 +256,7 @@
 #define __NR_io_submit          248
 #define __NR_io_cancel          249
 #define __NR_fadvise64          250
-
+#define __NR_set_zone_reclaim   251
 #define __NR_exit_group         252
 #define __NR_lookup_dcookie     253
 #define __NR_epoll_create       254
@@ -294,8 +294,13 @@
 #define __NR_add_key            286
 #define __NR_request_key        287
 #define __NR_keyctl             288
+#define __NR_ioprio_set         289
+#define __NR_ioprio_get         290
+#define __NR_inotify_init       291
+#define __NR_inotify_add_watch  292
+#define __NR_inotify_rm_watch   293
 
-#define NR_syscalls 289
+#define NR_syscalls 294
 
 /*
  * user-visible error numbers are in the range -1 - -128: see
diff --git a/include/asm-i386/xor.h b/include/asm-i386/xor.h
index f80e2dbe1b56..23c86cef3b25 100644
--- a/include/asm-i386/xor.h
+++ b/include/asm-i386/xor.h
@@ -535,14 +535,14 @@ static struct xor_block_template xor_block_p5_mmx = {
 
 #define XMMS_SAVE do {                          \
         preempt_disable();                      \
+        cr0 = read_cr0();                       \
+        clts();                                 \
         __asm__ __volatile__ (                  \
-                "movl %%cr0,%0          ;\n\t"  \
-                "clts                   ;\n\t"  \
-                "movups %%xmm0,(%1)     ;\n\t"  \
-                "movups %%xmm1,0x10(%1) ;\n\t"  \
-                "movups %%xmm2,0x20(%1) ;\n\t"  \
-                "movups %%xmm3,0x30(%1) ;\n\t"  \
-                : "=&r" (cr0)                   \
+                "movups %%xmm0,(%0)     ;\n\t"  \
+                "movups %%xmm1,0x10(%0) ;\n\t"  \
+                "movups %%xmm2,0x20(%0) ;\n\t"  \
+                "movups %%xmm3,0x30(%0) ;\n\t"  \
+                :                               \
                 : "r" (xmm_save)                \
                 : "memory");                    \
 } while(0)
@@ -550,14 +550,14 @@ static struct xor_block_template xor_block_p5_mmx = {
 #define XMMS_RESTORE do {                       \
         __asm__ __volatile__ (                  \
                 "sfence                 ;\n\t"  \
-                "movups (%1),%%xmm0     ;\n\t"  \
-                "movups 0x10(%1),%%xmm1 ;\n\t"  \
-                "movups 0x20(%1),%%xmm2 ;\n\t"  \
-                "movups 0x30(%1),%%xmm3 ;\n\t"  \
-                "movl   %0,%%cr0        ;\n\t"  \
+                "movups (%0),%%xmm0     ;\n\t"  \
+                "movups 0x10(%0),%%xmm1 ;\n\t"  \
+                "movups 0x20(%0),%%xmm2 ;\n\t"  \
+                "movups 0x30(%0),%%xmm3 ;\n\t"  \
                 :                               \
-                : "r" (cr0), "r" (xmm_save)     \
+                : "r" (xmm_save)                \
                 : "memory");                    \
+        write_cr0(cr0);                         \
         preempt_enable();                       \
 } while(0)
 
diff --git a/include/asm-ia64/acpi-ext.h b/include/asm-ia64/acpi-ext.h
index 9271d74c64cc..56d2ddc97b30 100644
--- a/include/asm-ia64/acpi-ext.h
+++ b/include/asm-ia64/acpi-ext.h
@@ -11,6 +11,7 @@
 #define _ASM_IA64_ACPI_EXT_H
 
 #include <linux/types.h>
+#include <acpi/actypes.h>
 
 extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length);
 
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index 6a26a977f253..3a544ffc5008 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -98,6 +98,15 @@ const char *acpi_get_sysname (void);
 int acpi_request_vector (u32 int_type);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
+/*
+ * Record the cpei override flag and current logical cpu. This is
+ * useful for CPU removal.
+ */
+extern unsigned int can_cpei_retarget(void);
+extern unsigned int is_cpu_cpei_target(unsigned int cpu);
+extern void set_cpei_target_cpu(unsigned int cpu);
+extern unsigned int get_cpei_target_cpu(void);
+
 #ifdef CONFIG_ACPI_NUMA
 /* Proximity bitmap length; _PXM is at most 255 (8 bit)*/
 #define MAX_PXM_DOMAINS (256)
@@ -107,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
 
 extern u16 ia64_acpiid_to_sapicid[];
 
+/*
+ * Refer Intel ACPI _PDC support document for bit definitions
+ */
+#define ACPI_PDC_EST_CAPABILITY_SMP     0x8
+
 #endif /*__KERNEL__*/
 
 #endif /*_ASM_ACPI_H*/
diff --git a/include/asm-ia64/auxvec.h b/include/asm-ia64/auxvec.h
new file mode 100644
index 000000000000..23cebe5685b9
--- /dev/null
+++ b/include/asm-ia64/auxvec.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_IA64_AUXVEC_H
+#define _ASM_IA64_AUXVEC_H
+
+/*
+ * Architecture-neutral AT_ values are in the range 0-17.  Leave some room for more of
+ * them, start the architecture-specific ones at 32.
+ */
+#define AT_SYSINFO      32
+#define AT_SYSINFO_EHDR 33
+
+#endif /* _ASM_IA64_AUXVEC_H */
diff --git a/include/asm-ia64/break.h b/include/asm-ia64/break.h
index 97c7b2d79600..8167828edc4b 100644
--- a/include/asm-ia64/break.h
+++ b/include/asm-ia64/break.h
@@ -12,6 +12,8 @@
  * OS-specific debug break numbers:
  */
 #define __IA64_BREAK_KDB                0x80100
+#define __IA64_BREAK_KPROBE             0x80200
+#define __IA64_BREAK_JPROBE             0x80300
 
 /*
  * OS-specific break numbers:
diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h
index cc0ff0a4bdd0..aaf11f4e9169 100644
--- a/include/asm-ia64/compat.h
+++ b/include/asm-ia64/compat.h
@@ -13,10 +13,10 @@ typedef s32		compat_time_t;
 typedef s32             compat_clock_t;
 typedef s32             compat_key_t;
 typedef s32             compat_pid_t;
-typedef u16             compat_uid_t;
-typedef u16             compat_gid_t;
-typedef u32             compat_uid32_t;
-typedef u32             compat_gid32_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u16             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u16             compat_dev_t;
@@ -27,6 +27,7 @@ typedef u16		compat_ipc_pid_t;
 typedef s32             compat_daddr_t;
 typedef u32             compat_caddr_t;
 typedef __kernel_fsid_t compat_fsid_t;
+typedef s32             compat_timer_t;
 
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
@@ -49,8 +50,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
         compat_dev_t    st_rdev;
         u16             __pad2;
         u32             st_size;
@@ -119,10 +120,10 @@ typedef u32		compat_sigset_word;
 
 struct compat_ipc64_perm {
         compat_key_t key;
-        compat_uid32_t uid;
-        compat_gid32_t gid;
-        compat_uid32_t cuid;
-        compat_gid32_t cgid;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
         unsigned short mode;
         unsigned short __pad1;
         unsigned short seq;
diff --git a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h
index 7d4ccc4b976e..446fce036fd9 100644
--- a/include/asm-ia64/elf.h
+++ b/include/asm-ia64/elf.h
@@ -12,6 +12,7 @@
 
 #include <asm/fpu.h>
 #include <asm/page.h>
+#include <asm/auxvec.h>
 
 /*
  * This is used to ensure we don't load something for the wrong architecture.
@@ -177,13 +178,6 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
    relevant until we have real hardware to play with... */
 #define ELF_PLATFORM    NULL
 
-/*
- * Architecture-neutral AT_ values are in the range 0-17.  Leave some room for more of
- * them, start the architecture-specific ones at 32.
- */
-#define AT_SYSINFO      32
-#define AT_SYSINFO_EHDR 33
-
 #ifdef __KERNEL__
 #define SET_PERSONALITY(ex, ibcs2)      set_personality(PER_LINUX)
 #define elf_read_implies_exec(ex, executable_stack)                                     \
diff --git a/include/asm-ia64/emergency-restart.h b/include/asm-ia64/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-ia64/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-ia64/fcntl.h b/include/asm-ia64/fcntl.h
index d193981bb1d8..1dd275dc8f65 100644
--- a/include/asm-ia64/fcntl.h
+++ b/include/asm-ia64/fcntl.h
@@ -1,84 +1,13 @@
 #ifndef _ASM_IA64_FCNTL_H
 #define _ASM_IA64_FCNTL_H
 /*
- * Based on <asm-i386/fcntl.h>.
- *
  * Modified 1998-2000
  *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
  */
 
-/*
- * open/fcntl - O_SYNC is only implemented on blocks devices and on
- * files located on an ext2 file system
- */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
+#define force_o_largefile()     \
+                (personality(current->personality) != PER_LINUX32)
 
-#define F_LINUX_SPECIFIC_BASE   1024
+#include <asm-generic/fcntl.h>
 
 #endif /* _ASM_IA64_FCNTL_H */
diff --git a/include/asm-ia64/futex.h b/include/asm-ia64/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-ia64/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-ia64/hdreg.h b/include/asm-ia64/hdreg.h
deleted file mode 100644
index 83b5161d2678..000000000000
--- a/include/asm-ia64/hdreg.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *  linux/include/asm-ia64/hdreg.h
- *
- *  Copyright (C) 1994-1996  Linus Torvalds & authors
- */
-
-#warning this file is obsolete, please do not use it
-
-#ifndef __ASM_IA64_HDREG_H
-#define __ASM_IA64_HDREG_H
-
-typedef unsigned short ide_ioreg_t;
-
-#endif /* __ASM_IA64_HDREG_H */
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index cd4e06b74ab6..0cf119b42f7d 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -81,7 +81,6 @@ extern __u8 isa_irq_to_vector_map[16];
 
 extern struct hw_interrupt_type irq_type_ia64_lsapic;   /* CPU-internal interrupt controller */
 
-extern int assign_irq_vector_nopanic (int irq); /* allocate a free vector without panic */
 extern int assign_irq_vector (int irq); /* allocate a free vector */
 extern void free_irq_vector (int vector);
 extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
@@ -117,13 +116,6 @@ __ia64_local_vector_to_irq (ia64_vector vec)
  * and to obtain the irq descriptor for a given irq number.
  */
 
-/* Return a pointer to the irq descriptor for IRQ.  */
-static inline irq_desc_t *
-irq_descp (int irq)
-{
-        return irq_desc + irq;
-}
-
 /* Extract the IA-64 vector that corresponds to IRQ.  */
 static inline ia64_vector
 irq_to_vector (int irq)
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h
index 491e9d1fc538..cf772a67f858 100644
--- a/include/asm-ia64/io.h
+++ b/include/asm-ia64/io.h
@@ -23,7 +23,7 @@
 #define __SLOW_DOWN_IO  do { } while (0)
 #define SLOW_DOWN_IO    do { } while (0)
 
-#define __IA64_UNCACHED_OFFSET  0xc000000000000000UL    /* region 6 */
+#define __IA64_UNCACHED_OFFSET  RGN_BASE(RGN_UNCACHED)
 
 /*
  * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
@@ -41,7 +41,7 @@
 #define IO_SPACE_BASE(space)            ((space) << IO_SPACE_BITS)
 #define IO_SPACE_PORT(port)             ((port) & (IO_SPACE_SIZE - 1))
 
-#define IO_SPACE_SPARSE_ENCODING(p)     ((((p) >> 2) << 12) | (p & 0xfff))
+#define IO_SPACE_SPARSE_ENCODING(p)     ((((p) >> 2) << 12) | ((p) & 0xfff))
 
 struct io_space {
         unsigned long mmio_base;        /* base in MMIO space */
@@ -120,14 +120,6 @@ static inline void ___ia64_mmiowb(void)
         ia64_mfa();
 }
 
-static inline const unsigned long
-__ia64_get_io_port_base (void)
-{
-        extern unsigned long ia64_iobase;
-
-        return ia64_iobase;
-}
-
 static inline void*
 __ia64_mk_io_addr (unsigned long port)
 {
diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h
index 38a7a72791cc..a429fe225b07 100644
--- a/include/asm-ia64/iosapic.h
+++ b/include/asm-ia64/iosapic.h
@@ -71,8 +71,13 @@ static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
 }
 
 extern void __init iosapic_system_init (int pcat_compat);
-extern void __init iosapic_init (unsigned long address,
+extern int __devinit iosapic_init (unsigned long address,
                                     unsigned int gsi_base);
+#ifdef CONFIG_HOTPLUG
+extern int iosapic_remove (unsigned int gsi_base);
+#else
+#define iosapic_remove(gsi_base)                                (-EINVAL)
+#endif /* CONFIG_HOTPLUG */
 extern int gsi_to_vector (unsigned int gsi);
 extern int gsi_to_irq (unsigned int gsi);
 extern void iosapic_enable_intr (unsigned int vector);
@@ -94,11 +99,12 @@ extern unsigned int iosapic_version (char __iomem *addr);
 
 extern void iosapic_pci_fixup (int);
 #ifdef CONFIG_NUMA
-extern void __init map_iosapic_to_node (unsigned int, int);
+extern void __devinit map_iosapic_to_node (unsigned int, int);
 #endif
 #else
 #define iosapic_system_init(pcat_compat)                        do { } while (0)
-#define iosapic_init(address,gsi_base)                          do { } while (0)
+#define iosapic_init(address,gsi_base)                          (-EINVAL)
+#define iosapic_remove(gsi_base)                                (-ENODEV)
 #define iosapic_register_intr(gsi,polarity,trigger)             (gsi)
 #define iosapic_unregister_intr(irq)                            do { } while (0)
 #define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger)  do { } while (0)
diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h
index bd07d11d9f37..cd984d08fd15 100644
--- a/include/asm-ia64/irq.h
+++ b/include/asm-ia64/irq.h
@@ -14,6 +14,11 @@
 #define NR_IRQS         256
 #define NR_IRQ_VECTORS  NR_IRQS
 
+/*
+ * IRQ line status macro IRQ_PER_CPU is used
+ */
+#define ARCH_HAS_IRQ_PER_CPU
+
 static __inline__ int
 irq_canonicalize (int irq)
 {
@@ -30,12 +35,6 @@ extern void disable_irq_nosync (unsigned int);
 extern void enable_irq (unsigned int);
 extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
 
-#ifdef CONFIG_SMP
-extern void move_irq(int irq);
-#else
-#define move_irq(irq)
-#endif
-
 struct irqaction;
 struct pt_regs;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
diff --git a/include/asm-ia64/kdebug.h b/include/asm-ia64/kdebug.h
new file mode 100644
index 000000000000..4d376e1663f7
--- /dev/null
+++ b/include/asm-ia64/kdebug.h
@@ -0,0 +1,61 @@
+#ifndef _IA64_KDEBUG_H
+#define _IA64_KDEBUG_H 1
+/*
+ * include/asm-ia64/kdebug.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) Intel Corporation, 2005
+ *
+ * 2005-Apr     Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
+ *              <anil.s.keshavamurthy@intel.com> adopted from
+ *              include/asm-x86_64/kdebug.h
+ */
+#include <linux/notifier.h>
+
+struct pt_regs;
+
+struct die_args {
+        struct pt_regs *regs;
+        const char *str;
+        long err;
+        int trapnr;
+        int signr;
+};
+
+int register_die_notifier(struct notifier_block *nb);
+extern struct notifier_block *ia64die_chain;
+
+enum die_val {
+        DIE_BREAK = 1,
+        DIE_SS,
+        DIE_PAGE_FAULT,
+};
+
+static inline int notify_die(enum die_val val, char *str, struct pt_regs *regs,
+                             long err, int trap, int sig)
+{
+        struct die_args args = {
+                .regs   = regs,
+                .str    = str,
+                .err    = err,
+                .trapnr = trap,
+                .signr  = sig
+        };
+
+        return notifier_call_chain(&ia64die_chain, val, &args);
+}
+
+#endif
diff --git a/include/asm-ia64/kprobes.h b/include/asm-ia64/kprobes.h
new file mode 100644
index 000000000000..573a3574a24f
--- /dev/null
+++ b/include/asm-ia64/kprobes.h
@@ -0,0 +1,121 @@
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-ia64/kprobes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ * Copyright (C) Intel Corporation, 2005
+ *
+ * 2005-Apr     Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
+ *              <anil.s.keshavamurthy@intel.com> adapted from i386
+ */
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <asm/break.h>
+
+#define MAX_INSN_SIZE   16
+#define BREAK_INST      (long)(__IA64_BREAK_KPROBE << 6)
+
+typedef union cmp_inst {
+        struct {
+        unsigned long long qp : 6;
+        unsigned long long p1 : 6;
+        unsigned long long c  : 1;
+        unsigned long long r2 : 7;
+        unsigned long long r3 : 7;
+        unsigned long long p2 : 6;
+        unsigned long long ta : 1;
+        unsigned long long x2 : 2;
+        unsigned long long tb : 1;
+        unsigned long long opcode : 4;
+        unsigned long long reserved : 23;
+        }f;
+        unsigned long long l;
+} cmp_inst_t;
+
+struct kprobe;
+
+typedef struct _bundle {
+        struct {
+                unsigned long long template : 5;
+                unsigned long long slot0 : 41;
+                unsigned long long slot1_p0 : 64-46;
+        } quad0;
+        struct {
+                unsigned long long slot1_p1 : 41 - (64-46);
+                unsigned long long slot2 : 41;
+        } quad1;
+} __attribute__((__aligned__(16)))  bundle_t;
+
+#define JPROBE_ENTRY(pentry)    (kprobe_opcode_t *)pentry
+
+#define ARCH_SUPPORTS_KRETPROBES
+
+#define SLOT0_OPCODE_SHIFT      (37)
+#define SLOT1_p1_OPCODE_SHIFT   (37 - (64-46))
+#define SLOT2_OPCODE_SHIFT      (37)
+
+#define INDIRECT_CALL_OPCODE            (1)
+#define IP_RELATIVE_CALL_OPCODE         (5)
+#define IP_RELATIVE_BRANCH_OPCODE       (4)
+#define IP_RELATIVE_PREDICT_OPCODE      (7)
+#define LONG_BRANCH_OPCODE              (0xC)
+#define LONG_CALL_OPCODE                (0xD)
+
+typedef struct kprobe_opcode {
+        bundle_t bundle;
+} kprobe_opcode_t;
+
+struct fnptr {
+        unsigned long ip;
+        unsigned long gp;
+};
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the instruction to be emulated */
+        kprobe_opcode_t insn;
+ #define INST_FLAG_FIX_RELATIVE_IP_ADDR         1
+ #define INST_FLAG_FIX_BRANCH_REG               2
+ #define INST_FLAG_BREAK_INST                   4
+        unsigned long inst_flag;
+        unsigned short target_br_reg;
+};
+
+/* ia64 does not need this */
+static inline void arch_copy_kprobe(struct kprobe *p)
+{
+}
+
+#ifdef CONFIG_KPROBES
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+/* ia64 does not need this */
+static inline void jprobe_return(void)
+{
+}
+
+#else                           /* !CONFIG_KPROBES */
+static inline int kprobe_exceptions_notify(struct notifier_block *self,
+                                           unsigned long val, void *data)
+{
+        return 0;
+}
+#endif
+#endif                          /* _ASM_KPROBES_H */
diff --git a/include/asm-ia64/mmu.h b/include/asm-ia64/mmu.h
index ae1525352a25..611432ba579c 100644
--- a/include/asm-ia64/mmu.h
+++ b/include/asm-ia64/mmu.h
@@ -2,10 +2,12 @@
 #define __MMU_H
 
 /*
- * Type for a context number.  We declare it volatile to ensure proper ordering when it's
- * accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and
- * init_new_context()).
+ * Type for a context number.  We declare it volatile to ensure proper
+ * ordering when it's accessed outside of spinlock'd critical sections
+ * (e.g., as done in activate_mm() and init_new_context()).
  */
 typedef volatile unsigned long mm_context_t;
 
+typedef unsigned long nv_mm_context_t;
+
 #endif
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index 0096e7e05012..8d6e72f7b08e 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -19,6 +19,7 @@
 
 #define ia64_rid(ctx,addr)      (((ctx) << 3) | (addr >> 61))
 
+# include <asm/page.h>
 # ifndef __ASSEMBLY__
 
 #include <linux/compiler.h>
@@ -55,34 +56,46 @@ static inline void
 delayed_tlb_flush (void)
 {
         extern void local_flush_tlb_all (void);
+        unsigned long flags;
 
         if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
-                local_flush_tlb_all();
-                __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
+                spin_lock_irqsave(&ia64_ctx.lock, flags);
+                {
+                        if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
+                                local_flush_tlb_all();
+                                __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
+                        }
+                }
+                spin_unlock_irqrestore(&ia64_ctx.lock, flags);
         }
 }
 
-static inline mm_context_t
+static inline nv_mm_context_t
 get_mmu_context (struct mm_struct *mm)
 {
         unsigned long flags;
-        mm_context_t context = mm->context;
-
-        if (context)
-                return context;
-
-        spin_lock_irqsave(&ia64_ctx.lock, flags);
-        {
-                /* re-check, now that we've got the lock: */
-                context = mm->context;
-                if (context == 0) {
-                        cpus_clear(mm->cpu_vm_mask);
-                        if (ia64_ctx.next >= ia64_ctx.limit)
-                                wrap_mmu_context(mm);
-                        mm->context = context = ia64_ctx.next++;
+        nv_mm_context_t context = mm->context;
+
+        if (unlikely(!context)) {
+                spin_lock_irqsave(&ia64_ctx.lock, flags);
+                {
+                        /* re-check, now that we've got the lock: */
+                        context = mm->context;
+                        if (context == 0) {
+                                cpus_clear(mm->cpu_vm_mask);
+                                if (ia64_ctx.next >= ia64_ctx.limit)
+                                        wrap_mmu_context(mm);
+                                mm->context = context = ia64_ctx.next++;
+                        }
                 }
+                spin_unlock_irqrestore(&ia64_ctx.lock, flags);
         }
-        spin_unlock_irqrestore(&ia64_ctx.lock, flags);
+        /*
+         * Ensure we're not starting to use "context" before any old
+         * uses of it are gone from our TLB.
+         */
+        delayed_tlb_flush();
+
         return context;
 }
 
@@ -104,13 +117,13 @@ destroy_context (struct mm_struct *mm)
 }
 
 static inline void
-reload_context (mm_context_t context)
+reload_context (nv_mm_context_t context)
 {
         unsigned long rid;
         unsigned long rid_incr = 0;
         unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
 
-        old_rr4 = ia64_get_rr(0x8000000000000000UL);
+        old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
         rid = context << 3;     /* make space for encoding the region number */
         rid_incr = 1 << 8;
 
@@ -122,6 +135,10 @@ reload_context (mm_context_t context)
         rr4 = rr0 + 4*rid_incr;
 #ifdef  CONFIG_HUGETLB_PAGE
         rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
+
+#  if RGN_HPAGE != 4
+#    error "reload_context assumes RGN_HPAGE is 4"
+#  endif
 #endif
 
         ia64_set_rr(0x0000000000000000UL, rr0);
@@ -132,10 +149,13 @@ reload_context (mm_context_t context)
         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 }
 
+/*
+ * Must be called with preemption off
+ */
 static inline void
 activate_context (struct mm_struct *mm)
 {
-        mm_context_t context;
+        nv_mm_context_t context;
 
         do {
                 context = get_mmu_context(mm);
@@ -154,8 +174,6 @@ activate_context (struct mm_struct *mm)
 static inline void
 activate_mm (struct mm_struct *prev, struct mm_struct *next)
 {
-        delayed_tlb_flush();
-
         /*
          * We may get interrupts here, but that's OK because interrupt handlers cannot
          * touch user-space.
diff --git a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h
index 9491dacc89cf..d32f51e3d6c2 100644
--- a/include/asm-ia64/mmzone.h
+++ b/include/asm-ia64/mmzone.h
@@ -17,6 +17,20 @@
 
 #ifdef CONFIG_DISCONTIGMEM
 
+static inline int pfn_to_nid(unsigned long pfn)
+{
+#ifdef CONFIG_NUMA
+        extern int paddr_to_nid(unsigned long);
+        int nid = paddr_to_nid(pfn << PAGE_SHIFT);
+        if (nid < 0)
+                return 0;
+        else
+                return nid;
+#else
+        return 0;
+#endif
+}
+
 #ifdef CONFIG_IA64_DIG /* DIG systems are small */
 # define MAX_PHYSNODE_ID        8
 # define NR_NODE_MEMBLKS        (MAX_NUMNODES * 8)
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 08894f73abf0..9edffad8c28b 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -13,6 +13,19 @@
 #include <asm/types.h>
 
 /*
+ * The top three bits of an IA64 address are its Region Number.
+ * Different regions are assigned to different purposes.
+ */
+#define RGN_SHIFT       (61)
+#define RGN_BASE(r)     (__IA64_UL_CONST(r)<<RGN_SHIFT)
+#define RGN_BITS        (RGN_BASE(-1))
+
+#define RGN_KERNEL      7       /* Identity mapped region */
+#define RGN_UNCACHED    6       /* Identity mapped I/O region */
+#define RGN_GATE        5       /* Gate page, Kernel text, etc */
+#define RGN_HPAGE       4       /* For Huge TLB pages */
+
+/*
  * PAGE_SHIFT determines the actual kernel page size.
  */
 #if defined(CONFIG_IA64_PAGE_SIZE_4KB)
@@ -36,10 +49,9 @@
 
 #define RGN_MAP_LIMIT   ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE)      /* per region addr limit */
 
+
 #ifdef CONFIG_HUGETLB_PAGE
-# define REGION_HPAGE           (4UL)   /* note: this is hardcoded in reload_context()!*/
-# define REGION_SHIFT           61
-# define HPAGE_REGION_BASE      (REGION_HPAGE << REGION_SHIFT)
+# define HPAGE_REGION_BASE      RGN_BASE(RGN_HPAGE)
 # define HPAGE_SHIFT            hpage_shift
 # define HPAGE_SHIFT_DEFAULT    28      /* check ia64 SDM for architecture supported size */
 # define HPAGE_SIZE             (__IA64_UL_CONST(1) << HPAGE_SHIFT)
@@ -130,16 +142,13 @@ typedef union ia64_va {
 #define REGION_NUMBER(x)        ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
 #define REGION_OFFSET(x)        ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
 
-#define REGION_SIZE             REGION_NUMBER(1)
-#define REGION_KERNEL           7
-
 #ifdef CONFIG_HUGETLB_PAGE
 # define htlbpage_to_page(x)    (((unsigned long) REGION_NUMBER(x) << 61)                       \
                                  | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
 # define HUGETLB_PAGE_ORDER     (HPAGE_SHIFT - PAGE_SHIFT)
 # define is_hugepage_only_range(mm, addr, len)          \
-         (REGION_NUMBER(addr) == REGION_HPAGE &&        \
-          REGION_NUMBER((addr)+(len)-1) == REGION_HPAGE)
+         (REGION_NUMBER(addr) == RGN_HPAGE &&   \
+          REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE)
 extern unsigned int hpage_shift;
 #endif
 
@@ -197,7 +206,7 @@ get_order (unsigned long size)
 # define __pgprot(x)    (x)
 #endif /* !STRICT_MM_TYPECHECKS */
 
-#define PAGE_OFFSET                     __IA64_UL_CONST(0xe000000000000000)
+#define PAGE_OFFSET                     RGN_BASE(RGN_KERNEL)
 
 #define VM_DATA_DEFAULT_FLAGS           (VM_READ | VM_WRITE |                                   \
                                          VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC |                \
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 2303a10ee595..e828377ad295 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -75,6 +75,8 @@
 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
 #define PAL_VM_TR_READ          261     /* read contents of translation register */
+#define PAL_GET_PSTATE          262     /* get the current P-state */
+#define PAL_SET_PSTATE          263     /* set the P-state */
 
 #ifndef __ASSEMBLY__
 
@@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
         return iprv.status;
 }
 
+/* Get the current P-state information */
+static inline s64
+ia64_pal_get_pstate (u64 *pstate_index)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
+        *pstate_index = iprv.v0;
+        return iprv.status;
+}
+
+/* Set the P-state */
+static inline s64
+ia64_pal_set_pstate (u64 pstate_index)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
+        return iprv.status;
+}
+
 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
  * suspended, but cache and TLB coherency is maintained.
  */
diff --git a/include/asm-ia64/param.h b/include/asm-ia64/param.h
index 6c6b679b7a9e..5e1e0d2d7baf 100644
--- a/include/asm-ia64/param.h
+++ b/include/asm-ia64/param.h
@@ -27,7 +27,7 @@
    */
 #  define HZ      32
 # else
-#  define HZ    1024
+#  define HZ    CONFIG_HZ
 # endif
 # define USER_HZ        HZ
 # define CLOCKS_PER_SEC HZ      /* frequency at which times() counts */
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index a8314ee4e7d2..dba9f220be71 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -47,7 +47,7 @@ pcibios_set_master (struct pci_dev *dev)
 }
 
 static inline void
-pcibios_penalize_isa_irq (int irq)
+pcibios_penalize_isa_irq (int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -82,6 +82,25 @@ extern int pcibios_prep_mwi (struct pci_dev *);
 #define sg_dma_len(sg)          ((sg)->dma_length)
 #define sg_dma_address(sg)      ((sg)->dma_address)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
 #define HAVE_PCI_MMAP
 extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
                                 enum pci_mmap_state mmap_state, int write_combine);
@@ -109,6 +128,7 @@ struct pci_controller {
         void *acpi_handle;
         void *iommu;
         int segment;
+        int node;               /* nearest node with memory or -1 for global allocation */
 
         unsigned int windows;
         struct pci_window *window;
diff --git a/include/asm-ia64/percpu.h b/include/asm-ia64/percpu.h
index 1e87f19dad56..2b14dee29ce7 100644
--- a/include/asm-ia64/percpu.h
+++ b/include/asm-ia64/percpu.h
@@ -50,7 +50,7 @@ extern void *per_cpu_init(void);
 
 #else /* ! SMP */
 
-#define per_cpu(var, cpu)                       (*((void)cpu, &per_cpu__##var))
+#define per_cpu(var, cpu)                       (*((void)(cpu), &per_cpu__##var))
 #define __get_cpu_var(var)                      per_cpu__##var
 #define per_cpu_init()                          (__phys_per_cpu_start)
 
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index fcc9c3344ab4..2e34c06e6777 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -204,21 +204,18 @@ ia64_phys_addr_valid (unsigned long addr)
 #define set_pte(ptep, pteval)   (*(ptep) = (pteval))
 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 
-#define RGN_SIZE        (1UL << 61)
-#define RGN_KERNEL      7
-
-#define VMALLOC_START           0xa000000200000000UL
+#define VMALLOC_START           (RGN_BASE(RGN_GATE) + 0x200000000UL)
 #ifdef CONFIG_VIRTUAL_MEM_MAP
-# define VMALLOC_END_INIT       (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
+# define VMALLOC_END_INIT       (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 # define VMALLOC_END            vmalloc_end
   extern unsigned long vmalloc_end;
 #else
-# define VMALLOC_END            (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
+# define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
 #endif
 
 /* fs/proc/kcore.c */
-#define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
-#define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
+#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
+#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
 
 /*
  * Conversion functions: convert page frame number (pfn) and a protection value to a page
@@ -283,6 +280,7 @@ ia64_phys_addr_valid (unsigned long addr)
 #define pte_mkyoung(pte)        (__pte(pte_val(pte) | _PAGE_A))
 #define pte_mkclean(pte)        (__pte(pte_val(pte) & ~_PAGE_D))
 #define pte_mkdirty(pte)        (__pte(pte_val(pte) | _PAGE_D))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) | _PAGE_P))
 
 /*
  * Macro to a page protection value as "uncacheable".  Note that "protection" is really a
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 91bbd1f22461..94e07e727395 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -20,9 +20,6 @@
 #include <asm/ptrace.h>
 #include <asm/ustack.h>
 
-/* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
-#define ARCH_HAS_SCHED_DOMAIN
-
 #define IA64_NUM_DBG_REGS       8
 /*
  * Limits for PMC and PMD are set to less than maximum architected values
diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h
index 6ece5061dc19..e18b5ab0cb75 100644
--- a/include/asm-ia64/rwsem.h
+++ b/include/asm-ia64/rwsem.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com>
  * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 2005 Christoph Lameter <clameter@sgi.com>
  *
  * Based on asm-i386/rwsem.h and other architecture implementation.
  *
@@ -11,9 +12,9 @@
  *
  * The lock count is initialized to 0 (no active and no waiting lockers).
  *
- * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case
- * of an uncontended lock. Readers increment by 1 and see a positive value
- * when uncontended, negative if there are writers (and maybe) readers
+ * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for
+ * the case of an uncontended lock. Readers increment by 1 and see a positive
+ * value when uncontended, negative if there are writers (and maybe) readers
  * waiting (in which case it goes to sleep).
  */
 
@@ -29,7 +30,7 @@
  * the semaphore definition
  */
 struct rw_semaphore {
-        signed int              count;
+        signed long             count;
         spinlock_t              wait_lock;
         struct list_head        wait_list;
 #if RWSEM_DEBUG
@@ -37,10 +38,10 @@ struct rw_semaphore {
 #endif
 };
 
-#define RWSEM_UNLOCKED_VALUE            0x00000000
-#define RWSEM_ACTIVE_BIAS               0x00000001
-#define RWSEM_ACTIVE_MASK               0x0000ffff
-#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_UNLOCKED_VALUE            __IA64_UL_CONST(0x0000000000000000)
+#define RWSEM_ACTIVE_BIAS               __IA64_UL_CONST(0x0000000000000001)
+#define RWSEM_ACTIVE_MASK               __IA64_UL_CONST(0x00000000ffffffff)
+#define RWSEM_WAITING_BIAS              -__IA64_UL_CONST(0x0000000100000000)
 #define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
 
@@ -83,7 +84,7 @@ init_rwsem (struct rw_semaphore *sem)
 static inline void
 __down_read (struct rw_semaphore *sem)
 {
-        int result = ia64_fetchadd4_acq((unsigned int *)&sem->count, 1);
+        long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1);
 
         if (result < 0)
                 rwsem_down_read_failed(sem);
@@ -95,7 +96,7 @@ __down_read (struct rw_semaphore *sem)
 static inline void
 __down_write (struct rw_semaphore *sem)
 {
-        int old, new;
+        long old, new;
 
         do {
                 old = sem->count;
@@ -112,7 +113,7 @@ __down_write (struct rw_semaphore *sem)
 static inline void
 __up_read (struct rw_semaphore *sem)
 {
-        int result = ia64_fetchadd4_rel((unsigned int *)&sem->count, -1);
+        long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1);
 
         if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0)
                 rwsem_wake(sem);
@@ -124,7 +125,7 @@ __up_read (struct rw_semaphore *sem)
 static inline void
 __up_write (struct rw_semaphore *sem)
 {
-        int old, new;
+        long old, new;
 
         do {
                 old = sem->count;
@@ -141,7 +142,7 @@ __up_write (struct rw_semaphore *sem)
 static inline int
 __down_read_trylock (struct rw_semaphore *sem)
 {
-        int tmp;
+        long tmp;
         while ((tmp = sem->count) >= 0) {
                 if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) {
                         return 1;
@@ -156,7 +157,7 @@ __down_read_trylock (struct rw_semaphore *sem)
 static inline int
 __down_write_trylock (struct rw_semaphore *sem)
 {
-        int tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
+        long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
                               RWSEM_ACTIVE_WRITE_BIAS);
         return tmp == RWSEM_UNLOCKED_VALUE;
 }
@@ -167,7 +168,7 @@ __down_write_trylock (struct rw_semaphore *sem)
 static inline void
 __downgrade_write (struct rw_semaphore *sem)
 {
-        int old, new;
+        long old, new;
 
         do {
                 old = sem->count;
@@ -182,7 +183,7 @@ __downgrade_write (struct rw_semaphore *sem)
  * Implement atomic add functionality.  These used to be "inline" functions, but GCC v3.1
  * doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd.
  */
-#define rwsem_atomic_add(delta, sem)    atomic_add(delta, (atomic_t *)(&(sem)->count))
-#define rwsem_atomic_update(delta, sem) atomic_add_return(delta, (atomic_t *)(&(sem)->count))
+#define rwsem_atomic_add(delta, sem)    atomic64_add(delta, (atomic64_t *)(&(sem)->count))
+#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
 
 #endif /* _ASM_IA64_RWSEM_H */
diff --git a/include/asm-ia64/sections.h b/include/asm-ia64/sections.h
index 8e3dbde1b429..e9eb7f62d32b 100644
--- a/include/asm-ia64/sections.h
+++ b/include/asm-ia64/sections.h
@@ -17,6 +17,7 @@ extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[];
 extern char __start_gate_fsyscall_patchlist[], __end_gate_fsyscall_patchlist[];
 extern char __start_gate_brl_fsys_bubble_down_patchlist[], __end_gate_brl_fsys_bubble_down_patchlist[];
 extern char __start_unwind[], __end_unwind[];
+extern char __start_ivt_text[], __end_ivt_text[];
 
 #endif /* _ASM_IA64_SECTIONS_H */
 
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
index 3ba1a061e4ae..a3914352c995 100644
--- a/include/asm-ia64/smp.h
+++ b/include/asm-ia64/smp.h
@@ -46,7 +46,7 @@ ia64_get_lid (void)
 #define SMP_IRQ_REDIRECTION     (1 << 0)
 #define SMP_IPI_REDIRECTION     (1 << 1)
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
 
 extern struct smp_boot_data {
         int cpu_count;
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 1bfdfb4d7b01..2c32e4b77b54 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_IA64_SN_ADDRS_H
@@ -65,7 +65,6 @@
 
 #define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
 #define AS_MASK                 ((u64)AS_BITMASK << AS_SHIFT)
-#define REGION_BITS             0xe000000000000000UL
 
 
 /*
@@ -79,38 +78,30 @@
 #define AS_CAC_SPACE            (AS_CAC_VAL << AS_SHIFT)
 
 
-/*
- * Base addresses for various address ranges.
- */
-#define CACHED                  0xe000000000000000UL
-#define UNCACHED                0xc000000000000000UL
-#define UNCACHED_PHYS           0x8000000000000000UL
-
-
 /* 
  * Virtual Mode Local & Global MMR space.  
  */
 #define SH1_LOCAL_MMR_OFFSET    0x8000000000UL
 #define SH2_LOCAL_MMR_OFFSET    0x0200000000UL
 #define LOCAL_MMR_OFFSET        (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
-#define LOCAL_MMR_SPACE         (UNCACHED | LOCAL_MMR_OFFSET)
-#define LOCAL_PHYS_MMR_SPACE    (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
+#define LOCAL_MMR_SPACE         (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
+#define LOCAL_PHYS_MMR_SPACE    (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
 
 #define SH1_GLOBAL_MMR_OFFSET   0x0800000000UL
 #define SH2_GLOBAL_MMR_OFFSET   0x0300000000UL
 #define GLOBAL_MMR_OFFSET       (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
-#define GLOBAL_MMR_SPACE        (UNCACHED | GLOBAL_MMR_OFFSET)
+#define GLOBAL_MMR_SPACE        (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
 
 /*
  * Physical mode addresses
  */
-#define GLOBAL_PHYS_MMR_SPACE   (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
+#define GLOBAL_PHYS_MMR_SPACE   (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
 
 
 /*
  * Clear region & AS bits.
  */
-#define TO_PHYS_MASK            (~(REGION_BITS | AS_MASK))
+#define TO_PHYS_MASK            (~(RGN_BITS | AS_MASK))
 
 
 /*
@@ -126,6 +117,7 @@
 #define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
 #define GLOBAL_CAC_ADDR(n,a)    (CAC_BASE | REMOTE_ADDR(n,a))
 #define CHANGE_NASID(n,x)       ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
+#define IS_TIO_NASID(n)         ((n) & 1)
 
 
 /* non-II mmr's start at top of big window space (4G) */
@@ -134,10 +126,10 @@
 /*
  * general address defines
  */
-#define CAC_BASE                (CACHED   | AS_CAC_SPACE)
-#define AMO_BASE                (UNCACHED | AS_AMO_SPACE)
-#define AMO_PHYS_BASE           (UNCACHED_PHYS | AS_AMO_SPACE)
-#define GET_BASE                (CACHED   | AS_GET_SPACE)
+#define CAC_BASE                (PAGE_OFFSET | AS_CAC_SPACE)
+#define AMO_BASE                (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
+#define AMO_PHYS_BASE           (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
+#define GET_BASE                (PAGE_OFFSET | AS_GET_SPACE)
 
 /*
  * Convert Memory addresses between various addressing modes.
@@ -155,17 +147,35 @@
  *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
  *           to insert a chiplet id into this macro.  However, it is our belief
  *           right now that this chiplet id will be ICE, which is also zero.
- *           Nasid starts on bit 40.
  */
-#define PHYS_TO_TIODMA(x)       ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
-#define PHYS_TO_DMA(x)          ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
+#define SH1_TIO_PHYS_TO_DMA(x)                                          \
+        ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
+
+#define SH2_NETWORK_BANK_OFFSET(x)                                      \
+        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
+
+#define SH2_NETWORK_BANK_SELECT(x)                                      \
+        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))        \
+                >> (sn_hub_info->nasid_shift - 4)) << 36)
+
+#define SH2_NETWORK_ADDRESS(x)                                          \
+        (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
+
+#define SH2_TIO_PHYS_TO_DMA(x)                                          \
+        (((u64)(NASID_GET(x)) << 40) |  SH2_NETWORK_ADDRESS(x))
+
+#define PHYS_TO_TIODMA(x)                                               \
+        (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
+
+#define PHYS_TO_DMA(x)                                                  \
+        ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
 
 
 /*
  * Macros to test for address type.
  */
-#define IS_AMO_ADDRESS(x)       (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
-#define IS_AMO_PHYS_ADDRESS(x)  (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
+#define IS_AMO_ADDRESS(x)       (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
+#define IS_AMO_PHYS_ADDRESS(x)  (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
 
 
 /*
@@ -180,18 +190,20 @@
 #define TIO_SWIN_BASE(n, w)             (TIO_IO_BASE(n) + \
                                             ((u64) (w) << TIO_SWIN_SIZE_BITS))
 #define NODE_IO_BASE(n)                 (GLOBAL_MMR_SPACE | NASID_SPACE(n))
-#define TIO_IO_BASE(n)                  (UNCACHED | NASID_SPACE(n))
+#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
 #define BWIN_SIZE                       (1UL << BWIN_SIZE_BITS)
 #define NODE_BWIN_BASE0(n)              (NODE_IO_BASE(n) + BWIN_SIZE)
 #define NODE_BWIN_BASE(n, w)            (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
 #define RAW_NODE_SWIN_BASE(n, w)        (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
 #define BWIN_WIDGET_MASK                0x7
 #define BWIN_WINDOWNUM(x)               (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+#define SH1_IS_BIG_WINDOW_ADDR(x)       ((x) & BWIN_TOP)
 
 #define TIO_BWIN_WINDOW_SELECT_MASK     0x7
 #define TIO_BWIN_WINDOWNUM(x)           (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
 
-
+#define TIO_HWIN_SHIFT_BITS             33
+#define TIO_HWIN(x)                     (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
 
 /*
  * The following definitions pertain to the IO special address
@@ -230,14 +242,39 @@
  *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *      They're always safe.
  */
-#define REMOTE_HUB_ADDR(n,x)                                            \
-        ((n & 1) ?                                                      \
-        /* TIO: */                                                      \
-        ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))                        \
-        : /* SHUB: */                                                   \
-        (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\
-        : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
+/* Shub1 TIO & MMR addressing macros */
+#define SH1_TIO_IOSPACE_ADDR(n,x)                                       \
+        GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_BWIN_MMR(n,x)                                        \
+        GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_SWIN_MMR(n,x)                                        \
+        (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
+
+#define SH1_REMOTE_MMR(n,x)                                             \
+        (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :         \
+                SH1_REMOTE_SWIN_MMR(n,x))
+
+/* Shub1 TIO & MMR addressing macros */
+#define SH2_TIO_IOSPACE_ADDR(n,x)                                       \
+        ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
 
+#define SH2_REMOTE_MMR(n,x)                                             \
+        GLOBAL_MMR_ADDR(n,x)
+
+
+/* TIO & MMR addressing macros that work on both shub1 & shub2 */
+#define TIO_IOSPACE_ADDR(n,x)                                           \
+        ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :               \
+                 SH2_TIO_IOSPACE_ADDR(n,x)))
+
+#define SH_REMOTE_MMR(n,x)                                              \
+        (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
+
+#define REMOTE_HUB_ADDR(n,x)                                            \
+        (IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :    \
+         ((volatile u64*)SH_REMOTE_MMR(n,x)))
 
 
 #define HUB_L(x)                        (*((volatile typeof(*x) *)x))
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index 635fdce854a8..ab827d298569 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -11,6 +11,7 @@
 #ifndef _ASM_IA64_SN_ARCH_H
 #define _ASM_IA64_SN_ARCH_H
 
+#include <linux/numa.h>
 #include <asm/types.h>
 #include <asm/percpu.h>
 #include <asm/sn/types.h>
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
index 84b254603b8d..f083c9434066 100644
--- a/include/asm-ia64/sn/geo.h
+++ b/include/asm-ia64/sn/geo.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_IA64_SN_GEO_H
@@ -108,7 +108,6 @@ typedef union geoid_u {
 #define INVALID_SLAB            (slabid_t)-1
 #define INVALID_SLOT            (slotid_t)-1
 #define INVALID_MODULE          ((moduleid_t)-1)
-#define INVALID_PARTID          ((partid_t)-1)
 
 static inline slabid_t geo_slab(geoid_t g)
 {
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index e51471fb0867..e35074f526d9 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -9,14 +9,15 @@
 #ifndef _ASM_IA64_SN_INTR_H
 #define _ASM_IA64_SN_INTR_H
 
+#include <linux/rcupdate.h>
+
 #define SGI_UART_VECTOR         (0xe9)
-#define SGI_PCIBR_ERROR         (0x33)
 
 /* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
 #define SGI_XPC_ACTIVATE                (0x30)
 #define SGI_II_ERROR                    (0x31)
 #define SGI_XBOW_ERROR                  (0x32)
-#define SGI_PCIBR_ERROR                 (0x33)
+#define SGI_PCIASIC_ERROR               (0x33)
 #define SGI_ACPI_SCI_INT                (0x34)
 #define SGI_TIOCA_ERROR                 (0x35)
 #define SGI_TIO_ERROR                   (0x36)
@@ -33,7 +34,7 @@
 
 // The SN PROM irq struct
 struct sn_irq_info {
-        struct sn_irq_info *irq_next;   /* sharing irq list          */
+        struct sn_irq_info *irq_next;   /* deprecated DO NOT USE     */
         short           irq_nasid;      /* Nasid IRQ is assigned to  */
         int             irq_slice;      /* slice IRQ is assigned to  */
         int             irq_cpuid;      /* kernel logical cpuid      */
@@ -47,6 +48,8 @@ struct sn_irq_info {
         int             irq_cookie;     /* unique cookie             */
         int             irq_flags;      /* flags */
         int             irq_share_cnt;  /* num devices sharing IRQ   */
+        struct list_head        list;   /* list of sn_irq_info structs */
+        struct rcu_head         rcu;    /* rcu callback list */
 };
 
 extern void sn_send_IPI_phys(int, long, int, int);
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 08050d37b662..2e5f0aa38889 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -33,5 +33,6 @@
 #define L1_BRICKTYPE_PA         0x6a            /* j */
 #define L1_BRICKTYPE_IA         0x6b            /* k */
 #define L1_BRICKTYPE_ATHENA     0x2b            /* + */
+#define L1_BRICKTYPE_DAYTONA    0x7a            /* z */
 
 #endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/mspec.h b/include/asm-ia64/sn/mspec.h
new file mode 100644
index 000000000000..dbe13c6121a8
--- /dev/null
+++ b/include/asm-ia64/sn/mspec.h
@@ -0,0 +1,59 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_MSPEC_H
+#define _ASM_IA64_SN_MSPEC_H
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD            0
+#define FETCHOP_INCREMENT       8
+#define FETCHOP_DECREMENT       16
+#define FETCHOP_CLEAR           24
+
+#define FETCHOP_STORE           0
+#define FETCHOP_AND             24
+#define FETCHOP_OR              32
+
+#define FETCHOP_CLEAR_CACHE     56
+
+#define FETCHOP_LOAD_OP(addr, op) ( \
+         *(volatile long *)((char*) (addr) + (op)))
+
+#define FETCHOP_STORE_OP(addr, op, x) ( \
+         *(volatile long *)((char*) (addr) + (op)) = (long) (x))
+
+#ifdef __KERNEL__
+
+/*
+ * Each Atomic Memory Operation (AMO formerly known as fetchop)
+ * variable is 64 bytes long.  The first 8 bytes are used.  The
+ * remaining 56 bytes are unaddressable due to the operation taking
+ * that portion of the address.
+ *
+ * NOTE: The AMO_t _MUST_ be placed in either the first or second half
+ * of the cache line.  The cache line _MUST NOT_ be used for anything
+ * other than additional AMO_t entries.  This is because there are two
+ * addresses which reference the same physical cache line.  One will
+ * be a cached entry with the memory type bits all set.  This address
+ * may be loaded into processor cache.  The AMO_t will be referenced
+ * uncached via the memory special memory type.  If any portion of the
+ * cached cache-line is modified, when that line is flushed, it will
+ * overwrite the uncached value in physical memory and lead to
+ * inconsistency.
+ */
+typedef struct {
+        u64 variable;
+        u64 unused[7];
+} AMO_t;
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 7138b1eafd6b..47bb8100fd00 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -37,7 +37,6 @@ struct phys_cpuid {
 
 struct nodepda_s {
         void            *pdinfo;        /* Platform-dependent per-node info */
-        spinlock_t              bist_lock;
 
         /*
          * The BTEs on this node are shared by the local cpus
@@ -55,6 +54,8 @@ struct nodepda_s {
          * Array of physical cpu identifiers. Indexed by cpuid.
          */
         struct phys_cpuid       phys_cpuid[NR_CPUS];
+        spinlock_t              ptc_lock ____cacheline_aligned_in_smp;
+        spinlock_t              bist_lock;
 };
 
 typedef struct nodepda_s nodepda_t;
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
new file mode 100644
index 000000000000..2b42d9ece26b
--- /dev/null
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -0,0 +1,159 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+
+#include <asm/sn/intr.h>
+#include <asm/sn/pcibus_provider_defs.h>
+
+/* Workarounds */
+#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
+
+#define BUSTYPE_MASK                    0x1
+
+/* Macros given a pcibus structure */
+#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
+#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
+                asic == PCIIO_ASIC_TYPE_TIOCP)
+#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
+
+
+/*
+ * The different PCI Bridge types supported on the SGI Altix platforms
+ */
+#define PCIBR_BRIDGETYPE_UNKNOWN       -1
+#define PCIBR_BRIDGETYPE_PIC            2
+#define PCIBR_BRIDGETYPE_TIOCP          3
+
+/*
+ * Bridge 64bit Direct Map Attributes
+ */
+#define PCI64_ATTR_PREF                 (1ull << 59)
+#define PCI64_ATTR_PREC                 (1ull << 58)
+#define PCI64_ATTR_VIRTUAL              (1ull << 57)
+#define PCI64_ATTR_BAR                  (1ull << 56)
+#define PCI64_ATTR_SWAP                 (1ull << 55)
+#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
+
+#define PCI32_LOCAL_BASE                0
+#define PCI32_MAPPED_BASE               0x40000000
+#define PCI32_DIRECT_BASE               0x80000000
+
+#define IS_PCI32_MAPPED(x)              ((uint64_t)(x) < PCI32_DIRECT_BASE && \
+                                         (uint64_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)              ((uint64_t)(x) >= PCI32_MAPPED_BASE)
+
+
+/*
+ * Bridge PMU Address Transaltion Entry Attibutes
+ */
+#define PCI32_ATE_V                     (0x1 << 0)
+#define PCI32_ATE_CO                    (0x1 << 1)
+#define PCI32_ATE_PREC                  (0x1 << 2)
+#define PCI32_ATE_PREF                  (0x1 << 3)
+#define PCI32_ATE_BAR                   (0x1 << 4)
+#define PCI32_ATE_ADDR_SHFT             12
+
+#define MINIMAL_ATES_REQUIRED(addr, size) \
+        (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
+
+#define MINIMAL_ATE_FLAG(addr, size) \
+        (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
+
+/* bit 29 of the pci address is the SWAP bit */
+#define ATE_SWAPSHIFT                   29
+#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
+#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
+
+/*
+ * I/O page size
+ */
+#if PAGE_SIZE < 16384
+#define IOPFNSHIFT                      12      /* 4K per mapped page */
+#else
+#define IOPFNSHIFT                      14      /* 16K per mapped page */
+#endif
+
+#define IOPGSIZE                        (1 << IOPFNSHIFT)
+#define IOPG(x)                         ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
+
+#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
+#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
+
+/*
+ * PMU resources.
+ */
+struct ate_resource{
+        uint64_t *ate;
+        uint64_t num_ate;
+        uint64_t lowest_free_index;
+};
+
+struct pcibus_info {
+        struct pcibus_bussoft   pbi_buscommon;   /* common header */
+        uint32_t                pbi_moduleid;
+        short                   pbi_bridge_type;
+        short                   pbi_bridge_mode;
+
+        struct ate_resource     pbi_int_ate_resource;
+        uint64_t                pbi_int_ate_size;
+
+        uint64_t                pbi_dir_xbase;
+        char                    pbi_hub_xid;
+
+        uint64_t                pbi_devreg[8];
+
+        uint32_t                pbi_valid_devices;
+        uint32_t                pbi_enabled_devices;
+
+        spinlock_t              pbi_lock;
+};
+
+/*
+ * pcibus_info structure locking macros
+ */
+inline static unsigned long
+pcibr_lock(struct pcibus_info *pcibus_info)
+{
+        unsigned long flag;
+        spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
+        return(flag);
+}
+#define pcibr_unlock(pcibus_info, flag)  spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
+
+extern int  pcibr_init_provider(void);
+extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
+extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t);
+extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t);
+extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
+
+/*
+ * prototypes for the bridge asic register access routines in pcibr_reg.c
+ */
+extern void             pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
+extern void             pcireg_control_bit_set(struct pcibus_info *, uint64_t);
+extern uint64_t         pcireg_tflush_get(struct pcibus_info *);
+extern uint64_t         pcireg_intr_status_get(struct pcibus_info *);
+extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
+extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
+extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
+extern void             pcireg_force_intr_set(struct pcibus_info *, int);
+extern uint64_t         pcireg_wrb_flush_get(struct pcibus_info *, int);
+extern void             pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
+extern uint64_t *       pcireg_int_ate_addr(struct pcibus_info *, int);
+extern void             pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
+extern void             pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
+extern int              pcibr_ate_alloc(struct pcibus_info *, int);
+extern void             pcibr_ate_free(struct pcibus_info *, int);
+extern void             ate_write(struct pcibus_info *, int, int, uint64_t);
+extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
+                                 void *resp);
+extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
+                                  int action, void *resp);
+#endif
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
index 04e27d5b3820..ad0e8e8ae53f 100644
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -18,8 +18,9 @@
 #define PCIIO_ASIC_TYPE_PIC     2
 #define PCIIO_ASIC_TYPE_TIOCP   3
 #define PCIIO_ASIC_TYPE_TIOCA   4
+#define PCIIO_ASIC_TYPE_TIOCE   5
 
-#define PCIIO_ASIC_MAX_TYPES    5
+#define PCIIO_ASIC_MAX_TYPES    6
 
 /*
  * Common pciio bus provider data.  There should be one of these as the
@@ -30,13 +31,15 @@
 struct pcibus_bussoft {
         uint32_t                bs_asic_type;   /* chipset type */
         uint32_t                bs_xid;         /* xwidget id */
-        uint64_t                bs_persist_busnum; /* Persistent Bus Number */
+        uint32_t                bs_persist_busnum; /* Persistent Bus Number */
+        uint32_t                bs_persist_segment; /* Segment Number */
         uint64_t                bs_legacy_io;   /* legacy io pio addr */
         uint64_t                bs_legacy_mem;  /* legacy mem pio addr */
         uint64_t                bs_base;        /* widget base */
         struct xwidget_info     *bs_xwidget_info;
 };
 
+struct pci_controller;
 /*
  * SN pci bus indirection
  */
@@ -45,7 +48,9 @@ struct sn_pcibus_provider {
         dma_addr_t      (*dma_map)(struct pci_dev *, unsigned long, size_t);
         dma_addr_t      (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
         void            (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
-        void *          (*bus_fixup)(struct pcibus_bussoft *);
+        void *          (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
+        void            (*force_interrupt)(struct sn_irq_info *);
+        void            (*target_interrupt)(struct sn_irq_info *);
 };
 
 extern struct sn_pcibus_provider *sn_pci_provider[];
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index ed4031d80811..49711d00ad04 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -10,11 +10,11 @@
 
 #include <linux/pci.h>
 
-extern struct sn_irq_info **sn_irq;
-
 #define SN_PCIDEV_INFO(pci_dev) \
         ((struct pcidev_info *)(pci_dev)->sysdata)
 
+#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
+        (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
 /*
  * Given a pci_bus, return the sn pcibus_bussoft struct.  Note that
  * this only works for root busses, not for busses represented by PPB's.
@@ -23,6 +23,8 @@ extern struct sn_irq_info **sn_irq;
 #define SN_PCIBUS_BUSSOFT(pci_bus) \
         ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
 
+#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
+        (struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
 /*
  * Given a struct pci_dev, return the sn pcibus_bussoft struct.  Note
  * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
@@ -50,9 +52,17 @@ struct pcidev_info {
 
         struct sn_irq_info      *pdi_sn_irq_info;
         struct sn_pcibus_provider *pdi_provider;        /* sn pci ops */
+        struct pci_dev          *host_pci_dev;          /* host bus link */
 };
 
 extern void sn_irq_fixup(struct pci_dev *pci_dev,
                          struct sn_irq_info *sn_irq_info);
-
+extern void sn_irq_unfixup(struct pci_dev *pci_dev);
+extern void sn_pci_controller_fixup(int segment, int busnum,
+                                    struct pci_bus *bus);
+extern void sn_bus_store_sysdata(struct pci_dev *dev);
+extern void sn_bus_free_sysdata(void);
+extern void sn_pci_fixup_slot(struct pci_dev *dev);
+extern void sn_pci_unfixup_slot(struct pci_dev *dev);
+extern void sn_irq_lh_init(void);
 #endif                          /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
index ea5590c76ca4..1c5108d44d8b 100644
--- a/include/asm-ia64/sn/pda.h
+++ b/include/asm-ia64/sn/pda.h
@@ -39,7 +39,6 @@ typedef struct pda_s {
         unsigned long pio_write_status_val;
         volatile unsigned long *pio_shub_war_cam_addr;
 
-        unsigned long   sn_soft_irr[4];
         unsigned long   sn_in_service_ivecs[4];
         int             sn_lb_int_war_ticks;
         int             sn_last_irq;
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
new file mode 100644
index 000000000000..0de82e6b0893
--- /dev/null
+++ b/include/asm-ia64/sn/pic.h
@@ -0,0 +1,261 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PIC_H
+#define _ASM_IA64_SN_PCI_PIC_H
+
+/*
+ * PIC AS DEVICE ZERO
+ * ------------------
+ *
+ * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
+ * be designated as 'device 0'.   That is a departure from earlier SGI
+ * PCI bridges.  Because of that we use config space 1 to access the
+ * config space of the first actual PCI device on the bus.
+ * Here's what the PIC manual says:
+ *
+ *     The current PCI-X bus specification now defines that the parent
+ *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
+ *     reduced the total number of devices from 8 to 4 and removed the
+ *     device registers and windows, now only supporting devices 0,1,2, and
+ *     3. PIC did leave all 8 configuration space windows. The reason was
+ *     there was nothing to gain by removing them. Here in lies the problem.
+ *     The device numbering we do using 0 through 3 is unrelated to the device
+ *     numbering which PCI-X requires in configuration space. In the past we
+ *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
+ *     PCI-X requires we start a 1, not 0 and currently the PX brick
+ *     does associate our:
+ *
+ *         device 0 with configuration space window 1,
+ *         device 1 with configuration space window 2,
+ *         device 2 with configuration space window 3,
+ *         device 3 with configuration space window 4.
+ *
+ * The net effect is that all config space access are off-by-one with
+ * relation to other per-slot accesses on the PIC.
+ * Here is a table that shows some of that:
+ *
+ *                               Internal Slot#
+ *           |
+ *           |     0         1        2         3
+ * ----------|---------------------------------------
+ * config    |  0x21000   0x22000  0x23000   0x24000
+ *           |
+ * even rrb  |  0[0]      n/a      1[0]      n/a        [] == implied even/odd
+ *           |
+ * odd rrb   |  n/a       0[1]     n/a       1[1]
+ *           |
+ * int dev   |  00       01        10        11
+ *           |
+ * ext slot# |  1        2         3         4
+ * ----------|---------------------------------------
+ */
+
+#define PIC_ATE_TARGETID_SHFT           8
+#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFFUL
+#define PIC_PCI64_ATTR_TARG_SHFT        60
+
+
+/*****************************************************************************
+ *********************** PIC MMR structure mapping ***************************
+ *****************************************************************************/
+
+/* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
+ * of a 64-bit register.  When writing PIC registers, always write the
+ * entire 64 bits.
+ */
+
+struct pic {
+
+    /* 0x000000-0x00FFFF -- Local Registers */
+
+    /* 0x000000-0x000057 -- Standard Widget Configuration */
+    uint64_t            p_wid_id;                       /* 0x000000 */
+    uint64_t            p_wid_stat;                     /* 0x000008 */
+    uint64_t            p_wid_err_upper;                /* 0x000010 */
+    uint64_t            p_wid_err_lower;                /* 0x000018 */
+    #define p_wid_err p_wid_err_lower
+    uint64_t            p_wid_control;                  /* 0x000020 */
+    uint64_t            p_wid_req_timeout;              /* 0x000028 */
+    uint64_t            p_wid_int_upper;                /* 0x000030 */
+    uint64_t            p_wid_int_lower;                /* 0x000038 */
+    #define p_wid_int p_wid_int_lower
+    uint64_t            p_wid_err_cmdword;              /* 0x000040 */
+    uint64_t            p_wid_llp;                      /* 0x000048 */
+    uint64_t            p_wid_tflush;                   /* 0x000050 */
+
+    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
+    uint64_t            p_wid_aux_err;                  /* 0x000058 */
+    uint64_t            p_wid_resp_upper;               /* 0x000060 */
+    uint64_t            p_wid_resp_lower;               /* 0x000068 */
+    #define p_wid_resp p_wid_resp_lower
+    uint64_t            p_wid_tst_pin_ctrl;             /* 0x000070 */
+    uint64_t            p_wid_addr_lkerr;               /* 0x000078 */
+
+    /* 0x000080-0x00008F -- PMU & MAP */
+    uint64_t            p_dir_map;                      /* 0x000080 */
+    uint64_t            _pad_000088;                    /* 0x000088 */
+
+    /* 0x000090-0x00009F -- SSRAM */
+    uint64_t            p_map_fault;                    /* 0x000090 */
+    uint64_t            _pad_000098;                    /* 0x000098 */
+
+    /* 0x0000A0-0x0000AF -- Arbitration */
+    uint64_t            p_arb;                          /* 0x0000A0 */
+    uint64_t            _pad_0000A8;                    /* 0x0000A8 */
+
+    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+    uint64_t            p_ate_parity_err;               /* 0x0000B0 */
+    uint64_t            _pad_0000B8;                    /* 0x0000B8 */
+
+    /* 0x0000C0-0x0000FF -- PCI/GIO */
+    uint64_t            p_bus_timeout;                  /* 0x0000C0 */
+    uint64_t            p_pci_cfg;                      /* 0x0000C8 */
+    uint64_t            p_pci_err_upper;                /* 0x0000D0 */
+    uint64_t            p_pci_err_lower;                /* 0x0000D8 */
+    #define p_pci_err p_pci_err_lower
+    uint64_t            _pad_0000E0[4];                 /* 0x0000{E0..F8} */
+
+    /* 0x000100-0x0001FF -- Interrupt */
+    uint64_t            p_int_status;                   /* 0x000100 */
+    uint64_t            p_int_enable;                   /* 0x000108 */
+    uint64_t            p_int_rst_stat;                 /* 0x000110 */
+    uint64_t            p_int_mode;                     /* 0x000118 */
+    uint64_t            p_int_device;                   /* 0x000120 */
+    uint64_t            p_int_host_err;                 /* 0x000128 */
+    uint64_t            p_int_addr[8];                  /* 0x0001{30,,,68} */
+    uint64_t            p_err_int_view;                 /* 0x000170 */
+    uint64_t            p_mult_int;                     /* 0x000178 */
+    uint64_t            p_force_always[8];              /* 0x0001{80,,,B8} */
+    uint64_t            p_force_pin[8];                 /* 0x0001{C0,,,F8} */
+
+    /* 0x000200-0x000298 -- Device */
+    uint64_t            p_device[4];                    /* 0x0002{00,,,18} */
+    uint64_t            _pad_000220[4];                 /* 0x0002{20,,,38} */
+    uint64_t            p_wr_req_buf[4];                /* 0x0002{40,,,58} */
+    uint64_t            _pad_000260[4];                 /* 0x0002{60,,,78} */
+    uint64_t            p_rrb_map[2];                   /* 0x0002{80,,,88} */
+    #define p_even_resp p_rrb_map[0]                    /* 0x000280 */
+    #define p_odd_resp  p_rrb_map[1]                    /* 0x000288 */
+    uint64_t            p_resp_status;                  /* 0x000290 */
+    uint64_t            p_resp_clear;                   /* 0x000298 */
+
+    uint64_t            _pad_0002A0[12];                /* 0x0002{A0..F8} */
+
+    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+    struct {
+        uint64_t        upper;                          /* 0x0003{00,,,F0} */
+        uint64_t        lower;                          /* 0x0003{08,,,F8} */
+    } p_buf_addr_match[16];
+
+    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+    struct {
+        uint64_t        flush_w_touch;                  /* 0x000{400,,,5C0} */
+        uint64_t        flush_wo_touch;                 /* 0x000{408,,,5C8} */
+        uint64_t        inflight;                       /* 0x000{410,,,5D0} */
+        uint64_t        prefetch;                       /* 0x000{418,,,5D8} */
+        uint64_t        total_pci_retry;                /* 0x000{420,,,5E0} */
+        uint64_t        max_pci_retry;                  /* 0x000{428,,,5E8} */
+        uint64_t        max_latency;                    /* 0x000{430,,,5F0} */
+        uint64_t        clear_all;                      /* 0x000{438,,,5F8} */
+    } p_buf_count[8];
+
+
+    /* 0x000600-0x0009FF -- PCI/X registers */
+    uint64_t            p_pcix_bus_err_addr;            /* 0x000600 */
+    uint64_t            p_pcix_bus_err_attr;            /* 0x000608 */
+    uint64_t            p_pcix_bus_err_data;            /* 0x000610 */
+    uint64_t            p_pcix_pio_split_addr;          /* 0x000618 */
+    uint64_t            p_pcix_pio_split_attr;          /* 0x000620 */
+    uint64_t            p_pcix_dma_req_err_attr;        /* 0x000628 */
+    uint64_t            p_pcix_dma_req_err_addr;        /* 0x000630 */
+    uint64_t            p_pcix_timeout;                 /* 0x000638 */
+
+    uint64_t            _pad_000640[120];               /* 0x000{640,,,9F8} */
+
+    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+    struct {
+        uint64_t        p_buf_addr;                     /* 0x000{A00,,,AF0} */
+        uint64_t        p_buf_attr;                     /* 0X000{A08,,,AF8} */
+    } p_pcix_read_buf_64[16];
+
+    struct {
+        uint64_t        p_buf_addr;                     /* 0x000{B00,,,BE0} */
+        uint64_t        p_buf_attr;                     /* 0x000{B08,,,BE8} */
+        uint64_t        p_buf_valid;                    /* 0x000{B10,,,BF0} */
+        uint64_t        __pad1;                         /* 0x000{B18,,,BF8} */
+    } p_pcix_write_buf_64[8];
+
+    /* End of Local Registers -- Start of Address Map space */
+
+    char                _pad_000c00[0x010000 - 0x000c00];
+
+    /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
+    uint64_t            p_int_ate_ram[1024];            /* 0x010000-0x011fff */
+
+    /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
+    uint64_t            p_int_ate_ram_mp[1024];         /* 0x012000-0x013fff */
+
+    char                _pad_014000[0x18000 - 0x014000];
+
+    /* 0x18000-0x197F8 -- PIC Write Request Ram */
+    uint64_t            p_wr_req_lower[256];            /* 0x18000 - 0x187F8 */
+    uint64_t            p_wr_req_upper[256];            /* 0x18800 - 0x18FF8 */
+    uint64_t            p_wr_req_parity[256];           /* 0x19000 - 0x197F8 */
+
+    char                _pad_019800[0x20000 - 0x019800];
+
+    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
+    union {
+        uint8_t         c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
+        uint16_t        s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
+        uint32_t        l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
+        uint64_t        d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
+        union {
+            uint8_t     c[0x100 / 1];
+            uint16_t    s[0x100 / 2];
+            uint32_t    l[0x100 / 4];
+            uint64_t    d[0x100 / 8];
+        } f[8];
+    } p_type0_cfg_dev[8];                               /* 0x02{0000,,,7FFF} */
+
+    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+    union {
+        uint8_t         c[0x1000 / 1];                  /* 0x028000-0x029000 */
+        uint16_t        s[0x1000 / 2];                  /* 0x028000-0x029000 */
+        uint32_t        l[0x1000 / 4];                  /* 0x028000-0x029000 */
+        uint64_t        d[0x1000 / 8];                  /* 0x028000-0x029000 */
+        union {
+            uint8_t     c[0x100 / 1];
+            uint16_t    s[0x100 / 2];
+            uint32_t    l[0x100 / 4];
+            uint64_t    d[0x100 / 8];
+        } f[8];
+    } p_type1_cfg;                                      /* 0x028000-0x029000 */
+
+    char                _pad_029000[0x030000-0x029000];
+
+    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+    union {
+        uint8_t         c[8 / 1];
+        uint16_t        s[8 / 2];
+        uint32_t        l[8 / 4];
+        uint64_t        d[8 / 8];
+    } p_pci_iack;                                       /* 0x030000-0x030007 */
+
+    char                _pad_030007[0x040000-0x030008];
+
+    /* 0x040000-0x030007 -- PCIX Special Cycle */
+    union {
+        uint8_t         c[8 / 1];
+        uint16_t        s[8 / 2];
+        uint32_t        l[8 / 4];
+        uint64_t        d[8 / 8];
+    } p_pcix_cycle;                                     /* 0x040000-0x040007 */
+};
+
+#endif                          /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
 /*                        Register "SH_IPI_INT"                         */
 /*               SHub Inter-Processor Interrupt Registers               */
 /* ==================================================================== */
-#define SH1_IPI_INT                               0x0000000110000380
-#define SH2_IPI_INT                               0x0000000010000380
+#define SH1_IPI_INT                     __IA64_UL_CONST(0x0000000110000380)
+#define SH2_IPI_INT                     __IA64_UL_CONST(0x0000000010000380)
 
 /*   SH_IPI_INT_TYPE                                                    */
 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_IPI_INT_TYPE_SHFT                     0
-#define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
+#define SH_IPI_INT_TYPE_SHFT                            0
+#define SH_IPI_INT_TYPE_MASK            __IA64_UL_CONST(0x0000000000000007)
 
 /*   SH_IPI_INT_AGT                                                     */
 /*   Description:  Agent, must be 0 for SHub                            */
-#define SH_IPI_INT_AGT_SHFT                      3
-#define SH_IPI_INT_AGT_MASK                      0x0000000000000008
+#define SH_IPI_INT_AGT_SHFT                             3
+#define SH_IPI_INT_AGT_MASK             __IA64_UL_CONST(0x0000000000000008)
 
 /*   SH_IPI_INT_PID                                                     */
 /*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_IPI_INT_PID_SHFT                      4
-#define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
+#define SH_IPI_INT_PID_SHFT                             4
+#define SH_IPI_INT_PID_MASK             __IA64_UL_CONST(0x00000000000ffff0)
 
 /*   SH_IPI_INT_BASE                                                    */
 /*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_IPI_INT_BASE_SHFT                     21
-#define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
+#define SH_IPI_INT_BASE_SHFT                            21
+#define SH_IPI_INT_BASE_MASK            __IA64_UL_CONST(0x0003ffffffe00000)
 
 /*   SH_IPI_INT_IDX                                                     */
 /*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_IPI_INT_IDX_SHFT                      52
-#define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
+#define SH_IPI_INT_IDX_SHFT                             52
+#define SH_IPI_INT_IDX_MASK             __IA64_UL_CONST(0x0ff0000000000000)
 
 /*   SH_IPI_INT_SEND                                                    */
 /*   Description:  Send Interrupt Message to PI, This generates a puls  */
-#define SH_IPI_INT_SEND_SHFT                     63
-#define SH_IPI_INT_SEND_MASK                     0x8000000000000000
+#define SH_IPI_INT_SEND_SHFT                            63
+#define SH_IPI_INT_SEND_MASK            __IA64_UL_CONST(0x8000000000000000)
 
 /* ==================================================================== */
 /*                     Register "SH_EVENT_OCCURRED"                     */
 /*                    SHub Interrupt Event Occurred                     */
 /* ==================================================================== */
-#define SH1_EVENT_OCCURRED                        0x0000000110010000
-#define SH1_EVENT_OCCURRED_ALIAS                  0x0000000110010008
-#define SH2_EVENT_OCCURRED                        0x0000000010010000
-#define SH2_EVENT_OCCURRED_ALIAS                  0x0000000010010008
+#define SH1_EVENT_OCCURRED              __IA64_UL_CONST(0x0000000110010000)
+#define SH1_EVENT_OCCURRED_ALIAS        __IA64_UL_CONST(0x0000000110010008)
+#define SH2_EVENT_OCCURRED              __IA64_UL_CONST(0x0000000010010000)
+#define SH2_EVENT_OCCURRED_ALIAS        __IA64_UL_CONST(0x0000000010010008)
 
 /* ==================================================================== */
 /*                     Register "SH_PI_CAM_CONTROL"                     */
 /*                      CRB CAM MMR Access Control                      */
 /* ==================================================================== */
-#define SH1_PI_CAM_CONTROL                        0x0000000120050300
+#define SH1_PI_CAM_CONTROL              __IA64_UL_CONST(0x0000000120050300)
 
 /* ==================================================================== */
 /*                        Register "SH_SHUB_ID"                         */
 /*                            SHub ID Number                            */
 /* ==================================================================== */
-#define SH1_SHUB_ID                               0x0000000110060580
-#define SH1_SHUB_ID_REVISION_SHFT                 28
-#define SH1_SHUB_ID_REVISION_MASK                 0x00000000f0000000
+#define SH1_SHUB_ID                     __IA64_UL_CONST(0x0000000110060580)
+#define SH1_SHUB_ID_REVISION_SHFT                       28
+#define SH1_SHUB_ID_REVISION_MASK       __IA64_UL_CONST(0x00000000f0000000)
 
 /* ==================================================================== */
 /*                          Register "SH_RTC"                           */
 /*                           Real-time Clock                            */
 /* ==================================================================== */
-#define SH1_RTC                                   0x00000001101c0000
-#define SH2_RTC                                   0x00000002101c0000
-#define SH_RTC_MASK                               0x007fffffffffffff
+#define SH1_RTC                         __IA64_UL_CONST(0x00000001101c0000)
+#define SH2_RTC                         __IA64_UL_CONST(0x00000002101c0000)
+#define SH_RTC_MASK                     __IA64_UL_CONST(0x007fffffffffffff)
 
 /* ==================================================================== */
 /*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
 /*                      PIO Write Status for CPU 0 & 1                  */
 /* ==================================================================== */
-#define SH1_PIO_WRITE_STATUS_0                    0x0000000120070200
-#define SH1_PIO_WRITE_STATUS_1                    0x0000000120070280
-#define SH2_PIO_WRITE_STATUS_0                    0x0000000020070200
-#define SH2_PIO_WRITE_STATUS_1                    0x0000000020070280
-#define SH2_PIO_WRITE_STATUS_2                    0x0000000020070300
-#define SH2_PIO_WRITE_STATUS_3                    0x0000000020070380
+#define SH1_PIO_WRITE_STATUS_0          __IA64_UL_CONST(0x0000000120070200)
+#define SH1_PIO_WRITE_STATUS_1          __IA64_UL_CONST(0x0000000120070280)
+#define SH2_PIO_WRITE_STATUS_0          __IA64_UL_CONST(0x0000000020070200)
+#define SH2_PIO_WRITE_STATUS_1          __IA64_UL_CONST(0x0000000020070280)
+#define SH2_PIO_WRITE_STATUS_2          __IA64_UL_CONST(0x0000000020070300)
+#define SH2_PIO_WRITE_STATUS_3          __IA64_UL_CONST(0x0000000020070380)
 
 /*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
 /*   Description:  Deadlock response detected                           */
-#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
-#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT         1
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
+                                        __IA64_UL_CONST(0x0000000000000002)
 
 /*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
 /*   Description:  Count of currently pending PIO writes                */
-#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
-#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT    56
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
+                                        __IA64_UL_CONST(0x3f00000000000000)
 
 /* ==================================================================== */
 /*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
 /* ==================================================================== */
-#define SH1_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
-#define SH2_PIO_WRITE_STATUS_0_ALIAS              0x0000000020070208
+#define SH1_PIO_WRITE_STATUS_0_ALIAS    __IA64_UL_CONST(0x0000000120070208)
+#define SH2_PIO_WRITE_STATUS_0_ALIAS    __IA64_UL_CONST(0x0000000020070208)
 
 /* ==================================================================== */
 /*                     Register "SH_EVENT_OCCURRED"                     */
@@ -111,33 +113,33 @@
 /* ==================================================================== */
 /*   SH_EVENT_OCCURRED_UART_INT                                         */
 /*   Description:  Pending Junk Bus UART Interrupt                      */
-#define SH_EVENT_OCCURRED_UART_INT_SHFT          20
-#define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
+#define SH_EVENT_OCCURRED_UART_INT_SHFT                 20
+#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
 
 /*   SH_EVENT_OCCURRED_IPI_INT                                          */
 /*   Description:  Pending IPI Interrupt                                */
-#define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
-#define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT                  28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK  __IA64_UL_CONST(0x0000000010000000)
 
 /*   SH_EVENT_OCCURRED_II_INT0                                          */
 /*   Description:  Pending II 0 Interrupt                               */
-#define SH_EVENT_OCCURRED_II_INT0_SHFT           29
-#define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
+#define SH_EVENT_OCCURRED_II_INT0_SHFT                  29
+#define SH_EVENT_OCCURRED_II_INT0_MASK  __IA64_UL_CONST(0x0000000020000000)
 
 /*   SH_EVENT_OCCURRED_II_INT1                                          */
 /*   Description:  Pending II 1 Interrupt                               */
-#define SH_EVENT_OCCURRED_II_INT1_SHFT           30
-#define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
+#define SH_EVENT_OCCURRED_II_INT1_SHFT                  30
+#define SH_EVENT_OCCURRED_II_INT1_MASK  __IA64_UL_CONST(0x0000000040000000)
 
 /*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
 /*   Description:  Pending SHUB 2 EXT IO INT2                           */
-#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT       33
-#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK       0x0000000200000000
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT              33
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
 
 /*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
 /*   Description:  Pending SHUB 2 EXT IO INT3                           */
-#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT       34
-#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK       0x0000000400000000
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT              34
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
 
 #define SH_ALL_INT_MASK \
         (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
 /* ==================================================================== */
 /*                         LEDS                                         */
 /* ==================================================================== */
-#define SH1_REAL_JUNK_BUS_LED0                   0x7fed00000UL
-#define SH1_REAL_JUNK_BUS_LED1                   0x7fed10000UL
-#define SH1_REAL_JUNK_BUS_LED2                   0x7fed20000UL
-#define SH1_REAL_JUNK_BUS_LED3                   0x7fed30000UL
+#define SH1_REAL_JUNK_BUS_LED0                  0x7fed00000UL
+#define SH1_REAL_JUNK_BUS_LED1                  0x7fed10000UL
+#define SH1_REAL_JUNK_BUS_LED2                  0x7fed20000UL
+#define SH1_REAL_JUNK_BUS_LED3                  0x7fed30000UL
 
-#define SH2_REAL_JUNK_BUS_LED0                   0xf0000000UL
-#define SH2_REAL_JUNK_BUS_LED1                   0xf0010000UL
-#define SH2_REAL_JUNK_BUS_LED2                   0xf0020000UL
-#define SH2_REAL_JUNK_BUS_LED3                   0xf0030000UL
+#define SH2_REAL_JUNK_BUS_LED0                  0xf0000000UL
+#define SH2_REAL_JUNK_BUS_LED1                  0xf0010000UL
+#define SH2_REAL_JUNK_BUS_LED2                  0xf0020000UL
+#define SH2_REAL_JUNK_BUS_LED3                  0xf0030000UL
 
 /* ==================================================================== */
 /*                         Register "SH1_PTC_0"                         */
 /*       Puge Translation Cache Message Configuration Information       */
 /* ==================================================================== */
-#define SH1_PTC_0                                 0x00000001101a0000
+#define SH1_PTC_0                       __IA64_UL_CONST(0x00000001101a0000)
 
 /*   SH1_PTC_0_A                                                        */
 /*   Description:  Type                                                 */
-#define SH1_PTC_0_A_SHFT                          0
+#define SH1_PTC_0_A_SHFT                                0
 
 /*   SH1_PTC_0_PS                                                       */
 /*   Description:  Page Size                                            */
-#define SH1_PTC_0_PS_SHFT                         2
+#define SH1_PTC_0_PS_SHFT                               2
 
 /*   SH1_PTC_0_RID                                                      */
 /*   Description:  Region ID                                            */
-#define SH1_PTC_0_RID_SHFT                        8
+#define SH1_PTC_0_RID_SHFT                              8
 
 /*   SH1_PTC_0_START                                                    */
 /*   Description:  Start                                                */
-#define SH1_PTC_0_START_SHFT                      63
+#define SH1_PTC_0_START_SHFT                            63
 
 /* ==================================================================== */
 /*                         Register "SH1_PTC_1"                         */
 /*       Puge Translation Cache Message Configuration Information       */
 /* ==================================================================== */
-#define SH1_PTC_1                                 0x00000001101a0080
+#define SH1_PTC_1                       __IA64_UL_CONST(0x00000001101a0080)
 
 /*   SH1_PTC_1_START                                                    */
 /*   Description:  PTC_1 Start                                          */
-#define SH1_PTC_1_START_SHFT                      63
-
+#define SH1_PTC_1_START_SHFT                            63
 
 /* ==================================================================== */
 /*                         Register "SH2_PTC"                           */
 /*       Puge Translation Cache Message Configuration Information       */
 /* ==================================================================== */
-#define SH2_PTC                                   0x0000000170000000
+#define SH2_PTC                         __IA64_UL_CONST(0x0000000170000000)
 
 /*   SH2_PTC_A                                                          */
 /*   Description:  Type                                                 */
-#define SH2_PTC_A_SHFT                            0
+#define SH2_PTC_A_SHFT                                  0
 
 /*   SH2_PTC_PS                                                         */
 /*   Description:  Page Size                                            */
-#define SH2_PTC_PS_SHFT                           2
+#define SH2_PTC_PS_SHFT                                 2
 
 /*   SH2_PTC_RID                                                      */
 /*   Description:  Region ID                                            */
-#define SH2_PTC_RID_SHFT                          4
+#define SH2_PTC_RID_SHFT                                4
 
 /*   SH2_PTC_START                                                      */
 /*   Description:  Start                                                */
-#define SH2_PTC_START_SHFT                        63
+#define SH2_PTC_START_SHFT                              63
 
 /*   SH2_PTC_ADDR_RID                                                   */
 /*   Description:  Region ID                                            */
-#define SH2_PTC_ADDR_SHFT                         4
-#define SH2_PTC_ADDR_MASK                         0x1ffffffffffff000
+#define SH2_PTC_ADDR_SHFT                               4
+#define SH2_PTC_ADDR_MASK               __IA64_UL_CONST(0x1ffffffffffff000)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC1_INT_CONFIG"                     */
 /*                SHub RTC 1 Interrupt Config Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC1_INT_CONFIG                      0x0000000110001480
-#define SH2_RTC1_INT_CONFIG                      0x0000000010001480
-#define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
-#define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
+#define SH1_RTC1_INT_CONFIG             __IA64_UL_CONST(0x0000000110001480)
+#define SH2_RTC1_INT_CONFIG             __IA64_UL_CONST(0x0000000010001480)
+#define SH_RTC1_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC1_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC1_INT_CONFIG_TYPE                                            */
 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
-#define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
 
 /*   SH_RTC1_INT_CONFIG_AGT                                             */
 /*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
-#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
+#define SH_RTC1_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC1_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
 
 /*   SH_RTC1_INT_CONFIG_PID                                             */
 /*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC1_INT_CONFIG_PID_SHFT              4
-#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
+#define SH_RTC1_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC1_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
 
 /*   SH_RTC1_INT_CONFIG_BASE                                            */
 /*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
-#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+#define SH_RTC1_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC1_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
 
 /*   SH_RTC1_INT_CONFIG_IDX                                             */
 /*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
-#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+#define SH_RTC1_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC1_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC1_INT_ENABLE"                     */
 /*                SHub RTC 1 Interrupt Enable Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC1_INT_ENABLE                      0x0000000110001500
-#define SH2_RTC1_INT_ENABLE                      0x0000000010001500
-#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
-#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
+#define SH1_RTC1_INT_ENABLE             __IA64_UL_CONST(0x0000000110001500)
+#define SH2_RTC1_INT_ENABLE             __IA64_UL_CONST(0x0000000010001500)
+#define SH_RTC1_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC1_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
 /*   Description:  Enable RTC 1 Interrupt                               */
-#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
-#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT             0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC2_INT_CONFIG"                     */
 /*                SHub RTC 2 Interrupt Config Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC2_INT_CONFIG                      0x0000000110001580
-#define SH2_RTC2_INT_CONFIG                      0x0000000010001580
-#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
-#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
+#define SH1_RTC2_INT_CONFIG             __IA64_UL_CONST(0x0000000110001580)
+#define SH2_RTC2_INT_CONFIG             __IA64_UL_CONST(0x0000000010001580)
+#define SH_RTC2_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC2_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC2_INT_CONFIG_TYPE                                            */
 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
-#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
 
 /*   SH_RTC2_INT_CONFIG_AGT                                             */
 /*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
-#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
+#define SH_RTC2_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC2_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
 
 /*   SH_RTC2_INT_CONFIG_PID                                             */
 /*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC2_INT_CONFIG_PID_SHFT              4
-#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
+#define SH_RTC2_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC2_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
 
 /*   SH_RTC2_INT_CONFIG_BASE                                            */
 /*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
-#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+#define SH_RTC2_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC2_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
 
 /*   SH_RTC2_INT_CONFIG_IDX                                             */
 /*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
-#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+#define SH_RTC2_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC2_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC2_INT_ENABLE"                     */
 /*                SHub RTC 2 Interrupt Enable Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC2_INT_ENABLE                      0x0000000110001600
-#define SH2_RTC2_INT_ENABLE                      0x0000000010001600
-#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
-#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
+#define SH1_RTC2_INT_ENABLE             __IA64_UL_CONST(0x0000000110001600)
+#define SH2_RTC2_INT_ENABLE             __IA64_UL_CONST(0x0000000010001600)
+#define SH_RTC2_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC2_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
 /*   Description:  Enable RTC 2 Interrupt                               */
-#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
-#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT             0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC3_INT_CONFIG"                     */
 /*                SHub RTC 3 Interrupt Config Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC3_INT_CONFIG                      0x0000000110001680
-#define SH2_RTC3_INT_CONFIG                      0x0000000010001680
-#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
-#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
+#define SH1_RTC3_INT_CONFIG             __IA64_UL_CONST(0x0000000110001680)
+#define SH2_RTC3_INT_CONFIG             __IA64_UL_CONST(0x0000000010001680)
+#define SH_RTC3_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC3_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC3_INT_CONFIG_TYPE                                            */
 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
-#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
-#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
 
 /*   SH_RTC3_INT_CONFIG_AGT                                             */
 /*   Description:  Agent, must be 0 for SHub                            */
-#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
-#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
+#define SH_RTC3_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC3_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
 
 /*   SH_RTC3_INT_CONFIG_PID                                             */
 /*   Description:  Processor ID, same setting as on targeted McKinley  */
-#define SH_RTC3_INT_CONFIG_PID_SHFT              4
-#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
+#define SH_RTC3_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC3_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
 
 /*   SH_RTC3_INT_CONFIG_BASE                                            */
 /*   Description:  Optional interrupt vector area, 2MB aligned          */
-#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
-#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+#define SH_RTC3_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC3_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
 
 /*   SH_RTC3_INT_CONFIG_IDX                                             */
 /*   Description:  Targeted McKinley interrupt vector                   */
-#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
-#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+#define SH_RTC3_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC3_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
 
 /* ==================================================================== */
 /*                    Register "SH_RTC3_INT_ENABLE"                     */
 /*                SHub RTC 3 Interrupt Enable Registers                 */
 /* ==================================================================== */
 
-#define SH1_RTC3_INT_ENABLE                      0x0000000110001700
-#define SH2_RTC3_INT_ENABLE                      0x0000000010001700
-#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
-#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
+#define SH1_RTC3_INT_ENABLE             __IA64_UL_CONST(0x0000000110001700)
+#define SH2_RTC3_INT_ENABLE             __IA64_UL_CONST(0x0000000010001700)
+#define SH_RTC3_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC3_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
 /*   Description:  Enable RTC 3 Interrupt                               */
-#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
-#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT             0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
 
 /*   SH_EVENT_OCCURRED_RTC1_INT                                         */
 /*   Description:  Pending RTC 1 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
-#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT                 24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
 
 /*   SH_EVENT_OCCURRED_RTC2_INT                                         */
 /*   Description:  Pending RTC 2 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
-#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT                 25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
 
 /*   SH_EVENT_OCCURRED_RTC3_INT                                         */
 /*   Description:  Pending RTC 3 Interrupt                              */
-#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
-#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT                 26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
 
 /* ==================================================================== */
 /*                       Register "SH_IPI_ACCESS"                       */
 /*                 CPU interrupt Access Permission Bits                 */
 /* ==================================================================== */
 
-#define SH1_IPI_ACCESS                           0x0000000110060480
-#define SH2_IPI_ACCESS0                          0x0000000010060c00
-#define SH2_IPI_ACCESS1                          0x0000000010060c80
-#define SH2_IPI_ACCESS2                          0x0000000010060d00
-#define SH2_IPI_ACCESS3                          0x0000000010060d80
+#define SH1_IPI_ACCESS                  __IA64_UL_CONST(0x0000000110060480)
+#define SH2_IPI_ACCESS0                 __IA64_UL_CONST(0x0000000010060c00)
+#define SH2_IPI_ACCESS1                 __IA64_UL_CONST(0x0000000010060c80)
+#define SH2_IPI_ACCESS2                 __IA64_UL_CONST(0x0000000010060d00)
+#define SH2_IPI_ACCESS3                 __IA64_UL_CONST(0x0000000010060d80)
 
 /* ==================================================================== */
 /*                        Register "SH_INT_CMPB"                        */
 /*                  RTC Compare Value for Processor B                   */
 /* ==================================================================== */
 
-#define SH1_INT_CMPB                             0x00000001101b0080
-#define SH2_INT_CMPB                             0x00000000101b0080
-#define SH_INT_CMPB_MASK                         0x007fffffffffffff
-#define SH_INT_CMPB_INIT                         0x0000000000000000
+#define SH1_INT_CMPB                    __IA64_UL_CONST(0x00000001101b0080)
+#define SH2_INT_CMPB                    __IA64_UL_CONST(0x00000000101b0080)
+#define SH_INT_CMPB_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPB_INIT                __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
 /*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
-#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT                 0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
 
 /* ==================================================================== */
 /*                        Register "SH_INT_CMPC"                        */
 /*                  RTC Compare Value for Processor C                   */
 /* ==================================================================== */
 
-#define SH1_INT_CMPC                             0x00000001101b0100
-#define SH2_INT_CMPC                             0x00000000101b0100
-#define SH_INT_CMPC_MASK                         0x007fffffffffffff
-#define SH_INT_CMPC_INIT                         0x0000000000000000
+#define SH1_INT_CMPC                    __IA64_UL_CONST(0x00000001101b0100)
+#define SH2_INT_CMPC                    __IA64_UL_CONST(0x00000000101b0100)
+#define SH_INT_CMPC_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPC_INIT                __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
 /*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
-#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT                 0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
 
 /* ==================================================================== */
 /*                        Register "SH_INT_CMPD"                        */
 /*                  RTC Compare Value for Processor D                   */
 /* ==================================================================== */
 
-#define SH1_INT_CMPD                             0x00000001101b0180
-#define SH2_INT_CMPD                             0x00000000101b0180
-#define SH_INT_CMPD_MASK                         0x007fffffffffffff
-#define SH_INT_CMPD_INIT                         0x0000000000000000
+#define SH1_INT_CMPD                    __IA64_UL_CONST(0x00000001101b0180)
+#define SH2_INT_CMPD                    __IA64_UL_CONST(0x00000000101b0180)
+#define SH_INT_CMPD_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPD_INIT                __IA64_UL_CONST(0x0000000000000000)
 
 /*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
 /*   Description:  Real Time Clock Compare                              */
-#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
-#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT                 0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
 
 /* ==================================================================== */
 /*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
 /*                      privilege vector for acc=0                      */
 /* ==================================================================== */
-
-#define SH1_MD_DQLP_MMR_DIR_PRIVEC0              0x0000000100030300
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0     __IA64_UL_CONST(0x0000000100030300)
 
 /* ==================================================================== */
 /*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
 /*                      privilege vector for acc=0                      */
 /* ==================================================================== */
-
-#define SH1_MD_DQRP_MMR_DIR_PRIVEC0              0x0000000100050300
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0     __IA64_UL_CONST(0x0000000100050300)
 
 /* ==================================================================== */
 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
 /*                    Engine 0 Control and Status Register                    */
 /* ========================================================================== */
 
-#define SH2_BT_ENG_CSR_0                         0x0000000030040000
-#define SH2_BT_ENG_SRC_ADDR_0                    0x0000000030040080
-#define SH2_BT_ENG_DEST_ADDR_0                   0x0000000030040100
-#define SH2_BT_ENG_NOTIF_ADDR_0                  0x0000000030040180
+#define SH2_BT_ENG_CSR_0                __IA64_UL_CONST(0x0000000030040000)
+#define SH2_BT_ENG_SRC_ADDR_0           __IA64_UL_CONST(0x0000000030040080)
+#define SH2_BT_ENG_DEST_ADDR_0          __IA64_UL_CONST(0x0000000030040100)
+#define SH2_BT_ENG_NOTIF_ADDR_0         __IA64_UL_CONST(0x0000000030040180)
 
 /* ========================================================================== */
 /*                       BTE interfaces 1-3                                   */
 /* ========================================================================== */
 
-#define SH2_BT_ENG_CSR_1                         0x0000000030050000
-#define SH2_BT_ENG_CSR_2                         0x0000000030060000
-#define SH2_BT_ENG_CSR_3                         0x0000000030070000
+#define SH2_BT_ENG_CSR_1                __IA64_UL_CONST(0x0000000030050000)
+#define SH2_BT_ENG_CSR_2                __IA64_UL_CONST(0x0000000030060000)
+#define SH2_BT_ENG_CSR_3                __IA64_UL_CONST(0x0000000030070000)
 
 #endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
index 78eb4f869c8b..16a48b5a039c 100644
--- a/include/asm-ia64/sn/simulator.h
+++ b/include/asm-ia64/sn/simulator.h
@@ -10,18 +10,12 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_IA64_SGI_SN_SIM
-
 #define SNMAGIC 0xaeeeeeee8badbeefL
-#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
-
-#define SIMULATOR_SLEEP()       asm("nop.i 0x8beef")
-
-#else
-
-#define IS_RUNNING_ON_SIMULATOR()       (0)
-#define SIMULATOR_SLEEP()
+#define IS_MEDUSA()                     ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
 
-#endif
+#define SIMULATOR_SLEEP()               asm("nop.i 0x8beef")
+#define IS_RUNNING_ON_SIMULATOR()       (sn_prom_type)
+#define IS_RUNNING_ON_FAKE_PROM()       (sn_prom_type == 2)
+extern int sn_prom_type;                /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
 
 #endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index b0c4d6dd77ba..291ef3d69da2 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -43,6 +43,7 @@ struct sn_hwperf_object_info {
 
 /* macros for object classification */
 #define SN_HWPERF_IS_NODE(x)            ((x) && strstr((x)->name, "SHub"))
+#define SN_HWPERF_IS_NODE_SHUB2(x)      ((x) && strstr((x)->name, "SHub 2."))
 #define SN_HWPERF_IS_IONODE(x)          ((x) && strstr((x)->name, "TIO"))
 #define SN_HWPERF_IS_ROUTER(x)          ((x) && strstr((x)->name, "Router"))
 #define SN_HWPERF_IS_NL3ROUTER(x)       ((x) && strstr((x)->name, "NL3Router"))
@@ -214,6 +215,15 @@ struct sn_hwperf_ioctl_args {
  */
 #define SN_HWPERF_GET_NODE_NASID        (102|SN_HWPERF_OP_MEM_COPYOUT)
 
+/*
+ * Given a node id, determine the id of the nearest node with CPUs
+ * and the id of the nearest node that has memory. The argument
+ * node would normally be a "headless" node, e.g. an "IO node".
+ * Return 0 on success.
+ */
+extern int sn_hwperf_get_nearest_node(cnodeid_t node,
+        cnodeid_t *near_mem, cnodeid_t *near_cpu);
+
 /* return codes */
 #define SN_HWPERF_OP_OK                 0
 #define SN_HWPERF_OP_NOMEM              1
@@ -223,4 +233,6 @@ struct sn_hwperf_ioctl_args {
 #define SN_HWPERF_OP_RECONFIGURE        253
 #define SN_HWPERF_OP_INVAL              254
 
+int sn_topology_open(struct inode *inode, struct file *file);
+int sn_topology_release(struct inode *inode, struct file *file);
 #endif                          /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
index 20b300187669..d2c1d34dcce4 100644
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -81,11 +81,6 @@
  *
  */
 
-#ifndef CONFIG_SMP
-#define cpu_physical_id(cpuid)                  ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
-#endif
-
-
 #define get_node_number(addr)                   NASID_GET(addr)
 
 /*
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index eb0395ad0d6a..e67825ad1930 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -55,7 +55,6 @@
 #define  SN_SAL_BUS_CONFIG                         0x02000037
 #define  SN_SAL_SYS_SERIAL_GET                     0x02000038
 #define  SN_SAL_PARTITION_SERIAL_GET               0x02000039
-#define  SN_SAL_SYSCTL_PARTITION_GET               0x0200003a
 #define  SN_SAL_SYSTEM_POWER_DOWN                  0x0200003b
 #define  SN_SAL_GET_MASTER_BASEIO_NASID            0x0200003c
 #define  SN_SAL_COHERENCE                          0x0200003d
@@ -78,7 +77,8 @@
 
 #define SN_SAL_HUB_ERROR_INTERRUPT                 0x02000060
 #define SN_SAL_BTE_RECOVER                         0x02000061
-#define SN_SAL_IOIF_GET_PCI_TOPOLOGY               0x02000062
+#define SN_SAL_RESERVED_DO_NOT_USE                 0x02000062
+#define SN_SAL_IOIF_GET_PCI_TOPOLOGY               0x02000064
 
 /*
  * Service-specific constants
@@ -132,43 +132,30 @@
 #define SALRET_INVALID_ARG      (-2)
 #define SALRET_ERROR            (-3)
 
+#define SN_SAL_FAKE_PROM                           0x02009999
 
 /**
- * sn_sal_rev_major - get the major SGI SAL revision number
- *
- * The SGI PROM stores its version in sal_[ab]_rev_(major|minor).
- * This routine simply extracts the major value from the
- * @ia64_sal_systab structure constructed by ia64_sal_init().
- */
-static inline int
-sn_sal_rev_major(void)
+  * sn_sal_revision - get the SGI SAL revision number
+  *
+  * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
+  * This routine simply extracts the major and minor values and
+  * presents them in a u32 format.
+  *
+  * For example, version 4.05 would be represented at 0x0405.
+  */
+static inline u32
+sn_sal_rev(void)
 {
         struct ia64_sal_systab *systab = efi.sal_systab;
 
-        return (int)systab->sal_b_rev_major;
-}
-
-/**
- * sn_sal_rev_minor - get the minor SGI SAL revision number
- *
- * The SGI PROM stores its version in sal_[ab]_rev_(major|minor).
- * This routine simply extracts the minor value from the
- * @ia64_sal_systab structure constructed by ia64_sal_init().
- */
-static inline int
-sn_sal_rev_minor(void)
-{
-        struct ia64_sal_systab *systab = efi.sal_systab;
-        
-        return (int)systab->sal_b_rev_minor;
+        return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
 }
 
 /*
  * Specify the minimum PROM revsion required for this kernel.
  * Note that they're stored in hex format...
  */
-#define SN_SAL_MIN_MAJOR        0x4  /* SN2 kernels need at least PROM 4.0 */
-#define SN_SAL_MIN_MINOR        0x0
+#define SN_SAL_MIN_VERSION      0x0404
 
 /*
  * Returns the master console nasid, if the call fails, return an illegal
@@ -599,35 +586,6 @@ sn_partition_serial_number_val(void) {
 }
 
 /*
- * Returns the partition id of the nasid passed in as an argument,
- * or INVALID_PARTID if the partition id cannot be retrieved.
- */
-static inline partid_t
-ia64_sn_sysctl_partition_get(nasid_t nasid)
-{
-        struct ia64_sal_retval ret_stuff;
-        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
-                                0, 0, 0, 0, 0, 0);
-        if (ret_stuff.status != 0)
-            return INVALID_PARTID;
-        return ((partid_t)ret_stuff.v0);
-}
-
-/*
- * Returns the partition id of the current processor.
- */
-
-extern partid_t sn_partid;
-
-static inline partid_t
-sn_local_partid(void) {
-        if (unlikely(sn_partid < 0)) {
-                sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()));
-        }
-        return sn_partid;
-}
-
-/*
  * Returns the physical address of the partition's reserved page through
  * an iterative number of calls.
  *
@@ -762,7 +720,8 @@ ia64_sn_power_down(void)
 {
         struct ia64_sal_retval ret_stuff;
         SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
-        while(1);
+        while(1)
+                cpu_relax();
         /* never returns */
 }
 
@@ -1031,24 +990,6 @@ ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
         ret_stuff.v2 = 0;
         SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
 
-/***** BEGIN HACK - temp til old proms no longer supported ********/
-        if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
-                int nasid = get_sapicid() & 0xfff;;
-#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL                                               
-#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48                                                               
-                if (shubtype) *shubtype = 0;
-                if (nasid_bitmask) *nasid_bitmask = 0x7ff;
-                if (nasid_shift) *nasid_shift = 38;
-                if (systemsize) *systemsize = 11;
-                if (sharing_domain_size) *sharing_domain_size = 9;
-                if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
-                if (coher) *coher = nasid >> 9;
-                if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
-                        SH_SHUB_ID_NODES_PER_BIT_SHFT;
-                return 0;
-        }
-/***** END HACK *******/
-
         if (ret_stuff.status < 0)
                 return ret_stuff.status;
 
@@ -1081,12 +1022,10 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
 }
 
 static inline int
-ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab,
-                              u64 buf, u64 len)
+ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
 {
         struct ia64_sal_retval rv;
-        SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY,
-                rack, bay, slot, slab, buf, len, 0);
+        SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
         return (int) rv.status;
 }
 
@@ -1105,4 +1044,12 @@ ia64_sn_bte_recovery(nasid_t nasid)
         return (int) rv.status;
 }
 
+static inline int
+ia64_sn_is_fake_prom(void)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
+        return (rv.status == 0);
+}
+
 #endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b6acc22ab239..5ccec608d325 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -201,6 +201,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
 }
 
 extern uint32_t tioca_gart_found;
+extern struct list_head tioca_list;
 extern int tioca_init_provider(void);
 extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
 #endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
new file mode 100644
index 000000000000..22879853e46c
--- /dev/null
+++ b/include/asm-ia64/sn/tioce.h
@@ -0,0 +1,740 @@
+/**************************************************************************
+ *                                                                        *
+ *  Unpublished copyright (c) 2005, Silicon Graphics, Inc.                *
+ *  THIS IS UNPUBLISHED CONFIDENTIAL AND PROPRIETARY SOURCE CODE OF SGI.  *
+ *                                                                        *
+ *  The copyright notice above does  not evidence any actual or intended  *
+ *  publication  or  disclosure  of  this source  code,  which  includes  *
+ *  information that is confidential  and/or proprietary, and is a trade  *
+ *  secret, of  Silicon Graphics, Inc.   ANY REPRODUCTION, MODIFICATION,  *
+ *  DISTRIBUTION, PUBLIC  PERFORMANCE, OR  PUBLIC DISPLAY OF  OR THROUGH  *
+ *  USE  OF THIS  SOURCE CODE  WITHOUT  THE EXPRESS  WRITTEN CONSENT  OF  *
+ *  SILICON GRAPHICS, INC.  IS  STRICTLY PROHIBITED, AND IN VIOLATION OF  *
+ *  APPLICABLE  LAWS   AND  INTERNATIONAL  TREATIES.    THE  RECEIPT  OR  *
+ *  POSSESSION OF  THIS SOURCE CODE AND/OR RELATED  INFORMATION DOES NOT  *
+ *  CONVEY OR IMPLY ANY RIGHTS  TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS  *
+ *  CONTENTS,  OR TO  MANUFACTURE, USE,  OR  SELL ANYTHING  THAT IT  MAY  *
+ *  DESCRIBE, IN WHOLE OR IN PART.                                        *
+ *                                                                        *
+ **************************************************************************/
+
+#ifndef __ASM_IA64_SN_TIOCE_H__
+#define __ASM_IA64_SN_TIOCE_H__
+
+/* CE ASIC part & mfgr information  */
+#define TIOCE_PART_NUM                  0xCE00
+#define TIOCE_MFGR_NUM                  0x36
+#define TIOCE_REV_A                     0x1
+
+/* CE Virtual PPB Vendor/Device IDs */
+#define CE_VIRT_PPB_VENDOR_ID           0x10a9
+#define CE_VIRT_PPB_DEVICE_ID           0x4002
+
+/* CE Host Bridge Vendor/Device IDs */
+#define CE_HOST_BRIDGE_VENDOR_ID        0x10a9
+#define CE_HOST_BRIDGE_DEVICE_ID        0x4003
+
+
+#define TIOCE_NUM_M40_ATES              4096
+#define TIOCE_NUM_M3240_ATES            2048
+#define TIOCE_NUM_PORTS                 2
+
+/*
+ * Register layout for TIOCE.  MMR offsets are shown at the far right of the
+ * structure definition.
+ */
+typedef volatile struct tioce {
+        /*
+         * ADMIN : Administration Registers
+         */
+        uint64_t        ce_adm_id;                              /* 0x000000 */
+        uint64_t        ce_pad_000008;                          /* 0x000008 */
+        uint64_t        ce_adm_dyn_credit_status;               /* 0x000010 */
+        uint64_t        ce_adm_last_credit_status;              /* 0x000018 */
+        uint64_t        ce_adm_credit_limit;                    /* 0x000020 */
+        uint64_t        ce_adm_force_credit;                    /* 0x000028 */
+        uint64_t        ce_adm_control;                         /* 0x000030 */
+        uint64_t        ce_adm_mmr_chn_timeout;                 /* 0x000038 */
+        uint64_t        ce_adm_ssp_ure_timeout;                 /* 0x000040 */
+        uint64_t        ce_adm_ssp_dre_timeout;                 /* 0x000048 */
+        uint64_t        ce_adm_ssp_debug_sel;                   /* 0x000050 */
+        uint64_t        ce_adm_int_status;                      /* 0x000058 */
+        uint64_t        ce_adm_int_status_alias;                /* 0x000060 */
+        uint64_t        ce_adm_int_mask;                        /* 0x000068 */
+        uint64_t        ce_adm_int_pending;                     /* 0x000070 */
+        uint64_t        ce_adm_force_int;                       /* 0x000078 */
+        uint64_t        ce_adm_ure_ups_buf_barrier_flush;       /* 0x000080 */
+        uint64_t        ce_adm_int_dest[15];        /* 0x000088 -- 0x0000F8 */
+        uint64_t        ce_adm_error_summary;                   /* 0x000100 */
+        uint64_t        ce_adm_error_summary_alias;             /* 0x000108 */
+        uint64_t        ce_adm_error_mask;                      /* 0x000110 */
+        uint64_t        ce_adm_first_error;                     /* 0x000118 */
+        uint64_t        ce_adm_error_overflow;                  /* 0x000120 */
+        uint64_t        ce_adm_error_overflow_alias;            /* 0x000128 */
+        uint64_t        ce_pad_000130[2];           /* 0x000130 -- 0x000138 */
+        uint64_t        ce_adm_tnum_error;                      /* 0x000140 */
+        uint64_t        ce_adm_mmr_err_detail;                  /* 0x000148 */
+        uint64_t        ce_adm_msg_sram_perr_detail;            /* 0x000150 */
+        uint64_t        ce_adm_bap_sram_perr_detail;            /* 0x000158 */
+        uint64_t        ce_adm_ce_sram_perr_detail;             /* 0x000160 */
+        uint64_t        ce_adm_ce_credit_oflow_detail;          /* 0x000168 */
+        uint64_t        ce_adm_tx_link_idle_max_timer;          /* 0x000170 */
+        uint64_t        ce_adm_pcie_debug_sel;                  /* 0x000178 */
+        uint64_t        ce_pad_000180[16];          /* 0x000180 -- 0x0001F8 */
+
+        uint64_t        ce_adm_pcie_debug_sel_top;              /* 0x000200 */
+        uint64_t        ce_adm_pcie_debug_lat_sel_lo_top;       /* 0x000208 */
+        uint64_t        ce_adm_pcie_debug_lat_sel_hi_top;       /* 0x000210 */
+        uint64_t        ce_adm_pcie_debug_trig_sel_top;         /* 0x000218 */
+        uint64_t        ce_adm_pcie_debug_trig_lat_sel_lo_top;  /* 0x000220 */
+        uint64_t        ce_adm_pcie_debug_trig_lat_sel_hi_top;  /* 0x000228 */
+        uint64_t        ce_adm_pcie_trig_compare_top;           /* 0x000230 */
+        uint64_t        ce_adm_pcie_trig_compare_en_top;        /* 0x000238 */
+        uint64_t        ce_adm_ssp_debug_sel_top;               /* 0x000240 */
+        uint64_t        ce_adm_ssp_debug_lat_sel_lo_top;        /* 0x000248 */
+        uint64_t        ce_adm_ssp_debug_lat_sel_hi_top;        /* 0x000250 */
+        uint64_t        ce_adm_ssp_debug_trig_sel_top;          /* 0x000258 */
+        uint64_t        ce_adm_ssp_debug_trig_lat_sel_lo_top;   /* 0x000260 */
+        uint64_t        ce_adm_ssp_debug_trig_lat_sel_hi_top;   /* 0x000268 */
+        uint64_t        ce_adm_ssp_trig_compare_top;            /* 0x000270 */
+        uint64_t        ce_adm_ssp_trig_compare_en_top;         /* 0x000278 */
+        uint64_t        ce_pad_000280[48];          /* 0x000280 -- 0x0003F8 */
+
+        uint64_t        ce_adm_bap_ctrl;                        /* 0x000400 */
+        uint64_t        ce_pad_000408[127];         /* 0x000408 -- 0x0007F8 */
+
+        uint64_t        ce_msg_buf_data63_0[35];    /* 0x000800 -- 0x000918 */
+        uint64_t        ce_pad_000920[29];          /* 0x000920 -- 0x0009F8 */
+
+        uint64_t        ce_msg_buf_data127_64[35];  /* 0x000A00 -- 0x000B18 */
+        uint64_t        ce_pad_000B20[29];          /* 0x000B20 -- 0x000BF8 */
+
+        uint64_t        ce_msg_buf_parity[35];      /* 0x000C00 -- 0x000D18 */
+        uint64_t        ce_pad_000D20[29];          /* 0x000D20 -- 0x000DF8 */
+
+        uint64_t        ce_pad_000E00[576];         /* 0x000E00 -- 0x001FF8 */
+
+        /*
+         * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
+         * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
+         * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
+         */
+        #define ce_lsi(link_num)        ce_lsi[link_num-1]
+        struct ce_lsi_reg {
+                uint64_t        ce_lsi_lpu_id;                  /* 0x00z000 */
+                uint64_t        ce_lsi_rst;                     /* 0x00z008 */
+                uint64_t        ce_lsi_dbg_stat;                /* 0x00z010 */
+                uint64_t        ce_lsi_dbg_cfg;                 /* 0x00z018 */
+                uint64_t        ce_lsi_ltssm_ctrl;              /* 0x00z020 */
+                uint64_t        ce_lsi_lk_stat;                 /* 0x00z028 */
+                uint64_t        ce_pad_00z030[2];   /* 0x00z030 -- 0x00z038 */
+                uint64_t        ce_lsi_int_and_stat;            /* 0x00z040 */
+                uint64_t        ce_lsi_int_mask;                /* 0x00z048 */
+                uint64_t        ce_pad_00z050[22];  /* 0x00z050 -- 0x00z0F8 */
+                uint64_t        ce_lsi_lk_perf_cnt_sel;         /* 0x00z100 */
+                uint64_t        ce_pad_00z108;                  /* 0x00z108 */
+                uint64_t        ce_lsi_lk_perf_cnt_ctrl;        /* 0x00z110 */
+                uint64_t        ce_pad_00z118;                  /* 0x00z118 */
+                uint64_t        ce_lsi_lk_perf_cnt1;            /* 0x00z120 */
+                uint64_t        ce_lsi_lk_perf_cnt1_test;       /* 0x00z128 */
+                uint64_t        ce_lsi_lk_perf_cnt2;            /* 0x00z130 */
+                uint64_t        ce_lsi_lk_perf_cnt2_test;       /* 0x00z138 */
+                uint64_t        ce_pad_00z140[24];  /* 0x00z140 -- 0x00z1F8 */
+                uint64_t        ce_lsi_lk_lyr_cfg;              /* 0x00z200 */
+                uint64_t        ce_lsi_lk_lyr_status;           /* 0x00z208 */
+                uint64_t        ce_lsi_lk_lyr_int_stat;         /* 0x00z210 */
+                uint64_t        ce_lsi_lk_ly_int_stat_test;     /* 0x00z218 */
+                uint64_t        ce_lsi_lk_ly_int_stat_mask;     /* 0x00z220 */
+                uint64_t        ce_pad_00z228[3];   /* 0x00z228 -- 0x00z238 */
+                uint64_t        ce_lsi_fc_upd_ctl;              /* 0x00z240 */
+                uint64_t        ce_pad_00z248[3];   /* 0x00z248 -- 0x00z258 */
+                uint64_t        ce_lsi_flw_ctl_upd_to_timer;    /* 0x00z260 */
+                uint64_t        ce_lsi_flw_ctl_upd_timer0;      /* 0x00z268 */
+                uint64_t        ce_lsi_flw_ctl_upd_timer1;      /* 0x00z270 */
+                uint64_t        ce_pad_00z278[49];  /* 0x00z278 -- 0x00z3F8 */
+                uint64_t        ce_lsi_freq_nak_lat_thrsh;      /* 0x00z400 */
+                uint64_t        ce_lsi_ack_nak_lat_tmr;         /* 0x00z408 */
+                uint64_t        ce_lsi_rply_tmr_thr;            /* 0x00z410 */
+                uint64_t        ce_lsi_rply_tmr;                /* 0x00z418 */
+                uint64_t        ce_lsi_rply_num_stat;           /* 0x00z420 */
+                uint64_t        ce_lsi_rty_buf_max_addr;        /* 0x00z428 */
+                uint64_t        ce_lsi_rty_fifo_ptr;            /* 0x00z430 */
+                uint64_t        ce_lsi_rty_fifo_rd_wr_ptr;      /* 0x00z438 */
+                uint64_t        ce_lsi_rty_fifo_cred;           /* 0x00z440 */
+                uint64_t        ce_lsi_seq_cnt;                 /* 0x00z448 */
+                uint64_t        ce_lsi_ack_sent_seq_num;        /* 0x00z450 */
+                uint64_t        ce_lsi_seq_cnt_fifo_max_addr;   /* 0x00z458 */
+                uint64_t        ce_lsi_seq_cnt_fifo_ptr;        /* 0x00z460 */
+                uint64_t        ce_lsi_seq_cnt_rd_wr_ptr;       /* 0x00z468 */
+                uint64_t        ce_lsi_tx_lk_ts_ctl;            /* 0x00z470 */
+                uint64_t        ce_pad_00z478;                  /* 0x00z478 */
+                uint64_t        ce_lsi_mem_addr_ctl;            /* 0x00z480 */
+                uint64_t        ce_lsi_mem_d_ld0;               /* 0x00z488 */
+                uint64_t        ce_lsi_mem_d_ld1;               /* 0x00z490 */
+                uint64_t        ce_lsi_mem_d_ld2;               /* 0x00z498 */
+                uint64_t        ce_lsi_mem_d_ld3;               /* 0x00z4A0 */
+                uint64_t        ce_lsi_mem_d_ld4;               /* 0x00z4A8 */
+                uint64_t        ce_pad_00z4B0[2];   /* 0x00z4B0 -- 0x00z4B8 */
+                uint64_t        ce_lsi_rty_d_cnt;               /* 0x00z4C0 */
+                uint64_t        ce_lsi_seq_buf_cnt;             /* 0x00z4C8 */
+                uint64_t        ce_lsi_seq_buf_bt_d;            /* 0x00z4D0 */
+                uint64_t        ce_pad_00z4D8;                  /* 0x00z4D8 */
+                uint64_t        ce_lsi_ack_lat_thr;             /* 0x00z4E0 */
+                uint64_t        ce_pad_00z4E8[3];   /* 0x00z4E8 -- 0x00z4F8 */
+                uint64_t        ce_lsi_nxt_rcv_seq_1_cntr;      /* 0x00z500 */
+                uint64_t        ce_lsi_unsp_dllp_rcvd;          /* 0x00z508 */
+                uint64_t        ce_lsi_rcv_lk_ts_ctl;           /* 0x00z510 */
+                uint64_t        ce_pad_00z518[29];  /* 0x00z518 -- 0x00z5F8 */
+                uint64_t        ce_lsi_phy_lyr_cfg;             /* 0x00z600 */
+                uint64_t        ce_pad_00z608;                  /* 0x00z608 */
+                uint64_t        ce_lsi_phy_lyr_int_stat;        /* 0x00z610 */
+                uint64_t        ce_lsi_phy_lyr_int_stat_test;   /* 0x00z618 */
+                uint64_t        ce_lsi_phy_lyr_int_mask;        /* 0x00z620 */
+                uint64_t        ce_pad_00z628[11];  /* 0x00z628 -- 0x00z678 */
+                uint64_t        ce_lsi_rcv_phy_cfg;             /* 0x00z680 */
+                uint64_t        ce_lsi_rcv_phy_stat1;           /* 0x00z688 */
+                uint64_t        ce_lsi_rcv_phy_stat2;           /* 0x00z690 */
+                uint64_t        ce_lsi_rcv_phy_stat3;           /* 0x00z698 */
+                uint64_t        ce_lsi_rcv_phy_int_stat;        /* 0x00z6A0 */
+                uint64_t        ce_lsi_rcv_phy_int_stat_test;   /* 0x00z6A8 */
+                uint64_t        ce_lsi_rcv_phy_int_mask;        /* 0x00z6B0 */
+                uint64_t        ce_pad_00z6B8[9];   /* 0x00z6B8 -- 0x00z6F8 */
+                uint64_t        ce_lsi_tx_phy_cfg;              /* 0x00z700 */
+                uint64_t        ce_lsi_tx_phy_stat;             /* 0x00z708 */
+                uint64_t        ce_lsi_tx_phy_int_stat;         /* 0x00z710 */
+                uint64_t        ce_lsi_tx_phy_int_stat_test;    /* 0x00z718 */
+                uint64_t        ce_lsi_tx_phy_int_mask;         /* 0x00z720 */
+                uint64_t        ce_lsi_tx_phy_stat2;            /* 0x00z728 */
+                uint64_t        ce_pad_00z730[10];  /* 0x00z730 -- 0x00z77F */
+                uint64_t        ce_lsi_ltssm_cfg1;              /* 0x00z780 */
+                uint64_t        ce_lsi_ltssm_cfg2;              /* 0x00z788 */
+                uint64_t        ce_lsi_ltssm_cfg3;              /* 0x00z790 */
+                uint64_t        ce_lsi_ltssm_cfg4;              /* 0x00z798 */
+                uint64_t        ce_lsi_ltssm_cfg5;              /* 0x00z7A0 */
+                uint64_t        ce_lsi_ltssm_stat1;             /* 0x00z7A8 */
+                uint64_t        ce_lsi_ltssm_stat2;             /* 0x00z7B0 */
+                uint64_t        ce_lsi_ltssm_int_stat;          /* 0x00z7B8 */
+                uint64_t        ce_lsi_ltssm_int_stat_test;     /* 0x00z7C0 */
+                uint64_t        ce_lsi_ltssm_int_mask;          /* 0x00z7C8 */
+                uint64_t        ce_lsi_ltssm_stat_wr_en;        /* 0x00z7D0 */
+                uint64_t        ce_pad_00z7D8[5];   /* 0x00z7D8 -- 0x00z7F8 */
+                uint64_t        ce_lsi_gb_cfg1;                 /* 0x00z800 */
+                uint64_t        ce_lsi_gb_cfg2;                 /* 0x00z808 */
+                uint64_t        ce_lsi_gb_cfg3;                 /* 0x00z810 */
+                uint64_t        ce_lsi_gb_cfg4;                 /* 0x00z818 */
+                uint64_t        ce_lsi_gb_stat;                 /* 0x00z820 */
+                uint64_t        ce_lsi_gb_int_stat;             /* 0x00z828 */
+                uint64_t        ce_lsi_gb_int_stat_test;        /* 0x00z830 */
+                uint64_t        ce_lsi_gb_int_mask;             /* 0x00z838 */
+                uint64_t        ce_lsi_gb_pwr_dn1;              /* 0x00z840 */
+                uint64_t        ce_lsi_gb_pwr_dn2;              /* 0x00z848 */
+                uint64_t        ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
+        } ce_lsi[2];
+
+        uint64_t        ce_pad_004000[10];          /* 0x004000 -- 0x004048 */
+
+        /*
+         * CRM: Coretalk Receive Module Registers
+         */
+        uint64_t        ce_crm_debug_mux;                       /* 0x004050 */
+        uint64_t        ce_pad_004058;                          /* 0x004058 */
+        uint64_t        ce_crm_ssp_err_cmd_wrd;                 /* 0x004060 */
+        uint64_t        ce_crm_ssp_err_addr;                    /* 0x004068 */
+        uint64_t        ce_crm_ssp_err_syn;                     /* 0x004070 */
+
+        uint64_t        ce_pad_004078[499];         /* 0x004078 -- 0x005008 */
+
+        /*
+         * CXM: Coretalk Xmit Module Registers
+         */
+        uint64_t        ce_cxm_dyn_credit_status;               /* 0x005010 */
+        uint64_t        ce_cxm_last_credit_status;              /* 0x005018 */
+        uint64_t        ce_cxm_credit_limit;                    /* 0x005020 */
+        uint64_t        ce_cxm_force_credit;                    /* 0x005028 */
+        uint64_t        ce_cxm_disable_bypass;                  /* 0x005030 */
+        uint64_t        ce_pad_005038[3];           /* 0x005038 -- 0x005048 */
+        uint64_t        ce_cxm_debug_mux;                       /* 0x005050 */
+
+        uint64_t        ce_pad_005058[501];         /* 0x005058 -- 0x005FF8 */
+
+        /*
+         * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+         * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
+         * DTL: the comment offsets at far right: let 'y' = {6 or 8}
+         *
+         * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+         * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
+         * UTL: the comment offsets at far right: let 'z' = {7 or 9}
+         */
+        #define ce_dtl(link_num)        ce_dtl_utl[link_num-1]
+        #define ce_utl(link_num)        ce_dtl_utl[link_num-1]
+        struct ce_dtl_utl_reg {
+                /* DTL */
+                uint64_t        ce_dtl_dtdr_credit_limit;       /* 0x00y000 */
+                uint64_t        ce_dtl_dtdr_credit_force;       /* 0x00y008 */
+                uint64_t        ce_dtl_dyn_credit_status;       /* 0x00y010 */
+                uint64_t        ce_dtl_dtl_last_credit_stat;    /* 0x00y018 */
+                uint64_t        ce_dtl_dtl_ctrl;                /* 0x00y020 */
+                uint64_t        ce_pad_00y028[5];   /* 0x00y028 -- 0x00y048 */
+                uint64_t        ce_dtl_debug_sel;               /* 0x00y050 */
+                uint64_t        ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
+
+                /* UTL */
+                uint64_t        ce_utl_utl_ctrl;                /* 0x00z000 */
+                uint64_t        ce_utl_debug_sel;               /* 0x00z008 */
+                uint64_t        ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
+        } ce_dtl_utl[2];
+
+        uint64_t        ce_pad_00A000[514];         /* 0x00A000 -- 0x00B008 */
+
+        /*
+         * URE: Upstream Request Engine
+         */
+        uint64_t        ce_ure_dyn_credit_status;               /* 0x00B010 */
+        uint64_t        ce_ure_last_credit_status;              /* 0x00B018 */
+        uint64_t        ce_ure_credit_limit;                    /* 0x00B020 */
+        uint64_t        ce_pad_00B028;                          /* 0x00B028 */
+        uint64_t        ce_ure_control;                         /* 0x00B030 */
+        uint64_t        ce_ure_status;                          /* 0x00B038 */
+        uint64_t        ce_pad_00B040[2];           /* 0x00B040 -- 0x00B048 */
+        uint64_t        ce_ure_debug_sel;                       /* 0x00B050 */
+        uint64_t        ce_ure_pcie_debug_sel;                  /* 0x00B058 */
+        uint64_t        ce_ure_ssp_err_cmd_wrd;                 /* 0x00B060 */
+        uint64_t        ce_ure_ssp_err_addr;                    /* 0x00B068 */
+        uint64_t        ce_ure_page_map;                        /* 0x00B070 */
+        uint64_t        ce_ure_dir_map[TIOCE_NUM_PORTS];        /* 0x00B078 */
+        uint64_t        ce_ure_pipe_sel1;                       /* 0x00B088 */
+        uint64_t        ce_ure_pipe_mask1;                      /* 0x00B090 */
+        uint64_t        ce_ure_pipe_sel2;                       /* 0x00B098 */
+        uint64_t        ce_ure_pipe_mask2;                      /* 0x00B0A0 */
+        uint64_t        ce_ure_pcie1_credits_sent;              /* 0x00B0A8 */
+        uint64_t        ce_ure_pcie1_credits_used;              /* 0x00B0B0 */
+        uint64_t        ce_ure_pcie1_credit_limit;              /* 0x00B0B8 */
+        uint64_t        ce_ure_pcie2_credits_sent;              /* 0x00B0C0 */
+        uint64_t        ce_ure_pcie2_credits_used;              /* 0x00B0C8 */
+        uint64_t        ce_ure_pcie2_credit_limit;              /* 0x00B0D0 */
+        uint64_t        ce_ure_pcie_force_credit;               /* 0x00B0D8 */
+        uint64_t        ce_ure_rd_tnum_val;                     /* 0x00B0E0 */
+        uint64_t        ce_ure_rd_tnum_rsp_rcvd;                /* 0x00B0E8 */
+        uint64_t        ce_ure_rd_tnum_esent_timer;             /* 0x00B0F0 */
+        uint64_t        ce_ure_rd_tnum_error;                   /* 0x00B0F8 */
+        uint64_t        ce_ure_rd_tnum_first_cl;                /* 0x00B100 */
+        uint64_t        ce_ure_rd_tnum_link_buf;                /* 0x00B108 */
+        uint64_t        ce_ure_wr_tnum_val;                     /* 0x00B110 */
+        uint64_t        ce_ure_sram_err_addr0;                  /* 0x00B118 */
+        uint64_t        ce_ure_sram_err_addr1;                  /* 0x00B120 */
+        uint64_t        ce_ure_sram_err_addr2;                  /* 0x00B128 */
+        uint64_t        ce_ure_sram_rd_addr0;                   /* 0x00B130 */
+        uint64_t        ce_ure_sram_rd_addr1;                   /* 0x00B138 */
+        uint64_t        ce_ure_sram_rd_addr2;                   /* 0x00B140 */
+        uint64_t        ce_ure_sram_wr_addr0;                   /* 0x00B148 */
+        uint64_t        ce_ure_sram_wr_addr1;                   /* 0x00B150 */
+        uint64_t        ce_ure_sram_wr_addr2;                   /* 0x00B158 */
+        uint64_t        ce_ure_buf_flush10;                     /* 0x00B160 */
+        uint64_t        ce_ure_buf_flush11;                     /* 0x00B168 */
+        uint64_t        ce_ure_buf_flush12;                     /* 0x00B170 */
+        uint64_t        ce_ure_buf_flush13;                     /* 0x00B178 */
+        uint64_t        ce_ure_buf_flush20;                     /* 0x00B180 */
+        uint64_t        ce_ure_buf_flush21;                     /* 0x00B188 */
+        uint64_t        ce_ure_buf_flush22;                     /* 0x00B190 */
+        uint64_t        ce_ure_buf_flush23;                     /* 0x00B198 */
+        uint64_t        ce_ure_pcie_control1;                   /* 0x00B1A0 */
+        uint64_t        ce_ure_pcie_control2;                   /* 0x00B1A8 */
+
+        uint64_t        ce_pad_00B1B0[458];         /* 0x00B1B0 -- 0x00BFF8 */
+
+        /* Upstream Data Buffer, Port1 */
+        struct ce_ure_maint_ups_dat1_data {
+                uint64_t        data63_0[512];      /* 0x00C000 -- 0x00CFF8 */
+                uint64_t        data127_64[512];    /* 0x00D000 -- 0x00DFF8 */
+                uint64_t        parity[512];        /* 0x00E000 -- 0x00EFF8 */
+        } ce_ure_maint_ups_dat1;
+
+        /* Upstream Header Buffer, Port1 */
+        struct ce_ure_maint_ups_hdr1_data {
+                uint64_t        data63_0[512];      /* 0x00F000 -- 0x00FFF8 */
+                uint64_t        data127_64[512];    /* 0x010000 -- 0x010FF8 */
+                uint64_t        parity[512];        /* 0x011000 -- 0x011FF8 */
+        } ce_ure_maint_ups_hdr1;
+
+        /* Upstream Data Buffer, Port2 */
+        struct ce_ure_maint_ups_dat2_data {
+                uint64_t        data63_0[512];      /* 0x012000 -- 0x012FF8 */
+                uint64_t        data127_64[512];    /* 0x013000 -- 0x013FF8 */
+                uint64_t        parity[512];        /* 0x014000 -- 0x014FF8 */
+        } ce_ure_maint_ups_dat2;
+
+        /* Upstream Header Buffer, Port2 */
+        struct ce_ure_maint_ups_hdr2_data {
+                uint64_t        data63_0[512];      /* 0x015000 -- 0x015FF8 */
+                uint64_t        data127_64[512];    /* 0x016000 -- 0x016FF8 */
+                uint64_t        parity[512];        /* 0x017000 -- 0x017FF8 */
+        } ce_ure_maint_ups_hdr2;
+
+        /* Downstream Data Buffer */
+        struct ce_ure_maint_dns_dat_data {
+                uint64_t        data63_0[512];      /* 0x018000 -- 0x018FF8 */
+                uint64_t        data127_64[512];    /* 0x019000 -- 0x019FF8 */
+                uint64_t        parity[512];        /* 0x01A000 -- 0x01AFF8 */
+        } ce_ure_maint_dns_dat;
+
+        /* Downstream Header Buffer */
+        struct  ce_ure_maint_dns_hdr_data {
+                uint64_t        data31_0[64];       /* 0x01B000 -- 0x01B1F8 */
+                uint64_t        data95_32[64];      /* 0x01B200 -- 0x01B3F8 */
+                uint64_t        parity[64];         /* 0x01B400 -- 0x01B5F8 */
+        } ce_ure_maint_dns_hdr;
+
+        /* RCI Buffer Data */
+        struct  ce_ure_maint_rci_data {
+                uint64_t        data41_0[64];       /* 0x01B600 -- 0x01B7F8 */
+                uint64_t        data69_42[64];      /* 0x01B800 -- 0x01B9F8 */
+        } ce_ure_maint_rci;
+
+        /* Response Queue */
+        uint64_t        ce_ure_maint_rspq[64];      /* 0x01BA00 -- 0x01BBF8 */
+
+        uint64_t        ce_pad_01C000[4224];        /* 0x01BC00 -- 0x023FF8 */
+
+        /* Admin Build-a-Packet Buffer */
+        struct  ce_adm_maint_bap_buf_data {
+                uint64_t        data63_0[258];      /* 0x024000 -- 0x024808 */
+                uint64_t        data127_64[258];    /* 0x024810 -- 0x025018 */
+                uint64_t        parity[258];        /* 0x025020 -- 0x025828 */
+        } ce_adm_maint_bap_buf;
+
+        uint64_t        ce_pad_025830[5370];        /* 0x025830 -- 0x02FFF8 */
+
+        /* URE: 40bit PMU ATE Buffer */             /* 0x030000 -- 0x037FF8 */
+        uint64_t        ce_ure_ate40[TIOCE_NUM_M40_ATES];
+
+        /* URE: 32/40bit PMU ATE Buffer */          /* 0x038000 -- 0x03BFF8 */
+        uint64_t        ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
+
+        uint64_t        ce_pad_03C000[2050];        /* 0x03C000 -- 0x040008 */
+
+        /*
+         * DRE: Down Stream Request Engine
+         */
+        uint64_t        ce_dre_dyn_credit_status1;              /* 0x040010 */
+        uint64_t        ce_dre_dyn_credit_status2;              /* 0x040018 */
+        uint64_t        ce_dre_last_credit_status1;             /* 0x040020 */
+        uint64_t        ce_dre_last_credit_status2;             /* 0x040028 */
+        uint64_t        ce_dre_credit_limit1;                   /* 0x040030 */
+        uint64_t        ce_dre_credit_limit2;                   /* 0x040038 */
+        uint64_t        ce_dre_force_credit1;                   /* 0x040040 */
+        uint64_t        ce_dre_force_credit2;                   /* 0x040048 */
+        uint64_t        ce_dre_debug_mux1;                      /* 0x040050 */
+        uint64_t        ce_dre_debug_mux2;                      /* 0x040058 */
+        uint64_t        ce_dre_ssp_err_cmd_wrd;                 /* 0x040060 */
+        uint64_t        ce_dre_ssp_err_addr;                    /* 0x040068 */
+        uint64_t        ce_dre_comp_err_cmd_wrd;                /* 0x040070 */
+        uint64_t        ce_dre_comp_err_addr;                   /* 0x040078 */
+        uint64_t        ce_dre_req_status;                      /* 0x040080 */
+        uint64_t        ce_dre_config1;                         /* 0x040088 */
+        uint64_t        ce_dre_config2;                         /* 0x040090 */
+        uint64_t        ce_dre_config_req_status;               /* 0x040098 */
+        uint64_t        ce_pad_0400A0[12];          /* 0x0400A0 -- 0x0400F8 */
+        uint64_t        ce_dre_dyn_fifo;                        /* 0x040100 */
+        uint64_t        ce_pad_040108[3];           /* 0x040108 -- 0x040118 */
+        uint64_t        ce_dre_last_fifo;                       /* 0x040120 */
+
+        uint64_t        ce_pad_040128[27];          /* 0x040128 -- 0x0401F8 */
+
+        /* DRE Downstream Head Queue */
+        struct  ce_dre_maint_ds_head_queue {
+                uint64_t        data63_0[32];       /* 0x040200 -- 0x0402F8 */
+                uint64_t        data127_64[32];     /* 0x040300 -- 0x0403F8 */
+                uint64_t        parity[32];         /* 0x040400 -- 0x0404F8 */
+        } ce_dre_maint_ds_head_q;
+
+        uint64_t        ce_pad_040500[352];         /* 0x040500 -- 0x040FF8 */
+
+        /* DRE Downstream Data Queue */
+        struct  ce_dre_maint_ds_data_queue {
+                uint64_t        data63_0[256];      /* 0x041000 -- 0x0417F8 */
+                uint64_t        ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
+                uint64_t        data127_64[256];    /* 0x042000 -- 0x0427F8 */
+                uint64_t        ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
+                uint64_t        parity[256];        /* 0x043000 -- 0x0437F8 */
+                uint64_t        ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
+        } ce_dre_maint_ds_data_q;
+
+        /* DRE URE Upstream Response Queue */
+        struct  ce_dre_maint_ure_us_rsp_queue {
+                uint64_t        data63_0[8];        /* 0x044000 -- 0x044038 */
+                uint64_t        ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
+                uint64_t        data127_64[8];      /* 0x044100 -- 0x044138 */
+                uint64_t        ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
+                uint64_t        parity[8];          /* 0x044200 -- 0x044238 */
+                uint64_t        ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
+        } ce_dre_maint_ure_us_rsp_q;
+
+        uint64_t        ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
+
+        uint64_t        ce_end_of_struct;                       /* 0x044400 */
+} tioce_t;
+
+
+/* ce_adm_int_mask/ce_adm_int_status register bit defines */
+#define CE_ADM_INT_CE_ERROR_SHFT                0
+#define CE_ADM_INT_LSI1_IP_ERROR_SHFT           1
+#define CE_ADM_INT_LSI2_IP_ERROR_SHFT           2
+#define CE_ADM_INT_PCIE_ERROR_SHFT              3
+#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT     4
+#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT     5
+#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT        6
+#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT        7
+#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT        8
+#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT        9
+#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT        10
+#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT        11
+#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT        12
+#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT        13
+#define CE_ADM_INT_PCIE_MSG_SHFT                14 /*see int_dest_14*/
+#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT         14
+#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT         15
+#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT         16
+#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT         17
+#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT        22
+#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT        23
+
+/* ce_adm_force_int register bit defines */
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT  0
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT  1
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT  2
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT  3
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT  4
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT  5
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT  6
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT  7
+#define CE_ADM_FORCE_INT_ALWAYS_SHFT            8
+
+/* ce_adm_int_dest register bit masks & shifts */
+#define INTR_VECTOR_SHFT                        56
+
+/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
+#define CE_ADM_ERR_CRM_SSP_REQ_INVALID                  (0x1ULL <<  0)
+#define CE_ADM_ERR_SSP_REQ_HEADER                       (0x1ULL <<  1)
+#define CE_ADM_ERR_SSP_RSP_HEADER                       (0x1ULL <<  2)
+#define CE_ADM_ERR_SSP_PROTOCOL_ERROR                   (0x1ULL <<  3)
+#define CE_ADM_ERR_SSP_SBE                              (0x1ULL <<  4)
+#define CE_ADM_ERR_SSP_MBE                              (0x1ULL <<  5)
+#define CE_ADM_ERR_CXM_CREDIT_OFLOW                     (0x1ULL <<  6)
+#define CE_ADM_ERR_DRE_SSP_REQ_INVAL                    (0x1ULL <<  7)
+#define CE_ADM_ERR_SSP_REQ_LONG                         (0x1ULL <<  8)
+#define CE_ADM_ERR_SSP_REQ_OFLOW                        (0x1ULL <<  9)
+#define CE_ADM_ERR_SSP_REQ_SHORT                        (0x1ULL << 10)
+#define CE_ADM_ERR_SSP_REQ_SIDEBAND                     (0x1ULL << 11)
+#define CE_ADM_ERR_SSP_REQ_ADDR_ERR                     (0x1ULL << 12)
+#define CE_ADM_ERR_SSP_REQ_BAD_BE                       (0x1ULL << 13)
+#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT                   (0x1ULL << 14)
+#define CE_ADM_ERR_PCIE_UNEXP_COMPL                     (0x1ULL << 15)
+#define CE_ADM_ERR_PCIE_ERR_COMPL                       (0x1ULL << 16)
+#define CE_ADM_ERR_DRE_CREDIT_OFLOW                     (0x1ULL << 17)
+#define CE_ADM_ERR_DRE_SRAM_PE                          (0x1ULL << 18)
+#define CE_ADM_ERR_SSP_RSP_INVALID                      (0x1ULL << 19)
+#define CE_ADM_ERR_SSP_RSP_LONG                         (0x1ULL << 20)
+#define CE_ADM_ERR_SSP_RSP_SHORT                        (0x1ULL << 21)
+#define CE_ADM_ERR_SSP_RSP_SIDEBAND                     (0x1ULL << 22)
+#define CE_ADM_ERR_URE_SSP_RSP_UNEXP                    (0x1ULL << 23)
+#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT               (0x1ULL << 24)
+#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT               (0x1ULL << 25)
+#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT               (0x1ULL << 26)
+#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT                 (0x1ULL << 27)
+#define CE_ADM_ERR_URE_CREDIT_OFLOW                     (0x1ULL << 28)
+#define CE_ADM_ERR_URE_SRAM_PE                          (0x1ULL << 29)
+#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP                    (0x1ULL << 30)
+#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT                  (0x1ULL << 31)
+#define CE_ADM_ERR_MMR_ACCESS_ERROR                     (0x1ULL << 32)
+#define CE_ADM_ERR_MMR_ADDR_ERROR                       (0x1ULL << 33)
+#define CE_ADM_ERR_ADM_CREDIT_OFLOW                     (0x1ULL << 34)
+#define CE_ADM_ERR_ADM_SRAM_PE                          (0x1ULL << 35)
+#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR            (0x1ULL << 36)
+#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR         (0x1ULL << 37)
+#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR        (0x1ULL << 38)
+#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR       (0x1ULL << 39)
+#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR            (0x1ULL << 40)
+#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR             (0x1ULL << 41)
+#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR         (0x1ULL << 42)
+#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR          (0x1ULL << 43)
+#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR          (0x1ULL << 44)
+#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR           (0x1ULL << 45)
+#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR            (0x1ULL << 46)
+#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR         (0x1ULL << 47)
+#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR        (0x1ULL << 48)
+#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR       (0x1ULL << 49)
+#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR            (0x1ULL << 50)
+#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR             (0x1ULL << 51)
+#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR         (0x1ULL << 52)
+#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR          (0x1ULL << 53)
+#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR          (0x1ULL << 54)
+#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR           (0x1ULL << 55)
+#define CE_ADM_ERR_PORT1_PCIE_COR_ERR                   (0x1ULL << 56)
+#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR                  (0x1ULL << 57)
+#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR                   (0x1ULL << 58)
+#define CE_ADM_ERR_PORT2_PCIE_COR_ERR                   (0x1ULL << 59)
+#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR                  (0x1ULL << 60)
+#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR                   (0x1ULL << 61)
+
+/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
+#define FLUSH_SEL_PORT1_PIPE0_SHFT      0
+#define FLUSH_SEL_PORT1_PIPE1_SHFT      4
+#define FLUSH_SEL_PORT1_PIPE2_SHFT      8
+#define FLUSH_SEL_PORT1_PIPE3_SHFT      12
+#define FLUSH_SEL_PORT2_PIPE0_SHFT      16
+#define FLUSH_SEL_PORT2_PIPE1_SHFT      20
+#define FLUSH_SEL_PORT2_PIPE2_SHFT      24
+#define FLUSH_SEL_PORT2_PIPE3_SHFT      28
+
+/* ce_dre_config1 register bit masks and shifts */
+#define CE_DRE_RO_ENABLE                (0x1ULL << 0)
+#define CE_DRE_DYN_RO_ENABLE            (0x1ULL << 1)
+#define CE_DRE_SUP_CONFIG_COMP_ERROR    (0x1ULL << 2)
+#define CE_DRE_SUP_IO_COMP_ERROR        (0x1ULL << 3)
+#define CE_DRE_ADDR_MODE_SHFT           4
+
+/* ce_dre_config_req_status register bit masks */
+#define CE_DRE_LAST_CONFIG_COMPLETION   (0x7ULL << 0)
+#define CE_DRE_DOWNSTREAM_CONFIG_ERROR  (0x1ULL << 3)
+#define CE_DRE_CONFIG_COMPLETION_VALID  (0x1ULL << 4)
+#define CE_DRE_CONFIG_REQUEST_ACTIVE    (0x1ULL << 5)
+
+/* ce_ure_control register bit masks & shifts */
+#define CE_URE_RD_MRG_ENABLE            (0x1ULL << 0)
+#define CE_URE_WRT_MRG_ENABLE1          (0x1ULL << 4)
+#define CE_URE_WRT_MRG_ENABLE2          (0x1ULL << 5)
+#define CE_URE_RSPQ_BYPASS_DISABLE      (0x1ULL << 24)
+#define CE_URE_UPS_DAT1_PAR_DISABLE     (0x1ULL << 32)
+#define CE_URE_UPS_HDR1_PAR_DISABLE     (0x1ULL << 33)
+#define CE_URE_UPS_DAT2_PAR_DISABLE     (0x1ULL << 34)
+#define CE_URE_UPS_HDR2_PAR_DISABLE     (0x1ULL << 35)
+#define CE_URE_ATE_PAR_DISABLE          (0x1ULL << 36)
+#define CE_URE_RCI_PAR_DISABLE          (0x1ULL << 37)
+#define CE_URE_RSPQ_PAR_DISABLE         (0x1ULL << 38)
+#define CE_URE_DNS_DAT_PAR_DISABLE      (0x1ULL << 39)
+#define CE_URE_DNS_HDR_PAR_DISABLE      (0x1ULL << 40)
+#define CE_URE_MALFORM_DISABLE          (0x1ULL << 44)
+#define CE_URE_UNSUP_DISABLE            (0x1ULL << 45)
+
+/* ce_ure_page_map register bit masks & shifts */
+#define CE_URE_ATE3240_ENABLE           (0x1ULL << 0)
+#define CE_URE_ATE40_ENABLE             (0x1ULL << 1)
+#define CE_URE_PAGESIZE_SHFT            4
+#define CE_URE_PAGESIZE_MASK            (0x7ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_4K_PAGESIZE              (0x0ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_16K_PAGESIZE             (0x1ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_64K_PAGESIZE             (0x2ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_128K_PAGESIZE            (0x3ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_256K_PAGESIZE            (0x4ULL << CE_URE_PAGESIZE_SHFT)
+
+/* ce_ure_pipe_sel register bit masks & shifts */
+#define PKT_TRAFIC_SHRT                 16
+#define BUS_SRC_ID_SHFT                 8
+#define DEV_SRC_ID_SHFT                 3
+#define FNC_SRC_ID_SHFT                 0
+#define CE_URE_TC_MASK                  (0x07ULL << PKT_TRAFIC_SHRT)
+#define CE_URE_BUS_MASK                 (0xFFULL << BUS_SRC_ID_SHFT)
+#define CE_URE_DEV_MASK                 (0x1FULL << DEV_SRC_ID_SHFT)
+#define CE_URE_FNC_MASK                 (0x07ULL << FNC_SRC_ID_SHFT)
+#define CE_URE_PIPE_BUS(b)              (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \
+                                         CE_URE_BUS_MASK)
+#define CE_URE_PIPE_DEV(d)              (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \
+                                         CE_URE_DEV_MASK)
+#define CE_URE_PIPE_FNC(f)              (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \
+                                         CE_URE_FNC_MASK)
+
+#define CE_URE_SEL1_SHFT                0
+#define CE_URE_SEL2_SHFT                20
+#define CE_URE_SEL3_SHFT                40
+#define CE_URE_SEL1_MASK                (0x7FFFFULL << CE_URE_SEL1_SHFT)
+#define CE_URE_SEL2_MASK                (0x7FFFFULL << CE_URE_SEL2_SHFT)
+#define CE_URE_SEL3_MASK                (0x7FFFFULL << CE_URE_SEL3_SHFT)
+
+
+/* ce_ure_pipe_mask register bit masks & shifts */
+#define CE_URE_MASK1_SHFT               0
+#define CE_URE_MASK2_SHFT               20
+#define CE_URE_MASK3_SHFT               40
+#define CE_URE_MASK1_MASK               (0x7FFFFULL << CE_URE_MASK1_SHFT)
+#define CE_URE_MASK2_MASK               (0x7FFFFULL << CE_URE_MASK2_SHFT)
+#define CE_URE_MASK3_MASK               (0x7FFFFULL << CE_URE_MASK3_SHFT)
+
+
+/* ce_ure_pcie_control1 register bit masks & shifts */
+#define CE_URE_SI                       (0x1ULL << 0)
+#define CE_URE_ELAL_SHFT                4
+#define CE_URE_ELAL_MASK                (0x7ULL << CE_URE_ELAL_SHFT)
+#define CE_URE_ELAL1_SHFT               8
+#define CE_URE_ELAL1_MASK               (0x7ULL << CE_URE_ELAL1_SHFT)
+#define CE_URE_SCC                      (0x1ULL << 12)
+#define CE_URE_PN1_SHFT                 16
+#define CE_URE_PN1_MASK                 (0xFFULL << CE_URE_PN1_SHFT)
+#define CE_URE_PN2_SHFT                 24
+#define CE_URE_PN2_MASK                 (0xFFULL << CE_URE_PN2_SHFT)
+#define CE_URE_PN1_SET(n)               (((uint64_t)(n) << CE_URE_PN1_SHFT) & \
+                                         CE_URE_PN1_MASK)
+#define CE_URE_PN2_SET(n)               (((uint64_t)(n) << CE_URE_PN2_SHFT) & \
+                                         CE_URE_PN2_MASK)
+
+/* ce_ure_pcie_control2 register bit masks & shifts */
+#define CE_URE_ABP                      (0x1ULL << 0)
+#define CE_URE_PCP                      (0x1ULL << 1)
+#define CE_URE_MSP                      (0x1ULL << 2)
+#define CE_URE_AIP                      (0x1ULL << 3)
+#define CE_URE_PIP                      (0x1ULL << 4)
+#define CE_URE_HPS                      (0x1ULL << 5)
+#define CE_URE_HPC                      (0x1ULL << 6)
+#define CE_URE_SPLV_SHFT                7
+#define CE_URE_SPLV_MASK                (0xFFULL << CE_URE_SPLV_SHFT)
+#define CE_URE_SPLS_SHFT                15
+#define CE_URE_SPLS_MASK                (0x3ULL << CE_URE_SPLS_SHFT)
+#define CE_URE_PSN1_SHFT                19
+#define CE_URE_PSN1_MASK                (0x1FFFULL << CE_URE_PSN1_SHFT)
+#define CE_URE_PSN2_SHFT                32
+#define CE_URE_PSN2_MASK                (0x1FFFULL << CE_URE_PSN2_SHFT)
+#define CE_URE_PSN1_SET(n)              (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \
+                                         CE_URE_PSN1_MASK)
+#define CE_URE_PSN2_SET(n)              (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \
+                                         CE_URE_PSN2_MASK)
+
+/*
+ * PIO address space ranges for CE
+ */
+
+/* Local CE Registers Space */
+#define CE_PIO_MMR                      0x00000000
+#define CE_PIO_MMR_LEN                  0x04000000
+
+/* PCI Compatible Config Space */
+#define CE_PIO_CONFIG_SPACE             0x04000000
+#define CE_PIO_CONFIG_SPACE_LEN         0x04000000
+
+/* PCI I/O Space Alias */
+#define CE_PIO_IO_SPACE_ALIAS           0x08000000
+#define CE_PIO_IO_SPACE_ALIAS_LEN       0x08000000
+
+/* PCI Enhanced Config Space */
+#define CE_PIO_E_CONFIG_SPACE           0x10000000
+#define CE_PIO_E_CONFIG_SPACE_LEN       0x10000000
+
+/* PCI I/O Space */
+#define CE_PIO_IO_SPACE                 0x100000000
+#define CE_PIO_IO_SPACE_LEN             0x100000000
+
+/* PCI MEM Space */
+#define CE_PIO_MEM_SPACE                0x200000000
+#define CE_PIO_MEM_SPACE_LEN            TIO_HWIN_SIZE
+
+
+/*
+ * CE PCI Enhanced Config Space shifts & masks
+ */
+#define CE_E_CONFIG_BUS_SHFT            20
+#define CE_E_CONFIG_BUS_MASK            (0xFF << CE_E_CONFIG_BUS_SHFT)
+#define CE_E_CONFIG_DEVICE_SHFT         15
+#define CE_E_CONFIG_DEVICE_MASK         (0x1F << CE_E_CONFIG_DEVICE_SHFT)
+#define CE_E_CONFIG_FUNC_SHFT           12
+#define CE_E_CONFIG_FUNC_MASK           (0x7  << CE_E_CONFIG_FUNC_SHFT)
+
+#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
new file mode 100644
index 000000000000..7f63dec0a79a
--- /dev/null
+++ b/include/asm-ia64/sn/tioce_provider.h
@@ -0,0 +1,66 @@
+/**************************************************************************
+ *             Copyright (C) 2005, Silicon Graphics, Inc.                 *
+ *                                                                        *
+ *  These coded instructions, statements, and computer programs  contain  *
+ *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
+ *  are protected by Federal copyright law.  They  may  not be disclosed  *
+ *  to  third  parties  or copied or duplicated in any form, in whole or  *
+ *  in part, without the prior written consent of Silicon Graphics, Inc.  *
+ *                                                                        *
+ **************************************************************************/
+
+#ifndef _ASM_IA64_SN_CE_PROVIDER_H
+#define _ASM_IA64_SN_CE_PROVIDER_H
+
+#include <asm/sn/pcibus_provider_defs.h>
+#include <asm/sn/tioce.h>
+
+/*
+ * Common TIOCE structure shared between the prom and kernel
+ *
+ * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
+ * PROM VERSION.
+ */
+struct tioce_common {
+        struct pcibus_bussoft   ce_pcibus;      /* common pciio header */
+
+        uint32_t                ce_rev;
+        uint64_t                ce_kernel_private;
+        uint64_t                ce_prom_private;
+};
+
+struct tioce_kernel {
+        struct tioce_common     *ce_common;
+        spinlock_t              ce_lock;
+        struct list_head        ce_dmamap_list;
+
+        uint64_t                ce_ate40_shadow[TIOCE_NUM_M40_ATES];
+        uint64_t                ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
+        uint32_t                ce_ate3240_pagesize;
+
+        uint8_t                 ce_port1_secondary;
+
+        /* per-port resources */
+        struct {
+                int             dirmap_refcnt;
+                uint64_t        dirmap_shadow;
+        } ce_port[TIOCE_NUM_PORTS];
+};
+
+struct tioce_dmamap {
+        struct list_head        ce_dmamap_list; /* headed by tioce_kernel */
+        uint32_t                refcnt;
+
+        uint64_t                nbytes;         /* # bytes mapped */
+
+        uint64_t                ct_start;       /* coretalk start address */
+        uint64_t                pci_start;      /* bus start address */
+
+        uint64_t                *ate_hw;        /* hw ptr of first ate in map */
+        uint64_t                *ate_shadow;    /* shadow ptr of firat ate */
+        uint16_t                ate_count;      /* # ate's in the map */
+};
+
+extern int tioce_init_provider(void);
+
+#endif  /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
new file mode 100644
index 000000000000..5f2489c9d2dd
--- /dev/null
+++ b/include/asm-ia64/sn/tiocp.h
@@ -0,0 +1,256 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_TIOCP_H
+#define _ASM_IA64_SN_PCI_TIOCP_H
+
+#define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFFUL
+#define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)
+
+
+/*****************************************************************************
+ *********************** TIOCP MMR structure mapping ***************************
+ *****************************************************************************/
+
+struct tiocp{
+
+    /* 0x000000-0x00FFFF -- Local Registers */
+
+    /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
+    uint64_t            cp_id;                          /* 0x000000 */
+    uint64_t            cp_stat;                        /* 0x000008 */
+    uint64_t            cp_err_upper;                   /* 0x000010 */
+    uint64_t            cp_err_lower;                   /* 0x000018 */
+    #define cp_err cp_err_lower
+    uint64_t            cp_control;                     /* 0x000020 */
+    uint64_t            cp_req_timeout;                 /* 0x000028 */
+    uint64_t            cp_intr_upper;                  /* 0x000030 */
+    uint64_t            cp_intr_lower;                  /* 0x000038 */
+    #define cp_intr cp_intr_lower
+    uint64_t            cp_err_cmdword;                 /* 0x000040 */
+    uint64_t            _pad_000048;                    /* 0x000048 */
+    uint64_t            cp_tflush;                      /* 0x000050 */
+
+    /* 0x000058-0x00007F -- Bridge-specific Configuration */
+    uint64_t            cp_aux_err;                     /* 0x000058 */
+    uint64_t            cp_resp_upper;                  /* 0x000060 */
+    uint64_t            cp_resp_lower;                  /* 0x000068 */
+    #define cp_resp cp_resp_lower
+    uint64_t            cp_tst_pin_ctrl;                /* 0x000070 */
+    uint64_t            cp_addr_lkerr;                  /* 0x000078 */
+
+    /* 0x000080-0x00008F -- PMU & MAP */
+    uint64_t            cp_dir_map;                     /* 0x000080 */
+    uint64_t            _pad_000088;                    /* 0x000088 */
+
+    /* 0x000090-0x00009F -- SSRAM */
+    uint64_t            cp_map_fault;                   /* 0x000090 */
+    uint64_t            _pad_000098;                    /* 0x000098 */
+
+    /* 0x0000A0-0x0000AF -- Arbitration */
+    uint64_t            cp_arb;                         /* 0x0000A0 */
+    uint64_t            _pad_0000A8;                    /* 0x0000A8 */
+
+    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+    uint64_t            cp_ate_parity_err;              /* 0x0000B0 */
+    uint64_t            _pad_0000B8;                    /* 0x0000B8 */
+
+    /* 0x0000C0-0x0000FF -- PCI/GIO */
+    uint64_t            cp_bus_timeout;                 /* 0x0000C0 */
+    uint64_t            cp_pci_cfg;                     /* 0x0000C8 */
+    uint64_t            cp_pci_err_upper;               /* 0x0000D0 */
+    uint64_t            cp_pci_err_lower;               /* 0x0000D8 */
+    #define cp_pci_err cp_pci_err_lower
+    uint64_t            _pad_0000E0[4];                 /* 0x0000{E0..F8} */
+
+    /* 0x000100-0x0001FF -- Interrupt */
+    uint64_t            cp_int_status;                  /* 0x000100 */
+    uint64_t            cp_int_enable;                  /* 0x000108 */
+    uint64_t            cp_int_rst_stat;                /* 0x000110 */
+    uint64_t            cp_int_mode;                    /* 0x000118 */
+    uint64_t            cp_int_device;                  /* 0x000120 */
+    uint64_t            cp_int_host_err;                /* 0x000128 */
+    uint64_t            cp_int_addr[8];                 /* 0x0001{30,,,68} */
+    uint64_t            cp_err_int_view;                /* 0x000170 */
+    uint64_t            cp_mult_int;                    /* 0x000178 */
+    uint64_t            cp_force_always[8];             /* 0x0001{80,,,B8} */
+    uint64_t            cp_force_pin[8];                /* 0x0001{C0,,,F8} */
+
+    /* 0x000200-0x000298 -- Device */
+    uint64_t            cp_device[4];                   /* 0x0002{00,,,18} */
+    uint64_t            _pad_000220[4];                 /* 0x0002{20,,,38} */
+    uint64_t            cp_wr_req_buf[4];               /* 0x0002{40,,,58} */
+    uint64_t            _pad_000260[4];                 /* 0x0002{60,,,78} */
+    uint64_t            cp_rrb_map[2];                  /* 0x0002{80,,,88} */
+    #define cp_even_resp cp_rrb_map[0]                  /* 0x000280 */
+    #define cp_odd_resp  cp_rrb_map[1]                  /* 0x000288 */
+    uint64_t            cp_resp_status;                 /* 0x000290 */
+    uint64_t            cp_resp_clear;                  /* 0x000298 */
+
+    uint64_t            _pad_0002A0[12];                /* 0x0002{A0..F8} */
+
+    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+    struct {
+        uint64_t        upper;                          /* 0x0003{00,,,F0} */
+        uint64_t        lower;                          /* 0x0003{08,,,F8} */
+    } cp_buf_addr_match[16];
+
+    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+    struct {
+        uint64_t        flush_w_touch;                  /* 0x000{400,,,5C0} */
+        uint64_t        flush_wo_touch;                 /* 0x000{408,,,5C8} */
+        uint64_t        inflight;                       /* 0x000{410,,,5D0} */
+        uint64_t        prefetch;                       /* 0x000{418,,,5D8} */
+        uint64_t        total_pci_retry;                /* 0x000{420,,,5E0} */
+        uint64_t        max_pci_retry;                  /* 0x000{428,,,5E8} */
+        uint64_t        max_latency;                    /* 0x000{430,,,5F0} */
+        uint64_t        clear_all;                      /* 0x000{438,,,5F8} */
+    } cp_buf_count[8];
+
+
+    /* 0x000600-0x0009FF -- PCI/X registers */
+    uint64_t            cp_pcix_bus_err_addr;           /* 0x000600 */
+    uint64_t            cp_pcix_bus_err_attr;           /* 0x000608 */
+    uint64_t            cp_pcix_bus_err_data;           /* 0x000610 */
+    uint64_t            cp_pcix_pio_split_addr;         /* 0x000618 */
+    uint64_t            cp_pcix_pio_split_attr;         /* 0x000620 */
+    uint64_t            cp_pcix_dma_req_err_attr;       /* 0x000628 */
+    uint64_t            cp_pcix_dma_req_err_addr;       /* 0x000630 */
+    uint64_t            cp_pcix_timeout;                /* 0x000638 */
+
+    uint64_t            _pad_000640[24];                /* 0x000{640,,,6F8} */
+
+    /* 0x000700-0x000737 -- Debug Registers */
+    uint64_t            cp_ct_debug_ctl;                /* 0x000700 */
+    uint64_t            cp_br_debug_ctl;                /* 0x000708 */
+    uint64_t            cp_mux3_debug_ctl;              /* 0x000710 */
+    uint64_t            cp_mux4_debug_ctl;              /* 0x000718 */
+    uint64_t            cp_mux5_debug_ctl;              /* 0x000720 */
+    uint64_t            cp_mux6_debug_ctl;              /* 0x000728 */
+    uint64_t            cp_mux7_debug_ctl;              /* 0x000730 */
+
+    uint64_t            _pad_000738[89];                /* 0x000{738,,,9F8} */
+
+    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+    struct {
+        uint64_t        cp_buf_addr;                    /* 0x000{A00,,,AF0} */
+        uint64_t        cp_buf_attr;                    /* 0X000{A08,,,AF8} */
+    } cp_pcix_read_buf_64[16];
+
+    struct {
+        uint64_t        cp_buf_addr;                    /* 0x000{B00,,,BE0} */
+        uint64_t        cp_buf_attr;                    /* 0x000{B08,,,BE8} */
+        uint64_t        cp_buf_valid;                   /* 0x000{B10,,,BF0} */
+        uint64_t        __pad1;                         /* 0x000{B18,,,BF8} */
+    } cp_pcix_write_buf_64[8];
+
+    /* End of Local Registers -- Start of Address Map space */
+
+    char                _pad_000c00[0x010000 - 0x000c00];
+
+    /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
+    uint64_t            cp_int_ate_ram[1024];           /* 0x010000-0x011FF8 */
+
+    char                _pad_012000[0x14000 - 0x012000];
+
+    /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
+    uint64_t            cp_int_ate_ram_mp[1024];        /* 0x014000-0x015FF8 */
+
+    char                _pad_016000[0x18000 - 0x016000];
+
+    /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
+    uint64_t            cp_wr_req_lower[256];           /* 0x18000 - 0x187F8 */
+    uint64_t            cp_wr_req_upper[256];           /* 0x18800 - 0x18FF8 */
+    uint64_t            cp_wr_req_parity[256];          /* 0x19000 - 0x197F8 */
+
+    char                _pad_019800[0x1C000 - 0x019800];
+
+    /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
+    uint64_t            cp_rd_resp_lower[512];          /* 0x1C000 - 0x1CFF8 */
+    uint64_t            cp_rd_resp_upper[512];          /* 0x1D000 - 0x1DFF8 */
+    uint64_t            cp_rd_resp_parity[512];         /* 0x1E000 - 0x1EFF8 */
+
+    char                _pad_01F000[0x20000 - 0x01F000];
+
+    /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
+    char                _pad_020000[0x021000 - 0x20000];
+
+    /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
+    union {
+        uint8_t         c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
+        uint16_t        s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
+        uint32_t        l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
+        uint64_t        d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
+        union {
+            uint8_t     c[0x100 / 1];
+            uint16_t    s[0x100 / 2];
+            uint32_t    l[0x100 / 4];
+            uint64_t    d[0x100 / 8];
+        } f[8];
+    } cp_type0_cfg_dev[7];                              /* 0x02{1000,,,7FFF} */
+
+    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+    union {
+        uint8_t         c[0x1000 / 1];                  /* 0x028000-0x029000 */
+        uint16_t        s[0x1000 / 2];                  /* 0x028000-0x029000 */
+        uint32_t        l[0x1000 / 4];                  /* 0x028000-0x029000 */
+        uint64_t        d[0x1000 / 8];                  /* 0x028000-0x029000 */
+        union {
+            uint8_t     c[0x100 / 1];
+            uint16_t    s[0x100 / 2];
+            uint32_t    l[0x100 / 4];
+            uint64_t    d[0x100 / 8];
+        } f[8];
+    } cp_type1_cfg;                                     /* 0x028000-0x029000 */
+
+    char                _pad_029000[0x030000-0x029000];
+
+    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+    union {
+        uint8_t         c[8 / 1];
+        uint16_t        s[8 / 2];
+        uint32_t        l[8 / 4];
+        uint64_t        d[8 / 8];
+    } cp_pci_iack;                                      /* 0x030000-0x030007 */
+
+    char                _pad_030007[0x040000-0x030008];
+
+    /* 0x040000-0x040007 -- PCIX Special Cycle */
+    union {
+        uint8_t         c[8 / 1];
+        uint16_t        s[8 / 2];
+        uint32_t        l[8 / 4];
+        uint64_t        d[8 / 8];
+    } cp_pcix_cycle;                                    /* 0x040000-0x040007 */
+
+    char                _pad_040007[0x200000-0x040008];
+
+    /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
+    union {
+        uint8_t         c[0x100000 / 1];
+        uint16_t        s[0x100000 / 2];
+        uint32_t        l[0x100000 / 4];
+        uint64_t        d[0x100000 / 8];
+    } cp_devio_raw[6];                                  /* 0x200000-0x7FFFFF */
+
+    #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]
+
+    char                _pad_800000[0xA00000-0x800000];
+
+    /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
+    union {
+        uint8_t         c[0x100000 / 1];
+        uint16_t        s[0x100000 / 2];
+        uint32_t        l[0x100000 / 4];
+        uint64_t        d[0x100000 / 8];
+    } cp_devio_raw_flush[6];                            /* 0xA00000-0xBFFFFF */
+
+    #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
+
+};
+
+#endif  /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h
index 9902185c0288..1df1c9f61a65 100644
--- a/include/asm-ia64/sn/xp.h
+++ b/include/asm-ia64/sn/xp.h
@@ -16,7 +16,6 @@
 #define _ASM_IA64_SN_XP_H
 
 
-#include <linux/version.h>
 #include <linux/cache.h>
 #include <linux/hardirq.h>
 #include <asm/sn/types.h>
diff --git a/include/asm-ia64/socket.h b/include/asm-ia64/socket.h
index 21a9f10d6baa..a255006fb7b5 100644
--- a/include/asm-ia64/socket.h
+++ b/include/asm-ia64/socket.h
@@ -23,6 +23,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
index 909936f25512..d2430aa0d49d 100644
--- a/include/asm-ia64/spinlock.h
+++ b/include/asm-ia64/spinlock.h
@@ -93,7 +93,15 @@ _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
 # endif /* CONFIG_MCKINLEY */
 #endif
 }
+
 #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
+
+/* Unlock by doing an ordered store and releasing the cacheline with nta */
+static inline void _raw_spin_unlock(spinlock_t *x) {
+        barrier();
+        asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
+}
+
 #else /* !ASM_SUPPORTED */
 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
 # define _raw_spin_lock(x)                                                              \
@@ -109,16 +117,16 @@ do {											\
                 } while (ia64_spinlock_val);                                            \
         }                                                                               \
 } while (0)
+#define _raw_spin_unlock(x)     do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
 #endif /* !ASM_SUPPORTED */
 
 #define spin_is_locked(x)       ((x)->lock != 0)
-#define _raw_spin_unlock(x)     do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
 #define _raw_spin_trylock(x)    (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
 #define spin_unlock_wait(x)     do { barrier(); } while ((x)->lock)
 
 typedef struct {
-        volatile unsigned int read_counter      : 31;
-        volatile unsigned int write_lock        :  1;
+        volatile unsigned int read_counter      : 24;
+        volatile unsigned int write_lock        :  8;
 #ifdef CONFIG_PREEMPT
         unsigned int break_lock;
 #endif
@@ -174,6 +182,13 @@ do {										\
         (result == 0);                                                          \
 })
 
+static inline void _raw_write_unlock(rwlock_t *x)
+{
+        u8 *y = (u8 *)x;
+        barrier();
+        asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
+}
+
 #else /* !ASM_SUPPORTED */
 
 #define _raw_write_lock(l)                                                              \
@@ -195,14 +210,14 @@ do {										\
         (ia64_val == 0);                                                \
 })
 
+static inline void _raw_write_unlock(rwlock_t *x)
+{
+        barrier();
+        x->write_lock = 0;
+}
+
 #endif /* !ASM_SUPPORTED */
 
 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
 
-#define _raw_write_unlock(x)                                                            \
-({                                                                                      \
-        smp_mb__before_clear_bit();     /* need barrier before releasing lock... */     \
-        clear_bit(31, (x));                                                             \
-})
-
 #endif /*  _ASM_IA64_SPINLOCK_H */
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h
index 6f516e76d1f0..33256db4a7cf 100644
--- a/include/asm-ia64/system.h
+++ b/include/asm-ia64/system.h
@@ -19,12 +19,13 @@
 #include <asm/pal.h>
 #include <asm/percpu.h>
 
-#define GATE_ADDR               __IA64_UL_CONST(0xa000000000000000)
+#define GATE_ADDR               RGN_BASE(RGN_GATE)
+
 /*
  * 0xa000000000000000+2*PERCPU_PAGE_SIZE
  * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
  */
-#define KERNEL_START             __IA64_UL_CONST(0xa000000100000000)
+#define KERNEL_START             (GATE_ADDR+0x100000000)
 #define PERCPU_ADDR             (-PERCPU_PAGE_SIZE)
 
 #ifndef __ASSEMBLY__
@@ -183,8 +184,6 @@ do {								\
 
 #ifdef __KERNEL__
 
-#define prepare_to_switch()    do { } while(0)
-
 #ifdef CONFIG_IA32_SUPPORT
 # define IS_IA32_PROCESS(regs)  (ia64_psr(regs)->is != 0)
 #else
@@ -274,13 +273,7 @@ extern void ia64_load_extra (struct task_struct *task);
  * of that CPU which will not be released, because there we wait for the
  * tasklist_lock to become available.
  */
-#define prepare_arch_switch(rq, next)           \
-do {                                            \
-        spin_lock(&(next)->switch_lock);        \
-        spin_unlock(&(rq)->lock);               \
-} while (0)
-#define finish_arch_switch(rq, prev)    spin_unlock_irq(&(prev)->switch_lock)
-#define task_running(rq, p)             ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
+#define __ARCH_WANT_UNLOCKED_CTXSW
 
 #define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
 
diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h
index 8d5b7e77028c..7dc8951708a3 100644
--- a/include/asm-ia64/thread_info.h
+++ b/include/asm-ia64/thread_info.h
@@ -25,7 +25,7 @@ struct thread_info {
         __u32 flags;                    /* thread_info flags (see TIF_*) */
         __u32 cpu;                      /* current CPU */
         mm_segment_t addr_limit;        /* user-level address space limit */
-        __s32 preempt_count;            /* 0=premptable, <0=BUG; will also serve as bh-counter */
+        int preempt_count;              /* 0=premptable, <0=BUG; will also serve as bh-counter */
         struct restart_block restart_block;
         struct {
                 int signo;
diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h
index 21cf351fd05c..a9f738bf18a7 100644
--- a/include/asm-ia64/topology.h
+++ b/include/asm-ia64/topology.h
@@ -40,46 +40,61 @@
  */
 #define node_to_first_cpu(node) (__ffs(node_to_cpumask(node)))
 
+/*
+ * Determines the node for a given pci bus
+ */
+#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
+
 void build_cpu_to_node_map(void);
 
-/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
+#define SD_CPU_INIT (struct sched_domain) {             \
         .span                   = CPU_MASK_NONE,        \
         .parent                 = NULL,                 \
         .groups                 = NULL,                 \
-        .min_interval           = 80,                   \
-        .max_interval           = 320,                  \
-        .busy_factor            = 320,                  \
+        .min_interval           = 1,                    \
+        .max_interval           = 4,                    \
+        .busy_factor            = 64,                   \
         .imbalance_pct          = 125,                  \
         .cache_hot_time         = (10*1000000),         \
-        .cache_nice_tries       = 1,                    \
         .per_cpu_gain           = 100,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 2,                    \
+        .idle_idx               = 1,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
         .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_EXEC       \
                                 | SD_BALANCE_NEWIDLE    \
-                                | SD_WAKE_IDLE          \
-                                | SD_WAKE_BALANCE,      \
+                                | SD_BALANCE_EXEC       \
+                                | SD_WAKE_AFFINE,       \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
         .nr_balance_failed      = 0,                    \
 }
 
-/* sched_domains SD_ALLNODES_INIT for IA64 NUMA machines */
-#define SD_ALLNODES_INIT (struct sched_domain) {        \
+/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
         .span                   = CPU_MASK_NONE,        \
         .parent                 = NULL,                 \
         .groups                 = NULL,                 \
-        .min_interval           = 80,                   \
-        .max_interval           = 320,                  \
-        .busy_factor            = 320,                  \
+        .min_interval           = 8,                    \
+        .max_interval           = 8*(min(num_online_cpus(), 32)), \
+        .busy_factor            = 64,                   \
         .imbalance_pct          = 125,                  \
         .cache_hot_time         = (10*1000000),         \
-        .cache_nice_tries       = 1,                    \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 0, /* unused */       \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
         .per_cpu_gain           = 100,                  \
         .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_EXEC,      \
+                                | SD_BALANCE_EXEC       \
+                                | SD_BALANCE_FORK       \
+                                | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
-        .balance_interval       = 100*(63+num_online_cpus())/64,   \
+        .balance_interval       = 64,                   \
         .nr_balance_failed      = 0,                    \
 }
 
diff --git a/include/asm-ia64/types.h b/include/asm-ia64/types.h
index a677565aa954..902850d12424 100644
--- a/include/asm-ia64/types.h
+++ b/include/asm-ia64/types.h
@@ -67,8 +67,6 @@ typedef __u64 u64;
 
 typedef u64 dma_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 # endif /* __KERNEL__ */
 #endif /* !__ASSEMBLY__ */
 
diff --git a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h
index 8edd9a90949c..3a7829bb5954 100644
--- a/include/asm-ia64/uaccess.h
+++ b/include/asm-ia64/uaccess.h
@@ -72,13 +72,6 @@
 })
 #define access_ok(type, addr, size)     __access_ok((addr), (size), get_fs())
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated
-verify_area (int type, const void __user *addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
 /*
  * These are the main single-value transfer routines.  They automatically
  * use the right size if we just have the right pointer type.
diff --git a/include/asm-ia64/uncached.h b/include/asm-ia64/uncached.h
new file mode 100644
index 000000000000..b82d923b73c1
--- /dev/null
+++ b/include/asm-ia64/uncached.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2001-2005 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * Prototypes for the uncached page allocator
+ */
+
+extern unsigned long uncached_alloc_page(int nid);
+extern void uncached_free_page(unsigned long);
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 33e26c557c5c..3a0c69524656 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -263,6 +263,12 @@
 #define __NR_add_key                    1271
 #define __NR_request_key                1272
 #define __NR_keyctl                     1273
+#define __NR_ioprio_set                 1274
+#define __NR_ioprio_get                 1275
+#define __NR_set_zone_reclaim           1276
+#define __NR_inotify_init               1277
+#define __NR_inotify_add_watch          1278
+#define __NR_inotify_rm_watch           1279
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-ia64/vga.h b/include/asm-ia64/vga.h
index 1f446d6841f6..bc3349ffc505 100644
--- a/include/asm-ia64/vga.h
+++ b/include/asm-ia64/vga.h
@@ -14,7 +14,10 @@
  * videoram directly without any black magic.
  */
 
-#define VGA_MAP_MEM(x)  ((unsigned long) ioremap((x), 0))
+extern unsigned long vga_console_iobase;
+extern unsigned long vga_console_membase;
+
+#define VGA_MAP_MEM(x)  ((unsigned long) ioremap(vga_console_membase + (x), 0))
 
 #define vga_readb(x)    (*(x))
 #define vga_writeb(x,y) (*(y) = (x))
diff --git a/include/asm-m32r/auxvec.h b/include/asm-m32r/auxvec.h
new file mode 100644
index 000000000000..f76dcc860fae
--- /dev/null
+++ b/include/asm-m32r/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_M32R__AUXVEC_H
+#define _ASM_M32R__AUXVEC_H
+
+#endif  /* _ASM_M32R__AUXVEC_H */
diff --git a/include/asm-m32r/checksum.h b/include/asm-m32r/checksum.h
index 99f37dbf2558..877ebf46e9ff 100644
--- a/include/asm-m32r/checksum.h
+++ b/include/asm-m32r/checksum.h
@@ -105,7 +105,7 @@ static inline unsigned short ip_fast_csum(unsigned char * iph,
                 "       addx    %0, %3 \n"
                 "       .fillinsn\n"
                 "2: \n"
-        /* Since the input registers which are loaded with iph and ipl
+        /* Since the input registers which are loaded with iph and ihl
            are modified, we must also specify them as outputs, or gcc
            will assume they contain their original values. */
         : "=&r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmpreg0), "=&r" (tmpreg1)
diff --git a/include/asm-m32r/div64.h b/include/asm-m32r/div64.h
index 417a51bd552d..6cd978cefb28 100644
--- a/include/asm-m32r/div64.h
+++ b/include/asm-m32r/div64.h
@@ -1,38 +1 @@
-#ifndef _ASM_M32R_DIV64
-#define _ASM_M32R_DIV64
-
-/* $Id$ */
-
-/* unsigned long long division.
- * Input:
- *  unsigned long long  n
- *  unsigned long  base
- * Output:
- *  n = n / base;
- *  return value = n % base;
- */
-#define do_div(n, base)                                         \
-({                                                              \
-        unsigned long _res, _high, _mid, _low;                  \
-                                                                \
-        _low = (n) & 0xffffffffUL;                              \
-        _high = (n) >> 32;                                      \
-        if (_high) {                                            \
-                _mid = (_high % (unsigned long)(base)) << 16;   \
-                _high = _high / (unsigned long)(base);          \
-                _mid += _low >> 16;                             \
-                _low &= 0x0000ffffUL;                           \
-                _low += (_mid % (unsigned long)(base)) << 16;   \
-                _mid = _mid / (unsigned long)(base);            \
-                _res = _low % (unsigned long)(base);            \
-                _low = _low / (unsigned long)(base);            \
-                n = _low + ((long long)_mid << 16) +            \
-                        ((long long)_high << 32);               \
-        } else {                                                \
-                _res = _low % (unsigned long)(base);            \
-                n = (_low / (unsigned long)(base));             \
-        }                                                       \
-        _res;                                                   \
-})
-
-#endif  /* _ASM_M32R_DIV64 */
+#include <asm-generic/div64.h>
diff --git a/include/asm-m32r/emergency-restart.h b/include/asm-m32r/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-m32r/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-m32r/fcntl.h b/include/asm-m32r/fcntl.h
index 3e3089572028..46ab12db5739 100644
--- a/include/asm-m32r/fcntl.h
+++ b/include/asm-m32r/fcntl.h
@@ -1,92 +1 @@
-#ifndef _ASM_M32R_FCNTL_H
-#define _ASM_M32R_FCNTL_H
-
-/* $Id$ */
-
-/* orig : i386 2.4.18 */
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-
-#endif  /* _ASM_M32R_FCNTL_H */
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-m32r/futex.h b/include/asm-m32r/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-m32r/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-m32r/hdreg.h b/include/asm-m32r/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-m32r/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-m32r/ide.h b/include/asm-m32r/ide.h
index be64f24e37ee..194393bd8beb 100644
--- a/include/asm-m32r/ide.h
+++ b/include/asm-m32r/ide.h
@@ -35,7 +35,7 @@
 static __inline__ int ide_default_irq(unsigned long base)
 {
         switch (base) {
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2)
+#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
                 case 0x1f0: return PLD_IRQ_CFIREQ;
                 default:
                         return 0;
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index b56034026bf8..cb98101f4f6e 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -175,6 +175,7 @@
 #define M32R_ICU_CR5_PORTL    (0x210+M32R_ICU_OFFSET)  /* INT4 */
 #define M32R_ICU_CR6_PORTL    (0x214+M32R_ICU_OFFSET)  /* INT5 */
 #define M32R_ICU_CR7_PORTL    (0x218+M32R_ICU_OFFSET)  /* INT6 */
+#define M32R_ICU_CR8_PORTL    (0x219+M32R_ICU_OFFSET)  /* INT7 */
 #define M32R_ICU_CR16_PORTL   (0x23C+M32R_ICU_OFFSET)  /* MFT0 */
 #define M32R_ICU_CR17_PORTL   (0x240+M32R_ICU_OFFSET)  /* MFT1 */
 #define M32R_ICU_CR18_PORTL   (0x244+M32R_ICU_OFFSET)  /* MFT2 */
diff --git a/include/asm-m32r/m32102peri.h b/include/asm-m32r/m32102peri.h
deleted file mode 100644
index 3c12955ad0f0..000000000000
--- a/include/asm-m32r/m32102peri.h
+++ /dev/null
@@ -1,468 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000,2001 by Hiroyuki Kondo
- */
-
-#ifndef __ASSEMBLY__
-
-typedef void    V;
-typedef char    B;
-typedef short   S;
-typedef int             W;
-typedef long    L;
-typedef float   F;
-typedef double  D;
-typedef unsigned char   UB;
-typedef unsigned short  US;
-typedef unsigned int    UW;
-typedef unsigned long   UL;
-typedef const unsigned int      CUW;
-
-/*********************************
-
-M32102 ICU
-
-*********************************/
-#define         ICUISTS         (UW *)0xa0EFF004
-#define         ICUIREQ0        (UW *)0xa0EFF008
-#define         ICUIREQ1        (UW *)0xa0EFF00C
-
-#define         ICUSBICR        (UW *)0xa0EFF018
-#define         ICUIMASK        (UW *)0xa0EFF01C
-
-#define         ICUCR1          (UW *)0xa0EFF200        /* INT0 */
-#define         ICUCR2          (UW *)0xa0EFF204        /* INT1 */
-#define         ICUCR3          (UW *)0xa0EFF208        /* INT2 */
-#define         ICUCR4          (UW *)0xa0EFF20C        /* INT3 */
-#define         ICUCR5          (UW *)0xa0EFF210        /* INT4 */
-#define         ICUCR6          (UW *)0xa0EFF214        /* INT5 */
-#define         ICUCR7          (UW *)0xa0EFF218        /* INT6 */
-
-#define         ICUCR16         (UW *)0xa0EFF23C        /* MFT0 */
-#define         ICUCR17         (UW *)0xa0EFF240        /* MFT1 */
-#define         ICUCR18         (UW *)0xa0EFF244        /* MFT2 */
-#define         ICUCR19         (UW *)0xa0EFF248        /* MFT3 */
-#define         ICUCR20         (UW *)0xa0EFF24C        /* MFT4 */
-#define         ICUCR21         (UW *)0xa0EFF250        /* MFT5 */
-
-#define         ICUCR32         (UW *)0xa0EFF27C        /* DMA0 */
-#define         ICUCR33         (UW *)0xa0EFF280        /* DMA1 */
-
-#define         ICUCR48         (UW *)0xa0EFF2BC        /* SIO0R */
-#define         ICUCR49         (UW *)0xa0EFF2C0        /* SIO0S */
-#define         ICUCR50         (UW *)0xa0EFF2C4        /* SIO1R */
-#define         ICUCR51         (UW *)0xa0EFF2C8        /* SIO1S */
-#define         ICUCR52         (UW *)0xa0EFF2CC        /* SIO2R */
-#define         ICUCR53         (UW *)0xa0EFF2D0        /* SIO2S */
-#define         ICUCR54         (UW *)0xa0EFF2D4        /* SIO3R */
-#define         ICUCR55         (UW *)0xa0EFF2D8        /* SIO3S */
-#define         ICUCR56         (UW *)0xa0EFF2DC        /* SIO4R */
-#define         ICUCR57         (UW *)0xa0EFF2E0        /* SIO4S */
-
-/*********************************
-
-M32102 MFT
-
-*********************************/
-#define         MFTCR           (US *)0xa0EFC002
-#define         MFTRPR          (UB *)0xa0EFC006
-
-#define         MFT0MOD         (US *)0xa0EFC102
-#define         MFT0BOS         (US *)0xa0EFC106
-#define         MFT0CUT         (US *)0xa0EFC10A
-#define         MFT0RLD         (US *)0xa0EFC10E
-#define         MFT0CRLD        (US *)0xa0EFC112
-
-#define         MFT1MOD         (US *)0xa0EFC202
-#define         MFT1BOS         (US *)0xa0EFC206
-#define         MFT1CUT         (US *)0xa0EFC20A
-#define         MFT1RLD         (US *)0xa0EFC20E
-#define         MFT1CRLD        (US *)0xa0EFC212
-
-#define         MFT2MOD         (US *)0xa0EFC302
-#define         MFT2BOS         (US *)0xa0EFC306
-#define         MFT2CUT         (US *)0xa0EFC30A
-#define         MFT2RLD         (US *)0xa0EFC30E
-#define         MFT2CRLD        (US *)0xa0EFC312
-
-#define         MFT3MOD         (US *)0xa0EFC402
-#define         MFT3CUT         (US *)0xa0EFC40A
-#define         MFT3RLD         (US *)0xa0EFC40E
-#define         MFT3CRLD        (US *)0xa0EFC412
-
-#define         MFT4MOD         (US *)0xa0EFC502
-#define         MFT4CUT         (US *)0xa0EFC50A
-#define         MFT4RLD         (US *)0xa0EFC50E
-#define         MFT4CRLD        (US *)0xa0EFC512
-
-#define         MFT5MOD         (US *)0xa0EFC602
-#define         MFT5CUT         (US *)0xa0EFC60A
-#define         MFT5RLD         (US *)0xa0EFC60E
-#define         MFT5CRLD        (US *)0xa0EFC612
-
-/*********************************
-
-M32102 SIO
-
-*********************************/
-
-#define SIO0CR     (volatile int *)0xa0efd000
-#define SIO0MOD0   (volatile int *)0xa0efd004
-#define SIO0MOD1   (volatile int *)0xa0efd008
-#define SIO0STS    (volatile int *)0xa0efd00c
-#define SIO0IMASK  (volatile int *)0xa0efd010
-#define SIO0BAUR   (volatile int *)0xa0efd014
-#define SIO0RBAUR  (volatile int *)0xa0efd018
-#define SIO0TXB    (volatile int *)0xa0efd01c
-#define SIO0RXB    (volatile int *)0xa0efd020
-
-#define SIO1CR     (volatile int *)0xa0efd100
-#define SIO1MOD0   (volatile int *)0xa0efd104
-#define SIO1MOD1   (volatile int *)0xa0efd108
-#define SIO1STS    (volatile int *)0xa0efd10c
-#define SIO1IMASK  (volatile int *)0xa0efd110
-#define SIO1BAUR   (volatile int *)0xa0efd114
-#define SIO1RBAUR  (volatile int *)0xa0efd118
-#define SIO1TXB    (volatile int *)0xa0efd11c
-#define SIO1RXB    (volatile int *)0xa0efd120
-/*********************************
-
-M32102 PORT
-
-*********************************/
-#define         PIEN            (UB *)0xa0EF1003        /* input enable */
-
-#define         P0DATA          (UB *)0xa0EF1020        /* data */
-#define         P1DATA          (UB *)0xa0EF1021
-#define         P2DATA          (UB *)0xa0EF1022
-#define         P3DATA          (UB *)0xa0EF1023
-#define         P4DATA          (UB *)0xa0EF1024
-#define         P5DATA          (UB *)0xa0EF1025
-#define         P6DATA          (UB *)0xa0EF1026
-#define         P7DATA          (UB *)0xa0EF1027
-
-#define         P0DIR           (UB *)0xa0EF1040        /* direction */
-#define         P1DIR           (UB *)0xa0EF1041
-#define         P2DIR           (UB *)0xa0EF1042
-#define         P3DIR           (UB *)0xa0EF1043
-#define         P4DIR           (UB *)0xa0EF1044
-#define         P5DIR           (UB *)0xa0EF1045
-#define         P6DIR           (UB *)0xa0EF1046
-#define         P7DIR           (UB *)0xa0EF1047
-
-#define         P0MOD           (US *)0xa0EF1060        /* mode control */
-#define         P1MOD           (US *)0xa0EF1062
-#define         P2MOD           (US *)0xa0EF1064
-#define         P3MOD           (US *)0xa0EF1066
-#define         P4MOD           (US *)0xa0EF1068
-#define         P5MOD           (US *)0xa0EF106A
-#define         P6MOD           (US *)0xa0EF106C
-#define         P7MOD           (US *)0xa0EF106E
-
-#define         P0ODCR          (UB *)0xa0EF1080        /* open-drain control */
-#define         P1ODCR          (UB *)0xa0EF1081
-#define         P2ODCR          (UB *)0xa0EF1082
-#define         P3ODCR          (UB *)0xa0EF1083
-#define         P4ODCR          (UB *)0xa0EF1084
-#define         P5ODCR          (UB *)0xa0EF1085
-#define         P6ODCR          (UB *)0xa0EF1086
-#define         P7ODCR          (UB *)0xa0EF1087
-
-/*********************************
-
-M32102 Cache
-
-********************************/
-
-#define         MCCR    (US *)0xFFFFFFFE
-
-
-#else  /* __ASSEMBLY__ */
-
-;;
-;; PIO     0x80ef1000
-;;
-
-#define PIEN          0xa0ef1000
-
-#define P0DATA        0xa0ef1020
-#define P1DATA        0xa0ef1021
-#define P2DATA        0xa0ef1022
-#define P3DATA        0xa0ef1023
-#define P4DATA        0xa0ef1024
-#define P5DATA        0xa0ef1025
-#define P6DATA        0xa0ef1026
-#define P7DATA        0xa0ef1027
-
-#define P0DIR         0xa0ef1040
-#define P1DIR         0xa0ef1041
-#define P2DIR         0xa0ef1042
-#define P3DIR         0xa0ef1043
-#define P4DIR         0xa0ef1044
-#define P5DIR         0xa0ef1045
-#define P6DIR         0xa0ef1046
-#define P7DIR         0xa0ef1047
-
-#define P0MOD         0xa0ef1060
-#define P1MOD         0xa0ef1062
-#define P2MOD         0xa0ef1064
-#define P3MOD         0xa0ef1066
-#define P4MOD         0xa0ef1068
-#define P5MOD         0xa0ef106a
-#define P6MOD         0xa0ef106c
-#define P7MOD         0xa0ef106e
-;
-#define P0ODCR        0xa0ef1080
-#define P1ODCR        0xa0ef1081
-#define P2ODCR        0xa0ef1082
-#define P3ODCR        0xa0ef1083
-#define P4ODCR        0xa0ef1084
-#define P5ODCR        0xa0ef1085
-#define P6ODCR        0xa0ef1086
-#define P7ODCR        0xa0ef1087
-
-;;
-;; WDT     0xa0ef2000
-;;
-
-#define WDTCR         0xa0ef2000
-
-
-;;
-;; CLK     0xa0ef4000
-;;
-
-#define CPUCLKCR      0xa0ef4000
-#define CLKMOD        0xa0ef4004
-#define PLLCR         0xa0ef4008
-
-
-;;
-;; BSEL    0xa0ef5000
-;;
-
-#define BSEL0CR       0xa0ef5000
-#define BSEL1CR       0xa0ef5004
-#define BSEL2CR       0xa0ef5008
-#define BSEL3CR       0xa0ef500c
-#define BSEL4CR       0xa0ef5010
-#define BSEL5CR       0xa0ef5014
-
-
-;;
-;; SDRAMC  0xa0ef6000
-;;
-
-#define SDRF0         0xa0ef6000
-#define SDRF1         0xa0ef6004
-#define SDIR0         0xa0ef6008
-#define SDIR1         0xa0ef600c
-#define SDBR          0xa0ef6010
-
-;; CH0
-#define SD0ADR        0xa0ef6020
-#define SD0SZ         0xa0ef6022
-#define SD0ER         0xa0ef6024
-#define SD0TR         0xa0ef6028
-#define SD0MOD        0xa0ef602c
-
-;; CH1
-#define SD1ADR        0xa0ef6040
-#define SD1SZ         0xa0ef6042
-#define SD1ER         0xa0ef6044
-#define SD1TR         0xa0ef6048
-#define SD1MOD        0xa0ef604c
-
-
-;;
-;; DMAC    0xa0ef8000
-;;
-
-#define DMAEN         0xa0ef8000
-#define DMAISTS       0xa0ef8004
-#define DMAEDET       0xa0ef8008
-#define DMAASTS       0xa0ef800c
-
-;; CH0
-#define DMA0CR0       0xa0ef8100
-#define DMA0CR1       0xa0ef8104
-#define DMA0CSA       0xa0ef8108
-#define DMA0RSA       0xa0ef810c
-#define DMA0CDA       0xa0ef8110
-#define DMA0RDA       0xa0ef8114
-#define DMA0CBCUT     0xa0ef8118
-#define DMA0RBCUT     0xa0ef811c
-
-;; CH1
-#define DMA1CR0       0xa0ef8200
-#define DMA1CR1       0xa0ef8204
-#define DMA1CSA       0xa0ef8208
-#define DMA1RSA       0xa0ef820c
-#define DMA1CDA       0xa0ef8210
-#define DMA1RDA       0xa0ef8214
-#define DMA1CBCUT     0xa0ef8218
-#define DMA1RBCUT     0xa0ef821c
-
-
-;;
-;; MFT     0xa0efc000
-;;
-
-#define MFTCR        0xa0efc000
-#define MFTRPR       0xa0efc004
-
-;; CH0
-#define MFT0MOD      0xa0efc100
-#define MFT0BOS      0xa0efc104
-#define MFT0CUT      0xa0efc108
-#define MFT0RLD      0xa0efc10c
-#define MFT0CMPRLD   0xa0efc110
-
-;; CH1
-#define MFT1MOD      0xa0efc200
-#define MFT1BOS      0xa0efc204
-#define MFT1CUT      0xa0efc208
-#define MFT1RLD      0xa0efc20c
-#define MFT1CMPRLD   0xa0efc210
-
-;; CH2
-#define MFT2MOD      0xa0efc300
-#define MFT2BOS      0xa0efc304
-#define MFT2CUT      0xa0efc308
-#define MFT2RLD      0xa0efc30c
-#define MFT2CMPRLD   0xa0efc310
-
-;; CH3
-#define MFT3MOD      0xa0efc400
-#define MFT3BOS      0xa0efc404
-#define MFT3CUT      0xa0efc408
-#define MFT3RLD      0xa0efc40c
-#define MFT3CMPRLD   0xa0efc410
-
-;; CH4
-#define MFT4MOD      0xa0efc500
-#define MFT4BOS      0xa0efc504
-#define MFT4CUT      0xa0efc508
-#define MFT4RLD      0xa0efc50c
-#define MFT4CMPRLD   0xa0efc510
-
-;; CH5
-#define MFT5MOD      0xa0efc600
-#define MFT5BOS      0xa0efc604
-#define MFT5CUT      0xa0efc608
-#define MFT5RLD      0xa0efc60c
-#define MFT5CMPRLD   0xa0efc610
-
-
-;;
-;; SIO     0xa0efd000
-;;
-
-;; CH0
-#define SIO0CR        0xa0efd000
-#define SIO0MOD0      0xa0efd004
-#define SIO0MOD1      0xa0efd008
-#define SIO0STS       0xa0efd00c
-#define SIO0IMASK     0xa0efd010
-#define SIO0BAUR      0xa0efd014
-#define SIO0RBAUR     0xa0efd018
-#define SIO0TXB       0xa0efd01c
-#define SIO0RXB       0xa0efd020
-
-;; CH1
-#define SIO1CR        0xa0efd100
-#define SIO1MOD0      0xa0efd104
-#define SIO1MOD1      0xa0efd108
-#define SIO1STS       0xa0efd10c
-#define SIO1IMASK     0xa0efd110
-#define SIO1BAUR      0xa0efd114
-#define SIO1RBAUR     0xa0efd118
-#define SIO1TXB       0xa0efd11c
-#define SIO1RXB       0xa0efd120
-
-;; CH2
-#define SIO2CR        0xa0efd200
-#define SIO2MOD0      0xa0efd204
-#define SIO2MOD1      0xa0efd208
-#define SIO2STS       0xa0efd20c
-#define SIO2IMASK     0xa0efd210
-#define SIO2BAUR      0xa0efd214
-#define SIO2RBAUR     0xa0efd218
-#define SIO2TXB       0xa0efd21c
-#define SIO2RXB       0xa0efd220
-
-;; CH3
-#define SIO3CR        0xa0efd300
-#define SIO3MOD0      0xa0efd304
-#define SIO3MOD1      0xa0efd308
-#define SIO3STS       0xa0efd30c
-#define SIO3IMASK     0xa0efd310
-#define SIO3BAUR      0xa0efd314
-#define SIO3RBAUR     0xa0efd318
-#define SIO3TXB       0xa0efd31c
-#define SIO3RXB       0xa0efd320
-
-;; CH4
-#define SIO4CR        0xa0efd400
-#define SIO4MOD0      0xa0efd404
-#define SIO4MOD1      0xa0efd408
-#define SIO4STS       0xa0efd40c
-#define SIO4IMASK     0xa0efd410
-#define SIO4BAUR      0xa0efd414
-#define SIO4RBAUR     0xa0efd418
-#define SIO4TXB       0xa0efd41c
-#define SIO4RXB       0xa0efd420
-
-
-;;
-;; ICU     0xa0eff000
-;;
-
-#define ICUISTS       0xa0eff004
-#define ICUIREQ0      0xa0eff008
-#define ICUIREQ1      0xa0eff00c
-
-#define ICUSBICR      0xa0eff018
-#define ICUIMASK      0xa0eff01c
-
-#define ICUCR1        0xa0eff200
-#define ICUCR2        0xa0eff204
-#define ICUCR3        0xa0eff208
-#define ICUCR4        0xa0eff20c
-#define ICUCR5        0xa0eff210
-#define ICUCR6        0xa0eff214
-#define ICUCR7        0xa0eff218
-
-#define ICUCR16       0xa0eff23c
-#define ICUCR17       0xa0eff240
-#define ICUCR18       0xa0eff244
-#define ICUCR19       0xa0eff248
-#define ICUCR20       0xa0eff24c
-#define ICUCR21       0xa0eff250
-
-#define ICUCR32       0xa0eff27c
-#define ICUCR33       0xa0eff280
-
-#define ICUCR48       0xa0eff2bc
-#define ICUCR49       0xa0eff2c0
-#define ICUCR50       0xa0eff2c4
-#define ICUCR51       0xa0eff2c8
-#define ICUCR52       0xa0eff2cc
-#define ICUCR53       0xa0eff2d0
-#define ICUCR54       0xa0eff2d4
-#define ICUCR55       0xa0eff2d8
-#define ICUCR56       0xa0eff2dc
-#define ICUCR57       0xa0eff2e0
-
-;;
-;; CACHE
-;;
-
-#define MCCR              0xfffffffc
-
-
-#endif  /* __ASSEMBLY__ */
diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h
index f116649bbef3..ec142be00862 100644
--- a/include/asm-m32r/m32r.h
+++ b/include/asm-m32r/m32r.h
@@ -16,7 +16,6 @@
         || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
         || defined(CONFIG_CHIP_OPSP)
 #include <asm/m32102.h>
-#include <asm/m32102peri.h>
 #endif
 
 /* Platform type */
@@ -36,6 +35,10 @@
 #include <asm/mappi2/mappi2_pld.h>
 #endif  /* CONFIG_PLAT_MAPPI2 */
 
+#if defined(CONFIG_PLAT_MAPPI3)
+#include <asm/mappi3/mappi3_pld.h>
+#endif  /* CONFIG_PLAT_MAPPI3 */
+
 #if defined(CONFIG_PLAT_USRV)
 #include <asm/m32700ut/m32700ut_pld.h>
 #endif
diff --git a/include/asm-m32r/mappi3/mappi3_pld.h b/include/asm-m32r/mappi3/mappi3_pld.h
new file mode 100644
index 000000000000..3f1551f7f01f
--- /dev/null
+++ b/include/asm-m32r/mappi3/mappi3_pld.h
@@ -0,0 +1,143 @@
+/*
+ * include/asm/mappi3/mappi3_pld.h
+ *
+ * Definitions for Extended IO Logic on MAPPI3 board.
+ *  based on m32700ut_pld.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ */
+
+#ifndef _MAPPI3_PLD_H
+#define _MAPPI3_PLD_H
+
+#ifndef __ASSEMBLY__
+/* FIXME:
+ * Some C functions use non-cache address, so can't define non-cache address.
+ */
+#define PLD_BASE                (0x1c000000 /* + NONCACHE_OFFSET */)
+#define __reg8                  (volatile unsigned char *)
+#define __reg16                 (volatile unsigned short *)
+#define __reg32                 (volatile unsigned int *)
+#else
+#define PLD_BASE                (0x1c000000 + NONCACHE_OFFSET)
+#define __reg8
+#define __reg16
+#define __reg32
+#endif  /* __ASSEMBLY__ */
+
+/* CFC */
+#define PLD_CFRSTCR             __reg16(PLD_BASE + 0x0000)
+#define PLD_CFSTS               __reg16(PLD_BASE + 0x0002)
+#define PLD_CFIMASK             __reg16(PLD_BASE + 0x0004)
+#define PLD_CFBUFCR             __reg16(PLD_BASE + 0x0006)
+#define PLD_CFCR0               __reg16(PLD_BASE + 0x000a)
+#define PLD_CFCR1               __reg16(PLD_BASE + 0x000c)
+
+/* MMC */
+#define PLD_MMCCR               __reg16(PLD_BASE + 0x4000)
+#define PLD_MMCMOD              __reg16(PLD_BASE + 0x4002)
+#define PLD_MMCSTS              __reg16(PLD_BASE + 0x4006)
+#define PLD_MMCBAUR             __reg16(PLD_BASE + 0x400a)
+#define PLD_MMCCMDBCUT          __reg16(PLD_BASE + 0x400c)
+#define PLD_MMCCDTBCUT          __reg16(PLD_BASE + 0x400e)
+#define PLD_MMCDET              __reg16(PLD_BASE + 0x4010)
+#define PLD_MMCWP               __reg16(PLD_BASE + 0x4012)
+#define PLD_MMCWDATA            __reg16(PLD_BASE + 0x5000)
+#define PLD_MMCRDATA            __reg16(PLD_BASE + 0x6000)
+#define PLD_MMCCMDDATA          __reg16(PLD_BASE + 0x7000)
+#define PLD_MMCRSPDATA          __reg16(PLD_BASE + 0x7006)
+
+/* Power Control of MMC and CF */
+#define PLD_CPCR                __reg16(PLD_BASE + 0x14000)
+
+
+/*==== ICU ====*/
+#define  M32R_IRQ_PC104        (5)   /* INT4(PC/104) */
+#define  M32R_IRQ_I2C          (28)  /* I2C-BUS     */
+#define  PLD_IRQ_CFIREQ       (6)  /* INT5 CFC Card Interrupt */
+#define  PLD_IRQ_CFC_INSERT   (7)  /* INT6 CFC Card Insert */
+#define  PLD_IRQ_CFC_EJECT    (8)  /* INT7 CFC Card Eject */
+#define  PLD_IRQ_MMCCARD      (43)  /* MMC Card Insert */
+#define  PLD_IRQ_MMCIRQ       (44)  /* MMC Transfer Done */
+
+
+#if 0
+/* LED Control
+ *
+ * 1: DIP swich side
+ * 2: Reset switch side
+ */
+#define PLD_IOLEDCR             __reg16(PLD_BASE + 0x14002)
+#define PLD_IOLED_1_ON          0x001
+#define PLD_IOLED_1_OFF         0x000
+#define PLD_IOLED_2_ON          0x002
+#define PLD_IOLED_2_OFF         0x000
+
+/* DIP Switch
+ *  0: Write-protect of Flash Memory (0:protected, 1:non-protected)
+ *  1: -
+ *  2: -
+ *  3: -
+ */
+#define PLD_IOSWSTS             __reg16(PLD_BASE + 0x14004)
+#define PLD_IOSWSTS_IOSW2       0x0200
+#define PLD_IOSWSTS_IOSW1       0x0100
+#define PLD_IOSWSTS_IOWP0       0x0001
+
+#endif
+
+/* CRC */
+#define PLD_CRC7DATA            __reg16(PLD_BASE + 0x18000)
+#define PLD_CRC7INDATA          __reg16(PLD_BASE + 0x18002)
+#define PLD_CRC16DATA           __reg16(PLD_BASE + 0x18004)
+#define PLD_CRC16INDATA         __reg16(PLD_BASE + 0x18006)
+#define PLD_CRC16ADATA          __reg16(PLD_BASE + 0x18008)
+#define PLD_CRC16AINDATA        __reg16(PLD_BASE + 0x1800a)
+
+
+#if 0
+/* RTC */
+#define PLD_RTCCR               __reg16(PLD_BASE + 0x1c000)
+#define PLD_RTCBAUR             __reg16(PLD_BASE + 0x1c002)
+#define PLD_RTCWRDATA           __reg16(PLD_BASE + 0x1c004)
+#define PLD_RTCRDDATA           __reg16(PLD_BASE + 0x1c006)
+#define PLD_RTCRSTODT           __reg16(PLD_BASE + 0x1c008)
+
+/* SIO0 */
+#define PLD_ESIO0CR             __reg16(PLD_BASE + 0x20000)
+#define PLD_ESIO0CR_TXEN        0x0001
+#define PLD_ESIO0CR_RXEN        0x0002
+#define PLD_ESIO0MOD0           __reg16(PLD_BASE + 0x20002)
+#define PLD_ESIO0MOD0_CTSS      0x0040
+#define PLD_ESIO0MOD0_RTSS      0x0080
+#define PLD_ESIO0MOD1           __reg16(PLD_BASE + 0x20004)
+#define PLD_ESIO0MOD1_LMFS      0x0010
+#define PLD_ESIO0STS            __reg16(PLD_BASE + 0x20006)
+#define PLD_ESIO0STS_TEMP       0x0001
+#define PLD_ESIO0STS_TXCP       0x0002
+#define PLD_ESIO0STS_RXCP       0x0004
+#define PLD_ESIO0STS_TXSC       0x0100
+#define PLD_ESIO0STS_RXSC       0x0200
+#define PLD_ESIO0STS_TXREADY    (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
+#define PLD_ESIO0INTCR          __reg16(PLD_BASE + 0x20008)
+#define PLD_ESIO0INTCR_TXIEN    0x0002
+#define PLD_ESIO0INTCR_RXCEN    0x0004
+#define PLD_ESIO0BAUR           __reg16(PLD_BASE + 0x2000a)
+#define PLD_ESIO0TXB            __reg16(PLD_BASE + 0x2000c)
+#define PLD_ESIO0RXB            __reg16(PLD_BASE + 0x2000e)
+
+/* SIM Card */
+#define PLD_SCCR                __reg16(PLD_BASE + 0x38000)
+#define PLD_SCMOD               __reg16(PLD_BASE + 0x38004)
+#define PLD_SCSTS               __reg16(PLD_BASE + 0x38006)
+#define PLD_SCINTCR             __reg16(PLD_BASE + 0x38008)
+#define PLD_SCBAUR              __reg16(PLD_BASE + 0x3800a)
+#define PLD_SCTXB               __reg16(PLD_BASE + 0x3800c)
+#define PLD_SCRXB               __reg16(PLD_BASE + 0x3800e)
+
+#endif
+
+#endif  /* _MAPPI3_PLD.H */
diff --git a/include/asm-m32r/mmzone.h b/include/asm-m32r/mmzone.h
index ebf0228fec42..d58878ec899e 100644
--- a/include/asm-m32r/mmzone.h
+++ b/include/asm-m32r/mmzone.h
@@ -14,7 +14,6 @@ extern struct pglist_data *node_data[];
 #define NODE_DATA(nid)          (node_data[nid])
 
 #define node_localnr(pfn, nid)  ((pfn) - NODE_DATA(nid)->node_start_pfn)
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)                                               \
 ({                                                                      \
@@ -32,7 +31,7 @@ extern struct pglist_data *node_data[];
 ({                                                                      \
         unsigned long __pfn = pfn;                                      \
         int __node  = pfn_to_nid(__pfn);                                \
-        &node_mem_map(__node)[node_localnr(__pfn,__node)];              \
+        &NODE_DATA(__node)->node_mem_map[node_localnr(__pfn,__node)];   \
 })
 
 #define page_to_pfn(pg)                                                 \
diff --git a/include/asm-m32r/page.h b/include/asm-m32r/page.h
index 1c6abb9f3f1f..4ab578876361 100644
--- a/include/asm-m32r/page.h
+++ b/include/asm-m32r/page.h
@@ -61,25 +61,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 /* This handles the memory map.. */
 
-#ifndef __ASSEMBLY__
-
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size - 1) >> (PAGE_SHIFT - 1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-
-        return order;
-}
-
-#endif /* __ASSEMBLY__ */
-
 #define __MEMORY_START  CONFIG_MEMORY_START
 #define __MEMORY_SIZE   CONFIG_MEMORY_SIZE
 
@@ -111,5 +92,7 @@ static __inline__ int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _ASM_M32R_PAGE_H */
 
diff --git a/include/asm-m32r/s1d13806.h b/include/asm-m32r/s1d13806.h
new file mode 100644
index 000000000000..248d36a82d79
--- /dev/null
+++ b/include/asm-m32r/s1d13806.h
@@ -0,0 +1,199 @@
+//----------------------------------------------------------------------------
+//
+//  File generated by S1D13806CFG.EXE
+//
+//  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+//  All rights reserved.
+//
+//----------------------------------------------------------------------------
+
+// Panel:  (active)  640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
+// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
+
+#define SWIVEL_VIEW             0       /* 0:none, 1:90 not completed */
+
+static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
+
+    {0x0001,0x00},   // Miscellaneous Register
+    {0x01FC,0x00},   // Display Mode Register
+#if defined(CONFIG_PLAT_MAPPI)
+    {0x0004,0x00},   // General IO Pins Configuration Register 0
+    {0x0005,0x00},   // General IO Pins Configuration Register 1
+    {0x0008,0x00},   // General IO Pins Control Register 0
+    {0x0009,0x00},   // General IO Pins Control Register 1
+    {0x0010,0x00},   // Memory Clock Configuration Register
+    {0x0014,0x00},   // LCD Pixel Clock Configuration Register
+    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
+    {0x001C,0x00},   // MediaPlug Clock Configuration Register
+/*
+ * .. 10MHz: 0x00
+ * .. 30MHz: 0x01
+ * 30MHz ..: 0x02
+ */
+    {0x001E,0x02},   // CPU To Memory Wait State Select Register
+    {0x0021,0x02},   // DRAM Refresh Rate Register
+    {0x002A,0x11},   // DRAM Timings Control Register 0
+    {0x002B,0x13},   // DRAM Timings Control Register 1
+    {0x0020,0x80},   // Memory Configuration Register
+    {0x0030,0x25},   // Panel Type Register
+    {0x0031,0x00},   // MOD Rate Register
+    {0x0032,0x4F},   // LCD Horizontal Display Width Register
+    {0x0034,0x12},   // LCD Horizontal Non-Display Period Register
+    {0x0035,0x01},   // TFT FPLINE Start Position Register
+    {0x0036,0x0B},   // TFT FPLINE Pulse Width Register
+    {0x0038,0xDF},   // LCD Vertical Display Height Register 0
+    {0x0039,0x01},   // LCD Vertical Display Height Register 1
+    {0x003A,0x2C},   // LCD Vertical Non-Display Period Register
+    {0x003B,0x0A},   // TFT FPFRAME Start Position Register
+    {0x003C,0x01},   // TFT FPFRAME Pulse Width Register
+
+    {0x0041,0x00},   // LCD Miscellaneous Register
+    {0x0042,0x00},   // LCD Display Start Address Register 0
+    {0x0043,0x00},   // LCD Display Start Address Register 1
+    {0x0044,0x00},   // LCD Display Start Address Register 2
+
+#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
+    {0x0004,0x07},   // GPIO[0:7] direction
+    {0x0005,0x00},   // GPIO[8:12] direction
+    {0x0008,0x00},   // GPIO[0:7] data
+    {0x0009,0x00},   // GPIO[8:12] data
+    {0x0008,0x04},   // LCD panel Vcc on
+    {0x0008,0x05},   // LCD panel reset
+    {0x0010,0x01},   // Memory Clock Configuration Register
+    {0x0014,0x30},   // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
+    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
+    {0x001C,0x00},   // MediaPlug Clock Configuration Register(10MHz)
+    {0x001E,0x00},   // CPU To Memory Wait State Select Register
+    {0x0020,0x80},   // Memory Configuration Register
+    {0x0021,0x03},   // DRAM Refresh Rate Register
+    {0x002A,0x00},   // DRAM Timings Control Register 0
+    {0x002B,0x01},   // DRAM Timings Control Register 1
+    {0x0030,0x25},   // Panel Type Register
+    {0x0031,0x00},   // MOD Rate Register
+    {0x0032,0x1d},   // LCD Horizontal Display Width Register
+    {0x0034,0x05},   // LCD Horizontal Non-Display Period Register
+    {0x0035,0x01},   // TFT FPLINE Start Position Register
+    {0x0036,0x01},   // TFT FPLINE Pulse Width Register
+    {0x0038,0x3F},   // LCD Vertical Display Height Register 0
+    {0x0039,0x01},   // LCD Vertical Display Height Register 1
+    {0x003A,0x0b},   // LCD Vertical Non-Display Period Register
+    {0x003B,0x07},   // TFT FPFRAME Start Position Register
+    {0x003C,0x02},   // TFT FPFRAME Pulse Width Register
+
+    {0x0041,0x00},   // LCD Miscellaneous Register
+#if (SWIVEL_VIEW == 0)
+    {0x0042,0x00},   // LCD Display Start Address Register 0
+    {0x0043,0x00},   // LCD Display Start Address Register 1
+    {0x0044,0x00},   // LCD Display Start Address Register 2
+
+#elif (SWIVEL_VIEW == 1)
+    // 1024 - W(320) = 0x2C0
+    {0x0042,0xC0},   // LCD Display Start Address Register 0
+    {0x0043,0x02},   // LCD Display Start Address Register 1
+    {0x0044,0x00},   // LCD Display Start Address Register 2
+    // 1024
+    {0x0046,0x00},   // LCD Memory Address Offset Register 0
+    {0x0047,0x02},   // LCD Memory Address Offset Register 1
+#else
+#error unsupported SWIVEL_VIEW mode
+#endif
+#else
+#error no platform configuration
+#endif  /* CONFIG_PLAT_XXX */
+
+    {0x0048,0x00},   // LCD Pixel Panning Register
+    {0x004A,0x00},   // LCD Display FIFO High Threshold Control Register
+    {0x004B,0x00},   // LCD Display FIFO Low Threshold Control Register
+    {0x0050,0x4F},   // CRT/TV Horizontal Display Width Register
+    {0x0052,0x13},   // CRT/TV Horizontal Non-Display Period Register
+    {0x0053,0x01},   // CRT/TV HRTC Start Position Register
+    {0x0054,0x0B},   // CRT/TV HRTC Pulse Width Register
+    {0x0056,0xDF},   // CRT/TV Vertical Display Height Register 0
+    {0x0057,0x01},   // CRT/TV Vertical Display Height Register 1
+    {0x0058,0x2B},   // CRT/TV Vertical Non-Display Period Register
+    {0x0059,0x09},   // CRT/TV VRTC Start Position Register
+    {0x005A,0x01},   // CRT/TV VRTC Pulse Width Register
+    {0x005B,0x10},   // TV Output Control Register
+
+    {0x0062,0x00},   // CRT/TV Display Start Address Register 0
+    {0x0063,0x00},   // CRT/TV Display Start Address Register 1
+    {0x0064,0x00},   // CRT/TV Display Start Address Register 2
+
+    {0x0068,0x00},   // CRT/TV Pixel Panning Register
+    {0x006A,0x00},   // CRT/TV Display FIFO High Threshold Control Register
+    {0x006B,0x00},   // CRT/TV Display FIFO Low Threshold Control Register
+    {0x0070,0x00},   // LCD Ink/Cursor Control Register
+    {0x0071,0x01},   // LCD Ink/Cursor Start Address Register
+    {0x0072,0x00},   // LCD Cursor X Position Register 0
+    {0x0073,0x00},   // LCD Cursor X Position Register 1
+    {0x0074,0x00},   // LCD Cursor Y Position Register 0
+    {0x0075,0x00},   // LCD Cursor Y Position Register 1
+    {0x0076,0x00},   // LCD Ink/Cursor Blue Color 0 Register
+    {0x0077,0x00},   // LCD Ink/Cursor Green Color 0 Register
+    {0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
+    {0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
+    {0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
+    {0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
+    {0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register
+    {0x0080,0x00},   // CRT/TV Ink/Cursor Control Register
+    {0x0081,0x01},   // CRT/TV Ink/Cursor Start Address Register
+    {0x0082,0x00},   // CRT/TV Cursor X Position Register 0
+    {0x0083,0x00},   // CRT/TV Cursor X Position Register 1
+    {0x0084,0x00},   // CRT/TV Cursor Y Position Register 0
+    {0x0085,0x00},   // CRT/TV Cursor Y Position Register 1
+    {0x0086,0x00},   // CRT/TV Ink/Cursor Blue Color 0 Register
+    {0x0087,0x00},   // CRT/TV Ink/Cursor Green Color 0 Register
+    {0x0088,0x00},   // CRT/TV Ink/Cursor Red Color 0 Register
+    {0x008A,0x1F},   // CRT/TV Ink/Cursor Blue Color 1 Register
+    {0x008B,0x3F},   // CRT/TV Ink/Cursor Green Color 1 Register
+    {0x008C,0x1F},   // CRT/TV Ink/Cursor Red Color 1 Register
+    {0x008E,0x00},   // CRT/TV Ink/Cursor FIFO Threshold Register
+    {0x0100,0x00},   // BitBlt Control Register 0
+    {0x0101,0x00},   // BitBlt Control Register 1
+    {0x0102,0x00},   // BitBlt ROP Code/Color Expansion Register
+    {0x0103,0x00},   // BitBlt Operation Register
+    {0x0104,0x00},   // BitBlt Source Start Address Register 0
+    {0x0105,0x00},   // BitBlt Source Start Address Register 1
+    {0x0106,0x00},   // BitBlt Source Start Address Register 2
+    {0x0108,0x00},   // BitBlt Destination Start Address Register 0
+    {0x0109,0x00},   // BitBlt Destination Start Address Register 1
+    {0x010A,0x00},   // BitBlt Destination Start Address Register 2
+    {0x010C,0x00},   // BitBlt Memory Address Offset Register 0
+    {0x010D,0x00},   // BitBlt Memory Address Offset Register 1
+    {0x0110,0x00},   // BitBlt Width Register 0
+    {0x0111,0x00},   // BitBlt Width Register 1
+    {0x0112,0x00},   // BitBlt Height Register 0
+    {0x0113,0x00},   // BitBlt Height Register 1
+    {0x0114,0x00},   // BitBlt Background Color Register 0
+    {0x0115,0x00},   // BitBlt Background Color Register 1
+    {0x0118,0x00},   // BitBlt Foreground Color Register 0
+    {0x0119,0x00},   // BitBlt Foreground Color Register 1
+    {0x01E0,0x00},   // Look-Up Table Mode Register
+    {0x01E2,0x00},   // Look-Up Table Address Register
+    {0x01F0,0x10},   // Power Save Configuration Register
+    {0x01F1,0x00},   // Power Save Status Register
+    {0x01F4,0x00},   // CPU-to-Memory Access Watchdog Timer Register
+#if (SWIVEL_VIEW == 0)
+    {0x01FC,0x01},   // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
+#elif (SWIVEL_VIEW == 1)
+    {0x01FC,0x41},   // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
+#else
+#error unsupported SWIVEL_VIEW mode
+#endif  /* SWIVEL_VIEW */
+
+#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
+    {0x0008,0x07},   // LCD panel Vdd & Vg on
+#endif
+
+    {0x0040,0x05},   // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
+#if defined(CONFIG_PLAT_MAPPI)
+    {0x0046,0x80},   // LCD Memory Address Offset Register 0
+    {0x0047,0x02},   // LCD Memory Address Offset Register 1
+#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
+    {0x0046,0xf0},   // LCD Memory Address Offset Register 0
+    {0x0047,0x00},   // LCD Memory Address Offset Register 1
+#endif
+    {0x0060,0x05},   // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
+    {0x0066,0x80},   // CRT/TV Memory Address Offset Register 0 // takeo
+    {0x0067,0x02},   // CRT/TV Memory Address Offset Register 1
+};
diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h
index 8cd4d0da4be1..7885b7df84a2 100644
--- a/include/asm-m32r/smp.h
+++ b/include/asm-m32r/smp.h
@@ -61,12 +61,10 @@ extern physid_mask_t phys_cpu_present_map;
  * Some lowlevel functions might want to know about
  * the real CPU ID <-> CPU # mapping.
  */
-extern volatile int physid_2_cpu[NR_CPUS];
 extern volatile int cpu_2_physid[NR_CPUS];
-#define physid_to_cpu(physid)   physid_2_cpu[physid]
 #define cpu_to_physid(cpu_id)   cpu_2_physid[cpu_id]
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 extern cpumask_t cpu_callout_map;
 #define cpu_possible_map cpu_callout_map
diff --git a/include/asm-m32r/socket.h b/include/asm-m32r/socket.h
index 159519d99042..8b6680f223c0 100644
--- a/include/asm-m32r/socket.h
+++ b/include/asm-m32r/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-m32r/thread_info.h b/include/asm-m32r/thread_info.h
index 9f3a0fcf6e2b..7a6be7727a92 100644
--- a/include/asm-m32r/thread_info.h
+++ b/include/asm-m32r/thread_info.h
@@ -28,7 +28,7 @@ struct thread_info {
         unsigned long           flags;          /* low level flags */
         unsigned long           status;         /* thread-synchronous flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
         mm_segment_t            addr_limit;     /* thread address space:
                                                    0-0xBFFFFFFF for user-thread
diff --git a/include/asm-m32r/topology.h b/include/asm-m32r/topology.h
index 299a89d91bde..d607eb32bd7e 100644
--- a/include/asm-m32r/topology.h
+++ b/include/asm-m32r/topology.h
@@ -1,48 +1,6 @@
-/*
- * linux/include/asm-generic/topology.h
- *
- * Written by: Matthew Dobson, IBM Corporation
- *
- * Copyright (C) 2002, IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <colpatch@us.ibm.com>
- */
 #ifndef _ASM_M32R_TOPOLOGY_H
 #define _ASM_M32R_TOPOLOGY_H
 
-/* Other architectures wishing to use this simple topology API should fill
-   in the below functions as appropriate in their own <asm/topology.h> file. */
-
-#define cpu_to_node(cpu)        (0)
-
-#ifndef parent_node
-#define parent_node(node)       (0)
-#endif
-#ifndef node_to_cpumask
-#define node_to_cpumask(node)   (cpu_online_map)
-#endif
-#ifndef node_to_first_cpu
-#define node_to_first_cpu(node) (0)
-#endif
-#ifndef pcibus_to_cpumask
-#define pcibus_to_cpumask(bus)  (cpu_online_map)
-#endif
+#include <asm-generic/topology.h>
 
 #endif /* _ASM_M32R_TOPOLOGY_H */
diff --git a/include/asm-m32r/types.h b/include/asm-m32r/types.h
index ca0a887d2237..fcf24c64c3ba 100644
--- a/include/asm-m32r/types.h
+++ b/include/asm-m32r/types.h
@@ -55,8 +55,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u64 dma64_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-m32r/uaccess.h b/include/asm-m32r/uaccess.h
index bbb8ac4018a0..93d863c455a1 100644
--- a/include/asm-m32r/uaccess.h
+++ b/include/asm-m32r/uaccess.h
@@ -120,31 +120,6 @@ static inline int access_ok(int type, const void *addr, unsigned long size)
 }
 #endif /* CONFIG_MMU */
 
-/**
- * verify_area: - Obsolete/deprecated and will go away soon,
- * use access_ok() instead.
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * This function has been replaced by access_ok().
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns zero if the memory block may be valid, -EFAULT
- * if it is definitely invalid.
- *
- * See access_ok() for more details.
- */
-static inline int __deprecated verify_area(int type, const void __user *addr,
-                              unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-m68k/auxvec.h b/include/asm-m68k/auxvec.h
new file mode 100644
index 000000000000..844d6d52204b
--- /dev/null
+++ b/include/asm-m68k/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMm68k_AUXVEC_H
+#define __ASMm68k_AUXVEC_H
+
+#endif
diff --git a/include/asm-m68k/cacheflush.h b/include/asm-m68k/cacheflush.h
index e4773946f10d..8aba971b1368 100644
--- a/include/asm-m68k/cacheflush.h
+++ b/include/asm-m68k/cacheflush.h
@@ -130,20 +130,25 @@ static inline void __flush_page_to_ram(void *vaddr)
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 #define flush_icache_page(vma, page)    __flush_page_to_ram(page_address(page))
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-        do {                                                    \
-                flush_cache_page(vma, vaddr, page_to_pfn(page));\
-                memcpy(dst, src, len);                          \
-        } while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-        do {                                                    \
-                flush_cache_page(vma, vaddr, page_to_pfn(page));\
-                memcpy(dst, src, len);                          \
-        } while (0)
 
+extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+                                    unsigned long addr, int len);
 extern void flush_icache_range(unsigned long address, unsigned long endaddr);
 
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+                                     struct page *page, unsigned long vaddr,
+                                     void *dst, void *src, int len)
+{
+        flush_cache_page(vma, vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+        flush_icache_user_range(vma, page, vaddr, len);
+}
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+                                       struct page *page, unsigned long vaddr,
+                                       void *dst, void *src, int len)
+{
+        flush_cache_page(vma, vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+}
+
 #endif /* _M68K_CACHEFLUSH_H */
diff --git a/include/asm-m68k/emergency-restart.h b/include/asm-m68k/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-m68k/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-m68k/fcntl.h b/include/asm-m68k/fcntl.h
index 0d4212983a33..1c369b20dc45 100644
--- a/include/asm-m68k/fcntl.h
+++ b/include/asm-m68k/fcntl.h
@@ -1,87 +1,11 @@
 #ifndef _M68K_FCNTL_H
 #define _M68K_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE         0003
-#define O_RDONLY            00
-#define O_WRONLY            01
-#define O_RDWR              02
-#define O_CREAT           0100  /* not fcntl */
-#define O_EXCL            0200  /* not fcntl */
-#define O_NOCTTY          0400  /* not fcntl */
-#define O_TRUNC          01000  /* not fcntl */
-#define O_APPEND         02000
-#define O_NONBLOCK       04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC          010000
-#define FASYNC          020000  /* fcntl, for BSD compatibility */
 #define O_DIRECTORY     040000  /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
 #define O_LARGEFILE     0400000
-#define O_NOATIME       01000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
+#include <asm-generic/fcntl.h>
 
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif /* _M68K_FCNTL_H */
diff --git a/include/asm-m68k/futex.h b/include/asm-m68k/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-m68k/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-m68k/hdreg.h b/include/asm-m68k/hdreg.h
deleted file mode 100644
index 5989bbc97cbf..000000000000
--- a/include/asm-m68k/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#warning this file is obsolete, please do not use it
diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h
index 99a516709210..f206dfbc1d48 100644
--- a/include/asm-m68k/page.h
+++ b/include/asm-m68k/page.h
@@ -107,20 +107,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #endif /* !__ASSEMBLY__ */
 
 #include <asm/page_offset.h>
@@ -138,13 +124,13 @@ extern unsigned long m68k_memoffset;
 #define __pa(vaddr)             ((unsigned long)(vaddr)+m68k_memoffset)
 #define __va(paddr)             ((void *)((unsigned long)(paddr)-m68k_memoffset))
 #else
-#define __pa(vaddr)             virt_to_phys((void *)vaddr)
-#define __va(paddr)             phys_to_virt((unsigned long)paddr)
+#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
+#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
 #endif
 
 #else   /* !CONFIG_SUN3 */
 /* This #define is a horrible hack to suppress lots of warnings. --m */
-#define __pa(x) ___pa((unsigned long)x)
+#define __pa(x) ___pa((unsigned long)(x))
 static inline unsigned long ___pa(unsigned long x)
 {
      if(x == 0)
@@ -192,4 +178,6 @@ static inline void *__va(unsigned long x)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _M68K_PAGE_H */
diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h
index 9e7d79ab5d13..9d2c07abe44f 100644
--- a/include/asm-m68k/pci.h
+++ b/include/asm-m68k/pci.h
@@ -43,7 +43,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
diff --git a/include/asm-m68k/serial.h b/include/asm-m68k/serial.h
index 9f5bcdc105fc..3fe29f8b0194 100644
--- a/include/asm-m68k/serial.h
+++ b/include/asm-m68k/serial.h
@@ -26,54 +26,9 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#endif
-
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-m68k/socket.h b/include/asm-m68k/socket.h
index 8d0b9fc2d07e..f578ca4b776a 100644
--- a/include/asm-m68k/socket.h
+++ b/include/asm-m68k/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h
index 44def078132a..6c59215b285e 100644
--- a/include/asm-m68k/string.h
+++ b/include/asm-m68k/string.h
@@ -80,43 +80,6 @@ static inline char * strchr(const char * s, int c)
   return( (char *) s);
 }
 
-#if 0
-#define __HAVE_ARCH_STRPBRK
-static inline char *strpbrk(const char *cs,const char *ct)
-{
-  const char *sc1,*sc2;
-
-  for( sc1 = cs; *sc1 != '\0'; ++sc1)
-    for( sc2 = ct; *sc2 != '\0'; ++sc2)
-      if (*sc1 == *sc2)
-        return((char *) sc1);
-  return( NULL );
-}
-#endif
-
-#if 0
-#define __HAVE_ARCH_STRSPN
-static inline size_t strspn(const char *s, const char *accept)
-{
-  const char *p;
-  const char *a;
-  size_t count = 0;
-
-  for (p = s; *p != '\0'; ++p)
-    {
-      for (a = accept; *a != '\0'; ++a)
-        if (*p == *a)
-          break;
-      if (*a == '\0')
-        return count;
-      else
-        ++count;
-    }
-
-  return count;
-}
-#endif
-
 /* strstr !! */
 
 #define __HAVE_ARCH_STRLEN
@@ -173,370 +136,18 @@ static inline int strncmp(const char * cs,const char * ct,size_t count)
 }
 
 #define __HAVE_ARCH_MEMSET
-/*
- * This is really ugly, but its highly optimizatiable by the
- * compiler and is meant as compensation for gcc's missing
- * __builtin_memset(). For the 680[23]0 it might be worth considering
- * the optimal number of misaligned writes compared to the number of
- * tests'n'branches needed to align the destination address. The
- * 680[46]0 doesn't really care due to their copy-back caches.
- *                                              10/09/96 - Jes Sorensen
- */
-static inline void * __memset_g(void * s, int c, size_t count)
-{
-  void *xs = s;
-  size_t temp;
-
-  if (!count)
-    return xs;
-
-  c &= 0xff;
-  c |= c << 8;
-  c |= c << 16;
-
-  if (count < 36){
-          long *ls = s;
-
-          switch(count){
-          case 32: case 33: case 34: case 35:
-                  *ls++ = c;
-          case 28: case 29: case 30: case 31:
-                  *ls++ = c;
-          case 24: case 25: case 26: case 27:
-                  *ls++ = c;
-          case 20: case 21: case 22: case 23:
-                  *ls++ = c;
-          case 16: case 17: case 18: case 19:
-                  *ls++ = c;
-          case 12: case 13: case 14: case 15:
-                  *ls++ = c;
-          case 8: case 9: case 10: case 11:
-                  *ls++ = c;
-          case 4: case 5: case 6: case 7:
-                  *ls++ = c;
-                  break;
-          default:
-                  break;
-          }
-          s = ls;
-          if (count & 0x02){
-                  short *ss = s;
-                  *ss++ = c;
-                  s = ss;
-          }
-          if (count & 0x01){
-                  char *cs = s;
-                  *cs++ = c;
-                  s = cs;
-          }
-          return xs;
-  }
-
-  if ((long) s & 1)
-    {
-      char *cs = s;
-      *cs++ = c;
-      s = cs;
-      count--;
-    }
-  if (count > 2 && (long) s & 2)
-    {
-      short *ss = s;
-      *ss++ = c;
-      s = ss;
-      count -= 2;
-    }
-  temp = count >> 2;
-  if (temp)
-    {
-      long *ls = s;
-      temp--;
-      do
-        *ls++ = c;
-      while (temp--);
-      s = ls;
-    }
-  if (count & 2)
-    {
-      short *ss = s;
-      *ss++ = c;
-      s = ss;
-    }
-  if (count & 1)
-    {
-      char *cs = s;
-      *cs = c;
-    }
-  return xs;
-}
-
-/*
- * __memset_page assumes that data is longword aligned. Most, if not
- * all, of these page sized memsets are performed on page aligned
- * areas, thus we do not need to check if the destination is longword
- * aligned. Of course we suffer a serious performance loss if this is
- * not the case but I think the risk of this ever happening is
- * extremely small. We spend a lot of time clearing pages in
- * get_empty_page() so I think it is worth it anyway. Besides, the
- * 680[46]0 do not really care about misaligned writes due to their
- * copy-back cache.
- *
- * The optimized case for the 680[46]0 is implemented using the move16
- * instruction. My tests showed that this implementation is 35-45%
- * faster than the original implementation using movel, the only
- * caveat is that the destination address must be 16-byte aligned.
- *                                            01/09/96 - Jes Sorensen
- */
-static inline void * __memset_page(void * s,int c,size_t count)
-{
-  unsigned long data, tmp;
-  void *xs = s;
-
-  c = c & 255;
-  data = c | (c << 8);
-  data |= data << 16;
-
-#ifdef CPU_M68040_OR_M68060_ONLY
-
-  if (((unsigned long) s) & 0x0f)
-          __memset_g(s, c, count);
-  else{
-          unsigned long *sp = s;
-          *sp++ = data;
-          *sp++ = data;
-          *sp++ = data;
-          *sp++ = data;
-
-          __asm__ __volatile__("1:\t"
-                               ".chip 68040\n\t"
-                               "move16 %2@+,%0@+\n\t"
-                               ".chip 68k\n\t"
-                               "subqw  #8,%2\n\t"
-                               "subqw  #8,%2\n\t"
-                               "dbra   %1,1b\n\t"
-                               : "=a" (sp), "=d" (tmp)
-                               : "a" (s), "0" (sp), "1" ((count - 16) / 16 - 1)
-                               );
-  }
-
-#else
-  __asm__ __volatile__("1:\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "movel %2,%0@+\n\t"
-                       "dbra  %1,1b\n\t"
-                       : "=a" (s), "=d" (tmp)
-                       : "d" (data), "0" (s), "1" (count / 32 - 1)
-                       );
-#endif
-
-  return xs;
-}
-
-extern void *memset(void *,int,__kernel_size_t);
-
-#define __memset_const(s,c,count) \
-((count==PAGE_SIZE) ? \
-  __memset_page((s),(c),(count)) : \
-  __memset_g((s),(c),(count)))
-
-#define memset(s, c, count) \
-(__builtin_constant_p(count) ? \
- __memset_const((s),(c),(count)) : \
- __memset_g((s),(c),(count)))
+extern void *memset(void *, int, __kernel_size_t);
+#define memset(d, c, n) __builtin_memset(d, c, n)
 
 #define __HAVE_ARCH_MEMCPY
-extern void * memcpy(void *, const void *, size_t );
-/*
- * __builtin_memcpy() does not handle page-sized memcpys very well,
- * thus following the same assumptions as for page-sized memsets, this
- * function copies page-sized areas using an unrolled loop, without
- * considering alignment.
- *
- * For the 680[46]0 only kernels we use the move16 instruction instead
- * as it writes through the data-cache, invalidating the cache-lines
- * touched. In this way we do not use up the entire data-cache (well,
- * half of it on the 68060) by copying a page. An unrolled loop of two
- * move16 instructions seem to the fastest. The only caveat is that
- * both source and destination must be 16-byte aligned, if not we fall
- * back to the generic memcpy function.  - Jes
- */
-static inline void * __memcpy_page(void * to, const void * from, size_t count)
-{
-  unsigned long tmp;
-  void *xto = to;
-
-#ifdef CPU_M68040_OR_M68060_ONLY
-
-  if (((unsigned long) to | (unsigned long) from) & 0x0f)
-          return memcpy(to, from, count);
-
-  __asm__ __volatile__("1:\t"
-                       ".chip 68040\n\t"
-                       "move16 %1@+,%0@+\n\t"
-                       "move16 %1@+,%0@+\n\t"
-                       ".chip 68k\n\t"
-                       "dbra  %2,1b\n\t"
-                       : "=a" (to), "=a" (from), "=d" (tmp)
-                       : "0" (to), "1" (from) , "2" (count / 32 - 1)
-                       );
-#else
-  __asm__ __volatile__("1:\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "movel %1@+,%0@+\n\t"
-                       "dbra  %2,1b\n\t"
-                       : "=a" (to), "=a" (from), "=d" (tmp)
-                       : "0" (to), "1" (from) , "2" (count / 32 - 1)
-                       );
-#endif
-  return xto;
-}
-
-#define __memcpy_const(to, from, n) \
-((n==PAGE_SIZE) ? \
-  __memcpy_page((to),(from),(n)) : \
-  __builtin_memcpy((to),(from),(n)))
-
-#define memcpy(to, from, n) \
-(__builtin_constant_p(n) ? \
- __memcpy_const((to),(from),(n)) : \
- memcpy((to),(from),(n)))
+extern void *memcpy(void *, const void *, __kernel_size_t);
+#define memcpy(d, s, n) __builtin_memcpy(d, s, n)
 
 #define __HAVE_ARCH_MEMMOVE
-static inline void * memmove(void * dest,const void * src, size_t n)
-{
-  void *xdest = dest;
-  size_t temp;
-
-  if (!n)
-    return xdest;
-
-  if (dest < src)
-    {
-      if ((long) dest & 1)
-        {
-          char *cdest = dest;
-          const char *csrc = src;
-          *cdest++ = *csrc++;
-          dest = cdest;
-          src = csrc;
-          n--;
-        }
-      if (n > 2 && (long) dest & 2)
-        {
-          short *sdest = dest;
-          const short *ssrc = src;
-          *sdest++ = *ssrc++;
-          dest = sdest;
-          src = ssrc;
-          n -= 2;
-        }
-      temp = n >> 2;
-      if (temp)
-        {
-          long *ldest = dest;
-          const long *lsrc = src;
-          temp--;
-          do
-            *ldest++ = *lsrc++;
-          while (temp--);
-          dest = ldest;
-          src = lsrc;
-        }
-      if (n & 2)
-        {
-          short *sdest = dest;
-          const short *ssrc = src;
-          *sdest++ = *ssrc++;
-          dest = sdest;
-          src = ssrc;
-        }
-      if (n & 1)
-        {
-          char *cdest = dest;
-          const char *csrc = src;
-          *cdest = *csrc;
-        }
-    }
-  else
-    {
-      dest = (char *) dest + n;
-      src = (const char *) src + n;
-      if ((long) dest & 1)
-        {
-          char *cdest = dest;
-          const char *csrc = src;
-          *--cdest = *--csrc;
-          dest = cdest;
-          src = csrc;
-          n--;
-        }
-      if (n > 2 && (long) dest & 2)
-        {
-          short *sdest = dest;
-          const short *ssrc = src;
-          *--sdest = *--ssrc;
-          dest = sdest;
-          src = ssrc;
-          n -= 2;
-        }
-      temp = n >> 2;
-      if (temp)
-        {
-          long *ldest = dest;
-          const long *lsrc = src;
-          temp--;
-          do
-            *--ldest = *--lsrc;
-          while (temp--);
-          dest = ldest;
-          src = lsrc;
-        }
-      if (n & 2)
-        {
-          short *sdest = dest;
-          const short *ssrc = src;
-          *--sdest = *--ssrc;
-          dest = sdest;
-          src = ssrc;
-        }
-      if (n & 1)
-        {
-          char *cdest = dest;
-          const char *csrc = src;
-          *--cdest = *--csrc;
-        }
-    }
-  return xdest;
-}
+extern void *memmove(void *, const void *, __kernel_size_t);
 
 #define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void * ,const void * ,size_t );
-#define memcmp(cs, ct, n) \
-(__builtin_constant_p(n) ? \
- __builtin_memcmp((cs),(ct),(n)) : \
- memcmp((cs),(ct),(n)))
-
-#define __HAVE_ARCH_MEMCHR
-static inline void *memchr(const void *cs, int c, size_t count)
-{
-        /* Someone else can optimize this, I don't care - tonym@mac.linux-m68k.org */
-        unsigned char *ret = (unsigned char *)cs;
-        for(;count>0;count--,ret++)
-                if(*ret == c) return ret;
-
-        return NULL;
-}
+extern int memcmp(const void *, const void *, __kernel_size_t);
+#define memcmp(d, s, n) __builtin_memcmp(d, s, n)
 
 #endif /* _M68K_STRING_H_ */
diff --git a/include/asm-m68k/thread_info.h b/include/asm-m68k/thread_info.h
index 5f58939c59db..2aed24f6fd2e 100644
--- a/include/asm-m68k/thread_info.h
+++ b/include/asm-m68k/thread_info.h
@@ -8,7 +8,7 @@
 struct thread_info {
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         __u32 cpu; /* should always be 0 on m68k */
         struct restart_block    restart_block;
 
diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h
index f391cbe39b96..b5a1febc97d4 100644
--- a/include/asm-m68k/types.h
+++ b/include/asm-m68k/types.h
@@ -60,8 +60,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-m68k/uaccess.h b/include/asm-m68k/uaccess.h
index 605e6cb811f8..f5cedf19cf68 100644
--- a/include/asm-m68k/uaccess.h
+++ b/include/asm-m68k/uaccess.h
@@ -14,12 +14,6 @@
 /* We let the MMU do all checking */
 #define access_ok(type,addr,size) 1
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void *addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-m68knommu/auxvec.h b/include/asm-m68knommu/auxvec.h
new file mode 100644
index 000000000000..844d6d52204b
--- /dev/null
+++ b/include/asm-m68knommu/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMm68k_AUXVEC_H
+#define __ASMm68k_AUXVEC_H
+
+#endif
diff --git a/include/asm-m68knommu/emergency-restart.h b/include/asm-m68knommu/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-m68knommu/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-m68knommu/futex.h b/include/asm-m68knommu/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-m68knommu/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-m68knommu/hdreg.h b/include/asm-m68knommu/hdreg.h
deleted file mode 100644
index 5cdd9b084d37..000000000000
--- a/include/asm-m68knommu/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-m68k/hdreg.h>
diff --git a/include/asm-m68knommu/page.h b/include/asm-m68knommu/page.h
index 05e03df0ec29..942dfbead27f 100644
--- a/include/asm-m68knommu/page.h
+++ b/include/asm-m68knommu/page.h
@@ -48,20 +48,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 extern unsigned long memory_start;
 extern unsigned long memory_end;
 
@@ -73,8 +59,8 @@ extern unsigned long memory_end;
 
 #ifndef __ASSEMBLY__
 
-#define __pa(vaddr)             virt_to_phys((void *)vaddr)
-#define __va(paddr)             phys_to_virt((unsigned long)paddr)
+#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
+#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
 
 #define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
 #define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
@@ -84,6 +70,7 @@ extern unsigned long memory_end;
 
 #define pfn_to_page(pfn)        virt_to_page(pfn_to_virt(pfn))
 #define page_to_pfn(page)       virt_to_pfn(page_to_virt(page))
+#define pfn_valid(pfn)          ((pfn) < max_mapnr)
 
 #define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
                                 ((void *)(kaddr) < (void *)memory_end))
@@ -92,4 +79,6 @@ extern unsigned long memory_end;
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _M68KNOMMU_PAGE_H */
diff --git a/include/asm-m68knommu/thread_info.h b/include/asm-m68knommu/thread_info.h
index c8153b7c1f5c..7b9a3fa3af5d 100644
--- a/include/asm-m68knommu/thread_info.h
+++ b/include/asm-m68knommu/thread_info.h
@@ -36,7 +36,7 @@ struct thread_info {
         struct exec_domain *exec_domain;        /* execution domain */
         unsigned long      flags;               /* low level flags */
         int                cpu;                 /* cpu we're on */
-        int                preempt_count;       /* 0 => preemptable, <0 => BUG*/
+        int                preempt_count;       /* 0 => preemptable, <0 => BUG */
         struct restart_block restart_block;
 };
 
diff --git a/include/asm-m68knommu/uaccess.h b/include/asm-m68knommu/uaccess.h
index f0be74bb353c..05be9515a2d2 100644
--- a/include/asm-m68knommu/uaccess.h
+++ b/include/asm-m68knommu/uaccess.h
@@ -23,12 +23,6 @@ static inline int _access_ok(unsigned long addr, unsigned long size)
                 (is_in_rom(addr) && is_in_rom(addr+size)));
 }
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-{
-        return access_ok(type,addr,size)?0:-EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h
index e42b3093e903..2b3dc3bed4da 100644
--- a/include/asm-mips/a.out.h
+++ b/include/asm-mips/a.out.h
@@ -35,10 +35,10 @@ struct exec
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define STACK_TOP       TASK_SIZE
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define STACK_TOP       (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
 #endif
 
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 2caa8c427204..7dc2619f5006 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -48,7 +48,7 @@
 #define CPHYSADDR(a)            ((_ACAST32_ (a)) & 0x1fffffff)
 #define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * Memory segments (64bit kernel mode addresses)
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 37a460aa0378..30b18ea6cb11 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -7,14 +7,14 @@
  */
 #ifndef _ASM_ASMMACRO_H
 #define _ASM_ASMMACRO_H
- 
+
 #include <linux/config.h>
 #include <asm/hazards.h>
- 
-#ifdef CONFIG_MIPS32
+
+#ifdef CONFIG_32BIT
 #include <asm/asmmacro-32.h>
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #include <asm/asmmacro-64.h>
 #endif
 
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 7d89e87bc8c6..c0bd8d014e14 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -334,7 +334,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
  */
 #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 typedef struct { volatile __s64 counter; } atomic64_t;
 
@@ -639,7 +639,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
  */
 #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * atomic*_return operations are serializing but not the non-*_return
diff --git a/include/asm-mips/auxvec.h b/include/asm-mips/auxvec.h
new file mode 100644
index 000000000000..7cf7f2d21943
--- /dev/null
+++ b/include/asm-mips/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_AUXVEC_H
+#define _ASM_AUXVEC_H
+
+#endif /* _ASM_AUXVEC_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 779d2187a6a4..eb8d79dba11c 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -20,13 +20,13 @@
 #define SZLONG_MASK 31UL
 #define __LL    "ll     "
 #define __SC    "sc     "
-#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL    "lld    "
 #define __SC    "scd    "
-#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
 
 #ifdef __KERNEL__
@@ -533,14 +533,14 @@ static inline unsigned long ffz(unsigned long word)
         int b = 0, s;
 
         word = ~word;
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
         s =  8; if (word << 24 != 0) s = 0; b += s; word >>= s;
         s =  4; if (word << 28 != 0) s = 0; b += s; word >>= s;
         s =  2; if (word << 30 != 0) s = 0; b += s; word >>= s;
         s =  1; if (word << 31 != 0) s = 0; b += s;
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
         s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s;
         s =  8; if (word << 56 != 0) s = 0; b += s; word >>= s;
@@ -683,7 +683,7 @@ found_middle:
  */
 static inline int sched_find_first_bit(const unsigned long *b)
 {
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
@@ -694,7 +694,7 @@ static inline int sched_find_first_bit(const unsigned long *b)
                 return __ffs(b[3]) + 96;
         return __ffs(b[4]) + 128;
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index 18cced19cca4..b14b961c2100 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -15,7 +15,7 @@ extern void check_bugs64(void);
 static inline void check_bugs(void)
 {
         check_bugs32();
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         check_bugs64();
 #endif
 }
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index c25cc92b9950..c1ea5a8714f3 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -128,7 +128,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
 {
         __asm__(
         ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         "addu\t%0, %2\n\t"
         "sltu\t$1, %0, %2\n\t"
         "addu\t%0, $1\n\t"
@@ -141,7 +141,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
         "sltu\t$1, %0, %4\n\t"
         "addu\t%0, $1\n\t"
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         "daddu\t%0, %2\n\t"
         "daddu\t%0, %3\n\t"
         "daddu\t%0, %4\n\t"
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index dce92079e7fc..2c084cd4bc0a 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -15,8 +15,10 @@ typedef s32		compat_clock_t;
 typedef s32             compat_suseconds_t;
 
 typedef s32             compat_pid_t;
-typedef s32             compat_uid_t;
-typedef s32             compat_gid_t;
+typedef u32             __compat_uid_t;
+typedef u32             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u32             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
@@ -29,6 +31,7 @@ typedef s32		compat_caddr_t;
 typedef struct {
         s32     val[2];
 } compat_fsid_t;
+typedef s32             compat_timer_t;
 
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
@@ -51,8 +54,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid32_t        st_uid;
+        __compat_gid32_t        st_gid;
         compat_dev_t    st_rdev;
         s32             st_pad2[2];
         compat_off_t    st_size;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 1df2c299de82..9a2de642eee6 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -106,7 +106,7 @@
 #define PLAT_TRAMPOLINE_STUFF_LINE      0UL
 #endif
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 # endif
@@ -124,7 +124,7 @@
 # endif
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex                0
 # endif
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
index ae3e2a38fd5f..a438548e6ef3 100644
--- a/include/asm-mips/ddb5xxx/ddb5477.h
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
  *  All PCI irq but INTC are active low.
  */
 
-/* 
+/*
  * irq number block assignment
  */
 
@@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 #define VRC5477_IRQ_IOPCI_INTB  (17 + VRC5477_IRQ_BASE)      /* USB-P */
 #define VRC5477_IRQ_IOPCI_INTC  (18 + VRC5477_IRQ_BASE)      /* AC97 */
 #define VRC5477_IRQ_IOPCI_INTD  (19 + VRC5477_IRQ_BASE)      /* Reserved */
-#define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)     
+#define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)
 #define VRC5477_IRQ_SPT0        (21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
 #define VRC5477_IRQ_GPT0        (22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
 #define VRC5477_IRQ_GPT1        (23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
@@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 /*
  * i2859 irq assignment
  */
-#define I8259_IRQ_RESERVED_0    (0 + I8259_IRQ_BASE)    
+#define I8259_IRQ_RESERVED_0    (0 + I8259_IRQ_BASE)
 #define I8259_IRQ_KEYBOARD      (1 + I8259_IRQ_BASE)    /* M1543 default */
 #define I8259_IRQ_CASCADE       (2 + I8259_IRQ_BASE)
 #define I8259_IRQ_UART_B        (3 + I8259_IRQ_BASE)    /* M1543 default, may conflict with RTC according to schematic diagram  */
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
index b63e2f2317d1..a05d6d3395fe 100644
--- a/include/asm-mips/dec/prom.h
+++ b/include/asm-mips/dec/prom.h
@@ -48,15 +48,15 @@
  */
 #define REX_PROM_MAGIC          0x30464354
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define prom_is_rex(magic)      1       /* KN04 and KN05 are REX PROMs.  */
 
-#else /* !CONFIG_MIPS64 */
+#else /* !CONFIG_64BIT */
 
 #define prom_is_rex(magic)      ((magic) == REX_PROM_MAGIC)
 
-#endif /* !CONFIG_MIPS64 */
+#endif /* !CONFIG_64BIT */
 
 
 /*
@@ -105,7 +105,7 @@ extern int (*__pmax_read)(int, void *, int);
 extern int (*__pmax_close)(int);
 
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * On MIPS64 we have to call PROM functions via a helper
@@ -138,7 +138,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
 #define prom_getenv(x)          _prom_getenv(__prom_getenv, x)
 #define prom_printf(x...)       _prom_printf(__prom_printf, x)
 
-#else /* !CONFIG_MIPS64 */
+#else /* !CONFIG_64BIT */
 
 /*
  * On plain MIPS we just call PROM functions directly.
@@ -160,7 +160,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
 #define pmax_read               __pmax_read
 #define pmax_close              __pmax_close
 
-#endif /* !CONFIG_MIPS64 */
+#endif /* !CONFIG_64BIT */
 
 
 extern void prom_meminit(u32);
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index d0f68447e5a7..a606dbee0412 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -57,11 +57,11 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
          * The common rates of 1000 and 128 are rounded wrongly by the
          * catchall case for 64-bit.  Excessive precission?  Probably ...
          */
-#if defined(CONFIG_MIPS64) && (HZ == 128)
+#if defined(CONFIG_64BIT) && (HZ == 128)
         usecs *= 0x0008637bd05af6c7UL;          /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_MIPS64) && (HZ == 1000)
+#elif defined(CONFIG_64BIT) && (HZ == 1000)
         usecs *= 0x004189374BC6A7f0UL;          /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_MIPS64)
+#elif defined(CONFIG_64BIT)
         usecs *= (0x8000000000000000UL / (500000 / HZ));
 #else /* 32-bit junk follows here */
         usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index 7b92c8045cc2..e48811440015 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -125,7 +125,7 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef double elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 /*
  * This is used to ensure we don't load something for the wrong architecture.
@@ -153,9 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  */
 #define ELF_CLASS       ELFCLASS32
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  */
@@ -177,7 +177,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  */
 #define ELF_CLASS       ELFCLASS64
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * These are used to set parameters in the core dumps.
@@ -193,7 +193,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define SET_PERSONALITY(ex, ibcs2)                      \
 do {                                                    \
@@ -202,9 +202,9 @@ do {							\
         set_personality(PER_LINUX);                     \
 } while (0)
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define SET_PERSONALITY(ex, ibcs2)                              \
 do {    current->thread.mflags &= ~MF_ABI_MASK;                 \
@@ -222,7 +222,7 @@ do {	current->thread.mflags &= ~MF_ABI_MASK;			\
                 set_personality(PER_LINUX);                     \
 } while (0)
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
diff --git a/include/asm-mips/emergency-restart.h b/include/asm-mips/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-mips/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 2436392e7990..06c5d13faf66 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -8,33 +8,16 @@
 #ifndef _ASM_FCNTL_H
 #define _ASM_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE       0x0003
-#define O_RDONLY        0x0000
-#define O_WRONLY        0x0001
-#define O_RDWR          0x0002
 #define O_APPEND        0x0008
 #define O_SYNC          0x0010
 #define O_NONBLOCK      0x0080
 #define O_CREAT         0x0100  /* not fcntl */
-#define O_TRUNC         0x0200  /* not fcntl */
 #define O_EXCL          0x0400  /* not fcntl */
 #define O_NOCTTY        0x0800  /* not fcntl */
 #define FASYNC          0x1000  /* fcntl, for BSD compatibility */
 #define O_LARGEFILE     0x2000  /* allow large file opens */
 #define O_DIRECT        0x8000  /* direct disk access hint */
-#define O_DIRECTORY     0x10000 /* must be a directory */
-#define O_NOFOLLOW      0x20000 /* don't follow links */
-#define O_NOATIME       0x40000
 
-#define O_NDELAY        O_NONBLOCK
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
 #define F_GETLK         14
 #define F_SETLK         6
 #define F_SETLKW        7
@@ -50,33 +33,6 @@
 #define F_SETLKW64      35
 #endif
 
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
 /*
  * The flavours of struct flock.  "struct flock" is the ABI compliant
  * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
@@ -86,7 +42,7 @@
 
 #ifndef __mips64
 
-typedef struct flock {
+struct flock {
         short   l_type;
         short   l_whence;
         __kernel_off_t l_start;
@@ -94,32 +50,17 @@ typedef struct flock {
         long    l_sysid;
         __kernel_pid_t l_pid;
         long    pad[4];
-} flock_t;
-
-typedef struct flock64 {
-        short   l_type;
-        short   l_whence;
-        loff_t  l_start;
-        loff_t  l_len;
-        pid_t   l_pid;
-} flock64_t;
+};
 
-#else /* 64-bit definitions */
+#define HAVE_ARCH_STRUCT_FLOCK
 
-typedef struct flock {
-        short   l_type;
-        short   l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
-        __kernel_pid_t l_pid;
-} flock_t;
-
-#ifdef __KERNEL__
-#define flock64         flock
 #endif
 
-#endif
+#include <asm-generic/fcntl.h>
 
-#define F_LINUX_SPECIFIC_BASE   1024
+typedef struct flock flock_t;
+#ifndef __mips64
+typedef struct flock64 flock64_t;
+#endif
 
 #endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
index 1d9aa0979181..2b5fddc8f487 100644
--- a/include/asm-mips/fpregdef.h
+++ b/include/asm-mips/fpregdef.h
@@ -13,7 +13,7 @@
 #define _ASM_FPREGDEF_H
 
 #include <asm/sgidefs.h>
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
@@ -56,7 +56,7 @@
 #define fcr31   $31      /* FPU status register */
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
 #define fv0     $f0     /* return value */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index 6cb38d5c0407..ea24e733b1bc 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -82,7 +82,7 @@ do {									\
 
 static inline int is_fpu_owner(void)
 {
-        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 
+        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
 }
 
 static inline void own_fpu(void)
@@ -90,7 +90,7 @@ static inline void own_fpu(void)
         if (cpu_has_fpu) {
                 __enable_fpu();
                 KSTK_STATUS(current) |= ST0_CU1;
-                set_thread_flag(TIF_USEDFPU); 
+                set_thread_flag(TIF_USEDFPU);
         }
 }
 
@@ -98,7 +98,7 @@ static inline void lose_fpu(void)
 {
         if (cpu_has_fpu) {
                 KSTK_STATUS(current) &= ~ST0_CU1;
-                clear_thread_flag(TIF_USEDFPU); 
+                clear_thread_flag(TIF_USEDFPU);
                 __disable_fpu();
         }
 }
@@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk)
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
         if (cpu_has_fpu) {
-                if ((tsk == current) && is_fpu_owner()) 
+                if ((tsk == current) && is_fpu_owner())
                         _save_fp(current);
                 return tsk->thread.fpu.hard.fpr;
         }
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
new file mode 100644
index 000000000000..9feff4ce1424
--- /dev/null
+++ b/include/asm-mips/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-mips/hdreg.h b/include/asm-mips/hdreg.h
deleted file mode 100644
index 5989bbc97cbf..000000000000
--- a/include/asm-mips/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#warning this file is obsolete, please do not use it
diff --git a/include/asm-mips/hp-lj/asic.h b/include/asm-mips/hp-lj/asic.h
deleted file mode 100644
index fc2ca656da00..000000000000
--- a/include/asm-mips/hp-lj/asic.h
+++ /dev/null
@@ -1,7 +0,0 @@
-
-typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId;
-
-AsicId GetAsicId(void);
-
-const char* const GetAsicName(void);
-
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 2b7b0fdeac19..432011b16c26 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -94,7 +94,7 @@ struct mace_video {
         unsigned long xxx;      /* later... */
 };
 
-/* 
+/*
  * Ethernet interface
  */
 struct mace_ethernet {
@@ -129,7 +129,7 @@ struct mace_ethernet {
         volatile unsigned long rx_fifo;
 };
 
-/* 
+/*
  * Peripherals
  */
 
@@ -251,7 +251,7 @@ struct mace_timers {
         timer_reg audio_out2;
         timer_reg video_in1;
         timer_reg video_in2;
-        timer_reg video_out;    
+        timer_reg video_out;
 };
 
 struct mace_perif {
@@ -272,7 +272,7 @@ struct mace_perif {
 };
 
 
-/* 
+/*
  * ISA peripherals
  */
 
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index 21d0fb7cee64..9e88c7669c7a 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -1,13 +1,13 @@
 #include <asm/lasat/lasat.h>
 
 /* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100             ( 7372800 / 16 ) 
+#define LASAT_BASE_BAUD_100             ( 7372800 / 16 )
 #define LASAT_UART_REGS_BASE_100        0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100       2
 #define LASATINT_UART_100               8
 
 /* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12) 
+#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
 #define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
 #define LASAT_UART_REGS_SHIFT_200       3
 #define LASATINT_UART_200               13
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index 7eb6bf661b80..c38844f615fc 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -5,7 +5,7 @@
 #include <linux/percpu.h>
 #include <asm/atomic.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 typedef atomic_t local_t;
 
@@ -20,7 +20,7 @@ typedef atomic_t local_t;
 
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 typedef atomic64_t local_t;
 
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 2b36ea346910..148bae2fa7d3 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
-#define PCI_MEM_END     0 
+#define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
 #endif
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 4691398a414f..efafe65258b6 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -23,7 +23,7 @@
  *
  * ########################################################################
  *
- * 
+ *
  */
 #ifndef __ASM_DB1X00_H
 #define __ASM_DB1X00_H
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 63c0a81c7832..5a2c1efb4eb7 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -12,7 +12,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define CAC_BASE                0x80000000
 #define IO_BASE                 0xa0000000
@@ -32,9 +32,9 @@
 #define HIGHMEM_START           0x20000000UL
 #endif
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * This handles the memory map.
@@ -67,6 +67,6 @@
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index 30d42fcafe3d..e96166f27c49 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -12,7 +12,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define CAC_BASE                0x80000000
 #define IO_BASE                 0xa0000000
@@ -32,9 +32,9 @@
 #define HIGHMEM_START           0x20000000UL
 #endif
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define PAGE_OFFSET             0xffffffff80000000UL
 
 #ifndef HIGHMEM_START
@@ -50,6 +50,6 @@
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index b932237f2193..04713973c6c3 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -18,7 +18,7 @@
  * so, for 64bit IP32 kernel we just don't use ll/sc.
  * This does not affect luserland.
  */
-#if defined(CONFIG_CPU_R5000) && defined(CONFIG_MIPS64)
+#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT)
 #define cpu_has_llsc            0
 #else
 #define cpu_has_llsc            1
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
index 8cf0d042c864..c9dad99b1232 100644
--- a/include/asm-mips/mach-jazz/floppy.h
+++ b/include/asm-mips/mach-jazz/floppy.h
@@ -92,7 +92,7 @@ static inline int fd_request_irq(void)
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
                            SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
 }
-                                                                                
+
 static inline void fd_free_irq(void)
 {
         free_irq(FLOPPY_IRQ, NULL);
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index d6c779747b3c..ff6d40c87a25 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -33,11 +33,11 @@
 #define PCI_BOARD_REG             0xAE000010
 #define PCMCIA_BOARD_REG          0xAE000010
   #define PC_DEASSERT_RST               0x80
-  #define PC_DRV_EN                     0x10 
+  #define PC_DRV_EN                     0x10
 #define PB1500_G_CONTROL          0xAE000014
 #define PB1500_RST_VDDI           0xAE00001C
 #define PB1500_LEDS               0xAE000018
-  
+
 #define PB1500_HEX_LED            0xAF000004
 #define PB1500_HEX_LED_BLANK      0xAF000008
 
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f4e370e27168
--- /dev/null
+++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
+ */
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+
+#define cpu_has_dsp             0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          0
+
+#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h
new file mode 100644
index 000000000000..cb30ee490ae6
--- /dev/null
+++ b/include/asm-mips/mach-qemu/param.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_PARAM_H
+#define __ASM_MACH_QEMU_PARAM_H
+
+#define HZ              100             /* Internal kernel timer frequency */
+
+#endif /* __ASM_MACH_QEMU_PARAM_H */
diff --git a/include/asm-mips/mach-vr41xx/timex.h b/include/asm-mips/mach-vr41xx/timex.h
deleted file mode 100644
index 8d71485d003a..000000000000
--- a/include/asm-mips/mach-vr41xx/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-/*
- * Changes:
- *  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
- *  - CLOCK_TICK_RATE is changed into 32768 from 6144000.
- */
-#ifndef __ASM_MACH_VR41XX_TIMEX_H
-#define __ASM_MACH_VR41XX_TIMEX_H
-
-#define CLOCK_TICK_RATE         32768
-
-#endif /* __ASM_MACH_VR41XX_TIMEX_H */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 48b77c9fb4f2..45cd72d172e8 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -28,17 +28,17 @@ extern unsigned long pgd_current[];
 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
         pgd_current[smp_processor_id()] = (unsigned long)(pgd)
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 23);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 23);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index 29ee13be0b2a..d721143dbd47 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -8,6 +8,8 @@
 #include <asm/page.h>
 #include <mmzone.h>
 
+#ifdef CONFIG_DISCONTIGMEM
+
 #define kvaddr_to_nid(kvaddr)   pa_to_nid(__pa(kvaddr))
 #define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
 
@@ -36,4 +38,6 @@
 /* XXX: FIXME -- wli */
 #define kern_addr_valid(addr)   (0)
 
+#endif /* CONFIG_DISCONTIGMEM */
+
 #endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 90ee24aad955..0be58b2aeb9f 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -25,7 +25,7 @@ typedef struct
   Elf64_Sxword r_addend;                /* Addend.  */
 } Elf64_Mips_Rela;
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
@@ -33,7 +33,7 @@ typedef struct
 
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define Elf_Shdr        Elf64_Shdr
 #define Elf_Sym         Elf64_Sym
diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h
index 513b2824838b..a1533959742e 100644
--- a/include/asm-mips/msgbuf.h
+++ b/include/asm-mips/msgbuf.h
@@ -15,25 +15,25 @@
 
 struct msqid64_ds {
         struct ipc64_perm msg_perm;
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused1;
 #endif
         __kernel_time_t msg_stime;      /* last msgsnd time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused1;
 #endif
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused2;
 #endif
         __kernel_time_t msg_rtime;      /* last msgrcv time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused2;
 #endif
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused3;
 #endif
         __kernel_time_t msg_ctime;      /* last change time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused3;
 #endif
         unsigned long  msg_cbytes;      /* current number of bytes on queue */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 36cec9e31696..309bc3099f68 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -16,10 +16,10 @@
 #include <linux/config.h>
 #include <linux/errno.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __PA_ADDR       ".word"
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define __PA_ADDR       ".dword"
 #endif
 
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index d1bf8240e73b..652b6d67a571 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -103,20 +103,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #endif /* !__ASSEMBLY__ */
 
 /* to align the pointer to the (next) page boundary */
@@ -127,7 +113,7 @@ static __inline__ int get_order(unsigned long size)
 
 #define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
 
-#ifndef CONFIG_DISCONTIGMEM
+#ifndef CONFIG_NEED_MULTIPLE_NODES
 #define pfn_to_page(pfn)        (mem_map + (pfn))
 #define page_to_pfn(page)       ((unsigned long)((page) - mem_map))
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
@@ -148,4 +134,6 @@ static __inline__ int get_order(unsigned long size)
 #define WANT_PAGE_VIRTUAL
 #endif
 
+#include <asm-generic/page.h>
+
 #endif /* _ASM_PAGE_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c9c576b48556..c9a00ca1c012 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -69,7 +69,7 @@ extern unsigned long PCIBIOS_MIN_MEM;
 
 extern void pcibios_set_master(struct pci_dev *dev);
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -94,7 +94,7 @@ struct pci_dev;
  */
 extern unsigned int PCI_DMA_BUS_IS_PHYS;
 
-#ifdef CONFIG_MAPPED_DMA_IO
+#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
 
 /* pci_unmap_{single,page} is not a nop, thus... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
@@ -104,7 +104,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS;
 #define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
 
-#else /* CONFIG_MAPPED_DMA_IO  */
+#else /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
 
 /* pci_unmap_{page,single} is a nop so... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
@@ -114,7 +114,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS;
 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 
-#endif /* CONFIG_MAPPED_DMA_IO  */
+#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
 
 /* This is always fine. */
 #define pci_dac_dma_supported(pci_dev, mask)    (1)
@@ -130,8 +130,20 @@ extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev,
 extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
         dma64_addr_t dma_addr, size_t len, int direction);
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
         struct pci_bus_region *region, struct resource *res);
+extern void pcibios_bus_to_resource(struct pci_dev *dev,
+        struct resource *res, struct pci_bus_region *region);
 
 #ifdef CONFIG_PCI_DOMAINS
 
@@ -157,4 +169,17 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 /* Do platform specific device initialization at pci_enable_device() time */
 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index 2d63f5ba403f..ce57288d43bd 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -85,7 +85,7 @@ static inline void pte_free(struct page *pte)
 
 #define __pte_free_tlb(tlb,pte)         tlb_remove_page((tlb),(pte))
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define pgd_populate(mm, pmd, pte)      BUG()
 
 /*
@@ -97,7 +97,7 @@ static inline void pte_free(struct page *pte)
 #define __pmd_free_tlb(tlb,x)           do { } while (0)
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define pgd_populate(mm, pgd, pmd)      set_pgd(pgd, __pgd(pmd))
 
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 878843203d67..dbe13da0bdad 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -11,10 +11,10 @@
 #include <asm-generic/4level-fixup.h>
 
 #include <linux/config.h>
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #include <asm/pgtable-64.h>
 #endif
 
@@ -350,7 +350,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         __update_cache(vma, address, pte);
 }
 
-#ifndef CONFIG_DISCONTIGMEM
+#ifndef CONFIG_NEED_MULTIPLE_NODES
 #define kern_addr_valid(addr)   (1)
 #endif
 
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 13c54d5b3b48..d6466aa09fb7 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -33,7 +33,7 @@ extern void (*cpu_wait)(void);
 
 extern unsigned int vced_count, vcei_count;
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 /*
  * User space process size: 2GB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.
@@ -47,7 +47,7 @@ extern unsigned int vced_count, vcei_count;
 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 /*
  * User space process size: 1TB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.  TASK_SIZE
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index d3c46d633826..2b5c624c3d4f 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -28,7 +28,7 @@
  * system call/exception. As usual the registers k0/k1 aren't being saved.
  */
 struct pt_regs {
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         /* Pad bytes for argument save space on the stack. */
         unsigned long pad0[6];
 #endif
diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h
new file mode 100644
index 000000000000..905c39585903
--- /dev/null
+++ b/include/asm-mips/qemu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_QEMU_H
+#define __ASM_QEMU_H
+
+/*
+ * Interrupt numbers
+ */
+#define Q_PIC_IRQ_BASE          0
+#define Q_COUNT_COMPARE_IRQ     16
+
+/*
+ * Qemu clock rate.  Unlike on real MIPS this has no relation to the
+ * instruction issue rate, so the choosen value is pure fiction, just needs
+ * to match the value in Qemu itself.
+ */
+#define QEMU_C0_COUNTER_CLOCK   100000000
+
+#endif /* __ASM_QEMU_H */
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index da03a32c1ca7..5bea49feec66 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -171,11 +171,11 @@ static inline void blast_dcache16(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.dcache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-        unsigned long ws_end = current_cpu_data.dcache.ways << 
+        unsigned long ws_end = current_cpu_data.dcache.ways <<
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
@@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -214,8 +214,8 @@ static inline void blast_icache16(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -249,11 +249,11 @@ static inline void blast_scache16(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -318,8 +318,8 @@ static inline void blast_dcache32(void)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -357,8 +357,8 @@ static inline void blast_icache32(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page)
         unsigned long ws, addr;
 
         for (ws = 0; ws < ws_end; ws += ws_inc)
-                for (addr = start; addr < end; addr += 0x400) 
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -392,11 +392,11 @@ static inline void blast_scache32(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -461,8 +461,8 @@ static inline void blast_icache64(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x800) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page)
         unsigned long ws, addr;
 
         for (ws = 0; ws < ws_end; ws += ws_inc)
-                for (addr = start; addr < end; addr += 0x800) 
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -496,11 +496,11 @@ static inline void blast_scache64(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x800) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -561,11 +561,11 @@ static inline void blast_scache128(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x1000)
                         cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x1000) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x1000)
                         cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
index 7b33bbca9585..6173004cc88e 100644
--- a/include/asm-mips/reg.h
+++ b/include/asm-mips/reg.h
@@ -14,7 +14,7 @@
 
 #include <linux/config.h>
 
-#if defined(CONFIG_MIPS32) || defined(WANT_COMPAT_REG_H)
+#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
 
 #define EF_R0                   6
 #define EF_R1                   7
@@ -70,7 +70,7 @@
 
 #endif
 
-#if CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define EF_R0                    0
 #define EF_R1                    1
@@ -124,6 +124,6 @@
 
 #define EF_SIZE                 304     /* size in bytes */
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h
index fd3c6d17a5f6..1fba00c22077 100644
--- a/include/asm-mips/resource.h
+++ b/include/asm-mips/resource.h
@@ -27,7 +27,7 @@
  * but we keep the old value on MIPS32,
  * for compatibility:
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 # define RLIM_INFINITY          0x7fffffffUL
 #endif
 
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 31c0c2347f4f..3c4b637fd925 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-mips/rtc.h 
+ * include/asm-mips/rtc.h
  *
  * (Really an interface for drivers/char/genrtc.c)
  *
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 8a70ff58f760..4eed8e2acdc3 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -29,32 +29,6 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#define HUB6_FLAGS 0
-#define RS_TABLE_SIZE   64
-#else
-#define RS_TABLE_SIZE
-#endif
-
-/*
- * The following define the access methods for the HUB6 card. All
- * access is through two ports for all 24 possible chips. The card is
- * selected through the high 2 bits, the port on that card with the
- * "middle" 3 bits, and the register on that port with the bottom
- * 3 bits.
- *
- * While the access port and interrupt is configurable, the default
- * port locations are 0x302 for the port control register, and 0x303
- * for the data read/write register. Normally, the interrupt is at irq3
- * but can be anything from 3 to 7 inclusive. Note that using 3 will
- * require disabling com2.
- */
-
-#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
-
 #ifdef CONFIG_MACH_JAZZ
 #include <asm/jazz.h>
 
@@ -240,66 +214,10 @@
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },                  /* ttyS14 (spare) */ \
-        { 0, BASE_BAUD, 0x000, 0, 0 },                  /* ttyS15 (spare) */ \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else /* CONFIG_SERIAL_MANY_PORTS */
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif /* CONFIG_SERIAL_MANY_PORTS */
-
 #else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
 #define STD_SERIAL_PORT_DEFNS
-#define EXTRA_SERIAL_PORT_DEFNS
 #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
 
-/* You can have up to four HUB6's in the system, but I've only
- * included two cards here for a total of twelve ports.
- */
-#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
-#define HUB6_SERIAL_PORT_DFNS           \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
-#else
-#define HUB6_SERIAL_PORT_DFNS
-#endif
-
 #ifdef CONFIG_MOMENCO_JAGUAR_ATX
 /* Ordinary NS16552 duart with a 20MHz crystal.  */
 #define JAGUAR_ATX_UART_CLK     20000000
@@ -427,8 +345,6 @@
         COBALT_SERIAL_PORT_DEFNS                        \
         DDB5477_SERIAL_PORT_DEFNS                       \
         EV96100_SERIAL_PORT_DEFNS                       \
-        EXTRA_SERIAL_PORT_DEFNS                         \
-        HUB6_SERIAL_PORT_DFNS                           \
         IP32_SERIAL_PORT_DEFNS                          \
         ITE_SERIAL_PORT_DEFNS                           \
         IVR_SERIAL_PORT_DEFNS                           \
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
index a38d66f99872..889cf028c95d 100644
--- a/include/asm-mips/sgi/gio.h
+++ b/include/asm-mips/sgi/gio.h
@@ -16,7 +16,7 @@
  *
  * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
  * three physical connectors, but only two slots, GFX and EXP0.
- * 
+ *
  * There is 10MB of GIO address space for GIO64 slot devices
  * slot#   slot type address range            size
  * -----   --------- ----------------------- -----
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index a5b988d7327a..ac3dfc7af5b0 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -221,7 +221,7 @@ struct hpc3_regs {
 #define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
 
         u32 _unused1[0x14000/4 - 5];    /* padding */
-        
+
         /* Now direct PIO per-HPC3 peripheral access to external regs. */
         volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
         u32 _unused2[0x7c00/4];
@@ -304,7 +304,7 @@ struct hpc3_regs {
         volatile u32 bbram[8192-50-14]; /* Battery backed ram */
 };
 
-/* 
+/*
  * It is possible to have two HPC3's within the address space on
  * one machine, though only having one is more likely on an Indy.
  */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index 169187f53fbc..f3e3dc9bb732 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -16,7 +16,7 @@
 #include <linux/types.h>
 #include <asm/sgi/pi1.h>
 
-/* 
+/*
  * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
  * happen if you try word access them. You have been warned.
  */
@@ -138,7 +138,7 @@ struct sgioc_regs {
         u8 _sysid[3];
         volatile u8 sysid;
 #define SGIOC_SYSID_FULLHOUSE   0x01
-#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 
+#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
 #define SGIOC_SYSID_CHIPREV(x)  ((x & 0x1e) > 1)
         u32 _unused2;
         u8 _read[3];
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 97d73adb4e40..bbfc05c3cab9 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -12,7 +12,7 @@
 #ifndef _SGI_IP22_H
 #define _SGI_IP22_H
 
-/* 
+/*
  * These are the virtual IRQ numbers, we divide all IRQ's into
  * 'spaces', the 'space' determines where and how to enable/disable
  * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index fd98f930607c..c52f7834c7c8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -182,14 +182,14 @@ struct sgimc_regs {
         volatile u32 dtlb_hi3;
         u32 _unused33;
         volatile u32 dtlb_lo3;
-        
+
         u32 _unused34[0x0392];
-        
+
         u32 _unused35;
         volatile u32 rpsscounter;       /* Chirps at 100ns */
 
         u32 _unused36[0x1000/4-2*4];
-        
+
         u32 _unused37;
         volatile u32 maddronly;         /* Address DMA goes at */
         u32 _unused38;
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
index 59450335f049..722b77a8c5e5 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/include/asm-mips/sgiarcs.h
@@ -367,7 +367,7 @@ struct linux_smonblock {
  * Macros for calling a 32-bit ARC implementation from 64-bit code
  */
 
-#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32)
+#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
 
 #define __arc_clobbers                                                  \
         "$2","$3" /* ... */, "$8","$9","$10","$11",                     \
@@ -476,10 +476,10 @@ struct linux_smonblock {
         __res;                                                          \
 })
 
-#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
 
-#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) ||                \
-    (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64))
+#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
+    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
 
 #define ARC_CALL0(dest)                                                 \
 ({      long __res;                                                     \
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 7ac5da13ce8a..b5e7dae19f0f 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -25,12 +25,12 @@
 
 #define SIBYTE_BOARD_NAME "Carmel"
 
-#define GPIO_PHY_INTERRUPT      2 
-#define GPIO_NONMASKABLE_INT    3 
-#define GPIO_CF_INSERTED        6 
-#define GPIO_MONTEREY_RESET     7 
-#define GPIO_QUADUART_INT       8 
-#define GPIO_CF_INT             9 
+#define GPIO_PHY_INTERRUPT      2
+#define GPIO_NONMASKABLE_INT    3
+#define GPIO_CF_INSERTED        6
+#define GPIO_MONTEREY_RESET     7
+#define GPIO_QUADUART_INT       8
+#define GPIO_CF_INT             9
 #define GPIO_FPGA_CCLK          10
 #define GPIO_FPGA_DOUT          11
 #define GPIO_FPGA_DIN           12
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 96088fb074a4..40ef97c76c8b 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
-    *  Global constants and macros              File: sb1250_defs.h     
-    *  
+    *
+    *  Global constants and macros              File: sb1250_defs.h
+    *
     *  This file contains macros and definitions used by the other
     *  include files.
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -105,7 +105,7 @@
 #define SIBYTE_HDR_FMASK_112x_ALL               0x0000f00
 #define SIBYTE_HDR_FMASK_112x_PASS1             0x0000100
 
-/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */ 
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
 #define SIBYTE_HDR_FMASK(chip, pass)                                    \
     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
 #define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
@@ -150,31 +150,31 @@
 
 /*  *********************************************************************
     *  Naming schemes for constants in these files:
-    *  
-    *  M_xxx           MASK constant (identifies bits in a register). 
+    *
+    *  M_xxx           MASK constant (identifies bits in a register).
     *                  For multi-bit fields, all bits in the field will
     *                  be set.
     *
     *  K_xxx           "Code" constant (value for data in a multi-bit
     *                  field).  The value is right justified.
     *
-    *  V_xxx           "Value" constant.  This is the same as the 
+    *  V_xxx           "Value" constant.  This is the same as the
     *                  corresponding "K_xxx" constant, except it is
     *                  shifted to the correct position in the register.
     *
     *  S_xxx           SHIFT constant.  This is the number of bits that
-    *                  a field value (code) needs to be shifted 
+    *                  a field value (code) needs to be shifted
     *                  (towards the left) to put the value in the right
     *                  position for the register.
     *
-    *  A_xxx           ADDRESS constant.  This will be a physical 
+    *  A_xxx           ADDRESS constant.  This will be a physical
     *                  address.  Use the PHYS_TO_K1 macro to generate
     *                  a K1SEG address.
     *
     *  R_xxx           RELATIVE offset constant.  This is an offset from
     *                  an A_xxx constant (usually the first register in
     *                  a group).
-    *  
+    *
     *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
     *                  from a register, masks it, and shifts it to
     *                  the bottom of the register (retrieving a K_xxx
@@ -189,7 +189,7 @@
 
 
 /*
- * Cast to 64-bit number.  Presumably the syntax is different in 
+ * Cast to 64-bit number.  Presumably the syntax is different in
  * assembly language.
  *
  * Note: you'll need to define uint32_t and uint64_t in your headers.
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index f1b08d32338d..3cdb48f50ed0 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -1,24 +1,24 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  DMA definitions                          File: sb1250_dma.h
-    *  
+    *
     *  This module contains constants and macros useful for
     *  programming the SB1250's DMA controllers, both the data mover
     *  and the Ethernet DMA.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -28,7 +28,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -43,9 +43,9 @@
     *  DMA Registers
     ********************************************************************* */
 
-/* 
+/*
  * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
- * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
  * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
  * Registers: DMA_CONFIG0_SER_x_RX
  * Registers: DMA_CONFIG0_SER_x_TX
@@ -98,7 +98,7 @@
 
 /*
  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
- * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
  * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
  * Registers: DMA_CONFIG1_SER_x_RX
  * Registers: DMA_CONFIG1_SER_x_TX
@@ -152,11 +152,11 @@
 /*
  * DMA Descriptor Count Registers (Table 7-8)
  */
- 
+
 /* No bitfields */
 
 
-/* 
+/*
  * Current Descriptor Address Register (Table 7-11)
  */
 
@@ -275,14 +275,14 @@
 #define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
 #define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
 
-/* 
+/*
  * Ethernet Descriptor Status Bits (Table 7-15)
  */
 
 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 /* Note: BADTCPCS is actually in DSCR_B options field */
 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
 #endif /* 1250 PASS2 || 112x PASS1 */
@@ -324,7 +324,7 @@
 
 #define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
 
-/* 
+/*
  * Ethernet Transmit Options (Table 7-17)
  */
 
@@ -377,7 +377,7 @@
     *  Data Mover Registers
     ********************************************************************* */
 
-/* 
+/*
  * Data Mover Descriptor Base Address Register (Table 7-22)
  * Register: DM_DSCR_BASE_0
  * Register: DM_DSCR_BASE_1
@@ -414,7 +414,7 @@
 #define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
 #define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
 
-/* 
+/*
  * Data Mover Descriptor Count Register (Table 7-25)
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index 0d9dfac3d7db..f1f509f295c4 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Generic Bus Constants                     File: sb1250_genbus.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's Generic Bus interface
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index c3f74df211f4..e173e2ea4c98 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Interrupt Mapper definitions             File: sb1250_int.h
-    *  
+    *
     *  This module contains constants for manipulating the SB1250's
     *  interrupt mapper and definitions for the interrupt sources.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -43,7 +43,7 @@
 
 /*
  * Interrupt sources (Table 4-8, UM 0.2)
- * 
+ *
  * First, the interrupt numbers.
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 799db828d963..8afe8e01581b 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  L2 Cache constants and macros            File: sb1250_l2c.h
-    *  
+    *
     *  This module contains constants useful for manipulating the
     *  level 2 cache.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index d8753885df17..f2617ded0a8f 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  LDT constants                            File: sb1250_ldt.h
-    *  
-    *  This module contains constants and macros to describe 
-    *  the LDT interface on the SB1250.  
-    *  
+    *
+    *  This module contains constants and macros to describe
+    *  the LDT interface on the SB1250.
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -155,7 +155,7 @@
 
 /*
  * LDT Status Register (Table 8-14).  Note that these constants
- * assume you've read the command and status register 
+ * assume you've read the command and status register
  * together (32-bit read at offset 0x04)
  *
  * These bits also apply to the secondary status
@@ -183,8 +183,8 @@
 #define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
 
 /*
- * Bridge Control Register (Table 8-16).  Note that these 
- * constants assume you've read the register as a 32-bit 
+ * Bridge Control Register (Table 8-16).  Note that these
+ * constants assume you've read the register as a 32-bit
  * read (offset 0x3C)
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 81f603f03a98..18e74e43f4a2 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  MAC constants and macros                 File: sb1250_mac.h
-    *  
+    *
     *  This module contains constants and macros for the SB1250's
     *  ethernet controllers.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -311,7 +311,7 @@
 
 /*
  * These constants are used to configure the fields within the Frame
- * Configuration Register.  
+ * Configuration Register.
  */
 
 #define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
@@ -393,7 +393,7 @@
  * Register: MAC_INT_MASK_2
  */
 
-/* 
+/*
  * Use these constants to shift the appropriate channel
  * into the CH0 position so the same tests can be used
  * on each channel.
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 93a48334b874..1dd41c927996 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
-    *  Memory Controller constants              File: sb1250_mc.h       
-    *  
+    *
+    *  Memory Controller constants              File: sb1250_mc.h
+    *
     *  This module contains constants and macros useful for
     *  programming the memory controller.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -166,7 +166,7 @@
 
 #define K_MC_REF_RATE_100MHz         0x62
 #define K_MC_REF_RATE_133MHz         0x81
-#define K_MC_REF_RATE_200MHz         0xC4 
+#define K_MC_REF_RATE_200MHz         0xC4
 
 #define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
 #define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
@@ -228,7 +228,7 @@
                                      V_MC_ADDR_DRIVE_DEFAULT | \
                                      V_MC_DATA_DRIVE_DEFAULT | \
                                      V_MC_CLOCK_DRIVE_DEFAULT | \
-                                     V_MC_REF_RATE_DEFAULT 
+                                     V_MC_REF_RATE_DEFAULT
 
 
 
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 5d496c6faba6..9db80cd13a79 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Register Definitions                     File: sb1250_regs.h
-    *  
+    *
     *  This module contains the addresses of the on-chip peripherals
     *  on the SB1250.
-    *  
+    *
     *  SB1250 specification level:  01/02/2002
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -40,20 +40,20 @@
 
 /*  *********************************************************************
     *  Some general notes:
-    *  
+    *
     *  For the most part, when there is more than one peripheral
     *  of the same type on the SOC, the constants below will be
     *  offsets from the base of each peripheral.  For example,
     *  the MAC registers are described as offsets from the first
     *  MAC register, and there will be a MAC_REGISTER() macro
-    *  to calculate the base address of a given MAC.  
-    *  
+    *  to calculate the base address of a given MAC.
+    *
     *  The information in this file is based on the SB1250 SOC
     *  manual version 0.2, July 2000.
     ********************************************************************* */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Memory Controller Registers
     ********************************************************************* */
 
@@ -101,7 +101,7 @@
 #define R_MC_TEST_ECC               0x0000000420
 #define R_MC_MCLK_CFG               0x0000000500
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * L2 Cache Control Registers
     ********************************************************************* */
 
@@ -126,7 +126,7 @@
 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * PCI Interface Registers
     ********************************************************************* */
 
@@ -134,7 +134,7 @@
 #define A_PCI_TYPE01_HEADER         0x00DE000800
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Ethernet DMA and MACs
     ********************************************************************* */
 
@@ -184,7 +184,7 @@
             (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
             (reg))
 
-/* 
+/*
  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
  */
 
@@ -259,7 +259,7 @@
 #define MAC_CHMAP_COUNT                 4
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * DUART Registers
     ********************************************************************* */
 
@@ -363,7 +363,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Synchronous Serial Registers
     ********************************************************************* */
 
@@ -397,7 +397,7 @@
             (reg))
 
 
-/* 
+/*
  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
  */
 
@@ -457,7 +457,7 @@
 #define R_SER_RMON_RX_ERRORS        0x000001F0
 #define R_SER_RMON_RX_BADADDR       0x000001F8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Generic Bus Registers
     ********************************************************************* */
 
@@ -513,7 +513,7 @@
 #define R_IO_PCMCIA_CFG             0x0A60
 #define R_IO_PCMCIA_STATUS          0x0A70
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * GPIO Registers
     ********************************************************************* */
 
@@ -537,7 +537,7 @@
 #define R_GPIO_PIN_CLR              0x30
 #define R_GPIO_PIN_SET              0x38
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * SMBus Registers
     ********************************************************************* */
 
@@ -573,7 +573,7 @@
 #define R_SMB_CONTROL               0x0000000060
 #define R_SMB_PEC                   0x0000000070
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Timer Registers
     ********************************************************************* */
 
@@ -641,7 +641,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Control Registers
     ********************************************************************* */
 
@@ -649,7 +649,7 @@
 #define A_SCD_SYSTEM_CFG            0x0010020008
 #define A_SCD_SYSTEM_MANUF          0x0010038000
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Address Trap Registers
     ********************************************************************* */
 
@@ -672,7 +672,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Interrupt Mapper Registers
     ********************************************************************* */
 
@@ -701,7 +701,7 @@
 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
 #define R_IMR_INTERRUPT_MAP_COUNT       64
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Performance Counter Registers
     ********************************************************************* */
 
@@ -711,7 +711,7 @@
 #define A_SCD_PERF_CNT_2            0x00100204E0
 #define A_SCD_PERF_CNT_3            0x00100204E8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Bus Watcher Registers
     ********************************************************************* */
 
@@ -726,13 +726,13 @@
 #define A_BUS_L2_ERRORS             0x00100208C0
 #define A_BUS_MEM_IO_ERRORS         0x00100208C8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Debug Controller Registers
     ********************************************************************* */
 
 #define A_SCD_JTAG_BASE             0x0010000000
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Trace Buffer Registers
     ********************************************************************* */
 
@@ -755,7 +755,7 @@
 #define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
 #define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Generic DMA Registers
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 22e8041959e2..dbbd682fb47e 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  SCD Constants and Macros                 File: sb1250_scd.h
-    *  
+    *
     *  This module contains constants and macros useful for
     *  manipulating the System Control and Debug module on the 1250.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -130,40 +130,40 @@
 /* System Manufacturing Register
 * Register: SCD_SYSTEM_MANUF
 */
- 
+
 /* Wafer ID: bits 31:0 */
 #define S_SYS_WAFERID1_200        _SB_MAKE64(0)
 #define M_SYS_WAFERID1_200        _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
 #define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
 #define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
- 
+
 #define S_SYS_BIN                 _SB_MAKE64(32)
 #define M_SYS_BIN                 _SB_MAKEMASK(4,S_SYS_BIN)
 #define V_SYS_BIN                 _SB_MAKEVALUE(x,S_SYS_BIN)
 #define G_SYS_BIN                 _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
- 
+
 /* Wafer ID: bits 39:36 */
 #define S_SYS_WAFERID2_200        _SB_MAKE64(36)
 #define M_SYS_WAFERID2_200        _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
 #define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
 #define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
- 
+
 /* Wafer ID: bits 39:0 */
 #define S_SYS_WAFERID_300         _SB_MAKE64(0)
 #define M_SYS_WAFERID_300         _SB_MAKEMASK(40,S_SYS_WAFERID_300)
 #define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
 #define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
- 
+
 #define S_SYS_XPOS                _SB_MAKE64(40)
 #define M_SYS_XPOS                _SB_MAKEMASK(6,S_SYS_XPOS)
 #define V_SYS_XPOS(x)             _SB_MAKEVALUE(x,S_SYS_XPOS)
 #define G_SYS_XPOS(x)             _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
- 
+
 #define S_SYS_YPOS                _SB_MAKE64(46)
 #define M_SYS_YPOS                _SB_MAKEMASK(6,S_SYS_YPOS)
 #define V_SYS_YPOS(x)             _SB_MAKEVALUE(x,S_SYS_YPOS)
 #define G_SYS_YPOS(x)             _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
- 
+
 /*
  * System Config Register (Table 4-2)
  * Register: SCD_SYSTEM_CFG
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 287cbfe9efa2..335c53e92936 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  SMBUS Constants                          File: sb1250_smbus.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's SMbus devices.
-    *  
+    *
     *  SB1250 specification level:  01/02/2002
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index 8d5e8edd3c4b..fa2760d38b8b 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -7,17 +7,17 @@
     *  manipulating the SB1250's Synchronous Serial
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
     *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 7655d6945cca..923ea4f44e0f 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  UART Constants                           File: sb1250_uart.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's UARTs
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -37,7 +37,7 @@
 
 #include "sb1250_defs.h"
 
-/* ********************************************************************** 
+/* **********************************************************************
    * DUART Registers
    ********************************************************************** */
 
@@ -145,7 +145,7 @@
 #define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
 #define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
 
-#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7) 
+#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
 
 /*
  * DUART Status Register (Table 10-6)
@@ -165,7 +165,7 @@
 
 /*
  * DUART Baud Rate Register (Table 10-7)
- * Register: DUART_CLK_SEL_A 
+ * Register: DUART_CLK_SEL_A
  * Register: DUART_CLK_SEL_B
  */
 
@@ -332,7 +332,7 @@
     (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-/* 
+/*
  * Full Interrupt Control Register
  */
 
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index 18939e84b6f2..f7fbebaa0744 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -10,7 +10,7 @@
 #define _ASM_SIGCONTEXT_H
 
 #include <asm/sgidefs.h>
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
@@ -38,7 +38,7 @@ struct sigcontext {
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
 /*
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index a0e26e6c994d..698becab5a9e 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -25,10 +25,10 @@ struct siginfo;
 /*
  * Careful to keep union _sifields from shifting ...
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
 #endif
 
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 6333169be329..3ccfe09fa744 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -16,7 +16,7 @@
 #define __str2(x) #x
 #define __str(x) __str2(x)
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define save_static_function(symbol)                                    \
 __asm__ (                                                               \
@@ -42,9 +42,9 @@ __asm__ (								\
 
 #define nabi_no_regargs
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define save_static_function(symbol)                                    \
 __asm__ (                                                               \
@@ -78,6 +78,6 @@ __asm__ (								\
         unsigned long __dummy6,                                         \
         unsigned long __dummy7,
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* _ASM_SIM_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 8ba370ecfd4c..5618f1e12f40 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -21,7 +21,7 @@
 #include <linux/cpumask.h>
 #include <asm/atomic.h>
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
 
 /* Map from cpu id to sequential logical cpu number.  This will only
    not be idempotent when cpus failed to come on-line.  */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index 020b4db70ee5..753b6620e6fa 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -37,6 +37,8 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SO_ERROR        0x1007  /* get error status and clear */
 #define SO_SNDBUF       0x1001  /* Send buffer size. */
 #define SO_RCVBUF       0x1002  /* Receive buffer. */
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
 #define SO_SNDLOWAT     0x1003  /* send low-water mark */
 #define SO_RCVLOWAT     0x1004  /* receive low-water mark */
 #define SO_SNDTIMEO     0x1005  /* send timeout */
@@ -80,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
  * @SOCK_STREAM - stream (connection) socket
  * @SOCK_RAW - raw socket
  * @SOCK_RDM - reliably-delivered message
- * @SOCK_SEQPACKET - sequential packet socket 
+ * @SOCK_SEQPACKET - sequential packet socket
  * @SOCK_PACKET - linux specific way of getting packets at the dev level.
  *                For writing rarp and other similar things on the user level.
  */
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 86283c25fd5b..fb42f99f8527 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -26,7 +26,7 @@
 
                 .macro  SAVE_TEMP
                 mfhi    v1
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
@@ -56,7 +56,7 @@
 
 #ifdef CONFIG_SMP
                 .macro  get_saved_sp    /* SMP variation */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 mfc0    k0, CP0_CONTEXT
                 lui     k1, %hi(kernelsp)
                 srl     k0, k0, 23
@@ -64,7 +64,7 @@
                 addu    k1, k0
                 LONG_L  k1, %lo(kernelsp)(k1)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                 MFC0    k1, CP0_CONTEXT
                 dsra    k1, 23
                 lui     k0, %hi(pgd_current)
@@ -74,7 +74,7 @@
                 daddu   k1, k0
                 LONG_L  k1, %lo(kernelsp)(k1)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                 MFC0    k1, CP0_CONTEXT
                 dsrl    k1, 23
                 dsll    k1, k1, 3
@@ -83,20 +83,20 @@
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 mfc0    \temp, CP0_CONTEXT
                 srl     \temp, 23
                 sll     \temp, 2
                 LONG_S  \stackp, kernelsp(\temp)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                 lw      \temp, TI_CPU(gp)
                 dsll    \temp, 3
                 lui     \temp2, %hi(kernelsp)
                 daddu   \temp, \temp2
                 LONG_S  \stackp, %lo(kernelsp)(\temp)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                 lw      \temp, TI_CPU(gp)
                 dsll    \temp, 3
                 LONG_S  \stackp, kernelsp(\temp)
@@ -140,7 +140,7 @@
                 LONG_S  $6, PT_R6(sp)
                 MFC0    v1, CP0_EPC
                 LONG_S  $7, PT_R7(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
@@ -169,7 +169,7 @@
 
                 .macro  RESTORE_TEMP
                 LONG_L  $24, PT_LO(sp)
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
@@ -217,7 +217,7 @@
                 LONG_L  $31, PT_R31(sp)
                 LONG_L  $28, PT_R28(sp)
                 LONG_L  $25, PT_R25(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
@@ -262,7 +262,7 @@
                 LONG_L  $31, PT_R31(sp)
                 LONG_L  $28, PT_R28(sp)
                 LONG_L  $25, PT_R25(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
index 5076fec65780..c3ddf973c1c0 100644
--- a/include/asm-mips/statfs.h
+++ b/include/asm-mips/statfs.h
@@ -57,7 +57,7 @@ struct statfs64 {
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
- 
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
 struct statfs64 {                       /* Same as struct statfs */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
index b18345504f8a..5a06f6d13899 100644
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@@ -16,7 +16,7 @@
  * Most of the inline functions are rather naive implementations so I just
  * didn't bother updating them for 64-bit ...
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #ifndef IN_STRING_C
 
@@ -130,7 +130,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
 
         return __res;
 }
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
 #define __HAVE_ARCH_MEMSET
 extern void *memset(void *__s, int __c, size_t __count);
@@ -141,7 +141,7 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
 #define __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __HAVE_ARCH_MEMSCAN
 static __inline__ void *memscan(void *__addr, int __c, size_t __size)
 {
@@ -161,6 +161,6 @@ static __inline__ void *memscan(void *__addr, int __c, size_t __size)
 
         return __addr;
 }
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
 #endif /* _ASM_STRING_H */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 888fd8908467..6663efd49b27 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -208,7 +208,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
         return retval;
 }
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 {
         __u64 retval;
@@ -330,7 +330,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
         return retval;
 }
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
         unsigned long new)
 {
@@ -422,16 +422,10 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
 extern int stop_a_enabled;
 
 /*
- * Taken from include/asm-ia64/system.h; prevents deadlock on SMP
+ * See include/asm-ia64/system.h; prevents deadlock on SMP
  * systems.
  */
-#define prepare_arch_switch(rq, next)           \
-do {                                            \
-        spin_lock(&(next)->switch_lock);        \
-        spin_unlock(&(rq)->lock);               \
-} while (0)
-#define finish_arch_switch(rq, prev)    spin_unlock_irq(&(prev)->switch_lock)
-#define task_running(rq, p)             ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
+#define __ARCH_WANT_UNLOCKED_CTXSW
 
 #define arch_align_stack(x) (x)
 
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index 768900305e2f..a70cb0854c8a 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -27,7 +27,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
         mm_segment_t            addr_limit;     /* thread address space:
                                                    0-0xBFFFFFFF for user-thead
@@ -62,10 +62,10 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define current_thread_info()  __current_thread_info
 
 /* thread information allocation */
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32)
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
 #define THREAD_SIZE_ORDER (1)
 #endif
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64)
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
 #define THREAD_SIZE_ORDER (2)
 #endif
 #ifdef CONFIG_PAGE_SIZE_8KB
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
index fd9599e40a0a..fee1908c65d2 100644
--- a/include/asm-mips/titan_dep.h
+++ b/include/asm-mips/titan_dep.h
@@ -228,4 +228,4 @@ extern unsigned long ocd_base;
 #define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
 #define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
 
-#endif 
+#endif
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 5d939db6e220..3bb7f0087d68 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -45,14 +45,14 @@
 
 
 /* TX4927 SDRAM controller (64-bit registers) */
-#define TX4927_SDRAMC_BASE              0x8000 
-#define TX4927_SDRAMC_SDCCR0            0x8000 
+#define TX4927_SDRAMC_BASE              0x8000
+#define TX4927_SDRAMC_SDCCR0            0x8000
 #define TX4927_SDRAMC_SDCCR1            0x8008
 #define TX4927_SDRAMC_SDCCR2            0x8010
 #define TX4927_SDRAMC_SDCCR3            0x8018
 #define TX4927_SDRAMC_SDCTR             0x8040
 #define TX4927_SDRAMC_SDCMD             0x8058
-#define TX4927_SDRAMC_LIMIT             0x8fff 
+#define TX4927_SDRAMC_LIMIT             0x8fff
 
 
 /* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
 
 
 /* TX4927 serial port 0 (32-bit registers) */
-#define TX4927_SIO0_BASE                         0xf300 
-#define TX4927_SIO0_SILCR0                       0xf300 
+#define TX4927_SIO0_BASE                         0xf300
+#define TX4927_SIO0_SILCR0                       0xf300
 #define TX4927_SIO0_SILCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SILCR0_RWUB                          BM_15_15
 #define TX4927_SIO0_SILCR0_TWUB                          BM_14_14
@@ -309,7 +309,7 @@
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)
 #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC           BM_01_01
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC           BM_00_01
-#define TX4927_SIO0_SIDICR0                      0xf304 
+#define TX4927_SIO0_SIDICR0                      0xf304
 #define TX4927_SIO0_SIDICR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDICR0_TDE                          BM_15_15
 #define TX4927_SIO0_SIDICR0_RDE                          BM_14_14
@@ -330,7 +330,7 @@
 #define TX4927_SIO0_SIDICR0_STIE_TRDY                    BM_02_02
 #define TX4927_SIO0_SIDICR0_STIE_TXALS                   BM_01_01
 #define TX4927_SIO0_SIDICR0_STIE_UBRKD                   BM_00_00
-#define TX4927_SIO0_SIDISR0                      0xf308 
+#define TX4927_SIO0_SIDISR0                      0xf308
 #define TX4927_SIO0_SIDISR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDISR0_UBRK                         BM_15_15
 #define TX4927_SIO0_SIDISR0_UVALID                       BM_14_14
@@ -344,7 +344,7 @@
 #define TX4927_SIO0_SIDISR0_STIS                         BM_06_06
 #define TX4927_SIO0_SIDISR0_RESERVED_05_05               BM_05_05
 #define TX4927_SIO0_SIDISR0_RFDN                         BM_00_04
-#define TX4927_SIO0_SISCISR0                     0xf30c 
+#define TX4927_SIO0_SISCISR0                     0xf30c
 #define TX4927_SIO0_SISCISR0_RESERVED_06_31              BM_06_31
 #define TX4927_SIO0_SISCISR0_OERS                        BM_05_05
 #define TX4927_SIO0_SISCISR0_CTSS                        BM_04_04
@@ -352,7 +352,7 @@
 #define TX4927_SIO0_SISCISR0_TRDY                        BM_02_02
 #define TX4927_SIO0_SISCISR0_TXALS                       BM_01_01
 #define TX4927_SIO0_SISCISR0_UBRKD                       BM_00_00
-#define TX4927_SIO0_SIFCR0                       0xf310 
+#define TX4927_SIO0_SIFCR0                       0xf310
 #define TX4927_SIO0_SIFCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SIFCR0_SWRST                         BM_16_31
 #define TX4927_SIO0_SIFCR0_RESERVED_09_14                BM_09_14
@@ -370,7 +370,7 @@
 #define TX4927_SIO0_SIFCR0_TFRST                         BM_02_02
 #define TX4927_SIO0_SIFCR0_RFRST                         BM_01_01
 #define TX4927_SIO0_SIFCR0_FRSTE                         BM_00_00
-#define TX4927_SIO0_SIFLCR0                      0xf314 
+#define TX4927_SIO0_SIFLCR0                      0xf314
 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31               BM_13_31
 #define TX4927_SIO0_SIFLCR0_RCS                          BM_12_12
 #define TX4927_SIO0_SIFLCR0_TES                          BM_11_11
@@ -381,7 +381,7 @@
 #define TX4927_SIO0_SIFLCR0_RESERVED_05_06               BM_05_06
 #define TX4927_SIO0_SIFLCR0_RTSTL                        BM_01_04
 #define TX4927_SIO0_SIFLCR0_TBRK                         BM_00_00
-#define TX4927_SIO0_SIBGR0                       0xf318 
+#define TX4927_SIO0_SIBGR0                       0xf318
 #define TX4927_SIO0_SIBGR0_RESERVED_10_31                BM_10_31
 #define TX4927_SIO0_SIBGR0_BCLK                          BM_08_09
 #define TX4927_SIO0_SIBGR0_BCLK_T0                     (~BM_08_09)
@@ -389,28 +389,28 @@
 #define TX4927_SIO0_SIBGR0_BCLK_T4                       BM_09_09
 #define TX4927_SIO0_SIBGR0_BCLK_T6                       BM_08_09
 #define TX4927_SIO0_SIBGR0_BRD                           BM_00_07
-#define TX4927_SIO0_SITFIF00                     0xf31c 
+#define TX4927_SIO0_SITFIF00                     0xf31c
 #define TX4927_SIO0_SITFIF00_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SITFIF00_TXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_SIRFIFO0                     0xf320
 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SIRFIFO0_RXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
-#define TX4927_SIO0_LIMIT                        0xf3ff 
+#define TX4927_SIO0_SIRFIFO0                     0xf320
+#define TX4927_SIO0_LIMIT                        0xf3ff
 
 
 /* TX4927 serial port 1 (32-bit registers) */
-#define TX4927_SIO1_BASE                0xf400 
-#define TX4927_SIO1_SILCR1              0xf400 
-#define TX4927_SIO1_SIDICR1             0xf404 
-#define TX4927_SIO1_SIDISR1             0xf408 
-#define TX4927_SIO1_SISCISR1            0xf40c 
-#define TX4927_SIO1_SIFCR1              0xf410 
-#define TX4927_SIO1_SIFLCR1             0xf414 
-#define TX4927_SIO1_SIBGR1              0xf418 
-#define TX4927_SIO1_SITFIF01            0xf41c 
-#define TX4927_SIO1_SIRFIFO1            0xf420 
-#define TX4927_SIO1_LIMIT               0xf4ff 
+#define TX4927_SIO1_BASE                0xf400
+#define TX4927_SIO1_SILCR1              0xf400
+#define TX4927_SIO1_SIDICR1             0xf404
+#define TX4927_SIO1_SIDISR1             0xf408
+#define TX4927_SIO1_SISCISR1            0xf40c
+#define TX4927_SIO1_SIFCR1              0xf410
+#define TX4927_SIO1_SIFLCR1             0xf414
+#define TX4927_SIO1_SIBGR1              0xf418
+#define TX4927_SIO1_SITFIF01            0xf41c
+#define TX4927_SIO1_SIRFIFO1            0xf420
+#define TX4927_SIO1_LIMIT               0xf4ff
 
 
 /* TX4927 parallel port (32-bit registers) */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 170433492246..165f6b8b217f 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -5,8 +5,8 @@
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
  */
-#ifndef __ASM_TX4927_TX4927_PCI_H 
-#define __ASM_TX4927_TX4927_PCI_H 
+#ifndef __ASM_TX4927_TX4927_PCI_H
+#define __ASM_TX4927_TX4927_PCI_H
 
 #define TX4927_CCFG_TOE 0x00004000
 
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
index d2f0c76b00a9..421b3aea14cc 100644
--- a/include/asm-mips/types.h
+++ b/include/asm-mips/types.h
@@ -78,7 +78,7 @@ typedef unsigned long long u64;
 #endif
 
 #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_MIPS64)
+    || defined(CONFIG_64BIT)
 typedef u64 dma_addr_t;
 #else
 typedef u32 dma_addr_t;
@@ -99,8 +99,6 @@ typedef u64 sector_t;
 #define HAVE_SECTOR_T
 #endif
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 07114898e065..5c2c98329012 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -22,7 +22,7 @@
  *
  * For historical reasons, these macros are grossly misnamed.
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define __UA_LIMIT      0x80000000UL
 
@@ -32,9 +32,9 @@
 #define __UA_t0         "$8"
 #define __UA_t1         "$9"
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define __UA_LIMIT      (- TASK_SIZE)
 
@@ -44,7 +44,7 @@
 #define __UA_t0         "$12"
 #define __UA_t1         "$13"
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * USER_DS is a bitmask that has the bits set that may not be set in a valid
@@ -112,29 +112,6 @@
         likely(__access_ok((unsigned long)(addr), (size),__access_mask))
 
 /*
- * verify_area: - Obsolete/deprecated and will go away soon,
- * use access_ok() instead.
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * This function has been replaced by access_ok().
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns zero if the memory block may be valid, -EFAULT
- * if it is definitely invalid.
- *
- * See access_ok() for more details.
- */
-static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
-/*
  * put_user: - Write a simple value into user space.
  * @x:   Value to copy to user space.
  * @ptr: Destination address, in user space.
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 6d21cc964f76..ad4d48056307 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -1124,7 +1124,7 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
 # ifndef __mips64
 #  define __ARCH_WANT_STAT64
 # endif
-# ifdef CONFIG_MIPS32
+# ifdef CONFIG_32BIT
 #  define __ARCH_WANT_SYS_TIME
 # endif
 # ifdef CONFIG_MIPS32_O32
diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h
deleted file mode 100644
index 4bf0ea970ed0..000000000000
--- a/include/asm-mips/vr4181/irq.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Macros for vr4181 IRQ numbers.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-/*
- * Strategy:
- *
- * Vr4181 has conceptually three levels of interrupt controllers:
- *  1. the CPU itself with 8 intr level.
- *  2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
- *  3. GPIO interrupts : forwarding external interrupts to sys intr controller
- */
-
-/* decide the irq block assignment */
-#define VR4181_NUM_CPU_IRQ      8
-#define VR4181_NUM_SYS_IRQ      32
-#define VR4181_NUM_GPIO_IRQ     16
-
-#define VR4181_IRQ_BASE         0
-
-#define VR4181_CPU_IRQ_BASE     VR4181_IRQ_BASE
-#define VR4181_SYS_IRQ_BASE     (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
-#define VR4181_GPIO_IRQ_BASE    (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
-
-/* CPU interrupts */
-
-/*
-   IP0 - Software interrupt
-   IP1 - Software interrupt
-   IP2 - All but battery, high speed modem, and real time clock
-   IP3 - RTC Long1 (system timer)
-   IP4 - RTC Long2
-   IP5 - High Speed Modem (unused on VR4181)
-   IP6 - Unused
-   IP7 - Timer interrupt from CPO_COMPARE
-*/
-
-#define VR4181_IRQ_SW1       (VR4181_CPU_IRQ_BASE + 0)
-#define VR4181_IRQ_SW2       (VR4181_CPU_IRQ_BASE + 1)
-#define VR4181_IRQ_INT0      (VR4181_CPU_IRQ_BASE + 2)
-#define VR4181_IRQ_INT1      (VR4181_CPU_IRQ_BASE + 3)
-#define VR4181_IRQ_INT2      (VR4181_CPU_IRQ_BASE + 4)
-#define VR4181_IRQ_INT3      (VR4181_CPU_IRQ_BASE + 5)
-#define VR4181_IRQ_INT4      (VR4181_CPU_IRQ_BASE + 6)
-#define VR4181_IRQ_TIMER     (VR4181_CPU_IRQ_BASE + 7)
-
-
-/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
-
-/*
-   IP2 - same as VR4181_IRQ_INT1
-   IP8 - This is a cascade to GPIO IRQ's. Do not use.
-   IP16 - same as VR4181_IRQ_INT2
-   IP18 - CompactFlash
-*/
-
-#define VR4181_IRQ_BATTERY   (VR4181_SYS_IRQ_BASE + 0)
-#define VR4181_IRQ_POWER     (VR4181_SYS_IRQ_BASE + 1)
-#define VR4181_IRQ_RTCL1     (VR4181_SYS_IRQ_BASE + 2)
-#define VR4181_IRQ_ETIMER    (VR4181_SYS_IRQ_BASE + 3)
-#define VR4181_IRQ_RFU12     (VR4181_SYS_IRQ_BASE + 4)
-#define VR4181_IRQ_PIU       (VR4181_SYS_IRQ_BASE + 5)
-#define VR4181_IRQ_AIU       (VR4181_SYS_IRQ_BASE + 6)
-#define VR4181_IRQ_KIU       (VR4181_SYS_IRQ_BASE + 7)
-#define VR4181_IRQ_GIU       (VR4181_SYS_IRQ_BASE + 8)
-#define VR4181_IRQ_SIU       (VR4181_SYS_IRQ_BASE + 9)
-#define VR4181_IRQ_RFU18     (VR4181_SYS_IRQ_BASE + 10)
-#define VR4181_IRQ_SOFT      (VR4181_SYS_IRQ_BASE + 11)
-#define VR4181_IRQ_RFU20     (VR4181_SYS_IRQ_BASE + 12)
-#define VR4181_IRQ_DOZEPIU   (VR4181_SYS_IRQ_BASE + 13)
-#define VR4181_IRQ_RFU22     (VR4181_SYS_IRQ_BASE + 14)
-#define VR4181_IRQ_RFU23     (VR4181_SYS_IRQ_BASE + 15)
-#define VR4181_IRQ_RTCL2     (VR4181_SYS_IRQ_BASE + 16)
-#define VR4181_IRQ_LED       (VR4181_SYS_IRQ_BASE + 17)
-#define VR4181_IRQ_ECU       (VR4181_SYS_IRQ_BASE + 18)
-#define VR4181_IRQ_CSU       (VR4181_SYS_IRQ_BASE + 19)
-#define VR4181_IRQ_USB       (VR4181_SYS_IRQ_BASE + 20)
-#define VR4181_IRQ_DMA       (VR4181_SYS_IRQ_BASE + 21)
-#define VR4181_IRQ_LCD       (VR4181_SYS_IRQ_BASE + 22)
-#define VR4181_IRQ_RFU31     (VR4181_SYS_IRQ_BASE + 23)
-#define VR4181_IRQ_RFU32     (VR4181_SYS_IRQ_BASE + 24)
-#define VR4181_IRQ_RFU33     (VR4181_SYS_IRQ_BASE + 25)
-#define VR4181_IRQ_RFU34     (VR4181_SYS_IRQ_BASE + 26)
-#define VR4181_IRQ_RFU35     (VR4181_SYS_IRQ_BASE + 27)
-#define VR4181_IRQ_RFU36     (VR4181_SYS_IRQ_BASE + 28)
-#define VR4181_IRQ_RFU37     (VR4181_SYS_IRQ_BASE + 29)
-#define VR4181_IRQ_RFU38     (VR4181_SYS_IRQ_BASE + 30)
-#define VR4181_IRQ_RFU39     (VR4181_SYS_IRQ_BASE + 31)
-
-/* Cascaded from VR4181_IRQ_GIU */
-#define VR4181_IRQ_GPIO0     (VR4181_GPIO_IRQ_BASE + 0)
-#define VR4181_IRQ_GPIO1     (VR4181_GPIO_IRQ_BASE + 1)
-#define VR4181_IRQ_GPIO2     (VR4181_GPIO_IRQ_BASE + 2)
-#define VR4181_IRQ_GPIO3     (VR4181_GPIO_IRQ_BASE + 3)
-#define VR4181_IRQ_GPIO4     (VR4181_GPIO_IRQ_BASE + 4)
-#define VR4181_IRQ_GPIO5     (VR4181_GPIO_IRQ_BASE + 5)
-#define VR4181_IRQ_GPIO6     (VR4181_GPIO_IRQ_BASE + 6)
-#define VR4181_IRQ_GPIO7     (VR4181_GPIO_IRQ_BASE + 7)
-#define VR4181_IRQ_GPIO8     (VR4181_GPIO_IRQ_BASE + 8)
-#define VR4181_IRQ_GPIO9     (VR4181_GPIO_IRQ_BASE + 9)
-#define VR4181_IRQ_GPIO10    (VR4181_GPIO_IRQ_BASE + 10)
-#define VR4181_IRQ_GPIO11    (VR4181_GPIO_IRQ_BASE + 11)
-#define VR4181_IRQ_GPIO12    (VR4181_GPIO_IRQ_BASE + 12)
-#define VR4181_IRQ_GPIO13    (VR4181_GPIO_IRQ_BASE + 13)
-#define VR4181_IRQ_GPIO14    (VR4181_GPIO_IRQ_BASE + 14)
-#define VR4181_IRQ_GPIO15    (VR4181_GPIO_IRQ_BASE + 15)
-
-
-// Alternative to above GPIO IRQ defines
-#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
-
-#define VR4181_IRQ_MAX       (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
-                              VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h
deleted file mode 100644
index 5c5d60741515..000000000000
--- a/include/asm-mips/vr4181/vr4181.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 by Michael Klar
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- */
-#ifndef __ASM_VR4181_VR4181_H
-#define __ASM_VR4181_VR4181_H
-
-#include <asm/addrspace.h>
-
-#include <asm/vr4181/irq.h>
-
-#ifndef __ASSEMBLY__
-#define __preg8         (volatile unsigned char*)
-#define __preg16        (volatile unsigned short*)
-#define __preg32        (volatile unsigned int*)
-#else
-#define __preg8
-#define __preg16
-#define __preg32
-#endif
-
-// Embedded CPU peripheral registers
-// Note that many of the registers have different physical address for VR4181
-
-// Bus Control Unit (BCU)
-#define VR4181_BCUCNTREG1       __preg16(KSEG1 + 0x0A000000)    /* BCU control register 1 (R/W) */
-#define VR4181_CMUCLKMSK        __preg16(KSEG1 + 0x0A000004)    /* Clock mask register (R/W) */
-#define VR4181_CMUCLKMSK_MSKCSUPCLK  0x0040
-#define VR4181_CMUCLKMSK_MSKAIUPCLK  0x0020
-#define VR4181_CMUCLKMSK_MSKPIUPCLK  0x0010
-#define VR4181_CMUCLKMSK_MSKADUPCLK  0x0008
-#define VR4181_CMUCLKMSK_MSKSIU18M   0x0004
-#define VR4181_CMUCLKMSK_MSKADU18M   0x0002
-#define VR4181_CMUCLKMSK_MSKUSB      0x0001
-#define VR4181_CMUCLKMSK_MSKSIU      VR4181_CMUCLKMSK_MSKSIU18M
-#define VR4181_BCUSPEEDREG      __preg16(KSEG1 + 0x0A00000C)    /* BCU access time parameter (R/W) */
-#define VR4181_BCURFCNTREG      __preg16(KSEG1 + 0x0A000010)    /* BCU refresh control register (R/W) */
-#define VR4181_REVIDREG         __preg16(KSEG1 + 0x0A000014)    /* Revision ID register (R) */
-#define VR4181_CLKSPEEDREG      __preg16(KSEG1 + 0x0A000018)    /* Clock speed register (R) */
-#define VR4181_EDOMCYTREG       __preg16(KSEG1 + 0x0A000300)    /* Memory cycle timing register (R/W) */
-#define VR4181_MEMCFG_REG       __preg16(KSEG1 + 0x0A000304)    /* Memory configuration register (R/W) */
-#define VR4181_MODE_REG         __preg16(KSEG1 + 0x0A000308)    /* SDRAM mode register (R/W) */
-#define VR4181_SDTIMINGREG      __preg16(KSEG1 + 0x0A00030C)    /* SDRAM timing register (R/W) */
-
-// DMA Control Unit (DCU)
-#define VR4181_MICDEST1REG1     __preg16(KSEG1 + 0x0A000020)    /* Microphone destination 1 address register 1 (R/W) */
-#define VR4181_MICDEST1REG2     __preg16(KSEG1 + 0x0A000022)    /* Microphone destination 1 address register 2 (R/W) */
-#define VR4181_MICDEST2REG1     __preg16(KSEG1 + 0x0A000024)    /* Microphone destination 2 address register 1 (R/W) */
-#define VR4181_MICDEST2REG2     __preg16(KSEG1 + 0x0A000026)    /* Microphone destination 2 address register 2 (R/W) */
-#define VR4181_SPKRRC1REG1      __preg16(KSEG1 + 0x0A000028)    /* Speaker Source 1 address register 1 (R/W) */
-#define VR4181_SPKRRC1REG2      __preg16(KSEG1 + 0x0A00002A)    /* Speaker Source 1 address register 2 (R/W) */
-#define VR4181_SPKRRC2REG1      __preg16(KSEG1 + 0x0A00002C)    /* Speaker Source 2 address register 1 (R/W) */
-#define VR4181_SPKRRC2REG2      __preg16(KSEG1 + 0x0A00002E)    /* Speaker Source 2 address register 2 (R/W) */
-#define VR4181_DMARSTREG        __preg16(KSEG1 + 0x0A000040)    /* DMA Reset register (R/W) */
-#define VR4181_AIUDMAMSKREG     __preg16(KSEG1 + 0x0A000046)    /* Audio DMA mask register (R/W) */
-#define VR4181_USBDMAMSKREG     __preg16(KSEG1 + 0x0A000600)    /* USB DMA Mask register (R/W) */
-#define VR4181_USBRXS1AREG1     __preg16(KSEG1 + 0x0A000602)    /* USB Rx source 1 address register 1 (R/W) */
-#define VR4181_USBRXS1AREG2     __preg16(KSEG1 + 0x0A000604)    /* USB Rx source 1 address register 2 (R/W) */
-#define VR4181_USBRXS2AREG1     __preg16(KSEG1 + 0x0A000606)    /* USB Rx source 2 address register 1 (R/W) */
-#define VR4181_USBRXS2AREG2     __preg16(KSEG1 + 0x0A000608)    /* USB Rx source 2 address register 2 (R/W) */
-#define VR4181_USBTXS1AREG1     __preg16(KSEG1 + 0x0A00060A)    /* USB Tx source 1 address register 1 (R/W) */
-#define VR4181_USBTXS1AREG2     __preg16(KSEG1 + 0x0A00060C)    /* USB Tx source 1 address register 2 (R/W) */
-#define VR4181_USBTXS2AREG1     __preg16(KSEG1 + 0x0A00060E)    /* USB Tx source 2 address register 1 (R/W) */
-#define VR4181_USBTXS2AREG2     __preg16(KSEG1 + 0x0A000610)    /* USB Tx source 2 address register 2 (R/W) */
-#define VR4181_USBRXD1AREG1     __preg16(KSEG1 + 0x0A00062A)    /* USB Rx destination 1 address register 1 (R/W) */
-#define VR4181_USBRXD1AREG2     __preg16(KSEG1 + 0x0A00062C)    /* USB Rx destination 1 address register 2 (R/W) */
-#define VR4181_USBRXD2AREG1     __preg16(KSEG1 + 0x0A00062E)    /* USB Rx destination 2 address register 1 (R/W) */
-#define VR4181_USBRXD2AREG2     __preg16(KSEG1 + 0x0A000630)    /* USB Rx destination 2 address register 2 (R/W) */
-#define VR4181_USBTXD1AREG1     __preg16(KSEG1 + 0x0A000632)    /* USB Tx destination 1 address register 1 (R/W) */
-#define VR4181_USBTXD1AREG2     __preg16(KSEG1 + 0x0A000634)    /* USB Tx destination 1 address register 2 (R/W) */
-#define VR4181_USBTXD2AREG1     __preg16(KSEG1 + 0x0A000636)    /* USB Tx destination 2 address register 1 (R/W) */
-#define VR4181_USBTXD2AREG2     __preg16(KSEG1 + 0x0A000638)    /* USB Tx destination 2 address register 2 (R/W) */
-#define VR4181_RxRCLENREG       __preg16(KSEG1 + 0x0A000652)    /* USB Rx record length register (R/W) */
-#define VR4181_TxRCLENREG       __preg16(KSEG1 + 0x0A000654)    /* USB Tx record length register (R/W) */
-#define VR4181_MICRCLENREG      __preg16(KSEG1 + 0x0A000658)    /* Microphone record length register (R/W) */
-#define VR4181_SPKRCLENREG      __preg16(KSEG1 + 0x0A00065A)    /* Speaker record length register (R/W) */
-#define VR4181_USBCFGREG        __preg16(KSEG1 + 0x0A00065C)    /* USB configuration register (R/W) */
-#define VR4181_MICDMACFGREG     __preg16(KSEG1 + 0x0A00065E)    /* Microphone DMA configuration register (R/W) */
-#define VR4181_SPKDMACFGREG     __preg16(KSEG1 + 0x0A000660)    /* Speaker DMA configuration register (R/W) */
-#define VR4181_DMAITRQREG       __preg16(KSEG1 + 0x0A000662)    /* DMA interrupt request register (R/W) */
-#define VR4181_DMACLTREG        __preg16(KSEG1 + 0x0A000664)    /* DMA control register (R/W) */
-#define VR4181_DMAITMKREG       __preg16(KSEG1 + 0x0A000666)    /* DMA interrupt mask register (R/W) */
-
-// ISA Bridge
-#define VR4181_ISABRGCTL        __preg16(KSEG1 + 0x0B0002C0)    /* ISA Bridge Control Register (R/W) */
-#define VR4181_ISABRGSTS        __preg16(KSEG1 + 0x0B0002C2)    /* ISA Bridge Status Register (R/W) */
-#define VR4181_XISACTL          __preg16(KSEG1 + 0x0B0002C4)    /* External ISA Control Register (R/W) */
-
-// Clocked Serial Interface (CSI)
-#define VR4181_CSIMODE          __preg16(KSEG1 + 0x0B000900)    /* CSI Mode Register (R/W) */
-#define VR4181_CSIRXDATA        __preg16(KSEG1 + 0x0B000902)    /* CSI Receive Data Register (R) */
-#define VR4181_CSITXDATA        __preg16(KSEG1 + 0x0B000904)    /* CSI Transmit Data Register (R/W) */
-#define VR4181_CSILSTAT         __preg16(KSEG1 + 0x0B000906)    /* CSI Line Status Register (R/W) */
-#define VR4181_CSIINTMSK        __preg16(KSEG1 + 0x0B000908)    /* CSI Interrupt Mask Register (R/W) */
-#define VR4181_CSIINTSTAT       __preg16(KSEG1 + 0x0B00090a)    /* CSI Interrupt Status Register (R/W) */
-#define VR4181_CSITXBLEN        __preg16(KSEG1 + 0x0B00090c)    /* CSI Transmit Burst Length Register (R/W) */
-#define VR4181_CSIRXBLEN        __preg16(KSEG1 + 0x0B00090e)    /* CSI Receive Burst Length Register (R/W) */
-
-// Interrupt Control Unit (ICU)
-#define VR4181_SYSINT1REG       __preg16(KSEG1 + 0x0A000080)    /* Level 1 System interrupt register 1 (R) */
-#define VR4181_MSYSINT1REG      __preg16(KSEG1 + 0x0A00008C)    /* Level 1 mask system interrupt register 1 (R/W) */
-#define VR4181_NMIREG           __preg16(KSEG1 + 0x0A000098)    /* NMI register (R/W) */
-#define VR4181_SOFTINTREG       __preg16(KSEG1 + 0x0A00009A)    /* Software interrupt register (R/W) */
-#define VR4181_SYSINT2REG       __preg16(KSEG1 + 0x0A000200)    /* Level 1 System interrupt register 2 (R) */
-#define VR4181_MSYSINT2REG      __preg16(KSEG1 + 0x0A000206)    /* Level 1 mask system interrupt register 2 (R/W) */
-#define VR4181_PIUINTREGro      __preg16(KSEG1 + 0x0B000082)    /* Level 2 PIU interrupt register (R) */
-#define VR4181_AIUINTREG        __preg16(KSEG1 + 0x0B000084)    /* Level 2 AIU interrupt register (R) */
-#define VR4181_MPIUINTREG       __preg16(KSEG1 + 0x0B00008E)    /* Level 2 mask PIU interrupt register (R/W) */
-#define VR4181_MAIUINTREG       __preg16(KSEG1 + 0x0B000090)    /* Level 2 mask AIU interrupt register (R/W) */
-#define VR4181_MKIUINTREG       __preg16(KSEG1 + 0x0B000092)    /* Level 2 mask KIU interrupt register (R/W) */
-#define VR4181_KIUINTREG        __preg16(KSEG1 + 0x0B000198)    /* Level 2 KIU interrupt register (R) */
-
-// Power Management Unit (PMU)
-#define VR4181_PMUINTREG        __preg16(KSEG1 + 0x0B0000A0)    /* PMU Status Register (R/W) */
-#define VR4181_PMUINT_POWERSW  0x1      /* Power switch */
-#define VR4181_PMUINT_BATT     0x2      /* Low batt during normal operation */
-#define VR4181_PMUINT_DEADMAN  0x4      /* Deadman's switch */
-#define VR4181_PMUINT_RESET    0x8      /* Reset switch */
-#define VR4181_PMUINT_RTCRESET 0x10     /* RTC Reset */
-#define VR4181_PMUINT_TIMEOUT  0x20     /* HAL Timer Reset */
-#define VR4181_PMUINT_BATTLOW  0x100    /* Battery low */
-#define VR4181_PMUINT_RTC      0x200    /* RTC Alarm */
-#define VR4181_PMUINT_DCD      0x400    /* DCD# */
-#define VR4181_PMUINT_GPIO0    0x1000   /* GPIO0 */
-#define VR4181_PMUINT_GPIO1    0x2000   /* GPIO1 */
-#define VR4181_PMUINT_GPIO2    0x4000   /* GPIO2 */
-#define VR4181_PMUINT_GPIO3    0x8000   /* GPIO3 */
-
-#define VR4181_PMUCNTREG        __preg16(KSEG1 + 0x0B0000A2)    /* PMU Control Register (R/W) */
-#define VR4181_PMUWAITREG       __preg16(KSEG1 + 0x0B0000A8)    /* PMU Wait Counter Register (R/W) */
-#define VR4181_PMUDIVREG        __preg16(KSEG1 + 0x0B0000AC)    /* PMU Divide Mode Register (R/W) */
-#define VR4181_DRAMHIBCTL       __preg16(KSEG1 + 0x0B0000B2)    /* DRAM Hibernate Control Register (R/W) */
-
-// Real Time Clock Unit (RTC)
-#define VR4181_ETIMELREG        __preg16(KSEG1 + 0x0B0000C0)    /* Elapsed Time L Register (R/W) */
-#define VR4181_ETIMEMREG        __preg16(KSEG1 + 0x0B0000C2)    /* Elapsed Time M Register (R/W) */
-#define VR4181_ETIMEHREG        __preg16(KSEG1 + 0x0B0000C4)    /* Elapsed Time H Register (R/W) */
-#define VR4181_ECMPLREG         __preg16(KSEG1 + 0x0B0000C8)    /* Elapsed Compare L Register (R/W) */
-#define VR4181_ECMPMREG         __preg16(KSEG1 + 0x0B0000CA)    /* Elapsed Compare M Register (R/W) */
-#define VR4181_ECMPHREG         __preg16(KSEG1 + 0x0B0000CC)    /* Elapsed Compare H Register (R/W) */
-#define VR4181_RTCL1LREG        __preg16(KSEG1 + 0x0B0000D0)    /* RTC Long 1 L Register (R/W) */
-#define VR4181_RTCL1HREG        __preg16(KSEG1 + 0x0B0000D2)    /* RTC Long 1 H Register (R/W) */
-#define VR4181_RTCL1CNTLREG     __preg16(KSEG1 + 0x0B0000D4)    /* RTC Long 1 Count L Register (R) */
-#define VR4181_RTCL1CNTHREG     __preg16(KSEG1 + 0x0B0000D6)    /* RTC Long 1 Count H Register (R) */
-#define VR4181_RTCL2LREG        __preg16(KSEG1 + 0x0B0000D8)    /* RTC Long 2 L Register (R/W) */
-#define VR4181_RTCL2HREG        __preg16(KSEG1 + 0x0B0000DA)    /* RTC Long 2 H Register (R/W) */
-#define VR4181_RTCL2CNTLREG     __preg16(KSEG1 + 0x0B0000DC)    /* RTC Long 2 Count L Register (R) */
-#define VR4181_RTCL2CNTHREG     __preg16(KSEG1 + 0x0B0000DE)    /* RTC Long 2 Count H Register (R) */
-#define VR4181_RTCINTREG        __preg16(KSEG1 + 0x0B0001DE)    /* RTC Interrupt Register (R/W) */
-
-// Deadman's Switch Unit (DSU)
-#define VR4181_DSUCNTREG        __preg16(KSEG1 + 0x0B0000E0)    /* DSU Control Register (R/W) */
-#define VR4181_DSUSETREG        __preg16(KSEG1 + 0x0B0000E2)    /* DSU Dead Time Set Register (R/W) */
-#define VR4181_DSUCLRREG        __preg16(KSEG1 + 0x0B0000E4)    /* DSU Clear Register (W) */
-#define VR4181_DSUTIMREG        __preg16(KSEG1 + 0x0B0000E6)    /* DSU Elapsed Time Register (R/W) */
-
-// General Purpose I/O Unit (GIU)
-#define VR4181_GPMD0REG         __preg16(KSEG1 + 0x0B000300)    /* GPIO Mode 0 Register (R/W) */
-#define VR4181_GPMD1REG         __preg16(KSEG1 + 0x0B000302)    /* GPIO Mode 1 Register (R/W) */
-#define VR4181_GPMD2REG         __preg16(KSEG1 + 0x0B000304)    /* GPIO Mode 2 Register (R/W) */
-#define VR4181_GPMD3REG         __preg16(KSEG1 + 0x0B000306)    /* GPIO Mode 3 Register (R/W) */
-#define VR4181_GPDATHREG        __preg16(KSEG1 + 0x0B000308)    /* GPIO Data High Register (R/W) */
-#define VR4181_GPDATHREG_GPIO16  0x0001
-#define VR4181_GPDATHREG_GPIO17  0x0002
-#define VR4181_GPDATHREG_GPIO18  0x0004
-#define VR4181_GPDATHREG_GPIO19  0x0008
-#define VR4181_GPDATHREG_GPIO20  0x0010
-#define VR4181_GPDATHREG_GPIO21  0x0020
-#define VR4181_GPDATHREG_GPIO22  0x0040
-#define VR4181_GPDATHREG_GPIO23  0x0080
-#define VR4181_GPDATHREG_GPIO24  0x0100
-#define VR4181_GPDATHREG_GPIO25  0x0200
-#define VR4181_GPDATHREG_GPIO26  0x0400
-#define VR4181_GPDATHREG_GPIO27  0x0800
-#define VR4181_GPDATHREG_GPIO28  0x1000
-#define VR4181_GPDATHREG_GPIO29  0x2000
-#define VR4181_GPDATHREG_GPIO30  0x4000
-#define VR4181_GPDATHREG_GPIO31  0x8000
-#define VR4181_GPDATLREG        __preg16(KSEG1 + 0x0B00030A)    /* GPIO Data Low Register (R/W) */
-#define VR4181_GPDATLREG_GPIO0   0x0001
-#define VR4181_GPDATLREG_GPIO1   0x0002
-#define VR4181_GPDATLREG_GPIO2   0x0004
-#define VR4181_GPDATLREG_GPIO3   0x0008
-#define VR4181_GPDATLREG_GPIO4   0x0010
-#define VR4181_GPDATLREG_GPIO5   0x0020
-#define VR4181_GPDATLREG_GPIO6   0x0040
-#define VR4181_GPDATLREG_GPIO7   0x0080
-#define VR4181_GPDATLREG_GPIO8   0x0100
-#define VR4181_GPDATLREG_GPIO9   0x0200
-#define VR4181_GPDATLREG_GPIO10  0x0400
-#define VR4181_GPDATLREG_GPIO11  0x0800
-#define VR4181_GPDATLREG_GPIO12  0x1000
-#define VR4181_GPDATLREG_GPIO13  0x2000
-#define VR4181_GPDATLREG_GPIO14  0x4000
-#define VR4181_GPDATLREG_GPIO15  0x8000
-#define VR4181_GPINTEN          __preg16(KSEG1 + 0x0B00030C)    /* GPIO Interrupt Enable Register (R/W) */
-#define VR4181_GPINTMSK         __preg16(KSEG1 + 0x0B00030E)    /* GPIO Interrupt Mask Register (R/W) */
-#define VR4181_GPINTTYPH        __preg16(KSEG1 + 0x0B000310)    /* GPIO Interrupt Type High Register (R/W) */
-#define VR4181_GPINTTYPL        __preg16(KSEG1 + 0x0B000312)    /* GPIO Interrupt Type Low Register (R/W) */
-#define VR4181_GPINTSTAT        __preg16(KSEG1 + 0x0B000314)    /* GPIO Interrupt Status Register (R/W) */
-#define VR4181_GPHIBSTH         __preg16(KSEG1 + 0x0B000316)    /* GPIO Hibernate Pin State High Register (R/W) */
-#define VR4181_GPHIBSTL         __preg16(KSEG1 + 0x0B000318)    /* GPIO Hibernate Pin State Low Register (R/W) */
-#define VR4181_GPSICTL          __preg16(KSEG1 + 0x0B00031A)    /* GPIO Serial Interface Control Register (R/W) */
-#define VR4181_KEYEN            __preg16(KSEG1 + 0x0B00031C)    /* Keyboard Scan Pin Enable Register (R/W) */
-#define VR4181_PCS0STRA         __preg16(KSEG1 + 0x0B000320)    /* Programmable Chip Select [0] Start Address Register (R/W) */
-#define VR4181_PCS0STPA         __preg16(KSEG1 + 0x0B000322)    /* Programmable Chip Select [0] Stop Address Register (R/W) */
-#define VR4181_PCS0HIA          __preg16(KSEG1 + 0x0B000324)    /* Programmable Chip Select [0] High Address Register (R/W) */
-#define VR4181_PCS1STRA         __preg16(KSEG1 + 0x0B000326)    /* Programmable Chip Select [1] Start Address Register (R/W) */
-#define VR4181_PCS1STPA         __preg16(KSEG1 + 0x0B000328)    /* Programmable Chip Select [1] Stop Address Register (R/W) */
-#define VR4181_PCS1HIA          __preg16(KSEG1 + 0x0B00032A)    /* Programmable Chip Select [1] High Address Register (R/W) */
-#define VR4181_PCSMODE          __preg16(KSEG1 + 0x0B00032C)    /* Programmable Chip Select Mode Register (R/W) */
-#define VR4181_LCDGPMODE        __preg16(KSEG1 + 0x0B00032E)    /* LCD General Purpose Mode Register (R/W) */
-#define VR4181_MISCREG0         __preg16(KSEG1 + 0x0B000330)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG1         __preg16(KSEG1 + 0x0B000332)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG2         __preg16(KSEG1 + 0x0B000334)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG3         __preg16(KSEG1 + 0x0B000336)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG4         __preg16(KSEG1 + 0x0B000338)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG5         __preg16(KSEG1 + 0x0B00033A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG6         __preg16(KSEG1 + 0x0B00033C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG7         __preg16(KSEG1 + 0x0B00033D)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG8         __preg16(KSEG1 + 0x0B000340)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG9         __preg16(KSEG1 + 0x0B000342)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG10        __preg16(KSEG1 + 0x0B000344)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG11        __preg16(KSEG1 + 0x0B000346)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG12        __preg16(KSEG1 + 0x0B000348)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG13        __preg16(KSEG1 + 0x0B00034A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG14        __preg16(KSEG1 + 0x0B00034C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG15        __preg16(KSEG1 + 0x0B00034E)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_SECIRQMASKL      VR4181_GPINTEN
-// No SECIRQMASKH for VR4181
-
-// Touch Panel Interface Unit (PIU)
-#define VR4181_PIUCNTREG        __preg16(KSEG1 + 0x0B000122)    /* PIU Control register (R/W) */
-#define VR4181_PIUCNTREG_PIUSEQEN       0x0004
-#define VR4181_PIUCNTREG_PIUPWR         0x0002
-#define VR4181_PIUCNTREG_PADRST         0x0001
-
-#define VR4181_PIUINTREG        __preg16(KSEG1 + 0x0B000124)    /* PIU Interrupt cause register (R/W) */
-#define VR4181_PIUINTREG_OVP            0x8000
-#define VR4181_PIUINTREG_PADCMD         0x0040
-#define VR4181_PIUINTREG_PADADP         0x0020
-#define VR4181_PIUINTREG_PADPAGE1       0x0010
-#define VR4181_PIUINTREG_PADPAGE0       0x0008
-#define VR4181_PIUINTREG_PADDLOST       0x0004
-#define VR4181_PIUINTREG_PENCHG         0x0001
-
-#define VR4181_PIUSIVLREG       __preg16(KSEG1 + 0x0B000126)    /* PIU Data sampling interval register (R/W) */
-#define VR4181_PIUSTBLREG       __preg16(KSEG1 + 0x0B000128)    /* PIU A/D converter start delay register (R/W) */
-#define VR4181_PIUCMDREG        __preg16(KSEG1 + 0x0B00012A)    /* PIU A/D command register (R/W) */
-#define VR4181_PIUASCNREG       __preg16(KSEG1 + 0x0B000130)    /* PIU A/D port scan register (R/W) */
-#define VR4181_PIUAMSKREG       __preg16(KSEG1 + 0x0B000132)    /* PIU A/D scan mask register (R/W) */
-#define VR4181_PIUCIVLREG       __preg16(KSEG1 + 0x0B00013E)    /* PIU Check interval register (R) */
-#define VR4181_PIUPB00REG       __preg16(KSEG1 + 0x0B0002A0)    /* PIU Page 0 Buffer 0 register (R/W) */
-#define VR4181_PIUPB01REG       __preg16(KSEG1 + 0x0B0002A2)    /* PIU Page 0 Buffer 1 register (R/W) */
-#define VR4181_PIUPB02REG       __preg16(KSEG1 + 0x0B0002A4)    /* PIU Page 0 Buffer 2 register (R/W) */
-#define VR4181_PIUPB03REG       __preg16(KSEG1 + 0x0B0002A6)    /* PIU Page 0 Buffer 3 register (R/W) */
-#define VR4181_PIUPB10REG       __preg16(KSEG1 + 0x0B0002A8)    /* PIU Page 1 Buffer 0 register (R/W) */
-#define VR4181_PIUPB11REG       __preg16(KSEG1 + 0x0B0002AA)    /* PIU Page 1 Buffer 1 register (R/W) */
-#define VR4181_PIUPB12REG       __preg16(KSEG1 + 0x0B0002AC)    /* PIU Page 1 Buffer 2 register (R/W) */
-#define VR4181_PIUPB13REG       __preg16(KSEG1 + 0x0B0002AE)    /* PIU Page 1 Buffer 3 register (R/W) */
-#define VR4181_PIUAB0REG        __preg16(KSEG1 + 0x0B0002B0)    /* PIU A/D scan Buffer 0 register (R/W) */
-#define VR4181_PIUAB1REG        __preg16(KSEG1 + 0x0B0002B2)    /* PIU A/D scan Buffer 1 register (R/W) */
-#define VR4181_PIUAB2REG        __preg16(KSEG1 + 0x0B0002B4)    /* PIU A/D scan Buffer 2 register (R/W) */
-#define VR4181_PIUAB3REG        __preg16(KSEG1 + 0x0B0002B6)    /* PIU A/D scan Buffer 3 register (R/W) */
-#define VR4181_PIUPB04REG       __preg16(KSEG1 + 0x0B0002BC)    /* PIU Page 0 Buffer 4 register (R/W) */
-#define VR4181_PIUPB14REG       __preg16(KSEG1 + 0x0B0002BE)    /* PIU Page 1 Buffer 4 register (R/W) */
-
-// Audio Interface Unit (AIU)
-#define VR4181_SODATREG         __preg16(KSEG1 + 0x0B000166)    /* Speaker Output Data Register (R/W) */
-#define VR4181_SCNTREG          __preg16(KSEG1 + 0x0B000168)    /* Speaker Output Control Register (R/W) */
-#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Mike Input Data Register (R/W) */
-#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Mike Input Control Register (R/W) */
-#define VR4181_DVALIDREG        __preg16(KSEG1 + 0x0B000178)    /* Data Valid Register (R/W) */
-#define VR4181_SEQREG           __preg16(KSEG1 + 0x0B00017A)    /* Sequential Register (R/W) */
-#define VR4181_INTREG           __preg16(KSEG1 + 0x0B00017C)    /* Interrupt Register (R/W) */
-#define VR4181_SDMADATREG       __preg16(KSEG1 + 0x0B000160)    /* Speaker DMA Data Register (R/W) */
-#define VR4181_MDMADATREG       __preg16(KSEG1 + 0x0B000162)    /* Microphone DMA Data Register (R/W) */
-#define VR4181_DAVREF_SETUP     __preg16(KSEG1 + 0x0B000164)    /* DAC Vref setup register (R/W) */
-#define VR4181_SCNVC_END        __preg16(KSEG1 + 0x0B00016E)    /* Speaker sample rate control (R/W) */
-#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Microphone Input Data Register (R/W) */
-#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Microphone Input Control Register (R/W) */
-#define VR4181_MCNVC_END        __preg16(KSEG1 + 0x0B00017E)    /* Microphone sample rate control (R/W) */
-
-// Keyboard Interface Unit (KIU)
-#define VR4181_KIUDAT0          __preg16(KSEG1 + 0x0B000180)    /* KIU Data0 Register (R/W) */
-#define VR4181_KIUDAT1          __preg16(KSEG1 + 0x0B000182)    /* KIU Data1 Register (R/W) */
-#define VR4181_KIUDAT2          __preg16(KSEG1 + 0x0B000184)    /* KIU Data2 Register (R/W) */
-#define VR4181_KIUDAT3          __preg16(KSEG1 + 0x0B000186)    /* KIU Data3 Register (R/W) */
-#define VR4181_KIUDAT4          __preg16(KSEG1 + 0x0B000188)    /* KIU Data4 Register (R/W) */
-#define VR4181_KIUDAT5          __preg16(KSEG1 + 0x0B00018A)    /* KIU Data5 Register (R/W) */
-#define VR4181_KIUSCANREP       __preg16(KSEG1 + 0x0B000190)    /* KIU Scan/Repeat Register (R/W) */
-#define VR4181_KIUSCANREP_KEYEN      0x8000
-#define VR4181_KIUSCANREP_SCANSTP    0x0008
-#define VR4181_KIUSCANREP_SCANSTART  0x0004
-#define VR4181_KIUSCANREP_ATSTP      0x0002
-#define VR4181_KIUSCANREP_ATSCAN     0x0001
-#define VR4181_KIUSCANS         __preg16(KSEG1 + 0x0B000192)    /* KIU Scan Status Register (R) */
-#define VR4181_KIUWKS           __preg16(KSEG1 + 0x0B000194)    /* KIU Wait Keyscan Stable Register (R/W) */
-#define VR4181_KIUWKI           __preg16(KSEG1 + 0x0B000196)    /* KIU Wait Keyscan Interval Register (R/W) */
-#define VR4181_KIUINT           __preg16(KSEG1 + 0x0B000198)    /* KIU Interrupt Register (R/W) */
-#define VR4181_KIUINT_KDATLOST       0x0004
-#define VR4181_KIUINT_KDATRDY        0x0002
-#define VR4181_KIUINT_SCANINT        0x0001
-#define VR4181_KIUDAT6          __preg16(KSEG1 + 0x0B00018C)    /* Scan Line 6 Key Data Register (R) */
-#define VR4181_KIUDAT7          __preg16(KSEG1 + 0x0B00018E)    /* Scan Line 7 Key Data Register (R) */
-
-// CompactFlash Controller
-#define VR4181_PCCARDINDEX      __preg8(KSEG1 + 0x0B0008E0)     /* PC Card Controller Index Register */
-#define VR4181_PCCARDDATA       __preg8(KSEG1 + 0x0B0008E1)     /* PC Card Controller Data Register */
-#define VR4181_INTSTATREG       __preg16(KSEG1 + 0x0B0008F8)    /* Interrupt Status Register (R/W) */
-#define VR4181_INTMSKREG        __preg16(KSEG1 + 0x0B0008FA)    /* Interrupt Mask Register (R/W) */
-#define VR4181_CFG_REG_1        __preg16(KSEG1 + 0x0B0008FE)    /* Configuration Register 1 */
-
-// LED Control Unit (LED)
-#define VR4181_LEDHTSREG        __preg16(KSEG1 + 0x0B000240)    /* LED H Time Set register (R/W) */
-#define VR4181_LEDLTSREG        __preg16(KSEG1 + 0x0B000242)    /* LED L Time Set register (R/W) */
-#define VR4181_LEDCNTREG        __preg16(KSEG1 + 0x0B000248)    /* LED Control register (R/W) */
-#define VR4181_LEDASTCREG       __preg16(KSEG1 + 0x0B00024A)    /* LED Auto Stop Time Count register (R/W) */
-#define VR4181_LEDINTREG        __preg16(KSEG1 + 0x0B00024C)    /* LED Interrupt register (R/W) */
-
-// Serial Interface Unit (SIU / SIU1 and SIU2)
-#define VR4181_SIURB            __preg8(KSEG1 + 0x0C000010)     /* Receiver Buffer Register (Read) DLAB = 0 (R) */
-#define VR4181_SIUTH            __preg8(KSEG1 + 0x0C000010)     /* Transmitter Holding Register (Write) DLAB = 0 (W) */
-#define VR4181_SIUDLL           __preg8(KSEG1 + 0x0C000010)     /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
-#define VR4181_SIUIE            __preg8(KSEG1 + 0x0C000011)     /* Interrupt Enable DLAB = 0 (R/W) */
-#define VR4181_SIUDLM           __preg8(KSEG1 + 0x0C000011)     /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
-#define VR4181_SIUIID           __preg8(KSEG1 + 0x0C000012)     /* Interrupt Identification Register (Read) (R) */
-#define VR4181_SIUFC            __preg8(KSEG1 + 0x0C000012)     /* FIFO Control Register (Write) (W) */
-#define VR4181_SIULC            __preg8(KSEG1 + 0x0C000013)     /* Line Control Register (R/W) */
-#define VR4181_SIUMC            __preg8(KSEG1 + 0x0C000014)     /* MODEM Control Register (R/W) */
-#define VR4181_SIULS            __preg8(KSEG1 + 0x0C000015)     /* Line Status Register (R/W) */
-#define VR4181_SIUMS            __preg8(KSEG1 + 0x0C000016)     /* MODEM Status Register (R/W) */
-#define VR4181_SIUSC            __preg8(KSEG1 + 0x0C000017)     /* Scratch Register (R/W) */
-#define VR4181_SIURESET         __preg8(KSEG1 + 0x0C000019)     /* SIU Reset Register (R/W) */
-#define VR4181_SIUACTMSK        __preg8(KSEG1 + 0x0C00001C)     /* SIU Activity Mask (R/W) */
-#define VR4181_SIUACTTMR        __preg8(KSEG1 + 0x0C00001E)     /* SIU Activity Timer (R/W) */
-#define VR4181_SIURB_2          __preg8(KSEG1 + 0x0C000000)     /* Receive Buffer Register (Read) (R) */
-#define VR4181_SIUTH_2          __preg8(KSEG1 + 0x0C000000)     /* Transmitter Holding Register (Write) (W) */
-#define VR4181_SIUDLL_2         __preg8(KSEG1 + 0x0C000000)     /* Divisor Latch (Least Significant Byte) (R/W) */
-#define VR4181_SIUIE_2          __preg8(KSEG1 + 0x0C000001)     /* Interrupt Enable (DLAB = 0) (R/W) */
-#define VR4181_SIUDLM_2         __preg8(KSEG1 + 0x0C000001)     /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
-#define VR4181_SIUIID_2         __preg8(KSEG1 + 0x0C000002)     /* Interrupt Identification Register (Read) (R) */
-#define VR4181_SIUFC_2          __preg8(KSEG1 + 0x0C000002)     /* FIFO Control Register (Write) (W) */
-#define VR4181_SIULC_2          __preg8(KSEG1 + 0x0C000003)     /* Line Control Register (R/W) */
-#define VR4181_SIUMC_2          __preg8(KSEG1 + 0x0C000004)     /* Modem Control Register (R/W) */
-#define VR4181_SIULS_2          __preg8(KSEG1 + 0x0C000005)     /* Line Status Register (R/W) */
-#define VR4181_SIUMS_2          __preg8(KSEG1 + 0x0C000006)     /* Modem Status Register (R/W) */
-#define VR4181_SIUSC_2          __preg8(KSEG1 + 0x0C000007)     /* Scratch Register (R/W) */
-#define VR4181_SIUIRSEL_2       __preg8(KSEG1 + 0x0C000008)     /* SIU IrDA Selectot (R/W) */
-#define VR4181_SIURESET_2       __preg8(KSEG1 + 0x0C000009)     /* SIU Reset Register (R/W) */
-#define VR4181_SIUCSEL_2        __preg8(KSEG1 + 0x0C00000A)     /* IrDA Echo-back Control (R/W) */
-#define VR4181_SIUACTMSK_2      __preg8(KSEG1 + 0x0C00000C)     /* SIU Activity Mask Register (R/W) */
-#define VR4181_SIUACTTMR_2      __preg8(KSEG1 + 0x0C00000E)     /* SIU Activity Timer Register (R/W) */
-
-
-// USB Module
-#define VR4181_USBINFIFO        __preg16(KSEG1 + 0x0B000780)    /* USB Bulk Input FIFO (Bulk In End Point) (W) */
-#define VR4181_USBOUTFIFO       __preg16(KSEG1 + 0x0B000782)    /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
-#define VR4181_USBCTLFIFO       __preg16(KSEG1 + 0x0B000784)    /* USB Control FIFO (Control End Point) (W) */
-#define VR4181_USBSTAT          __preg16(KSEG1 + 0x0B000786)    /* Interrupt Status Register (R/W) */
-#define VR4181_USBINTMSK        __preg16(KSEG1 + 0x0B000788)    /* Interrupt Mask Register (R/W) */
-#define VR4181_USBCTLREG        __preg16(KSEG1 + 0x0B00078A)    /* Control Register (R/W) */
-#define VR4181_USBSTPREG        __preg16(KSEG1 + 0x0B00078C)    /* USB Transfer Stop Register (R/W) */
-
-// LCD Controller
-#define VR4181_HRTOTALREG       __preg16(KSEG1 + 0x0A000400)    /* Horizontal total Register (R/W) */
-#define VR4181_HRVISIBREG       __preg16(KSEG1 + 0x0A000402)    /* Horizontal Visible Register (R/W) */
-#define VR4181_LDCLKSTREG       __preg16(KSEG1 + 0x0A000404)    /* Load clock start Register (R/W) */
-#define VR4181_LDCLKNDREG       __preg16(KSEG1 + 0x0A000406)    /* Load clock end Register (R/W) */
-#define VR4181_VRTOTALREG       __preg16(KSEG1 + 0x0A000408)    /* Vertical Total Register (R/W) */
-#define VR4181_VRVISIBREG       __preg16(KSEG1 + 0x0A00040A)    /* Vertical Visible Register (R/W) */
-#define VR4181_FVSTARTREG       __preg16(KSEG1 + 0x0A00040C)    /* FLM vertical start Register (R/W) */
-#define VR4181_FVENDREG         __preg16(KSEG1 + 0x0A00040E)    /* FLM vertical end Register (R/W) */
-#define VR4181_LCDCTRLREG       __preg16(KSEG1 + 0x0A000410)    /* LCD control Register (R/W) */
-#define VR4181_LCDINRQREG       __preg16(KSEG1 + 0x0A000412)    /* LCD Interrupt request Register (R/W) */
-#define VR4181_LCDCFGREG0       __preg16(KSEG1 + 0x0A000414)    /* LCD Configuration Register 0 (R/W) */
-#define VR4181_LCDCFGREG1       __preg16(KSEG1 + 0x0A000416)    /* LCD Configuration Register 1 (R/W) */
-#define VR4181_FBSTAD1REG       __preg16(KSEG1 + 0x0A000418)    /* Frame Buffer Start Address 1 Register (R/W) */
-#define VR4181_FBSTAD2REG       __preg16(KSEG1 + 0x0A00041A)    /* Frame Buffer Start Address 2 Register (R/W) */
-#define VR4181_FBNDAD1REG       __preg16(KSEG1 + 0x0A000420)    /* Frame Buffer End Address 1 Register (R/W) */
-#define VR4181_FBNDAD2REG       __preg16(KSEG1 + 0x0A000422)    /* Frame Buffer End Address 2 register (R/W) */
-#define VR4181_FHSTARTREG       __preg16(KSEG1 + 0x0A000424)    /* FLM horizontal Start Register (R/W) */
-#define VR4181_FHENDREG         __preg16(KSEG1 + 0x0A000426)    /* FLM horizontal End Register (R/W) */
-#define VR4181_PWRCONREG1       __preg16(KSEG1 + 0x0A000430)    /* Power Control register 1 (R/W) */
-#define VR4181_PWRCONREG2       __preg16(KSEG1 + 0x0A000432)    /* Power Control register 2 (R/W) */
-#define VR4181_LCDIMSKREG       __preg16(KSEG1 + 0x0A000434)    /* LCD Interrupt Mask register (R/W) */
-#define VR4181_CPINDCTREG       __preg16(KSEG1 + 0x0A00047E)    /* Color palette Index and control Register (R/W) */
-#define VR4181_CPALDATREG       __preg32(KSEG1 + 0x0A000480)    /* Color palette data register (32bits Register) (R/W) */
-
-// physical address spaces
-#define VR4181_LCD             0x0a000000
-#define VR4181_INTERNAL_IO_2   0x0b000000
-#define VR4181_INTERNAL_IO_1   0x0c000000
-#define VR4181_ISA_MEM         0x10000000
-#define VR4181_ISA_IO          0x14000000
-#define VR4181_ROM             0x18000000
-
-// This is the base address for IO port decoding to which the 16 bit IO port address
-// is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
-// attempted, which can be handy for turning up parts of the kernel that make
-// incorrect architecture assumptions (by assuming that everything acts like a PC),
-// but we need it correctly defined to use the PCMCIA/CF controller:
-#define VR4181_PORT_BASE        (KSEG1 + VR4181_ISA_IO)
-#define VR4181_ISAMEM_BASE      (KSEG1 + VR4181_ISA_MEM)
-
-#endif /* __ASM_VR4181_VR4181_H */
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h
new file mode 100644
index 000000000000..8590885a7638
--- /dev/null
+++ b/include/asm-mips/vr41xx/giu.h
@@ -0,0 +1,69 @@
+/*
+ *  Include file for NEC VR4100 series General-purpose I/O Unit.
+ *
+ *  Copyright (C) 2005  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VR41XX_GIU_H
+#define __NEC_VR41XX_GIU_H
+
+typedef enum {
+        IRQ_TRIGGER_LEVEL,
+        IRQ_TRIGGER_EDGE,
+        IRQ_TRIGGER_EDGE_FALLING,
+        IRQ_TRIGGER_EDGE_RISING,
+} irq_trigger_t;
+
+typedef enum {
+        IRQ_SIGNAL_THROUGH,
+        IRQ_SIGNAL_HOLD,
+} irq_signal_t;
+
+extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
+
+typedef enum {
+        IRQ_LEVEL_LOW,
+        IRQ_LEVEL_HIGH,
+} irq_level_t;
+
+extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
+
+typedef enum {
+        GPIO_DATA_LOW,
+        GPIO_DATA_HIGH,
+        GPIO_DATA_INVAL,
+} gpio_data_t;
+
+extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
+extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
+
+typedef enum {
+        GPIO_INPUT,
+        GPIO_OUTPUT,
+        GPIO_OUTPUT_DISABLE,
+} gpio_direction_t;
+
+extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
+
+typedef enum {
+        GPIO_PULL_DOWN,
+        GPIO_PULL_UP,
+        GPIO_PULL_DISABLE,
+} gpio_pull_t;
+
+extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
+
+#endif /* __NEC_VR41XX_GIU_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index ad0d1ea144f0..bd2723c30901 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -7,7 +7,7 @@
  * Copyright (C) 2001, 2002 Paul Mundt
  * Copyright (C) 2002 MontaVista Software, Inc.
  * Copyright (C) 2002 TimeSys Corp.
- * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
 #define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
 #define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
-#define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
-#define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
-#define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
-#define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
-#define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
+#define INT0_IRQ                MIPS_CPU_IRQ(2)
+#define INT1_IRQ                MIPS_CPU_IRQ(3)
+#define INT2_IRQ                MIPS_CPU_IRQ(4)
+#define INT3_IRQ                MIPS_CPU_IRQ(5)
+#define INT4_IRQ                MIPS_CPU_IRQ(6)
 #define TIMER_IRQ               MIPS_CPU_IRQ(7)
 
 /* SYINT1 Interrupt Numbers */
@@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define PIU_IRQ                 SYSINT1_IRQ(5)
 #define AIU_IRQ                 SYSINT1_IRQ(6)
 #define KIU_IRQ                 SYSINT1_IRQ(7)
-#define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
+#define GIUINT_IRQ              SYSINT1_IRQ(8)
 #define SIU_IRQ                 SYSINT1_IRQ(9)
 #define BUSERR_IRQ              SYSINT1_IRQ(10)
 #define SOFTINT_IRQ             SYSINT1_IRQ(11)
@@ -126,10 +126,9 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define GIU_IRQ_BASE            40
 #define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
 #define GIU_IRQ_LAST            GIU_IRQ(31)
-#define GIU_IRQ_TO_PIN(x)       ((x) - GIU_IRQ_BASE)    /* Pin 0-31 */
 
 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
-extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
+extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
 
 #define PIUINT_COMMAND          0x0040
 #define PIUINT_DATA             0x0020
@@ -197,38 +196,4 @@ extern void vr41xx_disable_csiint(uint16_t mask);
 extern void vr41xx_enable_bcuint(void);
 extern void vr41xx_disable_bcuint(void);
 
-/*
- * General-Purpose I/O Unit
- */
-enum {
-        TRIGGER_LEVEL,
-        TRIGGER_EDGE,
-        TRIGGER_EDGE_FALLING,
-        TRIGGER_EDGE_RISING
-};
-
-enum {
-        SIGNAL_THROUGH,
-        SIGNAL_HOLD
-};
-
-extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
-
-enum {
-        LEVEL_LOW,
-        LEVEL_HIGH
-};
-
-extern void vr41xx_set_irq_level(int pin, int level);
-
-enum {
-        PIO_INPUT,
-        PIO_OUTPUT
-};
-
-enum {
-        DATA_LOW,
-        DATA_HIGH
-};
-
 #endif /* __NEC_VR41XX_H */
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
index 58e193c51b45..bb7a85c186e4 100644
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ b/include/asm-mips/vr41xx/vrc4173.h
@@ -21,8 +21,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#ifndef __NEC_VRC4173_H 
-#define __NEC_VRC4173_H 
+#ifndef __NEC_VRC4173_H
+#define __NEC_VRC4173_H
 
 #include <linux/config.h>
 #include <asm/io.h>
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c4a704121343..04ee53b34c2e 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
  */
 #define BCM1250_M3_WAR 1
 
-/* 
+/*
  * This is a DUART workaround related to glitches around register accesses
  */
 #define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
 
 /*
  * Fill buffers not flushed on CACHE instructions
- * 
+ *
  * Hit_Invalidate_I cacheops invalidate an icache line but the refill
  * for that line can get stale data from the fill buffer instead of
  * accessing memory if the previous icache miss was also to that line.
diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h
index 75c0ddfeca13..4d84a90b0f20 100644
--- a/include/asm-mips/xxs1500.h
+++ b/include/asm-mips/xxs1500.h
@@ -22,7 +22,7 @@
  *
  * ########################################################################
  *
- * 
+ *
  */
 #ifndef __ASM_XXS1500_H
 #define __ASM_XXS1500_H
diff --git a/include/asm-parisc/auxvec.h b/include/asm-parisc/auxvec.h
new file mode 100644
index 000000000000..9c3ac4b89dc9
--- /dev/null
+++ b/include/asm-parisc/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMPARISC_AUXVEC_H
+#define __ASMPARISC_AUXVEC_H
+
+#endif
diff --git a/include/asm-parisc/compat.h b/include/asm-parisc/compat.h
index ca0eac647a05..38b918feead9 100644
--- a/include/asm-parisc/compat.h
+++ b/include/asm-parisc/compat.h
@@ -13,8 +13,10 @@ typedef s32	compat_ssize_t;
 typedef s32     compat_time_t;
 typedef s32     compat_clock_t;
 typedef s32     compat_pid_t;
-typedef u32     compat_uid_t;
-typedef u32     compat_gid_t;
+typedef u32     __compat_uid_t;
+typedef u32     __compat_gid_t;
+typedef u32     __compat_uid32_t;
+typedef u32     __compat_gid32_t;
 typedef u16     compat_mode_t;
 typedef u32     compat_ino_t;
 typedef u32     compat_dev_t;
@@ -24,7 +26,7 @@ typedef u16	compat_nlink_t;
 typedef u16     compat_ipc_pid_t;
 typedef s32     compat_daddr_t;
 typedef u32     compat_caddr_t;
-typedef u32     compat_timer_t;
+typedef s32     compat_timer_t;
 
 typedef s32     compat_int_t;
 typedef s32     compat_long_t;
@@ -67,8 +69,8 @@ struct compat_stat {
         compat_dev_t            st_realdev;
         u16                     st_basemode;
         u16                     st_spareshort;
-        compat_uid_t            st_uid;
-        compat_gid_t            st_gid;
+        __compat_uid32_t        st_uid;
+        __compat_gid32_t        st_gid;
         u32                     st_spare4[3];
 };
 
diff --git a/include/asm-parisc/emergency-restart.h b/include/asm-parisc/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-parisc/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-parisc/fcntl.h b/include/asm-parisc/fcntl.h
index def35230716a..317851fa78f3 100644
--- a/include/asm-parisc/fcntl.h
+++ b/include/asm-parisc/fcntl.h
@@ -3,38 +3,22 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_ACCMODE       00000003
-#define O_RDONLY        00000000
-#define O_WRONLY        00000001
-#define O_RDWR          00000002
 #define O_APPEND        00000010
 #define O_BLKSEEK       00000100 /* HPUX only */
 #define O_CREAT         00000400 /* not fcntl */
-#define O_TRUNC         00001000 /* not fcntl */
 #define O_EXCL          00002000 /* not fcntl */
 #define O_LARGEFILE     00004000
 #define O_SYNC          00100000
 #define O_NONBLOCK      00200004 /* HPUX has separate NDELAY & NONBLOCK */
-#define O_NDELAY        O_NONBLOCK
 #define O_NOCTTY        00400000 /* not fcntl */
 #define O_DSYNC         01000000 /* HPUX only */
 #define O_RSYNC         02000000 /* HPUX only */
 #define O_NOATIME       04000000
 
-#define FASYNC          00020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT        00040000 /* direct disk access hint - currently ignored */
 #define O_DIRECTORY     00010000 /* must be a directory */
 #define O_NOFOLLOW      00000200 /* don't follow links */
 #define O_INVISIBLE     04000000 /* invisible I/O, for DMAPI/XDSM */
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get f_flags */
-#define F_SETFD         2       /* set f_flags */
-#define F_GETFL         3       /* more flags (cloexec) */
-#define F_SETFL         4
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
 #define F_GETLK64       8
 #define F_SETLK64       9
 #define F_SETLKW64      10
@@ -44,49 +28,11 @@
 #define F_SETSIG        13      /*  for sockets. */
 #define F_GETSIG        14      /*  for sockets. */
 
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
 /* for posix fcntl() and lockf() */
 #define F_RDLCK         01
 #define F_WRLCK         02
 #define F_UNLCK         03
 
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short l_type;
-        short l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE  1024
+#include <asm-generic/fcntl.h>
 
 #endif
diff --git a/include/asm-parisc/futex.h b/include/asm-parisc/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-parisc/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-parisc/hdreg.h b/include/asm-parisc/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-parisc/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-parisc/irq.h b/include/asm-parisc/irq.h
index 75654ba93353..f876bdf22056 100644
--- a/include/asm-parisc/irq.h
+++ b/include/asm-parisc/irq.h
@@ -26,6 +26,11 @@
 
 #define NR_IRQS         (CPU_IRQ_MAX + 1)
 
+/*
+ * IRQ line status macro IRQ_PER_CPU is used
+ */
+#define ARCH_HAS_IRQ_PER_CPU
+
 static __inline__ int irq_canonicalize(int irq)
 {
         return (irq == 2) ? 9 : irq;
diff --git a/include/asm-parisc/mmzone.h b/include/asm-parisc/mmzone.h
index 928bf50c4693..595d3dce120a 100644
--- a/include/asm-parisc/mmzone.h
+++ b/include/asm-parisc/mmzone.h
@@ -19,7 +19,6 @@ extern struct node_map_data node_data[];
  */
 #define kvaddr_to_nid(kaddr)    pfn_to_nid(__pa(kaddr) >> PAGE_SHIFT)
 
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)                                               \
 ({                                                                      \
@@ -38,7 +37,7 @@ extern struct node_map_data node_data[];
 ({                                                                      \
         unsigned long __pfn = (pfn);                                    \
         int __node  = pfn_to_nid(__pfn);                                \
-        &node_mem_map(__node)[node_localnr(__pfn,__node)];              \
+        &NODE_DATA(__node)->node_mem_map[node_localnr(__pfn,__node)];   \
 })
 
 #define page_to_pfn(pg)                                                 \
diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h
index 4a12692f94b4..44eae9f8274d 100644
--- a/include/asm-parisc/page.h
+++ b/include/asm-parisc/page.h
@@ -74,20 +74,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 typedef struct __physmem_range {
         unsigned long start_pfn;
         unsigned long pages;       /* PAGE_SIZE pages */
@@ -159,4 +145,6 @@ extern int npmem_ranges;
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _PARISC_PAGE_H */
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index 0763c2982fb0..98d79a3d54fa 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -230,10 +230,33 @@ extern inline void pcibios_register_hba(struct pci_hba_data *x)
 /* export the pci_ DMA API in terms of the dma_ one */
 #include <asm-generic/pci-dma-compat.h>
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
 extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                          struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 239c5dcab7e6..82fd820d684f 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -19,18 +19,4 @@
  * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
  */
  
-#define STD_SERIAL_PORT_DEFNS                   \
-        { 0, },         /* ttyS0 */     \
-        { 0, },         /* ttyS1 */     \
-        { 0, },         /* ttyS2 */     \
-        { 0, },         /* ttyS3 */     \
-        { 0, },         /* ttyS4 */     \
-        { 0, },         /* ttyS5 */     \
-        { 0, },         /* ttyS6 */     \
-        { 0, },         /* ttyS7 */     \
-        { 0, },         /* ttyS8 */
-
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS
-
+#define SERIAL_PORT_DFNS
diff --git a/include/asm-parisc/smp.h b/include/asm-parisc/smp.h
index fde77ac35463..9413f67a540b 100644
--- a/include/asm-parisc/smp.h
+++ b/include/asm-parisc/smp.h
@@ -51,7 +51,7 @@ extern void smp_send_reschedule(int cpu);
 
 extern unsigned long cpu_present_mask;
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 #endif /* CONFIG_SMP */
 
diff --git a/include/asm-parisc/socket.h b/include/asm-parisc/socket.h
index 4a77996c1862..1bf54dc53c10 100644
--- a/include/asm-parisc/socket.h
+++ b/include/asm-parisc/socket.h
@@ -16,6 +16,8 @@
 /* To add :#define SO_REUSEPORT 0x0200 */
 #define SO_SNDBUF       0x1001
 #define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
 #define SO_SNDLOWAT     0x1003
 #define SO_RCVLOWAT     0x1004
 #define SO_SNDTIMEO     0x1005
diff --git a/include/asm-parisc/thread_info.h b/include/asm-parisc/thread_info.h
index fe9b7f8ae4c6..57bbb76cb6c1 100644
--- a/include/asm-parisc/thread_info.h
+++ b/include/asm-parisc/thread_info.h
@@ -12,7 +12,7 @@ struct thread_info {
         unsigned long flags;            /* thread_info flags (see TIF_*) */
         mm_segment_t addr_limit;        /* user-level address space limit */
         __u32 cpu;                      /* current CPU */
-        __s32 preempt_count;            /* 0=premptable, <0=BUG; will also serve as bh-counter */
+        int preempt_count;              /* 0=premptable, <0=BUG; will also serve as bh-counter */
         struct restart_block restart_block;
 };
 
diff --git a/include/asm-parisc/types.h b/include/asm-parisc/types.h
index 8fe7a44ea205..d21b9d0d63ea 100644
--- a/include/asm-parisc/types.h
+++ b/include/asm-parisc/types.h
@@ -56,8 +56,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u64 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-parisc/uaccess.h b/include/asm-parisc/uaccess.h
index c1b5bdea53ee..f6c417c8c484 100644
--- a/include/asm-parisc/uaccess.h
+++ b/include/asm-parisc/uaccess.h
@@ -40,10 +40,6 @@ static inline long access_ok(int type, const void __user * addr,
         return 1;
 }
 
-#define verify_area(type,addr,size) (0) /* FIXME: all users should go away soon,
-                                         * and use access_ok instead, then this
-                                         * should be removed. */
-
 #define put_user __put_user
 #define get_user __get_user
 
diff --git a/include/asm-ppc64/8253pit.h b/include/asm-powerpc/8253pit.h
index 285f78488ccb..862708a749b0 100644
--- a/include/asm-ppc64/8253pit.h
+++ b/include/asm-powerpc/8253pit.h
@@ -5,6 +5,6 @@
 #ifndef _8253PIT_H
 #define _8253PIT_H
 
-#define PIT_TICK_RATE   1193182UL
+#define PIT_TICK_RATE   1193182UL
 
 #endif
diff --git a/include/asm-ppc/agp.h b/include/asm-powerpc/agp.h
index ca9e423307f4..ca9e423307f4 100644
--- a/include/asm-ppc/agp.h
+++ b/include/asm-powerpc/agp.h
diff --git a/include/asm-ppc64/shmparam.h b/include/asm-powerpc/bugs.h
index b2825ceff05e..310187d0e33a 100644
--- a/include/asm-ppc64/shmparam.h
+++ b/include/asm-powerpc/bugs.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_SHMPARAM_H
-#define _PPC64_SHMPARAM_H
+#ifndef _POWERPC_BUGS_H
+#define _POWERPC_BUGS_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -8,6 +8,11 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
+/*
+ * This file is included by 'init/main.c' to check for
+ * architecture-dependent bugs.
+ */
+
+extern void check_bugs(void);
 
-#endif /* _PPC64_SHMPARAM_H */
+#endif /* _POWERPC_BUGS_H */
diff --git a/include/asm-powerpc/cputime.h b/include/asm-powerpc/cputime.h
new file mode 100644
index 000000000000..6d68ad7e0ea3
--- /dev/null
+++ b/include/asm-powerpc/cputime.h
@@ -0,0 +1 @@
+#include <asm-generic/cputime.h>
diff --git a/include/asm-ppc/div64.h b/include/asm-powerpc/div64.h
index 6cd978cefb28..6cd978cefb28 100644
--- a/include/asm-ppc/div64.h
+++ b/include/asm-powerpc/div64.h
diff --git a/include/asm-powerpc/emergency-restart.h b/include/asm-powerpc/emergency-restart.h
new file mode 100644
index 000000000000..3711bd9d50bd
--- /dev/null
+++ b/include/asm-powerpc/emergency-restart.h
@@ -0,0 +1 @@
+#include <asm-generic/emergency-restart.h>
diff --git a/include/asm-ppc/errno.h b/include/asm-powerpc/errno.h
index 19f20bd41ae6..19f20bd41ae6 100644
--- a/include/asm-ppc/errno.h
+++ b/include/asm-powerpc/errno.h
diff --git a/include/asm-powerpc/fcntl.h b/include/asm-powerpc/fcntl.h
new file mode 100644
index 000000000000..ce5c4516d404
--- /dev/null
+++ b/include/asm-powerpc/fcntl.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_FCNTL_H
+#define _ASM_FCNTL_H
+
+#define O_DIRECTORY      040000 /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_LARGEFILE     0200000
+#define O_DIRECT        0400000 /* direct disk access hint */
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _ASM_FCNTL_H */
diff --git a/include/asm-ppc/ioctl.h b/include/asm-powerpc/ioctl.h
index 93c6acfdd0fd..93c6acfdd0fd 100644
--- a/include/asm-ppc/ioctl.h
+++ b/include/asm-powerpc/ioctl.h
diff --git a/include/asm-ppc/ioctls.h b/include/asm-powerpc/ioctls.h
index f5b7f2b055e7..f5b7f2b055e7 100644
--- a/include/asm-ppc/ioctls.h
+++ b/include/asm-powerpc/ioctls.h
diff --git a/include/asm-ppc/ipc.h b/include/asm-powerpc/ipc.h
index a46e3d9c2a3f..a46e3d9c2a3f 100644
--- a/include/asm-ppc/ipc.h
+++ b/include/asm-powerpc/ipc.h
diff --git a/include/asm-ppc/linkage.h b/include/asm-powerpc/linkage.h
index 291c2d01c44f..291c2d01c44f 100644
--- a/include/asm-ppc/linkage.h
+++ b/include/asm-powerpc/linkage.h
diff --git a/include/asm-ppc64/local.h b/include/asm-powerpc/local.h
index c11c530f74d0..c11c530f74d0 100644
--- a/include/asm-ppc64/local.h
+++ b/include/asm-powerpc/local.h
diff --git a/include/asm-ppc64/mc146818rtc.h b/include/asm-powerpc/mc146818rtc.h
index f713e1bbb533..a5619a2a1393 100644
--- a/include/asm-ppc64/mc146818rtc.h
+++ b/include/asm-powerpc/mc146818rtc.h
@@ -1,3 +1,6 @@
+#ifndef _POWERPC_MC146818RTC_H
+#define _POWERPC_MC146818RTC_H
+
 /*
  * Machine dependent access functions for RTC registers.
  *
@@ -6,8 +9,8 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
-#ifndef __ASM_PPC64_MC146818RTC_H
-#define __ASM_PPC64_MC146818RTC_H
+
+#ifdef __KERNEL__
 
 #include <asm/io.h>
 
@@ -29,4 +32,5 @@ outb_p((addr),RTC_PORT(0)); \
 outb_p((val),RTC_PORT(1)); \
 })
 
-#endif /* __ASM_PPC64_MC146818RTC_H */
+#endif  /* __KERNEL__ */
+#endif  /* _POWERPC_MC146818RTC_H */
diff --git a/include/asm-ppc64/mman.h b/include/asm-powerpc/mman.h
index d4f93446a52c..f2d55988d749 100644
--- a/include/asm-ppc64/mman.h
+++ b/include/asm-powerpc/mman.h
@@ -1,5 +1,5 @@
-#ifndef __PPC64_MMAN_H__
-#define __PPC64_MMAN_H__
+#ifndef _POWERPC_MMAN_H
+#define _POWERPC_MMAN_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -49,4 +49,4 @@
 #define MAP_ANON        MAP_ANONYMOUS
 #define MAP_FILE        0
 
-#endif /* __PPC64_MMAN_H__ */
+#endif /* _POWERPC_MMAN_H */
diff --git a/include/asm-powerpc/module.h b/include/asm-powerpc/module.h
new file mode 100644
index 000000000000..4438f4fd6524
--- /dev/null
+++ b/include/asm-powerpc/module.h
@@ -0,0 +1,77 @@
+#ifndef _POWERPC_MODULE_H
+#define _POWERPC_MODULE_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/list.h>
+#include <asm/bug.h>
+
+
+#ifndef __powerpc64__
+/*
+ * Thanks to Paul M for explaining this.
+ *
+ * PPC can only do rel jumps += 32MB, and often the kernel and other
+ * modules are furthur away than this.  So, we jump to a table of
+ * trampolines attached to the module (the Procedure Linkage Table)
+ * whenever that happens.
+ */
+
+struct ppc_plt_entry {
+        /* 16 byte jump instruction sequence (4 instructions) */
+        unsigned int jump[4];
+};
+#endif  /* __powerpc64__ */
+
+
+struct mod_arch_specific {
+#ifdef __powerpc64__
+        unsigned int stubs_section;     /* Index of stubs section in module */
+        unsigned int toc_section;       /* What section is the TOC? */
+#else
+        /* Indices of PLT sections within module. */
+        unsigned int core_plt_section;
+        unsigned int init_plt_section;
+#endif
+
+        /* List of BUG addresses, source line numbers and filenames */
+        struct list_head bug_list;
+        struct bug_entry *bug_table;
+        unsigned int num_bugs;
+};
+
+extern struct bug_entry *module_find_bug(unsigned long bugaddr);
+
+/*
+ * Select ELF headers.
+ * Make empty section for module_frob_arch_sections to expand.
+ */
+
+#ifdef __powerpc64__
+#    define Elf_Shdr    Elf64_Shdr
+#    define Elf_Sym     Elf64_Sym
+#    define Elf_Ehdr    Elf64_Ehdr
+#    ifdef MODULE
+        asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
+#    endif
+#else
+#    define Elf_Shdr    Elf32_Shdr
+#    define Elf_Sym     Elf32_Sym
+#    define Elf_Ehdr    Elf32_Ehdr
+#    ifdef MODULE
+        asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
+        asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
+#    endif      /* MODULE */
+#endif
+
+
+struct exception_table_entry;
+void sort_ex_table(struct exception_table_entry *start,
+                   struct exception_table_entry *finish);
+
+#endif /* _POWERPC_MODULE_H */
diff --git a/include/asm-ppc/namei.h b/include/asm-powerpc/namei.h
index 29c9ec832133..29c9ec832133 100644
--- a/include/asm-ppc/namei.h
+++ b/include/asm-powerpc/namei.h
diff --git a/include/asm-powerpc/percpu.h b/include/asm-powerpc/percpu.h
new file mode 100644
index 000000000000..06a959d67234
--- /dev/null
+++ b/include/asm-powerpc/percpu.h
@@ -0,0 +1 @@
+#include <asm-generic/percpu.h>
diff --git a/include/asm-ppc/poll.h b/include/asm-powerpc/poll.h
index be5024913c62..be5024913c62 100644
--- a/include/asm-ppc/poll.h
+++ b/include/asm-powerpc/poll.h
diff --git a/include/asm-powerpc/resource.h b/include/asm-powerpc/resource.h
new file mode 100644
index 000000000000..04bc4db8921b
--- /dev/null
+++ b/include/asm-powerpc/resource.h
@@ -0,0 +1 @@
+#include <asm-generic/resource.h>
diff --git a/include/asm-ppc64/sembuf.h b/include/asm-powerpc/sembuf.h
index 172e59000767..c98fc18fe805 100644
--- a/include/asm-ppc64/sembuf.h
+++ b/include/asm-powerpc/sembuf.h
@@ -1,27 +1,36 @@
-#ifndef _PPC64_SEMBUF_H
-#define _PPC64_SEMBUF_H
+#ifndef _POWERPC_SEMBUF_H
+#define _POWERPC_SEMBUF_H
 
-/* 
- * The semid64_ds structure for PPC architecture.
- *
- *
+/*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * The semid64_ds structure for PPC architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
  *
  * Pad space is left for:
- * - 2 miscellaneous 64-bit values
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
  */
 
 struct semid64_ds {
         struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
+#ifndef __powerpc64__
+        unsigned long   __unused1;
+#endif
         __kernel_time_t sem_otime;      /* last semop time */
+#ifndef __powerpc64__
+        unsigned long   __unused2;
+#endif
         __kernel_time_t sem_ctime;      /* last change time */
         unsigned long   sem_nsems;      /* no. of semaphores in array */
-
-        unsigned long   __unused1;
-        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
 };
 
-#endif /* _PPC64_SEMBUF_H */
+#endif /* _POWERPC_SEMBUF_H */
diff --git a/include/asm-ppc64/shmbuf.h b/include/asm-powerpc/shmbuf.h
index 02e99d6ec925..29632db3b178 100644
--- a/include/asm-ppc64/shmbuf.h
+++ b/include/asm-powerpc/shmbuf.h
@@ -1,31 +1,47 @@
-#ifndef _PPC64_SHMBUF_H
-#define _PPC64_SHMBUF_H
+#ifndef _POWERPC_SHMBUF_H
+#define _POWERPC_SHMBUF_H
 
-/* 
- * The shmid64_ds structure for PPC64 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 64-bit values
- *
+/*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
 
+/*
+ * The shmid64_ds structure for PPC architecture.
+ *
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
 struct shmid64_ds {
         struct ipc64_perm       shm_perm;       /* operation perms */
+#ifndef __power64__
+        unsigned long           __unused1;
+#endif
         __kernel_time_t         shm_atime;      /* last attach time */
+#ifndef __power64__
+        unsigned long           __unused2;
+#endif
         __kernel_time_t         shm_dtime;      /* last detach time */
+#ifndef __power64__
+        unsigned long           __unused3;
+#endif
         __kernel_time_t         shm_ctime;      /* last change time */
+#ifndef __power64__
+        unsigned long           __unused4;
+#endif
         size_t                  shm_segsz;      /* size of segment (bytes) */
         __kernel_pid_t          shm_cpid;       /* pid of creator */
         __kernel_pid_t          shm_lpid;       /* pid of last operator */
         unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused1;
-        unsigned long           __unused2;
+        unsigned long           __unused5;
+        unsigned long           __unused6;
 };
 
 struct shminfo64 {
@@ -40,4 +56,4 @@ struct shminfo64 {
         unsigned long   __unused4;
 };
 
-#endif /* _PPC64_SHMBUF_H */
+#endif /* _POWERPC_SHMBUF_H */
diff --git a/include/asm-ppc/shmparam.h b/include/asm-powerpc/shmparam.h
index d6250602ae64..d6250602ae64 100644
--- a/include/asm-ppc/shmparam.h
+++ b/include/asm-powerpc/shmparam.h
diff --git a/include/asm-ppc64/siginfo.h b/include/asm-powerpc/siginfo.h
index 3a7c23dcb5aa..ae70b8010b19 100644
--- a/include/asm-ppc64/siginfo.h
+++ b/include/asm-powerpc/siginfo.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_SIGINFO_H
-#define _PPC64_SIGINFO_H
+#ifndef _POWERPC_SIGINFO_H
+#define _POWERPC_SIGINFO_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -8,9 +8,11 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
-#define SI_PAD_SIZE32           ((SI_MAX_SIZE/sizeof(int)) - 3)
+#ifdef __powerpc64__
+#    define __ARCH_SI_PREAMBLE_SIZE     (4 * sizeof(int))
+#    define SI_PAD_SIZE32               ((SI_MAX_SIZE/sizeof(int)) - 3)
+#endif
 
 #include <asm-generic/siginfo.h>
 
-#endif /* _PPC64_SIGINFO_H */
+#endif /* _POWERPC_SIGINFO_H */
diff --git a/include/asm-ppc64/socket.h b/include/asm-powerpc/socket.h
index 59e00dfc8b8e..51a0cf5ee9f0 100644
--- a/include/asm-ppc64/socket.h
+++ b/include/asm-powerpc/socket.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
+#ifndef _POWERPC_SOCKET_H
+#define _POWERPC_SOCKET_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -10,7 +10,7 @@
 
 #include <asm/sockios.h>
 
-/* For setsockoptions(2) */
+/* For setsockopt(2) */
 #define SOL_SOCKET      1
 
 #define SO_DEBUG        1
@@ -21,6 +21,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
@@ -50,8 +52,8 @@
 #define SO_TIMESTAMP            29
 #define SCM_TIMESTAMP           SO_TIMESTAMP
 
-#define SO_ACCEPTCONN           30
+#define SO_ACCEPTCONN           30
 
-#define SO_PEERSEC             31
+#define SO_PEERSEC              31
 
-#endif /* _ASM_SOCKET_H */
+#endif /* _POWERPC_SOCKET_H */
diff --git a/include/asm-ppc64/sockios.h b/include/asm-powerpc/sockios.h
index 6bd1a22af4f6..ef7ff664167e 100644
--- a/include/asm-ppc64/sockios.h
+++ b/include/asm-powerpc/sockios.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC64_SOCKIOS_H
-#define _ASM_PPC64_SOCKIOS_H
+#ifndef _POWERPC_SOCKIOS_H
+#define _POWERPC_SOCKIOS_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -16,4 +16,4 @@
 #define SIOCATMARK      0x8905
 #define SIOCGSTAMP      0x8906          /* Get stamp */
 
-#endif /* _ASM_PPC64_SOCKIOS_H */
+#endif /* _POWERPC_SOCKIOS_H */
diff --git a/include/asm-ppc/string.h b/include/asm-powerpc/string.h
index 225575997392..225575997392 100644
--- a/include/asm-ppc/string.h
+++ b/include/asm-powerpc/string.h
diff --git a/include/asm-ppc64/termbits.h b/include/asm-powerpc/termbits.h
index d1a2bee10cef..2c5bf85a8c3c 100644
--- a/include/asm-ppc64/termbits.h
+++ b/include/asm-powerpc/termbits.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_TERMBITS_H
-#define _PPC64_TERMBITS_H
+#ifndef _POWERPC_TERMBITS_H
+#define _POWERPC_TERMBITS_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -8,8 +8,6 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#include <linux/posix_types.h>
-
 typedef unsigned char   cc_t;
 typedef unsigned int    speed_t;
 typedef unsigned int    tcflag_t;
@@ -190,4 +188,4 @@ struct termios {
 #define TCSADRAIN       1
 #define TCSAFLUSH       2
 
-#endif /* _PPC64_TERMBITS_H */
+#endif /* _POWERPC_TERMBITS_H */
diff --git a/include/asm-ppc64/termios.h b/include/asm-powerpc/termios.h
index 02c3d283aa62..237533bb0e9f 100644
--- a/include/asm-ppc64/termios.h
+++ b/include/asm-powerpc/termios.h
@@ -1,5 +1,5 @@
-#ifndef _PPC64_TERMIOS_H
-#define _PPC64_TERMIOS_H
+#ifndef _POWERPC_TERMIOS_H
+#define _POWERPC_TERMIOS_H
 
 /*
  * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
@@ -87,6 +87,7 @@ struct termio {
 #define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
 #define N_HDLC          13      /* synchronous HDLC */
 #define N_SYNC_PPP      14
+#define N_HCI           15  /* Bluetooth HCI UART */
 
 #ifdef __KERNEL__
 /*                   ^C  ^\ del  ^U  ^D   1   0   0   0   0  ^W  ^R  ^Z  ^Q  ^S  ^V  ^U  */
@@ -232,4 +233,4 @@ struct termio {
 
 #endif  /* __KERNEL__ */
 
-#endif  /* _PPC64_TERMIOS_H */
+#endif  /* _POWERPC_TERMIOS_H */
diff --git a/include/asm-ppc/unaligned.h b/include/asm-powerpc/unaligned.h
index 45520d9b85d1..45520d9b85d1 100644
--- a/include/asm-ppc/unaligned.h
+++ b/include/asm-powerpc/unaligned.h
diff --git a/include/asm-ppc/xor.h b/include/asm-powerpc/xor.h
index c82eb12a5b18..c82eb12a5b18 100644
--- a/include/asm-ppc/xor.h
+++ b/include/asm-powerpc/xor.h
diff --git a/include/asm-ppc/8253pit.h b/include/asm-ppc/8253pit.h
deleted file mode 100644
index 285f78488ccb..000000000000
--- a/include/asm-ppc/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE   1193182UL
-
-#endif
diff --git a/include/asm-ppc/auxvec.h b/include/asm-ppc/auxvec.h
new file mode 100644
index 000000000000..172358df29c8
--- /dev/null
+++ b/include/asm-ppc/auxvec.h
@@ -0,0 +1,14 @@
+#ifndef __PPC_AUXVEC_H
+#define __PPC_AUXVEC_H
+
+/*
+ * We need to put in some extra aux table entries to tell glibc what
+ * the cache block size is, so it can use the dcbz instruction safely.
+ */
+#define AT_DCACHEBSIZE          19
+#define AT_ICACHEBSIZE          20
+#define AT_UCACHEBSIZE          21
+/* A special ignored type value for PPC, for glibc compatibility.  */
+#define AT_IGNOREPPC            22
+
+#endif
diff --git a/include/asm-ppc/bugs.h b/include/asm-ppc/bugs.h
deleted file mode 100644
index 8dce1e290fd0..000000000000
--- a/include/asm-ppc/bugs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * This file is included by 'init/main.c'
- */
-
-extern void
-check_bugs(void);
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index c5883dbed63f..9483d4bfacf7 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -109,6 +109,7 @@ static inline long IS_DPERR(const uint offset)
  * and dual port ram.
  */
 extern          cpm_cpm2_t      *cpmp;   /* Pointer to comm processor */
+
 extern uint cpm_dpalloc(uint size, uint align);
 extern int cpm_dpfree(uint offset);
 extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
@@ -116,6 +117,8 @@ extern void cpm_dpdump(void);
 extern void *cpm_dpram_addr(uint offset);
 extern void cpm_setbrg(uint brg, uint rate);
 extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void cpm2_reset(void);
+
 
 /* Buffer descriptors used by many of the CPM protocols.
 */
@@ -1087,5 +1090,3 @@ typedef struct im_idma {
 
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
-
-
diff --git a/include/asm-ppc/cputime.h b/include/asm-ppc/cputime.h
deleted file mode 100644
index 8e9faf5ce720..000000000000
--- a/include/asm-ppc/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PPC_CPUTIME_H
-#define __PPC_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __PPC_CPUTIME_H */
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
index 7f0487afebbe..92b8ee78dcc2 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-ppc/dma-mapping.h
@@ -60,7 +60,8 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
 }
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                                       dma_addr_t * dma_handle, int gfp)
+                                       dma_addr_t * dma_handle,
+                                       unsigned int __nocast gfp)
 {
 #ifdef CONFIG_NOT_COHERENT_CACHE
         return __dma_alloc_coherent(size, dma_handle, gfp);
@@ -117,7 +118,7 @@ dma_map_page(struct device *dev, struct page *page,
 
         __dma_sync_page(page, offset, size, direction);
 
-        return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
+        return page_to_bus(page) + offset;
 }
 
 /* We do nothing. */
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
index 2c056966efd3..c25cc35e6ab5 100644
--- a/include/asm-ppc/elf.h
+++ b/include/asm-ppc/elf.h
@@ -7,6 +7,7 @@
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
+#include <asm/auxvec.h>
 
 /* PowerPC relocations defined by the ABIs */
 #define R_PPC_NONE              0
@@ -122,16 +123,6 @@ extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
 
 #define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
 
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE          19
-#define AT_ICACHEBSIZE          20
-#define AT_UCACHEBSIZE          21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC            22
-
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;
diff --git a/include/asm-ppc/fcntl.h b/include/asm-ppc/fcntl.h
deleted file mode 100644
index 5e28e41fb29f..000000000000
--- a/include/asm-ppc/fcntl.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef _PPC_FCNTL_H
-#define _PPC_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECTORY      040000 /* must be a directory */
-#define O_NOFOLLOW      0100000 /* don't follow links */
-#define O_LARGEFILE     0200000
-#define O_DIRECT        0400000 /* direct disk access hint */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-#ifdef __KERNEL__
-#define F_POSIX         1
-#define F_FLOCK         2
-#define F_BROKEN        4       /* broken flock() emulation */
-#endif /* __KERNEL__ */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-#endif
diff --git a/include/asm-ppc/fsl_ocp.h b/include/asm-ppc/fsl_ocp.h
deleted file mode 100644
index 050fbba8d049..000000000000
--- a/include/asm-ppc/fsl_ocp.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * include/asm-ppc/fsl_ocp.h
- *
- * Definitions for the on-chip peripherals on Freescale PPC processors
- *
- * Maintainer: Kumar Gala (kumar.gala@freescale.com)
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_FS_OCP_H__
-#define __ASM_FS_OCP_H__
-
-/* A table of information for supporting the Gianfar Ethernet Controller
- * This helps identify which enet controller we are dealing with,
- * and what type of enet controller it is
- */
-struct ocp_gfar_data {
-        uint interruptTransmit;
-        uint interruptError;
-        uint interruptReceive;
-        uint interruptPHY;
-        uint flags;
-        uint phyid;
-        uint phyregidx;
-        unsigned char mac_addr[6];
-};
-
-/* Flags in the flags field */
-#define GFAR_HAS_COALESCE               0x20
-#define GFAR_HAS_RMON                   0x10
-#define GFAR_HAS_MULTI_INTR             0x08
-#define GFAR_FIRM_SET_MACADDR           0x04
-#define GFAR_HAS_PHY_INTR               0x02    /* if not set use a timer */
-#define GFAR_HAS_GIGABIT                0x01
-
-/* Data structure for I2C support.  Just contains a couple flags
- * to distinguish various I2C implementations*/
-struct ocp_fs_i2c_data {
-        uint flags;
-};
-
-/* Flags for I2C */
-#define FS_I2C_SEPARATE_DFSRR   0x02
-#define FS_I2C_CLOCK_5200       0x01
-
-#endif  /* __ASM_FS_OCP_H__ */
-#endif  /* __KERNEL__ */
diff --git a/include/asm-ppc/futex.h b/include/asm-ppc/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-ppc/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-ppc/hdreg.h b/include/asm-ppc/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-ppc/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9d..e5374be86aef 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
 #define PPC44x_LOW_SLOT         63
 
 /* LS 32-bits of UART0 physical address location for early serial text debug */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define UART0_PHYS_IO_BASE      0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE      0xe0000000
 #else
 #define UART0_PHYS_IO_BASE      0x40000200
 #endif
@@ -49,11 +51,16 @@
 /*
  * Standard 4GB "page" definitions
  */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define PPC44x_IO_PAGE          0x0000000100000000ULL
 #define PPC44x_PCICFG_PAGE      0x0000000900000000ULL
 #define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
 #define PPC44x_PCIMEM_PAGE      0x0000000a00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE          0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE      0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE      0x0000000000000000ULL
 #else
 #define PPC44x_IO_PAGE          0x0000000100000000ULL
 #define PPC44x_PCICFG_PAGE      0x0000000200000000ULL
@@ -64,7 +71,7 @@
 /*
  * 36-bit trap ranges
  */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define PPC44x_IO_LO            0xf0000000UL
 #define PPC44x_IO_HI            0xf0000fffUL
 #define PPC44x_PCI0CFG_LO       0x0ec00000UL
@@ -75,6 +82,13 @@
 #define PPC44x_PCI2CFG_HI       0x2ec00007UL
 #define PPC44x_PCIMEM_LO        0x80000000UL
 #define PPC44x_PCIMEM_HI        0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO            0xef500000UL
+#define PPC44x_IO_HI            0xefffffffUL
+#define PPC44x_PCI0CFG_LO       0xeec00000UL
+#define PPC44x_PCI0CFG_HI       0xeecfffffUL
+#define PPC44x_PCIMEM_LO        0xa0000000UL
+#define PPC44x_PCIMEM_HI        0xdfffffffUL
 #else
 #define PPC44x_IO_LO            0x40000000UL
 #define PPC44x_IO_HI            0x40000fffUL
@@ -152,6 +166,12 @@
 #define DCRN_SDR_UART0          0x0120
 #define DCRN_SDR_UART1          0x0121
 
+#ifdef CONFIG_440EP
+#define DCRN_SDR_UART2          0x0122
+#define DCRN_SDR_UART3          0x0123
+#define DCRN_SDR_CUST0          0x4000
+#endif
+
 /* SDR read/write helper macros */
 #define SDR_READ(offset) ({\
         mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
 #define DCRNCAP_DMA_SG          1       /* have DMA scatter/gather capability */
 #define DCRN_MAL_BASE           0x180
 
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE       0x300
+#define DCRN_DMA2P41_BASE       0x308
+#define DCRN_DMA2P42_BASE       0x310
+#define DCRN_DMA2P43_BASE       0x318
+#define DCRN_DMA2P4SR_BASE      0x320
+#endif
+
 /* UIC */
 #define DCRN_UIC0_BASE  0xc0
 #define DCRN_UIC1_BASE  0xd0
@@ -395,11 +423,7 @@
 #define MQ0_CONFIG_SIZE_2G              0x0000c000
 
 /* Internal SRAM Controller 440GX/440SP */
-#ifdef CONFIG_440SP
-#define DCRN_SRAM0_BASE         0x100
-#else /* 440GX */
 #define DCRN_SRAM0_BASE         0x000
-#endif
 
 #define DCRN_SRAM0_SB0CR        (DCRN_SRAM0_BASE + 0x020)
 #define DCRN_SRAM0_SB1CR        (DCRN_SRAM0_BASE + 0x021)
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 35260afa33a9..e992369cb8e9 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -19,10 +19,6 @@
 
 #ifdef CONFIG_40x
 
-#if defined(CONFIG_ASH)
-#include <platforms/4xx/ash.h>
-#endif
-
 #if defined(CONFIG_BUBINGA)
 #include <platforms/4xx/bubinga.h>
 #endif
@@ -35,14 +31,6 @@
 #include <platforms/4xx/ep405.h>
 #endif
 
-#if defined(CONFIG_OAK)
-#include <platforms/4xx/oak.h>
-#endif
-
-#if defined(CONFIG_REDWOOD_4)
-#include <platforms/4xx/redwood.h>
-#endif
-
 #if defined(CONFIG_REDWOOD_5)
 #include <platforms/4xx/redwood5.h>
 #endif
@@ -97,6 +85,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
 
 #elif CONFIG_44x
 
+#if defined(CONFIG_BAMBOO)
+#include <platforms/4xx/bamboo.h>
+#endif
+
 #if defined(CONFIG_EBONY)
 #include <platforms/4xx/ebony.h>
 #endif
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
index 8c61d93043af..6f10a25bd628 100644
--- a/include/asm-ppc/ibm_ocp.h
+++ b/include/asm-ppc/ibm_ocp.h
@@ -67,10 +67,13 @@ struct ocp_func_emac_data {
         int     phy_mode;       /* PHY type or configurable mode */
         u8      mac_addr[6];    /* EMAC mac address */
         u32     phy_map;        /* EMAC phy map */
+        u32     phy_feat_exc;   /* Excluded PHY features */
 };
 
 /* Sysfs support */
 #define OCP_SYSFS_EMAC_DATA()                                           \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx)     \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux)     \
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)      \
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)      \
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)       \
@@ -78,9 +81,15 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)   \
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)       \
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)      \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)       \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)      \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)   \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
                                                                         \
 void ocp_show_emac_data(struct device *dev)                             \
 {                                                                       \
+        device_create_file(dev, &dev_attr_emac_rgmii_idx);              \
+        device_create_file(dev, &dev_attr_emac_rgmii_mux);              \
         device_create_file(dev, &dev_attr_emac_zmii_idx);               \
         device_create_file(dev, &dev_attr_emac_zmii_mux);               \
         device_create_file(dev, &dev_attr_emac_mal_idx);                \
@@ -88,8 +97,25 @@ void ocp_show_emac_data(struct device *dev)				\
         device_create_file(dev, &dev_attr_emac_mal_tx_chan);            \
         device_create_file(dev, &dev_attr_emac_wol_irq);                \
         device_create_file(dev, &dev_attr_emac_mdio_idx);               \
+        device_create_file(dev, &dev_attr_emac_tah_idx);                \
+        device_create_file(dev, &dev_attr_emac_phy_mode);               \
+        device_create_file(dev, &dev_attr_emac_phy_map);                \
+        device_create_file(dev, &dev_attr_emac_phy_feat_exc);           \
 }
 
+/*
+ * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
+ */
+#define PHY_MODE_NA     0
+#define PHY_MODE_MII    1
+#define PHY_MODE_RMII   2
+#define PHY_MODE_SMII   3
+#define PHY_MODE_RGMII  4
+#define PHY_MODE_TBI    5
+#define PHY_MODE_GMII   6
+#define PHY_MODE_RTBI   7
+#define PHY_MODE_SGMII  8
+
 #ifdef CONFIG_40x
 /*
  * Helper function to copy MAC addresses from the bd_t to OCP EMAC
@@ -123,6 +149,7 @@ struct ocp_func_mal_data {
         int     txde_irq;       /* TX Descriptor Error IRQ */
         int     rxde_irq;       /* RX Descriptor Error IRQ */
         int     serr_irq;       /* MAL System Error IRQ    */
+        int     dcr_base;       /* MALx_CFG DCR number   */
 };
 
 #define OCP_SYSFS_MAL_DATA()                                            \
@@ -133,6 +160,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq)	\
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)        \
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)        \
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)        \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base)        \
                                                                         \
 void ocp_show_mal_data(struct device *dev)                              \
 {                                                                       \
@@ -143,6 +171,7 @@ void ocp_show_mal_data(struct device *dev)				\
         device_create_file(dev, &dev_attr_mal_txde_irq);                \
         device_create_file(dev, &dev_attr_mal_rxde_irq);                \
         device_create_file(dev, &dev_attr_mal_serr_irq);                \
+        device_create_file(dev, &dev_attr_mal_dcr_base);                \
 }
 
 /*
@@ -157,7 +186,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)	\
                                                                         \
 void ocp_show_iic_data(struct device *dev)                              \
 {                                                                       \
-        device_create_file(dev, &dev_attr_iic_fast_mode);                       \
+        device_create_file(dev, &dev_attr_iic_fast_mode);               \
 }
 #endif /* __IBM_OCP_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 06b86be61ed1..b4b270457edd 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -19,6 +19,11 @@
 #define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
 #define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
 
+/*
+ * IRQ line status macro IRQ_PER_CPU is used
+ */
+#define ARCH_HAS_IRQ_PER_CPU
+
 #if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 
@@ -176,7 +181,7 @@ static __inline__ int irq_canonicalize(int irq)
 */
 #include <asm/mpc85xx.h>
 
-/* The MPC8560 openpic has  32 internal interrupts and 12 external
+/* The MPC8548 openpic has 48 internal interrupts and 12 external
  * interrupts.
  *
  * We are "flattening" the interrupt vectors of the cascaded CPM
@@ -184,7 +189,7 @@ static __inline__ int irq_canonicalize(int irq)
  * single integer.
  */
 #define NR_CPM_INTS     64
-#define NR_EPIC_INTS    44
+#define NR_EPIC_INTS    60
 #ifndef NR_8259_INTS
 #define NR_8259_INTS    0
 #endif
@@ -223,9 +228,15 @@ static __inline__ int irq_canonicalize(int irq)
 #define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_TX    (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_RX    (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_TX    (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_RX    (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
@@ -235,18 +246,18 @@ static __inline__ int irq_canonicalize(int irq)
 #define MPC85xx_IRQ_CPM         (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
 
 /* The 12 external interrupt lines */
-#define MPC85xx_IRQ_EXT0        (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT1        (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT2        (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT3        (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT4        (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT5        (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT6        (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT7        (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT8        (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT9        (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT10       (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
-#define MPC85xx_IRQ_EXT11       (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT0        (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT1        (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT2        (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT3        (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT4        (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT5        (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT6        (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT7        (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT8        (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT9        (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT10       (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT11       (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
 
 /* CPM related interrupts */
 #define SIU_INT_ERROR           ((uint)0x00+CPM_IRQ_OFFSET)
@@ -331,6 +342,7 @@ static __inline__ int irq_canonicalize(int irq)
 #define SIU_INT_IDMA3           ((uint)0x08 + CPM_IRQ_OFFSET)
 #define SIU_INT_IDMA4           ((uint)0x09 + CPM_IRQ_OFFSET)
 #define SIU_INT_SDMA            ((uint)0x0a + CPM_IRQ_OFFSET)
+#define SIU_INT_USB             ((uint)0x0b + CPM_IRQ_OFFSET)
 #define SIU_INT_TIMER1          ((uint)0x0c + CPM_IRQ_OFFSET)
 #define SIU_INT_TIMER2          ((uint)0x0d + CPM_IRQ_OFFSET)
 #define SIU_INT_TIMER3          ((uint)0x0e + CPM_IRQ_OFFSET)
diff --git a/include/asm-ppc/kexec.h b/include/asm-ppc/kexec.h
new file mode 100644
index 000000000000..6d2aa0aa4642
--- /dev/null
+++ b/include/asm-ppc/kexec.h
@@ -0,0 +1,40 @@
+#ifndef _PPC_KEXEC_H
+#define _PPC_KEXEC_H
+
+#ifdef CONFIG_KEXEC
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
+ * calculation for the amount of memory directly mappable into the
+ * kernel memory space.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_PPC
+
+#ifndef __ASSEMBLY__
+
+extern void *crash_notes;
+
+struct kimage;
+
+extern void machine_kexec_simple(struct kimage *image);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_KEXEC */
+
+#endif /* _PPC_KEXEC_H */
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
index 2589f182a6ad..6d6fc78731e5 100644
--- a/include/asm-ppc/kmap_types.h
+++ b/include/asm-ppc/kmap_types.h
@@ -17,6 +17,7 @@ enum km_type {
         KM_SOFTIRQ0,
         KM_SOFTIRQ1,
         KM_PPC_SYNC_PAGE,
+        KM_PPC_SYNC_ICACHE,
         KM_TYPE_NR
 };
 
diff --git a/include/asm-ppc/local.h b/include/asm-ppc/local.h
deleted file mode 100644
index b08e3eced10e..000000000000
--- a/include/asm-ppc/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PPC_LOCAL_H
-#define __PPC_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* __PPC_LOCAL_H */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index b78d40870c95..1d4ab70a56f3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -4,6 +4,7 @@
 
 #include <linux/config.h>
 #include <linux/init.h>
+#include <linux/kexec.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -114,6 +115,36 @@ struct machdep_calls {
         /* functions for dealing with other cpus */
         struct smp_ops_t *smp_ops;
 #endif /* CONFIG_SMP */
+
+#ifdef CONFIG_KEXEC
+        /* Called to shutdown machine specific hardware not already controlled
+         * by other drivers.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_shutdown)(void);
+
+        /* Called to do the minimal shutdown needed to run a kexec'd kernel
+         * to run successfully.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_crash_shutdown)(void);
+
+        /* Called to do what every setup is needed on image and the
+         * reboot code buffer. Returns 0 on success.
+         * Provide your own (maybe dummy) implementation if your platform
+         * claims to support kexec.
+         */
+        int (*machine_kexec_prepare)(struct kimage *image);
+
+        /* Called to handle any machine specific cleanup on image */
+        void (*machine_kexec_cleanup)(struct kimage *image);
+
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
+#endif /* CONFIG_KEXEC */
 };
 
 extern struct machdep_calls ppc_md;
diff --git a/include/asm-ppc/macio.h b/include/asm-ppc/macio.h
index 2cafc9978607..a481b772d154 100644
--- a/include/asm-ppc/macio.h
+++ b/include/asm-ppc/macio.h
@@ -1,6 +1,7 @@
 #ifndef __MACIO_ASIC_H__
 #define __MACIO_ASIC_H__
 
+#include <linux/mod_devicetable.h>
 #include <asm/of_device.h>
 
 extern struct bus_type macio_bus_type;
@@ -120,10 +121,10 @@ static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
 struct macio_driver
 {
         char                    *name;
-        struct of_match         *match_table;
+        struct of_device_id     *match_table;
         struct module           *owner;
 
-        int     (*probe)(struct macio_dev* dev, const struct of_match *match);
+        int     (*probe)(struct macio_dev* dev, const struct of_device_id *match);
         int     (*remove)(struct macio_dev* dev);
 
         int     (*suspend)(struct macio_dev* dev, pm_message_t state);
diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h
deleted file mode 100644
index 227018b2fef8..000000000000
--- a/include/asm-ppc/mc146818rtc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_MC146818RTC_H
-#define __ASM_PPC_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#define RTC_IRQ 8
-
-#endif /* __ASM_PPC_MC146818RTC_H */
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mman.h b/include/asm-ppc/mman.h
deleted file mode 100644
index 5fd19fd4936c..000000000000
--- a/include/asm-ppc/mman.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __PPC_MMAN_H__
-#define __PPC_MMAN_H__
-
-#define PROT_READ       0x1             /* page can be read */
-#define PROT_WRITE      0x2             /* page can be written */
-#define PROT_EXEC       0x4             /* page can be executed */
-#define PROT_SEM        0x8             /* page may be used for atomic ops */
-#define PROT_NONE       0x0             /* page can not be accessed */
-#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
-
-#define MAP_SHARED      0x01            /* Share changes */
-#define MAP_PRIVATE     0x02            /* Changes are private */
-#define MAP_TYPE        0x0f            /* Mask for type of mapping */
-#define MAP_FIXED       0x10            /* Interpret addr exactly */
-#define MAP_ANONYMOUS   0x20            /* don't use a file */
-#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
-#define MAP_NORESERVE   0x40            /* don't reserve swap pages */
-#define MAP_LOCKED      0x80
-
-#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
-#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
-#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
-#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x10000         /* do not block on IO */
-
-#define MS_ASYNC        1               /* sync memory asynchronously */
-#define MS_INVALIDATE   2               /* invalidate the caches */
-#define MS_SYNC         4               /* synchronous memory sync */
-
-#define MCL_CURRENT     0x2000          /* lock all currently mapped pages */
-#define MCL_FUTURE      0x4000          /* lock all additions to address space */
-
-#define MADV_NORMAL     0x0             /* default page-in behavior */
-#define MADV_RANDOM     0x1             /* page-in minimum required */
-#define MADV_SEQUENTIAL 0x2             /* read-ahead aggressively */
-#define MADV_WILLNEED   0x3             /* pre-fault pages */
-#define MADV_DONTNEED   0x4             /* discard these pages */
-
-/* compatibility flags */
-#define MAP_ANON        MAP_ANONYMOUS
-#define MAP_FILE        0
-
-#endif /* __PPC_MMAN_H__ */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index d465aee1c82e..9205db404c7a 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -405,7 +405,7 @@ typedef struct _P601_BAT {
 
 #define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
 #define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
-#define MAS0_NV         0x00000FFF
+#define MAS0_NV(x)      ((x) & 0x00000FFF)
 
 #define MAS1_VALID      0x80000000
 #define MAS1_IPROT      0x40000000
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index 9222fa6ca172..afe26ffc2e2d 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -63,7 +63,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 #define LAST_CONTEXT            255
 #define FIRST_CONTEXT           1
 
-#elif defined(CONFIG_E500)
+#elif defined(CONFIG_E200) || defined(CONFIG_E500)
 #define NO_CONTEXT              256
 #define LAST_CONTEXT            255
 #define FIRST_CONTEXT           1
@@ -149,6 +149,7 @@ static inline void get_mmu_context(struct mm_struct *mm)
  */
 static inline void destroy_context(struct mm_struct *mm)
 {
+        preempt_disable();
         if (mm->context != NO_CONTEXT) {
                 clear_bit(mm->context, context_map);
                 mm->context = NO_CONTEXT;
@@ -156,6 +157,7 @@ static inline void destroy_context(struct mm_struct *mm)
                 atomic_inc(&nr_free_contexts);
 #endif
         }
+        preempt_enable();
 }
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
diff --git a/include/asm-ppc/module.h b/include/asm-ppc/module.h
deleted file mode 100644
index fb63492562b0..000000000000
--- a/include/asm-ppc/module.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef _ASM_PPC_MODULE_H
-#define _ASM_PPC_MODULE_H
-/* Module stuff for PPC.  (C) 2001 Rusty Russell */
-
-#include <linux/list.h>
-#include <asm/bug.h>
-
-/* Thanks to Paul M for explaining this.
-
-   PPC can only do rel jumps += 32MB, and often the kernel and other
-   modules are furthur away than this.  So, we jump to a table of
-   trampolines attached to the module (the Procedure Linkage Table)
-   whenever that happens.
-*/
-
-struct ppc_plt_entry
-{
-        /* 16 byte jump instruction sequence (4 instructions) */
-        unsigned int jump[4];
-};
-
-struct mod_arch_specific
-{
-        /* Indices of PLT sections within module. */
-        unsigned int core_plt_section, init_plt_section;
-
-        /* List of BUG addresses, source line numbers and filenames */
-        struct list_head bug_list;
-        struct bug_entry *bug_table;
-        unsigned int num_bugs;
-};
-
-extern struct bug_entry *module_find_bug(unsigned long bugaddr);
-
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-
-/* Make empty sections for module_frob_arch_sections to expand. */
-#ifdef MODULE
-asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
-asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
-#endif
-#endif /* _ASM_PPC_MODULE_H */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
index d8e7e2d6128e..77b1e092c206 100644
--- a/include/asm-ppc/mpc10x.h
+++ b/include/asm-ppc/mpc10x.h
@@ -159,6 +159,13 @@ extern unsigned long			ioremap_base;
 #define MPC10X_MAPA_EUMB_BASE           (ioremap_base - MPC10X_EUMB_SIZE)
 #define MPC10X_MAPB_EUMB_BASE           MPC10X_MAPA_EUMB_BASE
 
+enum ppc_sys_devices {
+        MPC10X_IIC1,
+        MPC10X_DMA0,
+        MPC10X_DMA1,
+        MPC10X_UART0,
+        MPC10X_UART1,
+};
 
 int mpc10x_bridge_init(struct pci_controller *hose,
                        uint current_map,
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index 89eb8a2ac693..9694eca16e92 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -67,6 +67,24 @@
 #define IO_VIRT_ADDR    IO_PHYS_ADDR
 #endif
 
+enum ppc_sys_devices {
+        MPC82xx_CPM_FCC1,
+        MPC82xx_CPM_FCC2,
+        MPC82xx_CPM_FCC3,
+        MPC82xx_CPM_I2C,
+        MPC82xx_CPM_SCC1,
+        MPC82xx_CPM_SCC2,
+        MPC82xx_CPM_SCC3,
+        MPC82xx_CPM_SCC4,
+        MPC82xx_CPM_SPI,
+        MPC82xx_CPM_MCC1,
+        MPC82xx_CPM_MCC2,
+        MPC82xx_CPM_SMC1,
+        MPC82xx_CPM_SMC2,
+        MPC82xx_CPM_USB,
+        MPC82xx_SEC1,
+};
+
 #ifndef __ASSEMBLY__
 /* The "residual" data board information structure the boot loader
  * hands to us.
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 22713e331585..516984ee14b5 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -25,7 +25,7 @@
 #ifdef CONFIG_MPC8540_ADS
 #include <platforms/85xx/mpc8540_ads.h>
 #endif
-#ifdef CONFIG_MPC8555_CDS
+#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
 #include <platforms/85xx/mpc8555_cds.h>
 #endif
 #ifdef CONFIG_MPC8560_ADS
@@ -74,7 +74,7 @@ extern unsigned char __res[];
 #define MPC85xx_GUTS_OFFSET     (0xe0000)
 #define MPC85xx_GUTS_SIZE       (0x01000)
 #define MPC85xx_IIC1_OFFSET     (0x03000)
-#define MPC85xx_IIC1_SIZE       (0x01000)
+#define MPC85xx_IIC1_SIZE       (0x00100)
 #define MPC85xx_OPENPIC_OFFSET  (0x40000)
 #define MPC85xx_OPENPIC_SIZE    (0x40000)
 #define MPC85xx_PCI1_OFFSET     (0x08000)
@@ -127,8 +127,64 @@ enum ppc_sys_devices {
         MPC85xx_CPM_MCC2,
         MPC85xx_CPM_SMC1,
         MPC85xx_CPM_SMC2,
+        MPC85xx_eTSEC1,
+        MPC85xx_eTSEC2,
+        MPC85xx_eTSEC3,
+        MPC85xx_eTSEC4,
+        MPC85xx_IIC2,
 };
 
+/* Internal interrupts are all Level Sensitive, and Positive Polarity */
+#define MPC85XX_INTERNAL_IRQ_SENSES \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46 */       \
+        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE)       /* Internal 47 */
+
 #endif /* CONFIG_85xx */
 #endif /* __ASM_MPC85xx_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index 714d69c819d3..dc8e59896050 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -36,10 +36,6 @@
 #include <platforms/tqm8xx.h>
 #endif
 
-#if defined(CONFIG_SPD823TS)
-#include <platforms/spd8xx.h>
-#endif
-
 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 #include <platforms/ivms8.h>
 #endif
@@ -68,6 +64,10 @@
 #include <platforms/lantec.h>
 #endif
 
+#if defined(CONFIG_MPC885ADS)
+#include <platforms/mpc885ads.h>
+#endif
+
 /* Currently, all 8xx boards that support a processor to PCI/ISA bridge
  * use the same memory map.
  */
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
index cc25b921ad4f..835930d6faa1 100644
--- a/include/asm-ppc/mv64x60.h
+++ b/include/asm-ppc/mv64x60.h
@@ -278,6 +278,13 @@ mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
 #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
 #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
 
+#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
+#define MV64XXX_DEV_NAME        "mv64xxx"
+
+struct mv64xxx_pdata {
+        u32     hs_reg_valid;
+};
+#endif
 
 /* Externally visible function prototypes */
 int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
index 2f428746c02b..f8f7f16b9b53 100644
--- a/include/asm-ppc/mv64x60_defs.h
+++ b/include/asm-ppc/mv64x60_defs.h
@@ -333,7 +333,7 @@
 /*
  *****************************************************************************
  *
- *      SRAM Cotnroller Registers
+ *      SRAM Controller Registers
  *
  *****************************************************************************
  */
@@ -352,7 +352,7 @@
 /*
  *****************************************************************************
  *
- *      SDRAM/MEM Cotnroller Registers
+ *      SDRAM/MEM Controller Registers
  *
  *****************************************************************************
  */
@@ -375,6 +375,7 @@
 /* SDRAM Control Registers */
 #define MV64360_D_UNIT_CONTROL_LOW              0x1404
 #define MV64360_D_UNIT_CONTROL_HIGH             0x1424
+#define MV64460_D_UNIT_MMASK                    0x14b0
 
 /* SDRAM Error Report Registers (64360) */
 #define MV64360_SDRAM_ERR_DATA_LO               0x1444
@@ -388,7 +389,7 @@
 /*
  *****************************************************************************
  *
- *      Device/BOOT Cotnroller Registers
+ *      Device/BOOT Controller Registers
  *
  *****************************************************************************
  */
@@ -680,6 +681,8 @@
 #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP         0x0dec
 #define MV64x60_PCI1_SLAVE_CPU_REMAP            0x0df0
 
+#define MV64360_PCICFG_CPCI_HOTSWAP             0x68
+
 /*
  *****************************************************************************
  *
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
index b98db3cdae83..983116f59d90 100644
--- a/include/asm-ppc/ocp.h
+++ b/include/asm-ppc/ocp.h
@@ -189,7 +189,7 @@ extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg),
 /* Sysfs support */
 #define OCP_SYSFS_ADDTL(type, format, name, field)                      \
 static ssize_t                                                          \
-show_##name##_##field(struct device *dev, char *buf)                    \
+show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf)                     \
 {                                                                       \
         struct ocp_device *odev = to_ocp_dev(dev);                      \
         type *add = odev->def->additions;                               \
@@ -202,10 +202,6 @@ static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
 #include <asm/ibm_ocp.h>
 #endif
 
-#ifdef CONFIG_FSL_OCP
-#include <asm/fsl_ocp.h>
-#endif
-
 #endif                          /* CONFIG_PPC_OCP */
 #endif                          /* __OCP_H__ */
 #endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/of_device.h b/include/asm-ppc/of_device.h
index 7229735a7c18..4b264cfd3998 100644
--- a/include/asm-ppc/of_device.h
+++ b/include/asm-ppc/of_device.h
@@ -24,20 +24,8 @@ struct of_device
 };
 #define to_of_device(d) container_of(d, struct of_device, dev)
 
-/*
- * Struct used for matching a device
- */
-struct of_match
-{
-        char    *name;
-        char    *type;
-        char    *compatible;
-        void    *data;
-};
-#define OF_ANY_MATCH            ((char *)-1L)
-
-extern const struct of_match *of_match_device(
-        const struct of_match *matches, const struct of_device *dev);
+extern const struct of_device_id *of_match_device(
+        const struct of_device_id *matches, const struct of_device *dev);
 
 extern struct of_device *of_dev_get(struct of_device *dev);
 extern void of_dev_put(struct of_device *dev);
@@ -49,10 +37,10 @@ extern void of_dev_put(struct of_device *dev);
 struct of_platform_driver
 {
         char                    *name;
-        struct of_match         *match_table;
+        struct of_device_id     *match_table;
         struct module           *owner;
 
-        int     (*probe)(struct of_device* dev, const struct of_match *match);
+        int     (*probe)(struct of_device* dev, const struct of_device_id *match);
         int     (*remove)(struct of_device* dev);
 
         int     (*suspend)(struct of_device* dev, pm_message_t state);
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
index dbe853319741..7848aa610c05 100644
--- a/include/asm-ppc/open_pic.h
+++ b/include/asm-ppc/open_pic.h
@@ -25,6 +25,11 @@
 #define OPENPIC_VEC_IPI         118     /* and up */
 #define OPENPIC_VEC_SPURIOUS    255
 
+/* Priorities */
+#define OPENPIC_PRIORITY_IPI_BASE       10
+#define OPENPIC_PRIORITY_DEFAULT        4
+#define OPENPIC_PRIORITY_NMI            9
+
 /* OpenPIC IRQ controller structure */
 extern struct hw_interrupt_type open_pic;
 
@@ -42,6 +47,7 @@ extern int epic_serial_mode;
 extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
 extern void openpic_init(int linux_irq_offset);
 extern void openpic_init_nmi_irq(u_int irq);
+extern void openpic_set_irq_priority(u_int irq, u_int pri);
 extern void openpic_hookup_cascade(u_int irq, char *name,
                                    int (*cascade_fn)(struct pt_regs *));
 extern u_int openpic_irq(void);
diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h
index b24a4e37196a..6198b1657a45 100644
--- a/include/asm-ppc/param.h
+++ b/include/asm-ppc/param.h
@@ -1,8 +1,10 @@
 #ifndef _ASM_PPC_PARAM_H
 #define _ASM_PPC_PARAM_H
 
+#include <linux/config.h>
+
 #ifdef __KERNEL__
-#define HZ              1000            /* internal timer frequency */
+#define HZ              CONFIG_HZ       /* internal timer frequency */
 #define USER_HZ         100             /* for user interfaces in "ticks" */
 #define CLOCKS_PER_SEC  (USER_HZ)       /* frequency at which times() counts */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
index fa9cbb67ce3e..8f994f9f8857 100644
--- a/include/asm-ppc/pc_serial.h
+++ b/include/asm-ppc/pc_serial.h
@@ -35,93 +35,9 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#define HUB6_FLAGS 0
-#endif
-        
-/*
- * The following define the access methods for the HUB6 card. All
- * access is through two ports for all 24 possible chips. The card is
- * selected through the high 2 bits, the port on that card with the
- * "middle" 3 bits, and the register on that port with the bottom
- * 3 bits.
- *
- * While the access port and interrupt is configurable, the default
- * port locations are 0x302 for the port control register, and 0x303
- * for the data read/write register. Normally, the interrupt is at irq3
- * but can be anything from 3 to 7 inclusive. Note that using 3 will
- * require disabling com2.
- */
-
-#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
-
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif
-
-/* You can have up to four HUB6's in the system, but I've only
- * included two cards here for a total of twelve ports.
- */
-#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
-#define HUB6_SERIAL_PORT_DFNS           \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
-#else
-#define HUB6_SERIAL_PORT_DFNS
-#endif
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS         \
-        HUB6_SERIAL_PORT_DFNS
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index ce5ae6d048f5..a811e440c978 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -37,7 +37,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-extern inline void pcibios_penalize_isa_irq(int irq)
+extern inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -69,6 +69,16 @@ extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 /*
  * At present there are very few 32-bit PPC machines that can have
  * memory above the 4GB point, and we don't support that.
@@ -95,6 +105,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                         struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
+
 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 
 struct file;
@@ -103,6 +117,12 @@ extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
                                          unsigned long size,
                                          pgprot_t prot);
 
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
+                                 const struct resource *rsrc,
+                                 u64 *start, u64 *end);
+
+
 #endif  /* __KERNEL__ */
 
 #endif /* __PPC_PCI_H */
diff --git a/include/asm-ppc/percpu.h b/include/asm-ppc/percpu.h
deleted file mode 100644
index d66667cd5878..000000000000
--- a/include/asm-ppc/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_PPC_PERCPU__
-#define __ARCH_PPC_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_PPC_PERCPU__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index a38606d15549..92f30b28b252 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base;
  *
  * Note that these bits preclude future use of a page size
  * less than 4KB.
+ *
+ *
+ * PPC 440 core has following TLB attribute fields;
+ *
+ *   TLB1:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   RPN.................................  -  -  -  -  -  - ERPN.......
+ *
+ *   TLB2:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
+ *
+ * There are some constrains and options, to decide mapping software bits
+ * into TLB entry.
+ *
+ *   - PRESENT *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - FILE *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
+ *     doesn't support SMP. So we can use this as software bit, like
+ *     DIRTY.
+ *
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
+ * above bits.  Note that the bit values are CPU specific, not architecture
+ * specific.
+ *
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
+ *
+ * There are three protection bits available for SWAP entry:
+ *      _PAGE_PRESENT
+ *      _PAGE_FILE
+ *      _PAGE_HASHPTE (if HW has)
+ *
+ * So those three bits have to be inside of 0-2nd LSB of PTE.
+ *
  */
+
 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 #define _PAGE_RW        0x00000002              /* S: Write permission */
-#define _PAGE_DIRTY     0x00000004              /* S: Page dirty */
+#define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 #define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
 #define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
 #define _PAGE_USER      0x00000040              /* S: User page */
 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
-#define _PAGE_COHERENT  0x00000200              /* H: M bit */
-#define _PAGE_FILE      0x00000400              /* S: nonlinear file mapping */
+#define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 
@@ -267,8 +313,6 @@ extern unsigned long ioremap_bot, ioremap_base;
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
 
-#define NUM_TLBCAMS     (16)
-
 #elif defined(CONFIG_8xx)
 /* Definitions for 8xx embedded chips. */
 #define _PAGE_PRESENT   0x0001  /* Page is valid */
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h
index 8beb162873f4..e9683bcff19b 100644
--- a/include/asm-ppc/pmac_feature.h
+++ b/include/asm-ppc/pmac_feature.h
@@ -32,6 +32,7 @@
 #define __PPC_ASM_PMAC_FEATURE_H
 
 #include <asm/macio.h>
+#include <asm/machdep.h>
 
 /*
  * Known Mac motherboard models
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h
index 8636cdbf6f8f..a415001165fa 100644
--- a/include/asm-ppc/ppc4xx_dma.h
+++ b/include/asm-ppc/ppc4xx_dma.h
@@ -285,7 +285,7 @@ typedef uint32_t sgl_handle_t;
 
 #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
 
-#elif defined(CONFIG_STBXXX_DMA)                /* stb03xxx */
+#elif defined(CONFIG_STB03xxx)          /* stb03xxx */
 
 #define DMA_PPC4xx_SIZE 4096
 
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index 13fa8e7483c1..bb53e2def363 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -174,6 +174,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define CLR_TOP32(r)
 #endif /* CONFIG_PPC64BRIDGE */
 
+#define RFCI            .long 0x4c000066        /* rfci instruction */
+#define RFDI            .long 0x4c00004e        /* rfdi instruction */
 #define RFMCI           .long 0x4c00004c        /* rfmci instruction */
 
 #ifdef CONFIG_IBM405_ERR77
@@ -184,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define PPC405_ERR77_SYNC
 #endif
 
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
 /* The boring bits... */
 
 /* Condition Register Bit Fields */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 24b991c42769..048f7c8596ee 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -21,12 +21,16 @@
 #include <linux/device.h>
 #include <linux/types.h>
 
-#if defined(CONFIG_83xx)
+#if defined(CONFIG_8260)
+#include <asm/mpc8260.h>
+#elif defined(CONFIG_83xx)
 #include <asm/mpc83xx.h>
 #elif defined(CONFIG_85xx)
 #include <asm/mpc85xx.h>
 #elif defined(CONFIG_PPC_MPC52xx)
 #include <asm/mpc52xx.h>
+#elif defined(CONFIG_MPC10X_BRIDGE)
+#include <asm/mpc10x.h>
 #else
 #error "need definition of ppc_sys_devices"
 #endif
@@ -48,6 +52,7 @@ extern struct ppc_sys_spec *cur_ppc_sys_spec;
 /* determine which specific SOC we are */
 extern void identify_ppc_sys_by_id(u32 id) __init;
 extern void identify_ppc_sys_by_name(char *name) __init;
+extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init;
 
 /* describes all devices that may exist in a given family of processors */
 extern struct platform_device ppc_sys_platform_devices[];
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index c418aab7cd34..88b4222154d4 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -160,6 +160,7 @@
 #define HID0_ICFI       (1<<11)         /* Instr. Cache Flash Invalidate */
 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
 #define HID0_SPD        (1<<9)          /* Speculative disable */
+#define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
 #define HID0_SGE        (1<<7)          /* Store Gathering Enable */
 #define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
 #define HID0_DFCA       (1<<6)          /* Data Cache Flush Assist */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 45c5e6f2b7ab..00ad9c754c78 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -165,6 +165,8 @@ do {						\
 #define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
 #define SPRN_MCSR       0x23C   /* Machine Check Status Register */
 #define SPRN_MCAR       0x23D   /* Machine Check Address Register */
+#define SPRN_DSRR0      0x23E   /* Debug Save and Restore Register 0 */
+#define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
 #define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
 #define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
 #define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
@@ -264,6 +266,17 @@ do {						\
 #define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
 #define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
 #endif
+#ifdef CONFIG_E200
+#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
+#define MCSR_CP_PERR    0x20000000UL /* Cache Push Parity Error */
+#define MCSR_CPERR      0x10000000UL /* Cache Parity Error */
+#define MCSR_EXCP_ERR   0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
+                                        fetch for an exception handler */
+#define MCSR_BUS_IRERR  0x00000010UL /* Read Bus Error on instruction fetch*/
+#define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
+#define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
+                                        store or cache line push */
+#endif
 
 /* Bit definitions for the DBSR. */
 /*
@@ -311,6 +324,7 @@ do {						\
 #define ESR_ST          0x00800000      /* Store Operation */
 #define ESR_DLK         0x00200000      /* Data Cache Locking */
 #define ESR_ILK         0x00100000      /* Instr. Cache Locking */
+#define ESR_PUO         0x00040000      /* Unimplemented Operation exception */
 #define ESR_BO          0x00020000      /* Byte Ordering */
 
 /* Bit definitions related to the DBCR0. */
@@ -387,10 +401,12 @@ do {						\
 #define ICCR_CACHE      1               /* Cacheable */
 
 /* Bit definitions for L1CSR0. */
+#define L1CSR0_CLFC     0x00000100      /* Cache Lock Bits Flash Clear */
 #define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
+#define L1CSR0_CFI      0x00000002      /* Cache Flash Invalidate */
 #define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
 
-/* Bit definitions for L1CSR0. */
+/* Bit definitions for L1CSR1. */
 #define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
 #define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
 #define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
diff --git a/include/asm-ppc/resource.h b/include/asm-ppc/resource.h
deleted file mode 100644
index 86a1ea23a6ed..000000000000
--- a/include/asm-ppc/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _PPC_RESOURCE_H
-#define _PPC_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif
diff --git a/include/asm-ppc/seccomp.h b/include/asm-ppc/seccomp.h
new file mode 100644
index 000000000000..666c4da96d87
--- /dev/null
+++ b/include/asm-ppc/seccomp.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc/sembuf.h b/include/asm-ppc/sembuf.h
deleted file mode 100644
index 883f682f85b8..000000000000
--- a/include/asm-ppc/sembuf.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _PPC_SEMBUF_H
-#define _PPC_SEMBUF_H
-
-/*
- * The semid64_ds structure for PPC architecture.
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        unsigned int    __unused1;
-        __kernel_time_t sem_otime;              /* last semop time */
-        unsigned int    __unused2;
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _PPC_SEMBUF_H */
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
index 6d47438be58c..485a924e4d06 100644
--- a/include/asm-ppc/serial.h
+++ b/include/asm-ppc/serial.h
@@ -18,8 +18,6 @@
 #include <platforms/powerpmc250.h>
 #elif defined(CONFIG_LOPEC)
 #include <platforms/lopec.h>
-#elif defined(CONFIG_MCPN765)
-#include <platforms/mcpn765.h>
 #elif defined(CONFIG_MVME5100)
 #include <platforms/mvme5100.h>
 #elif defined(CONFIG_PAL4)
diff --git a/include/asm-ppc/siginfo.h b/include/asm-ppc/siginfo.h
deleted file mode 100644
index 4b9435bb9049..000000000000
--- a/include/asm-ppc/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _PPC_SIGINFO_H
-#define _PPC_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
index ebfb614f55f6..17530c232c76 100644
--- a/include/asm-ppc/smp.h
+++ b/include/asm-ppc/smp.h
@@ -44,7 +44,7 @@ extern void smp_message_recv(int, struct pt_regs *);
 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 #define PROC_CHANGE_PENALTY     20
 
-#define smp_processor_id() (current_thread_info()->cpu)
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 extern int __cpu_up(unsigned int cpu);
 
diff --git a/include/asm-ppc/sockios.h b/include/asm-ppc/sockios.h
deleted file mode 100644
index 385aedc55ceb..000000000000
--- a/include/asm-ppc/sockios.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_PPC_SOCKIOS_H
-#define _ASM_PPC_SOCKIOS_H
-
-#if 0 /* These are defined this way on Alpha - maybe later. */
-/* Socket-level I/O control calls. */
-
-#define FIOGETOWN       _IOR('f', 123, int)
-#define FIOSETOWN       _IOW('f', 124, int)
-
-#define SIOCATMARK      _IOR('s', 7, int)
-#define SIOCSPGRP       _IOW('s', 8, pid_t)
-#define SIOCGPGRP       _IOR('s', 9, pid_t)
-
-#define SIOCGSTAMP      0x8906          /* Get stamp - linux-specific */
-#endif
-
-#endif /* _ASM_PPC_SOCKIOS_H */
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index 82395f30004b..513a334c5810 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -84,9 +84,14 @@ extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
 extern void cvt_df(double *from, float *to, unsigned long *fpscr);
 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 extern void cacheable_memzero(void *p, unsigned int nb);
+extern void *cacheable_memcpy(void *, const void *, unsigned int);
 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 extern void die(const char *, struct pt_regs *, long);
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+#endif /* CONFIG_BOOKE_WDT */
 
 struct device_node;
 extern void note_scsi_host(struct device_node *, void *);
diff --git a/include/asm-ppc/termbits.h b/include/asm-ppc/termbits.h
deleted file mode 100644
index c343fb7bdfed..000000000000
--- a/include/asm-ppc/termbits.h
+++ /dev/null
@@ -1,185 +0,0 @@
-#ifndef _PPC_TERMBITS_H
-#define _PPC_TERMBITS_H
-
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-
-/*
- * termios type and macro definitions.  Be careful about adding stuff
- * to this file since it's used in GNU libc and there are strict rules
- * concerning namespace pollution.
- */
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_cc[NCCS];                /* control characters */
-        cc_t c_line;                    /* line discipline (== c_cc[19]) */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR   0
-#define VQUIT   1
-#define VERASE  2
-#define VKILL   3
-#define VEOF    4
-#define VMIN    5
-#define VEOL    6
-#define VTIME   7
-#define VEOL2   8
-#define VSWTC   9
-
-#define VWERASE         10
-#define VREPRINT        11
-#define VSUSP           12
-#define VSTART          13
-#define VSTOP           14
-#define VLNEXT          15
-#define VDISCARD        16
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IXON    0001000
-#define IXOFF   0002000
-#define IXANY           0004000
-#define IUCLC           0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define ONLCR   0000002
-#define OLCUC   0000004
-
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-
-#define OFILL   00000100
-#define OFDEL   00000200
-#define NLDLY   00001400
-#define   NL0   00000000
-#define   NL1   00000400
-#define   NL2   00001000
-#define   NL3   00001400
-#define TABDLY  00006000
-#define   TAB0  00000000
-#define   TAB1  00002000
-#define   TAB2  00004000
-#define   TAB3  00006000
-#define   XTABS 00006000        /* required by POSIX to == TAB3 */
-#define CRDLY   00030000
-#define   CR0   00000000
-#define   CR1   00010000
-#define   CR2   00020000
-#define   CR3   00030000
-#define FFDLY   00040000
-#define   FF0   00000000
-#define   FF1   00040000
-#define BSDLY   00100000
-#define   BS0   00000000
-#define   BS1   00100000
-#define VTDLY   00200000
-#define   VT0   00000000
-#define   VT1   00200000
-
-/* c_cflag bit meaning */
-#define CBAUD   0000377
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CBAUDEX 0000000
-#define  B57600   00020
-#define  B115200  00021
-#define  B230400  00022
-#define  B460800  00023
-#define  B500000  00024
-#define  B576000  00025
-#define  B921600  00026
-#define B1000000  00027
-#define B1152000  00030
-#define B1500000  00031
-#define B2000000  00032
-#define B2500000  00033
-#define B3000000  00034
-#define B3500000  00035
-#define B4000000  00036
-
-#define CSIZE   00001400
-#define   CS5   00000000
-#define   CS6   00000400
-#define   CS7   00001000
-#define   CS8   00001400
-
-#define CSTOPB  00002000
-#define CREAD   00004000
-#define PARENB  00010000
-#define PARODD  00020000
-#define HUPCL   00040000
-
-#define CLOCAL  00100000
-#define CRTSCTS   020000000000          /* flow control */
-
-/* c_lflag bits */
-#define ISIG    0x00000080
-#define ICANON  0x00000100
-#define XCASE   0x00004000
-#define ECHO    0x00000008
-#define ECHOE   0x00000002
-#define ECHOK   0x00000004
-#define ECHONL  0x00000010
-#define NOFLSH  0x80000000
-#define TOSTOP  0x00400000
-#define ECHOCTL 0x00000040
-#define ECHOPRT 0x00000020
-#define ECHOKE  0x00000001
-#define FLUSHO  0x00800000
-#define PENDIN  0x20000000
-#define IEXTEN  0x00000400
-
-/* Values for the ACTION argument to `tcflow'.  */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* Values for the QUEUE_SELECTOR argument to `tcflush'.  */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'.  */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif /* _PPC_TERMBITS_H */
diff --git a/include/asm-ppc/termios.h b/include/asm-ppc/termios.h
deleted file mode 100644
index 97c6287a6cba..000000000000
--- a/include/asm-ppc/termios.h
+++ /dev/null
@@ -1,232 +0,0 @@
-#ifndef _PPC_TERMIOS_H
-#define _PPC_TERMIOS_H
-
-/*
- * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
- * fields have been reordered so that termio & termios share the
- * common subset in the same order (for brain dead programs that don't
- * know or care about the differences).
- */
-
-#include <asm/ioctls.h>
-#include <asm/termbits.h>
-
-struct sgttyb {
-        char    sg_ispeed;
-        char    sg_ospeed;
-        char    sg_erase;
-        char    sg_kill;
-        short   sg_flags;
-};
-
-struct tchars {
-        char    t_intrc;
-        char    t_quitc;
-        char    t_startc;
-        char    t_stopc;
-        char    t_eofc;
-        char    t_brkc;
-};
-
-struct ltchars {
-        char    t_suspc;
-        char    t_dsuspc;
-        char    t_rprntc;
-        char    t_flushc;
-        char    t_werasc;
-        char    t_lnextc;
-};
-
-#define FIOCLEX         _IO('f', 1)
-#define FIONCLEX        _IO('f', 2)
-#define FIOASYNC        _IOW('f', 125, int)
-#define FIONBIO         _IOW('f', 126, int)
-#define FIONREAD        _IOR('f', 127, int)
-#define TIOCINQ         FIONREAD
-#define FIOQSIZE        _IOR('f', 128, loff_t)
-
-#define TIOCGETP        _IOR('t', 8, struct sgttyb)
-#define TIOCSETP        _IOW('t', 9, struct sgttyb)
-#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
-
-#define TIOCSETC        _IOW('t', 17, struct tchars)
-#define TIOCGETC        _IOR('t', 18, struct tchars)
-#define TCGETS          _IOR('t', 19, struct termios)
-#define TCSETS          _IOW('t', 20, struct termios)
-#define TCSETSW         _IOW('t', 21, struct termios)
-#define TCSETSF         _IOW('t', 22, struct termios)
-
-#define TCGETA          _IOR('t', 23, struct termio)
-#define TCSETA          _IOW('t', 24, struct termio)
-#define TCSETAW         _IOW('t', 25, struct termio)
-#define TCSETAF         _IOW('t', 28, struct termio)
-
-#define TCSBRK          _IO('t', 29)
-#define TCXONC          _IO('t', 30)
-#define TCFLSH          _IO('t', 31)
-
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
-#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
-#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-
-#define TIOCGLTC        _IOR('t', 116, struct ltchars)
-#define TIOCSLTC        _IOW('t', 117, struct ltchars)
-#define TIOCSPGRP       _IOW('t', 118, int)
-#define TIOCGPGRP       _IOR('t', 119, int)
-
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-
-#define TIOCSTI         0x5412
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 10
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-/* c_cc characters */
-#define _VINTR  0
-#define _VQUIT  1
-#define _VERASE 2
-#define _VKILL  3
-#define _VEOF   4
-#define _VMIN   5
-#define _VEOL   6
-#define _VTIME  7
-#define _VEOL2  8
-#define _VSWTC  9
-
-#ifdef __KERNEL__
-/*                   ^C  ^\ del  ^U  ^D   1   0   0   0   0  ^W  ^R  ^Z  ^Q  ^S  ^V  ^U  */
-#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
-#endif  /* __KERNEL__ */
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-
-/* line disciplines */
-#define N_TTY           0
-#define N_SLIP          1
-#define N_MOUSE         2
-#define N_PPP           3
-#define N_STRIP         4
-#define N_AX25          5
-#define N_X25           6       /* X.25 async */
-#define N_6PACK         7
-#define N_MASC          8       /* Reserved for Mobitex module <kaz@cafe.net> */
-#define N_R3964         9       /* Reserved for Simatic R3964 module */
-#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
-#define N_IRDA          11      /* Linux IrDa - http://irda.sourceforge.net/ */
-#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
-#define N_HDLC          13      /* synchronous HDLC */
-#define N_SYNC_PPP      14
-#define N_HCI           15  /* Bluetooth HCI UART */
-
-#ifdef __KERNEL__
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-        unsigned short __tmp; \
-        get_user(__tmp,&(termio)->x); \
-        (termios)->x = (0xffff0000 & (termios)->x) | __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif  /* __KERNEL__ */
-
-#endif  /* _PPC_TERMIOS_H */
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
index f7f01524e8a8..27903db42efc 100644
--- a/include/asm-ppc/thread_info.h
+++ b/include/asm-ppc/thread_info.h
@@ -20,7 +20,8 @@ struct thread_info {
         unsigned long           flags;          /* low level flags */
         unsigned long           local_flags;    /* non-racy flags */
         int                     cpu;            /* cpu we're on */
-        int                     preempt_count;
+        int                     preempt_count;  /* 0 => preemptable,
+                                                   <0 => BUG */
         struct restart_block    restart_block;
 };
 
@@ -77,12 +78,19 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
                                            TIF_NEED_RESCHED */
 #define TIF_MEMDIE              5
+#define TIF_SYSCALL_AUDIT       6       /* syscall auditing active */
+#define TIF_SECCOMP             7      /* secure computing */
+
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+
+#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
 
 /*
  * Non racy (local) flags bit numbers
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h
index ce09b47fa819..321fb75b5f22 100644
--- a/include/asm-ppc/time.h
+++ b/include/asm-ppc/time.h
@@ -58,7 +58,7 @@ static __inline__ void set_dec(unsigned int val)
 /* Accessor functions for the timebase (RTC on 601) registers. */
 /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
 #ifdef CONFIG_6xx
-extern __inline__ int const __USE_RTC(void) {
+extern __inline__ int __attribute_pure__ __USE_RTC(void) {
         return (mfspr(SPRN_PVR)>>16) == 1;
 }
 #else
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
index a787bc032587..77dc24d7d2ad 100644
--- a/include/asm-ppc/types.h
+++ b/include/asm-ppc/types.h
@@ -62,8 +62,6 @@ typedef u64 sector_t;
 #define HAVE_SECTOR_T
 #endif
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h
index b044ae03ac56..63f56224da8c 100644
--- a/include/asm-ppc/uaccess.h
+++ b/include/asm-ppc/uaccess.h
@@ -37,13 +37,6 @@
 #define access_ok(type, addr, size) \
         (__chk_user_ptr(addr),__access_ok((unsigned long)(addr),(size)))
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
index cc51e5c9acc2..3173ab3d2eb9 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-ppc/unistd.h
@@ -262,7 +262,7 @@
 #define __NR_rtas               255
 #define __NR_sys_debug_setcontext 256
 /* Number 257 is reserved for vserver */
-/* Number 258 is reserved for new sys_remap_file_pages */
+/* 258 currently unused */
 /* Number 259 is reserved for new sys_mbind */
 /* Number 260 is reserved for new sys_get_mempolicy */
 /* Number 261 is reserved for new sys_set_mempolicy */
@@ -277,8 +277,13 @@
 #define __NR_request_key        270
 #define __NR_keyctl             271
 #define __NR_waitid             272
+#define __NR_ioprio_set         273
+#define __NR_ioprio_get         274
+#define __NR_inotify_init       275
+#define __NR_inotify_add_watch  276
+#define __NR_inotify_rm_watch   277
 
-#define __NR_syscalls           273
+#define __NR_syscalls           278
 
 #define __NR(n) #n
 
diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-ppc64/abs_addr.h
index 6d4e8e787058..84c24d4cdb71 100644
--- a/include/asm-ppc64/abs_addr.h
+++ b/include/asm-ppc64/abs_addr.h
@@ -16,93 +16,51 @@
 #include <asm/page.h>
 #include <asm/prom.h>
 #include <asm/lmb.h>
+#include <asm/firmware.h>
 
-typedef u32 msChunks_entry;
-struct msChunks {
+struct mschunks_map {
         unsigned long num_chunks;
         unsigned long chunk_size;
         unsigned long chunk_shift;
         unsigned long chunk_mask;
-        msChunks_entry *abs;
+        u32 *mapping;
 };
 
-extern struct msChunks msChunks;
+extern struct mschunks_map mschunks_map;
 
-extern unsigned long msChunks_alloc(unsigned long, unsigned long, unsigned long);
-extern unsigned long reloc_offset(void);
+/* Chunks are 256 KB */
+#define MSCHUNKS_CHUNK_SHIFT    (18)
+#define MSCHUNKS_CHUNK_SIZE     (1UL << MSCHUNKS_CHUNK_SHIFT)
+#define MSCHUNKS_OFFSET_MASK    (MSCHUNKS_CHUNK_SIZE - 1)
 
-#ifdef CONFIG_MSCHUNKS
-
-static inline unsigned long
-chunk_to_addr(unsigned long chunk)
+static inline unsigned long chunk_to_addr(unsigned long chunk)
 {
-        unsigned long offset = reloc_offset();
-        struct msChunks *_msChunks = PTRRELOC(&msChunks);
-
-        return chunk << _msChunks->chunk_shift;
+        return chunk << MSCHUNKS_CHUNK_SHIFT;
 }
 
-static inline unsigned long
-addr_to_chunk(unsigned long addr)
+static inline unsigned long addr_to_chunk(unsigned long addr)
 {
-        unsigned long offset = reloc_offset();
-        struct msChunks *_msChunks = PTRRELOC(&msChunks);
-
-        return addr >> _msChunks->chunk_shift;
+        return addr >> MSCHUNKS_CHUNK_SHIFT;
 }
 
-static inline unsigned long
-chunk_offset(unsigned long addr)
+static inline unsigned long phys_to_abs(unsigned long pa)
 {
-        unsigned long offset = reloc_offset();
-        struct msChunks *_msChunks = PTRRELOC(&msChunks);
+        unsigned long chunk;
 
-        return addr & _msChunks->chunk_mask;
-}
+        /* This is a no-op on non-iSeries */
+        if (!firmware_has_feature(FW_FEATURE_ISERIES))
+                return pa;
 
-static inline unsigned long
-abs_chunk(unsigned long pchunk)
-{
-        unsigned long offset = reloc_offset();
-        struct msChunks *_msChunks = PTRRELOC(&msChunks);
-        if ( pchunk >= _msChunks->num_chunks ) {
-                return pchunk;
-        }
-        return PTRRELOC(_msChunks->abs)[pchunk];
-}
+        chunk = addr_to_chunk(pa);
 
-/* A macro so it can take pointers or unsigned long. */
-#define phys_to_abs(pa)                                              \
-        ({ unsigned long _pa = (unsigned long)(pa);                          \
-           chunk_to_addr(abs_chunk(addr_to_chunk(_pa))) + chunk_offset(_pa); \
-        })
+        if (chunk < mschunks_map.num_chunks)
+                chunk = mschunks_map.mapping[chunk];
 
-static inline unsigned long
-physRpn_to_absRpn(unsigned long rpn)
-{
-        unsigned long pa = rpn << PAGE_SHIFT;
-        unsigned long aa = phys_to_abs(pa);
-        return (aa >> PAGE_SHIFT);
+        return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
 }
 
-/* A macro so it can take pointers or unsigned long. */
-#define abs_to_phys(aa) lmb_abs_to_phys((unsigned long)(aa))
-
-#else  /* !CONFIG_MSCHUNKS */
-
-#define chunk_to_addr(chunk) ((unsigned long)(chunk))
-#define addr_to_chunk(addr) (addr)
-#define chunk_offset(addr) (0)
-#define abs_chunk(pchunk) (pchunk)
-
-#define phys_to_abs(pa) (pa)
-#define physRpn_to_absRpn(rpn) (rpn)
-#define abs_to_phys(aa) (aa)
-
-#endif /* !CONFIG_MSCHUNKS */
-
 /* Convenience macros */
 #define virt_to_abs(va) phys_to_abs(__pa(va))
-#define abs_to_virt(aa) __va(abs_to_phys(aa))
+#define abs_to_virt(aa) __va(aa)
 
 #endif /* _ABS_ADDR_H */
diff --git a/include/asm-ppc64/agp.h b/include/asm-ppc64/agp.h
deleted file mode 100644
index ca9e423307f4..000000000000
--- a/include/asm-ppc64/agp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef AGP_H
-#define AGP_H 1
-
-#include <asm/io.h>
-
-/* nothing much needed here */
-
-#define map_page_into_agp(page)
-#define unmap_page_from_agp(page)
-#define flush_agp_mappings()
-#define flush_agp_cache() mb()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)         \
-        ((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)   \
-        free_pages((unsigned long)(table), (order))
-
-#endif
diff --git a/include/asm-ppc64/auxvec.h b/include/asm-ppc64/auxvec.h
new file mode 100644
index 000000000000..ac6381a106e1
--- /dev/null
+++ b/include/asm-ppc64/auxvec.h
@@ -0,0 +1,19 @@
+#ifndef __PPC64_AUXVEC_H
+#define __PPC64_AUXVEC_H
+
+/*
+ * We need to put in some extra aux table entries to tell glibc what
+ * the cache block size is, so it can use the dcbz instruction safely.
+ */
+#define AT_DCACHEBSIZE          19
+#define AT_ICACHEBSIZE          20
+#define AT_UCACHEBSIZE          21
+/* A special ignored type value for PPC, for glibc compatibility.  */
+#define AT_IGNOREPPC            22
+
+/* The vDSO location. We have to use the same value as x86 for glibc's
+ * sake :-)
+ */
+#define AT_SYSINFO_EHDR         33
+
+#endif /* __PPC64_AUXVEC_H */
diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h
index 169868fa307d..160178278861 100644
--- a/include/asm-ppc64/bug.h
+++ b/include/asm-ppc64/bug.h
@@ -43,8 +43,8 @@ struct bug_entry *find_bug(unsigned long bugaddr);
                 ".section __bug_table,\"a\"\n\t"                \
                 "       .llong 1b,%1,%2,%3\n"                   \
                 ".previous"                                     \
-                : : "r" (x), "i" (__LINE__), "i" (__FILE__),    \
-                    "i" (__FUNCTION__));                        \
+                : : "r" ((long long)(x)), "i" (__LINE__),       \
+                    "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
 
 #define WARN_ON(x) do {                                         \
@@ -53,7 +53,8 @@ struct bug_entry *find_bug(unsigned long bugaddr);
                 ".section __bug_table,\"a\"\n\t"                \
                 "       .llong 1b,%1,%2,%3\n"                   \
                 ".previous"                                     \
-                : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
+                : : "r" ((long long)(x)),                       \
+                    "i" (__LINE__ + BUG_WARNING_TRAP),          \
                     "i" (__FILE__), "i" (__FUNCTION__));        \
 } while (0)
 
diff --git a/include/asm-ppc64/bugs.h b/include/asm-ppc64/bugs.h
deleted file mode 100644
index 861074b3cf71..000000000000
--- a/include/asm-ppc64/bugs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * This file is included by 'init/main.c' to check for architecture-dependent
- * bugs.
- *
- */
-#ifndef _ASM_PPC64_BUGS_H
-#define _ASM_PPC64_BUGS_H
-
-static void check_bugs(void) {
-}
-
-#endif /* _ASM_PPC64_BUGS_H */
diff --git a/include/asm-ppc64/byteorder.h b/include/asm-ppc64/byteorder.h
index 80327532de64..8b57da62b674 100644
--- a/include/asm-ppc64/byteorder.h
+++ b/include/asm-ppc64/byteorder.h
@@ -40,7 +40,6 @@ static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
         __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
 }
 
-#if 0
 static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
 {
         __u16 result;
@@ -63,17 +62,8 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
         return result;
 }
 
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 value)
-{
-        __u64 result;
-#error implement me
-}
-
 #define __arch__swab16(x) ___arch__swab16(x)
 #define __arch__swab32(x) ___arch__swab32(x)
-#define __arch__swab64(x) ___arch__swab64(x)
-
-#endif
 
 /* The same, but returns converted value from the location pointer by addr. */
 #define __arch__swab16p(addr) ld_le16(addr)
diff --git a/include/asm-ppc64/compat.h b/include/asm-ppc64/compat.h
index 09c28d28ce6c..6ec62cd2d1d1 100644
--- a/include/asm-ppc64/compat.h
+++ b/include/asm-ppc64/compat.h
@@ -13,8 +13,10 @@ typedef s32		compat_ssize_t;
 typedef s32             compat_time_t;
 typedef s32             compat_clock_t;
 typedef s32             compat_pid_t;
-typedef u32             compat_uid_t;
-typedef u32             compat_gid_t;
+typedef u32             __compat_uid_t;
+typedef u32             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u32             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
@@ -26,6 +28,7 @@ typedef s32		compat_daddr_t;
 typedef u32             compat_caddr_t;
 typedef __kernel_fsid_t compat_fsid_t;
 typedef s32             compat_key_t;
+typedef s32             compat_timer_t;
 
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
@@ -47,8 +50,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;       
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid32_t        st_uid;
+        __compat_gid32_t        st_gid;
         compat_dev_t    st_rdev;
         compat_off_t    st_size;
         compat_off_t    st_blksize;
@@ -143,10 +146,10 @@ static inline void __user *compat_alloc_user_space(long len)
  */
 struct compat_ipc64_perm {
         compat_key_t key;
-        compat_uid_t uid;
-        compat_gid_t gid;
-        compat_uid_t cuid;
-        compat_gid_t cgid;
+        __compat_uid_t uid;
+        __compat_gid_t gid;
+        __compat_uid_t cuid;
+        __compat_gid_t cgid;
         compat_mode_t mode;
         unsigned int seq;
         unsigned int __pad2;
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
index cbbfbec78b6b..acc9b4d6c168 100644
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -36,6 +36,7 @@
  * via the mkdefs mechanism.
  */
 struct cpu_spec;
+struct op_ppc64_model;
 
 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
 
@@ -52,15 +53,19 @@ struct cpu_spec {
         unsigned int    icache_bsize;
         unsigned int    dcache_bsize;
 
+        /* number of performance monitor counters */
+        unsigned int    num_pmcs;
+
         /* this is called to initialize various CPU bits like L1 cache,
          * BHT, SPD, etc... from head.S before branching to identify_machine
          */
         cpu_setup_t     cpu_setup;
 
-        /* This is used to identify firmware features which are available
-         * to the kernel.
-         */
-        unsigned long   firmware_features;
+        /* Used by oprofile userspace to select the right counters */
+        char            *oprofile_cpu_type;
+
+        /* Processor specific oprofile operations */
+        struct op_ppc64_model *oprofile_model;
 };
 
 extern struct cpu_spec          cpu_specs[];
@@ -71,39 +76,6 @@ static inline unsigned long cpu_has_feature(unsigned long feature)
         return cur_cpu_spec->cpu_features & feature;
 }
 
-
-/* firmware feature bitmask values */
-#define FIRMWARE_MAX_FEATURES 63
-
-#define FW_FEATURE_PFT          (1UL<<0)
-#define FW_FEATURE_TCE          (1UL<<1)        
-#define FW_FEATURE_SPRG0        (1UL<<2)        
-#define FW_FEATURE_DABR         (1UL<<3)        
-#define FW_FEATURE_COPY         (1UL<<4)        
-#define FW_FEATURE_ASR          (1UL<<5)        
-#define FW_FEATURE_DEBUG        (1UL<<6)        
-#define FW_FEATURE_TERM         (1UL<<7)        
-#define FW_FEATURE_PERF         (1UL<<8)        
-#define FW_FEATURE_DUMP         (1UL<<9)        
-#define FW_FEATURE_INTERRUPT    (1UL<<10)       
-#define FW_FEATURE_MIGRATE      (1UL<<11)       
-#define FW_FEATURE_PERFMON      (1UL<<12)       
-#define FW_FEATURE_CRQ          (1UL<<13)       
-#define FW_FEATURE_VIO          (1UL<<14)       
-#define FW_FEATURE_RDMA         (1UL<<15)       
-#define FW_FEATURE_LLAN         (1UL<<16)       
-#define FW_FEATURE_BULK         (1UL<<17)       
-#define FW_FEATURE_XDABR        (1UL<<18)       
-#define FW_FEATURE_MULTITCE     (1UL<<19)       
-#define FW_FEATURE_SPLPAR       (1UL<<20)       
-
-typedef struct {
-    unsigned long val;
-    char * name;
-} firmware_feature_t;
-
-extern firmware_feature_t firmware_features_table[];
-
 #endif /* __ASSEMBLY__ */
 
 /* CPU kernel features */
@@ -133,32 +105,30 @@ extern firmware_feature_t firmware_features_table[];
 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000001000000000)
 #define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
 #define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
-#define CPU_FTR_PMC8                    ASM_CONST(0x0000008000000000)
+/* unused                               ASM_CONST(0x0000008000000000) */
 #define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
-
-/* Platform firmware features */
-#define FW_FTR_                         ASM_CONST(0x0000000000000001)
+#define CPU_FTR_CTRL                    ASM_CONST(0x0000100000000000)
 
 #ifndef __ASSEMBLY__
+
 #define COMMON_USER_PPC64       (PPC_FEATURE_32 | PPC_FEATURE_64 | \
                                  PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
 
 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-                                 CPU_FTR_NODSISRALIGN)
+                                 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
 
 /* iSeries doesn't support large pages */
 #ifdef CONFIG_PPC_ISERIES
 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
 #else
 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif
+#endif /* CONFIG_PPC_ISERIES */
 
-#define COMMON_PPC64_FW (0)
-#endif
+#endif /* __ASSEMBLY */
 
 #ifdef __ASSEMBLY__
 
diff --git a/include/asm-ppc64/cputime.h b/include/asm-ppc64/cputime.h
deleted file mode 100644
index 8e9faf5ce720..000000000000
--- a/include/asm-ppc64/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PPC_CPUTIME_H
-#define __PPC_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __PPC_CPUTIME_H */
diff --git a/include/asm-ppc64/div64.h b/include/asm-ppc64/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-ppc64/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-ppc64/dma.h b/include/asm-ppc64/dma.h
index d693b8026bc3..dfd1f69059ba 100644
--- a/include/asm-ppc64/dma.h
+++ b/include/asm-ppc64/dma.h
@@ -27,6 +27,8 @@
 /* Doesn't really apply... */
 #define MAX_DMA_ADDRESS  (~0UL)
 
+#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
+
 #define dma_outb        outb
 #define dma_inb         inb
 
@@ -323,4 +325,5 @@ extern int isa_dma_bridge_buggy;
 #else                                                         
 #define isa_dma_bridge_buggy   (0)
 #endif
+#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
 #endif /* _ASM_DMA_H */
diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h
index 085eedb956fe..c919a89343db 100644
--- a/include/asm-ppc64/elf.h
+++ b/include/asm-ppc64/elf.h
@@ -4,6 +4,7 @@
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
+#include <asm/auxvec.h>
 
 /* PowerPC relocations defined by the ABIs */
 #define R_PPC_NONE              0
@@ -237,21 +238,6 @@ do {								\
 
 #endif
 
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE          19
-#define AT_ICACHEBSIZE          20
-#define AT_UCACHEBSIZE          21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC            22
-
-/* The vDSO location. We have to use the same value as x86 for glibc's
- * sake :-)
- */
-#define AT_SYSINFO_EHDR         33
-
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;
diff --git a/include/asm-ppc64/errno.h b/include/asm-ppc64/errno.h
deleted file mode 100644
index 69bc3b0c6cbe..000000000000
--- a/include/asm-ppc64/errno.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _PPC64_ERRNO_H
-#define _PPC64_ERRNO_H
-
-/* 
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm-generic/errno.h>
-
-#undef  EDEADLOCK
-#define EDEADLOCK       58      /* File locking deadlock error */
-
-#define _LAST_ERRNO     516
-
-#endif
diff --git a/include/asm-ppc64/fcntl.h b/include/asm-ppc64/fcntl.h
deleted file mode 100644
index 842560d50656..000000000000
--- a/include/asm-ppc64/fcntl.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef _PPC64_FCNTL_H
-#define _PPC64_FCNTL_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECTORY      040000 /* must be a directory */
-#define O_NOFOLLOW      0100000 /* don't follow links */
-#define O_LARGEFILE     0200000
-#define O_DIRECT        0400000 /* direct disk access hint */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-#ifdef __KERNEL__
-#define F_POSIX         1
-#define F_FLOCK         2
-#define F_BROKEN        4       /* broken flock() emulation */
-#endif /* __KERNEL__ */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-
-#endif /* _PPC64_FCNTL_H */
diff --git a/include/asm-ppc64/firmware.h b/include/asm-ppc64/firmware.h
new file mode 100644
index 000000000000..22bb85cf60af
--- /dev/null
+++ b/include/asm-ppc64/firmware.h
@@ -0,0 +1,101 @@
+/*
+ *  include/asm-ppc64/firmware.h
+ *
+ *  Extracted from include/asm-ppc64/cputable.h
+ *
+ *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ *  Modifications for ppc64:
+ *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_PPC_FIRMWARE_H
+#define __ASM_PPC_FIRMWARE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+/* firmware feature bitmask values */
+#define FIRMWARE_MAX_FEATURES 63
+
+#define FW_FEATURE_PFT          (1UL<<0)
+#define FW_FEATURE_TCE          (1UL<<1)
+#define FW_FEATURE_SPRG0        (1UL<<2)
+#define FW_FEATURE_DABR         (1UL<<3)
+#define FW_FEATURE_COPY         (1UL<<4)
+#define FW_FEATURE_ASR          (1UL<<5)
+#define FW_FEATURE_DEBUG        (1UL<<6)
+#define FW_FEATURE_TERM         (1UL<<7)
+#define FW_FEATURE_PERF         (1UL<<8)
+#define FW_FEATURE_DUMP         (1UL<<9)
+#define FW_FEATURE_INTERRUPT    (1UL<<10)
+#define FW_FEATURE_MIGRATE      (1UL<<11)
+#define FW_FEATURE_PERFMON      (1UL<<12)
+#define FW_FEATURE_CRQ          (1UL<<13)
+#define FW_FEATURE_VIO          (1UL<<14)
+#define FW_FEATURE_RDMA         (1UL<<15)
+#define FW_FEATURE_LLAN         (1UL<<16)
+#define FW_FEATURE_BULK         (1UL<<17)
+#define FW_FEATURE_XDABR        (1UL<<18)
+#define FW_FEATURE_MULTITCE     (1UL<<19)
+#define FW_FEATURE_SPLPAR       (1UL<<20)
+#define FW_FEATURE_ISERIES      (1UL<<21)
+
+enum {
+        FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
+                FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
+                FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
+                FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
+                FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
+                FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
+                FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE |
+                FW_FEATURE_SPLPAR,
+        FW_FEATURE_PSERIES_ALWAYS = 0,
+        FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES,
+        FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES,
+        FW_FEATURE_POSSIBLE =
+#ifdef CONFIG_PPC_PSERIES
+                FW_FEATURE_PSERIES_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_ISERIES
+                FW_FEATURE_ISERIES_POSSIBLE |
+#endif
+                0,
+        FW_FEATURE_ALWAYS =
+#ifdef CONFIG_PPC_PSERIES
+                FW_FEATURE_PSERIES_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_ISERIES
+                FW_FEATURE_ISERIES_ALWAYS &
+#endif
+                FW_FEATURE_POSSIBLE,
+};
+
+/* This is used to identify firmware features which are available
+ * to the kernel.
+ */
+extern unsigned long    ppc64_firmware_features;
+
+static inline unsigned long firmware_has_feature(unsigned long feature)
+{
+        return (FW_FEATURE_ALWAYS & feature) ||
+                (FW_FEATURE_POSSIBLE & ppc64_firmware_features & feature);
+}
+
+#ifdef CONFIG_PPC_PSERIES
+typedef struct {
+    unsigned long val;
+    char * name;
+} firmware_feature_t;
+
+extern firmware_feature_t firmware_features_table[];
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_PPC_FIRMWARE_H */
diff --git a/include/asm-ppc64/futex.h b/include/asm-ppc64/futex.h
new file mode 100644
index 000000000000..cb2640b3a408
--- /dev/null
+++ b/include/asm-ppc64/futex.h
@@ -0,0 +1,83 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/memory.h>
+#include <asm/uaccess.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile (SYNC_ON_SMP                               \
+"1:     lwarx   %0,0,%2\n"                                      \
+        insn                                                    \
+"2:     stwcx.  %1,0,%2\n\
+        bne-    1b\n\
+        li      %1,0\n\
+3:      .section .fixup,\"ax\"\n\
+4:      li      %1,%3\n\
+        b       3b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align 3\n\
+        .llong  1b,4b,2b,4b\n\
+        .previous"                                              \
+        : "=&r" (oldval), "=&r" (ret)                           \
+        : "b" (uaddr), "i" (-EFAULT), "1" (oparg)               \
+        : "cr0", "memory")
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("add %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("andc %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-ppc64/hdreg.h b/include/asm-ppc64/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-ppc64/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-ppc64/hvconsole.h b/include/asm-ppc64/hvconsole.h
index d89d94c91815..6da93ce74dc0 100644
--- a/include/asm-ppc64/hvconsole.h
+++ b/include/asm-ppc64/hvconsole.h
@@ -29,12 +29,21 @@
  */
 #define MAX_NR_HVC_CONSOLES     16
 
+/* implemented by a low level driver */
+struct hv_ops {
+        int (*get_chars)(uint32_t vtermno, char *buf, int count);
+        int (*put_chars)(uint32_t vtermno, const char *buf, int count);
+};
 extern int hvc_get_chars(uint32_t vtermno, char *buf, int count);
 extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
 
-/* Early discovery of console adapters. */
-extern int hvc_find_vtys(void);
+struct hvc_struct;
 
-/* Implemented by a console driver */
-extern int hvc_instantiate(uint32_t vtermno, int index);
+/* Register a vterm and a slot index for use as a console (console_init) */
+extern int hvc_instantiate(uint32_t vtermno, int index, struct hv_ops *ops);
+/* register a vterm for hvc tty operation (module_init or hotplug add) */
+extern struct hvc_struct * __devinit hvc_alloc(uint32_t vtermno, int irq,
+                                                 struct hv_ops *ops);
+/* remove a vterm from hvc tty operation (modele_exit or hotplug remove) */
+extern int __devexit hvc_remove(struct hvc_struct *hp);
 #endif /* _PPC64_HVCONSOLE_H */
diff --git a/include/asm-ppc64/iSeries/HvCall.h b/include/asm-ppc64/iSeries/HvCall.h
index d9a2e74e2399..c3f19475c0d9 100644
--- a/include/asm-ppc64/iSeries/HvCall.h
+++ b/include/asm-ppc64/iSeries/HvCall.h
@@ -1,84 +1,36 @@
 /*
  * HvCall.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
-
-//===========================================================================
-//
-//      This file contains the "hypervisor call" interface which is used to
-//      drive the hypervisor from the OS.
-//
-//===========================================================================
+/*
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
+ */
 #ifndef _HVCALL_H
 #define _HVCALL_H
 
-//-------------------------------------------------------------------
-// Standard Includes
-//-------------------------------------------------------------------
 #include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 #include <asm/paca.h>
 
-/*
-enum HvCall_ReturnCode
-{
-        HvCall_Good             = 0,
-        HvCall_Partial          = 1,
-        HvCall_NotOwned         = 2,
-        HvCall_NotFreed         = 3,
-        HvCall_UnspecifiedError = 4
-};
-
-enum HvCall_TypeOfSIT
-{
-        HvCall_ReduceOnly       = 0,
-        HvCall_Unconditional    = 1
-};
-
-enum HvCall_TypeOfYield
-{
-        HvCall_YieldTimed       = 0,    // Yield until specified time
-        HvCall_YieldToActive    = 1,    // Yield until all active procs have run
-        HvCall_YieldToProc      = 2     // Yield until the specified processor has run
-};
-
-enum HvCall_InterruptMasks
-{
-        HvCall_MaskIPI          = 0x00000001,
-        HvCall_MaskLpEvent      = 0x00000002,
-        HvCall_MaskLpProd       = 0x00000004,
-        HvCall_MaskTimeout      = 0x00000008
-};
-
-enum HvCall_VaryOffChunkRc
-{
-        HvCall_VaryOffSucceeded         = 0,
-        HvCall_VaryOffWithdrawn         = 1,
-        HvCall_ChunkInLoadArea          = 2,
-        HvCall_ChunkInHPT               = 3,
-        HvCall_ChunkNotAccessible       = 4,
-        HvCall_ChunkInUse               = 5
-};
-*/
-
 /* Type of yield for HvCallBaseYieldProcessor */
-#define HvCall_YieldTimed       0       // Yield until specified time (tb)
-#define HvCall_YieldToActive    1       // Yield until all active procs have run
-#define HvCall_YieldToProc      2       // Yield until the specified processor has run
+#define HvCall_YieldTimed       0       /* Yield until specified time (tb) */
+#define HvCall_YieldToActive    1       /* Yield until all active procs have run */
+#define HvCall_YieldToProc      2       /* Yield until the specified processor has run */
 
 /* interrupt masks for setEnabledInterrupts */
 #define HvCall_MaskIPI          0x00000001
@@ -86,7 +38,7 @@ enum HvCall_VaryOffChunkRc
 #define HvCall_MaskLpProd       0x00000004
 #define HvCall_MaskTimeout      0x00000008
 
-/* Log buffer formats                       */
+/* Log buffer formats */
 #define HvCall_LogBuffer_ASCII          0
 #define HvCall_LogBuffer_EBCDIC         1
 
@@ -95,7 +47,7 @@ enum HvCall_VaryOffChunkRc
 #define HvCallBaseGetHwPatch                            HvCallBase +  2
 #define HvCallBaseReIplSpAttn                           HvCallBase +  3
 #define HvCallBaseSetASR                                HvCallBase +  4
-#define HvCallBaseSetASRAndRfi                          HvCallBase +  5 
+#define HvCallBaseSetASRAndRfi                          HvCallBase +  5
 #define HvCallBaseSetIMR                                HvCallBase +  6
 #define HvCallBaseSendIPI                               HvCallBase +  7
 #define HvCallBaseTerminateMachine                      HvCallBase +  8
@@ -115,91 +67,47 @@ enum HvCall_VaryOffChunkRc
 #define HvCallBaseGetLogBufferCodePage                  HvCallBase + 22
 #define HvCallBaseGetLogBufferFormat                    HvCallBase + 23
 #define HvCallBaseGetLogBufferLength                    HvCallBase + 24
-#define HvCallBaseReadLogBuffer                         HvCallBase + 25
+#define HvCallBaseReadLogBuffer                         HvCallBase + 25
 #define HvCallBaseSetLogBufferFormatAndCodePage         HvCallBase + 26
-#define HvCallBaseWriteLogBuffer                        HvCallBase + 27
+#define HvCallBaseWriteLogBuffer                        HvCallBase + 27
 #define HvCallBaseRouter28                              HvCallBase + 28
 #define HvCallBaseRouter29                              HvCallBase + 29
 #define HvCallBaseRouter30                              HvCallBase + 30
-#define HvCallBaseSetDebugBus                           HvCallBase + 31
+#define HvCallBaseSetDebugBus                           HvCallBase + 31
 
-#define HvCallCcSetDABR                                 HvCallCc + 7
+#define HvCallCcSetDABR                                 HvCallCc + 7
 
-//=====================================================================================
-static inline void              HvCall_setVirtualDecr(void)
+static inline void HvCall_setVirtualDecr(void)
 {
-        /* Ignore any error return codes - most likely means that the target value for the
-         * LP has been increased and this vary off would bring us below the new target. */
+        /*
+         * Ignore any error return codes - most likely means that the
+         * target value for the LP has been increased and this vary off
+         * would bring us below the new target.
+         */
         HvCall0(HvCallBaseSetVirtualDecr);
 }
-//=====================================================================
-static inline void              HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
-{
-        HvCall2( HvCallBaseYieldProcessor, typeOfYield, yieldParm );
-}
-//=====================================================================
-static inline void              HvCall_setEnabledInterrupts(u64 enabledInterrupts)
-{
-        HvCall1(HvCallBaseSetEnabledInterrupts,enabledInterrupts);
-}
-
-//=====================================================================
-static inline void              HvCall_clearLogBuffer(HvLpIndex lpindex)
-{
-        HvCall1(HvCallBaseClearLogBuffer,lpindex);
-}
-
-//=====================================================================
-static inline u32               HvCall_getLogBufferCodePage(HvLpIndex lpindex)
-{
-        u32 retVal = HvCall1(HvCallBaseGetLogBufferCodePage,lpindex);
-        return retVal;
-}
-
-//=====================================================================
-static inline int               HvCall_getLogBufferFormat(HvLpIndex lpindex)
-{
-        int retVal = HvCall1(HvCallBaseGetLogBufferFormat,lpindex);
-        return retVal;
-}
-
-//=====================================================================
-static inline u32               HvCall_getLogBufferLength(HvLpIndex lpindex)
-{
-        u32 retVal = HvCall1(HvCallBaseGetLogBufferLength,lpindex);
-        return retVal;
-}
 
-//=====================================================================
-static inline void              HvCall_setLogBufferFormatAndCodepage(int format, u32 codePage)
+static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
 {
-        HvCall2(HvCallBaseSetLogBufferFormatAndCodePage,format, codePage);
+        HvCall2(HvCallBaseYieldProcessor, typeOfYield, yieldParm);
 }
 
-//=====================================================================
-int HvCall_readLogBuffer(HvLpIndex lpindex, void *buffer, u64 bufLen);
-void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
-
-//=====================================================================
-static inline void              HvCall_sendIPI(struct paca_struct * targetPaca)
+static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts)
 {
-        HvCall1( HvCallBaseSendIPI, targetPaca->paca_index );
+        HvCall1(HvCallBaseSetEnabledInterrupts, enabledInterrupts);
 }
 
-//=====================================================================
-static inline void              HvCall_terminateMachineSrc(void)
+static inline void HvCall_setLogBufferFormatAndCodepage(int format,
+                u32 codePage)
 {
-        HvCall0( HvCallBaseTerminateMachineSrc );
+        HvCall2(HvCallBaseSetLogBufferFormatAndCodePage, format, codePage);
 }
 
-static inline void HvCall_setDABR(unsigned long val)
-{
-        HvCall1(HvCallCcSetDABR, val);
-}
+extern void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
 
-static inline void HvCall_setDebugBus(unsigned long val)
+static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
 {
-        HvCall1(HvCallBaseSetDebugBus, val);
+        HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
 }
 
 #endif /* _HVCALL_H */
diff --git a/include/asm-ppc64/iSeries/HvCallCfg.h b/include/asm-ppc64/iSeries/HvCallCfg.h
deleted file mode 100644
index 9f40f16de533..000000000000
--- a/include/asm-ppc64/iSeries/HvCallCfg.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * HvCallCfg.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-//=====================================================================================
-//
-//      This file contains the "hypervisor call" interface which is used to
-//      drive the hypervisor from the OS.
-//
-//=====================================================================================
-#ifndef _HVCALLCFG_H
-#define _HVCALLCFG_H
-
-//-------------------------------------------------------------------
-// Standard Includes
-//-------------------------------------------------------------------
-#include <asm/iSeries/HvCallSc.h>
-#include <asm/iSeries/HvTypes.h>
-
-//-------------------------------------------------------------------------------------
-// Constants
-//-------------------------------------------------------------------------------------
-
-enum HvCallCfg_ReqQual
-{
-        HvCallCfg_Cur   = 0,
-        HvCallCfg_Init  = 1,
-        HvCallCfg_Max   = 2,
-        HvCallCfg_Min   = 3
-};
-
-#define HvCallCfgGetLps                                 HvCallCfg +  0
-#define HvCallCfgGetActiveLpMap                         HvCallCfg +  1
-#define HvCallCfgGetLpVrmIndex                          HvCallCfg +  2
-#define HvCallCfgGetLpMinSupportedPlicVrmIndex          HvCallCfg +  3
-#define HvCallCfgGetLpMinCompatablePlicVrmIndex         HvCallCfg +  4
-#define HvCallCfgGetLpVrmName                           HvCallCfg +  5 
-#define HvCallCfgGetSystemPhysicalProcessors            HvCallCfg +  6
-#define HvCallCfgGetPhysicalProcessors                  HvCallCfg +  7
-#define HvCallCfgGetSystemMsChunks                      HvCallCfg +  8
-#define HvCallCfgGetMsChunks                            HvCallCfg +  9
-#define HvCallCfgGetInteractivePercentage               HvCallCfg + 10
-#define HvCallCfgIsBusDedicated                         HvCallCfg + 11
-#define HvCallCfgGetBusOwner                            HvCallCfg + 12
-#define HvCallCfgGetBusAllocation                       HvCallCfg + 13
-#define HvCallCfgGetBusUnitOwner                        HvCallCfg + 14
-#define HvCallCfgGetBusUnitAllocation                   HvCallCfg + 15
-#define HvCallCfgGetVirtualBusPool                      HvCallCfg + 16
-#define HvCallCfgGetBusUnitInterruptProc                HvCallCfg + 17
-#define HvCallCfgGetConfiguredBusUnitsForIntProc        HvCallCfg + 18
-#define HvCallCfgGetRioSanBusPool                       HvCallCfg + 19
-#define HvCallCfgGetSharedPoolIndex                     HvCallCfg + 20
-#define HvCallCfgGetSharedProcUnits                     HvCallCfg + 21
-#define HvCallCfgGetNumProcsInSharedPool                HvCallCfg + 22
-#define HvCallCfgRouter23                               HvCallCfg + 23
-#define HvCallCfgRouter24                               HvCallCfg + 24
-#define HvCallCfgRouter25                               HvCallCfg + 25
-#define HvCallCfgRouter26                               HvCallCfg + 26
-#define HvCallCfgRouter27                               HvCallCfg + 27
-#define HvCallCfgGetMinRuntimeMsChunks                  HvCallCfg + 28
-#define HvCallCfgSetMinRuntimeMsChunks                  HvCallCfg + 29
-#define HvCallCfgGetVirtualLanIndexMap                  HvCallCfg + 30
-#define HvCallCfgGetLpExecutionMode                     HvCallCfg + 31
-#define HvCallCfgGetHostingLpIndex                      HvCallCfg + 32
-
-//====================================================================
-static inline HvLpIndex HvCallCfg_getLps(void)
-{
-        HvLpIndex retVal = HvCall0(HvCallCfgGetLps);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//====================================================================
-static inline int               HvCallCfg_isBusDedicated(u64 busIndex)
-{
-        int retVal = HvCall1(HvCallCfgIsBusDedicated,busIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//====================================================================
-static inline HvLpIndex HvCallCfg_getBusOwner(u64 busIndex)
-{
-        HvLpIndex retVal = HvCall1(HvCallCfgGetBusOwner,busIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//====================================================================
-static inline HvLpIndexMap      HvCallCfg_getBusAllocation(u64 busIndex)
-{
-        HvLpIndexMap retVal = HvCall1(HvCallCfgGetBusAllocation,busIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//====================================================================
-static inline HvLpIndexMap      HvCallCfg_getActiveLpMap(void)
-{
-        HvLpIndexMap retVal = HvCall0(HvCallCfgGetActiveLpMap);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//====================================================================
-static inline HvLpVirtualLanIndexMap    HvCallCfg_getVirtualLanIndexMap(HvLpIndex lp)
-{
-        // This is a new function in V5R1 so calls to this on older 
-        // hypervisors will return -1
-        u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
-        if(retVal == -1)
-                retVal = 0;
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getSystemMsChunks(void)
-{
-        u64 retVal = HvCall0(HvCallCfgGetSystemMsChunks);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getMsChunks(HvLpIndex lp,enum HvCallCfg_ReqQual qual)
-{
-        u64 retVal = HvCall2(HvCallCfgGetMsChunks,lp,qual);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getMinRuntimeMsChunks(HvLpIndex lp)
-{
-        // NOTE: This function was added in v5r1 so older hypervisors will return a -1 value
-        u64 retVal = HvCall1(HvCallCfgGetMinRuntimeMsChunks,lp);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_setMinRuntimeMsChunks(u64 chunks)
-{
-        u64 retVal = HvCall1(HvCallCfgSetMinRuntimeMsChunks,chunks);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getSystemPhysicalProcessors(void)
-{
-        u64 retVal = HvCall0(HvCallCfgGetSystemPhysicalProcessors);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getPhysicalProcessors(HvLpIndex lp,enum HvCallCfg_ReqQual qual)
-{
-        u64 retVal = HvCall2(HvCallCfgGetPhysicalProcessors,lp,qual);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-}
-//===================================================================
-static inline u64               HvCallCfg_getConfiguredBusUnitsForInterruptProc(HvLpIndex lp,
-                                                                                u16 hvLogicalProcIndex)
-{
-        u64 retVal = HvCall2(HvCallCfgGetConfiguredBusUnitsForIntProc,lp,hvLogicalProcIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-
-}
-//==================================================================
-static inline HvLpSharedPoolIndex       HvCallCfg_getSharedPoolIndex(HvLpIndex lp)
-{
-        HvLpSharedPoolIndex retVal =
-                HvCall1(HvCallCfgGetSharedPoolIndex,lp);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-
-}
-//==================================================================
-static inline u64       HvCallCfg_getSharedProcUnits(HvLpIndex lp,enum HvCallCfg_ReqQual qual)
-{
-        u64 retVal = HvCall2(HvCallCfgGetSharedProcUnits,lp,qual);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-
-}
-//==================================================================
-static inline u64       HvCallCfg_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
-{
-        u16 retVal = HvCall1(HvCallCfgGetNumProcsInSharedPool,sPI);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-
-}
-//==================================================================
-static inline HvLpIndex HvCallCfg_getHostingLpIndex(HvLpIndex lp)
-{
-        u64 retVal = HvCall1(HvCallCfgGetHostingLpIndex,lp);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
-
-}
-
-#endif /* _HVCALLCFG_H */
diff --git a/include/asm-ppc64/iSeries/HvCallEvent.h b/include/asm-ppc64/iSeries/HvCallEvent.h
index 191ddce0c2c6..5d9a327d0122 100644
--- a/include/asm-ppc64/iSeries/HvCallEvent.h
+++ b/include/asm-ppc64/iSeries/HvCallEvent.h
@@ -1,32 +1,28 @@
 /*
  * HvCallEvent.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
-
 /*
- *      This file contains the "hypervisor call" interface which is used to
- *      drive the hypervisor from the OS.
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
  */
 #ifndef _HVCALLEVENT_H
 #define _HVCALLEVENT_H
 
-/*
- * Standard Includes
- */
 #include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 #include <asm/abs_addr.h>
@@ -71,7 +67,7 @@ typedef u64 HvLpDma_Rc;
 #define HvCallEventCloseLpEventPath                     HvCallEvent +  2
 #define HvCallEventDmaBufList                           HvCallEvent +  3
 #define HvCallEventDmaSingle                            HvCallEvent +  4
-#define HvCallEventDmaToSp                              HvCallEvent +  5 
+#define HvCallEventDmaToSp                              HvCallEvent +  5
 #define HvCallEventGetOverflowLpEvents                  HvCallEvent +  6
 #define HvCallEventGetSourceLpInstanceId                HvCallEvent +  7
 #define HvCallEventGetTargetLpInstanceId                HvCallEvent +  8
@@ -85,14 +81,12 @@ typedef u64 HvLpDma_Rc;
 
 static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex)
 {
-        HvCall1(HvCallEventGetOverflowLpEvents,queueIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall1(HvCallEventGetOverflowLpEvents, queueIndex);
 }
 
 static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex)
 {
-        HvCall1(HvCallEventSetInterLpQueueIndex,queueIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall1(HvCallEventSetInterLpQueueIndex, queueIndex);
 }
 
 static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
@@ -103,7 +97,6 @@ static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
         abs_addr = virt_to_abs(eventStackAddr);
         HvCall3(HvCallEventSetLpEventStack, queueIndex, abs_addr,
                         eventStackSize);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
 }
 
 static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
@@ -111,22 +104,18 @@ static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
 {
         HvCall2(HvCallEventSetLpEventQueueInterruptProc, queueIndex,
                         lpLogicalProcIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
 }
 
 static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent *event)
 {
         u64 abs_addr;
-        HvLpEvent_Rc retVal;
 
 #ifdef DEBUG_SENDEVENT
         printk("HvCallEvent_signalLpEvent: *event = %016lx\n ",
                         (unsigned long)event);
 #endif
         abs_addr = virt_to_abs(event);
-        retVal = (HvLpEvent_Rc)HvCall1(HvCallEventSignalLpEvent, abs_addr);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall1(HvCallEventSignalLpEvent, abs_addr);
 }
 
 static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
@@ -136,9 +125,7 @@ static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
                 u64 eventData1, u64 eventData2, u64 eventData3,
                 u64 eventData4, u64 eventData5)
 {
-        HvLpEvent_Rc retVal;
-
-        // Pack the misc bits into a single Dword to pass to PLIC
+        /* Pack the misc bits into a single Dword to pass to PLIC */
         union {
                 struct HvCallEvent_PackedParms  parms;
                 u64             dword;
@@ -152,67 +139,49 @@ static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
         packed.parms.xSourceInstId      = sourceInstanceId;
         packed.parms.xTargetInstId      = targetInstanceId;
 
-        retVal = (HvLpEvent_Rc)HvCall7(HvCallEventSignalLpEventParms,
-                        packed.dword, correlationToken, eventData1,eventData2,
-                        eventData3,eventData4, eventData5);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall7(HvCallEventSignalLpEventParms, packed.dword,
+                        correlationToken, eventData1, eventData2,
+                        eventData3, eventData4, eventData5);
 }
 
 static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
 {
         u64 abs_addr;
-        HvLpEvent_Rc retVal;
 
         abs_addr = virt_to_abs(event);
-        retVal = (HvLpEvent_Rc)HvCall1(HvCallEventAckLpEvent, abs_addr);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall1(HvCallEventAckLpEvent, abs_addr);
 }
 
 static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent *event)
 {
         u64 abs_addr;
-        HvLpEvent_Rc retVal;
 
         abs_addr = virt_to_abs(event);
-        retVal = (HvLpEvent_Rc)HvCall1(HvCallEventCancelLpEvent, abs_addr);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall1(HvCallEventCancelLpEvent, abs_addr);
 }
 
 static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(
                 HvLpIndex targetLp, HvLpEvent_Type type)
 {
-        HvLpInstanceId retVal;  
-
-        retVal = HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
 }
 
 static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(
                 HvLpIndex targetLp, HvLpEvent_Type type)
 {
-        HvLpInstanceId retVal;  
-
-        retVal = HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
 }
 
 static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp,
                 HvLpEvent_Type type)
 {
         HvCall2(HvCallEventOpenLpEventPath, targetLp, type);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
 }
 
 static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp,
                 HvLpEvent_Type type)
 {
         HvCall2(HvCallEventCloseLpEventPath, targetLp, type);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
 }
 
 static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
@@ -224,8 +193,7 @@ static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
                 /* Do these need to be converted to absolute addresses? */
                 u64 localBufList, u64 remoteBufList, u32 transferLength)
 {
-        HvLpDma_Rc retVal;
-        // Pack the misc bits into a single Dword to pass to PLIC
+        /* Pack the misc bits into a single Dword to pass to PLIC */
         union {
                 struct HvCallEvent_PackedDmaParms       parms;
                 u64             dword;
@@ -241,11 +209,8 @@ static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
         packed.parms.xLocalInstId       = localInstanceId;
         packed.parms.xRemoteInstId      = remoteInstanceId;
 
-        retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaBufList,
-                        packed.dword, localBufList, remoteBufList,
-                        transferLength);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall4(HvCallEventDmaBufList, packed.dword, localBufList,
+                        remoteBufList, transferLength);
 }
 
 static inline HvLpDma_Rc HvCallEvent_dmaSingle(HvLpEvent_Type type,
@@ -256,8 +221,7 @@ static inline HvLpDma_Rc HvCallEvent_dmaSingle(HvLpEvent_Type type,
                 HvLpDma_AddressType remoteAddressType,
                 u64 localAddrOrTce, u64 remoteAddrOrTce, u32 transferLength)
 {
-        HvLpDma_Rc retVal;
-        // Pack the misc bits into a single Dword to pass to PLIC
+        /* Pack the misc bits into a single Dword to pass to PLIC */
         union {
                 struct HvCallEvent_PackedDmaParms       parms;
                 u64             dword;
@@ -273,25 +237,17 @@ static inline HvLpDma_Rc HvCallEvent_dmaSingle(HvLpEvent_Type type,
         packed.parms.xLocalInstId       = localInstanceId;
         packed.parms.xRemoteInstId      = remoteInstanceId;
 
-        retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaSingle,
-                        packed.dword, localAddrOrTce, remoteAddrOrTce,
-                        transferLength);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return (HvLpDma_Rc)HvCall4(HvCallEventDmaSingle, packed.dword,
+                        localAddrOrTce, remoteAddrOrTce, transferLength);
 }
 
-static inline HvLpDma_Rc HvCallEvent_dmaToSp(void* local, u32 remote,
+static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
                 u32 length, HvLpDma_Direction dir)
 {
         u64 abs_addr;
-        HvLpDma_Rc retVal;
 
         abs_addr = virt_to_abs(local);
-        retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaToSp, abs_addr, remote,
-                        length, dir);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall4(HvCallEventDmaToSp, abs_addr, remote, length, dir);
 }
 
-
 #endif /* _HVCALLEVENT_H */
diff --git a/include/asm-ppc64/iSeries/HvCallHpt.h b/include/asm-ppc64/iSeries/HvCallHpt.h
index da769873d18b..43a1969230b8 100644
--- a/include/asm-ppc64/iSeries/HvCallHpt.h
+++ b/include/asm-ppc64/iSeries/HvCallHpt.h
@@ -1,17 +1,17 @@
 /*
  * HvCallHpt.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,21 +19,15 @@
 #ifndef _HVCALLHPT_H
 #define _HVCALLHPT_H
 
-//============================================================================
-//
-//      This file contains the "hypervisor call" interface which is used to
-//      drive the hypervisor from the OS.
-//
-//============================================================================
+/*
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
+ */
 
 #include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 #include <asm/mmu.h>
 
-//-----------------------------------------------------------------------------
-// Constants
-//-----------------------------------------------------------------------------
-
 #define HvCallHptGetHptAddress          HvCallHpt +  0
 #define HvCallHptGetHptPages            HvCallHpt +  1
 #define HvCallHptSetPp                  HvCallHpt +  5
@@ -47,81 +41,62 @@
 #define HvCallHptInvalidateSetSwBitsGet HvCallHpt + 18
 
 
-//============================================================================
-static inline u64               HvCallHpt_getHptAddress(void)
+static inline u64 HvCallHpt_getHptAddress(void)
 {
-        u64 retval = HvCall0(HvCallHptGetHptAddress);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retval;
+        return HvCall0(HvCallHptGetHptAddress);
 }
-//============================================================================
-static inline u64               HvCallHpt_getHptPages(void)
-{       
-        u64 retval = HvCall0(HvCallHptGetHptPages);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retval;
+
+static inline u64 HvCallHpt_getHptPages(void)
+{
+        return HvCall0(HvCallHptGetHptPages);
 }
-//=============================================================================
-static inline void              HvCallHpt_setPp(u32 hpteIndex, u8 value)
+
+static inline void HvCallHpt_setPp(u32 hpteIndex, u8 value)
 {
-        HvCall2( HvCallHptSetPp, hpteIndex, value );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall2(HvCallHptSetPp, hpteIndex, value);
 }
-//=============================================================================
-static inline void              HvCallHpt_setSwBits(u32 hpteIndex, u8 bitson, u8 bitsoff )
+
+static inline void HvCallHpt_setSwBits(u32 hpteIndex, u8 bitson, u8 bitsoff)
 {
-        HvCall3( HvCallHptSetSwBits, hpteIndex, bitson, bitsoff );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall3(HvCallHptSetSwBits, hpteIndex, bitson, bitsoff);
 }
-//=============================================================================
-static inline void              HvCallHpt_invalidateNoSyncICache(u32 hpteIndex)
-                                                
+
+static inline void HvCallHpt_invalidateNoSyncICache(u32 hpteIndex)
 {
-        HvCall1( HvCallHptInvalidateNoSyncICache, hpteIndex );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
 }
-//=============================================================================
-static inline u64               HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson, u8 bitsoff )
-                                                
+
+static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson,
+                u8 bitsoff)
 {
         u64 compressedStatus;
-        compressedStatus = HvCall4( HvCallHptInvalidateSetSwBitsGet, hpteIndex, bitson, bitsoff, 1 );
-        HvCall1( HvCallHptInvalidateNoSyncICache, hpteIndex );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+
+        compressedStatus = HvCall4(HvCallHptInvalidateSetSwBitsGet,
+                        hpteIndex, bitson, bitsoff, 1);
+        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
         return compressedStatus;
 }
-//=============================================================================
-static inline u64               HvCallHpt_findValid( HPTE *hpte, u64 vpn )
+
+static inline u64 HvCallHpt_findValid(hpte_t *hpte, u64 vpn)
 {
-        u64 retIndex = HvCall3Ret16( HvCallHptFindValid, hpte, vpn, 0, 0 );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retIndex;
+        return HvCall3Ret16(HvCallHptFindValid, hpte, vpn, 0, 0);
 }
-//=============================================================================
-static inline u64               HvCallHpt_findNextValid( HPTE *hpte, u32 hpteIndex, u8 bitson, u8 bitsoff )
+
+static inline u64 HvCallHpt_findNextValid(hpte_t *hpte, u32 hpteIndex,
+                u8 bitson, u8 bitsoff)
 {
-        u64 retIndex = HvCall3Ret16( HvCallHptFindNextValid, hpte, hpteIndex, bitson, bitsoff );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retIndex;
+        return HvCall3Ret16(HvCallHptFindNextValid, hpte, hpteIndex,
+                        bitson, bitsoff);
 }
-//=============================================================================
-static inline void              HvCallHpt_get( HPTE *hpte, u32 hpteIndex )
+
+static inline void HvCallHpt_get(hpte_t *hpte, u32 hpteIndex)
 {
-        HvCall2Ret16( HvCallHptGet, hpte, hpteIndex, 0 );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall2Ret16(HvCallHptGet, hpte, hpteIndex, 0);
 }
-//============================================================================
-static inline void              HvCallHpt_addValidate( u32 hpteIndex,
-                                                       u32 hBit,
-                                                       HPTE *hpte )
-                                                
+
+static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit, hpte_t *hpte)
 {
-        HvCall4( HvCallHptAddValidate, hpteIndex,
-                 hBit, (*((u64 *)hpte)), (*(((u64 *)hpte)+1)) );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        HvCall4(HvCallHptAddValidate, hpteIndex, hBit, hpte->v, hpte->r);
 }
 
-
-//=============================================================================
-
 #endif /* _HVCALLHPT_H */
diff --git a/include/asm-ppc64/iSeries/HvCallPci.h b/include/asm-ppc64/iSeries/HvCallPci.h
index 6887b619288e..c8d675c40f5e 100644
--- a/include/asm-ppc64/iSeries/HvCallPci.h
+++ b/include/asm-ppc64/iSeries/HvCallPci.h
@@ -1,26 +1,26 @@
-/************************************************************************/
-/* Provides the Hypervisor PCI calls for iSeries Linux Parition.        */
-/* Copyright (C) 2001  <Wayne G Holm> <IBM Corporation>                 */
-/*                                                                      */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation; either version 2 of the License, or    */
-/* (at your option) any later version.                                  */
-/*                                                                      */
-/* This program is distributed in the hope that it will be useful,      */ 
-/* but WITHOUT ANY WARRANTY; without even the implied warranty of       */
-/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the        */
-/* GNU General Public License for more details.                         */
-/*                                                                      */
-/* You should have received a copy of the GNU General Public License    */ 
-/* along with this program; if not, write to the:                       */
-/* Free Software Foundation, Inc.,                                      */ 
-/* 59 Temple Place, Suite 330,                                          */ 
-/* Boston, MA  02111-1307  USA                                          */
-/************************************************************************/
-/* Change Activity:                                                     */
-/*   Created, Jan 9, 2001                                               */
-/************************************************************************/
+/*
+ * Provides the Hypervisor PCI calls for iSeries Linux Parition.
+ * Copyright (C) 2001  <Wayne G Holm> <IBM Corporation>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the:
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330,
+ * Boston, MA  02111-1307  USA
+ *
+ * Change Activity:
+ *   Created, Jan 9, 2001
+ */
 
 #ifndef _HVCALLPCI_H
 #define _HVCALLPCI_H
@@ -34,8 +34,8 @@
  */
 struct HvCallPci_DsaAddr {
         u16             busNumber;              /* PHB index? */
-        u8              subBusNumber;           /* PCI bus number? */
-        u8              deviceId;               /* device and function? */
+        u8              subBusNumber;           /* PCI bus number? */
+        u8              deviceId;               /* device and function? */
         u8              barNumber;
         u8              reserved[3];
 };
@@ -52,34 +52,37 @@ struct HvCallPci_LoadReturn {
 
 enum HvCallPci_DeviceType {
         HvCallPci_NodeDevice    = 1,
-        HvCallPci_SpDevice      = 2,    
-        HvCallPci_IopDevice     = 3,    
-        HvCallPci_BridgeDevice  = 4,    
-        HvCallPci_MultiFunctionDevice = 5,      
-        HvCallPci_IoaDevice     = 6     
+        HvCallPci_SpDevice      = 2,
+        HvCallPci_IopDevice     = 3,
+        HvCallPci_BridgeDevice  = 4,
+        HvCallPci_MultiFunctionDevice = 5,
+        HvCallPci_IoaDevice     = 6
 };
 
 
 struct HvCallPci_DeviceInfo {
-        u32     deviceType;             // See DeviceType enum for values
+        u32     deviceType;             /* See DeviceType enum for values */
 };
-    
+
 struct HvCallPci_BusUnitInfo {
-        u32     sizeReturned;           // length of data returned
-        u32     deviceType;             // see DeviceType enum for values
+        u32     sizeReturned;           /* length of data returned */
+        u32     deviceType;             /* see DeviceType enum for values */
 };
 
 struct HvCallPci_BridgeInfo {
-        struct HvCallPci_BusUnitInfo busUnitInfo;  // Generic bus unit info
-        u8              subBusNumber;           // Bus number of secondary bus
-        u8              maxAgents;              // Max idsels on secondary bus
-        u8              maxSubBusNumber;        // Max Sub Bus
-        u8              logicalSlotNumber;      // Logical Slot Number for IOA 
+        struct HvCallPci_BusUnitInfo busUnitInfo;  /* Generic bus unit info */
+        u8              subBusNumber;   /* Bus number of secondary bus */
+        u8              maxAgents;      /* Max idsels on secondary bus */
+        u8              maxSubBusNumber; /* Max Sub Bus */
+        u8              logicalSlotNumber; /* Logical Slot Number for IOA */
 };
-    
 
-//  Maximum BusUnitInfo buffer size.  Provided for clients so they can allocate
-//  a buffer big enough for any type of bus unit.  Increase as needed.
+
+/*
+ * Maximum BusUnitInfo buffer size.  Provided for clients so
+ * they can allocate a buffer big enough for any type of bus
+ * unit.  Increase as needed.
+ */
 enum {HvCallPci_MaxBusUnitInfoSize = 128};
 
 struct HvCallPci_BarParms {
@@ -89,12 +92,12 @@ struct HvCallPci_BarParms {
         u64             protectStart;
         u64             protectEnd;
         u64             relocationOffset;
-        u64             pciAddress;             
+        u64             pciAddress;
         u64             reserved[3];
-};                                      
+};
 
 enum HvCallPci_VpdType {
-        HvCallPci_BusVpd                = 1,
+        HvCallPci_BusVpd        = 1,
         HvCallPci_BusAdapterVpd = 2
 };
 
@@ -123,15 +126,13 @@ enum HvCallPci_VpdType {
 #define HvCallPciUnmaskInterrupts       HvCallPci + 49
 #define HvCallPciGetBusUnitInfo         HvCallPci + 50
 
-//============================================================================
 static inline u64 HvCallPci_configLoad8(u16 busNumber, u8 subBusNumber,
-                                        u8 deviceId, u32 offset,
-                                        u8 *value)
+                u8 deviceId, u32 offset, u8 *value)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
@@ -139,21 +140,18 @@ static inline u64 HvCallPci_configLoad8(u16 busNumber, u8 subBusNumber,
 
         HvCall3Ret16(HvCallPciConfigLoad8, &retVal, *(u64 *)&dsa, offset, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *value = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
+
 static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber,
-                                         u8 deviceId, u32 offset,
-                                         u16 *value)
+                u8 deviceId, u32 offset, u16 *value)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
@@ -161,21 +159,18 @@ static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber,
 
         HvCall3Ret16(HvCallPciConfigLoad16, &retVal, *(u64 *)&dsa, offset, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *value = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
-                                              u8 deviceId, u32 offset,
-                                              u32 *value)
+
+static inline u64 HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u32 offset, u32 *value)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
@@ -183,84 +178,61 @@ static inline u64	HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
 
         HvCall3Ret16(HvCallPciConfigLoad32, &retVal, *(u64 *)&dsa, offset, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *value = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_configStore8(u16 busNumber, u8 subBusNumber,
-                                              u8 deviceId, u32 offset,
-                                              u8  value)
+
+static inline u64 HvCallPci_configStore8(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u32 offset, u8 value)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
         dsa.deviceId = deviceId;
 
-        retVal = HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_configStore16(u16 busNumber, u8 subBusNumber,
-                                              u8 deviceId, u32 offset,
-                                              u16  value)
+
+static inline u64 HvCallPci_configStore16(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u32 offset, u16 value)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
         dsa.deviceId = deviceId;
 
-        retVal = HvCall4(HvCallPciConfigStore16, *(u64 *)&dsa, offset, value, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciConfigStore16, *(u64 *)&dsa, offset, value, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_configStore32(u16 busNumber, u8 subBusNumber,
-                                              u8 deviceId, u32 offset,
-                                              u32  value)
+
+static inline u64 HvCallPci_configStore32(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u32 offset, u32 value)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumber;
         dsa.subBusNumber = subBusNumber;
         dsa.deviceId = deviceId;
 
-        retVal = HvCall4(HvCallPciConfigStore32, *(u64 *)&dsa, offset, value, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciConfigStore32, *(u64 *)&dsa, offset, value, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_barLoad8(u16  busNumberParm,
-                                           u8           subBusParm,
-                                           u8           deviceIdParm,
-                                           u8           barNumberParm,
-                                           u64          offsetParm,
-                                           u8*          valueParm)
+
+static inline u64 HvCallPci_barLoad8(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u8 *valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
@@ -269,24 +241,19 @@ static inline u64	HvCallPci_barLoad8(u16	busNumberParm,
 
         HvCall3Ret16(HvCallPciBarLoad8, &retVal, *(u64 *)&dsa, offsetParm, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *valueParm = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_barLoad16(u16 busNumberParm,
-                                           u8           subBusParm,
-                                           u8           deviceIdParm,
-                                           u8           barNumberParm,
-                                           u64          offsetParm,
-                                           u16*         valueParm)
+
+static inline u64 HvCallPci_barLoad16(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u16 *valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
@@ -295,24 +262,19 @@ static inline u64	HvCallPci_barLoad16(u16	busNumberParm,
 
         HvCall3Ret16(HvCallPciBarLoad16, &retVal, *(u64 *)&dsa, offsetParm, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *valueParm = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_barLoad32(u16 busNumberParm,
-                                           u8           subBusParm,
-                                           u8           deviceIdParm,
-                                           u8           barNumberParm,
-                                           u64          offsetParm,
-                                           u32*         valueParm)
+
+static inline u64 HvCallPci_barLoad32(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u32 *valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
@@ -321,24 +283,19 @@ static inline u64	HvCallPci_barLoad32(u16	busNumberParm,
 
         HvCall3Ret16(HvCallPciBarLoad32, &retVal, *(u64 *)&dsa, offsetParm, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *valueParm = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_barLoad64(u16 busNumberParm,
-                                           u8           subBusParm,
-                                           u8           deviceIdParm,
-                                           u8           barNumberParm,
-                                           u64          offsetParm,
-                                           u64*         valueParm)
+
+static inline u64 HvCallPci_barLoad64(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u64 *valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
 
-        *((u64*)&dsa) = 0;                              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
@@ -347,112 +304,81 @@ static inline u64	HvCallPci_barLoad64(u16	busNumberParm,
 
         HvCall3Ret16(HvCallPciBarLoad64, &retVal, *(u64 *)&dsa, offsetParm, 0);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         *valueParm = retVal.value;
 
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_barStore8(u16 busNumberParm,
-                                            u8          subBusParm,
-                                            u8          deviceIdParm,
-                                            u8          barNumberParm,
-                                            u64         offsetParm,
-                                            u8          valueParm)
+
+static inline u64 HvCallPci_barStore8(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u8 valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
-                                
+
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
         dsa.barNumber = barNumberParm;
 
-        retVal = HvCall4(HvCallPciBarStore8, *(u64 *)&dsa, offsetParm, valueParm, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciBarStore8, *(u64 *)&dsa, offsetParm,
+                        valueParm, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_barStore16(u16        busNumberParm,
-                                             u8         subBusParm,
-                                             u8         deviceIdParm,
-                                             u8         barNumberParm,
-                                             u64        offsetParm,
-                                             u16        valueParm)
+
+static inline u64 HvCallPci_barStore16(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u16 valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
-                                
+
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
         dsa.barNumber = barNumberParm;
 
-        retVal = HvCall4(HvCallPciBarStore16, *(u64 *)&dsa, offsetParm, valueParm, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciBarStore16, *(u64 *)&dsa, offsetParm,
+                        valueParm, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_barStore32(u16        busNumberParm,
-                                             u8         subBusParm,
-                                             u8         deviceIdParm,
-                                             u8         barNumberParm,
-                                             u64        offsetParm,
-                                             u32        valueParm)
+
+static inline u64 HvCallPci_barStore32(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u32 valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
-                                
+
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
         dsa.barNumber = barNumberParm;
 
-        retVal = HvCall4(HvCallPciBarStore32, *(u64 *)&dsa, offsetParm, valueParm, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciBarStore32, *(u64 *)&dsa, offsetParm,
+                        valueParm, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_barStore64(u16        busNumberParm,
-                                             u8         subBusParm,
-                                             u8         deviceIdParm,
-                                             u8         barNumberParm,
-                                             u64        offsetParm,
-                                             u64        valueParm)
+
+static inline u64 HvCallPci_barStore64(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 offsetParm,
+                u64 valueParm)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
-                                
+
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
         dsa.barNumber = barNumberParm;
 
-        retVal = HvCall4(HvCallPciBarStore64, *(u64 *)&dsa, offsetParm, valueParm, 0);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall4(HvCallPciBarStore64, *(u64 *)&dsa, offsetParm,
+                        valueParm, 0);
 }
-//============================================================================
-static inline u64       HvCallPci_eoi(u16       busNumberParm,
-                                      u8        subBusParm,  
-                                      u8        deviceIdParm)
+
+static inline u64 HvCallPci_eoi(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm)
 {
         struct HvCallPci_DsaAddr dsa;
         struct HvCallPci_LoadReturn retVal;
@@ -465,20 +391,13 @@ static inline u64	HvCallPci_eoi(u16	busNumberParm,
 
         HvCall1Ret16(HvCallPciEoi, &retVal, *(u64*)&dsa);
 
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
         return retVal.rc;
 }
-//============================================================================
-static inline u64       HvCallPci_getBarParms(u16       busNumberParm,
-                                              u8        subBusParm,  
-                                              u8        deviceIdParm,
-                                              u8        barNumberParm,
-                                              u64       parms,
-                                              u32       sizeofParms)
+
+static inline u64 HvCallPci_getBarParms(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u8 barNumberParm, u64 parms, u32 sizeofParms)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
 
@@ -487,62 +406,41 @@ static inline u64	HvCallPci_getBarParms(u16	busNumberParm,
         dsa.deviceId = deviceIdParm;
         dsa.barNumber = barNumberParm;
 
-        retVal = HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms);
 }
-//============================================================================
-static inline u64       HvCallPci_maskFisr(u16  busNumberParm,
-                                           u8   subBusParm,  
-                                           u8   deviceIdParm,
-                                           u64  fisrMask)
+
+static inline u64 HvCallPci_maskFisr(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 fisrMask)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask);
 }
-//============================================================================
-static inline u64       HvCallPci_unmaskFisr(u16        busNumberParm,
-                                             u8         subBusParm,  
-                                             u8         deviceIdParm,
-                                             u64        fisrMask)
+
+static inline u64 HvCallPci_unmaskFisr(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 fisrMask)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask);
 }
-//============================================================================
-static inline u64       HvCallPci_setSlotReset(u16              busNumberParm,
-                                               u8               subBusParm,
-                                               u8               deviceIdParm,
-                                               u64              onNotOff)
+
+static inline u64 HvCallPci_setSlotReset(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 onNotOff)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
 
@@ -550,21 +448,13 @@ static inline u64	HvCallPci_setSlotReset(u16		busNumberParm,
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall2(HvCallPciSetSlotReset, *(u64*)&dsa, onNotOff);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall2(HvCallPciSetSlotReset, *(u64*)&dsa, onNotOff);
 }
-//============================================================================
-static inline u64       HvCallPci_getDeviceInfo(u16     busNumberParm,
-                                                u8      subBusParm,  
-                                                u8      deviceNumberParm,
-                                                u64     parms,
-                                                u32     sizeofParms)
+
+static inline u64 HvCallPci_getDeviceInfo(u16 busNumberParm, u8 subBusParm,
+                u8 deviceNumberParm, u64 parms, u32 sizeofParms)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
         *((u64*)&dsa) = 0;
 
@@ -572,102 +462,72 @@ static inline u64	HvCallPci_getDeviceInfo(u16	busNumberParm,
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceNumberParm << 4;
 
-        retVal = HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms);
 }
-//============================================================================
-static inline u64       HvCallPci_maskInterrupts(u16    busNumberParm,
-                                                 u8     subBusParm,  
-                                                 u8     deviceIdParm,
-                                                 u64    interruptMask)
+
+static inline u64 HvCallPci_maskInterrupts(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 interruptMask)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask);
 }
-//============================================================================
-static inline u64       HvCallPci_unmaskInterrupts(u16  busNumberParm,
-                                                 u8             subBusParm,  
-                                                 u8             deviceIdParm,
-                                                 u64            interruptMask)
+
+static inline u64 HvCallPci_unmaskInterrupts(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 interruptMask)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask);
 }
-//============================================================================
 
-static inline u64       HvCallPci_getBusUnitInfo(u16            busNumberParm,
-                                                 u8             subBusParm,  
-                                                 u8             deviceIdParm,
-                                                 u64            parms,
-                                                 u32            sizeofParms)
+static inline u64 HvCallPci_getBusUnitInfo(u16 busNumberParm, u8 subBusParm,
+                u8 deviceIdParm, u64 parms, u32 sizeofParms)
 {
         struct HvCallPci_DsaAddr dsa;
-        u64 retVal;
 
-        *((u64*)&dsa) = 0;              
+        *((u64*)&dsa) = 0;
 
         dsa.busNumber = busNumberParm;
         dsa.subBusNumber = subBusParm;
         dsa.deviceId = deviceIdParm;
 
-        retVal = HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms, sizeofParms);
-
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-
-        return retVal;
+        return HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms,
+                        sizeofParms);
 }
-//============================================================================
 
-static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm, u16 sizeParm)
+static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm,
+                u16 sizeParm)
 {
-        int xRetSize;
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm, sizeParm, HvCallPci_BusVpd);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
+                        sizeParm, HvCallPci_BusVpd);
         if (xRc == -1)
-                xRetSize = -1;
+                return -1;
         else
-                xRetSize = xRc & 0xFFFF;
-        return xRetSize;
+                return xRc & 0xFFFF;
 }
-//============================================================================
 
-static inline int HvCallPci_getBusAdapterVpd(u16 busNumParm, u64 destParm, u16 sizeParm)
+static inline int HvCallPci_getBusAdapterVpd(u16 busNumParm, u64 destParm,
+                u16 sizeParm)
 {
-        int xRetSize;
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm, sizeParm, HvCallPci_BusAdapterVpd);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
+        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
+                        sizeParm, HvCallPci_BusAdapterVpd);
         if (xRc == -1)
-                xRetSize = -1;
+                return -1;
         else
-                xRetSize = xRc & 0xFFFF;
-        return xRetSize;
+                return xRc & 0xFFFF;
 }
-//============================================================================
+
 #endif /* _HVCALLPCI_H */
diff --git a/include/asm-ppc64/iSeries/HvCallSc.h b/include/asm-ppc64/iSeries/HvCallSc.h
index eea258447642..a62cef3822f9 100644
--- a/include/asm-ppc64/iSeries/HvCallSc.h
+++ b/include/asm-ppc64/iSeries/HvCallSc.h
@@ -1,17 +1,17 @@
 /*
  * HvCallSc.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,7 +19,7 @@
 #ifndef _HVCALLSC_H
 #define _HVCALLSC_H
 
-#include <asm/iSeries/HvTypes.h>
+#include <linux/types.h>
 
 #define HvCallBase              0x8000000000000000ul
 #define HvCallCc                0x8001000000000000ul
@@ -30,22 +30,22 @@
 #define HvCallSm                0x8007000000000000ul
 #define HvCallXm                0x8009000000000000ul
 
-u64 HvCall0( u64 );
-u64 HvCall1( u64, u64 );
-u64 HvCall2( u64, u64, u64 );
-u64 HvCall3( u64, u64, u64, u64 );
-u64 HvCall4( u64, u64, u64, u64, u64 );
-u64 HvCall5( u64, u64, u64, u64, u64, u64 );
-u64 HvCall6( u64, u64, u64, u64, u64, u64, u64 );
-u64 HvCall7( u64, u64, u64, u64, u64, u64, u64, u64 );
+extern u64 HvCall0(u64);
+extern u64 HvCall1(u64, u64);
+extern u64 HvCall2(u64, u64, u64);
+extern u64 HvCall3(u64, u64, u64, u64);
+extern u64 HvCall4(u64, u64, u64, u64, u64);
+extern u64 HvCall5(u64, u64, u64, u64, u64, u64);
+extern u64 HvCall6(u64, u64, u64, u64, u64, u64, u64);
+extern u64 HvCall7(u64, u64, u64, u64, u64, u64, u64, u64);
 
-u64 HvCall0Ret16( u64, void * );
-u64 HvCall1Ret16( u64, void *, u64 );
-u64 HvCall2Ret16( u64, void *, u64, u64 );
-u64 HvCall3Ret16( u64, void *, u64, u64, u64 );
-u64 HvCall4Ret16( u64, void *, u64, u64, u64, u64 );
-u64 HvCall5Ret16( u64, void *, u64, u64, u64, u64, u64 );
-u64 HvCall6Ret16( u64, void *, u64, u64, u64, u64, u64, u64 );
-u64 HvCall7Ret16( u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64 );
+extern u64 HvCall0Ret16(u64, void *);
+extern u64 HvCall1Ret16(u64, void *, u64);
+extern u64 HvCall2Ret16(u64, void *, u64, u64);
+extern u64 HvCall3Ret16(u64, void *, u64, u64, u64);
+extern u64 HvCall4Ret16(u64, void *, u64, u64, u64, u64);
+extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
+extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
+extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
 
 #endif /* _HVCALLSC_H */
diff --git a/include/asm-ppc64/iSeries/HvCallSm.h b/include/asm-ppc64/iSeries/HvCallSm.h
index 9050c94a529d..8a3dbb071a43 100644
--- a/include/asm-ppc64/iSeries/HvCallSm.h
+++ b/include/asm-ppc64/iSeries/HvCallSm.h
@@ -1,17 +1,17 @@
 /*
  * HvCallSm.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,34 +19,20 @@
 #ifndef _HVCALLSM_H
 #define _HVCALLSM_H
 
-//============================================================================
-//
-//      This file contains the "hypervisor call" interface which is used to
-//      drive the hypervisor from the OS.
-//
-//============================================================================
+/*
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
+ */
 
-//-------------------------------------------------------------------
-// Standard Includes
-//-------------------------------------------------------------------
 #include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 
-//-----------------------------------------------------------------------------
-// Constants
-//-----------------------------------------------------------------------------
-
 #define HvCallSmGet64BitsOfAccessMap    HvCallSm  + 11
 
-
-//============================================================================
-static inline u64               HvCallSm_get64BitsOfAccessMap(
-                                        HvLpIndex lpIndex, u64 indexIntoBitMap )
+static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
+                u64 indexIntoBitMap)
 {
-        u64 retval = HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex,
-                             indexIntoBitMap );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retval;
+        return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
 }
-//============================================================================
+
 #endif /* _HVCALLSM_H */
diff --git a/include/asm-ppc64/iSeries/HvCallXm.h b/include/asm-ppc64/iSeries/HvCallXm.h
index bfb898f4db8d..8b9ba608daaf 100644
--- a/include/asm-ppc64/iSeries/HvCallXm.h
+++ b/include/asm-ppc64/iSeries/HvCallXm.h
@@ -1,30 +1,13 @@
-//============================================================================
-//                                                       Header File Id
-// Name______________:  HvCallXm.H
-//
-// Description_______:
-//
-//      This file contains the "hypervisor call" interface which is used to
-//      drive the hypervisor from SLIC.
-//
-//============================================================================
+/*
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from SLIC.
+ */
 #ifndef _HVCALLXM_H
 #define _HVCALLXM_H
 
-//-------------------------------------------------------------------
-// Forward declarations 
-//-------------------------------------------------------------------
-
-//-------------------------------------------------------------------
-// Standard Includes
-//-------------------------------------------------------------------
 #include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 
-//-----------------------------------------------------------------------------
-// Constants
-//-----------------------------------------------------------------------------
-
 #define HvCallXmGetTceTableParms        HvCallXm +  0
 #define HvCallXmTestBus                 HvCallXm +  1
 #define HvCallXmConnectBusUnit          HvCallXm +  2
@@ -33,63 +16,63 @@
 #define HvCallXmSetTce                  HvCallXm + 11
 #define HvCallXmSetTces                 HvCallXm + 13
 
+/*
+ * Structure passed to HvCallXm_getTceTableParms
+ */
+struct iommu_table_cb {
+        unsigned long   itc_busno;      /* Bus number for this tce table */
+        unsigned long   itc_start;      /* Will be NULL for secondary */
+        unsigned long   itc_totalsize;  /* Size (in pages) of whole table */
+        unsigned long   itc_offset;     /* Index into real tce table of the
+                                           start of our section */
+        unsigned long   itc_size;       /* Size (in pages) of our section */
+        unsigned long   itc_index;      /* Index of this tce table */
+        unsigned short  itc_maxtables;  /* Max num of tables for partition */
+        unsigned char   itc_virtbus;    /* Flag to indicate virtual bus */
+        unsigned char   itc_slotno;     /* IOA Tce Slot Index */
+        unsigned char   itc_rsvd[4];
+};
 
-
-//============================================================================
-static inline void              HvCallXm_getTceTableParms(u64 cb)
+static inline void HvCallXm_getTceTableParms(u64 cb)
 {
         HvCall1(HvCallXmGetTceTableParms, cb);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
 }
-//============================================================================
-static inline u64               HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
-{       
-        u64 retval = HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retval;
-}
-//============================================================================
-static inline u64               HvCallXm_setTces(u64 tceTableToken, u64 tceOffset, u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
-{       
-        u64 retval = HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
-                             tce1, tce2, tce3, tce4 );
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retval;
+
+static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
+{
+        return HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce);
 }
-//=============================================================================
-static inline u64       HvCallXm_testBus(u16 busNumber)
+
+static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset,
+                u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
 {
-        u64 retVal = HvCall1(HvCallXmTestBus, busNumber);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
+                             tce1, tce2, tce3, tce4);
 }
-//=====================================================================================
-static inline u64       HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber, u8 deviceId)
+
+static inline u64 HvCallXm_testBus(u16 busNumber)
 {
-        u64 busUnitNumber = (subBusNumber << 8) | deviceId;
-        u64 retVal = HvCall2(HvCallXmTestBusUnit, busNumber, busUnitNumber);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall1(HvCallXmTestBus, busNumber);
 }
-//=====================================================================================
-static inline u64       HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber, u8 deviceId,
-                                                u64 interruptToken)
+
+static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber,
+                u8 deviceId)
 {
-        u64 busUnitNumber = (subBusNumber << 8) | deviceId;
-        u64 queueIndex = 0; // HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard));  
+        return HvCall2(HvCallXmTestBusUnit, busNumber,
+                        (subBusNumber << 8) | deviceId);
+}
 
-        u64 retVal = HvCall5(HvCallXmConnectBusUnit, busNumber, busUnitNumber,
-                             interruptToken, 0, queueIndex);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u64 interruptToken)
+{
+        return HvCall5(HvCallXmConnectBusUnit, busNumber,
+                        (subBusNumber << 8) | deviceId, interruptToken, 0,
+                        0 /* HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)) */);
 }
-//=====================================================================================
-static inline u64       HvCallXm_loadTod(void)
+
+static inline u64 HvCallXm_loadTod(void)
 {
-        u64 retVal = HvCall0(HvCallXmLoadTod);
-        // getPaca()->adjustHmtForNoOfSpinLocksHeld();
-        return retVal;
+        return HvCall0(HvCallXmLoadTod);
 }
-//=====================================================================================
 
 #endif /* _HVCALLXM_H */
diff --git a/include/asm-ppc64/iSeries/HvLpConfig.h b/include/asm-ppc64/iSeries/HvLpConfig.h
index bdbd70f42c9d..f1cf1e70ca3c 100644
--- a/include/asm-ppc64/iSeries/HvLpConfig.h
+++ b/include/asm-ppc64/iSeries/HvLpConfig.h
@@ -1,17 +1,17 @@
 /*
  * HvLpConfig.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,262 +19,120 @@
 #ifndef _HVLPCONFIG_H
 #define _HVLPCONFIG_H
 
-//===========================================================================
-//
-//      This file contains the interface to the LPAR configuration data
-//  to determine which resources should be allocated to each partition.
-//
-//===========================================================================
+/*
+ * This file contains the interface to the LPAR configuration data
+ * to determine which resources should be allocated to each partition.
+ */
 
-#include <asm/iSeries/HvCallCfg.h>
+#include <asm/iSeries/HvCallSc.h>
 #include <asm/iSeries/HvTypes.h>
 #include <asm/iSeries/ItLpNaca.h>
-#include <asm/iSeries/LparData.h>
 
-//-------------------------------------------------------------------
-// Constants
-//-------------------------------------------------------------------
+enum {
+        HvCallCfg_Cur   = 0,
+        HvCallCfg_Init  = 1,
+        HvCallCfg_Max   = 2,
+        HvCallCfg_Min   = 3
+};
+
+#define HvCallCfgGetSystemPhysicalProcessors            HvCallCfg +  6
+#define HvCallCfgGetPhysicalProcessors                  HvCallCfg +  7
+#define HvCallCfgGetMsChunks                            HvCallCfg +  9
+#define HvCallCfgGetSharedPoolIndex                     HvCallCfg + 20
+#define HvCallCfgGetSharedProcUnits                     HvCallCfg + 21
+#define HvCallCfgGetNumProcsInSharedPool                HvCallCfg + 22
+#define HvCallCfgGetVirtualLanIndexMap                  HvCallCfg + 30
+#define HvCallCfgGetHostingLpIndex                      HvCallCfg + 32
 
 extern HvLpIndex HvLpConfig_getLpIndex_outline(void);
 
-//===================================================================
 static inline HvLpIndex HvLpConfig_getLpIndex(void)
 {
         return itLpNaca.xLpIndex;
 }
-//===================================================================
+
 static inline HvLpIndex HvLpConfig_getPrimaryLpIndex(void)
 {
         return itLpNaca.xPrimaryLpIndex;
 }
-//=================================================================
-static inline HvLpIndex HvLpConfig_getLps(void)
-{
-        return HvCallCfg_getLps();
-}
-//=================================================================
-static inline HvLpIndexMap      HvLpConfig_getActiveLpMap(void)
-{
-        return HvCallCfg_getActiveLpMap();
-}
-//=================================================================
-static inline u64               HvLpConfig_getSystemMsMegs(void)
-{
-        return HvCallCfg_getSystemMsChunks() / HVCHUNKSPERMEG;
-}
-//=================================================================
-static inline u64               HvLpConfig_getSystemMsChunks(void)
-{
-        return HvCallCfg_getSystemMsChunks();
-}
-//=================================================================
-static inline u64               HvLpConfig_getSystemMsPages(void)
-{
-        return HvCallCfg_getSystemMsChunks() * HVPAGESPERCHUNK;
-}
-//================================================================
-static inline u64               HvLpConfig_getMsMegs(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur) / HVCHUNKSPERMEG;
-}
-//================================================================
-static inline u64               HvLpConfig_getMsChunks(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur);
-}
-//================================================================
-static inline u64               HvLpConfig_getMsPages(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur) * HVPAGESPERCHUNK;
-}
-//================================================================
-static inline u64               HvLpConfig_getMinMsMegs(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min) / HVCHUNKSPERMEG;
-}
-//================================================================
-static inline u64               HvLpConfig_getMinMsChunks(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min);
-}
-//================================================================
-static inline u64               HvLpConfig_getMinMsPages(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min) * HVPAGESPERCHUNK;
-}
-//================================================================
-static inline u64               HvLpConfig_getMinRuntimeMsMegs(void)
-{
-        return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex()) / HVCHUNKSPERMEG;
-}
-//===============================================================
-static inline u64               HvLpConfig_getMinRuntimeMsChunks(void)
-{
-        return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex());
-}
-//===============================================================
-static inline u64               HvLpConfig_getMinRuntimeMsPages(void)
-{
-        return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex()) * HVPAGESPERCHUNK;
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxMsMegs(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max) / HVCHUNKSPERMEG;
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxMsChunks(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxMsPages(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max) * HVPAGESPERCHUNK;
-}
-//===============================================================
-static inline u64               HvLpConfig_getInitMsMegs(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init) / HVCHUNKSPERMEG;
-}
-//===============================================================
-static inline u64               HvLpConfig_getInitMsChunks(void)
-{
-        return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init);
-}
-//===============================================================
-static inline u64               HvLpConfig_getInitMsPages(void)
-{    return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init) * HVPAGESPERCHUNK;
-}
-//===============================================================
-static inline u64               HvLpConfig_getSystemPhysicalProcessors(void)
-{
-        return HvCallCfg_getSystemPhysicalProcessors();
-}
-//===============================================================
-static inline u64               HvLpConfig_getSystemLogicalProcessors(void)
-{
-        return HvCallCfg_getSystemPhysicalProcessors() * (/*getPaca()->getSecondaryThreadCount() +*/ 1);
-}
-//===============================================================
-static inline u64               HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
-{
-        return HvCallCfg_getNumProcsInSharedPool(sPI);
-}
-//===============================================================
-static inline u64               HvLpConfig_getPhysicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Cur);
-}
-//===============================================================
-static inline u64               HvLpConfig_getLogicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Cur) * (/*getPaca()->getSecondaryThreadCount() +*/ 1);
-}
-//===============================================================
-static inline HvLpSharedPoolIndex       HvLpConfig_getSharedPoolIndex(void)
-{
-        return HvCallCfg_getSharedPoolIndex(HvLpConfig_getLpIndex());
-}
-//===============================================================
-static inline u64               HvLpConfig_getSharedProcUnits(void)
-{
-        return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Cur);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMinSharedProcUnits(void)
-{
-        return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Min);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxSharedProcUnits(void)
-{
-        return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Max);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMinPhysicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Min);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMinLogicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Min) * (/*getPaca()->getSecondaryThreadCount() +*/ 1);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxPhysicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Max);
-}
-//===============================================================
-static inline u64               HvLpConfig_getMaxLogicalProcessors(void)
-{
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Max) * (/*getPaca()->getSecondaryThreadCount() +*/ 1);
-}
-//===============================================================
-static inline u64               HvLpConfig_getInitPhysicalProcessors(void)
+
+static inline u64 HvLpConfig_getMsChunks(void)
 {
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Init);
+        return HvCall2(HvCallCfgGetMsChunks, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
 }
-//===============================================================
-static inline u64               HvLpConfig_getInitLogicalProcessors(void)
+
+static inline u64 HvLpConfig_getSystemPhysicalProcessors(void)
 {
-        return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Init) * (/*getPaca()->getSecondaryThreadCount() +*/ 1);
+        return HvCall0(HvCallCfgGetSystemPhysicalProcessors);
 }
-//================================================================
-static inline HvLpVirtualLanIndexMap    HvLpConfig_getVirtualLanIndexMap(void)
+
+static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
 {
-        return HvCallCfg_getVirtualLanIndexMap(HvLpConfig_getLpIndex_outline());
+        return (u16)HvCall1(HvCallCfgGetNumProcsInSharedPool, sPI);
 }
-//===============================================================
-static inline HvLpVirtualLanIndexMap    HvLpConfig_getVirtualLanIndexMapForLp(HvLpIndex lp)
+
+static inline u64 HvLpConfig_getPhysicalProcessors(void)
 {
-        return HvCallCfg_getVirtualLanIndexMap(lp);
+        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
 }
-//================================================================
-static inline HvLpIndex HvLpConfig_getBusOwner(HvBusNumber busNumber)
+
+static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void)
 {
-        return HvCallCfg_getBusOwner(busNumber);
+        return HvCall1(HvCallCfgGetSharedPoolIndex, HvLpConfig_getLpIndex());
 }
-//===============================================================
-static inline int               HvLpConfig_isBusDedicated(HvBusNumber busNumber)
+
+static inline u64 HvLpConfig_getSharedProcUnits(void)
 {
-        return HvCallCfg_isBusDedicated(busNumber);
+        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
 }
-//================================================================
-static inline HvLpIndexMap      HvLpConfig_getBusAllocation(HvBusNumber busNumber)
+
+static inline u64 HvLpConfig_getMaxSharedProcUnits(void)
 {
-        return HvCallCfg_getBusAllocation(busNumber);
+        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Max);
 }
-//================================================================
-// returns the absolute real address of the load area
-static inline u64               HvLpConfig_getLoadAddress(void)
+
+static inline u64 HvLpConfig_getMaxPhysicalProcessors(void)
 {
-        return itLpNaca.xLoadAreaAddr & 0x7fffffffffffffff;
+        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Max);
 }
-//================================================================
-static inline u64               HvLpConfig_getLoadPages(void)
-{
-        return itLpNaca.xLoadAreaChunks * HVPAGESPERCHUNK;
+
+static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(
+                HvLpIndex lp)
+{
+        /*
+         * This is a new function in V5R1 so calls to this on older
+         * hypervisors will return -1
+         */
+        u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
+        if (retVal == -1)
+                retVal = 0;
+        return retVal;
 }
-//================================================================
-static inline int               HvLpConfig_isBusOwnedByThisLp(HvBusNumber busNumber)
+
+static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void)
 {
-        HvLpIndex busOwner = HvLpConfig_getBusOwner(busNumber);
-        return (busOwner == HvLpConfig_getLpIndex());
+        return HvLpConfig_getVirtualLanIndexMapForLp(
+                        HvLpConfig_getLpIndex_outline());
 }
-//================================================================
-static inline int         HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1, HvLpIndex lp2)
+
+static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1,
+                HvLpIndex lp2)
 {
-        HvLpVirtualLanIndexMap virtualLanIndexMap1 = HvCallCfg_getVirtualLanIndexMap( lp1 );
-        HvLpVirtualLanIndexMap virtualLanIndexMap2 = HvCallCfg_getVirtualLanIndexMap( lp2 );
+        HvLpVirtualLanIndexMap virtualLanIndexMap1 =
+                HvLpConfig_getVirtualLanIndexMapForLp(lp1);
+        HvLpVirtualLanIndexMap virtualLanIndexMap2 =
+                HvLpConfig_getVirtualLanIndexMapForLp(lp2);
         return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0);
 }
-//================================================================
-static inline HvLpIndex         HvLpConfig_getHostingLpIndex(HvLpIndex lp)
+
+static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
 {
-        return HvCallCfg_getHostingLpIndex(lp);
+        return HvCall1(HvCallCfgGetHostingLpIndex, lp);
 }
-//================================================================
 
 #endif /* _HVLPCONFIG_H */
diff --git a/include/asm-ppc64/iSeries/HvLpEvent.h b/include/asm-ppc64/iSeries/HvLpEvent.h
index 30936e433064..865000de79b6 100644
--- a/include/asm-ppc64/iSeries/HvLpEvent.h
+++ b/include/asm-ppc64/iSeries/HvLpEvent.h
@@ -1,27 +1,24 @@
 /*
  * HvLpEvent.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-//======================================================================
-//
-//      This file contains the class for HV events in the system.
-//
-//=====================================================================
+/* This file contains the class for HV events in the system. */
+
 #ifndef _HVLPEVENT_H
 #define _HVLPEVENT_H
 
@@ -30,69 +27,70 @@
 #include <asm/iSeries/HvTypes.h>
 #include <asm/iSeries/HvCallEvent.h>
 
-//=====================================================================
-//
-// HvLpEvent is the structure for Lp Event messages passed between
-// partitions through PLIC. 
-//
-//=====================================================================
-
-struct HvEventFlags
-{
-        u8      xValid:1;               // Indicates a valid request    x00-x00
-        u8      xRsvd1:4;               // Reserved                     ...
-        u8      xAckType:1;             // Immediate or deferred        ...
-        u8      xAckInd:1;              // Indicates if ACK required    ...
-        u8      xFunction:1;            // Interrupt or Acknowledge     ...
+/*
+ * HvLpEvent is the structure for Lp Event messages passed between
+ * partitions through PLIC.
+ */
+
+struct HvEventFlags {
+        u8      xValid:1;       /* Indicates a valid request    x00-x00 */
+        u8      xRsvd1:4;       /* Reserved                     ... */
+        u8      xAckType:1;     /* Immediate or deferred        ... */
+        u8      xAckInd:1;      /* Indicates if ACK required    ... */
+        u8      xFunction:1;    /* Interrupt or Acknowledge     ... */
 };
 
 
-struct HvLpEvent
-{
-        struct HvEventFlags xFlags;     // Event flags                  x00-x00
-        u8      xType;                  // Type of message              x01-x01
-        u16     xSubtype;               // Subtype for event            x02-x03
-        u8      xSourceLp;              // Source LP                    x04-x04
-        u8      xTargetLp;              // Target LP                    x05-x05
-        u8      xSizeMinus1;            // Size of Derived class - 1    x06-x06
-        u8      xRc;                    // RC for Ack flows             x07-x07
-        u16     xSourceInstanceId;      // Source sides instance id     x08-x09
-        u16     xTargetInstanceId;      // Target sides instance id     x0A-x0B
+struct HvLpEvent {
+        struct HvEventFlags xFlags;     /* Event flags                x00-x00 */
+        u8      xType;                  /* Type of message            x01-x01 */
+        u16     xSubtype;               /* Subtype for event          x02-x03 */
+        u8      xSourceLp;              /* Source LP                  x04-x04 */
+        u8      xTargetLp;              /* Target LP                  x05-x05 */
+        u8      xSizeMinus1;            /* Size of Derived class - 1  x06-x06 */
+        u8      xRc;                    /* RC for Ack flows           x07-x07 */
+        u16     xSourceInstanceId;      /* Source sides instance id   x08-x09 */
+        u16     xTargetInstanceId;      /* Target sides instance id   x0A-x0B */
         union {
-                u32     xSubtypeData;   // Data usable by the subtype   x0C-x0F
-                u16     xSubtypeDataShort[2];   // Data as 2 shorts
-                u8      xSubtypeDataChar[4];    // Data as 4 chars
+                u32     xSubtypeData;   /* Data usable by the subtype x0C-x0F */
+                u16     xSubtypeDataShort[2];   /* Data as 2 shorts */
+                u8      xSubtypeDataChar[4];    /* Data as 4 chars */
         } x;
 
-        u64     xCorrelationToken;      // Unique value for source/type x10-x17
+        u64     xCorrelationToken;      /* Unique value for source/type x10-x17 */
 };
 
-// Lp Event handler function
 typedef void (*LpEventHandler)(struct HvLpEvent *, struct pt_regs *);
 
-// Register a handler for an event type
-//  returns 0 on success
-extern int HvLpEvent_registerHandler( HvLpEvent_Type eventType, LpEventHandler hdlr);
-
-// Unregister a handler for an event type
-//  This call will sleep until the handler being removed is guaranteed to
-//  be no longer executing on any CPU. Do not call with locks held.
-//
-//  returns 0 on success
-//  Unregister will fail if there are any paths open for the type
-extern int HvLpEvent_unregisterHandler( HvLpEvent_Type eventType );
+/* Register a handler for an event type - returns 0 on success */
+extern int HvLpEvent_registerHandler(HvLpEvent_Type eventType,
+                LpEventHandler hdlr);
 
-// Open an Lp Event Path for an event type
-//  returns 0 on success
-//  openPath will fail if there is no handler registered for the event type.
-//  The lpIndex specified is the partition index for the target partition
-//  (for VirtualIo, VirtualLan and SessionMgr) other types specify zero) 
-extern int HvLpEvent_openPath( HvLpEvent_Type eventType, HvLpIndex lpIndex );
+/*
+ * Unregister a handler for an event type
+ *
+ * This call will sleep until the handler being removed is guaranteed to
+ * be no longer executing on any CPU. Do not call with locks held.
+ *
+ *  returns 0 on success
+ *  Unregister will fail if there are any paths open for the type
+ */
+extern int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType);
 
+/*
+ * Open an Lp Event Path for an event type
+ * returns 0 on success
+ * openPath will fail if there is no handler registered for the event type.
+ * The lpIndex specified is the partition index for the target partition
+ * (for VirtualIo, VirtualLan and SessionMgr) other types specify zero)
+ */
+extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
 
-// Close an Lp Event Path for a type and partition
-//  returns 0 on sucess
-extern int HvLpEvent_closePath( HvLpEvent_Type eventType, HvLpIndex lpIndex );
+/*
+ * Close an Lp Event Path for a type and partition
+ * returns 0 on sucess
+ */
+extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
 
 #define HvLpEvent_Type_Hypervisor 0
 #define HvLpEvent_Type_MachineFac 1
@@ -141,4 +139,4 @@ extern int HvLpEvent_closePath( HvLpEvent_Type eventType, HvLpIndex lpIndex );
 #define HvLpDma_Rc_InvalidAddress 4
 #define HvLpDma_Rc_InvalidLength 5
 
-#endif // _HVLPEVENT_H
+#endif /* _HVLPEVENT_H */
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
index 183e5e738c26..c8162e5ccb21 100644
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ b/include/asm-ppc64/iSeries/HvReleaseData.h
@@ -1,17 +1,17 @@
 /*
  * HvReleaseData.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,47 +19,46 @@
 #ifndef _HVRELEASEDATA_H
 #define _HVRELEASEDATA_H
 
-//=============================================================================
-//
-//   This control block contains the critical information about the 
-//   release so that it can be changed in the future (ie, the virtual 
-//   address of the OS's NACA).
-//
+/*
+ * This control block contains the critical information about the
+ * release so that it can be changed in the future (ie, the virtual
+ * address of the OS's NACA).
+ */
 #include <asm/types.h>
 #include <asm/naca.h>
 
-//=============================================================================
-//
-//      When we IPL a secondary partition, we will check if if the 
-//      secondary xMinPlicVrmIndex > the primary xVrmIndex.  
-//      If it is then this tells PLIC that this secondary is not 
-//      supported running on this "old" of a level of PLIC.
-//
-//      Likewise, we will compare the primary xMinSlicVrmIndex to 
-//      the secondary xVrmIndex. 
-//      If the primary xMinSlicVrmDelta > secondary xVrmDelta then we 
-//      know that this PLIC does not support running an OS "that old".
-//
-//=============================================================================
+/*
+ * When we IPL a secondary partition, we will check if if the
+ * secondary xMinPlicVrmIndex > the primary xVrmIndex.
+ * If it is then this tells PLIC that this secondary is not
+ * supported running on this "old" of a level of PLIC.
+ *
+ * Likewise, we will compare the primary xMinSlicVrmIndex to
+ * the secondary xVrmIndex.
+ * If the primary xMinSlicVrmDelta > secondary xVrmDelta then we
+ * know that this PLIC does not support running an OS "that old".
+ */
+
+#define HVREL_TAGSINACTIVE      0x8000
+#define HVREL_32BIT             0x4000
+#define HVREL_NOSHAREDPROCS     0x2000
+#define HVREL_NOHMT             0x1000
 
-struct  HvReleaseData
-{
-        u32     xDesc;                  // Descriptor   "HvRD" ebcdic   x00-x03
-        u16     xSize;                  // Size of this control block   x04-x05
-        u16     xVpdAreasPtrOffset;     // Offset in NACA of ItVpdAreas x06-x07
-        struct  naca_struct * xSlicNacaAddr; // Virt addr of SLIC NACA  x08-x0F
-        u32     xMsNucDataOffset;       // Offset of Linux Mapping Data x10-x13
-        u32     xRsvd1;                 // Reserved                     x14-x17
-        u16     xTagsMode:1;            // 0 == tags active, 1 == tags inactive
-        u16     xAddressSize:1;         // 0 == 64-bit, 1 == 32-bit
-        u16     xNoSharedProcs:1;       // 0 == shared procs, 1 == no shared
-        u16     xNoHMT:1;               // 0 == allow HMT, 1 == no HMT
-        u16     xRsvd2:12;              // Reserved                     x18-x19
-        u16     xVrmIndex;              // VRM Index of OS image        x1A-x1B
-        u16     xMinSupportedPlicVrmIndex;// Min PLIC level  (soft)     x1C-x1D
-        u16     xMinCompatablePlicVrmIndex;// Min PLIC levelP (hard)    x1E-x1F
-        char    xVrmName[12];           // Displayable name             x20-x2B
-        char    xRsvd3[20];             // Reserved                     x2C-x3F
+struct HvReleaseData {
+        u32     xDesc;          /* Descriptor "HvRD" ebcdic     x00-x03 */
+        u16     xSize;          /* Size of this control block   x04-x05 */
+        u16     xVpdAreasPtrOffset; /* Offset in NACA of ItVpdAreas x06-x07 */
+        struct  naca_struct     *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
+        u32     xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
+        u32     xRsvd1;         /* Reserved                     x14-x17 */
+        u16     xFlags;
+        u16     xVrmIndex;      /* VRM Index of OS image        x1A-x1B */
+        u16     xMinSupportedPlicVrmIndex; /* Min PLIC level  (soft) x1C-x1D */
+        u16     xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
+        char    xVrmName[12];   /* Displayable name             x20-x2B */
+        char    xRsvd3[20];     /* Reserved                     x2C-x3F */
 };
 
+extern struct HvReleaseData     hvReleaseData;
+
 #endif /* _HVRELEASEDATA_H */
diff --git a/include/asm-ppc64/iSeries/HvTypes.h b/include/asm-ppc64/iSeries/HvTypes.h
index 3ec49c1aec32..b1ef2b4cb3e3 100644
--- a/include/asm-ppc64/iSeries/HvTypes.h
+++ b/include/asm-ppc64/iSeries/HvTypes.h
@@ -1,17 +1,17 @@
 /*
  * HvTypes.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,74 +19,60 @@
 #ifndef _HVTYPES_H
 #define _HVTYPES_H
 
-//===========================================================================
-//                                                             Header File Id
-// Name______________:  HvTypes.H
-//
-// Description_______:
-//
-//      General typedefs for the hypervisor.
-//
-// Declared Class(es):
-//
-//===========================================================================
+/*
+ * General typedefs for the hypervisor.
+ */
 
 #include <asm/types.h>
 
-//-------------------------------------------------------------------
-// Typedefs
-//-------------------------------------------------------------------
 typedef u8      HvLpIndex;
 typedef u16     HvLpInstanceId;
-typedef u64     HvLpTOD;
-typedef u64     HvLpSystemSerialNum;
-typedef u8      HvLpDeviceSerialNum[12];
-typedef u16     HvLpSanHwSet;
-typedef u16     HvLpBus;
-typedef u16     HvLpBoard;
-typedef u16     HvLpCard;
-typedef u8      HvLpDeviceType[4];
-typedef u8      HvLpDeviceModel[3];
-typedef u64     HvIoToken;
-typedef u8      HvLpName[8];
+typedef u64     HvLpTOD;
+typedef u64     HvLpSystemSerialNum;
+typedef u8      HvLpDeviceSerialNum[12];
+typedef u16     HvLpSanHwSet;
+typedef u16     HvLpBus;
+typedef u16     HvLpBoard;
+typedef u16     HvLpCard;
+typedef u8      HvLpDeviceType[4];
+typedef u8      HvLpDeviceModel[3];
+typedef u64     HvIoToken;
+typedef u8      HvLpName[8];
 typedef u32     HvIoId;
 typedef u64     HvRealMemoryIndex;
-typedef u32     HvLpIndexMap;           // Must hold HvMaxArchitectedLps bits!!!
+typedef u32     HvLpIndexMap;   /* Must hold HVMAXARCHITECTEDLPS bits!!! */
 typedef u16     HvLpVrmIndex;
 typedef u32     HvXmGenerationId;
-typedef u8      HvLpBusPool;                    
-typedef u8      HvLpSharedPoolIndex;            
+typedef u8      HvLpBusPool;
+typedef u8      HvLpSharedPoolIndex;
 typedef u16     HvLpSharedProcUnitsX100;
 typedef u8      HvLpVirtualLanIndex;
-typedef u16     HvLpVirtualLanIndexMap; // Must hold HvMaxArchitectedVirtualLans bits!!!
-typedef u16     HvBusNumber;            // Hypervisor Bus Number
-typedef u8      HvSubBusNumber;         // Hypervisor SubBus Number
-typedef u8      HvAgentId;              // Hypervisor DevFn
+typedef u16     HvLpVirtualLanIndexMap; /* Must hold HVMAXARCHITECTEDVIRTUALLANS bits!!! */
+typedef u16     HvBusNumber;    /* Hypervisor Bus Number */
+typedef u8      HvSubBusNumber; /* Hypervisor SubBus Number */
+typedef u8      HvAgentId;      /* Hypervisor DevFn */
+
 
+#define HVMAXARCHITECTEDLPS             32
+#define HVMAXARCHITECTEDVIRTUALLANS     16
+#define HVMAXARCHITECTEDVIRTUALDISKS    32
+#define HVMAXARCHITECTEDVIRTUALCDROMS   8
+#define HVMAXARCHITECTEDVIRTUALTAPES    8
+#define HVCHUNKSIZE                     (256 * 1024)
+#define HVPAGESIZE                      (4 * 1024)
+#define HVLPMINMEGSPRIMARY              256
+#define HVLPMINMEGSSECONDARY            64
+#define HVCHUNKSPERMEG                  4
+#define HVPAGESPERMEG                   256
+#define HVPAGESPERCHUNK                 64
 
-#define HVMAXARCHITECTEDLPS 32
-#define HVMAXARCHITECTEDVIRTUALLANS 16
-#define HVMAXARCHITECTEDVIRTUALDISKS 32
-#define HVMAXARCHITECTEDVIRTUALCDROMS 8
-#define HVMAXARCHITECTEDVIRTUALTAPES 8
-#define HVCHUNKSIZE 256 * 1024
-#define HVPAGESIZE 4 * 1024
-#define HVLPMINMEGSPRIMARY 256
-#define HVLPMINMEGSSECONDARY 64
-#define HVCHUNKSPERMEG 4
-#define HVPAGESPERMEG 256
-#define HVPAGESPERCHUNK 64
- 
-#define HvMaxArchitectedLps             ((HvLpIndex)HVMAXARCHITECTEDLPS)
-#define HvMaxArchitectedVirtualLans     ((HvLpVirtualLanIndex)16)
 #define HvLpIndexInvalid                ((HvLpIndex)0xff)
 
-//--------------------------------------------------------------------
-// Enums for the sub-components under PLIC
-// Used in HvCall  and HvPrimaryCall
-//--------------------------------------------------------------------
-enum   HvCallCompIds
-{
+/*
+ * Enums for the sub-components under PLIC
+ * Used in HvCall  and HvPrimaryCall
+ */
+enum {
         HvCallCompId = 0,
         HvCallCpuCtlsCompId = 1,
         HvCallCfgCompId = 2,
@@ -97,18 +83,18 @@ enum   HvCallCompIds
         HvCallSmCompId = 7,
         HvCallSpdCompId = 8,
         HvCallXmCompId = 9,
-        HvCallRioCompId = 10, 
+        HvCallRioCompId = 10,
         HvCallRsvd3CompId = 11,
         HvCallRsvd2CompId = 12,
         HvCallRsvd1CompId = 13,
         HvCallMaxCompId = 14,
-        HvPrimaryCallCompId = 0,    
+        HvPrimaryCallCompId = 0,
         HvPrimaryCallCfgCompId = 1,
-        HvPrimaryCallPciCompId = 2,    
+        HvPrimaryCallPciCompId = 2,
         HvPrimaryCallSmCompId = 3,
         HvPrimaryCallSpdCompId = 4,
         HvPrimaryCallXmCompId = 5,
-        HvPrimaryCallRioCompId = 6, 
+        HvPrimaryCallRioCompId = 6,
         HvPrimaryCallRsvd7CompId = 7,
         HvPrimaryCallRsvd6CompId = 8,
         HvPrimaryCallRsvd5CompId = 9,
@@ -116,7 +102,7 @@ enum   HvCallCompIds
         HvPrimaryCallRsvd3CompId = 11,
         HvPrimaryCallRsvd2CompId = 12,
         HvPrimaryCallRsvd1CompId = 13,
-        HvPrimaryCallMaxCompId = HvCallMaxCompId     
+        HvPrimaryCallMaxCompId = HvCallMaxCompId
 };
 
 struct HvLpBufferList {
diff --git a/include/asm-ppc64/iSeries/IoHriMainStore.h b/include/asm-ppc64/iSeries/IoHriMainStore.h
index ff00e865f620..45ed3ea67d06 100644
--- a/include/asm-ppc64/iSeries/IoHriMainStore.h
+++ b/include/asm-ppc64/iSeries/IoHriMainStore.h
@@ -1,17 +1,17 @@
 /*
  * IoHriMainStore.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -21,7 +21,7 @@
 #define _IOHRIMAINSTORE_H
 
 /* Main Store Vpd for Condor,iStar,sStar */
-struct IoHriMainStoreSegment4 {    
+struct IoHriMainStoreSegment4 {
         u8      msArea0Exists:1;
         u8      msArea1Exists:1;
         u8      msArea2Exists:1;
@@ -51,7 +51,7 @@ struct IoHriMainStoreSegment4 {
         u8      msArea1HasRiserVpd:1;
         u8      msArea2HasRiserVpd:1;
         u8      msArea3HasRiserVpd:1;
-        u8      reserved5:4;    
+        u8      reserved5:4;
         u8      reserved6;
         u16     reserved7;
 
@@ -82,8 +82,8 @@ struct IoHriMainStoreVpdFruData {
 };
 
 struct IoHriMainStoreAdrRangeBlock {
-        void *  blockStart      __attribute((packed));
-        void *  blockEnd        __attribute((packed));
+        void    *blockStart      __attribute((packed));
+        void    *blockEnd        __attribute((packed));
         u32     blockProcChipId __attribute((packed));
 };
 
@@ -102,7 +102,7 @@ struct IoHriMainStoreArea4 {
         u32     procNodeId                      __attribute((packed));
 
         u32     numAdrRangeBlocks               __attribute((packed));
-        struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks] __attribute((packed));
+        struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks]        __attribute((packed));
 
         struct IoHriMainStoreChipInfo1  chipInfo0       __attribute((packed));
         struct IoHriMainStoreChipInfo1  chipInfo1       __attribute((packed));
@@ -113,17 +113,17 @@ struct IoHriMainStoreArea4 {
         struct IoHriMainStoreChipInfo1  chipInfo6       __attribute((packed));
         struct IoHriMainStoreChipInfo1  chipInfo7       __attribute((packed));
 
-        void *   msRamAreaArray                 __attribute((packed));
+        void    *msRamAreaArray                 __attribute((packed));
         u32     msRamAreaArrayNumEntries        __attribute((packed));
         u32     msRamAreaArrayEntrySize         __attribute((packed));
 
         u32     numaDimmExists                  __attribute((packed));
         u32     numaDimmFunctional              __attribute((packed));
-        void *  numaDimmArray                   __attribute((packed));
+        void    *numaDimmArray                  __attribute((packed));
         u32     numaDimmArrayNumEntries         __attribute((packed));
         u32     numaDimmArrayEntrySize          __attribute((packed));
 
-        struct IoHriMainStoreVpdIdData  idData  __attribute((packed));
+        struct IoHriMainStoreVpdIdData idData   __attribute((packed));
 
         u64     powerData                       __attribute((packed));
         u64     cardAssemblyPartNum             __attribute((packed));
@@ -143,7 +143,7 @@ struct IoHriMainStoreArea4 {
 };
 
 
-struct IoHriMainStoreSegment5 {    
+struct IoHriMainStoreSegment5 {
         u16     reserved1;
         u8      reserved2;
         u8      msVpdFormat;
@@ -151,17 +151,16 @@ struct IoHriMainStoreSegment5 {
         u32     totalMainStore;
         u64     maxConfiguredMsAdr;
 
-        struct IoHriMainStoreArea4*     msAreaArray;
+        struct IoHriMainStoreArea4      *msAreaArray;
         u32     msAreaArrayNumEntries;
         u32     msAreaArrayEntrySize;
 
-        u32     msAreaExists;    
+        u32     msAreaExists;
         u32     msAreaFunctional;
 
         u64     reserved3;
 };
 
+extern u64      xMsVpd[];
 
-
-#endif // _IOHRIMAINSTORE_H
-
+#endif  /* _IOHRIMAINSTORE_H */
diff --git a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h b/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
index 965433888653..73b73d80b8b1 100644
--- a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
+++ b/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
@@ -1,17 +1,17 @@
 /*
  * IoHriProcessorVpd.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,16 +19,12 @@
 #ifndef _IOHRIPROCESSORVPD_H
 #define _IOHRIPROCESSORVPD_H
 
-//===================================================================
-//
-//      This struct maps Processor Vpd that is DMAd to SLIC by CSP 
-//
-
 #include <asm/types.h>
 
-struct IoHriProcessorVpd
-{
-
+/*
+ * This struct maps Processor Vpd that is DMAd to SLIC by CSP
+ */
+struct IoHriProcessorVpd {
         u8      xFormat;                // VPD format indicator         x00-x00
         u8      xProcStatus:8;          // Processor State              x01-x01
         u8      xSecondaryThreadCount;  // Secondary thread cnt         x02-x02
@@ -40,12 +36,12 @@ struct IoHriProcessorVpd
         u16     xRsvd2;                 // Reserved                     x06-x07
         u32     xHwNodeId;              // Hardware node id             x08-x0B
         u32     xHwProcId;              // Hardware processor id        x0C-x0F
-        
+
         u32     xTypeNum;               // Card Type/CCIN number        x10-x13
         u32     xModelNum;              // Model/Feature number         x14-x17
         u64     xSerialNum;             // Serial number                x18-x1F
-        char xPartNum[12];              // Book Part or FPU number      x20-x2B
-        char xMfgID[4];                 // Manufacturing ID             x2C-x2F
+        char    xPartNum[12];           // Book Part or FPU number      x20-x2B
+        char    xMfgID[4];              // Manufacturing ID             x2C-x2F
 
         u32     xProcFreq;              // Processor Frequency          x30-x33
         u32     xTimeBaseFreq;          // Time Base Frequency          x34-x37
@@ -71,7 +67,7 @@ struct IoHriProcessorVpd
         u32     xDataL3CacheSizeKB;     // L3 data cache size in KB     x80-x83
         u32     xDataL3CacheLineSize;   // L3 data cache block size     x84-x87
         u64     xRsvd6;                 // Reserved                     x88-x8F
-   
+
         u64     xFruLabel;              // Card Location Label          x90-x97
         u8      xSlotsOnCard;           // Slots on card (0=no slots)   x98-x98
         u8      xPartLocFlag;           // Location flag (0-pluggable 1-imbedded) x99-x99
@@ -79,10 +75,12 @@ struct IoHriProcessorVpd
         u8      xSmartCardPortNo;       // Smart card port number       x9C-x9C
         u8      xRsvd7;                 // Reserved                     x9D-x9D
         u16     xFrameIdAndRackUnit;    // Frame ID and rack unit adr   x9E-x9F
-    
+
         u8      xRsvd8[24];             // Reserved                     xA0-xB7
 
-        char xProcSrc[72];              // CSP format SRC               xB8-xFF
+        char    xProcSrc[72];           // CSP format SRC               xB8-xFF
 };
 
+extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
+
 #endif /* _IOHRIPROCESSORVPD_H */
diff --git a/include/asm-ppc64/iSeries/ItExtVpdPanel.h b/include/asm-ppc64/iSeries/ItExtVpdPanel.h
index dee6b1273031..4c546a8802b4 100644
--- a/include/asm-ppc64/iSeries/ItExtVpdPanel.h
+++ b/include/asm-ppc64/iSeries/ItExtVpdPanel.h
@@ -1,17 +1,17 @@
 /*
  * ItExtVpdPanel.h
  * Copyright (C) 2002  Dave Boutcher IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -20,39 +20,33 @@
 #define _ITEXTVPDPANEL_H
 
 /*
- *
- *      This struct maps the panel information 
+ *      This struct maps the panel information
  *
  * Warning:
  *      This data must match the architecture for the panel information
- *
  */
 
-
-/*-------------------------------------------------------------------
- * Standard Includes
- *------------------------------------------------------------------- 
-*/
 #include <asm/types.h>
 
-struct ItExtVpdPanel
-{
-  // Definition of the Extended Vpd On Panel Data Area
-  char                      systemSerial[8];
-  char                      mfgID[4];
-  char                      reserved1[24];
-  char                      machineType[4];
-  char                      systemID[6];
-  char                      somUniqueCnt[4];
-  char                      serialNumberCount;
-  char                      reserved2[7];
-  u16                       bbu3;
-  u16                       bbu2;
-  u16                       bbu1;
-  char                      xLocationLabel[8];
-  u8                        xRsvd1[6];
-  u16                       xFrameId;
-  u8                        xRsvd2[48];
+struct ItExtVpdPanel {
+        /* Definition of the Extended Vpd On Panel Data Area */
+        char    systemSerial[8];
+        char    mfgID[4];
+        char    reserved1[24];
+        char    machineType[4];
+        char    systemID[6];
+        char    somUniqueCnt[4];
+        char    serialNumberCount;
+        char    reserved2[7];
+        u16     bbu3;
+        u16     bbu2;
+        u16     bbu1;
+        char    xLocationLabel[8];
+        u8      xRsvd1[6];
+        u16     xFrameId;
+        u8      xRsvd2[48];
 };
 
-#endif /* _ITEXTVPDPANEL_H  */
+extern struct ItExtVpdPanel     xItExtVpdPanel;
+
+#endif /* _ITEXTVPDPANEL_H */
diff --git a/include/asm-ppc64/iSeries/ItIplParmsReal.h b/include/asm-ppc64/iSeries/ItIplParmsReal.h
index 4d8b430ab12d..ae3417dc599e 100644
--- a/include/asm-ppc64/iSeries/ItIplParmsReal.h
+++ b/include/asm-ppc64/iSeries/ItIplParmsReal.h
@@ -1,17 +1,17 @@
 /*
  * ItIplParmsReal.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,58 +19,53 @@
 #ifndef _ITIPLPARMSREAL_H
 #define _ITIPLPARMSREAL_H
 
-//==============================================================================
-//
-//      This struct maps the IPL Parameters DMA'd from the SP.                  
-//
-// Warning:
-//      This data must map in exactly 64 bytes and match the architecture for
-//      the IPL parms
-//
-//=============================================================================
-
+/*
+ *      This struct maps the IPL Parameters DMA'd from the SP.
+ *
+ * Warning:
+ *      This data must map in exactly 64 bytes and match the architecture for
+ *      the IPL parms
+ */
 
-//-------------------------------------------------------------------
-// Standard Includes
-//-------------------------------------------------------------------
 #include <asm/types.h>
 
-struct ItIplParmsReal
-{
-        u8      xFormat;                // Defines format of IplParms           x00-x00
-        u8      xRsvd01:6;              // Reserved                             x01-x01
-        u8      xAlternateSearch:1;     // Alternate search indicator           ...
-        u8      xUaSupplied:1;          // UA Supplied on programmed IPL        ...
-        u8      xLsUaFormat;            // Format byte for UA                   x02-x02
-        u8      xRsvd02;                // Reserved                             x03-x03
-        u32     xLsUa;                  // LS UA                                x04-x07
-        u32     xUnusedLsLid;           // First OS LID to load                 x08-x0B
-        u16     xLsBusNumber;           // LS Bus Number                        x0C-x0D
-        u8      xLsCardAdr;             // LS Card Address                      x0E-x0E
-        u8      xLsBoardAdr;            // LS Board Address                     x0F-x0F
-        u32     xRsvd03;                // Reserved                             x10-x13
-        u8      xSpcnPresent:1;         // SPCN present                         x14-x14
-        u8      xCpmPresent:1;          // CPM present                          ...
-        u8      xRsvd04:6;              // Reserved                             ...
-        u8      xRsvd05:4;              // Reserved                             x15-x15
-        u8      xKeyLock:4;             // Keylock setting                      ...
-        u8      xRsvd06:6;              // Reserved                             x16-x16
-        u8      xIplMode:2;             // Ipl mode (A|B|C|D)                   ...
-        u8      xHwIplType;             // Fast v slow v slow EC HW IPL         x17-x17
-        u16     xCpmEnabledIpl:1;       // CPM in effect when IPL initiated     x18-x19
-        u16     xPowerOnResetIpl:1;     // Indicate POR condition               ...
-        u16     xMainStorePreserved:1;  // Main Storage is preserved            ...
-        u16     xRsvd07:13;             // Reserved                             ...
-        u16     xIplSource:16;          // Ipl source                           x1A-x1B
-        u8      xIplReason:8;           // Reason for this IPL                  x1C-x1C
-        u8      xRsvd08;                // Reserved                             x1D-x1D
-        u16     xRsvd09;                // Reserved                             x1E-x1F
-        u16     xSysBoxType;            // System Box Type                      x20-x21
-        u16     xSysProcType;           // System Processor Type                x22-x23
-        u32     xRsvd10;                // Reserved                             x24-x27
-        u64     xRsvd11;                // Reserved                             x28-x2F
-        u64     xRsvd12;                // Reserved                             x30-x37
-        u64     xRsvd13;                // Reserved                             x38-x3F
+struct ItIplParmsReal {
+        u8      xFormat;                // Defines format of IplParms   x00-x00
+        u8      xRsvd01:6;              // Reserved                     x01-x01
+        u8      xAlternateSearch:1;     // Alternate search indicator   ...
+        u8      xUaSupplied:1;          // UA Supplied on programmed IPL...
+        u8      xLsUaFormat;            // Format byte for UA           x02-x02
+        u8      xRsvd02;                // Reserved                     x03-x03
+        u32     xLsUa;                  // LS UA                        x04-x07
+        u32     xUnusedLsLid;           // First OS LID to load         x08-x0B
+        u16     xLsBusNumber;           // LS Bus Number                x0C-x0D
+        u8      xLsCardAdr;             // LS Card Address              x0E-x0E
+        u8      xLsBoardAdr;            // LS Board Address             x0F-x0F
+        u32     xRsvd03;                // Reserved                     x10-x13
+        u8      xSpcnPresent:1;         // SPCN present                 x14-x14
+        u8      xCpmPresent:1;          // CPM present                  ...
+        u8      xRsvd04:6;              // Reserved                     ...
+        u8      xRsvd05:4;              // Reserved                     x15-x15
+        u8      xKeyLock:4;             // Keylock setting              ...
+        u8      xRsvd06:6;              // Reserved                     x16-x16
+        u8      xIplMode:2;             // Ipl mode (A|B|C|D)           ...
+        u8      xHwIplType;             // Fast v slow v slow EC HW IPL x17-x17
+        u16     xCpmEnabledIpl:1;       // CPM in effect when IPL initiatedx18-x19
+        u16     xPowerOnResetIpl:1;     // Indicate POR condition       ...
+        u16     xMainStorePreserved:1;  // Main Storage is preserved    ...
+        u16     xRsvd07:13;             // Reserved                     ...
+        u16     xIplSource:16;          // Ipl source                   x1A-x1B
+        u8      xIplReason:8;           // Reason for this IPL          x1C-x1C
+        u8      xRsvd08;                // Reserved                     x1D-x1D
+        u16     xRsvd09;                // Reserved                     x1E-x1F
+        u16     xSysBoxType;            // System Box Type              x20-x21
+        u16     xSysProcType;           // System Processor Type        x22-x23
+        u32     xRsvd10;                // Reserved                     x24-x27
+        u64     xRsvd11;                // Reserved                     x28-x2F
+        u64     xRsvd12;                // Reserved                     x30-x37
+        u64     xRsvd13;                // Reserved                     x38-x3F
 };
 
+extern struct ItIplParmsReal    xItIplParmsReal;
+
 #endif /* _ITIPLPARMSREAL_H */
diff --git a/include/asm-ppc64/iSeries/ItLpNaca.h b/include/asm-ppc64/iSeries/ItLpNaca.h
index 5baffddfae1b..225d0176779d 100644
--- a/include/asm-ppc64/iSeries/ItLpNaca.h
+++ b/include/asm-ppc64/iSeries/ItLpNaca.h
@@ -1,17 +1,17 @@
 /*
  * ItLpNaca.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,18 +19,15 @@
 #ifndef _ITLPNACA_H
 #define _ITLPNACA_H
 
-//=============================================================================
-//
-//      This control block contains the data that is shared between the
-//      hypervisor (PLIC) and the OS.
-//
-//=============================================================================
+#include <linux/types.h>
 
-struct ItLpNaca
-{
-//=============================================================================
+/*
+ *      This control block contains the data that is shared between the
+ *      hypervisor (PLIC) and the OS.
+ */
+
+struct ItLpNaca {
 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
-//=============================================================================
         u32     xDesc;                  // Eye catcher                  x00-x03
         u16     xSize;                  // Size of this class           x04-x05
         u16     xIntHdlrOffset;         // Offset to IntHdlr array      x06-x07
@@ -59,30 +56,25 @@ struct ItLpNaca
         u64     xLoadAreaAddr;          // ER address of load area      x28-x2F
         u32     xLoadAreaChunks;        // Chunks for the load area     x30-x33
         u32     xPaseSysCallCRMask;     // Mask used to test CR before  x34-x37
-        // doing an ASR switch on PASE
-        // system call.
-        u64     xSlicSegmentTablePtr;   // Pointer to Slic seg table.   x38-x3f
-        u8      xRsvd1_4[64];           //                              x40-x7F 
-   
-//=============================================================================
+                                        // doing an ASR switch on PASE
+                                        // system call.
+        u64     xSlicSegmentTablePtr;   // Pointer to Slic seg table.   x38-x3f
+        u8      xRsvd1_4[64];           //                              x40-x7F
+
 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
-//=============================================================================
         u8      xRsvd2_0[128];          // Reserved                     x00-x7F
 
-//=============================================================================
 // CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators
-// NB: Padding required to keep xInterrruptHdlr at x300 which is required 
+// NB: Padding required to keep xInterrruptHdlr at x300 which is required
 // for v4r4 PLIC.
-//=============================================================================
         u8      xOldLpQueue[128];       // LP Queue needed for v4r4     100-17F
         u8      xRsvd3_0[384];          // Reserved                     180-2FF
-//=============================================================================
+
 // CACHE_LINE_7-8 0x0300 - 0x03FF Contains the address of the OS interrupt
 //  handlers
-//=============================================================================
         u64     xInterruptHdlr[32];     // Interrupt handlers           300-x3FF
 };
 
-//=============================================================================
+extern struct ItLpNaca          itLpNaca;
 
 #endif /* _ITLPNACA_H */
diff --git a/include/asm-ppc64/iSeries/ItLpQueue.h b/include/asm-ppc64/iSeries/ItLpQueue.h
index 4f4dde2a638d..69b26ad74135 100644
--- a/include/asm-ppc64/iSeries/ItLpQueue.h
+++ b/include/asm-ppc64/iSeries/ItLpQueue.h
@@ -1,17 +1,17 @@
 /*
  * ItLpQueue.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,74 +19,63 @@
 #ifndef _ITLPQUEUE_H
 #define _ITLPQUEUE_H
 
-//=============================================================================
-//
-//      This control block defines the simple LP queue structure that is 
-//      shared between the hypervisor (PLIC) and the OS in order to send 
-//      events to an LP.  
-//    
+/*
+ *      This control block defines the simple LP queue structure that is
+ *      shared between the hypervisor (PLIC) and the OS in order to send
+ *      events to an LP.
+ */
 
 #include <asm/types.h>
 #include <asm/ptrace.h>
 
 struct HvLpEvent;
 
-#define ITMaxLpQueues 8
+#define ITMaxLpQueues   8
 
 #define NotUsed         0       // Queue will not be used by PLIC
 #define DedicatedIo     1       // Queue dedicated to IO processor specified
 #define DedicatedLp     2       // Queue dedicated to LP specified
 #define Shared          3       // Queue shared for both IO and LP
 
-#define LpEventStackSize 4096
-#define LpEventMaxSize   256
-#define LpEventAlign     64
+#define LpEventStackSize        4096
+#define LpEventMaxSize          256
+#define LpEventAlign            64
 
-struct ItLpQueue
-{
-//
-//  The xSlicCurEventPtr is the pointer to the next event stack entry that will
-//  become valid.  The OS must peek at this entry to determine if it is valid.
-//  PLIC will set the valid indicator as the very last store into that entry.
-//
-//  When the OS has completed processing of the event then it will mark the event
-//  as invalid so that PLIC knows it can store into that event location again.
-//
-// If the event stack fills and there are overflow events, then PLIC will set 
-// the xPlicOverflowIntPending flag in which case the OS will have to fetch the 
-// additional LP events once they have drained the event stack.
-//
-// The first 16-bytes are known by both the OS and PLIC.  The remainder of the
-// cache line is for use by the OS.
-//
-//=============================================================================
+struct hvlpevent_queue {
+/*
+ * The xSlicCurEventPtr is the pointer to the next event stack entry
+ * that will become valid.  The OS must peek at this entry to determine
+ * if it is valid.  PLIC will set the valid indicator as the very last
+ * store into that entry.
+ *
+ * When the OS has completed processing of the event then it will mark
+ * the event as invalid so that PLIC knows it can store into that event
+ * location again.
+ *
+ * If the event stack fills and there are overflow events, then PLIC
+ * will set the xPlicOverflowIntPending flag in which case the OS will
+ * have to fetch the additional LP events once they have drained the
+ * event stack.
+ *
+ * The first 16-bytes are known by both the OS and PLIC.  The remainder
+ * of the cache line is for use by the OS.
+ */
         u8      xPlicOverflowIntPending;// 0x00 Overflow events are pending
         u8      xPlicStatus;            // 0x01 DedicatedIo or DedicatedLp or NotUsed
         u16     xSlicLogicalProcIndex;  // 0x02 Logical Proc Index for correlation
         u8      xPlicRsvd[12];          // 0x04
-        char*   xSlicCurEventPtr;       // 0x10
-        char*   xSlicLastValidEventPtr; // 0x18
-        char*   xSlicEventStackPtr;     // 0x20
+        char    *xSlicCurEventPtr;      // 0x10
+        char    *xSlicLastValidEventPtr; // 0x18
+        char    *xSlicEventStackPtr;    // 0x20
         u8      xIndex;                 // 0x28 unique sequential index.
         u8      xSlicRsvd[3];           // 0x29-2b
-        u32     xInUseWord;             // 0x2C
-        u64     xLpIntCount;            // 0x30 Total Lp Int msgs processed
-        u64     xLpIntCountByType[9];   // 0x38-0x7F Event counts by type
+        spinlock_t      lock;
 };
 
-extern struct ItLpQueue xItLpQueue;
-
-extern struct HvLpEvent * ItLpQueue_getNextLpEvent( struct ItLpQueue * );
-extern int ItLpQueue_isLpIntPending( struct ItLpQueue * ); 
-extern unsigned ItLpQueue_process( struct ItLpQueue *, struct pt_regs * );
-extern void ItLpQueue_clearValid( struct HvLpEvent * );
+extern struct hvlpevent_queue hvlpevent_queue;
 
-static __inline__ void process_iSeries_events( void )
-{
-        __asm__ __volatile__ (
-        "       li      0,0x5555        \n\
-                sc"
-        : : : "r0", "r3" );     
-}
+extern int hvlpevent_is_pending(void);
+extern void process_hvlpevents(struct pt_regs *);
+extern void setup_hvlpevent_queue(void);
 
 #endif /* _ITLPQUEUE_H */
diff --git a/include/asm-ppc64/iSeries/ItLpRegSave.h b/include/asm-ppc64/iSeries/ItLpRegSave.h
index dafc4c813788..1b3087e76205 100644
--- a/include/asm-ppc64/iSeries/ItLpRegSave.h
+++ b/include/asm-ppc64/iSeries/ItLpRegSave.h
@@ -1,17 +1,17 @@
 /*
  * ItLpRegSave.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,33 +19,30 @@
 #ifndef _ITLPREGSAVE_H
 #define _ITLPREGSAVE_H
 
-//=====================================================================================
-//
-//      This control block contains the data that is shared between PLIC
-//      and the OS
-//    
-//
+/*
+ * This control block contains the data that is shared between PLIC
+ * and the OS
+ */
 
-struct ItLpRegSave
-{
+struct ItLpRegSave {
         u32     xDesc;          // Eye catcher  "LpRS" ebcdic   000-003
         u16     xSize;          // Size of this class           004-005
         u8      xInUse;         // Area is live                 006-007
-        u8      xRsvd1[9];      // Reserved                     007-00F
+        u8      xRsvd1[9];      // Reserved                     007-00F
 
-        u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F 
+        u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
         u32     xCTRL;          // Control Register             170-173
-        u32     xDEC;           // Decrementer                  174-177    
+        u32     xDEC;           // Decrementer                  174-177
         u32     xFPSCR;         // FP Status and Control Reg    178-17B
         u32     xPVR;           // Processor Version Number     17C-17F
-    
+
         u64     xMMCR0;         // Monitor Mode Control Reg 0   180-187
         u32     xPMC1;          // Perf Monitor Counter 1       188-18B
         u32     xPMC2;          // Perf Monitor Counter 2       18C-18F
         u32     xPMC3;          // Perf Monitor Counter 3       190-193
         u32     xPMC4;          // Perf Monitor Counter 4       194-197
         u32     xPIR;           // Processor ID Reg             198-19B
-    
+
         u32     xMMCR1;         // Monitor Mode Control Reg 1   19C-19F
         u32     xMMCRA;         // Monitor Mode Control Reg A   1A0-1A3
         u32     xPMC5;          // Perf Monitor Counter 5       1A4-1A7
@@ -57,17 +54,17 @@ struct ItLpRegSave
         u32     xRsvd;          // Reserved                     1BC-1BF
 
         u64     xACCR;          // Address Compare Control Reg  1C0-1C7
-        u64     xIMR;           // Instruction Match Register   1C8-1CF    
-        u64     xSDR1;          // Storage Description Reg 1    1D0-1D7    
+        u64     xIMR;           // Instruction Match Register   1C8-1CF
+        u64     xSDR1;          // Storage Description Reg 1    1D0-1D7
         u64     xSPRG0;         // Special Purpose Reg General0 1D8-1DF
         u64     xSPRG1;         // Special Purpose Reg General1 1E0-1E7
         u64     xSPRG2;         // Special Purpose Reg General2 1E8-1EF
         u64     xSPRG3;         // Special Purpose Reg General3 1F0-1F7
         u64     xTB;            // Time Base Register           1F8-1FF
-   
+
         u64     xFPR[32];       // Floating Point Registers     200-2FF
 
-        u64     xMSR;           // Machine State Register       300-307
+        u64     xMSR;           // Machine State Register       300-307
         u64     xNIA;           // Next Instruction Address     308-30F
 
         u64     xDABR;          // Data Address Breakpoint Reg  310-317
@@ -76,8 +73,8 @@ struct ItLpRegSave
         u64     xHID0;          // HW Implementation Dependent0 320-327
 
         u64     xHID4;          // HW Implementation Dependent4 328-32F
-        u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
-        u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
+        u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
+        u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
         u64     xSDAR;          // Sample Data Address Register 340-347
         u64     xSIAR;          // Sample Inst Address Register 348-34F
 
diff --git a/include/asm-ppc64/iSeries/ItSpCommArea.h b/include/asm-ppc64/iSeries/ItSpCommArea.h
index f1b56f9e11e2..5535f8271c9f 100644
--- a/include/asm-ppc64/iSeries/ItSpCommArea.h
+++ b/include/asm-ppc64/iSeries/ItSpCommArea.h
@@ -1,29 +1,27 @@
 /*
  * ItSpCommArea.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-
 #ifndef _ITSPCOMMAREA_H
 #define _ITSPCOMMAREA_H
 
 
-struct SpCommArea
-{
+struct SpCommArea {
         u32     xDesc;                  // Descriptor (only in new formats)     000-003
         u8      xFormat;                // Format (only in new formats)         004-004
         u8      xRsvd1[11];             // Reserved                             005-00F
diff --git a/include/asm-ppc64/iSeries/ItVpdAreas.h b/include/asm-ppc64/iSeries/ItVpdAreas.h
index d120439f30a5..71b3ad24f95a 100644
--- a/include/asm-ppc64/iSeries/ItVpdAreas.h
+++ b/include/asm-ppc64/iSeries/ItVpdAreas.h
@@ -1,17 +1,17 @@
 /*
  * ItVpdAreas.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,78 +19,71 @@
 #ifndef _ITVPDAREAS_H
 #define _ITVPDAREAS_H
 
-//=====================================================================================
-//
-//      This file defines the address and length of all of the VPD area passed to
-//      the OS from PLIC (most of which start from the SP).
-//
+/*
+ * This file defines the address and length of all of the VPD area passed to
+ * the OS from PLIC (most of which start from the SP).
+ */
 
 #include <asm/types.h>
 
-// VPD Entry index is carved in stone - cannot be changed (easily).
-#define ItVpdCecVpd                                0
-#define ItVpdDynamicSpace                          1
-#define ItVpdExtVpd                                2
-#define ItVpdExtVpdOnPanel                         3
-#define ItVpdFirstPaca                             4
-#define ItVpdIoVpd                                 5
-#define ItVpdIplParms                              6
-#define ItVpdMsVpd                                 7
-#define ItVpdPanelVpd                              8
-#define ItVpdLpNaca                                9
-#define ItVpdBackplaneAndMaybeClockCardVpd        10 
-#define ItVpdRecoveryLogBuffer                    11
-#define ItVpdSpCommArea                           12
-#define ItVpdSpLogBuffer                          13
-#define ItVpdSpLogBufferSave                      14
-#define ItVpdSpCardVpd                            15
-#define ItVpdFirstProcVpd                         16    
-#define ItVpdApModelVpd                           17
-#define ItVpdClockCardVpd                         18
-#define ItVpdBusExtCardVpd                        19
-#define ItVpdProcCapacityVpd                      20
-#define ItVpdInteractiveCapacityVpd               21
-#define ItVpdFirstSlotLabel                       22
-#define ItVpdFirstLpQueue                         23
-#define ItVpdFirstL3CacheVpd                      24    
-#define ItVpdFirstProcFruVpd                      25
-
-#define ItVpdMaxEntries                           26
+/* VPD Entry index is carved in stone - cannot be changed (easily). */
+#define ItVpdCecVpd                             0
+#define ItVpdDynamicSpace                       1
+#define ItVpdExtVpd                             2
+#define ItVpdExtVpdOnPanel                      3
+#define ItVpdFirstPaca                          4
+#define ItVpdIoVpd                              5
+#define ItVpdIplParms                           6
+#define ItVpdMsVpd                              7
+#define ItVpdPanelVpd                           8
+#define ItVpdLpNaca                             9
+#define ItVpdBackplaneAndMaybeClockCardVpd      10
+#define ItVpdRecoveryLogBuffer                  11
+#define ItVpdSpCommArea                         12
+#define ItVpdSpLogBuffer                        13
+#define ItVpdSpLogBufferSave                    14
+#define ItVpdSpCardVpd                          15
+#define ItVpdFirstProcVpd                       16
+#define ItVpdApModelVpd                         17
+#define ItVpdClockCardVpd                       18
+#define ItVpdBusExtCardVpd                      19
+#define ItVpdProcCapacityVpd                    20
+#define ItVpdInteractiveCapacityVpd             21
+#define ItVpdFirstSlotLabel                     22
+#define ItVpdFirstLpQueue                       23
+#define ItVpdFirstL3CacheVpd                    24
+#define ItVpdFirstProcFruVpd                    25
 
+#define ItVpdMaxEntries                         26
 
-#define ItDmaMaxEntries                           10
+#define ItDmaMaxEntries                         10
 
-#define ItVpdAreasMaxSlotLabels          192 
+#define ItVpdAreasMaxSlotLabels                 192
 
 
-struct SlicVpdAdrs {
-        u32     pad1;
-        void *  vpdAddr;
+struct ItVpdAreas {
+        u32     xSlicDesc;              // Descriptor                   000-003
+        u16     xSlicSize;              // Size of this control block   004-005
+        u16     xPlicAdjustVpdLens:1;   // Flag to indicate new interface006-007
+        u16     xRsvd1:15;              // Reserved bits                ...
+        u16     xSlicVpdEntries;        // Number of VPD entries        008-009
+        u16     xSlicDmaEntries;        // Number of DMA entries        00A-00B
+        u16     xSlicMaxLogicalProcs;   // Maximum logical processors   00C-00D
+        u16     xSlicMaxPhysicalProcs;  // Maximum physical processors  00E-00F
+        u16     xSlicDmaToksOffset;     // Offset into this of array    010-011
+        u16     xSlicVpdAdrsOffset;     // Offset into this of array    012-013
+        u16     xSlicDmaLensOffset;     // Offset into this of array    014-015
+        u16     xSlicVpdLensOffset;     // Offset into this of array    016-017
+        u16     xSlicMaxSlotLabels;     // Maximum number of slot labels018-019
+        u16     xSlicMaxLpQueues;       // Maximum number of LP Queues  01A-01B
+        u8      xRsvd2[4];              // Reserved                     01C-01F
+        u64     xRsvd3[12];             // Reserved                     020-07F
+        u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths   080-0A7
+        u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens    0A8-0CF
+        u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths   0D0-12F
+        void    *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers  130-1EF
 };
 
-
-struct  ItVpdAreas
-{
-        u32     xSlicDesc;              // Descriptor                           000-003
-        u16     xSlicSize;              // Size of this control block           004-005
-        u16     xPlicAdjustVpdLens:1;   // Flag to indicate new interface       006-007
-        u16     xRsvd1:15;              // Reserved bits                        ...
-        u16     xSlicVpdEntries;        // Number of VPD entries                008-009
-        u16     xSlicDmaEntries;        // Number of DMA entries                00A-00B
-        u16     xSlicMaxLogicalProcs;   // Maximum logical processors           00C-00D
-        u16     xSlicMaxPhysicalProcs;  // Maximum physical processors          00E-00F
-        u16     xSlicDmaToksOffset;     // Offset into this of array            010-011
-        u16     xSlicVpdAdrsOffset;     // Offset into this of array            012-013
-        u16     xSlicDmaLensOffset;     // Offset into this of array            014-015
-        u16     xSlicVpdLensOffset;     // Offset into this of array            016-017
-        u16     xSlicMaxSlotLabels;     // Maximum number of slot labels        018-019
-        u16     xSlicMaxLpQueues;       // Maximum number of LP Queues          01A-01B
-        u8      xRsvd2[4];              // Reserved                             01C-01F
-        u64     xRsvd3[12];             // Reserved                             020-07F
-        u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths           080-0A7
-        u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens            0A8-0CF
-        u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths           0D0-12F
-        void * xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers    130-1EF
-};
+extern struct ItVpdAreas        itVpdAreas;
 
 #endif /* _ITVPDAREAS_H */
diff --git a/include/asm-ppc64/iSeries/LparData.h b/include/asm-ppc64/iSeries/LparData.h
deleted file mode 100644
index e54f3b686e58..000000000000
--- a/include/asm-ppc64/iSeries/LparData.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * LparData.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _LPARDATA_H
-#define _LPARDATA_H
-
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/abs_addr.h>
-
-#include <asm/iSeries/ItLpNaca.h>
-#include <asm/iSeries/ItLpRegSave.h>
-#include <asm/iSeries/HvReleaseData.h>
-#include <asm/iSeries/LparMap.h>
-#include <asm/iSeries/ItVpdAreas.h>
-#include <asm/iSeries/ItIplParmsReal.h>
-#include <asm/iSeries/ItExtVpdPanel.h>
-#include <asm/iSeries/ItLpQueue.h>
-#include <asm/iSeries/IoHriProcessorVpd.h>
-
-extern struct LparMap   xLparMap;
-extern struct HvReleaseData hvReleaseData;
-extern struct ItLpNaca  itLpNaca;
-extern struct ItIplParmsReal xItIplParmsReal;
-extern struct ItExtVpdPanel xItExtVpdPanel;
-extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
-extern struct ItLpQueue xItLpQueue;
-extern struct ItVpdAreas itVpdAreas;
-extern u64    xMsVpd[];
-extern struct msChunks msChunks;
-
-
-#endif /* _LPARDATA_H */
diff --git a/include/asm-ppc64/iSeries/LparMap.h b/include/asm-ppc64/iSeries/LparMap.h
index 075205bb0f4a..a6840b186d03 100644
--- a/include/asm-ppc64/iSeries/LparMap.h
+++ b/include/asm-ppc64/iSeries/LparMap.h
@@ -1,17 +1,17 @@
 /*
  * LparMap.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
@@ -19,15 +19,18 @@
 #ifndef _LPARMAP_H
 #define _LPARMAP_H
 
+#ifndef __ASSEMBLY__
+
 #include <asm/types.h>
 
-/* The iSeries hypervisor will set up mapping for one or more 
+/*
+ * The iSeries hypervisor will set up mapping for one or more
  * ESID/VSID pairs (in SLB/segment registers) and will set up
  * mappings of one or more ranges of pages to VAs.
  * We will have the hypervisor set up the ESID->VSID mapping
  * for the four kernel segments (C-F).  With shared processors,
  * the hypervisor will clear all segment registers and reload
- * these four whenever the processor is switched from one 
+ * these four whenever the processor is switched from one
  * partition to another.
  */
 
@@ -38,30 +41,43 @@
  * need to be located within the load area (if the total partition size
  * is 64 MB), but cannot be mapped.  Typically, this should specify
  * to map half (32 MB) of the load area.
- * 
- * The hypervisor will set up page table entries for the number of 
+ *
+ * The hypervisor will set up page table entries for the number of
  * pages specified.
  *
  * In 32-bit mode, the hypervisor will load all four of the
- * segment registers (identified by the low-order four bits of the 
+ * segment registers (identified by the low-order four bits of the
  * Esid field.  In 64-bit mode, the hypervisor will load one SLB
  * entry to map the Esid to the Vsid.
 */
 
-// Hypervisor initially maps 32MB of the load area 
-#define HvPagesToMap 8192
+#define HvEsidsToMap    2
+#define HvRangesToMap   1
+
+/* Hypervisor initially maps 32MB of the load area */
+#define HvPagesToMap    8192
 
-struct LparMap
-{
-        u64       xNumberEsids;         // Number of ESID/VSID pairs (1)
-        u64       xNumberRanges;        // Number of VA ranges to map (1)
-        u64       xSegmentTableOffs;    // Page number within load area of seg table (0)
-        u64       xRsvd[5];             // Reserved (0)
-        u64       xKernelEsid;          // Esid used to map kernel load (0x0C00000000)  
-        u64       xKernelVsid;          // Vsid used to map kernel load (0x0C00000000)
-        u64       xPages;               // Number of pages to be mapped (8192)
-        u64       xOffset;              // Offset from start of load area (0)
-        u64       xVPN;                 // Virtual Page Number (0x000C000000000000)
+struct LparMap {
+        u64     xNumberEsids;   // Number of ESID/VSID pairs
+        u64     xNumberRanges;  // Number of VA ranges to map
+        u64     xSegmentTableOffs; // Page number within load area of seg table
+        u64     xRsvd[5];
+        struct {
+                u64     xKernelEsid;    // Esid used to map kernel load
+                u64     xKernelVsid;    // Vsid used to map kernel load
+        } xEsids[HvEsidsToMap];
+        struct {
+                u64     xPages;         // Number of pages to be mapped
+                u64     xOffset;        // Offset from start of load area
+                u64     xVPN;           // Virtual Page Number
+        } xRanges[HvRangesToMap];
 };
 
+extern const struct LparMap     xLparMap;
+
+#endif /* __ASSEMBLY__ */
+
+/* the fixed address where the LparMap exists */
+#define LPARMAP_PHYS            0x7000
+
 #endif /* _LPARMAP_H */
diff --git a/include/asm-ppc64/iSeries/XmPciLpEvent.h b/include/asm-ppc64/iSeries/XmPciLpEvent.h
deleted file mode 100644
index a3d27f116e49..000000000000
--- a/include/asm-ppc64/iSeries/XmPciLpEvent.h
+++ /dev/null
@@ -1,18 +0,0 @@
-
-#ifndef __XMPCILPEVENT_H__
-#define __XMPCILPEVENT_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int XmPciLpEvent_init(void);
-void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XMPCILPEVENT_H__ */
diff --git a/include/asm-ppc64/iSeries/iSeries_io.h b/include/asm-ppc64/iSeries/iSeries_io.h
index f52b7599b372..9f79413342b3 100644
--- a/include/asm-ppc64/iSeries/iSeries_io.h
+++ b/include/asm-ppc64/iSeries/iSeries_io.h
@@ -5,32 +5,33 @@
 
 #ifdef CONFIG_PPC_ISERIES
 #include <linux/types.h>
-/************************************************************************/
-/* File iSeries_io.h created by Allan Trautman on Thu Dec 28 2000.      */
-/************************************************************************/
-/* Remaps the io.h for the iSeries Io                                   */
-/* Copyright (C) 20yy  Allan H Trautman, IBM Corporation                */
-/*                                                                      */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation; either version 2 of the License, or    */
-/* (at your option) any later version.                                  */
-/*                                                                      */
-/* This program is distributed in the hope that it will be useful,      */ 
-/* but WITHOUT ANY WARRANTY; without even the implied warranty of       */
-/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the        */
-/* GNU General Public License for more details.                         */
-/*                                                                      */
-/* You should have received a copy of the GNU General Public License    */ 
-/* along with this program; if not, write to the:                       */
-/* Free Software Foundation, Inc.,                                      */ 
-/* 59 Temple Place, Suite 330,                                          */ 
-/* Boston, MA  02111-1307  USA                                          */
-/************************************************************************/
-/* Change Activity:                                                     */
-/*   Created December 28, 2000                                          */
-/* End Change Activity                                                  */
-/************************************************************************/
+/*
+ * File iSeries_io.h created by Allan Trautman on Thu Dec 28 2000.
+ *
+ * Remaps the io.h for the iSeries Io
+ * Copyright (C) 2000  Allan H Trautman, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the:
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330,
+ * Boston, MA  02111-1307  USA
+ *
+ * Change Activity:
+ *   Created December 28, 2000
+ * End Change Activity
+ */
+
 extern u8   iSeries_Read_Byte(const volatile void __iomem * IoAddress);
 extern u16  iSeries_Read_Word(const volatile void __iomem * IoAddress);
 extern u32  iSeries_Read_Long(const volatile void __iomem * IoAddress);
@@ -39,8 +40,10 @@ extern void iSeries_Write_Word(u16 IoData, volatile void __iomem * IoAddress);
 extern void iSeries_Write_Long(u32 IoData, volatile void __iomem * IoAddress);
 
 extern void iSeries_memset_io(volatile void __iomem *dest, char x, size_t n);
-extern void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t n);
-extern void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *source, size_t n);
+extern void iSeries_memcpy_toio(volatile void __iomem *dest, void *source,
+                size_t n);
+extern void iSeries_memcpy_fromio(void *dest,
+                const volatile void __iomem *source, size_t n);
 
 #endif /* CONFIG_PPC_ISERIES */
 #endif /* _ISERIES_IO_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_irq.h b/include/asm-ppc64/iSeries/iSeries_irq.h
index ff8ddede038c..6c9767ac1302 100644
--- a/include/asm-ppc64/iSeries/iSeries_irq.h
+++ b/include/asm-ppc64/iSeries/iSeries_irq.h
@@ -1,19 +1,8 @@
 #ifndef __ISERIES_IRQ_H__
 #define __ISERIES_IRQ_H__
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void iSeries_init_IRQ(void);
-int  iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId);
-int  iSeries_assign_IRQ(int, HvBusNumber, HvSubBusNumber, HvAgentId);
-void iSeries_activate_IRQs(void);
-
-int XmPciLpEvent_init(void);
-
-#ifdef __cplusplus
-}
-#endif
+extern void iSeries_init_IRQ(void);
+extern int  iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId);
+extern void iSeries_activate_IRQs(void);
 
 #endif /* __ISERIES_IRQ_H__ */
diff --git a/include/asm-ppc64/iSeries/iSeries_pci.h b/include/asm-ppc64/iSeries/iSeries_pci.h
index 5769cff4c00c..575f611f8b33 100644
--- a/include/asm-ppc64/iSeries/iSeries_pci.h
+++ b/include/asm-ppc64/iSeries/iSeries_pci.h
@@ -1,112 +1,88 @@
 #ifndef _ISERIES_64_PCI_H
 #define _ISERIES_64_PCI_H
 
-/************************************************************************/
-/* File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001.    */
-/************************************************************************/
-/* Define some useful macros for the iSeries pci routines.              */
-/* Copyright (C) 2001  Allan H Trautman, IBM Corporation                */
-/*                                                                      */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation; either version 2 of the License, or    */
-/* (at your option) any later version.                                  */
-/*                                                                      */
-/* This program is distributed in the hope that it will be useful,      */ 
-/* but WITHOUT ANY WARRANTY; without even the implied warranty of       */
-/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the        */
-/* GNU General Public License for more details.                         */
-/*                                                                      */
-/* You should have received a copy of the GNU General Public License    */ 
-/* along with this program; if not, write to the:                       */
-/* Free Software Foundation, Inc.,                                      */ 
-/* 59 Temple Place, Suite 330,                                          */ 
-/* Boston, MA  02111-1307  USA                                          */
-/************************************************************************/
-/* Change Activity:                                                     */
-/*   Created Feb 20, 2001                                               */
-/*   Added device reset, March 22, 2001                                 */
-/*   Ported to ppc64, May 25, 2001                                      */
-/* End Change Activity                                                  */
-/************************************************************************/
+/*
+ * File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001.
+ *
+ * Define some useful macros for the iSeries pci routines.
+ * Copyright (C) 2001  Allan H Trautman, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the:
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330,
+ * Boston, MA  02111-1307  USA
+ *
+ * Change Activity:
+ *   Created Feb 20, 2001
+ *   Added device reset, March 22, 2001
+ *   Ported to ppc64, May 25, 2001
+ * End Change Activity
+ */
 
 #include <asm/iSeries/HvCallPci.h>
 #include <asm/abs_addr.h>
 
-struct pci_dev;                         /* For Forward Reference        */
+struct pci_dev;                         /* For Forward Reference */
 struct iSeries_Device_Node;
 
-/************************************************************************/
-/* Gets iSeries Bus, SubBus, DevFn using iSeries_Device_Node structure */
-/************************************************************************/
+/*
+ * Gets iSeries Bus, SubBus, DevFn using iSeries_Device_Node structure
+ */
 
 #define ISERIES_BUS(DevPtr)     DevPtr->DsaAddr.Dsa.busNumber
 #define ISERIES_SUBBUS(DevPtr)  DevPtr->DsaAddr.Dsa.subBusNumber
 #define ISERIES_DEVICE(DevPtr)  DevPtr->DsaAddr.Dsa.deviceId
 #define ISERIES_DSA(DevPtr)     DevPtr->DsaAddr.DsaAddr
-#define ISERIES_DEVFUN(DevPtr)  DevPtr->DevFn
-#define ISERIES_DEVNODE(PciDev) ((struct iSeries_Device_Node*)PciDev->sysdata)
+#define ISERIES_DEVNODE(PciDev) ((struct iSeries_Device_Node *)PciDev->sysdata)
 
 #define EADsMaxAgents 7
 
-/************************************************************************/
-/* Decodes Linux DevFn to iSeries DevFn, bridge device, or function.    */
-/* For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h          */
-/************************************************************************/
-
-#define ISERIES_PCI_AGENTID(idsel,func) ((idsel & 0x0F) << 4) | (func  & 0x07)
-#define ISERIES_ENCODE_DEVICE(agentid)  ((0x10) | ((agentid&0x20)>>2) | (agentid&07))
-
-#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus)   ((subbus >> 5) & 0x7)
-#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus) ((subbus >> 2) & 0x7)
-
 /*
- * N.B. the ISERIES_DECODE_* macros are not used anywhere, and I think
- * the 0x71 (at least) must be wrong - 0x78 maybe?  -- paulus.
+ * Decodes Linux DevFn to iSeries DevFn, bridge device, or function.
+ * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h
  */
-#define ISERIES_DECODE_DEVFN(linuxdevfn)  (((linuxdevfn & 0x71) << 1) | (linuxdevfn & 0x07))
-#define ISERIES_DECODE_DEVICE(linuxdevfn) (((linuxdevfn & 0x38) >> 3) |(((linuxdevfn & 0x40) >> 2) + 0x10))
-#define ISERIES_DECODE_FUNCTION(linuxdevfn) (linuxdevfn & 0x07)
 
-/************************************************************************/
-/* Converts Virtual Address to Real Address for Hypervisor calls        */
-/************************************************************************/
+#define ISERIES_PCI_AGENTID(idsel, func)        \
+        (((idsel & 0x0F) << 4) | (func & 0x07))
+#define ISERIES_ENCODE_DEVICE(agentid)          \
+        ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07))
 
-#define ISERIES_HV_ADDR(virtaddr)  (0x8000000000000000 | virt_to_abs(virtaddr))
+#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus)          ((subbus >> 5) & 0x7)
+#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)        ((subbus >> 2) & 0x7)
 
-/************************************************************************/
-/* iSeries Device Information                                           */
-/************************************************************************/
+/*
+ * Converts Virtual Address to Real Address for Hypervisor calls
+ */
+#define ISERIES_HV_ADDR(virtaddr)       \
+        (0x8000000000000000 | virt_to_abs(virtaddr))
 
+/*
+ * iSeries Device Information
+ */
 struct iSeries_Device_Node {
         struct list_head Device_List;
-        struct pci_dev* PciDev;         /* Pointer to pci_dev structure*/
-        union HvDsaMap  DsaAddr;        /* Direct Select Address       */
-                                        /* busNumber,subBusNumber,     */ 
-                                        /* deviceId, barNumber         */
-        HvAgentId       AgentId;        /* Hypervisor DevFn            */
-        int             DevFn;          /* Linux devfn                 */
-        int             BarOffset;
-        int             Irq;            /* Assigned IRQ                */
-        int             ReturnCode;     /* Return Code Holder          */
-        int             IoRetry;        /* Current Retry Count         */
-        int             Flags;          /* Possible flags(disable/bist)*/
-        u16             Vendor;         /* Vendor ID                   */
-        u8              LogicalSlot;    /* Hv Slot Index for Tces      */
-        struct iommu_table* iommu_table;/* Device TCE Table            */ 
-        u8              PhbId;          /* Phb Card is on.             */
-        u16             Board;          /* Board Number                */
-        u8              FrameId;        /* iSeries spcn Frame Id       */
-        char            CardLocation[4];/* Char format of planar vpd   */
-        char            Location[20];   /* Frame  1, Card C10          */
+        struct pci_dev  *PciDev;
+        union HvDsaMap  DsaAddr;        /* Direct Select Address */
+                                        /* busNumber, subBusNumber, */
+                                        /* deviceId, barNumber */
+        int             DevFn;          /* Linux devfn */
+        int             Irq;            /* Assigned IRQ */
+        int             Flags;          /* Possible flags(disable/bist)*/
+        u8              LogicalSlot;    /* Hv Slot Index for Tces */
+        struct iommu_table *iommu_table;/* Device TCE Table */
 };
 
-/************************************************************************/
-/* Functions                                                            */
-/************************************************************************/
-
-extern int           iSeries_Device_Information(struct pci_dev*,char*, int);
-extern void          iSeries_Get_Location_Code(struct iSeries_Device_Node*);
-extern int           iSeries_Device_ToggleReset(struct pci_dev* PciDev, int AssertTime, int DelayTime);
+extern void     iSeries_Device_Information(struct pci_dev*, int);
 
 #endif /* _ISERIES_64_PCI_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_proc.h b/include/asm-ppc64/iSeries/iSeries_proc.h
deleted file mode 100644
index adb6dc14dd4d..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_proc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * iSeries_proc.h
- * Copyright (C) 2001  Kyle A. Lucke IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_PROC_H
-#define _ISERIES_PROC_H
-
-extern void iSeries_proc_early_init(void);
-
-#endif /* _iSeries_PROC_H */
diff --git a/include/asm-ppc64/iSeries/mf.h b/include/asm-ppc64/iSeries/mf.h
index db333e1ee216..7e6a0d936999 100644
--- a/include/asm-ppc64/iSeries/mf.h
+++ b/include/asm-ppc64/iSeries/mf.h
@@ -9,17 +9,16 @@
  * all partitions in the iSeries.  It also provides miscellaneous low-level
  * machine facility type operations.
  *
- * 
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
diff --git a/include/asm-ppc64/iSeries/vio.h b/include/asm-ppc64/iSeries/vio.h
index 3e5766a849d6..6c05e6257f53 100644
--- a/include/asm-ppc64/iSeries/vio.h
+++ b/include/asm-ppc64/iSeries/vio.h
@@ -8,32 +8,32 @@
  *           Colin Devilbiss <devilbis@us.ibm.com>
  *
  * (C) Copyright 2000 IBM Corporation
- * 
+ *
  * This header file is used by the iSeries virtual I/O device
  * drivers.  It defines the interfaces to the common functions
  * (implemented in drivers/char/viopath.h) as well as defining
- * common functions and structures.  Currently (at the time I 
+ * common functions and structures.  Currently (at the time I
  * wrote this comment) the iSeries virtual I/O device drivers
- * that use this are 
- *   drivers/block/viodasd.c 
+ * that use this are
+ *   drivers/block/viodasd.c
  *   drivers/char/viocons.c
  *   drivers/char/viotape.c
  *   drivers/cdrom/viocd.c
  *
  * The iSeries virtual ethernet support (veth.c) uses a whole
  * different set of functions.
- * 
+ *
  * This program is free software;  you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of the
  * License, or (at your option) anyu later version.
  *
  * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.  
+ * General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License 
+ * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
@@ -44,39 +44,41 @@
 #include <asm/iSeries/HvTypes.h>
 #include <asm/iSeries/HvLpEvent.h>
 
-/* iSeries virtual I/O events use the subtype field in
+/*
+ * iSeries virtual I/O events use the subtype field in
  * HvLpEvent to figure out what kind of vio event is coming
  * in.  We use a table to route these, and this defines
  * the maximum number of distinct subtypes
  */
 #define VIO_MAX_SUBTYPES 8
 
-/* Each subtype can register a handler to process their events.
+/*
+ * Each subtype can register a handler to process their events.
  * The handler must have this interface.
  */
 typedef void (vio_event_handler_t) (struct HvLpEvent * event);
 
-int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
-int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
-int vio_setHandler(int subtype, vio_event_handler_t * beh);
-int vio_clearHandler(int subtype);
-int viopath_isactive(HvLpIndex lp);
-HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
-HvLpInstanceId viopath_targetinst(HvLpIndex lp);
-void vio_set_hostlp(void);
-void *vio_get_event_buffer(int subtype);
-void vio_free_event_buffer(int subtype, void *buffer);
+extern int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
+extern int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
+extern int vio_setHandler(int subtype, vio_event_handler_t * beh);
+extern int vio_clearHandler(int subtype);
+extern int viopath_isactive(HvLpIndex lp);
+extern HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
+extern HvLpInstanceId viopath_targetinst(HvLpIndex lp);
+extern void vio_set_hostlp(void);
+extern void *vio_get_event_buffer(int subtype);
+extern void vio_free_event_buffer(int subtype, void *buffer);
 
 extern HvLpIndex viopath_hostLp;
 extern HvLpIndex viopath_ourLp;
 
-#define VIOCHAR_MAX_DATA 200
+#define VIOCHAR_MAX_DATA        200
 
-#define VIOMAJOR_SUBTYPE_MASK 0xff00
-#define VIOMINOR_SUBTYPE_MASK 0x00ff
-#define VIOMAJOR_SUBTYPE_SHIFT 8
+#define VIOMAJOR_SUBTYPE_MASK   0xff00
+#define VIOMINOR_SUBTYPE_MASK   0x00ff
+#define VIOMAJOR_SUBTYPE_SHIFT  8
 
-#define VIOVERSION            0x0101
+#define VIOVERSION              0x0101
 
 /*
  * This is the general structure for VIO errors; each module should have
@@ -89,8 +91,8 @@ struct vio_error_entry {
         int errno;
         const char *msg;
 };
-const struct vio_error_entry *vio_lookup_rc(const struct vio_error_entry
-                                            *local_table, u16 rc);
+extern const struct vio_error_entry *vio_lookup_rc(
+                const struct vio_error_entry *local_table, u16 rc);
 
 enum viosubtypes {
         viomajorsubtype_monitor = 0x0100,
@@ -102,7 +104,6 @@ enum viosubtypes {
         viomajorsubtype_scsi = 0x0700
 };
 
-
 enum vioconfigsubtype {
         vioconfigget = 0x0001,
 };
diff --git a/include/asm-ppc64/imalloc.h b/include/asm-ppc64/imalloc.h
index 3a45e918bf16..42adf7033a81 100644
--- a/include/asm-ppc64/imalloc.h
+++ b/include/asm-ppc64/imalloc.h
@@ -4,9 +4,9 @@
 /*
  * Define the address range of the imalloc VM area.
  */
-#define PHBS_IO_BASE      IOREGIONBASE
-#define IMALLOC_BASE      (IOREGIONBASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
-#define IMALLOC_END       (IOREGIONBASE + EADDR_MASK)
+#define PHBS_IO_BASE      VMALLOC_END
+#define IMALLOC_BASE      (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
+#define IMALLOC_END       (VMALLOC_START + PGTABLE_RANGE)
 
 
 /* imalloc region types */
@@ -18,7 +18,9 @@
 
 extern struct vm_struct * im_get_free_area(unsigned long size);
 extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size,
-                        int region_type);
-unsigned long im_free(void *addr);
+                                      int region_type);
+extern void im_free(void *addr);
+
+extern unsigned long ioremap_bot;
 
 #endif /* _PPC64_IMALLOC_H */
diff --git a/include/asm-ppc64/ioctl.h b/include/asm-ppc64/ioctl.h
deleted file mode 100644
index 42b8c5da7fbc..000000000000
--- a/include/asm-ppc64/ioctl.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _PPC64_IOCTL_H
-#define _PPC64_IOCTL_H
-
-
-/*
- * This was copied from the alpha as it's a bit cleaner there.
- *                         -- Cort
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
-#define _IOC_SIZEBITS   13
-#define _IOC_DIRBITS    3
-
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-
-/*
- * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
- * And this turns out useful to catch old ioctl numbers in header
- * files for us.
- */
-#define _IOC_NONE       1U
-#define _IOC_READ       2U
-#define _IOC_WRITE      4U
-
-#define _IOC(dir,type,nr,size) \
-        (((dir)  << _IOC_DIRSHIFT) | \
-         ((type) << _IOC_TYPESHIFT) | \
-         ((nr)   << _IOC_NRSHIFT) | \
-         ((size) << _IOC_SIZESHIFT))
-
-/* provoke compile error for invalid uses of size argument */
-extern unsigned int __invalid_size_argument_for_IOC;
-#define _IOC_TYPECHECK(t) \
-       ((sizeof(t) == sizeof(t[1]) && \
-         sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
-         sizeof(t) : __invalid_size_argument_for_IOC)
-
-/* used to create numbers */
-#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
-#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
-#define _IOR_BAD(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
-#define _IOW_BAD(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
-#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
-
-/* used to decode them.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-
-/* various drivers, such as the pcmcia stuff, need these... */
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
-
-#endif /* _PPC64_IOCTL_H */
diff --git a/include/asm-ppc64/ioctls.h b/include/asm-ppc64/ioctls.h
deleted file mode 100644
index 48796bf3e4fc..000000000000
--- a/include/asm-ppc64/ioctls.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef _ASM_PPC64_IOCTLS_H
-#define _ASM_PPC64_IOCTLS_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/ioctl.h>
-
-#define FIOCLEX         _IO('f', 1)
-#define FIONCLEX        _IO('f', 2)
-#define FIOASYNC        _IOW('f', 125, int)
-#define FIONBIO         _IOW('f', 126, int)
-#define FIONREAD        _IOR('f', 127, int)
-#define TIOCINQ         FIONREAD
-#define FIOQSIZE        _IOR('f', 128, loff_t)
-
-#define TIOCGETP        _IOR('t', 8, struct sgttyb)
-#define TIOCSETP        _IOW('t', 9, struct sgttyb)
-#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
-
-#define TIOCSETC        _IOW('t', 17, struct tchars)
-#define TIOCGETC        _IOR('t', 18, struct tchars)
-#define TCGETS          _IOR('t', 19, struct termios)
-#define TCSETS          _IOW('t', 20, struct termios)
-#define TCSETSW         _IOW('t', 21, struct termios)
-#define TCSETSF         _IOW('t', 22, struct termios)
-
-#define TCGETA          _IOR('t', 23, struct termio)
-#define TCSETA          _IOW('t', 24, struct termio)
-#define TCSETAW         _IOW('t', 25, struct termio)
-#define TCSETAF         _IOW('t', 28, struct termio)
-
-#define TCSBRK          _IO('t', 29)
-#define TCXONC          _IO('t', 30)
-#define TCFLSH          _IO('t', 31)
-
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
-#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
-#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-
-#define TIOCGLTC        _IOR('t', 116, struct ltchars)
-#define TIOCSLTC        _IOW('t', 117, struct ltchars)
-#define TIOCSPGRP       _IOW('t', 118, int)
-#define TIOCGPGRP       _IOR('t', 119, int)
-
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-
-#define TIOCSTI         0x5412
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-# define TIOCM_LE       0x001
-# define TIOCM_DTR      0x002
-# define TIOCM_RTS      0x004
-# define TIOCM_ST       0x008
-# define TIOCM_SR       0x010
-# define TIOCM_CTS      0x020
-# define TIOCM_CAR      0x040
-# define TIOCM_RNG      0x080
-# define TIOCM_DSR      0x100
-# define TIOCM_CD       TIOCM_CAR
-# define TIOCM_RI       TIOCM_RNG
-
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-# define TIOCPKT_DATA            0
-# define TIOCPKT_FLUSHREAD       1
-# define TIOCPKT_FLUSHWRITE      2
-# define TIOCPKT_STOP            4
-# define TIOCPKT_START           8
-# define TIOCPKT_NOSTOP         16
-# define TIOCPKT_DOSTOP         32
-
-
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-
-#endif /* _ASM_PPC64_IOCTLS_H */
diff --git a/include/asm-ppc64/iommu.h b/include/asm-ppc64/iommu.h
index bd53ca4dcfa2..72dcf8116b04 100644
--- a/include/asm-ppc64/iommu.h
+++ b/include/asm-ppc64/iommu.h
@@ -82,24 +82,6 @@ struct iommu_table {
         unsigned long *it_map;       /* A simple allocation bitmap for now */
 };
 
-#ifdef CONFIG_PPC_ISERIES
-struct iommu_table_cb {
-        unsigned long   itc_busno;      /* Bus number for this tce table */
-        unsigned long   itc_start;      /* Will be NULL for secondary */
-        unsigned long   itc_totalsize;  /* Size (in pages) of whole table */
-        unsigned long   itc_offset;     /* Index into real tce table of the
-                                           start of our section */
-        unsigned long   itc_size;       /* Size (in pages) of our section */
-        unsigned long   itc_index;      /* Index of this tce table */
-        unsigned short  itc_maxtables;  /* Max num of tables for partition */
-        unsigned char   itc_virtbus;    /* Flag to indicate virtual bus */
-        unsigned char   itc_slotno;     /* IOA Tce Slot Index */
-        unsigned char   itc_rsvd[4];
-};
-
-extern struct iommu_table vio_tce_table;      /* Tce table for virtual bus */
-#endif /* CONFIG_PPC_ISERIES */
-
 struct scatterlist;
 
 #ifdef CONFIG_PPC_MULTIPLATFORM
@@ -122,12 +104,6 @@ extern void iommu_devnode_init_pSeries(struct device_node *dn);
 
 #ifdef CONFIG_PPC_ISERIES
 
-/* Walks all buses and creates iommu tables */
-extern void iommu_setup_iSeries(void);
-
-/* Initializes tables for bio buses */
-extern void __init iommu_vio_init(void);
-
 struct iSeries_Device_Node;
 /* Creates table for an individual device node */
 extern void iommu_devnode_init_iSeries(struct iSeries_Device_Node *dn);
@@ -158,8 +134,12 @@ extern void iommu_init_early_pSeries(void);
 extern void iommu_init_early_iSeries(void);
 extern void iommu_init_early_u3(void);
 
+#ifdef CONFIG_PCI
 extern void pci_iommu_init(void);
 extern void pci_direct_iommu_init(void);
+#else
+static inline void pci_iommu_init(void) { }
+#endif
 
 extern void alloc_u3_dart_table(void);
 
diff --git a/include/asm-ppc64/ipc.h b/include/asm-ppc64/ipc.h
deleted file mode 100644
index a46e3d9c2a3f..000000000000
--- a/include/asm-ppc64/ipc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipc.h>
diff --git a/include/asm-ppc64/irq.h b/include/asm-ppc64/irq.h
index 570678b1da95..99782afb4cde 100644
--- a/include/asm-ppc64/irq.h
+++ b/include/asm-ppc64/irq.h
@@ -33,6 +33,11 @@
 #define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
 #define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
 
+/*
+ * IRQ line status macro IRQ_PER_CPU is used
+ */
+#define ARCH_HAS_IRQ_PER_CPU
+
 #define get_irq_desc(irq) (&irq_desc[(irq)])
 
 /* Define a way to iterate across irqs. */
diff --git a/include/asm-ppc64/kdebug.h b/include/asm-ppc64/kdebug.h
index 488634258a72..d383d161cf8d 100644
--- a/include/asm-ppc64/kdebug.h
+++ b/include/asm-ppc64/kdebug.h
@@ -17,7 +17,7 @@ struct die_args {
 
 /*
    Note - you should never unregister because that can race with NMIs.
-   If you really want to do it first unregister - then synchronize_kernel -
+   If you really want to do it first unregister - then synchronize_sched -
    then free.
  */
 int register_die_notifier(struct notifier_block *nb);
diff --git a/include/asm-ppc64/kexec.h b/include/asm-ppc64/kexec.h
new file mode 100644
index 000000000000..511908afaeeb
--- /dev/null
+++ b/include/asm-ppc64/kexec.h
@@ -0,0 +1,41 @@
+#ifndef _PPC64_KEXEC_H
+#define _PPC64_KEXEC_H
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ */
+
+/* Maximum physical address we can use pages from */
+/* XXX: since we copy virt we can use any page we allocate */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can reach in physical address mode */
+/* XXX: I want to allow initrd in highmem.  otherwise set to rmo on lpar */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can use for the control code buffer */
+/* XXX: unused today, ppc32 uses TASK_SIZE, probably left over from use_mm  */
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
+
+/* XXX: today we don't use this at all, althogh we have a static stack */
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_PPC64
+
+#define MAX_NOTE_BYTES 1024
+
+#ifndef __ASSEMBLY__
+
+typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
+
+extern note_buf_t crash_notes[];
+
+extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
+                                          master to copy new code to 0 */
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PPC_KEXEC_H */
+
diff --git a/include/asm-ppc64/kprobes.h b/include/asm-ppc64/kprobes.h
index 19b468bed059..d9129d2b038e 100644
--- a/include/asm-ppc64/kprobes.h
+++ b/include/asm-ppc64/kprobes.h
@@ -42,10 +42,16 @@ typedef unsigned int kprobe_opcode_t;
 
 #define JPROBE_ENTRY(pentry)    (kprobe_opcode_t *)((func_descr_t *)pentry)
 
+#define is_trap(instr)  (IS_TW(instr) || IS_TD(instr) || \
+                        IS_TWI(instr) || IS_TDI(instr))
+
+#define ARCH_SUPPORTS_KRETPROBES
+void kretprobe_trampoline(void);
+
 /* Architecture specific copy of original instruction */
 struct arch_specific_insn {
         /* copy of original instruction */
-        kprobe_opcode_t insn[MAX_INSN_SIZE];
+        kprobe_opcode_t *insn;
 };
 
 #ifdef CONFIG_KPROBES
diff --git a/include/asm-ppc64/linkage.h b/include/asm-ppc64/linkage.h
deleted file mode 100644
index 291c2d01c44f..000000000000
--- a/include/asm-ppc64/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
diff --git a/include/asm-ppc64/lmb.h b/include/asm-ppc64/lmb.h
index a6cbca21ac1d..de91e034bd98 100644
--- a/include/asm-ppc64/lmb.h
+++ b/include/asm-ppc64/lmb.h
@@ -22,7 +22,6 @@
 
 struct lmb_property {
         unsigned long base;
-        unsigned long physbase;
         unsigned long size;
 };
 
@@ -57,4 +56,26 @@ extern void lmb_dump_all(void);
 
 extern unsigned long io_hole_start;
 
+static inline unsigned long
+lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
+{
+        return type->region[region_nr].size;
+}
+static inline unsigned long
+lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
+{
+        return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
+}
+static inline unsigned long
+lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
+{
+        return type->region[region_nr].base >> PAGE_SHIFT;
+}
+static inline unsigned long
+lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
+{
+        return lmb_start_pfn(type, region_nr) +
+               lmb_size_pages(type, region_nr);
+}
+
 #endif /* _PPC64_LMB_H */
diff --git a/include/asm-ppc64/lppaca.h b/include/asm-ppc64/lppaca.h
index 70766b5f26c1..9e2a6c0649a0 100644
--- a/include/asm-ppc64/lppaca.h
+++ b/include/asm-ppc64/lppaca.h
@@ -108,7 +108,7 @@ struct lppaca
         volatile u32 virtual_decr;      // Virtual DECR for shared procsx78-x7B
         u16     slb_count;              // # of SLBs to maintain        x7C-x7D
         u8      idle;                   // Indicate OS is idle          x7E
-        u8      reserved5;              // Reserved                     x7F
+        u8      vmxregs_in_use;         // VMX registers in use         x7F
 
 
 //=============================================================================
diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h
index 5d3cd9d042e2..9a1ef4427ed2 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-ppc64/machdep.h
@@ -53,10 +53,8 @@ struct machdep_calls {
         long            (*hpte_insert)(unsigned long hpte_group,
                                        unsigned long va,
                                        unsigned long prpn,
-                                       int secondary, 
-                                       unsigned long hpteflags, 
-                                       int bolted,
-                                       int large);
+                                       unsigned long vflags,
+                                       unsigned long rflags);
         long            (*hpte_remove)(unsigned long hpte_group);
         void            (*flush_hash_range)(unsigned long context,
                                             unsigned long number,
@@ -76,6 +74,7 @@ struct machdep_calls {
         void            (*tce_flush)(struct iommu_table *tbl);
         void            (*iommu_dev_setup)(struct pci_dev *dev);
         void            (*iommu_bus_setup)(struct pci_bus *bus);
+        void            (*irq_bus_setup)(struct pci_bus *bus);
 
         int             (*probe)(int platform);
         void            (*setup_arch)(void);
@@ -85,6 +84,7 @@ struct machdep_calls {
 
         void            (*init_IRQ)(void);
         int             (*get_irq)(struct pt_regs *);
+        void            (*cpu_irq_down)(int secondary);
 
         /* PCI stuff */
         void            (*pcibios_fixup)(void);
@@ -103,11 +103,6 @@ struct machdep_calls {
 
         void            (*progress)(char *, unsigned short);
 
-        /* Debug interface.  Low level I/O to some terminal device */
-        void            (*udbg_putc)(unsigned char c);
-        unsigned char   (*udbg_getc)(void);
-        int             (*udbg_getc_poll)(void);
-
         /* Interface for platform error logging */
         void            (*log_error)(char *buf, unsigned int err_type, int fatal);
 
@@ -138,8 +133,16 @@ struct machdep_calls {
                                                 unsigned long size,
                                                 pgprot_t vma_prot);
 
+        /* Idle loop for this platform, leave empty for default idle loop */
+        int             (*idle_loop)(void);
+
+        /* Function to enable pmcs for this platform, called once per cpu. */
+        void            (*enable_pmcs)(void);
 };
 
+extern int default_idle(void);
+extern int native_idle(void);
+
 extern struct machdep_calls ppc_md;
 extern char cmd_line[COMMAND_LINE_SIZE];
 
diff --git a/include/asm-ppc64/memory.h b/include/asm-ppc64/memory.h
index 56e09face9a8..af53ffb55726 100644
--- a/include/asm-ppc64/memory.h
+++ b/include/asm-ppc64/memory.h
@@ -18,9 +18,11 @@
 #ifdef CONFIG_SMP
 #define EIEIO_ON_SMP    "eieio\n"
 #define ISYNC_ON_SMP    "\n\tisync"
+#define SYNC_ON_SMP     "lwsync\n\t"
 #else
 #define EIEIO_ON_SMP
 #define ISYNC_ON_SMP
+#define SYNC_ON_SMP
 #endif
 
 static inline void eieio(void)
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index c78282a67d8e..7bc42eb087ad 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -28,9 +28,12 @@
 #define STE_VSID_SHIFT  12
 
 /* Location of cpu0's segment table */
-#define STAB0_PAGE      0x9
+#define STAB0_PAGE      0x6
 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
-#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR)
+
+#ifndef __ASSEMBLY__
+extern char initial_stab[];
+#endif /* ! __ASSEMBLY */
 
 /*
  * SLB
@@ -47,11 +50,14 @@
 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
-#define SLB_VSID_L              ASM_CONST(0x0000000000000100) /* largepage 16M */
+#define SLB_VSID_L              ASM_CONST(0x0000000000000100) /* largepage */
 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
+#define SLB_VSID_LS             ASM_CONST(0x0000000000000070) /* size of largepage */
+ 
+#define SLB_VSID_KERNEL         (SLB_VSID_KP)
+#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
 
-#define SLB_VSID_KERNEL         (SLB_VSID_KP|SLB_VSID_C)
-#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS)
+#define SLBIE_C                 (0x08000000)
 
 /*
  * Hash table
@@ -59,6 +65,22 @@
 
 #define HPTES_PER_GROUP 8
 
+#define HPTE_V_AVPN_SHIFT       7
+#define HPTE_V_AVPN             ASM_CONST(0xffffffffffffff80)
+#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
+#define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
+#define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
+#define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
+#define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
+#define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
+
+#define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
+#define HPTE_R_TS               ASM_CONST(0x4000000000000000)
+#define HPTE_R_RPN_SHIFT        12
+#define HPTE_R_RPN              ASM_CONST(0x3ffffffffffff000)
+#define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
+#define HPTE_R_PP               ASM_CONST(0x0000000000000003)
+
 /* Values for PP (assumes Ks=0, Kp=1) */
 /* pp0 will always be 0 for linux     */
 #define PP_RWXX 0       /* Supervisor read/write, User none */
@@ -68,54 +90,13 @@
 
 #ifndef __ASSEMBLY__
 
-/* Hardware Page Table Entry */
-typedef struct {
-        unsigned long avpn:57; /* vsid | api == avpn  */
-        unsigned long :     2; /* Software use */
-        unsigned long bolted: 1; /* HPTE is "bolted" */
-        unsigned long lock: 1; /* lock on pSeries SMP */
-        unsigned long l:    1; /* Virtual page is large (L=1) or 4 KB (L=0) */
-        unsigned long h:    1; /* Hash function identifier */
-        unsigned long v:    1; /* Valid (v=1) or invalid (v=0) */
-} Hpte_dword0;
-
-typedef struct {
-        unsigned long pp0:  1; /* Page protection bit 0 */
-        unsigned long ts:   1; /* Tag set bit */
-        unsigned long rpn: 50; /* Real page number */
-        unsigned long :     2; /* Reserved */
-        unsigned long ac:   1; /* Address compare */ 
-        unsigned long r:    1; /* Referenced */
-        unsigned long c:    1; /* Changed */
-        unsigned long w:    1; /* Write-thru cache mode */
-        unsigned long i:    1; /* Cache inhibited */
-        unsigned long m:    1; /* Memory coherence required */
-        unsigned long g:    1; /* Guarded */
-        unsigned long n:    1; /* No-execute */
-        unsigned long pp:   2; /* Page protection bits 1:2 */
-} Hpte_dword1;
-
-typedef struct {
-        char padding[6];                /* padding */
-        unsigned long :       6;        /* padding */ 
-        unsigned long flags: 10;        /* HPTE flags */
-} Hpte_dword1_flags;
-
 typedef struct {
-        union {
-                unsigned long dword0;
-                Hpte_dword0   dw0;
-        } dw0;
+        unsigned long v;
+        unsigned long r;
+} hpte_t;
 
-        union {
-                unsigned long dword1;
-                Hpte_dword1 dw1;
-                Hpte_dword1_flags flags;
-        } dw1;
-} HPTE; 
-
-extern HPTE *           htab_address;
-extern unsigned long    htab_hash_mask;
+extern hpte_t *htab_address;
+extern unsigned long htab_hash_mask;
 
 static inline unsigned long hpt_hash(unsigned long vpn, int large)
 {
@@ -180,6 +161,28 @@ static inline void tlbiel(unsigned long va)
         asm volatile("ptesync": : :"memory");
 }
 
+static inline unsigned long slot2va(unsigned long hpte_v, unsigned long slot)
+{
+        unsigned long avpn = HPTE_V_AVPN_VAL(hpte_v);
+        unsigned long va;
+
+        va = avpn << 23;
+
+        if (! (hpte_v & HPTE_V_LARGE)) {
+                unsigned long vpi, pteg;
+
+                pteg = slot / HPTES_PER_GROUP;
+                if (hpte_v & HPTE_V_SECONDARY)
+                        pteg = ~pteg;
+
+                vpi = ((va >> 28) ^ pteg) & htab_hash_mask;
+
+                va |= vpi << PAGE_SHIFT;
+        }
+
+        return va;
+}
+
 /*
  * Handle a fault by adding an HPTE. If the address can't be determined
  * to be valid via Linux page tables, return 1. If handled return 0
@@ -196,11 +199,13 @@ extern void hpte_init_iSeries(void);
 
 extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
                                      unsigned long va, unsigned long prpn,
-                                     int secondary, unsigned long hpteflags,
-                                     int bolted, int large);
+                                     unsigned long vflags,
+                                     unsigned long rflags);
 extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
-                               unsigned long prpn, int secondary,
-                               unsigned long hpteflags, int bolted, int large);
+                               unsigned long prpn,
+                               unsigned long vflags, unsigned long rflags);
+
+extern void stabs_alloc(void);
 
 #endif /* __ASSEMBLY__ */
 
@@ -259,8 +264,10 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
 #define VSID_BITS       36
 #define VSID_MODULUS    ((1UL<<VSID_BITS)-1)
 
-#define CONTEXT_BITS    20
-#define USER_ESID_BITS  15
+#define CONTEXT_BITS    19
+#define USER_ESID_BITS  16
+
+#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
 
 /*
  * This macro generates asm code to compute the VSID scramble
@@ -302,8 +309,7 @@ typedef unsigned long mm_context_id_t;
 typedef struct {
         mm_context_id_t id;
 #ifdef CONFIG_HUGETLB_PAGE
-        pgd_t *huge_pgdir;
-        u16 htlb_segs; /* bitmask */
+        u16 low_htlb_areas, high_htlb_areas;
 #endif
 } mm_context_t;
 
@@ -338,6 +344,9 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
                              | (ea >> SID_SHIFT));
 }
 
+#define VSID_SCRAMBLE(pvsid)    (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
+#define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
+
 #endif /* __ASSEMBLY */
 
 #endif /* _PPC64_MMU_H_ */
diff --git a/include/asm-ppc64/mmzone.h b/include/asm-ppc64/mmzone.h
index 0619a41a3c9d..ed473f4b0152 100644
--- a/include/asm-ppc64/mmzone.h
+++ b/include/asm-ppc64/mmzone.h
@@ -10,9 +10,20 @@
 #include <linux/config.h>
 #include <asm/smp.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+/* generic non-linear memory support:
+ *
+ * 1) we will not split memory into more chunks than will fit into the
+ *    flags field of the struct page
+ */
+
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
 
 extern struct pglist_data *node_data[];
+/*
+ * Return a pointer to the node data for node n.
+ */
+#define NODE_DATA(nid)          (node_data[nid])
 
 /*
  * Following are specific to this numa platform.
@@ -47,36 +58,32 @@ static inline int pa_to_nid(unsigned long pa)
         return nid;
 }
 
-#define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
-
-/*
- * Return a pointer to the node data for node n.
- */
-#define NODE_DATA(nid)          (node_data[nid])
-
 #define node_localnr(pfn, nid)  ((pfn) - NODE_DATA(nid)->node_start_pfn)
 
 /*
  * Following are macros that each numa implmentation must define.
  */
 
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define kvaddr_to_nid(kaddr)    pa_to_nid(__pa(kaddr))
-
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
 
 #define local_mapnr(kvaddr) \
         ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) 
 
+#ifdef CONFIG_DISCONTIGMEM
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define kvaddr_to_nid(kaddr)    pa_to_nid(__pa(kaddr))
+
+#define pfn_to_nid(pfn)         pa_to_nid((unsigned long)(pfn) << PAGE_SHIFT)
+
 /* Written this way to avoid evaluating arguments twice */
 #define discontigmem_pfn_to_page(pfn) \
 ({ \
         unsigned long __tmp = pfn; \
-        (node_mem_map(pfn_to_nid(__tmp)) + \
+        (NODE_DATA(pfn_to_nid(__tmp))->node_mem_map + \
          node_localnr(__tmp, pfn_to_nid(__tmp))); \
 })
 
@@ -91,4 +98,11 @@ static inline int pa_to_nid(unsigned long pa)
 #define discontigmem_pfn_valid(pfn)             ((pfn) < num_physpages)
 
 #endif /* CONFIG_DISCONTIGMEM */
+
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
+#define early_pfn_to_nid(pfn)  pa_to_nid(((unsigned long)pfn) << PAGE_SHIFT)
+#endif
+
 #endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-ppc64/module.h b/include/asm-ppc64/module.h
deleted file mode 100644
index 0581607826e8..000000000000
--- a/include/asm-ppc64/module.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _ASM_PPC64_MODULE_H
-#define _ASM_PPC64_MODULE_H
-
-#include <linux/list.h>
-#include <asm/bug.h>
-
-struct mod_arch_specific
-{
-        /* Index of stubs section within module. */
-        unsigned int stubs_section;
-
-        /* What section is the TOC? */
-        unsigned int toc_section;
-
-        /* List of BUG addresses, source line numbers and filenames */
-        struct list_head bug_list;
-        struct bug_entry *bug_table;
-        unsigned int num_bugs;
-};
-
-extern struct bug_entry *module_find_bug(unsigned long bugaddr);
-
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Sym Elf64_Sym
-#define Elf_Ehdr Elf64_Ehdr
-
-/* Make empty section for module_frob_arch_sections to expand. */
-#ifdef MODULE
-asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
-#endif
-
-struct exception_table_entry;
-void sort_ex_table(struct exception_table_entry *start,
-                        struct exception_table_entry *finish);
-
-#endif /* _ASM_PPC64_MODULE_H */
diff --git a/include/asm-ppc64/naca.h b/include/asm-ppc64/naca.h
index bfb7caa32eaf..d2afe6447597 100644
--- a/include/asm-ppc64/naca.h
+++ b/include/asm-ppc64/naca.h
@@ -12,8 +12,6 @@
 
 #include <asm/types.h>
 
-#ifndef __ASSEMBLY__
-
 struct naca_struct {
         /* Kernel only data - undefined for user space */
         void *xItVpdAreas;              /* VPD Data                  0x00 */
@@ -23,9 +21,4 @@ struct naca_struct {
 
 extern struct naca_struct naca;
 
-#endif /* __ASSEMBLY__ */
-
-#define NACA_PAGE      0x4
-#define NACA_PHYS_ADDR (NACA_PAGE<<PAGE_SHIFT)
-
 #endif /* _NACA_H */
diff --git a/include/asm-ppc64/namei.h b/include/asm-ppc64/namei.h
deleted file mode 100644
index a1412a2d102a..000000000000
--- a/include/asm-ppc64/namei.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* 
- * linux/include/asm-ppc/namei.h
- * Adapted from linux/include/asm-alpha/namei.h
- *
- * Included from linux/fs/namei.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __PPC64_NAMEI_H
-#define __PPC64_NAMEI_H
-
-/* This dummy routine maybe changed to something useful
- * for /usr/gnemul/ emulation stuff.
- * Look at asm-sparc/namei.h for details.
- */
-
-#define __emul_prefix() NULL
-
-#endif /* __PPC64_NAMEI_H */
diff --git a/include/asm-ppc64/nvram.h b/include/asm-ppc64/nvram.h
index 4e6dd370d936..dfaa21566c9a 100644
--- a/include/asm-ppc64/nvram.h
+++ b/include/asm-ppc64/nvram.h
@@ -70,6 +70,7 @@ extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
 
 extern int pSeries_nvram_init(void);
 extern int pmac_nvram_init(void);
+extern int bpa_nvram_init(void);
 
 /* PowerMac specific nvram stuffs */
 
diff --git a/include/asm-ppc64/oprofile_impl.h b/include/asm-ppc64/oprofile_impl.h
new file mode 100644
index 000000000000..b04f1dfb1421
--- /dev/null
+++ b/include/asm-ppc64/oprofile_impl.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
+ *
+ * Based on alpha version.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef OP_IMPL_H
+#define OP_IMPL_H 1
+
+#define OP_MAX_COUNTER 8
+
+/* Per-counter configuration as set via oprofilefs.  */
+struct op_counter_config {
+        unsigned long valid;
+        unsigned long enabled;
+        unsigned long event;
+        unsigned long count;
+        unsigned long kernel;
+        /* We dont support per counter user/kernel selection */
+        unsigned long user;
+        unsigned long unit_mask;
+};
+
+/* System-wide configuration as set via oprofilefs.  */
+struct op_system_config {
+        unsigned long mmcr0;
+        unsigned long mmcr1;
+        unsigned long mmcra;
+        unsigned long enable_kernel;
+        unsigned long enable_user;
+        unsigned long backtrace_spinlocks;
+};
+
+/* Per-arch configuration */
+struct op_ppc64_model {
+        void (*reg_setup) (struct op_counter_config *,
+                           struct op_system_config *,
+                           int num_counters);
+        void (*cpu_setup) (void *);
+        void (*start) (struct op_counter_config *);
+        void (*stop) (void);
+        void (*handle_interrupt) (struct pt_regs *,
+                                  struct op_counter_config *);
+        int num_counters;
+};
+
+extern struct op_ppc64_model op_model_rs64;
+extern struct op_ppc64_model op_model_power4;
+
+static inline unsigned int ctr_read(unsigned int i)
+{
+        switch(i) {
+        case 0:
+                return mfspr(SPRN_PMC1);
+        case 1:
+                return mfspr(SPRN_PMC2);
+        case 2:
+                return mfspr(SPRN_PMC3);
+        case 3:
+                return mfspr(SPRN_PMC4);
+        case 4:
+                return mfspr(SPRN_PMC5);
+        case 5:
+                return mfspr(SPRN_PMC6);
+        case 6:
+                return mfspr(SPRN_PMC7);
+        case 7:
+                return mfspr(SPRN_PMC8);
+        default:
+                return 0;
+        }
+}
+
+static inline void ctr_write(unsigned int i, unsigned int val)
+{
+        switch(i) {
+        case 0:
+                mtspr(SPRN_PMC1, val);
+                break;
+        case 1:
+                mtspr(SPRN_PMC2, val);
+                break;
+        case 2:
+                mtspr(SPRN_PMC3, val);
+                break;
+        case 3:
+                mtspr(SPRN_PMC4, val);
+                break;
+        case 4:
+                mtspr(SPRN_PMC5, val);
+                break;
+        case 5:
+                mtspr(SPRN_PMC6, val);
+                break;
+        case 6:
+                mtspr(SPRN_PMC7, val);
+                break;
+        case 7:
+                mtspr(SPRN_PMC8, val);
+                break;
+        default:
+                break;
+        }
+}
+
+#endif
diff --git a/include/asm-ppc64/paca.h b/include/asm-ppc64/paca.h
index 1a0223b5f3b8..2f0f36f73d38 100644
--- a/include/asm-ppc64/paca.h
+++ b/include/asm-ppc64/paca.h
@@ -26,7 +26,6 @@ register struct paca_struct *local_paca asm("r13");
 #define get_paca()      local_paca
 
 struct task_struct;
-struct ItLpQueue;
 
 /*
  * Defines the layout of the paca.
@@ -62,7 +61,6 @@ struct paca_struct {
         u16 paca_index;                 /* Logical processor number */
 
         u32 default_decr;               /* Default decrementer value */
-        struct ItLpQueue *lpqueue_ptr;  /* LpQueue handled by this CPU */
         u64 kernel_toc;                 /* Kernel TOC address */
         u64 stab_real;                  /* Absolute address of segment table */
         u64 stab_addr;                  /* Virtual address of segment table */
@@ -91,7 +89,6 @@ struct paca_struct {
         u64 next_jiffy_update_tb;       /* TB value for next jiffy update */
         u64 saved_r1;                   /* r1 save for RTAS calls */
         u64 saved_msr;                  /* MSR saved here by enter_rtas */
-        u32 lpevent_count;              /* lpevents processed  */
         u8 proc_enabled;                /* irq soft-enable flag */
 
         /* not yet used */
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index bcd21789d3b7..a15422bcf30d 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -37,39 +37,45 @@
 
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 
-/* For 64-bit processes the hugepage range is 1T-1.5T */
-#define TASK_HPAGE_BASE ASM_CONST(0x0000010000000000)
-#define TASK_HPAGE_END  ASM_CONST(0x0000018000000000)
+#define HTLB_AREA_SHIFT         40
+#define HTLB_AREA_SIZE          (1UL << HTLB_AREA_SHIFT)
+#define GET_HTLB_AREA(x)        ((x) >> HTLB_AREA_SHIFT)
 
 #define LOW_ESID_MASK(addr, len)        (((1U << (GET_ESID(addr+len-1)+1)) \
                                         - (1U << GET_ESID(addr))) & 0xffff)
+#define HTLB_AREA_MASK(addr, len)       (((1U << (GET_HTLB_AREA(addr+len-1)+1)) \
+                                        - (1U << GET_HTLB_AREA(addr))) & 0xffff)
 
 #define ARCH_HAS_HUGEPAGE_ONLY_RANGE
 #define ARCH_HAS_PREPARE_HUGEPAGE_RANGE
+#define ARCH_HAS_SETCLEAR_HUGE_PTE
 
 #define touches_hugepage_low_range(mm, addr, len) \
-        (LOW_ESID_MASK((addr), (len)) & mm->context.htlb_segs)
-#define touches_hugepage_high_range(addr, len) \
-        (((addr) > (TASK_HPAGE_BASE-(len))) && ((addr) < TASK_HPAGE_END))
+        (LOW_ESID_MASK((addr), (len)) & (mm)->context.low_htlb_areas)
+#define touches_hugepage_high_range(mm, addr, len) \
+        (HTLB_AREA_MASK((addr), (len)) & (mm)->context.high_htlb_areas)
 
 #define __within_hugepage_low_range(addr, len, segmask) \
         ((LOW_ESID_MASK((addr), (len)) | (segmask)) == (segmask))
 #define within_hugepage_low_range(addr, len) \
         __within_hugepage_low_range((addr), (len), \
-                                    current->mm->context.htlb_segs)
-#define within_hugepage_high_range(addr, len) (((addr) >= TASK_HPAGE_BASE) \
-          && ((addr)+(len) <= TASK_HPAGE_END) && ((addr)+(len) >= (addr)))
+                                    current->mm->context.low_htlb_areas)
+#define __within_hugepage_high_range(addr, len, zonemask) \
+        ((HTLB_AREA_MASK((addr), (len)) | (zonemask)) == (zonemask))
+#define within_hugepage_high_range(addr, len) \
+        __within_hugepage_high_range((addr), (len), \
+                                    current->mm->context.high_htlb_areas)
 
 #define is_hugepage_only_range(mm, addr, len) \
-        (touches_hugepage_high_range((addr), (len)) || \
+        (touches_hugepage_high_range((mm), (addr), (len)) || \
           touches_hugepage_low_range((mm), (addr), (len)))
 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
 
 #define in_hugepage_area(context, addr) \
         (cpu_has_feature(CPU_FTR_16M_PAGE) && \
-         ( (((addr) >= TASK_HPAGE_BASE) && ((addr) < TASK_HPAGE_END)) || \
+         ( ((1 << GET_HTLB_AREA(addr)) & (context).high_htlb_areas) || \
            ( ((addr) < 0x100000000L) && \
-             ((1 << GET_ESID(addr)) & (context).htlb_segs) ) ) )
+             ((1 << GET_ESID(addr)) & (context).low_htlb_areas) ) ) )
 
 #else /* !CONFIG_HUGETLB_PAGE */
 
@@ -125,55 +131,47 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct pag
  * Entries in the pte table are 64b, while entries in the pgd & pmd are 32b.
  */
 typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned int  pmd; } pmd_t;
-typedef struct { unsigned int  pgd; } pgd_t;
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pud; } pud_t;
+typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 
 #define pte_val(x)      ((x).pte)
 #define pmd_val(x)      ((x).pmd)
+#define pud_val(x)      ((x).pud)
 #define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
 
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
+#define __pte(x)        ((pte_t) { (x) })
+#define __pmd(x)        ((pmd_t) { (x) })
+#define __pud(x)        ((pud_t) { (x) })
+#define __pgd(x)        ((pgd_t) { (x) })
+#define __pgprot(x)     ((pgprot_t) { (x) })
 
 #else
 /*
  * .. while these make it easier on the compiler
  */
 typedef unsigned long pte_t;
-typedef unsigned int  pmd_t;
-typedef unsigned int  pgd_t;
+typedef unsigned long pmd_t;
+typedef unsigned long pud_t;
+typedef unsigned long pgd_t;
 typedef unsigned long pgprot_t;
 
 #define pte_val(x)      (x)
 #define pmd_val(x)      (x)
+#define pud_val(x)      (x)
 #define pgd_val(x)      (x)
 #define pgprot_val(x)   (x)
 
 #define __pte(x)        (x)
 #define __pmd(x)        (x)
+#define __pud(x)        (x)
 #define __pgd(x)        (x)
 #define __pgprot(x)     (x)
 
 #endif
 
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
 
 extern int page_is_ram(unsigned long pfn);
@@ -202,24 +200,20 @@ extern u64 ppc64_pft_size;		/* Log 2 of page table size */
 #define PAGE_OFFSET     ASM_CONST(0xC000000000000000)
 #define KERNELBASE      PAGE_OFFSET
 #define VMALLOCBASE     ASM_CONST(0xD000000000000000)
-#define IOREGIONBASE    ASM_CONST(0xE000000000000000)
 
-#define IO_REGION_ID       (IOREGIONBASE >> REGION_SHIFT)
 #define VMALLOC_REGION_ID  (VMALLOCBASE >> REGION_SHIFT)
 #define KERNEL_REGION_ID   (KERNELBASE >> REGION_SHIFT)
 #define USER_REGION_ID     (0UL)
 #define REGION_ID(ea)      (((unsigned long)(ea)) >> REGION_SHIFT)
 
-#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE)
-#define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT)
-
 #define __va(x) ((void *)((unsigned long)(x) + KERNELBASE))
 
 #ifdef CONFIG_DISCONTIGMEM
 #define page_to_pfn(page)       discontigmem_page_to_pfn(page)
 #define pfn_to_page(pfn)        discontigmem_pfn_to_page(pfn)
 #define pfn_valid(pfn)          discontigmem_pfn_valid(pfn)
-#else
+#endif
+#ifdef CONFIG_FLATMEM
 #define pfn_to_page(pfn)        (mem_map + (pfn))
 #define page_to_pfn(page)       ((unsigned long)((page) - mem_map))
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
@@ -262,4 +256,7 @@ extern u64 ppc64_pft_size;		/* Log 2 of page table size */
          VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
 
 #endif /* __KERNEL__ */
+
+#include <asm-generic/page.h>
+
 #endif /* _PPC64_PAGE_H */
diff --git a/include/asm-ppc64/param.h b/include/asm-ppc64/param.h
index 1fad38dcf707..76c212d475b3 100644
--- a/include/asm-ppc64/param.h
+++ b/include/asm-ppc64/param.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_PPC64_PARAM_H
 #define _ASM_PPC64_PARAM_H
 
+#include <linux/config.h>
+
 /*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -9,7 +11,7 @@
  */
 
 #ifdef __KERNEL__
-# define HZ             1000            /* Internal kernel timer frequency */
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
 # define USER_HZ        100             /* .. some user interfaces are in "ticks" */
 # define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
 #endif
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index 6cd593f660a0..4d057452f59b 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -37,7 +37,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -78,6 +78,25 @@ static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
         return 0;
 }
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
 extern int pci_domain_nr(struct pci_bus *bus);
 
 /* Decide whether to display the domain number in /proc */
@@ -115,6 +134,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
                         struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
+
 extern int
 unmap_bus_range(struct pci_bus *bus);
 
@@ -136,6 +159,13 @@ extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
                                          unsigned long size,
                                          pgprot_t prot);
 
+#ifdef CONFIG_PPC_MULTIPLATFORM
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
+                                 const struct resource *rsrc,
+                                 u64 *start, u64 *end);
+#endif /* CONFIG_PPC_MULTIPLATFORM */
+
 
 #endif  /* __KERNEL__ */
 
diff --git a/include/asm-ppc64/percpu.h b/include/asm-ppc64/percpu.h
deleted file mode 100644
index 60a659a4ce1f..000000000000
--- a/include/asm-ppc64/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_PPC64_PERCPU__
-#define __ARCH_PPC64_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_PPC64_PERCPU__ */
diff --git a/include/asm-ppc64/pgalloc.h b/include/asm-ppc64/pgalloc.h
index 4fc4b739b380..26bc49c1108d 100644
--- a/include/asm-ppc64/pgalloc.h
+++ b/include/asm-ppc64/pgalloc.h
@@ -6,7 +6,12 @@
 #include <linux/cpumask.h>
 #include <linux/percpu.h>
 
-extern kmem_cache_t *zero_cache;
+extern kmem_cache_t *pgtable_cache[];
+
+#define PTE_CACHE_NUM   0
+#define PMD_CACHE_NUM   1
+#define PUD_CACHE_NUM   1
+#define PGD_CACHE_NUM   0
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -15,30 +20,40 @@ extern kmem_cache_t *zero_cache;
  * 2 of the License, or (at your option) any later version.
  */
 
-static inline pgd_t *
-pgd_alloc(struct mm_struct *mm)
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return kmem_cache_alloc(zero_cache, GFP_KERNEL);
+        return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
 }
 
-static inline void
-pgd_free(pgd_t *pgd)
+static inline void pgd_free(pgd_t *pgd)
 {
-        kmem_cache_free(zero_cache, pgd);
+        kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
+}
+
+#define pgd_populate(MM, PGD, PUD)      pgd_set(PGD, PUD)
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pud_free(pud_t *pud)
+{
+        kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
 }
 
 #define pud_populate(MM, PUD, PMD)      pud_set(PUD, PMD)
 
-static inline pmd_t *
-pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT);
+        return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
 }
 
-static inline void
-pmd_free(pmd_t *pmd)
+static inline void pmd_free(pmd_t *pmd)
 {
-        kmem_cache_free(zero_cache, pmd);
+        kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
 }
 
 #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte)
@@ -47,44 +62,58 @@ pmd_free(pmd_t *pmd)
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 {
-        return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT);
+        return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
 {
-        pte_t *pte = kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT);
-        if (pte)
-                return virt_to_page(pte);
-        return NULL;
+        return virt_to_page(pte_alloc_one_kernel(mm, address));
 }
                 
 static inline void pte_free_kernel(pte_t *pte)
 {
-        kmem_cache_free(zero_cache, pte);
+        kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte);
 }
 
 static inline void pte_free(struct page *ptepage)
 {
-        kmem_cache_free(zero_cache, page_address(ptepage));
+        pte_free_kernel(page_address(ptepage));
 }
 
-struct pte_freelist_batch
+#define PGF_CACHENUM_MASK       0xf
+
+typedef struct pgtable_free {
+        unsigned long val;
+} pgtable_free_t;
+
+static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
+                                                unsigned long mask)
 {
-        struct rcu_head rcu;
-        unsigned int    index;
-        struct page *   pages[0];
-};
+        BUG_ON(cachenum > PGF_CACHENUM_MASK);
 
-#define PTE_FREELIST_SIZE       ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) / \
-                                  sizeof(struct page *))
+        return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
+}
 
-extern void pte_free_now(struct page *ptepage);
-extern void pte_free_submit(struct pte_freelist_batch *batch);
+static inline void pgtable_free(pgtable_free_t pgf)
+{
+        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
+        int cachenum = pgf.val & PGF_CACHENUM_MASK;
 
-DECLARE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
+        kmem_cache_free(pgtable_cache[cachenum], p);
+}
 
-void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage);
-#define __pmd_free_tlb(tlb, pmd)        __pte_free_tlb(tlb, virt_to_page(pmd))
+void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+
+#define __pte_free_tlb(tlb, ptepage)    \
+        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
+                PTE_CACHE_NUM, PTE_TABLE_SIZE-1))
+#define __pmd_free_tlb(tlb, pmd)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
+                PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
+#define __pud_free_tlb(tlb, pmd)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
+                PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
 
 #define check_pgt_cache()       do { } while (0)
 
diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h
index 264c4f7993be..c83679c9d2b0 100644
--- a/include/asm-ppc64/pgtable.h
+++ b/include/asm-ppc64/pgtable.h
@@ -15,19 +15,24 @@
 #include <asm/tlbflush.h>
 #endif /* __ASSEMBLY__ */
 
-#include <asm-generic/pgtable-nopud.h>
-
 /*
  * Entries per page directory level.  The PTE level must use a 64b record
  * for each page table entry.  The PMD and PGD level use a 32b record for 
  * each entry by assuming that each entry is page aligned.
  */
 #define PTE_INDEX_SIZE  9
-#define PMD_INDEX_SIZE  10
-#define PGD_INDEX_SIZE  10
+#define PMD_INDEX_SIZE  7
+#define PUD_INDEX_SIZE  7
+#define PGD_INDEX_SIZE  9
+
+#define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
+#define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
+#define PUD_TABLE_SIZE  (sizeof(pud_t) << PUD_INDEX_SIZE)
+#define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
 
 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PUD    (1 << PMD_INDEX_SIZE)
 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
 
 /* PMD_SHIFT determines what a second-level page table entry can map */
@@ -35,8 +40,13 @@
 #define PMD_SIZE        (1UL << PMD_SHIFT)
 #define PMD_MASK        (~(PMD_SIZE-1))
 
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PMD_SHIFT + PMD_INDEX_SIZE)
+/* PUD_SHIFT determines what a third-level page table entry can map */
+#define PUD_SHIFT       (PMD_SHIFT + PMD_INDEX_SIZE)
+#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_MASK        (~(PUD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
+#define PGDIR_SHIFT     (PUD_SHIFT + PUD_INDEX_SIZE)
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
@@ -45,15 +55,24 @@
 /*
  * Size of EA range mapped by our pagetables.
  */
-#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
-                    PGD_INDEX_SIZE + PAGE_SHIFT)
-#define EADDR_MASK ((1UL << EADDR_SIZE) - 1)
+#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
+                            PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
+#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
+
+#if TASK_SIZE_USER64 > PGTABLE_RANGE
+#error TASK_SIZE_USER64 exceeds pagetable range
+#endif
+
+#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#error TASK_SIZE_USER64 exceeds user VSID range
+#endif
 
 /*
  * Define the address range of the vmalloc VM area.
  */
 #define VMALLOC_START (0xD000000000000000ul)
-#define VMALLOC_END   (VMALLOC_START + EADDR_MASK)
+#define VMALLOC_SIZE  (0x80000000000UL)
+#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
 
 /*
  * Bits in a linux-style PTE.  These match the bits in the
@@ -153,8 +172,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
 #ifndef __ASSEMBLY__
 int hash_huge_page(struct mm_struct *mm, unsigned long access,
                    unsigned long ea, unsigned long vsid, int local);
-
-void hugetlb_mm_free_pgd(struct mm_struct *mm);
 #endif /* __ASSEMBLY__ */
 
 #define HAVE_ARCH_UNMAPPED_AREA
@@ -162,7 +179,6 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm);
 #else
 
 #define hash_huge_page(mm,a,ea,vsid,local)      -1
-#define hugetlb_mm_free_pgd(mm)                 do {} while (0)
 
 #endif
 
@@ -196,39 +212,45 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 #define pte_pfn(x)              ((unsigned long)((pte_val(x) >> PTE_SHIFT)))
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 
-#define pmd_set(pmdp, ptep)     \
-        (pmd_val(*(pmdp)) = __ba_to_bpn(ptep))
+#define pmd_set(pmdp, ptep)     ({BUG_ON((u64)ptep < KERNELBASE); pmd_val(*(pmdp)) = (unsigned long)(ptep);})
 #define pmd_none(pmd)           (!pmd_val(pmd))
 #define pmd_bad(pmd)            (pmd_val(pmd) == 0)
 #define pmd_present(pmd)        (pmd_val(pmd) != 0)
 #define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
-#define pmd_page_kernel(pmd)    (__bpn_to_ba(pmd_val(pmd)))
+#define pmd_page_kernel(pmd)    (pmd_val(pmd))
 #define pmd_page(pmd)           virt_to_page(pmd_page_kernel(pmd))
 
-#define pud_set(pudp, pmdp)     (pud_val(*(pudp)) = (__ba_to_bpn(pmdp)))
+#define pud_set(pudp, pmdp)     (pud_val(*(pudp)) = (unsigned long)(pmdp))
 #define pud_none(pud)           (!pud_val(pud))
-#define pud_bad(pud)            ((pud_val(pud)) == 0UL)
-#define pud_present(pud)        (pud_val(pud) != 0UL)
-#define pud_clear(pudp)         (pud_val(*(pudp)) = 0UL)
-#define pud_page(pud)           (__bpn_to_ba(pud_val(pud)))
+#define pud_bad(pud)            ((pud_val(pud)) == 0)
+#define pud_present(pud)        (pud_val(pud) != 0)
+#define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
+#define pud_page(pud)           (pud_val(pud))
+
+#define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
+#define pgd_none(pgd)           (!pgd_val(pgd))
+#define pgd_bad(pgd)            (pgd_val(pgd) == 0)
+#define pgd_present(pgd)        (pgd_val(pgd) != 0)
+#define pgd_clear(pgdp)         (pgd_val(*(pgdp)) = 0)
+#define pgd_page(pgd)           (pgd_val(pgd))
 
 /* 
  * Find an entry in a page-table-directory.  We combine the address region 
  * (the high order N bits) and the pgd portion of the address.
  */
 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
-#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x7ff)
+#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
 
 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 
-/* Find an entry in the second-level page table.. */
+#define pud_offset(pgdp, addr)  \
+  (((pud_t *) pgd_page(*(pgdp))) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
+
 #define pmd_offset(pudp,addr) \
-  ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
+  (((pmd_t *) pud_page(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 
-/* Find an entry in the third-level page table.. */
 #define pte_offset_kernel(dir,addr) \
-  ((pte_t *) pmd_page_kernel(*(dir)) \
- + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+  (((pte_t *) pmd_page_kernel(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 
 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
@@ -239,9 +261,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 /* This now only contains the vmalloc pages */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
-/* to find an entry in the ioremap page-table-directory */
-#define pgd_offset_i(address) (ioremap_pgd + pgd_index(address))
-
 /*
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
@@ -459,27 +478,21 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
 #define __HAVE_ARCH_PTE_SAME
 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 
-extern unsigned long ioremap_bot, ioremap_base;
-
 #define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e))
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pud_ERROR(e) \
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pud_val(e))
 #define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e))
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
 extern pgd_t swapper_pg_dir[];
-extern pgd_t ioremap_dir[];
 
 extern void paging_init(void);
 
-/*
- * Because the huge pgtables are only 2 level, they can take
- * at most around 4M, much less than one hugepage which the
- * process is presumably entitled to use.  So we don't bother
- * freeing up the pagetables on unmap, and wait until
- * destroy_context() to clean up the lot.
- */
+#ifdef CONFIG_HUGETLB_PAGE
 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
-                                                do { } while (0)
+        free_pgd_range(tlb, addr, end, floor, ceiling)
+#endif
 
 /*
  * This gets called at the end of handling a page fault, when
diff --git a/include/asm-ppc64/pmc.h b/include/asm-ppc64/pmc.h
index c924748c0bea..d1d297dbccfe 100644
--- a/include/asm-ppc64/pmc.h
+++ b/include/asm-ppc64/pmc.h
@@ -26,4 +26,6 @@ typedef void (*perf_irq_t)(struct pt_regs *);
 int reserve_pmc_hardware(perf_irq_t new_perf_irq);
 void release_pmc_hardware(void);
 
+void power4_enable_pmcs(void);
+
 #endif /* _PPC64_PMC_H */
diff --git a/include/asm-ppc64/poll.h b/include/asm-ppc64/poll.h
deleted file mode 100644
index 370fa3ba0db4..000000000000
--- a/include/asm-ppc64/poll.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __PPC64_POLL_H
-#define __PPC64_POLL_H
-
-/*
- * Copyright (C) 2001 PPC64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define POLLIN          0x0001
-#define POLLPRI         0x0002
-#define POLLOUT         0x0004
-#define POLLERR         0x0008
-#define POLLHUP         0x0010
-#define POLLNVAL        0x0020
-#define POLLRDNORM      0x0040
-#define POLLRDBAND      0x0080
-#define POLLWRNORM      0x0100
-#define POLLWRBAND      0x0200
-#define POLLMSG         0x0400
-#define POLLREMOVE      0x1000
-
-struct pollfd {
-        int fd;
-        short events;
-        short revents;
-};
-
-#endif /* __PPC64_POLL_H */
diff --git a/include/asm-ppc64/ppc32.h b/include/asm-ppc64/ppc32.h
index 1d0404897550..6b44a8caf395 100644
--- a/include/asm-ppc64/ppc32.h
+++ b/include/asm-ppc64/ppc32.h
@@ -32,7 +32,7 @@ typedef struct compat_siginfo {
 
                 /* POSIX.1b timers */
                 struct {
-                        timer_t _tid;                   /* timer id */
+                        compat_timer_t _tid;                    /* timer id */
                         int _overrun;                   /* overrun count */
                         compat_sigval_t _sigval;                /* same as below */
                         int _sys_private;               /* not to be passed to user */
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 809c634ba1df..8bd7aa959385 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -20,6 +20,7 @@
 #include <asm/ptrace.h>
 #include <asm/types.h>
 #include <asm/systemcfg.h>
+#include <asm/cputable.h>
 
 /* Machine State Register (MSR) Fields */
 #define MSR_SF_LG       63              /* Enable 64 bit mode */
@@ -138,8 +139,16 @@
 #define SPRN_NIADORM    0x3F3   /* Hardware Implementation Register 2 */
 #define SPRN_HID4       0x3F4   /* 970 HID4 */
 #define SPRN_HID5       0x3F6   /* 970 HID5 */
-#define SPRN_TSC        0x3FD   /* Thread switch control */
-#define SPRN_TST        0x3FC   /* Thread switch timeout */
+#define SPRN_HID6       0x3F9   /* BE HID 6 */
+#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
+#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
+#define SPRN_TSCR       0x399   /* Thread switch control on BE */
+#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
+#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
+#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
+#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
+#define SPRN_TSC        0x3FD   /* Thread switch control on others */
+#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 #define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 #define SPRN_LR         0x008   /* Link Register */
 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
@@ -259,6 +268,8 @@
 #define PV_970FX        0x003C
 #define PV_630          0x0040
 #define PV_630p         0x0041
+#define PV_970MP        0x0044
+#define PV_BE           0x0070
 
 /* Platforms supported by PPC64 */
 #define PLATFORM_PSERIES      0x0100
@@ -267,6 +278,7 @@
 #define PLATFORM_LPAR         0x0001
 #define PLATFORM_POWERMAC     0x0400
 #define PLATFORM_MAPLE        0x0500
+#define PLATFORM_BPA          0x1000
 
 /* Compatibility with drivers coming from PPC32 world */
 #define _machine        (systemcfg->platform)
@@ -278,6 +290,7 @@
 #define IC_INVALID    0
 #define IC_OPEN_PIC   1
 #define IC_PPC_XIC    2
+#define IC_BPA_IIC    3
 
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
@@ -298,6 +311,20 @@ name: \
         .type GLUE(.,name),@function; \
 GLUE(.,name):
 
+#define _KPROBE(name) \
+        .section ".kprobes.text","a"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
 #define _STATIC(name) \
         .section ".text"; \
         .align 2 ; \
@@ -370,8 +397,8 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 extern struct task_struct *last_task_used_math;
 extern struct task_struct *last_task_used_altivec;
 
-/* 64-bit user address space is 41-bits (2TBs user VM) */
-#define TASK_SIZE_USER64 (0x0000020000000000UL)
+/* 64-bit user address space is 44-bits (16TB user VM) */
+#define TASK_SIZE_USER64 (0x0000100000000000UL)
 
 /* 
  * 32-bit user address space is 4GB - 1 page 
@@ -430,16 +457,6 @@ struct thread_struct {
 }
 
 /*
- * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space.  (Could vm_end == vm_start perhaps?)
- */
-#define IOREMAP_MMAP { &ioremap_mm, 0, 0x1000, NULL, \
-                    PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
-                    1, NULL, NULL }
-
-extern struct mm_struct ioremap_mm;
-
-/*
  * Return saved PC of a blocked thread. For now, this is the "user" PC
  */
 #define thread_saved_pc(tsk)    \
@@ -500,24 +517,37 @@ static inline void ppc64_runlatch_on(void)
 {
         unsigned long ctrl;
 
-        ctrl = mfspr(SPRN_CTRLF);
-        ctrl |= CTRL_RUNLATCH;
-        mtspr(SPRN_CTRLT, ctrl);
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl |= CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
 }
 
 static inline void ppc64_runlatch_off(void)
 {
         unsigned long ctrl;
 
-        ctrl = mfspr(SPRN_CTRLF);
-        ctrl &= ~CTRL_RUNLATCH;
-        mtspr(SPRN_CTRLT, ctrl);
+        if (cpu_has_feature(CPU_FTR_CTRL)) {
+                ctrl = mfspr(SPRN_CTRLF);
+                ctrl &= ~CTRL_RUNLATCH;
+                mtspr(SPRN_CTRLT, ctrl);
+        }
 }
 
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
 
+#ifdef __KERNEL__
+#define RUNLATCH_ON(REG)                        \
+BEGIN_FTR_SECTION                               \
+        mfspr   (REG),SPRN_CTRLF;               \
+        ori     (REG),(REG),CTRL_RUNLATCH;      \
+        mtspr   SPRN_CTRLT,(REG);               \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+#endif
+
 /*
  * Number of entries in the SLB. If this ever changes we should handle
  * it with a use a cpu feature fixup.
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index 04b1a84f7ca3..dc5330b39509 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -22,13 +22,15 @@
 #define RELOC(x)        (*PTRRELOC(&(x)))
 
 /* Definitions used by the flattened device tree */
-#define OF_DT_HEADER            0xd00dfeed      /* 4: version, 4: total size */
-#define OF_DT_BEGIN_NODE        0x1             /* Start node: full name */
+#define OF_DT_HEADER            0xd00dfeed      /* marker */
+#define OF_DT_BEGIN_NODE        0x1             /* Start of node, full name */
 #define OF_DT_END_NODE          0x2             /* End node */
-#define OF_DT_PROP              0x3             /* Property: name off, size, content */
+#define OF_DT_PROP              0x3             /* Property: name off, size,
+                                                 * content */
+#define OF_DT_NOP               0x4             /* nop */
 #define OF_DT_END               0x9
 
-#define OF_DT_VERSION           1
+#define OF_DT_VERSION           0x10
 
 /*
  * This is what gets passed to the kernel by prom_init or kexec
@@ -54,7 +56,9 @@ struct boot_param_header
         u32     version;                /* format version */
         u32     last_comp_version;      /* last compatible version */
         /* version 2 fields below */
-        u32     boot_cpuid_phys;        /* Which physical CPU id we're booting on */
+        u32     boot_cpuid_phys;        /* Physical CPU id we're booting on */
+        /* version 3 fields below */
+        u32     dt_strings_size;        /* size of the DT strings block */
 };
 
 
diff --git a/include/asm-ppc64/resource.h b/include/asm-ppc64/resource.h
deleted file mode 100644
index add031b9dfd4..000000000000
--- a/include/asm-ppc64/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _PPC64_RESOURCE_H
-#define _PPC64_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _PPC64_RESOURCE_H */
diff --git a/include/asm-ppc64/rtas.h b/include/asm-ppc64/rtas.h
index a8ab0e9db84a..e7d1b5222802 100644
--- a/include/asm-ppc64/rtas.h
+++ b/include/asm-ppc64/rtas.h
@@ -186,8 +186,14 @@ extern int rtas_get_sensor(int sensor, int index, int *state);
 extern int rtas_get_power_level(int powerdomain, int *level);
 extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
 extern int rtas_set_indicator(int indicator, int index, int new_value);
+extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
 
+struct rtc_time;
+extern void rtas_get_boot_time(struct rtc_time *rtc_time);
+extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
+extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
+
 /* Given an RTAS status code of 9900..9905 compute the hinted delay */
 unsigned int rtas_extended_busy_delay_time(int status);
 static inline int rtas_is_extended_busy(int status)
diff --git a/include/asm-ppc64/smp.h b/include/asm-ppc64/smp.h
index c8646fa999c2..d86f742e9a21 100644
--- a/include/asm-ppc64/smp.h
+++ b/include/asm-ppc64/smp.h
@@ -45,7 +45,7 @@ void generic_cpu_die(unsigned int cpu);
 void generic_mach_cpu_die(void);
 #endif
 
-#define __smp_processor_id() (get_paca()->paca_index)
+#define raw_smp_processor_id()  (get_paca()->paca_index)
 #define hard_smp_processor_id() (get_paca()->hw_cpu_id)
 
 extern cpumask_t cpu_sibling_map[NR_CPUS];
@@ -85,6 +85,14 @@ extern void smp_generic_take_timebase(void);
 
 extern struct smp_ops_t *smp_ops;
 
+#ifdef CONFIG_PPC_PSERIES
+void vpa_init(int cpu);
+#else
+static inline void vpa_init(int cpu)
+{
+}
+#endif /* CONFIG_PPC_PSERIES */
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* !(_PPC64_SMP_H) */
diff --git a/include/asm-ppc64/sparsemem.h b/include/asm-ppc64/sparsemem.h
new file mode 100644
index 000000000000..c5bd47e57f17
--- /dev/null
+++ b/include/asm-ppc64/sparsemem.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_PPC64_SPARSEMEM_H
+#define _ASM_PPC64_SPARSEMEM_H 1
+
+#ifdef CONFIG_SPARSEMEM
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSADDR_BITS            2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       24
+#define MAX_PHYSADDR_BITS       38
+#define MAX_PHYSMEM_BITS        36
+
+#endif /* CONFIG_SPARSEMEM */
+
+#endif /* _ASM_PPC64_SPARSEMEM_H */
diff --git a/include/asm-ppc64/string.h b/include/asm-ppc64/string.h
deleted file mode 100644
index eeca68ef1e91..000000000000
--- a/include/asm-ppc64/string.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef _PPC64_STRING_H_
-#define _PPC64_STRING_H_
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCHR
-
-extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, int);
-extern char * strcpy(char *,const char *);
-extern char * strncpy(char *,const char *, __kernel_size_t);
-extern __kernel_size_t strlen(const char *);
-extern int strcmp(const char *,const char *);
-extern char * strcat(char *, const char *);
-extern void * memset(void *,int,__kernel_size_t);
-extern void * memcpy(void *,const void *,__kernel_size_t);
-extern void * memmove(void *,const void *,__kernel_size_t);
-extern int memcmp(const void *,const void *,__kernel_size_t);
-extern void * memchr(const void *,int,__kernel_size_t);
-
-#endif /* _PPC64_STRING_H_ */
diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h
index 98d120ca8a91..c0396428cc3c 100644
--- a/include/asm-ppc64/system.h
+++ b/include/asm-ppc64/system.h
@@ -88,7 +88,7 @@ DEBUGGER_BOILERPLATE(debugger_dabr_match)
 DEBUGGER_BOILERPLATE(debugger_fault_handler)
 
 #ifdef CONFIG_XMON
-extern void xmon_init(void);
+extern void xmon_init(int enable);
 #endif
 
 #else
@@ -158,7 +158,7 @@ static inline int __is_processor(unsigned long pv)
  * is more like most of the other architectures.
  */
 static __inline__ unsigned long
-__xchg_u32(volatile int *m, unsigned long val)
+__xchg_u32(volatile unsigned int *m, unsigned long val)
 {
         unsigned long dummy;
 
@@ -200,7 +200,7 @@ __xchg_u64(volatile long *m, unsigned long val)
 extern void __xchg_called_with_bad_pointer(void);
 
 static __inline__ unsigned long
-__xchg(volatile void *ptr, unsigned long x, int size)
+__xchg(volatile void *ptr, unsigned long x, unsigned int size)
 {
         switch (size) {
         case 4:
@@ -223,7 +223,7 @@ __xchg(volatile void *ptr, unsigned long x, int size)
 #define __HAVE_ARCH_CMPXCHG     1
 
 static __inline__ unsigned long
-__cmpxchg_u32(volatile int *p, int old, int new)
+__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 {
         unsigned int prev;
 
@@ -271,7 +271,8 @@ __cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
 extern void __cmpxchg_called_with_bad_pointer(void);
 
 static __inline__ unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
 {
         switch (size) {
         case 4:
@@ -283,13 +284,9 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
         return old;
 }
 
-#define cmpxchg(ptr,o,n)                                                 \
-  ({                                                                     \
-     __typeof__(*(ptr)) _o_ = (o);                                       \
-     __typeof__(*(ptr)) _n_ = (n);                                       \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
-                                    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
+#define cmpxchg(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
+        (unsigned long)(n),sizeof(*(ptr))))
 
 /*
  * We handle most unaligned accesses in hardware. On the other hand 
@@ -302,5 +299,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 
 #define arch_align_stack(x) (x)
 
+extern unsigned long reloc_offset(void);
+
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 48b7900e90ec..0494df6fca74 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -24,7 +24,7 @@ struct thread_info {
         struct task_struct *task;               /* main task structure */
         struct exec_domain *exec_domain;        /* execution domain */
         int             cpu;                    /* cpu we're on */
-        int             preempt_count;
+        int             preempt_count;          /* 0 => preemptable, <0 => BUG */
         struct restart_block restart_block;
         /* set by force_successful_syscall_return */
         unsigned char   syscall_noerror;
diff --git a/include/asm-ppc64/time.h b/include/asm-ppc64/time.h
index 8d6e3760ee10..c6c762cad8b0 100644
--- a/include/asm-ppc64/time.h
+++ b/include/asm-ppc64/time.h
@@ -34,6 +34,15 @@ struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
 extern time_t last_rtc_update;
 
+void generic_calibrate_decr(void);
+void setup_default_decr(void);
+
+/* Some sane defaults: 125 MHz timebase, 1GHz processor */
+extern unsigned long ppc_proc_freq;
+#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
+extern unsigned long ppc_tb_freq;
+#define DEFAULT_TB_FREQ         125000000UL
+
 /*
  * By putting all of this stuff into a single struct we 
  * reduce the number of cache lines touched by do_gettimeofday.
diff --git a/include/asm-ppc64/topology.h b/include/asm-ppc64/topology.h
index d58d9dd79998..1e9b19073230 100644
--- a/include/asm-ppc64/topology.h
+++ b/include/asm-ppc64/topology.h
@@ -33,6 +33,7 @@ static inline int node_to_first_cpu(int node)
         return first_cpu(tmp);
 }
 
+#define pcibus_to_node(node)    (-1)
 #define pcibus_to_cpumask(bus)  (cpu_online_map)
 
 #define nr_cpus_node(node)      (nr_cpus_in_node[node])
@@ -59,7 +60,7 @@ static inline int node_to_first_cpu(int node)
         .nr_balance_failed      = 0,                    \
 }
 
-#else /* !CONFIG_NUMA */
+#else
 
 #include <asm-generic/topology.h>
 
diff --git a/include/asm-ppc64/types.h b/include/asm-ppc64/types.h
index 5b8c2cfa1138..bf294c1761b2 100644
--- a/include/asm-ppc64/types.h
+++ b/include/asm-ppc64/types.h
@@ -72,7 +72,6 @@ typedef struct {
         unsigned long env;
 } func_descr_t;
 
-typedef unsigned int kmem_bufctl_t;
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/uaccess.h b/include/asm-ppc64/uaccess.h
index 05b5943ab1ee..c181a60d868c 100644
--- a/include/asm-ppc64/uaccess.h
+++ b/include/asm-ppc64/uaccess.h
@@ -56,13 +56,6 @@
 #define access_ok(type,addr,size) \
         __access_ok(((__force unsigned long)(addr)),(size),get_fs())
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user *addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-ppc64/udbg.h b/include/asm-ppc64/udbg.h
index a6e04d014b2b..c786604aef02 100644
--- a/include/asm-ppc64/udbg.h
+++ b/include/asm-ppc64/udbg.h
@@ -2,6 +2,7 @@
 #define __UDBG_HDR
 
 #include <linux/compiler.h>
+#include <linux/init.h>
 
 /*
  * c 2001 PPC 64 Team, IBM Corp
@@ -12,17 +13,19 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-void udbg_init_uart(void __iomem *comport, unsigned int speed);
-void udbg_putc(unsigned char c);
-unsigned char udbg_getc(void);
-int udbg_getc_poll(void);
-void udbg_puts(const char *s);
-int udbg_write(const char *s, int n);
-int udbg_read(char *buf, int buflen);
-struct console;
-void udbg_console_write(struct console *con, const char *s, unsigned int n);
-void udbg_printf(const char *fmt, ...);
-void udbg_ppcdbg(unsigned long flags, const char *fmt, ...);
-unsigned long udbg_ifdebug(unsigned long flags);
+extern void (*udbg_putc)(unsigned char c);
+extern unsigned char (*udbg_getc)(void);
+extern int (*udbg_getc_poll)(void);
 
+extern void udbg_puts(const char *s);
+extern int udbg_write(const char *s, int n);
+extern int udbg_read(char *buf, int buflen);
+
+extern void register_early_udbg_console(void);
+extern void udbg_printf(const char *fmt, ...);
+extern void udbg_ppcdbg(unsigned long flags, const char *fmt, ...);
+extern unsigned long udbg_ifdebug(unsigned long flags);
+extern void __init ppcdbg_initialize(void);
+
+extern void udbg_init_uart(void __iomem *comport, unsigned int speed);
 #endif
diff --git a/include/asm-ppc64/unaligned.h b/include/asm-ppc64/unaligned.h
deleted file mode 100644
index 636e93c4f379..000000000000
--- a/include/asm-ppc64/unaligned.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __PPC64_UNALIGNED_H
-#define __PPC64_UNALIGNED_H
-
-/*
- * The PowerPC can do unaligned accesses itself in big endian mode. 
- *
- * The strange macros are there to make sure these can't
- * be misused in a way that makes them not work on other
- * architectures where unaligned accesses aren't as simple.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define get_unaligned(ptr) (*(ptr))
-
-#define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
-
-#endif /* __PPC64_UNALIGNED_H */
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
index 605d91e011ec..977bc980c1af 100644
--- a/include/asm-ppc64/unistd.h
+++ b/include/asm-ppc64/unistd.h
@@ -268,7 +268,7 @@
 #define __NR_rtas               255
 /* Number 256 is reserved for sys_debug_setcontext */
 /* Number 257 is reserved for vserver */
-/* Number 258 is reserved for new sys_remap_file_pages */
+/* 258 currently unused */
 #define __NR_mbind              259
 #define __NR_get_mempolicy      260
 #define __NR_set_mempolicy      261
@@ -283,8 +283,13 @@
 #define __NR_request_key        270
 #define __NR_keyctl             271
 #define __NR_waitid             272
+#define __NR_ioprio_set         273
+#define __NR_ioprio_get         274
+#define __NR_inotify_init       275
+#define __NR_inotify_add_watch  276
+#define __NR_inotify_rm_watch   277
 
-#define __NR_syscalls           273
+#define __NR_syscalls           278
 #ifdef __KERNEL__
 #define NR_syscalls     __NR_syscalls
 #endif
diff --git a/include/asm-ppc64/vio.h b/include/asm-ppc64/vio.h
index 20cd98ee6337..03f1b95f433b 100644
--- a/include/asm-ppc64/vio.h
+++ b/include/asm-ppc64/vio.h
@@ -19,13 +19,15 @@
 #include <linux/errno.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/mod_devicetable.h>
+
 #include <asm/hvcall.h>
-#include <asm/prom.h>
 #include <asm/scatterlist.h>
-/* 
+
+/*
  * Architecture-specific constants for drivers to
  * extract attributes of the device using vio_get_attribute()
-*/
+ */
 #define VETH_MAC_ADDR "local-mac-address"
 #define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters"
 
@@ -37,64 +39,65 @@
 #define VIO_IRQ_DISABLE         0UL
 #define VIO_IRQ_ENABLE          1UL
 
-struct vio_dev;
-struct vio_driver;
-struct vio_device_id;
 struct iommu_table;
 
-int vio_register_driver(struct vio_driver *drv);
-void vio_unregister_driver(struct vio_driver *drv);
-
-#ifdef CONFIG_PPC_PSERIES
-struct vio_dev * __devinit vio_register_device_node(
-                struct device_node *node_vdev);
-#endif
-void __devinit vio_unregister_device(struct vio_dev *dev);
-struct vio_dev *vio_find_node(struct device_node *vnode);
-
-const void * vio_get_attribute(struct vio_dev *vdev, void* which, int* length);
-int vio_get_irq(struct vio_dev *dev);
-int vio_enable_interrupts(struct vio_dev *dev);
-int vio_disable_interrupts(struct vio_dev *dev);
-
-extern struct dma_mapping_ops vio_dma_ops;
-
-extern struct bus_type vio_bus_type;
-
-struct vio_device_id {
+/*
+ * The vio_dev structure is used to describe virtual I/O devices.
+ */
+struct vio_dev {
+        struct iommu_table *iommu_table;     /* vio_map_* uses this */
+        char *name;
         char *type;
-        char *compat;
+        uint32_t unit_address;
+        unsigned int irq;
+        struct device dev;
 };
 
 struct vio_driver {
         struct list_head node;
         char *name;
-        const struct vio_device_id *id_table;   /* NULL if wants all devices */
-        int  (*probe)  (struct vio_dev *dev, const struct vio_device_id *id);   /* New device inserted */
-        int (*remove) (struct vio_dev *dev);    /* Device removed (NULL if not a hot-plug capable driver) */
+        const struct vio_device_id *id_table;
+        int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
+        int (*remove)(struct vio_dev *dev);
         unsigned long driver_data;
-
         struct device_driver driver;
 };
 
+struct vio_bus_ops {
+        int (*match)(const struct vio_device_id *id, const struct vio_dev *dev);
+        void (*unregister_device)(struct vio_dev *);
+        void (*release_device)(struct device *);
+};
+
+extern struct dma_mapping_ops vio_dma_ops;
+extern struct bus_type vio_bus_type;
+extern struct vio_dev vio_bus_device;
+
+extern int vio_register_driver(struct vio_driver *drv);
+extern void vio_unregister_driver(struct vio_driver *drv);
+
+extern struct vio_dev * __devinit vio_register_device(struct vio_dev *viodev);
+extern void __devinit vio_unregister_device(struct vio_dev *dev);
+
+extern int vio_bus_init(struct vio_bus_ops *);
+
+#ifdef CONFIG_PPC_PSERIES
+struct device_node;
+
+extern struct vio_dev * __devinit vio_register_device_node(
+                struct device_node *node_vdev);
+extern struct vio_dev *vio_find_node(struct device_node *vnode);
+extern const void *vio_get_attribute(struct vio_dev *vdev, void *which,
+                int *length);
+extern int vio_enable_interrupts(struct vio_dev *dev);
+extern int vio_disable_interrupts(struct vio_dev *dev);
+#endif
+
 static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
 {
         return container_of(drv, struct vio_driver, driver);
 }
 
-/*
- * The vio_dev structure is used to describe virtual I/O devices.
- */
-struct vio_dev {
-        struct iommu_table *iommu_table;     /* vio_map_* uses this */
-        char *name;
-        char *type;
-        uint32_t unit_address;  
-        unsigned int irq;
-
-        struct device dev;
-};
-
 static inline struct vio_dev *to_vio_dev(struct device *dev)
 {
         return container_of(dev, struct vio_dev, dev);
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
index fdec5e7a7af6..1092af55d707 100644
--- a/include/asm-ppc64/xics.h
+++ b/include/asm-ppc64/xics.h
@@ -17,6 +17,7 @@
 void xics_init_IRQ(void);
 int xics_get_irq(struct pt_regs *);
 void xics_setup_cpu(void);
+void xics_teardown_cpu(int secondary);
 void xics_cause_IPI(int cpu);
 void xics_request_IPIs(void);
 void xics_migrate_irqs_away(void);
diff --git a/include/asm-ppc64/xor.h b/include/asm-ppc64/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/include/asm-ppc64/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index d5a05cf47168..9d86ba6f12d0 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -123,19 +123,19 @@ typedef struct {
 #define atomic64_read(v)          ((v)->counter)
 #define atomic64_set(v,i)         (((v)->counter) = (i))
 
-static __inline__ void atomic64_add(int i, atomic64_t * v)
+static __inline__ void atomic64_add(long long i, atomic64_t * v)
 {
                __CSG_LOOP(v, i, "agr");
 }
-static __inline__ long long atomic64_add_return(int i, atomic64_t * v)
+static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
 {
         return __CSG_LOOP(v, i, "agr");
 }
-static __inline__ long long atomic64_add_negative(int i, atomic64_t * v)
+static __inline__ long long atomic64_add_negative(long long i, atomic64_t * v)
 {
         return __CSG_LOOP(v, i, "agr") < 0;
 }
-static __inline__ void atomic64_sub(int i, atomic64_t * v)
+static __inline__ void atomic64_sub(long long i, atomic64_t * v)
 {
                __CSG_LOOP(v, i, "sgr");
 }
diff --git a/include/asm-s390/auxvec.h b/include/asm-s390/auxvec.h
new file mode 100644
index 000000000000..0d340720fd99
--- /dev/null
+++ b/include/asm-s390/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMS390_AUXVEC_H
+#define __ASMS390_AUXVEC_H
+
+#endif
diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h
index 16bb08499c7f..8651524217fd 100644
--- a/include/asm-s390/bitops.h
+++ b/include/asm-s390/bitops.h
@@ -527,13 +527,64 @@ __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
  __constant_test_bit((nr),(addr)) : \
  __test_bit((nr),(addr)) )
 
-#ifndef __s390x__
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long bit = 0;
+
+#ifdef __s390x__
+        if (likely((word & 0xffffffff) == 0xffffffff)) {
+                word >>= 32;
+                bit += 32;
+        }
+#endif
+        if (likely((word & 0xffff) == 0xffff)) {
+                word >>= 16;
+                bit += 16;
+        }
+        if (likely((word & 0xff) == 0xff)) {
+                word >>= 8;
+                bit += 8;
+        }
+        return bit + _zb_findmap[word & 0xff];
+}
+
+/*
+ * __ffs = find first bit in word. Undefined if no bit exists,
+ * so code should check against 0UL first..
+ */
+static inline unsigned long __ffs (unsigned long word)
+{
+        unsigned long bit = 0;
+
+#ifdef __s390x__
+        if (likely((word & 0xffffffff) == 0)) {
+                word >>= 32;
+                bit += 32;
+        }
+#endif
+        if (likely((word & 0xffff) == 0)) {
+                word >>= 16;
+                bit += 16;
+        }
+        if (likely((word & 0xff) == 0)) {
+                word >>= 8;
+                bit += 8;
+        }
+        return bit + _sb_findmap[word & 0xff];
+}
 
 /*
  * Find-bit routines..
  */
+
+#ifndef __s390x__
+
 static inline int
-find_first_zero_bit(const unsigned long * addr, unsigned int size)
+find_first_zero_bit(const unsigned long * addr, unsigned long size)
 {
         typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
         unsigned long cmp, count;
@@ -548,7 +599,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
                 "   srl  %2,5\n"
                 "0: c    %1,0(%0,%4)\n"
                 "   jne  1f\n"
-                "   ahi  %0,4\n"
+                "   la   %0,4(%0)\n"
                 "   brct %2,0b\n"
                 "   lr   %0,%3\n"
                 "   j    4f\n"
@@ -574,7 +625,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
 }
 
 static inline int
-find_first_bit(const unsigned long * addr, unsigned int size)
+find_first_bit(const unsigned long * addr, unsigned long size)
 {
         typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
         unsigned long cmp, count;
@@ -589,7 +640,7 @@ find_first_bit(const unsigned long * addr, unsigned int size)
                 "   srl  %2,5\n"
                 "0: c    %1,0(%0,%4)\n"
                 "   jne  1f\n"
-                "   ahi  %0,4\n"
+                "   la   %0,4(%0)\n"
                 "   brct %2,0b\n"
                 "   lr   %0,%3\n"
                 "   j    4f\n"
@@ -614,89 +665,8 @@ find_first_bit(const unsigned long * addr, unsigned int size)
         return (res < size) ? res : size;
 }
 
-static inline int
-find_next_zero_bit (const unsigned long * addr, int size, int offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
-        unsigned long bitvec, reg;
-        int set, bit = offset & 31, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slr  %0,%0\n"
-                        "   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                        "   jno  0f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "0: tml  %1,0x00ff\n"
-                        "   jno  1f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "1: nr   %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (set < (32 - bit))
-                        return set + offset;
-                offset += 32 - bit;
-                p++;
-        }
-        /*
-         * No zero yet, search remaining full words for a zero
-         */
-        res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
-static inline int
-find_next_bit (const unsigned long * addr, int size, int offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
-        unsigned long bitvec, reg;
-        int set, bit = offset & 31, res;
-
-        if (bit) {
-                /*
-                 * Look for set bit in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slr  %0,%0\n"
-                        "   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                        "   jnz  0f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "0: tml  %1,0x00ff\n"
-                        "   jnz  1f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "1: nr   %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_sb_findmap) : "cc" );
-                if (set < (32 - bit))
-                        return set + offset;
-                offset += 32 - bit;
-                p++;
-        }
-        /*
-         * No set bit yet, search remaining full words for a bit
-         */
-        res = find_first_bit (p, size - 32 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
 #else /* __s390x__ */
 
-/*
- * Find-bit routines..
- */
 static inline unsigned long
 find_first_zero_bit(const unsigned long * addr, unsigned long size)
 {
@@ -712,7 +682,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size)
                 "   srlg  %2,%2,6\n"
                 "0: cg    %1,0(%0,%4)\n"
                 "   jne   1f\n"
-                "   aghi  %0,8\n"
+                "   la    %0,8(%0)\n"
                 "   brct  %2,0b\n"
                 "   lgr   %0,%3\n"
                 "   j     5f\n"
@@ -785,143 +755,66 @@ find_first_bit(const unsigned long * addr, unsigned long size)
         return (res < size) ? res : size;
 }
 
-static inline unsigned long
-find_next_zero_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
-        unsigned long bitvec, reg;
-        unsigned long set, bit = offset & 63, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   lhi  %2,-1\n"
-                        "   slgr %0,%0\n"
-                        "   clr  %1,%2\n"
-                        "   jne  0f\n"
-                        "   aghi %0,32\n"
-                        "   srlg %1,%1,32\n"
-                        "0: lghi %2,0xff\n"
-                        "   tmll %1,0xffff\n"
-                        "   jno  1f\n"
-                        "   aghi %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0x00ff\n"
-                        "   jno  2f\n"
-                        "   aghi %0,8\n"
-                        "   srlg %1,%1,8\n"
-                        "2: ngr  %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   algr %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (set < (64 - bit))
-                        return set + offset;
-                offset += 64 - bit;
-                p++;
-        }
-        /*
-         * No zero yet, search remaining full words for a zero
-         */
-        res = find_first_zero_bit (p, size - 64 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
-static inline unsigned long
-find_next_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
-        unsigned long bitvec, reg;
-        unsigned long set, bit = offset & 63, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slgr %0,%0\n"
-                        "   ltr  %1,%1\n"
-                        "   jnz  0f\n"
-                        "   aghi %0,32\n"
-                        "   srlg %1,%1,32\n"
-                        "0: lghi %2,0xff\n"
-                        "   tmll %1,0xffff\n"
-                        "   jnz  1f\n"
-                        "   aghi %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0x00ff\n"
-                        "   jnz  2f\n"
-                        "   aghi %0,8\n"
-                        "   srlg %1,%1,8\n"
-                        "2: ngr  %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   algr %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_sb_findmap) : "cc" );
-                if (set < (64 - bit))
-                        return set + offset;
-                offset += 64 - bit;
-                p++;
-        }
-        /*
-         * No set bit yet, search remaining full words for a bit
-         */
-        res = find_first_bit (p, size - 64 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
 #endif /* __s390x__ */
 
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long word)
+static inline int
+find_next_zero_bit (const unsigned long * addr, unsigned long size,
+                    unsigned long offset)
 {
-        unsigned long bit = 0;
-
-#ifdef __s390x__
-        if (likely((word & 0xffffffff) == 0xffffffff)) {
-                word >>= 32;
-                bit += 32;
-        }
-#endif
-        if (likely((word & 0xffff) == 0xffff)) {
-                word >>= 16;
-                bit += 16;
+        const unsigned long *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * if no zero bit is present in the word.
+                 */
+                set = ffz(*p >> bit) + bit;
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
         }
-        if (likely((word & 0xff) == 0xff)) {
-                word >>= 8;
-                bit += 8;
-        }
-        return bit + _zb_findmap[word & 0xff];
+        return offset + find_first_zero_bit(p, size);
 }
 
-/*
- * __ffs = find first bit in word. Undefined if no bit exists,
- * so code should check against 0UL first..
- */
-static inline unsigned long __ffs (unsigned long word)
+static inline int
+find_next_bit (const unsigned long * addr, unsigned long size,
+               unsigned long offset)
 {
-        unsigned long bit = 0;
-
-#ifdef __s390x__
-        if (likely((word & 0xffffffff) == 0)) {
-                word >>= 32;
-                bit += 32;
+        const unsigned long *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * s390 version of __ffs returns __BITOPS_WORDSIZE
+                 * if no one bit is present in the word.
+                 */
+                set = __ffs(*p & (~0UL << bit));
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
         }
-#endif
-        if (likely((word & 0xffff) == 0)) {
-                word >>= 16;
-                bit += 16;
-        }
-        if (likely((word & 0xff) == 0)) {
-                word >>= 8;
-                bit += 8;
-        }
-        return bit + _sb_findmap[word & 0xff];
+        return offset + find_first_bit(p, size);
 }
 
 /*
@@ -1031,49 +924,6 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size)
         return (res < size) ? res : size;
 }
 
-static inline int 
-ext2_find_next_zero_bit(void *vaddr, unsigned int size, unsigned offset)
-{
-        unsigned long *addr = vaddr;
-        unsigned long *p = addr + (offset >> 5);
-        unsigned long word, reg;
-        unsigned int bit = offset & 31UL, res;
-
-        if (offset >= size)
-                return size;
-
-        if (bit) {
-                __asm__("   ic   %0,0(%1)\n"
-                        "   icm  %0,2,1(%1)\n"
-                        "   icm  %0,4,2(%1)\n"
-                        "   icm  %0,8,3(%1)"
-                        : "=&a" (word) : "a" (p) : "cc" );
-                word >>= bit;
-                res = bit;
-                /* Look for zero in first longword */
-                __asm__("   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                        "   jno  0f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "0: tml  %1,0x00ff\n"
-                        "   jno  1f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "1: nr   %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "+&d" (res), "+&a" (word), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (res < 32)
-                        return (p - addr)*32 + res;
-                p++;
-        }
-        /* No zero yet, search remaining full bytes for a zero */
-        res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
-        return (p - addr) * 32 + res;
-}
-
 #else /* __s390x__ */
 
 static inline unsigned long
@@ -1120,56 +970,46 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size)
         return (res < size) ? res : size;
 }
 
-static inline unsigned long
+#endif /* __s390x__ */
+
+static inline int
 ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset)
 {
-        unsigned long *addr = vaddr;
-        unsigned long *p = addr + (offset >> 6);
-        unsigned long word, reg;
-        unsigned long bit = offset & 63UL, res;
+        unsigned long *addr = vaddr, *p;
+        unsigned long word, bit, set;
 
         if (offset >= size)
                 return size;
-
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
         if (bit) {
-                __asm__("   lrvg %0,%1" /* load reversed, neat instruction */
-                        : "=a" (word) : "m" (*p) );
-                word >>= bit;
-                res = bit;
-                /* Look for zero in first 8 byte word */
-                __asm__("   lghi %2,0xff\n"
-                        "   tmll %1,0xffff\n"
-                        "   jno  2f\n"
-                        "   ahi  %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "0: tmll %1,0xffff\n"
-                        "   jno  2f\n"
-                        "   ahi  %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0xffff\n"
-                        "   jno  2f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "2: tmll %1,0x00ff\n"
-                        "   jno  3f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "3: ngr  %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "+&d" (res), "+a" (word), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (res < 64)
-                        return (p - addr)*64 + res;
-                p++;
+#ifndef __s390x__
+                asm("   ic   %0,0(%1)\n"
+                    "   icm  %0,2,1(%1)\n"
+                    "   icm  %0,4,2(%1)\n"
+                    "   icm  %0,8,3(%1)"
+                    : "=&a" (word) : "a" (p), "m" (*p) : "cc" );
+#else
+                asm("   lrvg %0,%1" : "=a" (word) : "m" (*p) );
+#endif
+                /*
+                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * if no zero bit is present in the word.
+                 */
+                set = ffz(word >> bit) + bit;
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
         }
-        /* No zero yet, search remaining full bytes for a zero */
-        res = ext2_find_first_zero_bit (p, size - 64 * (p - addr));
-        return (p - addr) * 64 + res;
+        return offset + ext2_find_first_zero_bit(p, size);
 }
 
-#endif /* __s390x__ */
-
 /* Bitmap functions for the minix filesystem.  */
 /* FIXME !!! */
 #define minix_test_and_set_bit(nr,addr) \
diff --git a/include/asm-s390/compat.h b/include/asm-s390/compat.h
index 7f8f544eb262..a007715f4aea 100644
--- a/include/asm-s390/compat.h
+++ b/include/asm-s390/compat.h
@@ -13,10 +13,10 @@ typedef s32		compat_ssize_t;
 typedef s32             compat_time_t;
 typedef s32             compat_clock_t;
 typedef s32             compat_pid_t;
-typedef u16             compat_uid_t;
-typedef u16             compat_gid_t;
-typedef u32             compat_uid32_t;
-typedef u32             compat_gid32_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u16             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u16             compat_dev_t;
@@ -51,8 +51,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
         compat_dev_t    st_rdev;
         u16             __pad2;
         u32             st_size;
@@ -140,10 +140,10 @@ static inline void __user *compat_alloc_user_space(long len)
 
 struct compat_ipc64_perm {
         compat_key_t key;
-        compat_uid32_t uid;
-        compat_gid32_t gid;
-        compat_uid32_t cuid;
-        compat_gid32_t cgid;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
         compat_mode_t mode;
         unsigned short __pad1;
         unsigned short seq;
diff --git a/include/asm-s390/cpcmd.h b/include/asm-s390/cpcmd.h
index 1d33c5da083e..1fcf65be7a23 100644
--- a/include/asm-s390/cpcmd.h
+++ b/include/asm-s390/cpcmd.h
@@ -11,14 +11,28 @@
 #define __CPCMD__
 
 /*
+ * the lowlevel function for cpcmd
  * the caller of __cpcmd has to ensure that the response buffer is below 2 GB
  */
-extern void __cpcmd(char *cmd, char *response, int rlen);
+extern int __cpcmd(const char *cmd, char *response, int rlen, int *response_code);
 
 #ifndef __s390x__
 #define cpcmd __cpcmd
 #else
-extern void cpcmd(char *cmd, char *response, int rlen);
+/*
+ * cpcmd is the in-kernel interface for issuing CP commands
+ *
+ * cmd:         null-terminated command string, max 240 characters
+ * response:    response buffer for VM's textual response
+ * rlen:        size of the response buffer, cpcmd will not exceed this size
+ *              but will cap the output, if its too large. Everything that
+ *              did not fit into the buffer will be silently dropped
+ * response_code: return pointer for VM's error code
+ * return value: the size of the response. The caller can check if the buffer
+ *              was large enough by comparing the return value and rlen
+ * NOTE: If the response buffer is not below 2 GB, cpcmd can sleep
+ */
+extern int cpcmd(const char *cmd, char *response, int rlen, int *response_code);
 #endif /*__s390x__*/
 
 #endif
diff --git a/include/asm-s390/debug.h b/include/asm-s390/debug.h
index 6bbcdea42a86..7127030ae162 100644
--- a/include/asm-s390/debug.h
+++ b/include/asm-s390/debug.h
@@ -9,6 +9,8 @@
 #ifndef DEBUG_H
 #define DEBUG_H
 
+#include <linux/config.h>
+#include <linux/fs.h>
 #include <linux/string.h>
 
 /* Note:
@@ -31,19 +33,18 @@ struct __debug_entry{
 } __attribute__((packed));
 
 
-#define __DEBUG_FEATURE_VERSION      1  /* version of debug feature */
+#define __DEBUG_FEATURE_VERSION      2  /* version of debug feature */
 
 #ifdef __KERNEL__
 #include <linux/spinlock.h>
 #include <linux/kernel.h>
 #include <linux/time.h>
-#include <linux/proc_fs.h>
 
 #define DEBUG_MAX_LEVEL            6  /* debug levels range from 0 to 6 */
 #define DEBUG_OFF_LEVEL            -1 /* level where debug is switched off */
 #define DEBUG_FLUSH_ALL            -1 /* parameter to flush all areas */
 #define DEBUG_MAX_VIEWS            10 /* max number of views in proc fs */
-#define DEBUG_MAX_PROCF_LEN        64 /* max length for a proc file name */
+#define DEBUG_MAX_NAME_LEN         64 /* max length for a debugfs file name */
 #define DEBUG_DEFAULT_LEVEL        3  /* initial debug level */
 
 #define DEBUG_DIR_ROOT "s390dbf" /* name of debug root directory in proc fs */
@@ -51,8 +52,6 @@ struct __debug_entry{
 #define DEBUG_DATA(entry) (char*)(entry + 1) /* data is stored behind */
                                              /* the entry information */
 
-#define STCK(x) asm volatile ("STCK 0(%1)" : "=m" (x) : "a" (&(x)) : "cc")
-
 typedef struct __debug_entry debug_entry_t;
 
 struct debug_view;
@@ -64,16 +63,17 @@ typedef struct debug_info {
         spinlock_t lock;                        
         int level;
         int nr_areas;
-        int page_order;
+        int pages_per_area;
         int buf_size;
         int entry_size; 
-        debug_entry_t** areas;
+        debug_entry_t*** areas;
         int active_area;
-        int *active_entry;
-        struct proc_dir_entry* proc_root_entry;
-        struct proc_dir_entry* proc_entries[DEBUG_MAX_VIEWS];
+        int *active_pages;
+        int *active_entries;
+        struct dentry* debugfs_root_entry;
+        struct dentry* debugfs_entries[DEBUG_MAX_VIEWS];
         struct debug_view* views[DEBUG_MAX_VIEWS];      
-        char name[DEBUG_MAX_PROCF_LEN];
+        char name[DEBUG_MAX_NAME_LEN];
 } debug_info_t;
 
 typedef int (debug_header_proc_t) (debug_info_t* id,
@@ -98,7 +98,7 @@ int debug_dflt_header_fn(debug_info_t* id, struct debug_view* view,
                          int area, debug_entry_t* entry, char* out_buf);                                                
                                 
 struct debug_view {
-        char name[DEBUG_MAX_PROCF_LEN];
+        char name[DEBUG_MAX_NAME_LEN];
         debug_prolog_proc_t* prolog_proc;
         debug_header_proc_t* header_proc;
         debug_format_proc_t* format_proc;
@@ -120,7 +120,7 @@ debug_entry_t* debug_exception_common(debug_info_t* id, int level,
 
 /* Debug Feature API: */
 
-debug_info_t* debug_register(char* name, int pages_index, int nr_areas,
+debug_info_t* debug_register(char* name, int pages, int nr_areas,
                              int buf_size);
 
 void debug_unregister(debug_info_t* id);
@@ -132,7 +132,8 @@ void debug_stop_all(void);
 extern inline debug_entry_t* 
 debug_event(debug_info_t* id, int level, void* data, int length)
 {
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_event_common(id,level,data,length);
 }
 
@@ -140,7 +141,8 @@ extern inline debug_entry_t*
 debug_int_event(debug_info_t* id, int level, unsigned int tag)
 {
         unsigned int t=tag;
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_event_common(id,level,&t,sizeof(unsigned int));
 }
 
@@ -148,14 +150,16 @@ extern inline debug_entry_t *
 debug_long_event (debug_info_t* id, int level, unsigned long tag)
 {
         unsigned long t=tag;
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_event_common(id,level,&t,sizeof(unsigned long));
 }
 
 extern inline debug_entry_t* 
 debug_text_event(debug_info_t* id, int level, const char* txt)
 {
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_event_common(id,level,txt,strlen(txt));
 }
 
@@ -167,7 +171,8 @@ debug_sprintf_event(debug_info_t* id,int level,char *string,...)
 extern inline debug_entry_t* 
 debug_exception(debug_info_t* id, int level, void* data, int length)
 {
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_exception_common(id,level,data,length);
 }
 
@@ -175,7 +180,8 @@ extern inline debug_entry_t*
 debug_int_exception(debug_info_t* id, int level, unsigned int tag)
 {
         unsigned int t=tag;
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_exception_common(id,level,&t,sizeof(unsigned int));
 }
 
@@ -183,14 +189,16 @@ extern inline debug_entry_t *
 debug_long_exception (debug_info_t* id, int level, unsigned long tag)
 {
         unsigned long t=tag;
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_exception_common(id,level,&t,sizeof(unsigned long));
 }
 
 extern inline debug_entry_t* 
 debug_text_exception(debug_info_t* id, int level, const char* txt)
 {
-        if ((!id) || (level > id->level)) return NULL;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
         return debug_exception_common(id,level,txt,strlen(txt));
 }
 
diff --git a/include/asm-s390/emergency-restart.h b/include/asm-s390/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-s390/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-s390/fcntl.h b/include/asm-s390/fcntl.h
index 48f692b45732..46ab12db5739 100644
--- a/include/asm-s390/fcntl.h
+++ b/include/asm-s390/fcntl.h
@@ -1,97 +1 @@
-/*
- *  include/asm-s390/fcntl.h
- *
- *  S390 version
- *
- *  Derived from "include/asm-i386/fcntl.h"
- */
-#ifndef _S390_FCNTL_H
-#define _S390_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#ifndef __s390x__
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-#endif /* ! __s390x__ */
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-#ifndef __s390x__
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-#endif
-#define F_LINUX_SPECIFIC_BASE   1024
-#endif
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-s390/futex.h b/include/asm-s390/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-s390/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-s390/kexec.h b/include/asm-s390/kexec.h
new file mode 100644
index 000000000000..54cf7d9f251c
--- /dev/null
+++ b/include/asm-s390/kexec.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-s390/kexec.h
+ *
+ * (C) Copyright IBM Corp. 2005
+ *
+ * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
+ *
+ */
+
+#ifndef _S390_KEXEC_H
+#define _S390_KEXEC_H
+
+#include <asm/page.h>
+#include <asm/processor.h>
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can use for the control pages */
+/* Not more than 2GB */
+#define KEXEC_CONTROL_MEMORY_LIMIT (1<<31)
+
+/* Allocate one page for the pdp and the second for the code */
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_S390
+
+#define MAX_NOTE_BYTES 1024
+typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
+
+extern note_buf_t crash_notes[];
+
+#endif /*_S390_KEXEC_H */
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
index df5172fc589d..c6f51c9ce3ff 100644
--- a/include/asm-s390/lowcore.h
+++ b/include/asm-s390/lowcore.h
@@ -68,6 +68,7 @@
 #define __LC_SYSTEM_TIMER               0x270
 #define __LC_LAST_UPDATE_CLOCK          0x278
 #define __LC_STEAL_CLOCK                0x280
+#define __LC_RETURN_MCCK_PSW            0x288
 #define __LC_KERNEL_STACK               0xC40
 #define __LC_THREAD_INFO                0xC44
 #define __LC_ASYNC_STACK                0xC48
@@ -90,7 +91,7 @@
 #define __LC_SYSTEM_TIMER               0x278
 #define __LC_LAST_UPDATE_CLOCK          0x280
 #define __LC_STEAL_CLOCK                0x288
-#define __LC_DIAG44_OPCODE              0x290
+#define __LC_RETURN_MCCK_PSW            0x290
 #define __LC_KERNEL_STACK               0xD40
 #define __LC_THREAD_INFO                0xD48
 #define __LC_ASYNC_STACK                0xD50
@@ -109,10 +110,14 @@
 
 #ifndef __s390x__
 #define __LC_PFAULT_INTPARM             0x080
+#define __LC_CPU_TIMER_SAVE_AREA        0x0D8
 #define __LC_AREGS_SAVE_AREA            0x120
+#define __LC_GPREGS_SAVE_AREA           0x180
 #define __LC_CREGS_SAVE_AREA            0x1C0
 #else /* __s390x__ */
 #define __LC_PFAULT_INTPARM             0x11B8
+#define __LC_GPREGS_SAVE_AREA           0x1280
+#define __LC_CPU_TIMER_SAVE_AREA        0x1328
 #define __LC_AREGS_SAVE_AREA            0x1340
 #define __LC_CREGS_SAVE_AREA            0x1380
 #endif /* __s390x__ */
@@ -167,7 +172,8 @@ struct _lowcore
         __u16        subchannel_nr;            /* 0x0ba */
         __u32        io_int_parm;              /* 0x0bc */
         __u32        io_int_word;              /* 0x0c0 */
-        __u8         pad3[0xD8-0xC4];          /* 0x0c4 */
+        __u8         pad3[0xD4-0xC4];          /* 0x0c4 */
+        __u32        extended_save_area_addr;  /* 0x0d4 */
         __u32        cpu_timer_save_area[2];   /* 0x0d8 */
         __u32        clock_comp_save_area[2];  /* 0x0e0 */
         __u32        mcck_interruption_code[2]; /* 0x0e8 */
@@ -192,7 +198,8 @@ struct _lowcore
         __u64        system_timer;             /* 0x270 */
         __u64        last_update_clock;        /* 0x278 */
         __u64        steal_clock;              /* 0x280 */
-        __u8         pad8[0xc00-0x288];        /* 0x288 */
+        psw_t        return_mcck_psw;          /* 0x288 */
+        __u8         pad8[0xc00-0x290];        /* 0x290 */
 
         /* System info area */
         __u32        save_area[16];            /* 0xc00 */
@@ -281,8 +288,8 @@ struct _lowcore
         __u64        system_timer;             /* 0x278 */
         __u64        last_update_clock;        /* 0x280 */
         __u64        steal_clock;              /* 0x288 */
-        __u32        diag44_opcode;            /* 0x290 */
-        __u8         pad8[0xc00-0x294];        /* 0x294 */
+        psw_t        return_mcck_psw;          /* 0x290 */
+        __u8         pad8[0xc00-0x2a0];        /* 0x2a0 */
         /* System info area */
         __u64        save_area[16];            /* 0xc00 */
         __u8         pad9[0xd40-0xc80];        /* 0xc80 */
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
index 2be287b9df88..2430c561e021 100644
--- a/include/asm-s390/page.h
+++ b/include/asm-s390/page.h
@@ -111,20 +111,6 @@ static inline void copy_page(void *to, void *from)
 #define alloc_zeroed_user_highpage(vma, vaddr) alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO, vma, vaddr)
 #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 /*
  * These are used to make use of C type-checking..
  */
@@ -207,4 +193,6 @@ page_get_storage_key(unsigned long addr)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _S390_PAGE_H */
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index fb46e9090b50..4ec652ebb3b1 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -203,10 +203,25 @@ unsigned long get_wchan(struct task_struct *p);
 # define cpu_relax()    asm volatile ("diag 0,0,68" : : : "memory")
 #else /* __s390x__ */
 # define cpu_relax() \
-        asm volatile ("ex 0,%0" : : "i" (__LC_DIAG44_OPCODE) : "memory")
+        do { \
+                if (MACHINE_HAS_DIAG44) \
+                        asm volatile ("diag 0,0,68" : : : "memory"); \
+        } while (0)
 #endif /* __s390x__ */
 
 /*
+ * Set PSW to specified value.
+ */
+static inline void __load_psw(psw_t psw)
+{
+#ifndef __s390x__
+        asm volatile ("lpsw  0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
+#else
+        asm volatile ("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
+#endif
+}
+
+/*
  * Set PSW mask to specified value, while leaving the
  * PSW addr pointing to the next instruction.
  */
@@ -214,8 +229,8 @@ unsigned long get_wchan(struct task_struct *p);
 static inline void __load_psw_mask (unsigned long mask)
 {
         unsigned long addr;
-
         psw_t psw;
+
         psw.mask = mask;
 
 #ifndef __s390x__
@@ -241,30 +256,8 @@ static inline void __load_psw_mask (unsigned long mask)
  */
 static inline void enabled_wait(void)
 {
-        unsigned long reg;
-        psw_t wait_psw;
-
-        wait_psw.mask = PSW_BASE_BITS | PSW_MASK_IO | PSW_MASK_EXT |
-                PSW_MASK_MCHECK | PSW_MASK_WAIT | PSW_DEFAULT_KEY;
-#ifndef __s390x__
-        asm volatile (
-                "    basr %0,0\n"
-                "0:  la   %0,1f-0b(%0)\n"
-                "    st   %0,4(%1)\n"
-                "    oi   4(%1),0x80\n"
-                "    lpsw 0(%1)\n"
-                "1:"
-                : "=&a" (reg) : "a" (&wait_psw), "m" (wait_psw)
-                : "memory", "cc" );
-#else /* __s390x__ */
-        asm volatile (
-                "    larl  %0,0f\n"
-                "    stg   %0,8(%1)\n"
-                "    lpswe 0(%1)\n"
-                "0:"
-                : "=&a" (reg) : "a" (&wait_psw), "m" (wait_psw)
-                : "memory", "cc" );
-#endif /* __s390x__ */
+        __load_psw_mask(PSW_BASE_BITS | PSW_MASK_IO | PSW_MASK_EXT |
+                        PSW_MASK_MCHECK | PSW_MASK_WAIT | PSW_DEFAULT_KEY);
 }
 
 /*
@@ -273,13 +266,11 @@ static inline void enabled_wait(void)
 
 static inline void disabled_wait(unsigned long code)
 {
-        char psw_buffer[2*sizeof(psw_t)];
         unsigned long ctl_buf;
-        psw_t *dw_psw = (psw_t *)(((unsigned long) &psw_buffer+sizeof(psw_t)-1)
-                                  & -sizeof(psw_t));
+        psw_t dw_psw;
 
-        dw_psw->mask = PSW_BASE_BITS | PSW_MASK_WAIT;
-        dw_psw->addr = code;
+        dw_psw.mask = PSW_BASE_BITS | PSW_MASK_WAIT;
+        dw_psw.addr = code;
         /* 
          * Store status and then load disabled wait psw,
          * the processor is dead afterwards
@@ -301,7 +292,7 @@ static inline void disabled_wait(unsigned long code)
                       "    oi    0x1c0,0x10\n" /* fake protection bit */
                       "    lpsw 0(%1)"
                       : "=m" (ctl_buf)
-                      : "a" (dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc" );
+                      : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc" );
 #else /* __s390x__ */
         asm volatile ("    stctg 0,0,0(%2)\n"
                       "    ni    4(%2),0xef\n" /* switch off protection */
@@ -333,7 +324,7 @@ static inline void disabled_wait(unsigned long code)
                       "    oi    0x384(1),0x10\n" /* fake protection bit */
                       "    lpswe 0(%1)"
                       : "=m" (ctl_buf)
-                      : "a" (dw_psw), "a" (&ctl_buf),
+                      : "a" (&dw_psw), "a" (&ctl_buf),
                         "m" (dw_psw) : "cc", "0", "1");
 #endif /* __s390x__ */
 }
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index 4eff8f2e3bf1..fc7c96edc697 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -276,7 +276,7 @@ typedef struct
 #endif /* __s390x__ */
 
 #define PSW_KERNEL_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_PRIMARY | \
-                         PSW_DEFAULT_KEY)
+                         PSW_MASK_MCHECK | PSW_DEFAULT_KEY)
 #define PSW_USER_BITS   (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_HOME | \
                          PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK | \
                          PSW_MASK_PSTATE | PSW_DEFAULT_KEY)
diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h
index 9473786387a3..dd50e57a928f 100644
--- a/include/asm-s390/smp.h
+++ b/include/asm-s390/smp.h
@@ -47,7 +47,7 @@ extern int smp_call_function_on(void (*func) (void *info), void *info,
  
 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
 
-#define smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
+#define raw_smp_processor_id()  (S390_lowcore.cpu_data.cpu_nr)
 
 extern int smp_get_cpu(cpumask_t cpu_map);
 extern void smp_put_cpu(int cpu);
diff --git a/include/asm-s390/socket.h b/include/asm-s390/socket.h
index 0e96eeca4e6b..15a5298c8744 100644
--- a/include/asm-s390/socket.h
+++ b/include/asm-s390/socket.h
@@ -22,6 +22,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
index 53cc736b9820..321b23bba1ec 100644
--- a/include/asm-s390/spinlock.h
+++ b/include/asm-s390/spinlock.h
@@ -11,21 +11,16 @@
 #ifndef __ASM_SPINLOCK_H
 #define __ASM_SPINLOCK_H
 
-#ifdef __s390x__
-/*
- * Grmph, take care of %&#! user space programs that include
- * asm/spinlock.h. The diagnose is only available in kernel
- * context.
- */
-#ifdef __KERNEL__
-#include <asm/lowcore.h>
-#define __DIAG44_INSN "ex"
-#define __DIAG44_OPERAND __LC_DIAG44_OPCODE
-#else
-#define __DIAG44_INSN "#"
-#define __DIAG44_OPERAND 0
-#endif
-#endif /* __s390x__ */
+static inline int
+_raw_compare_and_swap(volatile unsigned int *lock,
+                      unsigned int old, unsigned int new)
+{
+        asm volatile ("cs %0,%3,0(%4)"
+                      : "=d" (old), "=m" (*lock)
+                      : "0" (old), "d" (new), "a" (lock), "m" (*lock)
+                      : "cc", "memory" );
+        return old;
+}
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -41,58 +36,35 @@ typedef struct {
 #endif
 } __attribute__ ((aligned (4))) spinlock_t;
 
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
-#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
+#define SPIN_LOCK_UNLOCKED      (spinlock_t) { 0 }
+#define spin_lock_init(lp)      do { (lp)->lock = 0; } while(0)
 #define spin_unlock_wait(lp)    do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
-#define spin_is_locked(x) ((x)->lock != 0)
+#define spin_is_locked(x)       ((x)->lock != 0)
 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
 
-extern inline void _raw_spin_lock(spinlock_t *lp)
+extern void _raw_spin_lock_wait(spinlock_t *lp, unsigned int pc);
+extern int _raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc);
+
+static inline void _raw_spin_lock(spinlock_t *lp)
 {
-#ifndef __s390x__
-        unsigned int reg1, reg2;
-        __asm__ __volatile__("    bras  %0,1f\n"
-                           "0:  diag  0,0,68\n"
-                           "1:  slr   %1,%1\n"
-                           "    cs    %1,%0,0(%3)\n"
-                           "    jl    0b\n"
-                           : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
-                           : "a" (&lp->lock), "m" (lp->lock)
-                           : "cc", "memory" );
-#else /* __s390x__ */
-        unsigned long reg1, reg2;
-        __asm__ __volatile__("    bras  %1,1f\n"
-                           "0:  " __DIAG44_INSN " 0,%4\n"
-                           "1:  slr   %0,%0\n"
-                           "    cs    %0,%1,0(%3)\n"
-                           "    jl    0b\n"
-                           : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
-                           : "a" (&lp->lock), "i" (__DIAG44_OPERAND),
-                             "m" (lp->lock) : "cc", "memory" );
-#endif /* __s390x__ */
+        unsigned long pc = 1 | (unsigned long) __builtin_return_address(0);
+
+        if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0))
+                _raw_spin_lock_wait(lp, pc);
 }
 
-extern inline int _raw_spin_trylock(spinlock_t *lp)
+static inline int _raw_spin_trylock(spinlock_t *lp)
 {
-        unsigned long reg;
-        unsigned int result;
-
-        __asm__ __volatile__("    basr  %1,0\n"
-                           "0:  cs    %0,%1,0(%3)"
-                           : "=d" (result), "=&d" (reg), "=m" (lp->lock)
-                           : "a" (&lp->lock), "m" (lp->lock), "0" (0)
-                           : "cc", "memory" );
-        return !result;
+        unsigned long pc = 1 | (unsigned long) __builtin_return_address(0);
+
+        if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0))
+                return 1;
+        return _raw_spin_trylock_retry(lp, pc);
 }
 
-extern inline void _raw_spin_unlock(spinlock_t *lp)
+static inline void _raw_spin_unlock(spinlock_t *lp)
 {
-        unsigned int old;
-
-        __asm__ __volatile__("cs %0,%3,0(%4)"
-                           : "=d" (old), "=m" (lp->lock)
-                           : "0" (lp->lock), "d" (0), "a" (lp)
-                           : "cc", "memory" );
+        _raw_compare_and_swap(&lp->lock, lp->lock, 0);
 }
                 
 /*
@@ -106,7 +78,7 @@ extern inline void _raw_spin_unlock(spinlock_t *lp)
  * read-locks.
  */
 typedef struct {
-        volatile unsigned long lock;
+        volatile unsigned int lock;
         volatile unsigned long owner_pc;
 #ifdef CONFIG_PREEMPT
         unsigned int break_lock;
@@ -129,123 +101,55 @@ typedef struct {
  */
 #define write_can_lock(x) ((x)->lock == 0)
 
-#ifndef __s390x__
-#define _raw_read_lock(rw)   \
-        asm volatile("   l     2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: la    2,0(2)\n"     /* clear high (=write) bit */ \
-                     "   la    3,1(2)\n"     /* one more reader */ \
-                     "   cs    2,3,0(%1)\n"  /* try to write new value */ \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_read_lock(rw)   \
-        asm volatile("   lg    2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: " __DIAG44_INSN " 0,%2\n" \
-                     "1: nihh  2,0x7fff\n" /* clear high (=write) bit */ \
-                     "   la    3,1(2)\n"   /* one more reader */  \
-                     "   csg   2,3,0(%1)\n" /* try to write new value */ \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) \
-                     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_read_unlock(rw) \
-        asm volatile("   l     2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: lr    3,2\n"    \
-                     "   ahi   3,-1\n"    /* one less reader */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_read_unlock(rw) \
-        asm volatile("   lg    2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: " __DIAG44_INSN " 0,%2\n" \
-                     "1: lgr   3,2\n"    \
-                     "   bctgr 3,0\n"    /* one less reader */ \
-                     "   csg   2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) \
-                     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_write_lock(rw) \
-        asm volatile("   lhi   3,1\n"    \
-                     "   sll   3,31\n"    /* new lock value = 0x80000000 */ \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: slr   2,2\n"     /* old lock value must be 0 */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_write_lock(rw) \
-        asm volatile("   llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
-                     "   j     1f\n"       \
-                     "0: " __DIAG44_INSN " 0,%2\n"   \
-                     "1: slgr  2,2\n"      /* old lock value must be 0 */ \
-                     "   csg   2,3,0(%1)\n" \
-                     "   jl    0b"         \
-                     : "=m" ((rw)->lock) \
-                     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_write_unlock(rw) \
-        asm volatile("   slr   3,3\n"     /* new lock value = 0 */ \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: lhi   2,1\n"    \
-                     "   sll   2,31\n"    /* old lock value must be 0x80000000 */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_write_unlock(rw) \
-        asm volatile("   slgr  3,3\n"      /* new lock value = 0 */ \
-                     "   j     1f\n"       \
-                     "0: " __DIAG44_INSN " 0,%2\n"   \
-                     "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
-                     "   csg   2,3,0(%1)\n"   \
-                     "   jl    0b"         \
-                     : "=m" ((rw)->lock) \
-                     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-                       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
-
-extern inline int _raw_write_trylock(rwlock_t *rw)
+extern void _raw_read_lock_wait(rwlock_t *lp);
+extern int _raw_read_trylock_retry(rwlock_t *lp);
+extern void _raw_write_lock_wait(rwlock_t *lp);
+extern int _raw_write_trylock_retry(rwlock_t *lp);
+
+static inline void _raw_read_lock(rwlock_t *rw)
+{
+        unsigned int old;
+        old = rw->lock & 0x7fffffffU;
+        if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old)
+                _raw_read_lock_wait(rw);
+}
+
+static inline void _raw_read_unlock(rwlock_t *rw)
+{
+        unsigned int old, cmp;
+
+        old = rw->lock;
+        do {
+                cmp = old;
+                old = _raw_compare_and_swap(&rw->lock, old, old - 1);
+        } while (cmp != old);
+}
+
+static inline void _raw_write_lock(rwlock_t *rw)
+{
+        if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
+                _raw_write_lock_wait(rw);
+}
+
+static inline void _raw_write_unlock(rwlock_t *rw)
+{
+        _raw_compare_and_swap(&rw->lock, 0x80000000, 0);
+}
+
+static inline int _raw_read_trylock(rwlock_t *rw)
+{
+        unsigned int old;
+        old = rw->lock & 0x7fffffffU;
+        if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old))
+                return 1;
+        return _raw_read_trylock_retry(rw);
+}
+
+static inline int _raw_write_trylock(rwlock_t *rw)
 {
-        unsigned long result, reg;
-        
-        __asm__ __volatile__(
-#ifndef __s390x__
-                             "   lhi  %1,1\n"
-                             "   sll  %1,31\n"
-                             "   cs   %0,%1,0(%3)"
-#else /* __s390x__ */
-                             "   llihh %1,0x8000\n"
-                             "0: csg %0,%1,0(%3)\n"
-#endif /* __s390x__ */
-                             : "=d" (result), "=&d" (reg), "=m" (rw->lock)
-                             : "a" (&rw->lock), "m" (rw->lock), "0" (0UL)
-                             : "cc", "memory" );
-        return result == 0;
+        if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
+                return 1;
+        return _raw_write_trylock_retry(rw);
 }
 
 #endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index 81514d76edcf..864cae7e1fd6 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -16,6 +16,7 @@
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/setup.h>
+#include <asm/processor.h>
 
 #ifdef __KERNEL__
 
@@ -103,29 +104,16 @@ static inline void restore_access_regs(unsigned int *acrs)
         prev = __switch_to(prev,next);                                       \
 } while (0)
 
-#define prepare_arch_switch(rq, next)   do { } while(0)
-#define task_running(rq, p)             ((rq)->curr == (p))
-
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 extern void account_user_vtime(struct task_struct *);
 extern void account_system_vtime(struct task_struct *);
+#endif
 
-#define finish_arch_switch(rq, prev) do {                                    \
+#define finish_arch_switch(prev) do {                                        \
         set_fs(current->thread.mm_segment);                                  \
-        spin_unlock(&(rq)->lock);                                            \
         account_system_vtime(prev);                                          \
-        local_irq_enable();                                                  \
 } while (0)
 
-#else
-
-#define finish_arch_switch(rq, prev) do {                                    \
-        set_fs(current->thread.mm_segment);                                  \
-        spin_unlock_irq(&(rq)->lock);                                        \
-} while (0)
-
-#endif
-
 #define nop() __asm__ __volatile__ ("nop")
 
 #define xchg(ptr,x) \
@@ -331,9 +319,6 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 
 #ifdef __s390x__
 
-#define __load_psw(psw) \
-        __asm__ __volatile__("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
-
 #define __ctl_load(array, low, high) ({ \
         typedef struct { char _[sizeof(array)]; } addrtype; \
         __asm__ __volatile__ ( \
@@ -390,9 +375,6 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 
 #else /* __s390x__ */
 
-#define __load_psw(psw) \
-        __asm__ __volatile__("lpsw 0(%0)" : : "a" (&psw) : "cc" );
-
 #define __ctl_load(array, low, high) ({ \
         typedef struct { char _[sizeof(array)]; } addrtype; \
         __asm__ __volatile__ ( \
@@ -451,6 +433,20 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 /* For spinlocks etc */
 #define local_irq_save(x)       ((x) = local_irq_disable())
 
+/*
+ * Use to set psw mask except for the first byte which
+ * won't be changed by this function.
+ */
+static inline void
+__set_psw_mask(unsigned long mask)
+{
+        local_save_flags(mask);
+        __load_psw_mask(mask);
+}
+
+#define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
+#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
+
 #ifdef CONFIG_SMP
 
 extern void smp_ctl_set_bit(int cr, int bit);
diff --git a/include/asm-s390/thread_info.h b/include/asm-s390/thread_info.h
index aade85c53a63..6c18a3f24316 100644
--- a/include/asm-s390/thread_info.h
+++ b/include/asm-s390/thread_info.h
@@ -50,7 +50,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         unsigned int            cpu;            /* current CPU */
-        unsigned int            preempt_count; /* 0 => preemptable */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         struct restart_block    restart_block;
 };
 
@@ -96,6 +96,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTART_SVC         4       /* restart svc with new svc number */
 #define TIF_SYSCALL_AUDIT       5       /* syscall auditing active */
 #define TIF_SINGLE_STEP         6       /* deliver sigtrap on return to user */
+#define TIF_MCCK_PENDING        7       /* machine check handling is pending */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling 
                                            TIF_NEED_RESCHED */
@@ -109,6 +110,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_RESTART_SVC        (1<<TIF_RESTART_SVC)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SINGLE_STEP        (1<<TIF_SINGLE_STEP)
+#define _TIF_MCCK_PENDING       (1<<TIF_MCCK_PENDING)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_31BIT              (1<<TIF_31BIT)
diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h
index 3fefd61416a5..d0be3e477013 100644
--- a/include/asm-s390/types.h
+++ b/include/asm-s390/types.h
@@ -79,8 +79,6 @@ typedef unsigned  long u64;
 
 typedef u32 dma_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #ifndef __s390x__
 typedef union {
         unsigned long long pair;
diff --git a/include/asm-s390/uaccess.h b/include/asm-s390/uaccess.h
index a7f43a251f81..38a5cf8ab9e3 100644
--- a/include/asm-s390/uaccess.h
+++ b/include/asm-s390/uaccess.h
@@ -65,13 +65,6 @@
 
 #define access_ok(type,addr,size) __access_ok(addr,size)
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user *addr,
-                                                unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
@@ -149,11 +142,11 @@ struct exception_table_entry
 })
 #endif
 
-#ifndef __CHECKER__
 #define __put_user(x, ptr) \
 ({                                                              \
         __typeof__(*(ptr)) __x = (x);                           \
         int __pu_err;                                           \
+        __chk_user_ptr(ptr);                                    \
         switch (sizeof (*(ptr))) {                              \
         case 1:                                                 \
         case 2:                                                 \
@@ -167,14 +160,6 @@ struct exception_table_entry
          }                                                      \
         __pu_err;                                               \
 })
-#else
-#define __put_user(x, ptr)                      \
-({                                              \
-        void __user *p;                         \
-        p = (ptr);                              \
-        0;                                      \
-})
-#endif
 
 #define put_user(x, ptr)                                        \
 ({                                                              \
@@ -213,11 +198,11 @@ extern int __put_user_bad(void) __attribute__((noreturn));
 })
 #endif
 
-#ifndef __CHECKER__
 #define __get_user(x, ptr)                                      \
 ({                                                              \
         __typeof__(*(ptr)) __x;                                 \
         int __gu_err;                                           \
+        __chk_user_ptr(ptr);                                    \
         switch (sizeof(*(ptr))) {                               \
         case 1:                                                 \
         case 2:                                                 \
@@ -232,15 +217,6 @@ extern int __put_user_bad(void) __attribute__((noreturn));
         (x) = __x;                                              \
         __gu_err;                                               \
 })
-#else
-#define __get_user(x, ptr)                      \
-({                                              \
-        void __user *p;                         \
-        p = (ptr);                              \
-        0;                                      \
-})
-#endif
-
 
 #define get_user(x, ptr)                                        \
 ({                                                              \
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index f1a204f7c0f0..221e965da924 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -269,13 +269,18 @@
 #define __NR_mq_timedreceive    274
 #define __NR_mq_notify          275
 #define __NR_mq_getsetattr      276
-/* Number 277 is reserved for new sys_kexec_load */
+#define __NR_kexec_load         277
 #define __NR_add_key            278
 #define __NR_request_key        279
 #define __NR_keyctl             280
 #define __NR_waitid             281
+#define __NR_ioprio_set         282
+#define __NR_ioprio_get         283
+#define __NR_inotify_init       284
+#define __NR_inotify_add_watch  285
+#define __NR_inotify_rm_watch   286
 
-#define NR_syscalls 282
+#define NR_syscalls 287
 
 /* 
  * There are some system calls that are not present on 64 bit, some
diff --git a/include/asm-sh/auxvec.h b/include/asm-sh/auxvec.h
new file mode 100644
index 000000000000..fc21e4db5881
--- /dev/null
+++ b/include/asm-sh/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_SH_AUXVEC_H
+#define __ASM_SH_AUXVEC_H
+
+#endif /* __ASM_SH_AUXVEC_H */
diff --git a/include/asm-sh/bigsur/serial.h b/include/asm-sh/bigsur/serial.h
index 540f12205923..7233af42f755 100644
--- a/include/asm-sh/bigsur/serial.h
+++ b/include/asm-sh/bigsur/serial.h
@@ -14,13 +14,10 @@
 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
 
 
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                   \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ 
 
-
-#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
-
 /* XXX: This should be moved ino irq.h */
 #define irq_cannonicalize(x) (x)
 
diff --git a/include/asm-sh/ec3104/serial.h b/include/asm-sh/ec3104/serial.h
index f8eb16312ed9..cfe4d78ec1ee 100644
--- a/include/asm-sh/ec3104/serial.h
+++ b/include/asm-sh/ec3104/serial.h
@@ -10,13 +10,11 @@
  * it's got the keyboard controller behind it so we can't really use it
  * (without moving the keyboard driver to userspace, which doesn't sound
  * like a very good idea) */
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
         { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
         { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
 
-#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
-
 /* XXX: This should be moved ino irq.h */
 #define irq_cannonicalize(x) (x)
diff --git a/include/asm-sh/emergency-restart.h b/include/asm-sh/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-sh/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sh/fcntl.h b/include/asm-sh/fcntl.h
index 0b3ae524e34c..46ab12db5739 100644
--- a/include/asm-sh/fcntl.h
+++ b/include/asm-sh/fcntl.h
@@ -1,88 +1 @@
-#ifndef __ASM_SH_FCNTL_H
-#define __ASM_SH_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-#endif /* __ASM_SH_FCNTL_H */
-
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-sh/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-sh/hdreg.h b/include/asm-sh/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-sh/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 4c6d129e7d91..324e6cc5ecf7 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -31,6 +31,7 @@
 #define HPAGE_SIZE              (1UL << HPAGE_SHIFT)
 #define HPAGE_MASK              (~(HPAGE_SIZE-1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT-PAGE_SHIFT)
+#define ARCH_HAS_SETCLEAR_HUGE_PTE
 #endif
 
 #ifdef __KERNEL__
@@ -121,24 +122,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
-#ifndef __ASSEMBLY__
-
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
-#endif
-
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
index 9c3b63d0105e..0a523c85b11c 100644
--- a/include/asm-sh/pci.h
+++ b/include/asm-sh/pci.h
@@ -36,7 +36,7 @@ struct pci_dev;
 
 extern void pcibios_set_master(struct pci_dev *dev);
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -96,6 +96,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
 #define sg_dma_address(sg)      (virt_to_bus((sg)->dma_address))
 #define sg_dma_len(sg)          ((sg)->length)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 /* Board-specific fixup routines. */
 extern void pcibios_fixup(void);
 extern void pcibios_fixup_irqs(void);
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index cd847a47a9aa..ecb909572d3f 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -196,6 +196,7 @@ static inline pte_t pte_mkexec(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _
 static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
 static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
 static inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
+static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
 
 /*
  * Macro and implementation to make a page protection as uncachable.
diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h
index 5474dbdbaa86..f51e232d5cd9 100644
--- a/include/asm-sh/serial.h
+++ b/include/asm-sh/serial.h
@@ -29,20 +29,18 @@
 #ifdef CONFIG_HD64465
 #include <asm/hd64465.h>
 
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                   \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS }  /* ttyS0 */
 
 #else
 
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }       /* ttyS1 */
 
 #endif
 
-#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
-
 #endif
 #endif /* _ASM_SERIAL_H */
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index 38b54469d7d1..f19a8b3b69a6 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -25,7 +25,7 @@ extern cpumask_t cpu_possible_map;
 
 #define cpu_online(cpu)         cpu_isset(cpu, cpu_online_map)
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 /* I've no idea what the real meaning of this is */
 #define PROC_CHANGE_PENALTY     20
diff --git a/include/asm-sh/socket.h b/include/asm-sh/socket.h
index dde696c3b4c7..553904ff9336 100644
--- a/include/asm-sh/socket.h
+++ b/include/asm-sh/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_RCVBUFFORCE  32
+#define SO_SNDBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
index 4bbbd9f3c37e..46080cefaff8 100644
--- a/include/asm-sh/thread_info.h
+++ b/include/asm-sh/thread_info.h
@@ -20,7 +20,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         __u32                   flags;          /* low level flags */
         __u32                   cpu;
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count; /* 0 => preemptable, <0 => BUG */
         struct restart_block    restart_block;
         __u8                    supervisor_stack[0];
 };
diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h
index c4dc126c5621..cb7e183a0a6b 100644
--- a/include/asm-sh/types.h
+++ b/include/asm-sh/types.h
@@ -58,8 +58,6 @@ typedef u64 sector_t;
 #define HAVE_SECTOR_T
 #endif
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
index fb9e334afa2b..2cb01861e7c5 100644
--- a/include/asm-sh/uaccess.h
+++ b/include/asm-sh/uaccess.h
@@ -146,12 +146,6 @@ static inline int access_ok(int type, const void __user *p, unsigned long size)
         return __access_ok(addr, size);
 }
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
 /*
  * Uh, these should become the main single-value transfer routines ...
  * They automatically use the right size if we just have the right
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index 245447081f0d..ea89e8f223ea 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -295,8 +295,14 @@
 #define __NR_add_key            285
 #define __NR_request_key        286
 #define __NR_keyctl             287
+#define __NR_ioprio_set         288
+#define __NR_ioprio_get         289
+#define __NR_inotify_init       290
+#define __NR_inotify_add_watch  291
+#define __NR_inotify_rm_watch   292
 
-#define NR_syscalls 288
+
+#define NR_syscalls 293
 
 /* user-visible error numbers are in the range -1 - -124: see <asm-sh/errno.h> */
 
@@ -406,7 +412,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \
 register long __sc7 __asm__ ("r7") = (long) arg4; \
 register long __sc0 __asm__ ("r0") = (long) arg5; \
 register long __sc1 __asm__ ("r1") = (long) arg6; \
-__asm__ __volatile__ ("trapa    #0x15" \
+__asm__ __volatile__ ("trapa    #0x16" \
         : "=z" (__sc0) \
         : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
           "r" (__sc3), "r" (__sc1) \
diff --git a/include/asm-sh64/auxvec.h b/include/asm-sh64/auxvec.h
new file mode 100644
index 000000000000..1ad5a44bdc76
--- /dev/null
+++ b/include/asm-sh64/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_SH64_AUXVEC_H
+#define __ASM_SH64_AUXVEC_H
+
+#endif /* __ASM_SH64_AUXVEC_H */
diff --git a/include/asm-sh64/emergency-restart.h b/include/asm-sh64/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-sh64/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sh64/fcntl.h b/include/asm-sh64/fcntl.h
index ffcc36c64fa5..744dd79b9d5d 100644
--- a/include/asm-sh64/fcntl.h
+++ b/include/asm-sh64/fcntl.h
@@ -1,7 +1 @@
-#ifndef __ASM_SH64_FCNTL_H
-#define __ASM_SH64_FCNTL_H
-
 #include <asm-sh/fcntl.h>
-
-#endif /* __ASM_SH64_FCNTL_H */
-
diff --git a/include/asm-sh64/futex.h b/include/asm-sh64/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-sh64/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-sh64/hdreg.h b/include/asm-sh64/hdreg.h
deleted file mode 100644
index 52d983635a27..000000000000
--- a/include/asm-sh64/hdreg.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_SH64_HDREG_H
-#define __ASM_SH64_HDREG_H
-
-#include <asm-generic/hdreg.h>
-
-#endif /* __ASM_SH64_HDREG_H */
diff --git a/include/asm-sh64/page.h b/include/asm-sh64/page.h
index e1f7f5a41210..c86df90f7cbd 100644
--- a/include/asm-sh64/page.h
+++ b/include/asm-sh64/page.h
@@ -41,6 +41,7 @@
 #define HPAGE_SIZE              (1UL << HPAGE_SHIFT)
 #define HPAGE_MASK              (~(HPAGE_SIZE-1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT-PAGE_SHIFT)
+#define ARCH_HAS_SETCLEAR_HUGE_PTE
 #endif
 
 #ifdef __KERNEL__
@@ -114,24 +115,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
-#ifndef __ASSEMBLY__
-
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
-#endif
-
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* __ASM_SH64_PAGE_H */
diff --git a/include/asm-sh64/pci.h b/include/asm-sh64/pci.h
index 8cc14e139750..aa8043089bb6 100644
--- a/include/asm-sh64/pci.h
+++ b/include/asm-sh64/pci.h
@@ -26,7 +26,7 @@ extern void pcibios_set_master(struct pci_dev *dev);
 /*
  * Set penalize isa irq function
  */
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -86,6 +86,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
 #define sg_dma_address(sg)      ((sg)->dma_address)
 #define sg_dma_len(sg)          ((sg)->length)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 /* Board-specific fixup routines. */
 extern void pcibios_fixup(void);
 extern void pcibios_fixup_irqs(void);
diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h
index 525e1523ef5f..78ac6be2d9ef 100644
--- a/include/asm-sh64/pgtable.h
+++ b/include/asm-sh64/pgtable.h
@@ -430,6 +430,8 @@ extern inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) |
 extern inline pte_t pte_mkexec(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_EXECUTE)); return pte; }
 extern inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
 extern inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
+extern inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
+
 
 /*
  * Conversion functions: convert a page and protection to a page entry.
diff --git a/include/asm-sh64/serial.h b/include/asm-sh64/serial.h
index 8e39b4e90c76..29c9be15112b 100644
--- a/include/asm-sh64/serial.h
+++ b/include/asm-sh64/serial.h
@@ -20,13 +20,11 @@
 
 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
 
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }       /* ttyS1 */
 
-#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
-
 /* XXX: This should be moved ino irq.h */
 #define irq_cannonicalize(x) (x)
 
diff --git a/include/asm-sh64/thread_info.h b/include/asm-sh64/thread_info.h
index 8a32d6bd0b79..10f024c6a2e3 100644
--- a/include/asm-sh64/thread_info.h
+++ b/include/asm-sh64/thread_info.h
@@ -22,7 +22,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         /* Put the 4 32-bit fields together to make asm offsetting easier. */
-        __s32                   preempt_count; /* 0 => preemptable, <0 => BUG */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         __u16                   cpu;
 
         mm_segment_t            addr_limit;
diff --git a/include/asm-sh64/types.h b/include/asm-sh64/types.h
index 41d4d2f82aa9..8d41db2153b5 100644
--- a/include/asm-sh64/types.h
+++ b/include/asm-sh64/types.h
@@ -65,8 +65,6 @@ typedef u32 dma_addr_t;
 #endif
 typedef u64 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #define BITS_PER_LONG 32
diff --git a/include/asm-sh64/uaccess.h b/include/asm-sh64/uaccess.h
index a33654d576a1..56aa3cf0f273 100644
--- a/include/asm-sh64/uaccess.h
+++ b/include/asm-sh64/uaccess.h
@@ -60,12 +60,6 @@
 #define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
 #define __access_ok(addr,size) (__range_ok(addr,size) == 0)
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
 /*
  * Uh, these should become the main single-value transfer routines ...
  * They automatically use the right size if we just have the right
diff --git a/include/asm-sh64/unistd.h b/include/asm-sh64/unistd.h
index 95f0b130405c..2a1cfa404ea4 100644
--- a/include/asm-sh64/unistd.h
+++ b/include/asm-sh64/unistd.h
@@ -338,8 +338,13 @@
 #define __NR_add_key            313
 #define __NR_request_key        314
 #define __NR_keyctl             315
+#define __NR_ioprio_set         316
+#define __NR_ioprio_get         317
+#define __NR_inotify_init       318
+#define __NR_inotify_add_watch  319
+#define __NR_inotify_rm_watch   320
 
-#define NR_syscalls 316
+#define NR_syscalls 321
 
 /* user-visible error numbers are in the range -1 - -125: see <asm-sh64/errno.h> */
 
diff --git a/include/asm-sparc/auxvec.h b/include/asm-sparc/auxvec.h
new file mode 100644
index 000000000000..ad6f360261f6
--- /dev/null
+++ b/include/asm-sparc/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMSPARC_AUXVEC_H
+#define __ASMSPARC_AUXVEC_H
+
+#endif /* !(__ASMSPARC_AUXVEC_H) */
diff --git a/include/asm-sparc/emergency-restart.h b/include/asm-sparc/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-sparc/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sparc/fcntl.h b/include/asm-sparc/fcntl.h
index df9c75d41d68..5db60b5ae7b0 100644
--- a/include/asm-sparc/fcntl.h
+++ b/include/asm-sparc/fcntl.h
@@ -4,10 +4,6 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_RDONLY        0x0000
-#define O_WRONLY        0x0001
-#define O_RDWR          0x0002
-#define O_ACCMODE       0x0003
 #define O_APPEND        0x0008
 #define FASYNC          0x0040  /* fcntl, for BSD compatibility */
 #define O_CREAT         0x0200  /* not fcntl */
@@ -17,73 +13,24 @@
 #define O_NONBLOCK      0x4000
 #define O_NDELAY        (0x0004 | O_NONBLOCK)
 #define O_NOCTTY        0x8000  /* not fcntl */
-#define O_DIRECTORY     0x10000 /* must be a directory */
-#define O_NOFOLLOW      0x20000 /* don't follow links */
 #define O_LARGEFILE     0x40000
 #define O_DIRECT        0x100000 /* direct disk access hint */
 #define O_NOATIME       0x200000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
 #define F_GETOWN        5       /*  for sockets. */
 #define F_SETOWN        6       /*  for sockets. */
 #define F_GETLK         7
 #define F_SETLK         8
 #define F_SETLKW        9
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
 
 /* for posix fcntl() and lockf() */
 #define F_RDLCK         1
 #define F_WRLCK         2
 #define F_UNLCK         3
 
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-        short __unused;
-};
+#define __ARCH_FLOCK_PAD        short __unused;
+#define __ARCH_FLOCK64_PAD      short __unused;
 
-struct flock64 {
-        short l_type;
-        short l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t l_pid;
-        short __unused;
-};
+#include <asm-generic/fcntl.h>
 
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif
diff --git a/include/asm-sparc/futex.h b/include/asm-sparc/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-sparc/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-sparc/hdreg.h b/include/asm-sparc/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-sparc/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h
index 383060e90d94..9122684f6c1e 100644
--- a/include/asm-sparc/page.h
+++ b/include/asm-sparc/page.h
@@ -132,20 +132,6 @@ BTFIXUPDEF_SETHI(sparc_unmapped_base)
 
 #define TASK_UNMAPPED_BASE      BTFIXUP_SETHI(sparc_unmapped_base)
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #else /* !(__ASSEMBLY__) */
 
 #define __pgprot(x)     (x)
@@ -178,4 +164,6 @@ extern unsigned long pfn_base;
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _SPARC_PAGE_H */
diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h
index d200a25a7373..97052baf90c1 100644
--- a/include/asm-sparc/pci.h
+++ b/include/asm-sparc/pci.h
@@ -20,7 +20,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-extern inline void pcibios_penalize_isa_irq(int irq)
+extern inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -144,6 +144,16 @@ extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
 
 #define pci_dac_dma_supported(dev, mask)        (0)
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h
index 40ed30a2b7c6..8f4f6a959651 100644
--- a/include/asm-sparc/pgtable.h
+++ b/include/asm-sparc/pgtable.h
@@ -435,9 +435,6 @@ extern unsigned long *sparc_valid_addr_bitmap;
 #define kern_addr_valid(addr) \
         (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
 
-extern int io_remap_page_range(struct vm_area_struct *vma,
-                               unsigned long from, unsigned long to,
-                               unsigned long size, pgprot_t prot, int space);
 extern int io_remap_pfn_range(struct vm_area_struct *vma,
                               unsigned long from, unsigned long pfn,
                               unsigned long size, pgprot_t prot);
diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h
index 32c9699367cf..5a7a1a8d29ac 100644
--- a/include/asm-sparc/processor.h
+++ b/include/asm-sparc/processor.h
@@ -19,7 +19,6 @@
 #include <asm/ptrace.h>
 #include <asm/head.h>
 #include <asm/signal.h>
-#include <asm/segment.h>
 #include <asm/btfixup.h>
 #include <asm/page.h>
 
diff --git a/include/asm-sparc/segment.h b/include/asm-sparc/segment.h
deleted file mode 100644
index a1b7ffc9eec9..000000000000
--- a/include/asm-sparc/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __SPARC_SEGMENT_H
-#define __SPARC_SEGMENT_H
-
-/* Only here because we have some old header files that expect it.. */
-
-#endif
diff --git a/include/asm-sparc/smp.h b/include/asm-sparc/smp.h
index f986c0d0922a..4f96d8333a12 100644
--- a/include/asm-sparc/smp.h
+++ b/include/asm-sparc/smp.h
@@ -148,7 +148,7 @@ extern __inline__ int hard_smp_processor_id(void)
 }
 #endif
 
-#define smp_processor_id()      (current_thread_info()->cpu)
+#define raw_smp_processor_id()          (current_thread_info()->cpu)
 
 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
 #define prof_counter(__cpu)             cpu_data(__cpu).counter
diff --git a/include/asm-sparc/socket.h b/include/asm-sparc/socket.h
index c1154e3ecfdf..09575b608adb 100644
--- a/include/asm-sparc/socket.h
+++ b/include/asm-sparc/socket.h
@@ -29,6 +29,8 @@
 
 #define SO_SNDBUF       0x1001
 #define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
 #define SO_ERROR        0x1007
 #define SO_TYPE         0x1008
 
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 80cf20cfaee1..3557781a4bfd 100644
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -9,7 +9,6 @@
 #include <linux/threads.h>      /* NR_CPUS */
 #include <linux/thread_info.h>
 
-#include <asm/segment.h>
 #include <asm/page.h>
 #include <asm/psr.h>
 #include <asm/ptrace.h>
@@ -101,7 +100,7 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
  * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
  * XXX WTF is the above comment? Found in late teen 2.4.x.
  */
-#define prepare_arch_switch(rq, next) do { \
+#define prepare_arch_switch(next) do { \
         __asm__ __volatile__( \
         ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
@@ -109,8 +108,6 @@ extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
         "save %sp, -0x40, %sp\n\t" \
         "restore; restore; restore; restore; restore; restore; restore"); \
 } while(0)
-#define finish_arch_switch(rq, next)    spin_unlock_irq(&(rq)->lock)
-#define task_running(rq, p)             ((rq)->curr == (p))
 
         /* Much care has gone into this code, do not touch it.
          *
diff --git a/include/asm-sparc/thread_info.h b/include/asm-sparc/thread_info.h
index 104f03c55416..ff6ccb3d24c6 100644
--- a/include/asm-sparc/thread_info.h
+++ b/include/asm-sparc/thread_info.h
@@ -30,9 +30,9 @@ struct thread_info {
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
-
         int                     cpu;            /* cpu we're on */
-        int                     preempt_count;
+        int                     preempt_count;  /* 0 => preemptable,
+                                                   <0 => BUG */
         int                     softirq_count;
         int                     hardirq_count;
 
diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h
index 9eabf6e61ccc..42fc6ed98156 100644
--- a/include/asm-sparc/types.h
+++ b/include/asm-sparc/types.h
@@ -54,8 +54,6 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h
index 0a780e84a12b..f8f1ec1f06e6 100644
--- a/include/asm-sparc/uaccess.h
+++ b/include/asm-sparc/uaccess.h
@@ -47,12 +47,6 @@
 #define access_ok(type, addr, size)                                     \
         ({ (void)(type); __access_ok((unsigned long)(addr), size); })
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
index 846708403900..58dba518239e 100644
--- a/include/asm-sparc/unistd.h
+++ b/include/asm-sparc/unistd.h
@@ -167,12 +167,12 @@
 #define __NR_pciconfig_read     148 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_write    149 /* ENOSYS under SunOS                          */
 #define __NR_getsockname        150 /* Common                                      */
-/* #define __NR_getmsg          151    SunOS Specific                              */
-/* #define __NR_putmsg          152    SunOS Specific                              */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
 #define __NR_poll               153 /* Common                                      */
 #define __NR_getdents64         154 /* Linux specific                              */
 #define __NR_fcntl64            155 /* Linux sparc32 Specific                      */
-/* #define __NR_getdirentires   156    SunOS Specific                              */
+#define __NR_inotify_rm_watch   156 /* Linux specific                              */
 #define __NR_statfs             157 /* Common                                      */
 #define __NR_fstatfs            158 /* Common                                      */
 #define __NR_umount             159 /* Common                                      */
@@ -212,7 +212,7 @@
 #define __NR_epoll_create       193 /* Linux Specific                              */
 #define __NR_epoll_ctl          194 /* Linux Specific                              */
 #define __NR_epoll_wait         195 /* Linux Specific                              */
-/* #define __NR_ulimit          196    Linux Specific                              */
+#define __NR_ioprio_set         196 /* Linux Specific                              */
 #define __NR_getppid            197 /* Linux Specific                              */
 #define __NR_sigaction          198 /* Linux Specific                              */
 #define __NR_sgetmask           199 /* Linux Specific                              */
@@ -234,7 +234,7 @@
 #define __NR_ipc                215 /* Linux Specific                              */
 #define __NR_sigreturn          216 /* Linux Specific                              */
 #define __NR_clone              217 /* Linux Specific                              */
-/* #define __NR_modify_ldt      218    Linux Specific - i386 specific, unused      */
+#define __NR_ioprio_get         218 /* Linux Specific                              */
 #define __NR_adjtimex           219 /* Linux Specific                              */
 #define __NR_sigprocmask        220 /* Linux Specific                              */
 #define __NR_create_module      221 /* Linux Specific                              */
diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h
index d80f3379669b..e175afcf2cde 100644
--- a/include/asm-sparc64/atomic.h
+++ b/include/asm-sparc64/atomic.h
@@ -72,10 +72,10 @@ extern int atomic64_sub_ret(int, atomic64_t *);
 
 /* Atomic operations are already serializing */
 #ifdef CONFIG_SMP
-#define smp_mb__before_atomic_dec()     membar("#StoreLoad | #LoadLoad")
-#define smp_mb__after_atomic_dec()      membar("#StoreLoad | #StoreStore")
-#define smp_mb__before_atomic_inc()     membar("#StoreLoad | #LoadLoad")
-#define smp_mb__after_atomic_inc()      membar("#StoreLoad | #StoreStore")
+#define smp_mb__before_atomic_dec()     membar_storeload_loadload();
+#define smp_mb__after_atomic_dec()      membar_storeload_storestore();
+#define smp_mb__before_atomic_inc()     membar_storeload_loadload();
+#define smp_mb__after_atomic_inc()      membar_storeload_storestore();
 #else
 #define smp_mb__before_atomic_dec()     barrier()
 #define smp_mb__after_atomic_dec()      barrier()
diff --git a/include/asm-sparc64/auxio.h b/include/asm-sparc64/auxio.h
index 5eb01dd47150..81a590a50a1f 100644
--- a/include/asm-sparc64/auxio.h
+++ b/include/asm-sparc64/auxio.h
@@ -75,6 +75,8 @@
 
 #ifndef __ASSEMBLY__
 
+extern void __iomem *auxio_register;
+
 #define AUXIO_LTE_ON    1
 #define AUXIO_LTE_OFF   0
 
diff --git a/include/asm-sparc64/auxvec.h b/include/asm-sparc64/auxvec.h
new file mode 100644
index 000000000000..436a29129828
--- /dev/null
+++ b/include/asm-sparc64/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_SPARC64_AUXVEC_H
+#define __ASM_SPARC64_AUXVEC_H
+
+#endif /* !(__ASM_SPARC64_AUXVEC_H) */
diff --git a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
index 9d722dc8cca3..6388b8376c50 100644
--- a/include/asm-sparc64/bitops.h
+++ b/include/asm-sparc64/bitops.h
@@ -20,72 +20,72 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr);
 
 /* "non-atomic" versions... */
 
-static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
+static inline void __set_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
 
         *m |= (1UL << (nr & 63));
 }
 
-static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
 
         *m &= ~(1UL << (nr & 63));
 }
 
-static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
+static inline void __change_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
 
         *m ^= (1UL << (nr & 63));
 }
 
-static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
-        long old = *m;
-        long mask = (1UL << (nr & 63));
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+        unsigned long old = *m;
+        unsigned long mask = (1UL << (nr & 63));
 
         *m = (old | mask);
         return ((old & mask) != 0);
 }
 
-static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
-        long old = *m;
-        long mask = (1UL << (nr & 63));
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+        unsigned long old = *m;
+        unsigned long mask = (1UL << (nr & 63));
 
         *m = (old & ~mask);
         return ((old & mask) != 0);
 }
 
-static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
 {
-        volatile unsigned long *m = addr + (nr >> 6);
-        long old = *m;
-        long mask = (1UL << (nr & 63));
+        unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+        unsigned long old = *m;
+        unsigned long mask = (1UL << (nr & 63));
 
         *m = (old ^ mask);
         return ((old & mask) != 0);
 }
 
 #ifdef CONFIG_SMP
-#define smp_mb__before_clear_bit()      membar("#StoreLoad | #LoadLoad")
-#define smp_mb__after_clear_bit()       membar("#StoreLoad | #StoreStore")
+#define smp_mb__before_clear_bit()      membar_storeload_loadload()
+#define smp_mb__after_clear_bit()       membar_storeload_storestore()
 #else
 #define smp_mb__before_clear_bit()      barrier()
 #define smp_mb__after_clear_bit()       barrier()
 #endif
 
-static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr)
+static inline int test_bit(int nr, __const__ volatile unsigned long *addr)
 {
-        return (1UL & ((addr)[nr >> 6] >> (nr & 63))) != 0UL;
+        return (1UL & (addr[nr >> 6] >> (nr & 63))) != 0UL;
 }
 
 /* The easy/cheese version for now. */
-static __inline__ unsigned long ffz(unsigned long word)
+static inline unsigned long ffz(unsigned long word)
 {
         unsigned long result;
 
@@ -103,7 +103,7 @@ static __inline__ unsigned long ffz(unsigned long word)
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
-static __inline__ unsigned long __ffs(unsigned long word)
+static inline unsigned long __ffs(unsigned long word)
 {
         unsigned long result = 0;
 
@@ -144,7 +144,7 @@ static inline int sched_find_first_bit(unsigned long *b)
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
-static __inline__ int ffs(int x)
+static inline int ffs(int x)
 {
         if (!x)
                 return 0;
@@ -158,7 +158,7 @@ static __inline__ int ffs(int x)
 
 #ifdef ULTRA_HAS_POPULATION_COUNT
 
-static __inline__ unsigned int hweight64(unsigned long w)
+static inline unsigned int hweight64(unsigned long w)
 {
         unsigned int res;
 
@@ -166,7 +166,7 @@ static __inline__ unsigned int hweight64(unsigned long w)
         return res;
 }
 
-static __inline__ unsigned int hweight32(unsigned int w)
+static inline unsigned int hweight32(unsigned int w)
 {
         unsigned int res;
 
@@ -174,7 +174,7 @@ static __inline__ unsigned int hweight32(unsigned int w)
         return res;
 }
 
-static __inline__ unsigned int hweight16(unsigned int w)
+static inline unsigned int hweight16(unsigned int w)
 {
         unsigned int res;
 
@@ -182,7 +182,7 @@ static __inline__ unsigned int hweight16(unsigned int w)
         return res;
 }
 
-static __inline__ unsigned int hweight8(unsigned int w)
+static inline unsigned int hweight8(unsigned int w)
 {
         unsigned int res;
 
@@ -236,7 +236,7 @@ extern unsigned long find_next_zero_bit(const unsigned long *,
 #define test_and_clear_le_bit(nr,addr)  \
         test_and_clear_bit((nr) ^ 0x38, (addr))
 
-static __inline__ int test_le_bit(int nr, __const__ unsigned long * addr)
+static inline int test_le_bit(int nr, __const__ unsigned long * addr)
 {
         int                     mask;
         __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h
index 22f58055b8ab..c73935dc7ba1 100644
--- a/include/asm-sparc64/compat.h
+++ b/include/asm-sparc64/compat.h
@@ -12,8 +12,10 @@ typedef s32		compat_ssize_t;
 typedef s32             compat_time_t;
 typedef s32             compat_clock_t;
 typedef s32             compat_pid_t;
-typedef u16             compat_uid_t;
-typedef u16             compat_gid_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u16             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u16             compat_dev_t;
@@ -25,6 +27,7 @@ typedef s32		compat_daddr_t;
 typedef u32             compat_caddr_t;
 typedef __kernel_fsid_t compat_fsid_t;
 typedef s32             compat_key_t;
+typedef s32             compat_timer_t;
 
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
@@ -46,8 +49,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
         compat_dev_t    st_rdev;
         compat_off_t    st_size;
         compat_time_t   st_atime;
@@ -176,10 +179,10 @@ static __inline__ void __user *compat_alloc_user_space(long len)
 
 struct compat_ipc64_perm {
         compat_key_t key;
-        __kernel_uid_t uid;
-        __kernel_gid_t gid;
-        __kernel_uid_t cuid;
-        __kernel_gid_t cgid;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
         unsigned short __pad1;
         compat_mode_t mode;
         unsigned short __pad2;
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index cc7198aaac50..9a3a81f1cc58 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -1,6 +1,6 @@
 /* cpudata.h: Per-cpu parameters.
  *
- * Copyright (C) 2003 David S. Miller (davem@redhat.com)
+ * Copyright (C) 2003, 2005 David S. Miller (davem@redhat.com)
  */
 
 #ifndef _SPARC64_CPUDATA_H
@@ -10,7 +10,7 @@
 
 typedef struct {
         /* Dcache line 1 */
-        unsigned int    __pad0;         /* bh_count moved to irq_stat for consistency. KAO */
+        unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
         unsigned int    multiplier;
         unsigned int    counter;
         unsigned int    idle_volume;
diff --git a/include/asm-sparc64/emergency-restart.h b/include/asm-sparc64/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-sparc64/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sparc64/fcntl.h b/include/asm-sparc64/fcntl.h
index e36def0d0d80..b2aecf0054bd 100644
--- a/include/asm-sparc64/fcntl.h
+++ b/include/asm-sparc64/fcntl.h
@@ -4,10 +4,6 @@
 
 /* open/fcntl - O_SYNC is only implemented on blocks devices and on files
    located on an ext2 file system */
-#define O_RDONLY        0x0000
-#define O_WRONLY        0x0001
-#define O_RDWR          0x0002
-#define O_ACCMODE       0x0003
 #define O_NDELAY        0x0004
 #define O_APPEND        0x0008
 #define FASYNC          0x0040  /* fcntl, for BSD compatibility */
@@ -17,62 +13,24 @@
 #define O_SYNC          0x2000
 #define O_NONBLOCK      0x4000
 #define O_NOCTTY        0x8000  /* not fcntl */
-#define O_DIRECTORY     0x10000 /* must be a directory */
-#define O_NOFOLLOW      0x20000 /* don't follow links */
 #define O_LARGEFILE     0x40000
 #define O_DIRECT        0x100000 /* direct disk access hint */
 #define O_NOATIME       0x200000
 
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
 #define F_GETOWN        5       /*  for sockets. */
 #define F_SETOWN        6       /*  for sockets. */
 #define F_GETLK         7
 #define F_SETLK         8
 #define F_SETLKW        9
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
 
 /* for posix fcntl() and lockf() */
 #define F_RDLCK         1
 #define F_WRLCK         2
 #define F_UNLCK         3
 
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-        short __unused;
-};
+#define __ARCH_FLOCK_PAD        short __unused;
 
-#define F_LINUX_SPECIFIC_BASE   1024
+#include <asm-generic/fcntl.h>
 
 #endif /* !(_SPARC64_FCNTL_H) */
diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h
index e071b4b4edfd..49d49a285943 100644
--- a/include/asm-sparc64/floppy.h
+++ b/include/asm-sparc64/floppy.h
@@ -159,7 +159,7 @@ static void sun_82077_fd_outb(unsigned char value, unsigned long port)
  * underruns.  If non-zero, doing_pdma encodes the direction of
  * the transfer for debugging.  1=read 2=write
  */
-char *pdma_vaddr;
+unsigned char *pdma_vaddr;
 unsigned long pdma_size;
 volatile int doing_pdma = 0;
 
@@ -209,8 +209,7 @@ static void sun_fd_enable_dma(void)
         pdma_areasize = pdma_size;
 }
 
-/* Our low-level entry point in arch/sparc/kernel/entry.S */
-extern irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs);
+extern irqreturn_t sparc_floppy_irq(int, void *, struct pt_regs *);
 
 static int sun_fd_request_irq(void)
 {
@@ -220,8 +219,8 @@ static int sun_fd_request_irq(void)
         if(!once) {
                 once = 1;
 
-                error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, 
-                                         SA_INTERRUPT, "floppy", NULL);
+                error = request_irq(FLOPPY_IRQ, sparc_floppy_irq, 
+                                    SA_INTERRUPT, "floppy", NULL);
 
                 return ((error == 0) ? 0 : -1);
         }
@@ -615,7 +614,7 @@ static unsigned long __init sun_floppy_init(void)
                 struct linux_ebus *ebus;
                 struct linux_ebus_device *edev = NULL;
                 unsigned long config = 0;
-                unsigned long auxio_reg;
+                void __iomem *auxio_reg;
 
                 for_each_ebus(ebus) {
                         for_each_ebusdev(edev, ebus) {
@@ -642,7 +641,7 @@ static unsigned long __init sun_floppy_init(void)
                 /* Make sure the high density bit is set, some systems
                  * (most notably Ultra5/Ultra10) come up with it clear.
                  */
-                auxio_reg = edev->resource[2].start;
+                auxio_reg = (void __iomem *) edev->resource[2].start;
                 writel(readl(auxio_reg)|0x2, auxio_reg);
 
                 sun_pci_ebus_dev = ebus->self;
@@ -650,7 +649,8 @@ static unsigned long __init sun_floppy_init(void)
                 spin_lock_init(&sun_pci_fd_ebus_dma.lock);
 
                 /* XXX ioremap */
-                sun_pci_fd_ebus_dma.regs = edev->resource[1].start;
+                sun_pci_fd_ebus_dma.regs = (void __iomem *)
+                        edev->resource[1].start;
                 if (!sun_pci_fd_ebus_dma.regs)
                         return 0;
 
diff --git a/include/asm-sparc64/futex.h b/include/asm-sparc64/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-sparc64/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h
index d6db1aed7645..f0cf71376ec5 100644
--- a/include/asm-sparc64/hardirq.h
+++ b/include/asm-sparc64/hardirq.h
@@ -1,22 +1,16 @@
 /* hardirq.h: 64-bit Sparc hard IRQ support.
  *
- * Copyright (C) 1997, 1998 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net)
  */
 
 #ifndef __SPARC64_HARDIRQ_H
 #define __SPARC64_HARDIRQ_H
 
-#include <linux/config.h>
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
+#include <asm/cpudata.h>
 
-/* rtrap.S is sensitive to the offsets of these fields */
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+#define __ARCH_IRQ_STAT
+#define local_softirq_pending() \
+        (local_cpu_data().__softirq_pending)
 
 #define HARDIRQ_BITS    8
 
diff --git a/include/asm-sparc64/hdreg.h b/include/asm-sparc64/hdreg.h
deleted file mode 100644
index 7f7fd1af0af3..000000000000
--- a/include/asm-sparc64/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/hdreg.h>
diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h
index afdcea90707a..0056770e83ad 100644
--- a/include/asm-sparc64/io.h
+++ b/include/asm-sparc64/io.h
@@ -100,18 +100,41 @@ static __inline__ void _outl(u32 l, unsigned long addr)
 #define inl_p(__addr)           inl(__addr)
 #define outl_p(__l, __addr)     outl(__l, __addr)
 
-extern void outsb(void __iomem *addr, const void *src, unsigned long count);
-extern void outsw(void __iomem *addr, const void *src, unsigned long count);
-extern void outsl(void __iomem *addr, const void *src, unsigned long count);
-extern void insb(void __iomem *addr, void *dst, unsigned long count);
-extern void insw(void __iomem *addr, void *dst, unsigned long count);
-extern void insl(void __iomem *addr, void *dst, unsigned long count);
-#define ioread8_rep(a,d,c)      insb(a,d,c)
-#define ioread16_rep(a,d,c)     insw(a,d,c)
-#define ioread32_rep(a,d,c)     insl(a,d,c)
-#define iowrite8_rep(a,s,c)     outsb(a,s,c)
-#define iowrite16_rep(a,s,c)    outsw(a,s,c)
-#define iowrite32_rep(a,s,c)    outsl(a,s,c)
+extern void outsb(unsigned long, const void *, unsigned long);
+extern void outsw(unsigned long, const void *, unsigned long);
+extern void outsl(unsigned long, const void *, unsigned long);
+extern void insb(unsigned long, void *, unsigned long);
+extern void insw(unsigned long, void *, unsigned long);
+extern void insl(unsigned long, void *, unsigned long);
+
+static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insb((unsigned long __force)port, buf, count);
+}
+static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insw((unsigned long __force)port, buf, count);
+}
+
+static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insl((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsb((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsw((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsl((unsigned long __force)port, buf, count);
+}
 
 /* Memory functions, same as I/O accesses on Ultra. */
 static inline u8 _readb(const volatile void __iomem *addr)
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index 3aef0ca67750..8b70edcb80dc 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -16,10 +16,22 @@
 #include <asm/pil.h>
 #include <asm/ptrace.h>
 
+struct ino_bucket;
+
+#define MAX_IRQ_DESC_ACTION     4
+
+struct irq_desc {
+        void                    (*pre_handler)(struct ino_bucket *, void *, void *);
+        void                    *pre_handler_arg1;
+        void                    *pre_handler_arg2;
+        u32                     action_active_mask;
+        struct irqaction        action[MAX_IRQ_DESC_ACTION];
+};
+
 /* You should not mess with this directly. That's the job of irq.c.
  *
  * If you make changes here, please update hand coded assembler of
- * SBUS/floppy interrupt handler in entry.S -DaveM
+ * the vectored interrupt trap handler in entry.S -DaveM
  *
  * This is currently one DCACHE line, two buckets per L2 cache
  * line.  Keep this in mind please.
@@ -42,24 +54,11 @@ struct ino_bucket {
         /* Miscellaneous flags. */
 /*0x06*/unsigned char flags;
 
-        /* This is used to deal with IBF_DMA_SYNC on
-         * Sabre systems.
-         */
-/*0x07*/unsigned char synctab_ent;
-
-        /* Reference to handler for this IRQ.  If this is
-         * non-NULL this means it is active and should be
-         * serviced.  Else the pending member is set to one
-         * and later registry of the interrupt checks for
-         * this condition.
-         *
-         * Normally this is just an irq_action structure.
-         * But, on PCI, if multiple interrupt sources behind
-         * a bridge have multiple interrupt sources that share
-         * the same INO bucket, this points to an array of
-         * pointers to four IRQ action structures.
-         */
-/*0x08*/void *irq_info;
+        /* Currently unused.  */
+/*0x07*/unsigned char __pad;
+
+        /* Reference to IRQ descriptor for this bucket. */
+/*0x08*/struct irq_desc *irq_info;
 
         /* Sun5 Interrupt Clear Register. */
 /*0x10*/unsigned long iclr;
@@ -69,12 +68,6 @@ struct ino_bucket {
 
 };
 
-#ifdef CONFIG_PCI
-extern unsigned long pci_dma_wsync;
-extern unsigned long dma_sync_reg_table[256];
-extern unsigned char dma_sync_reg_table_entry;
-#endif
-
 /* IMAP/ICLR register defines */
 #define IMAP_VALID              0x80000000      /* IRQ Enabled          */
 #define IMAP_TID_UPA            0x7c000000      /* UPA TargetID         */
@@ -90,11 +83,9 @@ extern unsigned char dma_sync_reg_table_entry;
 #define ICLR_PENDING            0x00000003      /* Pending state        */
 
 /* Only 8-bits are available, be careful.  -DaveM */
-#define IBF_DMA_SYNC    0x01    /* DMA synchronization behind PCI bridge needed. */
-#define IBF_PCI         0x02    /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt.  */
-#define IBF_ACTIVE      0x04    /* This interrupt is active and has a handler.   */
-#define IBF_MULTI       0x08    /* On PCI, indicates shared bucket.              */
-#define IBF_INPROGRESS  0x10    /* IRQ is being serviced.                        */
+#define IBF_PCI         0x02    /* PSYCHO/SABRE/SCHIZO PCI interrupt.    */
+#define IBF_ACTIVE      0x04    /* Interrupt is active and has a handler.*/
+#define IBF_INPROGRESS  0x10    /* IRQ is being serviced.                */
 
 #define NUM_IVECS       (IMAP_INR + 1)
 extern struct ino_bucket ivector_table[NUM_IVECS];
@@ -122,11 +113,6 @@ extern void enable_irq(unsigned int);
 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 
-extern int request_fast_irq(unsigned int irq,
-                            irqreturn_t (*handler)(int, void *, struct pt_regs *),
-                            unsigned long flags, __const__ char *devname,
-                            void *dev_id);
-
 static __inline__ void set_softint(unsigned long bits)
 {
         __asm__ __volatile__("wr        %0, 0x0, %%set_softint"
diff --git a/include/asm-sparc64/kdebug.h b/include/asm-sparc64/kdebug.h
index f70d3dad01f9..6321f5a0198d 100644
--- a/include/asm-sparc64/kdebug.h
+++ b/include/asm-sparc64/kdebug.h
@@ -16,7 +16,7 @@ struct die_args {
 };
 
 /* Note - you should never unregister because that can race with NMIs.
- * If you really want to do it first unregister - then synchronize_kernel
+ * If you really want to do it first unregister - then synchronize_sched
  * - then free.
  */
 int register_die_notifier(struct notifier_block *nb);
diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h
index 219ea043a14a..c9f8ef208ea5 100644
--- a/include/asm-sparc64/page.h
+++ b/include/asm-sparc64/page.h
@@ -95,6 +95,8 @@ typedef unsigned long pgprot_t;
 #define HPAGE_SIZE              (_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK              (~(HPAGE_SIZE - 1UL))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#define ARCH_HAS_SETCLEAR_HUGE_PTE
+#define ARCH_HAS_HUGETLB_PREFAULT_HOOK
 #endif
 
 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_32BIT) ? \
@@ -148,20 +150,6 @@ struct sparc_phys_banks {
 
 extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
 
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #endif /* !(__ASSEMBLY__) */
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
@@ -169,4 +157,6 @@ static __inline__ int get_order(unsigned long size)
 
 #endif /* !(__KERNEL__) */
 
+#include <asm-generic/page.h>
+
 #endif /* !(_SPARC64_PAGE_H) */
diff --git a/include/asm-sparc64/param.h b/include/asm-sparc64/param.h
index 6a12f3ac0359..a1cd4974630b 100644
--- a/include/asm-sparc64/param.h
+++ b/include/asm-sparc64/param.h
@@ -1,9 +1,10 @@
-/* $Id: param.h,v 1.2 2000/10/30 21:01:41 davem Exp $ */
 #ifndef _ASMSPARC64_PARAM_H
 #define _ASMSPARC64_PARAM_H
 
+#include <linux/config.h>
+
 #ifdef __KERNEL__
-# define HZ             1000    /* Internal kernel timer frequency */
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
 # define USER_HZ        100     /* .. some user interfaces are in "ticks" */
 # define CLOCKS_PER_SEC (USER_HZ)
 #endif
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
index b7e635544cec..56b5197d7898 100644
--- a/include/asm-sparc64/parport.h
+++ b/include/asm-sparc64/parport.h
@@ -27,12 +27,12 @@ static struct sparc_ebus_info {
 
 static __inline__ void enable_dma(unsigned int dmanr)
 {
+        ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
+
         if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
                              sparc_ebus_dmas[dmanr].addr,
                              sparc_ebus_dmas[dmanr].count))
                 BUG();
-
-        ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
 }
 
 static __inline__ void disable_dma(unsigned int dmanr)
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 4c15610a2bac..38bbbccb4068 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -145,6 +145,9 @@ struct pci_pbm_info {
         /* Physical address base of PBM registers. */
         unsigned long                   pbm_regs;
 
+        /* Physical address of DMA sync register, if any.  */
+        unsigned long                   sync_reg;
+
         /* Opaque 32-bit system bus Port ID. */
         u32                             portid;
 
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
index 2a0c85cd1c11..a4ab0ec7143a 100644
--- a/include/asm-sparc64/pci.h
+++ b/include/asm-sparc64/pci.h
@@ -23,7 +23,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-static inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't do dynamic PCI IRQ allocation */
 }
@@ -220,6 +220,25 @@ static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
         return (dma_addr == PCI_DMA_ERROR_CODE);
 }
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_BOUNDARY;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
 /* Return the index of the PCI controller for device PDEV. */
 
 extern int pci_domain_nr(struct pci_bus *bus);
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index ae2cd5b09a7c..a2b4f5ed4625 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -286,6 +286,7 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
 #define pte_mkyoung(pte)        (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
 #define pte_mkwrite(pte)        (__pte(pte_val(pte) | _PAGE_WRITE))
 #define pte_mkdirty(pte)        (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) | _PAGE_SZHUGE))
 
 /* to find an entry in a page-table-directory. */
 #define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
@@ -409,9 +410,6 @@ extern unsigned long *sparc64_valid_addr_bitmap;
 #define kern_addr_valid(addr)   \
         (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
 
-extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from,
-                               unsigned long offset,
-                               unsigned long size, pgprot_t prot, int space);
 extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
                                unsigned long pfn,
                                unsigned long size, pgprot_t prot);
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
index bc1445b904ef..3169f3e2237e 100644
--- a/include/asm-sparc64/processor.h
+++ b/include/asm-sparc64/processor.h
@@ -18,7 +18,6 @@
 #include <asm/a.out.h>
 #include <asm/pstate.h>
 #include <asm/ptrace.h>
-#include <asm/segment.h>
 #include <asm/page.h>
 
 /* The sparc has no problems with write protection */
@@ -192,6 +191,40 @@ extern unsigned long get_wchan(struct task_struct *task);
 
 #define cpu_relax()     barrier()
 
+/* Prefetch support.  This is tuned for UltraSPARC-III and later.
+ * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
+ * a shallower prefetch queue than later chips.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+static inline void prefetch(const void *x)
+{
+        /* We do not use the read prefetch mnemonic because that
+         * prefetches into the prefetch-cache which only is accessible
+         * by floating point operations in UltraSPARC-III and later.
+         * By contrast, "#one_write" prefetches into the L2 cache
+         * in shared state.
+         */
+        __asm__ __volatile__("prefetch [%0], #one_write"
+                             : /* no outputs */
+                             : "r" (x));
+}
+
+static inline void prefetchw(const void *x)
+{
+        /* The most optimal prefetch to use for writes is
+         * "#n_writes".  This brings the cacheline into the
+         * L2 cache in "owned" state.
+         */
+        __asm__ __volatile__("prefetch [%0], #n_writes"
+                             : /* no outputs */
+                             : "r" (x));
+}
+
+#define spin_lock_prefetch(x)   prefetchw(x)
+
 #endif /* !(__ASSEMBLY__) */
 
 #endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h
index 2d2b5a113d24..6194f771e9fc 100644
--- a/include/asm-sparc64/ptrace.h
+++ b/include/asm-sparc64/ptrace.h
@@ -94,8 +94,9 @@ struct sparc_trapf {
 #define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
 
 #ifdef __KERNEL__
-#define force_successful_syscall_return()       \
-        set_thread_flag(TIF_SYSCALL_SUCCESS)
+#define force_successful_syscall_return()           \
+do {    current_thread_info()->syscall_noerror = 1; \
+} while (0)
 #define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
 #define instruction_pointer(regs) ((regs)->tpc)
 #ifdef CONFIG_SMP
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index bf2ae90ed3df..4568ee4022df 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -46,53 +46,14 @@ extern void __up_read(struct rw_semaphore *sem);
 extern void __up_write(struct rw_semaphore *sem);
 extern void __downgrade_write(struct rw_semaphore *sem);
 
-static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
 {
-        int tmp = delta;
-
-        __asm__ __volatile__(
-                "1:\tlduw       [%2], %%g1\n\t"
-                "add            %%g1, %1, %%g7\n\t"
-                "cas            [%2], %%g1, %%g7\n\t"
-                "cmp            %%g1, %%g7\n\t"
-                "bne,pn         %%icc, 1b\n\t"
-                " membar        #StoreLoad | #StoreStore\n\t"
-                "mov            %%g7, %0\n\t"
-                : "=&r" (tmp)
-                : "0" (tmp), "r" (sem)
-                : "g1", "g7", "memory", "cc");
-
-        return tmp + delta;
-}
-
-#define rwsem_atomic_add rwsem_atomic_update
-
-static __inline__ __u16 rwsem_cmpxchgw(struct rw_semaphore *sem, __u16 __old, __u16 __new)
-{
-        u32 old = (sem->count & 0xffff0000) | (u32) __old;
-        u32 new = (old & 0xffff0000) | (u32) __new;
-        u32 prev;
-
-again:
-        __asm__ __volatile__("cas       [%2], %3, %0\n\t"
-                             "membar    #StoreLoad | #StoreStore"
-                             : "=&r" (prev)
-                             : "0" (new), "r" (sem), "r" (old)
-                             : "memory");
-
-        /* To give the same semantics as x86 cmpxchgw, keep trying
-         * if only the upper 16-bits changed.
-         */
-        if (prev != old &&
-            ((prev & 0xffff) == (old & 0xffff)))
-                goto again;
-
-        return prev & 0xffff;
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
 
-static __inline__ signed long rwsem_cmpxchg(struct rw_semaphore *sem, signed long old, signed long new)
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
 {
-        return cmpxchg(&sem->count,old,new);
+        atomic_add(delta, (atomic_t *)(&sem->count));
 }
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-sparc64/seccomp.h b/include/asm-sparc64/seccomp.h
new file mode 100644
index 000000000000..7fcd9968192b
--- /dev/null
+++ b/include/asm-sparc64/seccomp.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_SECCOMP_H
+
+#include <linux/thread_info.h> /* already defines TIF_32BIT */
+
+#ifndef TIF_32BIT
+#error "unexpected TIF_32BIT on sparc64"
+#endif
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#define __NR_seccomp_read_32 __NR_read
+#define __NR_seccomp_write_32 __NR_write
+#define __NR_seccomp_exit_32 __NR_exit
+#define __NR_seccomp_sigreturn_32 __NR_sigreturn
+
+#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-sparc64/segment.h b/include/asm-sparc64/segment.h
deleted file mode 100644
index b03e709fc945..000000000000
--- a/include/asm-sparc64/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __SPARC64_SEGMENT_H
-#define __SPARC64_SEGMENT_H
-
-/* Only here because we have some old header files that expect it.. */
-
-#endif
diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h
new file mode 100644
index 000000000000..2f792c20b53c
--- /dev/null
+++ b/include/asm-sparc64/sfafsr.h
@@ -0,0 +1,82 @@
+#ifndef _SPARC64_SFAFSR_H
+#define _SPARC64_SFAFSR_H
+
+#include <asm/const.h>
+
+/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+
+#define SFAFSR_ME               (_AC(1,UL) << SFAFSR_ME_SHIFT)
+#define SFAFSR_ME_SHIFT         32
+#define SFAFSR_PRIV             (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
+#define SFAFSR_PRIV_SHIFT       31
+#define SFAFSR_ISAP             (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
+#define SFAFSR_ISAP_SHIFT       30
+#define SFAFSR_ETP              (_AC(1,UL) << SFAFSR_ETP_SHIFT)
+#define SFAFSR_ETP_SHIFT        29
+#define SFAFSR_IVUE             (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
+#define SFAFSR_IVUE_SHIFT       28
+#define SFAFSR_TO               (_AC(1,UL) << SFAFSR_TO_SHIFT)
+#define SFAFSR_TO_SHIFT         27
+#define SFAFSR_BERR             (_AC(1,UL) << SFAFSR_BERR_SHIFT)
+#define SFAFSR_BERR_SHIFT       26
+#define SFAFSR_LDP              (_AC(1,UL) << SFAFSR_LDP_SHIFT)
+#define SFAFSR_LDP_SHIFT        25
+#define SFAFSR_CP               (_AC(1,UL) << SFAFSR_CP_SHIFT)
+#define SFAFSR_CP_SHIFT         24
+#define SFAFSR_WP               (_AC(1,UL) << SFAFSR_WP_SHIFT)
+#define SFAFSR_WP_SHIFT         23
+#define SFAFSR_EDP              (_AC(1,UL) << SFAFSR_EDP_SHIFT)
+#define SFAFSR_EDP_SHIFT        22
+#define SFAFSR_UE               (_AC(1,UL) << SFAFSR_UE_SHIFT)
+#define SFAFSR_UE_SHIFT         21
+#define SFAFSR_CE               (_AC(1,UL) << SFAFSR_CE_SHIFT)
+#define SFAFSR_CE_SHIFT         20
+#define SFAFSR_ETS              (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
+#define SFAFSR_ETS_SHIFT        16
+#define SFAFSR_PSYND            (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
+#define SFAFSR_PSYND_SHIFT      0
+
+/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
+ *                     ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
+ */
+
+#define UDBE_UE                 (_AC(1,UL) << 9)
+#define UDBE_CE                 (_AC(1,UL) << 8)
+#define UDBE_E_SYNDR            (_AC(0xff,UL) << 0)
+
+/* The trap handlers for asynchronous errors encode the AFSR and
+ * other pieces of information into a 64-bit argument for C code
+ * encoded as follows:
+ *
+ * -----------------------------------------------
+ * |  UDB_H  |  UDB_L  | TL>1  |  TT  |   AFSR   |
+ * -----------------------------------------------
+ *  63     54 53     44    42   41  33 32       0
+ *
+ * The AFAR is passed in unchanged.
+ */
+#define SFSTAT_UDBH_MASK        (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBH_SHIFT       54
+#define SFSTAT_UDBL_MASK        (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBL_SHIFT       44
+#define SFSTAT_TL_GT_ONE        (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
+#define SFSTAT_TL_GT_ONE_SHIFT  42
+#define SFSTAT_TRAP_TYPE        (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
+#define SFSTAT_TRAP_TYPE_SHIFT  33
+#define SFSTAT_AFSR_MASK        (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
+#define SFSTAT_AFSR_SHIFT       0
+
+/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
+#define ESTATE_ERR_CE           0x1 /* Correctable errors                    */
+#define ESTATE_ERR_NCE          0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
+#define ESTATE_ERR_ISAP         0x4 /* System address parity error           */
+#define ESTATE_ERR_ALL          (ESTATE_ERR_CE | \
+                                 ESTATE_ERR_NCE | \
+                                 ESTATE_ERR_ISAP)
+
+/* The various trap types that report using the above state. */
+#define TRAP_TYPE_IAE           0x09 /* Instruction Access Error             */
+#define TRAP_TYPE_DAE           0x32 /* Data Access Error                    */
+#define TRAP_TYPE_CEE           0x63 /* Correctable ECC Error                */
+
+#endif /* _SPARC64_SFAFSR_H */
diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h
index becdf1bc5924..e3059bb4a465 100644
--- a/include/asm-sparc64/signal.h
+++ b/include/asm-sparc64/signal.h
@@ -162,21 +162,6 @@ struct sigstack {
 #define MINSIGSTKSZ     4096
 #define SIGSTKSZ        16384
 
-#ifdef __KERNEL__
-/*
- * DJHR
- * SA_STATIC_ALLOC is used for the SPARC system to indicate that this
- * interrupt handler's irq structure should be statically allocated
- * by the request_irq routine.
- * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge
- * of interrupt usage and that sucks. Also without a flag like this
- * it may be possible for the free_irq routine to attempt to free
- * statically allocated data.. which is NOT GOOD.
- *
- */
-#define SA_STATIC_ALLOC         0x80
-#endif
-
 #include <asm-generic/signal.h>
 
 struct __new_sigaction {
diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h
index 5e3e06d908fe..110a2de89123 100644
--- a/include/asm-sparc64/smp.h
+++ b/include/asm-sparc64/smp.h
@@ -64,7 +64,7 @@ static __inline__ int hard_smp_processor_id(void)
         }
 }
 
-#define smp_processor_id() (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
 
 #endif /* !(__ASSEMBLY__) */
 
diff --git a/include/asm-sparc64/socket.h b/include/asm-sparc64/socket.h
index 865547a23908..59987dad3359 100644
--- a/include/asm-sparc64/socket.h
+++ b/include/asm-sparc64/socket.h
@@ -29,6 +29,8 @@
 
 #define SO_SNDBUF       0x1001
 #define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
 #define SO_ERROR        0x1007
 #define SO_TYPE         0x1008
 
diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h
index db7581bdb531..a02c4370eb42 100644
--- a/include/asm-sparc64/spinlock.h
+++ b/include/asm-sparc64/spinlock.h
@@ -43,7 +43,7 @@ typedef struct {
 #define spin_is_locked(lp)  ((lp)->lock != 0)
 
 #define spin_unlock_wait(lp)    \
-do {    membar("#LoadLoad");    \
+do {    rmb();                  \
 } while((lp)->lock)
 
 static inline void _raw_spin_lock(spinlock_t *lock)
@@ -52,12 +52,14 @@ static inline void _raw_spin_lock(spinlock_t *lock)
 
         __asm__ __volatile__(
 "1:     ldstub          [%1], %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       brnz,pn         %0, 2f\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     ldub            [%1], %0\n"
+"       membar          #LoadLoad\n"
 "       brnz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 1b\n"
 "       .previous"
         : "=&r" (tmp)
@@ -95,16 +97,18 @@ static inline void _raw_spin_lock_flags(spinlock_t *lock, unsigned long flags)
 
         __asm__ __volatile__(
 "1:     ldstub          [%2], %0\n"
-"       brnz,pn         %0, 2f\n"
 "       membar          #StoreLoad | #StoreStore\n"
+"       brnz,pn         %0, 2f\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     rdpr            %%pil, %1\n"
 "       wrpr            %3, %%pil\n"
 "3:     ldub            [%2], %0\n"
-"       brnz,pt         %0, 3b\n"
 "       membar          #LoadLoad\n"
+"       brnz,pt         %0, 3b\n"
+"        nop\n"
 "       ba,pt           %%xcc, 1b\n"
-"       wrpr            %1, %%pil\n"
+"        wrpr           %1, %%pil\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
         : "r"(lock), "r"(flags)
@@ -125,15 +129,18 @@ typedef struct {
 #define spin_is_locked(__lock)  ((__lock)->lock != 0)
 #define spin_unlock_wait(__lock)        \
 do { \
-        membar("#LoadLoad"); \
+        rmb(); \
 } while((__lock)->lock)
 
-extern void _do_spin_lock (spinlock_t *lock, char *str);
-extern void _do_spin_unlock (spinlock_t *lock);
-extern int _do_spin_trylock (spinlock_t *lock);
+extern void _do_spin_lock(spinlock_t *lock, char *str, unsigned long caller);
+extern void _do_spin_unlock(spinlock_t *lock);
+extern int _do_spin_trylock(spinlock_t *lock, unsigned long caller);
 
-#define _raw_spin_trylock(lp)   _do_spin_trylock(lp)
-#define _raw_spin_lock(lock)    _do_spin_lock(lock, "spin_lock")
+#define _raw_spin_trylock(lp)   \
+        _do_spin_trylock(lp, (unsigned long) __builtin_return_address(0))
+#define _raw_spin_lock(lock)    \
+        _do_spin_lock(lock, "spin_lock", \
+                      (unsigned long) __builtin_return_address(0))
 #define _raw_spin_unlock(lock)  _do_spin_unlock(lock)
 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
 
@@ -162,12 +169,14 @@ static void inline __read_lock(rwlock_t *lock)
 "4:      add            %0, 1, %1\n"
 "       cas             [%2], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     ldsw            [%2], %0\n"
+"       membar          #LoadLoad\n"
 "       brlz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 4b\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
@@ -204,12 +213,14 @@ static void inline __write_lock(rwlock_t *lock)
 "4:      or             %0, %3, %1\n"
 "       cas             [%2], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       .subsection     2\n"
 "2:     lduw            [%2], %0\n"
+"       membar          #LoadLoad\n"
 "       brnz,pt         %0, 2b\n"
-"        membar         #LoadLoad\n"
+"        nop\n"
 "       ba,a,pt         %%xcc, 4b\n"
 "       .previous"
         : "=&r" (tmp1), "=&r" (tmp2)
@@ -240,8 +251,9 @@ static int inline __write_trylock(rwlock_t *lock)
 "        or             %0, %4, %1\n"
 "       cas             [%3], %0, %1\n"
 "       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
 "       bne,pn          %%icc, 1b\n"
-"        membar         #StoreLoad | #StoreStore\n"
+"        nop\n"
 "       mov             1, %2\n"
 "2:"
         : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
@@ -270,37 +282,41 @@ typedef struct {
 #define RW_LOCK_UNLOCKED        (rwlock_t) { 0, 0, 0xff, { } }
 #define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)
 
-extern void _do_read_lock(rwlock_t *rw, char *str);
-extern void _do_read_unlock(rwlock_t *rw, char *str);
-extern void _do_write_lock(rwlock_t *rw, char *str);
-extern void _do_write_unlock(rwlock_t *rw);
-extern int _do_write_trylock(rwlock_t *rw, char *str);
+extern void _do_read_lock(rwlock_t *rw, char *str, unsigned long caller);
+extern void _do_read_unlock(rwlock_t *rw, char *str, unsigned long caller);
+extern void _do_write_lock(rwlock_t *rw, char *str, unsigned long caller);
+extern void _do_write_unlock(rwlock_t *rw, unsigned long caller);
+extern int _do_write_trylock(rwlock_t *rw, char *str, unsigned long caller);
 
 #define _raw_read_lock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        _do_read_lock(lock, "read_lock"); \
+        _do_read_lock(lock, "read_lock", \
+                      (unsigned long) __builtin_return_address(0)); \
         local_irq_restore(flags); \
 } while(0)
 
 #define _raw_read_unlock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        _do_read_unlock(lock, "read_unlock"); \
+        _do_read_unlock(lock, "read_unlock", \
+                      (unsigned long) __builtin_return_address(0)); \
         local_irq_restore(flags); \
 } while(0)
 
 #define _raw_write_lock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        _do_write_lock(lock, "write_lock"); \
+        _do_write_lock(lock, "write_lock", \
+                      (unsigned long) __builtin_return_address(0)); \
         local_irq_restore(flags); \
 } while(0)
 
 #define _raw_write_unlock(lock) \
 do {    unsigned long flags; \
         local_irq_save(flags); \
-        _do_write_unlock(lock); \
+        _do_write_unlock(lock, \
+                      (unsigned long) __builtin_return_address(0)); \
         local_irq_restore(flags); \
 } while(0)
 
@@ -308,7 +324,8 @@ do {	unsigned long flags; \
 ({      unsigned long flags; \
         int val; \
         local_irq_save(flags); \
-        val = _do_write_trylock(lock, "write_trylock"); \
+        val = _do_write_trylock(lock, "write_trylock", \
+                                (unsigned long) __builtin_return_address(0)); \
         local_irq_restore(flags); \
         val; \
 })
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index 9d7613eea812..962638c9d122 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void);
          SPITFIRE_HIGHEST_LOCKED_TLBENT : \
          CHEETAH_HIGHEST_LOCKED_TLBENT)
 
-static __inline__ unsigned long spitfire_get_isfsr(void)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__("ldxa      [%1] %2, %0"
-                             : "=r" (ret)
-                             : "r" (TLB_SFSR), "i" (ASI_IMMU));
-        return ret;
-}
-
-static __inline__ unsigned long spitfire_get_dsfsr(void)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__("ldxa      [%1] %2, %0"
-                             : "=r" (ret)
-                             : "r" (TLB_SFSR), "i" (ASI_DMMU));
-        return ret;
-}
-
-static __inline__ unsigned long spitfire_get_sfar(void)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__("ldxa      [%1] %2, %0"
-                             : "=r" (ret)
-                             : "r" (DMMU_SFAR), "i" (ASI_DMMU));
-        return ret;
-}
-
-static __inline__ void spitfire_put_isfsr(unsigned long sfsr)
-{
-        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
-                             "membar    #Sync"
-                             : /* no outputs */
-                             : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
-}
-
-static __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
-{
-        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
-                             "membar    #Sync"
-                             : /* no outputs */
-                             : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
-}
-
 /* The data cache is write through, so this just invalidates the
  * specified line.
  */
@@ -111,7 +65,6 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
                              "membar    #Sync"
                              : /* No outputs */
                              : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
-        __asm__ __volatile__ ("membar #Sync" : : : "memory");
 }
 
 /* The instruction cache lines are flushed with this, but note that
@@ -194,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
                                "i" (ASI_ITLB_DATA_ACCESS));
 }
 
-/* Spitfire hardware assisted TLB flushes. */
-
-/* Context level flushes. */
-static __inline__ void spitfire_flush_dtlb_primary_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x40), "i" (ASI_DMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_itlb_primary_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x40), "i" (ASI_IMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_dtlb_secondary_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x50), "i" (ASI_DMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_itlb_secondary_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x50), "i" (ASI_IMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_dtlb_nucleus_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x60), "i" (ASI_DMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_itlb_nucleus_context(void)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (0x60), "i" (ASI_IMMU_DEMAP));
-}
-
-/* Page level flushes. */
-static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (page), "i" (ASI_DMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (page), "i" (ASI_IMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
-}
-
-static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
-{
-        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
-                             "membar    #Sync"
-                             : /* No outputs */
-                             : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
-}
-
 static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
 {
         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index fd12ca386f48..5e94c05dc2fc 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -28,6 +28,14 @@ enum sparc_cpu {
 #define ARCH_SUN4C_SUN4 0
 #define ARCH_SUN4 0
 
+extern void mb(void);
+extern void rmb(void);
+extern void wmb(void);
+extern void membar_storeload(void);
+extern void membar_storeload_storestore(void);
+extern void membar_storeload_loadload(void);
+extern void membar_storestore_loadstore(void);
+
 #endif
 
 #define setipl(__new_ipl) \
@@ -78,16 +86,11 @@ enum sparc_cpu {
 
 #define nop()           __asm__ __volatile__ ("nop")
 
-#define membar(type)    __asm__ __volatile__ ("membar " type : : : "memory")
-#define mb()            \
-        membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
-#define rmb()           membar("#LoadLoad")
-#define wmb()           membar("#StoreStore")
 #define read_barrier_depends()          do { } while(0)
 #define set_mb(__var, __value) \
-        do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0)
+        do { __var = __value; membar_storeload_storestore(); } while(0)
 #define set_wmb(__var, __value) \
-        do { __var = __value; membar("#StoreStore"); } while(0)
+        do { __var = __value; wmb(); } while(0)
 
 #ifdef CONFIG_SMP
 #define smp_mb()        mb()
@@ -139,19 +142,13 @@ extern void __flushw_user(void);
 #define flush_user_windows flushw_user
 #define flush_register_windows flushw_all
 
-#define prepare_arch_switch(rq, next)           \
-do {    spin_lock(&(next)->switch_lock);        \
-        spin_unlock(&(rq)->lock);               \
+/* Don't hold the runqueue lock over context switch */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+#define prepare_arch_switch(next)               \
+do {                                            \
         flushw_all();                           \
 } while (0)
 
-#define finish_arch_switch(rq, prev)            \
-do {    spin_unlock_irq(&(prev)->switch_lock);  \
-} while (0)
-
-#define task_running(rq, p) \
-        ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
-
         /* See what happens when you design the chip correctly?
          *
          * We tell gcc we clobber all non-fixed-usage registers except
@@ -196,24 +193,23 @@ do {	if (test_thread_flag(TIF_PERFCTR)) {				\
         "wrpr   %%g1, %%cwp\n\t"                                        \
         "ldx    [%%g6 + %3], %%o6\n\t"                                  \
         "ldub   [%%g6 + %2], %%o5\n\t"                                  \
-        "ldx    [%%g6 + %4], %%o7\n\t"                                  \
+        "ldub   [%%g6 + %4], %%o7\n\t"                                  \
         "mov    %%g6, %%l2\n\t"                                         \
         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
         "wrpr   %%g0, 0x94, %%pstate\n\t"                               \
         "mov    %%l2, %%g6\n\t"                                         \
-        "ldx    [%%g6 + %7], %%g4\n\t"                                  \
+        "ldx    [%%g6 + %6], %%g4\n\t"                                  \
         "wrpr   %%g0, 0x96, %%pstate\n\t"                               \
-        "andcc  %%o7, %6, %%g0\n\t"                                     \
-        "beq,pt %%icc, 1f\n\t"                                          \
+        "brz,pt %%o7, 1f\n\t"                                           \
         " mov   %%g7, %0\n\t"                                           \
         "b,a ret_from_syscall\n\t"                                      \
         "1:\n\t"                                                        \
         : "=&r" (last)                                                  \
         : "0" (next->thread_info),                                      \
-          "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP),  \
-          "i" (_TIF_NEWCHILD), "i" (TI_TASK)                            \
+          "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
+          "i" (TI_CWP), "i" (TI_TASK)                                   \
         : "cc",                                                         \
                 "g1", "g2", "g3",                   "g7",               \
                       "l2", "l3", "l4", "l5", "l6", "l7",               \
diff --git a/include/asm-sparc64/termios.h b/include/asm-sparc64/termios.h
index 8effce0da087..9777a9cca88a 100644
--- a/include/asm-sparc64/termios.h
+++ b/include/asm-sparc64/termios.h
@@ -100,16 +100,17 @@ struct winsize {
 #define user_termio_to_kernel_termios(termios, termio) \
 ({ \
         unsigned short tmp; \
-        get_user(tmp, &(termio)->c_iflag); \
+        int err; \
+        err = get_user(tmp, &(termio)->c_iflag); \
         (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
-        get_user(tmp, &(termio)->c_oflag); \
+        err |= get_user(tmp, &(termio)->c_oflag); \
         (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
-        get_user(tmp, &(termio)->c_cflag); \
+        err |= get_user(tmp, &(termio)->c_cflag); \
         (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
-        get_user(tmp, &(termio)->c_lflag); \
+        err |= get_user(tmp, &(termio)->c_lflag); \
         (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-        0; \
+        err |= copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+        err; \
 })
 
 /*
@@ -119,53 +120,56 @@ struct winsize {
  */
 #define kernel_termios_to_user_termio(termio, termios) \
 ({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+        int err; \
+        err  = put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        err |= put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        err |= put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        err |= put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        err |= put_user((termios)->c_line,  &(termio)->c_line); \
+        err |= copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
         if (!((termios)->c_lflag & ICANON)) { \
-                put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
-                put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
+                err |= put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
+                err |= put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
         } \
-        0; \
+        err; \
 })
 
 #define user_termios_to_kernel_termios(k, u) \
 ({ \
-        get_user((k)->c_iflag, &(u)->c_iflag); \
-        get_user((k)->c_oflag, &(u)->c_oflag); \
-        get_user((k)->c_cflag, &(u)->c_cflag); \
-        get_user((k)->c_lflag, &(u)->c_lflag); \
-        get_user((k)->c_line,  &(u)->c_line); \
-        copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
+        int err; \
+        err  = get_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= get_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= get_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= get_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= get_user((k)->c_line,  &(u)->c_line); \
+        err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
         if((k)->c_lflag & ICANON) { \
-                get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
-                get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+                err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
         } else { \
-                get_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
-                get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+                err |= get_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
         } \
-        0; \
+        err; \
 })
 
 #define kernel_termios_to_user_termios(u, k) \
 ({ \
-        put_user((k)->c_iflag, &(u)->c_iflag); \
-        put_user((k)->c_oflag, &(u)->c_oflag); \
-        put_user((k)->c_cflag, &(u)->c_cflag); \
-        put_user((k)->c_lflag, &(u)->c_lflag); \
-        put_user((k)->c_line, &(u)->c_line); \
-        copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
+        int err; \
+        err  = put_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= put_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= put_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= put_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= put_user((k)->c_line, &(u)->c_line); \
+        err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
         if(!((k)->c_lflag & ICANON)) { \
-                put_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
-                put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+                err |= put_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
         } else { \
-                put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
-                put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+                err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
         } \
-        0; \
+        err; \
 })
 
 #endif  /* __KERNEL__ */
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
index 517caaba1c87..c94d8b3991bd 100644
--- a/include/asm-sparc64/thread_info.h
+++ b/include/asm-sparc64/thread_info.h
@@ -46,8 +46,10 @@ struct thread_info {
         unsigned long           fault_address;
         struct pt_regs          *kregs;
         struct exec_domain      *exec_domain;
-        int                     preempt_count;
-        int                     __pad;
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
+        __u8                    new_child;
+        __u8                    syscall_noerror;
+        __u16                   __pad;
 
         unsigned long           *utraps;
 
@@ -66,6 +68,9 @@ struct thread_info {
 
         struct restart_block    restart_block;
 
+        struct pt_regs          *kern_una_regs;
+        unsigned int            kern_una_insn;
+
         unsigned long           fpregs[0] __attribute__ ((aligned(64)));
 };
 
@@ -87,6 +92,8 @@ struct thread_info {
 #define TI_KREGS        0x00000028
 #define TI_EXEC_DOMAIN  0x00000030
 #define TI_PRE_COUNT    0x00000038
+#define TI_NEW_CHILD    0x0000003c
+#define TI_SYS_NOERROR  0x0000003d
 #define TI_UTRAPS       0x00000040
 #define TI_REG_WINDOW   0x00000048
 #define TI_RWIN_SPTRS   0x000003c8      
@@ -99,6 +106,8 @@ struct thread_info {
 #define TI_PCR          0x00000490
 #define TI_CEE_STUFF    0x00000498
 #define TI_RESTART_BLOCK 0x000004a0
+#define TI_KUNA_REGS    0x000004c8
+#define TI_KUNA_INSN    0x000004d0
 #define TI_FPREGS       0x00000500
 
 /* We embed this in the uppermost byte of thread_info->flags */
@@ -219,16 +228,17 @@ register struct thread_info *current_thread_info_reg asm("g6");
 #define TIF_UNALIGNED           5       /* allowed to do unaligned accesses */
 #define TIF_NEWSIGNALS          6       /* wants new-style signals */
 #define TIF_32BIT               7       /* 32-bit binary */
-#define TIF_NEWCHILD            8       /* just-spawned child process */
-/* TIF_* value 9 is available */
-#define TIF_POLLING_NRFLAG      10
-#define TIF_SYSCALL_SUCCESS     11
+/* flag bit 8 is available */
+#define TIF_SECCOMP             9       /* secure computing */
+#define TIF_SYSCALL_AUDIT       10      /* syscall auditing active */
+/* flag bit 11 is available */
 /* NOTE: Thread flags >= 12 should be ones we have no interest
  *       in using in assembly, else we can't use the mask as
  *       an immediate value in instructions such as andcc.
  */
 #define TIF_ABI_PENDING         12
 #define TIF_MEMDIE              13
+#define TIF_POLLING_NRFLAG      14
 
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
@@ -238,10 +248,10 @@ register struct thread_info *current_thread_info_reg asm("g6");
 #define _TIF_UNALIGNED          (1<<TIF_UNALIGNED)
 #define _TIF_NEWSIGNALS         (1<<TIF_NEWSIGNALS)
 #define _TIF_32BIT              (1<<TIF_32BIT)
-#define _TIF_NEWCHILD           (1<<TIF_NEWCHILD)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
-#define _TIF_SYSCALL_SUCCESS    (1<<TIF_SYSCALL_SUCCESS)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 
 #define _TIF_USER_WORK_MASK     ((0xff << TI_FLAG_WSAVED_SHIFT) | \
                                  (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \
diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h
index ba33a2b6b7bd..edc8e08c3a39 100644
--- a/include/asm-sparc64/timer.h
+++ b/include/asm-sparc64/timer.h
@@ -9,49 +9,8 @@
 
 #include <linux/types.h>
 
-/* How timers work:
- *
- * On uniprocessors we just use counter zero for the system wide
- * ticker, this performs thread scheduling, clock book keeping,
- * and runs timer based events.  Previously we used the Ultra
- * %tick interrupt for this purpose.
- *
- * On multiprocessors we pick one cpu as the master level 10 tick
- * processor.  Here this counter zero tick handles clock book
- * keeping and timer events only.  Each Ultra has it's level
- * 14 %tick interrupt set to fire off as well, even the master
- * tick cpu runs this locally.  This ticker performs thread
- * scheduling, system/user tick counting for the current thread,
- * and also profiling if enabled.
- */
-
 #include <linux/config.h>
 
-/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
- * But since INO packets are used on sun5, we could use any PIL level
- * we like, however for now we use the normal ones.
- *
- * The 'reg' and 'interrupts' properties for these live in nodes named
- * 'counter-timer'.  The first of three 'reg' properties describe where
- * the sun5_timer registers are.  The other two I have no idea. (XXX)
- */
-struct sun5_timer {
-        u64     count0;
-        u64     limit0;
-        u64     count1;
-        u64     limit1;
-};
-
-#define SUN5_LIMIT_ENABLE       0x80000000
-#define SUN5_LIMIT_TOZERO       0x40000000
-#define SUN5_LIMIT_ZRESTART     0x20000000
-#define SUN5_LIMIT_CMASK        0x1fffffff
-
-/* Given a HZ value, set the limit register to so that the timer IRQ
- * gets delivered that often.
- */
-#define SUN5_HZ_TO_LIMIT(__hz)  (1000000/(__hz))
-
 struct sparc64_tick_ops {
         void (*init_tick)(unsigned long);
         unsigned long (*get_tick)(void);
diff --git a/include/asm-sparc64/types.h b/include/asm-sparc64/types.h
index 6248ed1a9a7a..d0ee7f105838 100644
--- a/include/asm-sparc64/types.h
+++ b/include/asm-sparc64/types.h
@@ -56,8 +56,6 @@ typedef unsigned long u64;
 typedef u32 dma_addr_t;
 typedef u64 dma64_addr_t;
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h
index 5690142f82de..80a65d7e3dbf 100644
--- a/include/asm-sparc64/uaccess.h
+++ b/include/asm-sparc64/uaccess.h
@@ -59,12 +59,6 @@ static inline int access_ok(int type, const void __user * addr, unsigned long si
         return 1;
 }
 
-/* this function will go away soon - use access_ok() instead */
-static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return 0;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h
index 5b8dcf5786a5..51ec2879b881 100644
--- a/include/asm-sparc64/unistd.h
+++ b/include/asm-sparc64/unistd.h
@@ -167,12 +167,12 @@
 #define __NR_pciconfig_read     148 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_write    149 /* ENOSYS under SunOS                          */
 #define __NR_getsockname        150 /* Common                                      */
-/* #define __NR_getmsg          151    SunOS Specific                              */
-/* #define __NR_putmsg          152    SunOS Specific                              */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
 #define __NR_poll               153 /* Common                                      */
 #define __NR_getdents64         154 /* Linux specific                              */
 /* #define __NR_fcntl64         155    Linux sparc32 Specific                      */
-/* #define __NR_getdirentries   156    SunOS Specific                              */
+#define __NR_inotify_rm_watch   156 /* Linux specific                              */
 #define __NR_statfs             157 /* Common                                      */
 #define __NR_fstatfs            158 /* Common                                      */
 #define __NR_umount             159 /* Common                                      */
@@ -212,7 +212,7 @@
 #define __NR_epoll_create       193 /* Linux Specific                              */
 #define __NR_epoll_ctl          194 /* Linux Specific                              */
 #define __NR_epoll_wait         195 /* Linux Specific                              */
-/* #define __NR_ulimit          196    Linux Specific                              */
+#define __NR_ioprio_set         196 /* Linux Specific                              */
 #define __NR_getppid            197 /* Linux Specific                              */
 #define __NR_sigaction          198 /* Linux Specific                              */
 #define __NR_sgetmask           199 /* Linux Specific                              */
@@ -234,7 +234,7 @@
 #define __NR_ipc                215 /* Linux Specific                              */
 #define __NR_sigreturn          216 /* Linux Specific                              */
 #define __NR_clone              217 /* Linux Specific                              */
-/* #define __NR_modify_ldt      218    Linux Specific - i386 specific, unused      */
+#define __NR_ioprio_get         218 /* Linux Specific                              */
 #define __NR_adjtimex           219 /* Linux Specific                              */
 #define __NR_sigprocmask        220 /* Linux Specific                              */
 #define __NR_create_module      221 /* Linux Specific                              */
diff --git a/include/asm-um/auxvec.h b/include/asm-um/auxvec.h
new file mode 100644
index 000000000000..1e5e1c2fc9b1
--- /dev/null
+++ b/include/asm-um/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __UM_AUXVEC_H
+#define __UM_AUXVEC_H
+
+#endif
diff --git a/include/asm-um/emergency-restart.h b/include/asm-um/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-um/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-um/futex.h b/include/asm-um/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-um/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-um/hdreg.h b/include/asm-um/hdreg.h
deleted file mode 100644
index cf6363abcab9..000000000000
--- a/include/asm-um/hdreg.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_HDREG_H
-#define __UM_HDREG_H
-
-#include "asm/arch/hdreg.h"
-
-#endif
diff --git a/include/asm-um/ldt.h b/include/asm-um/ldt.h
new file mode 100644
index 000000000000..e908439d338a
--- /dev/null
+++ b/include/asm-um/ldt.h
@@ -0,0 +1,5 @@
+#ifndef __UM_LDT_H
+#define __UM_LDT_H
+
+#include "asm/arch/ldt.h"
+#endif
diff --git a/include/asm-um/mmu_context.h b/include/asm-um/mmu_context.h
index 89bff310b7a9..2edb4f1f789c 100644
--- a/include/asm-um/mmu_context.h
+++ b/include/asm-um/mmu_context.h
@@ -7,19 +7,31 @@
 #define __UM_MMU_CONTEXT_H
 
 #include "linux/sched.h"
+#include "linux/config.h"
 #include "choose-mode.h"
+#include "um_mmu.h"
 
 #define get_mmu_context(task) do ; while(0)
 #define activate_context(tsk) do ; while(0)
 
 #define deactivate_mm(tsk,mm)   do { } while (0)
 
+extern void force_flush_all(void);
+
 static inline void activate_mm(struct mm_struct *old, struct mm_struct *new)
 {
+        /*
+         * This is called by fs/exec.c and fs/aio.c. In the first case, for an
+         * exec, we don't need to do anything as we're called from userspace
+         * and thus going to use a new host PID. In the second, we're called
+         * from a kernel thread, and thus need to go doing the mmap's on the
+         * host. Since they're very expensive, we want to avoid that as far as
+         * possible.
+         */
+        if (old != new && (current->flags & PF_BORROWED_MM))
+                force_flush_all();
 }
 
-extern void switch_mm_skas(int mm_fd);
-
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
                              struct task_struct *tsk)
 {
@@ -30,7 +42,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 cpu_set(cpu, next->cpu_vm_mask);
                 if(next != &init_mm)
                         CHOOSE_MODE((void) 0, 
-                                    switch_mm_skas(next->context.skas.mm_fd));
+                                    switch_mm_skas(&next->context.skas.id));
         }
 }
 
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
index 5afee8a8cdf3..bd850a249183 100644
--- a/include/asm-um/page.h
+++ b/include/asm-um/page.h
@@ -104,8 +104,8 @@ extern void *to_virt(unsigned long phys);
  * casting is the right thing, but 32-bit UML can't have 64-bit virtual
  * addresses
  */
-#define __pa(virt) to_phys((void *) (unsigned long) virt)
-#define __va(phys) to_virt((unsigned long) phys)
+#define __pa(virt) to_phys((void *) (unsigned long) (virt))
+#define __va(phys) to_virt((unsigned long) (phys))
 
 #define page_to_pfn(page) ((page) - mem_map)
 #define pfn_to_page(pfn) (mem_map + (pfn))
@@ -116,24 +116,12 @@ extern void *to_virt(unsigned long phys);
 #define pfn_valid(pfn) ((pfn) < max_mapnr)
 #define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v)))
 
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 extern struct page *arch_validate(struct page *page, int mask, int order);
 #define HAVE_ARCH_VALIDATE
 
 extern void arch_free_page(struct page *page, int order);
 #define HAVE_ARCH_FREE_PAGE
 
+#include <asm-generic/page.h>
+
 #endif
diff --git a/include/asm-um/pgalloc.h b/include/asm-um/pgalloc.h
index 8fcb2fc0a892..ea49411236dc 100644
--- a/include/asm-um/pgalloc.h
+++ b/include/asm-um/pgalloc.h
@@ -42,11 +42,13 @@ static inline void pte_free(struct page *pte)
 #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
 
 #ifdef CONFIG_3_LEVEL_PGTABLES
-/*
- * In the 3-level case we free the pmds as part of the pgd.
- */
-#define pmd_free(x)                     do { } while (0)
-#define __pmd_free_tlb(tlb,x)           do { } while (0)
+
+extern __inline__ void pmd_free(pmd_t *pmd)
+{
+        free_page((unsigned long)pmd);
+}
+
+#define __pmd_free_tlb(tlb,x)   tlb_remove_page((tlb),virt_to_page(x))
 #endif
 
 #define check_pgt_cache()       do { } while (0)
diff --git a/include/asm-um/pgtable-2level.h b/include/asm-um/pgtable-2level.h
index 9b3abc01d60e..ffe017f6b64b 100644
--- a/include/asm-um/pgtable-2level.h
+++ b/include/asm-um/pgtable-2level.h
@@ -35,35 +35,8 @@
 static inline int pgd_newpage(pgd_t pgd)        { return 0; }
 static inline void pgd_mkuptodate(pgd_t pgd)    { }
 
-#define pte_present(x)  (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-
-static inline pte_t pte_mknewprot(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_NEWPROT;
-        return(pte);
-}
-
-static inline pte_t pte_mknewpage(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_NEWPAGE;
-        return(pte);
-}
-
-static inline void set_pte(pte_t *pteptr, pte_t pteval)
-{
-        /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so
-         * fix_range knows to unmap it.  _PAGE_NEWPROT is specific to
-         * mapped pages.
-         */
-        *pteptr = pte_mknewpage(pteval);
-        if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr);
-}
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
 
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-#define pte_none(x) !(pte_val(x) & ~_PAGE_NEWPAGE)
 #define pte_pfn(x) phys_to_pfn(pte_val(x))
 #define pfn_pte(pfn, prot) __pte(pfn_to_phys(pfn) | pgprot_val(prot))
 #define pfn_pmd(pfn, prot) __pmd(pfn_to_phys(pfn) | pgprot_val(prot))
diff --git a/include/asm-um/pgtable-3level.h b/include/asm-um/pgtable-3level.h
index 65e8bfc55fc4..786c25727289 100644
--- a/include/asm-um/pgtable-3level.h
+++ b/include/asm-um/pgtable-3level.h
@@ -57,35 +57,6 @@ static inline int pgd_newpage(pgd_t pgd)
 
 static inline void pgd_mkuptodate(pgd_t pgd) { pgd_val(pgd) &= ~_PAGE_NEWPAGE; }
 
-
-#define pte_present(x)  pte_get_bits(x, (_PAGE_PRESENT | _PAGE_PROTNONE))
-
-static inline pte_t pte_mknewprot(pte_t pte)
-{
-        pte_set_bits(pte, _PAGE_NEWPROT);
-        return(pte);
-}
-
-static inline pte_t pte_mknewpage(pte_t pte)
-{
-        pte_set_bits(pte, _PAGE_NEWPAGE);
-        return(pte);
-}
-
-static inline void set_pte(pte_t *pteptr, pte_t pteval)
-{
-        pte_copy(*pteptr, pteval);
-
-        /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so
-         * fix_range knows to unmap it.  _PAGE_NEWPROT is specific to
-         * mapped pages.
-         */
-
-        *pteptr = pte_mknewpage(*pteptr);
-        if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr);
-}
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
 #define set_pmd(pmdptr, pmdval) set_64bit((phys_t *) (pmdptr), pmd_val(pmdval))
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
@@ -98,14 +69,11 @@ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
         return pmd;
 }
 
-static inline void pmd_free(pmd_t *pmd){
-        free_page((unsigned long) pmd);
+extern inline void pud_clear (pud_t *pud)
+{
+        set_pud(pud, __pud(0));
 }
 
-#define __pmd_free_tlb(tlb,x)   do { } while (0)
-
-static inline void pud_clear (pud_t * pud) { }
-
 #define pud_page(pud) \
         ((struct page *) __va(pud_val(pud) & PAGE_MASK))
 
@@ -113,13 +81,6 @@ static inline void pud_clear (pud_t * pud) { }
 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
                         pmd_index(address))
 
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-static inline int pte_none(pte_t pte)
-{
-        return pte_is_zero(pte);
-}
-
 static inline unsigned long pte_pfn(pte_t pte)
 {
         return phys_to_pfn(pte_val(pte));
diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h
index a88040920311..b48e0966ecd7 100644
--- a/include/asm-um/pgtable.h
+++ b/include/asm-um/pgtable.h
@@ -16,13 +16,15 @@
 
 #define _PAGE_PRESENT   0x001
 #define _PAGE_NEWPAGE   0x002
-#define _PAGE_NEWPROT   0x004
-#define _PAGE_FILE      0x008   /* set:pagecache unset:swap */
-#define _PAGE_PROTNONE  0x010   /* If not present */
+#define _PAGE_NEWPROT   0x004
 #define _PAGE_RW        0x020
 #define _PAGE_USER      0x040
 #define _PAGE_ACCESSED  0x080
 #define _PAGE_DIRTY     0x100
+/* If _PAGE_PRESENT is clear, we use these: */
+#define _PAGE_FILE      0x008   /* nonlinear file mapping, saved PTE; unset:swap */
+#define _PAGE_PROTNONE  0x010   /* if the user mapped it with PROT_NONE;
+                                   pte_present gives true */
 
 #ifdef CONFIG_3_LEVEL_PGTABLES
 #include "asm/pgtable-3level.h"
@@ -151,10 +153,24 @@ extern unsigned long pg0[1024];
 
 #define pmd_page(pmd) phys_to_page(pmd_val(pmd) & PAGE_MASK)
 
+#define pte_page(x) pfn_to_page(pte_pfn(x))
 #define pte_address(x) (__va(pte_val(x) & PAGE_MASK))
 #define mk_phys(a, r) ((a) + (((unsigned long) r) << REGION_SHIFT))
 #define phys_addr(p) ((p) & ~REGION_MASK)
 
+#define pte_present(x)  pte_get_bits(x, (_PAGE_PRESENT | _PAGE_PROTNONE))
+
+/*
+ * =================================
+ * Flags checking section.
+ * =================================
+ */
+
+static inline int pte_none(pte_t pte)
+{
+        return pte_is_zero(pte);
+}
+
 /*
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
@@ -210,6 +226,18 @@ static inline int pte_newprot(pte_t pte)
         return(pte_present(pte) && (pte_get_bits(pte, _PAGE_NEWPROT)));
 }
 
+/*
+ * =================================
+ * Flags setting section.
+ * =================================
+ */
+
+static inline pte_t pte_mknewprot(pte_t pte)
+{
+        pte_set_bits(pte, _PAGE_NEWPROT);
+        return(pte);
+}
+
 static inline pte_t pte_rdprotect(pte_t pte)
 { 
         pte_clear_bits(pte, _PAGE_USER);
@@ -278,6 +306,26 @@ static inline pte_t pte_mkuptodate(pte_t pte)
         return(pte); 
 }
 
+static inline pte_t pte_mknewpage(pte_t pte)
+{
+        pte_set_bits(pte, _PAGE_NEWPAGE);
+        return(pte);
+}
+
+static inline void set_pte(pte_t *pteptr, pte_t pteval)
+{
+        pte_copy(*pteptr, pteval);
+
+        /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so
+         * fix_range knows to unmap it.  _PAGE_NEWPROT is specific to
+         * mapped pages.
+         */
+
+        *pteptr = pte_mknewpage(*pteptr);
+        if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr);
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
 extern phys_t page_to_phys(struct page *page);
 
 /*
diff --git a/include/asm-um/ptrace-i386.h b/include/asm-um/ptrace-i386.h
index 04222f35c43e..fe882b9d917e 100644
--- a/include/asm-um/ptrace-i386.h
+++ b/include/asm-um/ptrace-i386.h
@@ -32,6 +32,10 @@
 #define PT_REGS_SYSCALL_RET(r) PT_REGS_EAX(r)
 #define PT_FIX_EXEC_STACK(sp) do ; while(0)
 
+/* Cope with a conditional i386 definition. */
+#undef profile_pc
+#define profile_pc(regs) PT_REGS_IP(regs)
+
 #define user_mode(r) UPT_IS_USER(&(r)->regs)
 
 #endif
diff --git a/include/asm-um/smp.h b/include/asm-um/smp.h
index 4412d5d9c26b..d879eba2b52c 100644
--- a/include/asm-um/smp.h
+++ b/include/asm-um/smp.h
@@ -8,7 +8,8 @@
 #include "asm/current.h"
 #include "linux/cpumask.h"
 
-#define smp_processor_id() (current_thread->cpu)
+#define raw_smp_processor_id() (current_thread->cpu)
+
 #define cpu_logical_map(n) (n)
 #define cpu_number_map(n) (n)
 #define PROC_CHANGE_PENALTY     15 /* Pick a number, any number */
diff --git a/include/asm-um/thread_info.h b/include/asm-um/thread_info.h
index 1feaaf148ef1..97267f059ef5 100644
--- a/include/asm-um/thread_info.h
+++ b/include/asm-um/thread_info.h
@@ -17,7 +17,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         __u32                   cpu;            /* current CPU */
-        __s32                   preempt_count;  /* 0 => preemptable, 
+        int                     preempt_count;  /* 0 => preemptable,
                                                    <0 => BUG */
         mm_segment_t            addr_limit;     /* thread address space:
                                                    0-0xBFFFFFFF for user
diff --git a/include/asm-um/vm86.h b/include/asm-um/vm86.h
new file mode 100644
index 000000000000..7801f82de1f4
--- /dev/null
+++ b/include/asm-um/vm86.h
@@ -0,0 +1,6 @@
+#ifndef __UM_VM86_H
+#define __UM_VM86_H
+
+#include "asm/arch/vm86.h"
+
+#endif
diff --git a/include/asm-v850/auxvec.h b/include/asm-v850/auxvec.h
new file mode 100644
index 000000000000..f493232d0224
--- /dev/null
+++ b/include/asm-v850/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __V850_AUXVEC_H__
+#define __V850_AUXVEC_H__
+
+#endif /* __V850_AUXVEC_H__ */
diff --git a/include/asm-v850/bitops.h b/include/asm-v850/bitops.h
index 7c4ecaf5151c..0e5c2f210872 100644
--- a/include/asm-v850/bitops.h
+++ b/include/asm-v850/bitops.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/bitops.h -- Bit operations
  *
- *  Copyright (C) 2001,02,03,04  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03,04  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,04,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,04,05  Miles Bader <miles@gnu.org>
  *  Copyright (C) 1992  Linus Torvalds.
  *
  * This file is subject to the terms and conditions of the GNU General
@@ -157,7 +157,7 @@ extern __inline__ int __test_bit (int nr, const void *addr)
 #define find_first_zero_bit(addr, size) \
   find_next_zero_bit ((addr), (size), 0)
 
-extern __inline__ int find_next_zero_bit (void *addr, int size, int offset)
+extern __inline__ int find_next_zero_bit(const void *addr, int size, int offset)
 {
         unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
         unsigned long result = offset & ~31UL;
diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h
index 027f8c9090cd..cbf9096e8517 100644
--- a/include/asm-v850/cache.h
+++ b/include/asm-v850/cache.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/cache.h -- Cache operations
  *
- *  Copyright (C) 2001  NEC Corporation
- *  Copyright (C) 2001  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,05  NEC Corporation
+ *  Copyright (C) 2001,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -20,6 +20,9 @@
 #ifndef L1_CACHE_BYTES
 /* This processor has no cache, so just choose an arbitrary value.  */
 #define L1_CACHE_BYTES          16
+#define L1_CACHE_SHIFT          4
 #endif
 
+#define L1_CACHE_SHIFT_MAX      L1_CACHE_SHIFT
+
 #endif /* __V850_CACHE_H__ */
diff --git a/include/asm-v850/checksum.h b/include/asm-v850/checksum.h
index d3aedb7bfc5c..4df5e71098f9 100644
--- a/include/asm-v850/checksum.h
+++ b/include/asm-v850/checksum.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/checksum.h -- Checksum ops
  *
- *  Copyright (C) 2001  NEC Corporation
- *  Copyright (C) 2001  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,2005  NEC Corporation
+ *  Copyright (C) 2001,2005  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -36,8 +36,8 @@ extern unsigned int csum_partial (const unsigned char * buff, int len,
  * here even more important to align src and dst on a 32-bit (or even
  * better 64-bit) boundary
  */
-extern unsigned csum_partial_copy (const char *src, char *dst, int len,
-                                   unsigned sum);
+extern unsigned csum_partial_copy (const unsigned char *src,
+                                   unsigned char *dst, int len, unsigned sum);
 
 
 /*
@@ -46,7 +46,8 @@ extern unsigned csum_partial_copy (const char *src, char *dst, int len,
  * here even more important to align src and dst on a 32-bit (or even
  * better 64-bit) boundary
  */
-extern unsigned csum_partial_copy_from_user (const char *src, char *dst,
+extern unsigned csum_partial_copy_from_user (const unsigned char *src,
+                                             unsigned char *dst,
                                              int len, unsigned sum,
                                              int *csum_err);
 
diff --git a/include/asm-v850/emergency-restart.h b/include/asm-v850/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-v850/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-v850/fcntl.h b/include/asm-v850/fcntl.h
index 31d4b5961221..3af4d56776dd 100644
--- a/include/asm-v850/fcntl.h
+++ b/include/asm-v850/fcntl.h
@@ -1,87 +1,11 @@
 #ifndef __V850_FCNTL_H__
 #define __V850_FCNTL_H__
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE         0003
-#define O_RDONLY            00
-#define O_WRONLY            01
-#define O_RDWR              02
-#define O_CREAT           0100  /* not fcntl */
-#define O_EXCL            0200  /* not fcntl */
-#define O_NOCTTY          0400  /* not fcntl */
-#define O_TRUNC          01000  /* not fcntl */
-#define O_APPEND         02000
-#define O_NONBLOCK       04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC          010000
-#define FASYNC          020000  /* fcntl, for BSD compatibility */
 #define O_DIRECTORY     040000  /* must be a directory */
 #define O_NOFOLLOW     0100000  /* don't follow links */
 #define O_DIRECT       0200000  /* direct disk access hint - currently ignored */
 #define O_LARGEFILE    0400000
-#define O_NOATIME       01000000
 
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
+#include <asm-generic/fcntl.h>
 
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-#define F_GETLK64       12      /*  using 'struct flock64' */
-#define F_SETLK64       13
-#define F_SETLKW64      14
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short l_type;
-        short l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t l_pid;
-};
-
-struct flock64 {
-        short  l_type;
-        short  l_whence;
-        loff_t l_start;
-        loff_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
 #endif /* __V850_FCNTL_H__ */
diff --git a/include/asm-v850/futex.h b/include/asm-v850/futex.h
new file mode 100644
index 000000000000..2cac5ecd9d00
--- /dev/null
+++ b/include/asm-v850/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-v850/io.h b/include/asm-v850/io.h
index bb5efd1b4b7d..cc364fcbec10 100644
--- a/include/asm-v850/io.h
+++ b/include/asm-v850/io.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/io.h -- Misc I/O operations
  *
- *  Copyright (C) 2001,02,03,04  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03,04  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,04,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,04,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -27,12 +27,12 @@
 #define readw_relaxed(a) readw(a)
 #define readl_relaxed(a) readl(a)
 
-#define writeb(b, addr) \
-  (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) \
-  (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) \
-  (void)((*(volatile unsigned int *) (addr)) = (b))
+#define writeb(val, addr) \
+  (void)((*(volatile unsigned char *) (addr)) = (val))
+#define writew(val, addr) \
+  (void)((*(volatile unsigned short *) (addr)) = (val))
+#define writel(val, addr) \
+  (void)((*(volatile unsigned int *) (addr)) = (val))
 
 #define __raw_readb readb
 #define __raw_readw readw
@@ -96,11 +96,22 @@ outsl (unsigned long port, const void *src, unsigned long count)
                 outl (*p++, port);
 }
 
-#define iounmap(addr)                           ((void)0)
-#define ioremap(physaddr, size)                 (physaddr)
-#define ioremap_nocache(physaddr, size)         (physaddr)
-#define ioremap_writethrough(physaddr, size)    (physaddr)
-#define ioremap_fullcache(physaddr, size)       (physaddr)
+
+/* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
+   long before casting it to a pointer to avoid compiler warnings.  */
+#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
+#define iounmap(addr)           ((void)0)
+
+#define ioremap_nocache(physaddr, size)         ioremap (physaddr, size)
+#define ioremap_writethrough(physaddr, size)    ioremap (physaddr, size)
+#define ioremap_fullcache(physaddr, size)       ioremap (physaddr, size)
+
+#define ioread8(addr)           readb (addr)
+#define ioread16(addr)          readw (addr)
+#define ioread32(addr)          readl (addr)
+#define iowrite8(val, addr)     writeb (val, addr)
+#define iowrite16(val, addr)    writew (val, addr)
+#define iowrite32(val, addr)    writel (val, addr)
 
 #define mmiowb()
 
diff --git a/include/asm-v850/mmu.h b/include/asm-v850/mmu.h
index e30a52becfd6..267768c66ef6 100644
--- a/include/asm-v850/mmu.h
+++ b/include/asm-v850/mmu.h
@@ -1,22 +1,11 @@
-/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
+/* Copyright (C) 2002, 2005, David McCullough <davidm@snapgear.com> */
 
 #ifndef __V850_MMU_H__
 #define __V850_MMU_H__
 
-struct mm_rblock_struct {
-        int             size;
-        int             refcount;
-        void    *kblock;
-};
-
-struct mm_tblock_struct {
-        struct mm_rblock_struct *rblock;
-        struct mm_tblock_struct *next;
-};
-
 typedef struct {
-        struct mm_tblock_struct tblock;
-        unsigned long                   end_brk;
+        struct vm_list_struct   *vmlist;
+        unsigned long           end_brk;
 } mm_context_t;
 
 #endif /* __V850_MMU_H__ */
diff --git a/include/asm-v850/page.h b/include/asm-v850/page.h
index 06085b0c043e..b4bc85e7b91a 100644
--- a/include/asm-v850/page.h
+++ b/include/asm-v850/page.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/page.h -- VM ops
  *
- *  Copyright (C) 2001,02,03  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -98,25 +98,6 @@ typedef unsigned long pgprot_t;
 #define PAGE_ALIGN(addr)        (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
 
 
-#ifndef __ASSEMBLY__
-
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order (unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-
 /* No current v850 processor has virtual memory.  */
 #define __virt_to_phys(addr)    (addr)
 #define __phys_to_virt(addr)    (addr)
@@ -132,6 +113,7 @@ extern __inline__ int get_order (unsigned long size)
 
 #define pfn_to_page(pfn)        virt_to_page (pfn_to_virt (pfn))
 #define page_to_pfn(page)       virt_to_pfn (page_to_virt (page))
+#define pfn_valid(pfn)          ((pfn) < max_mapnr)
 
 #define virt_addr_valid(kaddr)                                          \
   (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr)
@@ -143,4 +125,6 @@ extern __inline__ int get_order (unsigned long size)
 
 #endif /* KERNEL */
 
+#include <asm-generic/page.h>
+
 #endif /* __V850_PAGE_H__ */
diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h
index e41941447b49..4581826e1cac 100644
--- a/include/asm-v850/pci.h
+++ b/include/asm-v850/pci.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/pci.h -- PCI support
  *
- *  Copyright (C) 2001,02  NEC Corporation
- *  Copyright (C) 2001,02  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,05  NEC Corporation
+ *  Copyright (C) 2001,02,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -48,12 +48,12 @@ pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
    perform a pci_dma_sync_for_device, and then the device again owns
    the buffer.  */
 extern void
-pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, size_t size,
-                     int dir);
+pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr,
+                             size_t size, int dir);
 
 extern void
-pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, size_t size,
-                     int dir);
+pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr,
+                                size_t size, int dir);
 
 
 /* Do multiple DMA mappings at once.  */
@@ -65,6 +65,28 @@ extern void
 pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,
               int dir);
 
+/* SG-list versions of pci_dma_sync functions.  */
+extern void
+pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
+                         struct scatterlist *sg, int sg_len,
+                         int dir);
+extern void
+pci_dma_sync_sg_for_device (struct pci_dev *dev,
+                            struct scatterlist *sg, int sg_len,
+                            int dir);
+
+#define pci_map_page(dev, page, offs, size, dir) \
+  pci_map_single(dev, (page_address(page) + (offs)), size, dir)
+#define pci_unmap_page(dev,addr,sz,dir) \
+  pci_unmap_single(dev, addr, sz, dir)
+
+/* Test for pci_map_single or pci_map_page having generated an error.  */
+static inline int
+pci_dma_mapping_error (dma_addr_t dma_addr)
+{
+        return dma_addr == 0;
+}
+
 /* Allocate and map kernel buffer using consistent mode DMA for PCI
    device.  Returns non-NULL cpu-view pointer to the buffer if
    successful and sets *DMA_ADDR to the pci side dma address as well,
@@ -81,6 +103,19 @@ extern void
 pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
                      dma_addr_t dma_addr);
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-v850/pgtable.h b/include/asm-v850/pgtable.h
index 76e380e481e9..3cf8775ce85f 100644
--- a/include/asm-v850/pgtable.h
+++ b/include/asm-v850/pgtable.h
@@ -23,6 +23,8 @@
 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 
+static inline int pte_file (pte_t pte) { return 0; }
+
 
 /* These mean nothing to !CONFIG_MMU.  */
 #define PAGE_NONE               __pgprot(0)
diff --git a/include/asm-v850/socket.h b/include/asm-v850/socket.h
index 213b852af53e..0240d366a0a4 100644
--- a/include/asm-v850/socket.h
+++ b/include/asm-v850/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-v850/thread_info.h b/include/asm-v850/thread_info.h
index e2ef44593752..e4cfad94a553 100644
--- a/include/asm-v850/thread_info.h
+++ b/include/asm-v850/thread_info.h
@@ -30,7 +30,8 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
         int                     cpu;            /* cpu we're on */
-        int                     preempt_count;
+        int                     preempt_count;  /* 0 => preemptable,
+                                                   <0 => BUG */
         struct restart_block    restart_block;
 };
 
diff --git a/include/asm-v850/types.h b/include/asm-v850/types.h
index e7cfe5b33a10..dcef57196875 100644
--- a/include/asm-v850/types.h
+++ b/include/asm-v850/types.h
@@ -59,8 +59,6 @@ typedef unsigned long long u64;
 
 typedef u32 dma_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-v850/uaccess.h b/include/asm-v850/uaccess.h
index 4386cfc6a8dd..188b28597cf1 100644
--- a/include/asm-v850/uaccess.h
+++ b/include/asm-v850/uaccess.h
@@ -27,12 +27,6 @@ extern inline int access_ok (int type, const void *addr, unsigned long size)
         return val >= (0x80 + NUM_CPU_IRQS*16) && val < 0xFFFFF000;
 }
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area (int type, const void *addr, unsigned long size)
-{
-        return access_ok (type, addr, size) ? 0 : -EFAULT;
-}
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-v850/v850e2_cache.h b/include/asm-v850/v850e2_cache.h
index 61acda1023e8..87edf0d311d5 100644
--- a/include/asm-v850/v850e2_cache.h
+++ b/include/asm-v850/v850e2_cache.h
@@ -2,8 +2,8 @@
  * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
  *      cache memories
  *
- *  Copyright (C) 2003  NEC Electronics Corporation
- *  Copyright (C) 2003  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2003,05  NEC Electronics Corporation
+ *  Copyright (C) 2003,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -69,6 +69,7 @@
 
 /* For <asm/cache.h> */
 #define L1_CACHE_BYTES                  V850E2_CACHE_LINE_SIZE
+#define L1_CACHE_SHIFT                  V850E2_CACHE_LINE_SIZE_BITS
 
 
 #endif /* __V850_V850E2_CACHE_H__ */
diff --git a/include/asm-x86_64/a.out.h b/include/asm-x86_64/a.out.h
index 5952914f4121..7255cde06538 100644
--- a/include/asm-x86_64/a.out.h
+++ b/include/asm-x86_64/a.out.h
@@ -21,7 +21,7 @@ struct exec
 
 #ifdef __KERNEL__
 #include <linux/thread_info.h>
-#define STACK_TOP (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE)
+#define STACK_TOP TASK_SIZE
 #endif
 
 #endif /* __A_OUT_GNU_H__ */
diff --git a/include/asm-x86_64/acpi.h b/include/asm-x86_64/acpi.h
index a6b41b892062..aa1c7b2e438c 100644
--- a/include/asm-x86_64/acpi.h
+++ b/include/asm-x86_64/acpi.h
@@ -28,6 +28,8 @@
 
 #ifdef __KERNEL__
 
+#include <acpi/pdc_intel.h>
+
 #define COMPILER_DEPENDENT_INT64   long long
 #define COMPILER_DEPENDENT_UINT64  unsigned long long
 
@@ -99,13 +101,7 @@ __acpi_release_global_lock (unsigned int *lock)
         :"=r"(n_hi), "=r"(n_lo)     \
         :"0"(n_hi), "1"(n_lo))
 
-/*
- * Refer Intel ACPI _PDC support document for bit definitions
- */
-#define ACPI_PDC_EST_CAPABILITY_SMP     0xa
-#define ACPI_PDC_EST_CAPABILITY_MSR     0x1
-
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 extern int acpi_lapic;
 extern int acpi_ioapic;
 extern int acpi_noirq;
@@ -125,17 +121,6 @@ static inline void disable_acpi(void)
 #define FIX_ACPI_PAGES 4
 
 extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
-
-#else   /* !CONFIG_ACPI_BOOT */
-#define acpi_lapic 0
-#define acpi_ioapic 0
-#endif /* !CONFIG_ACPI_BOOT */
-
-extern int acpi_numa;
-extern int acpi_scan_nodes(unsigned long start, unsigned long end);
-#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
-
-#ifdef CONFIG_ACPI_PCI
 static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
 static inline void acpi_disable_pci(void) 
 {
@@ -143,11 +128,19 @@ static inline void acpi_disable_pci(void)
         acpi_noirq_set();
 }
 extern int acpi_irq_balance_set(char *str);
-#else
+
+#else   /* !CONFIG_ACPI */
+
+#define acpi_lapic 0
+#define acpi_ioapic 0
 static inline void acpi_noirq_set(void) { }
 static inline void acpi_disable_pci(void) { }
-static inline int acpi_irq_balance_set(char *str) { return 0; }
-#endif
+
+#endif /* !CONFIG_ACPI */
+
+extern int acpi_numa;
+extern int acpi_scan_nodes(unsigned long start, unsigned long end);
+#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
 
 #ifdef CONFIG_ACPI_SLEEP
 
diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h
index e4b1017b8b2b..16ec82e16b21 100644
--- a/include/asm-x86_64/apic.h
+++ b/include/asm-x86_64/apic.h
@@ -77,7 +77,7 @@ static inline void ack_APIC_irq(void)
 extern int get_maxlvt (void);
 extern void clear_local_APIC (void);
 extern void connect_bsp_APIC (void);
-extern void disconnect_bsp_APIC (void);
+extern void disconnect_bsp_APIC (int virt_wire_setup);
 extern void disable_local_APIC (void);
 extern int verify_local_APIC (void);
 extern void cache_APIC_registers (void);
diff --git a/include/asm-x86_64/apicdef.h b/include/asm-x86_64/apicdef.h
index bfebdb690654..9388062c4f6e 100644
--- a/include/asm-x86_64/apicdef.h
+++ b/include/asm-x86_64/apicdef.h
@@ -94,7 +94,7 @@
 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
 #define                         APIC_MODE_FIXED         0x0
 #define                         APIC_MODE_NMI           0x4
-#define                         APIC_MODE_EXINT         0x7
+#define                         APIC_MODE_EXTINT        0x7
 #define         APIC_LVT1       0x360
 #define         APIC_LVTERR     0x370
 #define         APIC_TMICT      0x380
diff --git a/include/asm-x86_64/auxvec.h b/include/asm-x86_64/auxvec.h
new file mode 100644
index 000000000000..2403c4cfced2
--- /dev/null
+++ b/include/asm-x86_64/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_X86_64_AUXVEC_H
+#define __ASM_X86_64_AUXVEC_H
+
+#endif
diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86_64/bitops.h
index 5dd7727c756b..05a0d374404b 100644
--- a/include/asm-x86_64/bitops.h
+++ b/include/asm-x86_64/bitops.h
@@ -348,8 +348,7 @@ static inline int sched_find_first_bit(const unsigned long *b)
                 return __ffs(b[0]);
         if (b[1])
                 return __ffs(b[1]) + 64;
-        if (b[2])
-                return __ffs(b[2]) + 128;
+        return __ffs(b[2]) + 128;
 }
 
 /**
@@ -411,8 +410,6 @@ static __inline__ int ffs(int x)
 /* find last set bit */
 #define fls(x) generic_fls(x)
 
-#define ARCH_HAS_ATOMIC_UNSIGNED 1
-
 #endif /* __KERNEL__ */
 
 #endif /* _X86_64_BITOPS_H */
diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h
index 3d2a666a5dd5..eed785667289 100644
--- a/include/asm-x86_64/bug.h
+++ b/include/asm-x86_64/bug.h
@@ -8,17 +8,24 @@
  * this frame.
  */
 struct bug_frame {
-       unsigned char ud2[2];
+        unsigned char ud2[2];
+        unsigned char mov;
         /* should use 32bit offset instead, but the assembler doesn't 
            like it */
         char *filename;
+        unsigned char ret;
         unsigned short line;
 } __attribute__((packed));
 
 #ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
-#define BUG() \
-        asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \
+/* We turn the bug frame into valid instructions to not confuse
+   the disassembler. Thanks to Jan Beulich & Suresh Siddha
+   for nice instruction selection.
+   The magic numbers generate mov $64bitimm,%eax ; ret $offset. */
+#define BUG()                                                           \
+        asm volatile(                                                   \
+        "ud2 ; .byte 0xa3 ; .quad %c1 ; .byte 0xc2 ; .short %c0" ::     \
                      "i"(__LINE__), "i" (__stringify(__FILE__)))
 void out_of_line_bug(void);
 #else
diff --git a/include/asm-x86_64/checksum.h b/include/asm-x86_64/checksum.h
index d01356f01448..989469e8e0b7 100644
--- a/include/asm-x86_64/checksum.h
+++ b/include/asm-x86_64/checksum.h
@@ -64,7 +64,7 @@ static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl)
                 "  adcl $0, %0\n"
                 "  notl %0\n"
                 "2:"
-        /* Since the input registers which are loaded with iph and ipl
+        /* Since the input registers which are loaded with iph and ihl
            are modified, we must also specify them as outputs, or gcc
            will assume they contain their original values. */
         : "=r" (sum), "=r" (iph), "=r" (ihl)
diff --git a/include/asm-x86_64/compat.h b/include/asm-x86_64/compat.h
index d0f453c5adfc..f0155c38f639 100644
--- a/include/asm-x86_64/compat.h
+++ b/include/asm-x86_64/compat.h
@@ -14,10 +14,10 @@ typedef s32		compat_ssize_t;
 typedef s32             compat_time_t;
 typedef s32             compat_clock_t;
 typedef s32             compat_pid_t;
-typedef u16             compat_uid_t;
-typedef u16             compat_gid_t;
-typedef u32             compat_uid32_t;
-typedef u32             compat_gid32_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u16             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u16             compat_dev_t;
@@ -52,8 +52,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
         compat_dev_t    st_rdev;
         u16             __pad2;
         u32             st_size;
@@ -122,10 +122,10 @@ typedef u32               compat_sigset_word;
 
 struct compat_ipc64_perm {
         compat_key_t key;
-        compat_uid32_t uid;
-        compat_gid32_t gid;
-        compat_uid32_t cuid;
-        compat_gid32_t cgid;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
         unsigned short mode;
         unsigned short __pad1;
         unsigned short seq;
diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h
index 6aefb9c0280d..c89b58bebee2 100644
--- a/include/asm-x86_64/desc.h
+++ b/include/asm-x86_64/desc.h
@@ -75,6 +75,7 @@ struct desc_ptr {
  */
 extern struct desc_struct default_ldt[];
 extern struct gate_struct idt_table[]; 
+extern struct desc_ptr cpu_gdt_descr[];
 
 static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist)  
 {
diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h
index 8e94edf0b984..e682edc24a68 100644
--- a/include/asm-x86_64/e820.h
+++ b/include/asm-x86_64/e820.h
@@ -51,6 +51,8 @@ extern int e820_mapped(unsigned long start, unsigned long end, unsigned type);
 
 extern void e820_bootmem_free(pg_data_t *pgdat, unsigned long start,unsigned long end);
 extern void e820_setup_gap(void);
+extern unsigned long e820_hole_size(unsigned long start_pfn,
+                                    unsigned long end_pfn);
 
 extern void __init parse_memopt(char *p, char **end);
 
diff --git a/include/asm-x86_64/emergency-restart.h b/include/asm-x86_64/emergency-restart.h
new file mode 100644
index 000000000000..680c39563345
--- /dev/null
+++ b/include/asm-x86_64/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+extern void machine_emergency_restart(void);
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-x86_64/fcntl.h b/include/asm-x86_64/fcntl.h
index 4411f221c037..46ab12db5739 100644
--- a/include/asm-x86_64/fcntl.h
+++ b/include/asm-x86_64/fcntl.h
@@ -1,76 +1 @@
-#ifndef _X86_64_FCNTL_H
-#define _X86_64_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE          0003
-#define O_RDONLY             00
-#define O_WRONLY             01
-#define O_RDWR               02
-#define O_CREAT            0100 /* not fcntl */
-#define O_EXCL             0200 /* not fcntl */
-#define O_NOCTTY           0400 /* not fcntl */
-#define O_TRUNC           01000 /* not fcntl */
-#define O_APPEND          02000
-#define O_NONBLOCK        04000
-#define O_NDELAY        O_NONBLOCK
-#define O_SYNC           010000
-#define FASYNC           020000 /* fcntl, for BSD compatibility */
-#define O_DIRECT         040000 /* direct disk access hint */
-#define O_LARGEFILE     0100000
-#define O_DIRECTORY     0200000 /* must be a directory */
-#define O_NOFOLLOW      0400000 /* don't follow links */
-#define O_NOATIME       01000000
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
-#define F_GETLK         5
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        8       /*  for sockets. */
-#define F_GETOWN        9       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
-struct flock {
-        short  l_type;
-        short  l_whence;
-        off_t l_start;
-        off_t l_len;
-        pid_t  l_pid;
-};
-
-#define F_LINUX_SPECIFIC_BASE   1024
-
-#endif /* !_X86_64_FCNTL_H */
+#include <asm-generic/fcntl.h>
diff --git a/include/asm-x86_64/futex.h b/include/asm-x86_64/futex.h
new file mode 100644
index 000000000000..8602c09bf89e
--- /dev/null
+++ b/include/asm-x86_64/futex.h
@@ -0,0 +1,98 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
+#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile (                                          \
+"1:     " insn "\n"                                             \
+"2:     .section .fixup,\"ax\"\n\
+3:      mov     %3, %1\n\
+        jmp     2b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align  8\n\
+        .quad   1b,3b\n\
+        .previous"                                              \
+        : "=r" (oldval), "=r" (ret), "=m" (*uaddr)              \
+        : "i" (-EFAULT), "m" (*uaddr), "0" (oparg), "1" (0))
+
+#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile (                                          \
+"1:     movl    %2, %0\n\
+        movl    %0, %3\n"                                       \
+        insn "\n"                                               \
+"2:     " LOCK_PREFIX "cmpxchgl %3, %2\n\
+        jnz     1b\n\
+3:      .section .fixup,\"ax\"\n\
+4:      mov     %5, %1\n\
+        jmp     3b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align  8\n\
+        .quad   1b,4b,2b,4b\n\
+        .previous"                                              \
+        : "=&a" (oldval), "=&r" (ret), "=m" (*uaddr),           \
+          "=&r" (tem)                                           \
+        : "r" (oparg), "i" (-EFAULT), "m" (*uaddr), "1" (0))
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret, oldval,
+                                   uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op2("orl %4, %3", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op2("andl %4, %3", ret, oldval, uaddr, ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op2("xorl %4, %3", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-x86_64/hdreg.h b/include/asm-x86_64/hdreg.h
deleted file mode 100644
index 5989bbc97cbf..000000000000
--- a/include/asm-x86_64/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#warning this file is obsolete, please do not use it
diff --git a/include/asm-x86_64/ia32.h b/include/asm-x86_64/ia32.h
index c0a7717923ed..6efa00fe4e7b 100644
--- a/include/asm-x86_64/ia32.h
+++ b/include/asm-x86_64/ia32.h
@@ -94,7 +94,7 @@ typedef struct compat_siginfo{
 
                 /* POSIX.1b timers */
                 struct {
-                        int _tid;               /* timer id */
+                        compat_timer_t _tid;    /* timer id */
                         int _overrun;           /* overrun count */
                         compat_sigval_t _sigval;        /* same as below */
                         int _sys_private;       /* not to be passed to user */
diff --git a/include/asm-x86_64/ia32_unistd.h b/include/asm-x86_64/ia32_unistd.h
index f3b7111cf33d..d5166ec3868d 100644
--- a/include/asm-x86_64/ia32_unistd.h
+++ b/include/asm-x86_64/ia32_unistd.h
@@ -294,7 +294,12 @@
 #define __NR_ia32_add_key               286
 #define __NR_ia32_request_key   287
 #define __NR_ia32_keyctl                288
+#define __NR_ia32_ioprio_set            289
+#define __NR_ia32_ioprio_get            290
+#define __NR_ia32_inotify_init          291
+#define __NR_ia32_inotify_add_watch     292
+#define __NR_ia32_inotify_rm_watch      293
 
-#define IA32_NR_syscalls 290    /* must be > than biggest syscall! */
+#define IA32_NR_syscalls 294    /* must be > than biggest syscall! */
 
 #endif /* _ASM_X86_64_IA32_UNISTD_H_ */
diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h
index 94202703fae2..37fc3f149a5a 100644
--- a/include/asm-x86_64/io.h
+++ b/include/asm-x86_64/io.h
@@ -124,12 +124,7 @@ extern inline void * phys_to_virt(unsigned long address)
 /*
  * Change "struct page" to physical address.
  */
-#ifdef CONFIG_DISCONTIGMEM
-#include <asm/mmzone.h>
 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-#else
-#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
-#endif
 
 #include <asm-generic/iomap.h>
 
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 32573749004c..ee1bc69aec9c 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -201,7 +201,7 @@ extern int skip_ioapic_setup;
  */
 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 extern int io_apic_get_version (int ioapic);
 extern int io_apic_get_redir_entries (int ioapic);
 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
@@ -217,4 +217,6 @@ extern int assign_irq_vector(int irq);
 
 void enable_NMI_through_LVT0 (void * dummy);
 
+extern spinlock_t i8259A_lock;
+
 #endif
diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86_64/ipi.h
index d1841847ed89..5e166b9d3bde 100644
--- a/include/asm-x86_64/ipi.h
+++ b/include/asm-x86_64/ipi.h
@@ -82,30 +82,27 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
          */
         local_irq_save(flags);
 
-        for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
-                if (cpu_isset(query_cpu, mask)) {
-
-                        /*
-                         * Wait for idle.
-                         */
-                        apic_wait_icr_idle();
-
-                        /*
-                         * prepare target chip field
-                         */
-                        cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
-                        apic_write_around(APIC_ICR2, cfg);
-
-                        /*
-                         * program the ICR
-                         */
-                        cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
-
-                        /*
-                         * Send the IPI. The write to APIC_ICR fires this off.
-                         */
-                        apic_write_around(APIC_ICR, cfg);
-                }
+        for_each_cpu_mask(query_cpu, mask) {
+                /*
+                 * Wait for idle.
+                 */
+                apic_wait_icr_idle();
+
+                /*
+                 * prepare target chip field
+                 */
+                cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
+                apic_write_around(APIC_ICR2, cfg);
+
+                /*
+                 * program the ICR
+                 */
+                cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
+
+                /*
+                 * Send the IPI. The write to APIC_ICR fires this off.
+                 */
+                apic_write_around(APIC_ICR, cfg);
         }
         local_irq_restore(flags);
 }
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index 3af50b3c3b05..4482657777bb 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -52,4 +52,11 @@ struct irqaction;
 struct pt_regs;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 
+#ifdef CONFIG_HOTPLUG_CPU
+#include <linux/cpumask.h>
+extern void fixup_irqs(cpumask_t map);
+#endif
+
+#define __ARCH_HAS_DO_SOFTIRQ 1
+
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86_64/kdebug.h b/include/asm-x86_64/kdebug.h
index 6277f75cbb4b..b90341994d80 100644
--- a/include/asm-x86_64/kdebug.h
+++ b/include/asm-x86_64/kdebug.h
@@ -14,7 +14,7 @@ struct die_args {
 }; 
 
 /* Note - you should never unregister because that can race with NMIs.
-   If you really want to do it first unregister - then synchronize_kernel - then free. 
+   If you really want to do it first unregister - then synchronize_sched - then free.
   */
 int register_die_notifier(struct notifier_block *nb);
 extern struct notifier_block *die_chain;
diff --git a/include/asm-x86_64/kexec.h b/include/asm-x86_64/kexec.h
new file mode 100644
index 000000000000..42d2ff15c592
--- /dev/null
+++ b/include/asm-x86_64/kexec.h
@@ -0,0 +1,33 @@
+#ifndef _X86_64_KEXEC_H
+#define _X86_64_KEXEC_H
+
+#include <asm/page.h>
+#include <asm/proto.h>
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * So far x86_64 is limited to 40 physical address bits.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT      (0xFFFFFFFFFFUL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (0xFFFFFFFFFFUL)
+/* Maximum address we can use for the control pages */
+#define KEXEC_CONTROL_MEMORY_LIMIT     (0xFFFFFFFFFFUL)
+
+/* Allocate one page for the pdp and the second for the code */
+#define KEXEC_CONTROL_CODE_SIZE  (4096UL + 4096UL)
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_X86_64
+
+#define MAX_NOTE_BYTES 1024
+typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
+
+extern note_buf_t crash_notes[];
+
+#endif /* _X86_64_KEXEC_H */
diff --git a/include/asm-x86_64/kprobes.h b/include/asm-x86_64/kprobes.h
index bfea52d516f8..6d6d883fdf6d 100644
--- a/include/asm-x86_64/kprobes.h
+++ b/include/asm-x86_64/kprobes.h
@@ -38,6 +38,9 @@ typedef u8 kprobe_opcode_t;
         : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
 
 #define JPROBE_ENTRY(pentry)    (kprobe_opcode_t *)pentry
+#define ARCH_SUPPORTS_KRETPROBES
+
+void kretprobe_trampoline(void);
 
 /* Architecture specific copy of original instruction*/
 struct arch_specific_insn {
diff --git a/include/asm-x86_64/mmzone.h b/include/asm-x86_64/mmzone.h
index d95b7c240831..768413751b34 100644
--- a/include/asm-x86_64/mmzone.h
+++ b/include/asm-x86_64/mmzone.h
@@ -6,7 +6,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 
 #define VIRTUAL_BUG_ON(x) 
 
@@ -30,27 +30,23 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
         return nid; 
 } 
 
-#define pfn_to_nid(pfn) phys_to_nid((unsigned long)(pfn) << PAGE_SHIFT)
-
-#define kvaddr_to_nid(kaddr)    phys_to_nid(__pa(kaddr))
 #define NODE_DATA(nid)          (node_data[nid])
 
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
-
-#define node_mem_map(nid)       (NODE_DATA(nid)->node_mem_map)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn + \
                                  NODE_DATA(nid)->node_spanned_pages)
 
-#define local_mapnr(kvaddr) \
-        ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) )
+#ifdef CONFIG_DISCONTIGMEM
+
+#define pfn_to_nid(pfn) phys_to_nid((unsigned long)(pfn) << PAGE_SHIFT)
+#define kvaddr_to_nid(kaddr)    phys_to_nid(__pa(kaddr))
 
 /* AK: this currently doesn't deal with invalid addresses. We'll see 
    if the 2.5 kernel doesn't pass them
    (2.4 used to). */
 #define pfn_to_page(pfn) ({ \
         int nid = phys_to_nid(((unsigned long)(pfn)) << PAGE_SHIFT);    \
-        ((pfn) - node_start_pfn(nid)) + node_mem_map(nid);              \
+        ((pfn) - node_start_pfn(nid)) + NODE_DATA(nid)->node_mem_map;   \
 })
 
 #define page_to_pfn(page) \
@@ -60,4 +56,8 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
                         ({ u8 nid__ = pfn_to_nid(pfn); \
                            nid__ != 0xff && (pfn) >= node_start_pfn(nid__) && (pfn) <= node_end_pfn(nid__); }))
 #endif
+
+#define local_mapnr(kvaddr) \
+        ( (__pa(kvaddr) >> PAGE_SHIFT) - node_start_pfn(kvaddr_to_nid(kvaddr)) )
+#endif
 #endif
diff --git a/include/asm-x86_64/mpspec.h b/include/asm-x86_64/mpspec.h
index 331f6a3c72a2..f267e10c023d 100644
--- a/include/asm-x86_64/mpspec.h
+++ b/include/asm-x86_64/mpspec.h
@@ -179,7 +179,7 @@ extern int mpc_default_type;
 extern unsigned long mp_lapic_addr;
 extern int pic_mode;
 
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 extern void mp_register_lapic (u8 id, u8 enabled);
 extern void mp_register_lapic_address (u64 address);
 
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index 513e52c71821..ba15279a79d0 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -57,11 +57,6 @@
      (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
 } while(0)
 
-#define rdpmc(counter,low,high) \
-     __asm__ __volatile__("rdpmc" \
-                          : "=a" (low), "=d" (high) \
-                          : "c" (counter))
-
 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
 
 #define rdpmc(counter,low,high) \
@@ -223,7 +218,7 @@ extern inline unsigned int cpuid_edx(unsigned int op)
 #define MSR_K7_PERFCTR3            0xC0010007
 #define MSR_K8_TOP_MEM1            0xC001001A
 #define MSR_K8_TOP_MEM2            0xC001001D
-#define MSR_K8_SYSCFG              0xC0000010   
+#define MSR_K8_SYSCFG              0xC0010010
 
 /* K6 MSRs */
 #define MSR_K6_EFER                     0xC0000080
diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h
index f43048035a03..135ffaa0393b 100644
--- a/include/asm-x86_64/page.h
+++ b/include/asm-x86_64/page.h
@@ -63,12 +63,14 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define __pgd(x) ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-#define __START_KERNEL          0xffffffff80100000UL
+#define __PHYSICAL_START        ((unsigned long)CONFIG_PHYSICAL_START)
+#define __START_KERNEL          (__START_KERNEL_map + __PHYSICAL_START)
 #define __START_KERNEL_map      0xffffffff80000000UL
 #define __PAGE_OFFSET           0xffff810000000000UL
 
 #else
-#define __START_KERNEL          0xffffffff80100000
+#define __PHYSICAL_START        CONFIG_PHYSICAL_START
+#define __START_KERNEL          (__START_KERNEL_map + __PHYSICAL_START)
 #define __START_KERNEL_map      0xffffffff80000000
 #define __PAGE_OFFSET           0xffff810000000000
 #endif /* !__ASSEMBLY__ */
@@ -89,20 +91,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 #include <asm/bug.h>
 
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #endif /* __ASSEMBLY__ */
 
 #define PAGE_OFFSET             ((unsigned long)__PAGE_OFFSET)
@@ -118,7 +106,9 @@ extern __inline__ int get_order(unsigned long size)
           __pa(v); })
 
 #define __va(x)                 ((void *)((unsigned long)(x)+PAGE_OFFSET))
-#ifndef CONFIG_DISCONTIGMEM
+#define __boot_va(x)            __va(x)
+#define __boot_pa(x)            __pa(x)
+#ifdef CONFIG_FLATMEM
 #define pfn_to_page(pfn)        (mem_map + (pfn))
 #define page_to_pfn(page)       ((unsigned long)((page) - mem_map))
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
@@ -136,4 +126,6 @@ extern __inline__ int get_order(unsigned long size)
 
 #endif /* __KERNEL__ */
 
+#include <asm-generic/page.h>
+
 #endif /* _X86_64_PAGE_H */
diff --git a/include/asm-x86_64/param.h b/include/asm-x86_64/param.h
index b707f0568c9e..40b11937180d 100644
--- a/include/asm-x86_64/param.h
+++ b/include/asm-x86_64/param.h
@@ -1,9 +1,11 @@
+#include <linux/config.h>
+
 #ifndef _ASMx86_64_PARAM_H
 #define _ASMx86_64_PARAM_H
 
 #ifdef __KERNEL__
-# define HZ            1000            /* Internal kernel timer frequency */
-# define USER_HZ       100          /* .. some user interfaces are in "ticks */
+# define HZ            CONFIG_HZ        /* Internal kernel timer frequency */
+# define USER_HZ       100              /* .. some user interfaces are in "ticks */
 #define CLOCKS_PER_SEC        (USER_HZ)       /* like times() */
 #endif
 
diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h
index 8712520ca47f..eeb3088a1c9e 100644
--- a/include/asm-x86_64/pci.h
+++ b/include/asm-x86_64/pci.h
@@ -33,7 +33,7 @@ extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int le
 extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
 
 void pcibios_set_master(struct pci_dev *dev);
-void pcibios_penalize_isa_irq(int irq);
+void pcibios_penalize_isa_irq(int irq, int active);
 struct irq_routing_table *pcibios_get_irq_routing_table(void);
 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
 
@@ -123,6 +123,16 @@ pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
         flush_write_buffers();
 }
 
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
 #define HAVE_PCI_MMAP
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
diff --git a/include/asm-x86_64/percpu.h b/include/asm-x86_64/percpu.h
index 415d73f3c8ef..9c71855736fb 100644
--- a/include/asm-x86_64/percpu.h
+++ b/include/asm-x86_64/percpu.h
@@ -39,7 +39,7 @@ extern void setup_per_cpu_areas(void);
 #define DEFINE_PER_CPU(type, name) \
     __typeof__(type) per_cpu__##name
 
-#define per_cpu(var, cpu)                       (*((void)cpu, &per_cpu__##var))
+#define per_cpu(var, cpu)                       (*((void)(cpu), &per_cpu__##var))
 #define __get_cpu_var(var)                      per_cpu__##var
 
 #endif  /* SMP */
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index db2a0efbf573..5e0f2fdab0d3 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -104,6 +104,19 @@ extern inline void pgd_clear (pgd_t * pgd)
 ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK))
 
 #define ptep_get_and_clear(mm,addr,xp)  __pte(xchg(&(xp)->pte, 0))
+
+static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
+{
+        pte_t pte;
+        if (full) {
+                pte = *ptep;
+                *ptep = __pte(0);
+        } else {
+                pte = ptep_get_and_clear(mm, addr, ptep);
+        }
+        return pte;
+}
+
 #define pte_same(a, b)          ((a).pte == (b).pte)
 
 #define PMD_SIZE        (1UL << PMD_SHIFT)
@@ -143,7 +156,7 @@ extern inline void pgd_clear (pgd_t * pgd)
 #define _PAGE_ACCESSED  0x020
 #define _PAGE_DIRTY     0x040
 #define _PAGE_PSE       0x080   /* 2MB page */
-#define _PAGE_FILE      0x040   /* set:pagecache, unset:swap */
+#define _PAGE_FILE      0x040   /* nonlinear file mapping, saved PTE; unset:swap */
 #define _PAGE_GLOBAL    0x100   /* Global TLB entry */
 
 #define _PAGE_PROTNONE  0x080   /* If not present */
@@ -176,6 +189,8 @@ extern inline void pgd_clear (pgd_t * pgd)
         (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD)
 #define __PAGE_KERNEL_LARGE \
         (__PAGE_KERNEL | _PAGE_PSE)
+#define __PAGE_KERNEL_LARGE_EXEC \
+        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
 
 #define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
 
@@ -245,6 +260,7 @@ static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
+#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT)
 static inline int pte_user(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 extern inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 extern inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
@@ -252,6 +268,7 @@ extern inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
 extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 extern inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
+static inline int pte_huge(pte_t pte)           { return (pte_val(pte) & __LARGE_PTE) == __LARGE_PTE; }
 
 extern inline pte_t pte_rdprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
 extern inline pte_t pte_exprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
@@ -263,6 +280,7 @@ extern inline pte_t pte_mkexec(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) | _
 extern inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
 extern inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
 extern inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
+extern inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | __LARGE_PTE)); return pte; }
 
 struct vm_area_struct;
 
@@ -290,7 +308,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
  */
 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))
 
-#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT) 
 static inline int pmd_large(pmd_t pte) { 
         return (pmd_val(pte) & __LARGE_PTE) == __LARGE_PTE; 
 }       
@@ -430,6 +447,7 @@ extern int kern_addr_valid(unsigned long addr);
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 #define __HAVE_ARCH_PTE_SAME
 #include <asm-generic/pgtable.h>
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index d641b19f6da5..a8321999448f 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -32,7 +32,7 @@
 #define ID_MASK         0x00200000
 
 #define desc_empty(desc) \
-               (!((desc)->a + (desc)->b))
+               (!((desc)->a | (desc)->b))
 
 #define desc_equal(desc1, desc2) \
                (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
@@ -160,16 +160,17 @@ static inline void clear_in_cr4 (unsigned long mask)
 /*
  * User space process size. 47bits minus one guard page.
  */
-#define TASK_SIZE       (0x800000000000UL - 4096)
+#define TASK_SIZE64     (0x800000000000UL - 4096)
 
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
  */
 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
-#define TASK_UNMAPPED_32 PAGE_ALIGN(IA32_PAGE_OFFSET/3)
-#define TASK_UNMAPPED_64 PAGE_ALIGN(TASK_SIZE/3) 
-#define TASK_UNMAPPED_BASE      \
-        (test_thread_flag(TIF_IA32) ? TASK_UNMAPPED_32 : TASK_UNMAPPED_64)  
+
+#define TASK_SIZE               (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
+#define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
+
+#define TASK_UNMAPPED_BASE      PAGE_ALIGN(TASK_SIZE/3)
 
 /*
  * Size of io_bitmap.
@@ -279,6 +280,14 @@ struct thread_struct {
         set_fs(USER_DS);                                                         \
 } while(0) 
 
+#define get_debugreg(var, register)                             \
+                __asm__("movq %%db" #register ", %0"            \
+                        :"=r" (var))
+#define set_debugreg(value, register)                   \
+                __asm__("movq %0,%%db" #register                \
+                        : /* no output */                       \
+                        :"r" (value))
+
 struct task_struct;
 struct mm_struct;
 
@@ -389,7 +398,7 @@ static inline void prefetch(void *x)
 #define ARCH_HAS_PREFETCHW 1
 static inline void prefetchw(void *x) 
 { 
-        alternative_input(ASM_NOP5,
+        alternative_input("prefetcht0 (%1)",
                           "prefetchw (%1)",
                           X86_FEATURE_3DNOW,
                           "r" (x));
@@ -428,6 +437,11 @@ static inline void prefetchw(void *x)
         outb((data), 0x23); \
 } while (0)
 
+static inline void serialize_cpu(void)
+{
+        __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
+}
+
 static inline void __monitor(const void *eax, unsigned long ecx,
                 unsigned long edx)
 {
diff --git a/include/asm-x86_64/proto.h b/include/asm-x86_64/proto.h
index f2f073642d62..6c813eb521f3 100644
--- a/include/asm-x86_64/proto.h
+++ b/include/asm-x86_64/proto.h
@@ -15,6 +15,13 @@ extern void pda_init(int);
 extern void early_idt_handler(void);
 
 extern void mcheck_init(struct cpuinfo_x86 *c);
+#ifdef CONFIG_MTRR
+extern void mtrr_ap_init(void);
+extern void mtrr_bp_init(void);
+#else
+#define mtrr_ap_init() do {} while (0)
+#define mtrr_bp_init() do {} while (0)
+#endif
 extern void init_memory_mapping(unsigned long start, unsigned long end);
 
 extern void system_call(void); 
diff --git a/include/asm-x86_64/ptrace.h b/include/asm-x86_64/ptrace.h
index 5bbc8d3141c8..ca6f15ff61d4 100644
--- a/include/asm-x86_64/ptrace.h
+++ b/include/asm-x86_64/ptrace.h
@@ -82,6 +82,7 @@ struct pt_regs {
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) 
 #define user_mode(regs) (!!((regs)->cs & 3))
+#define user_mode_vm(regs) user_mode(regs)
 #define instruction_pointer(regs) ((regs)->rip)
 extern unsigned long profile_pc(struct pt_regs *regs);
 void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
diff --git a/include/asm-x86_64/serial.h b/include/asm-x86_64/serial.h
index dbab232044cd..dc752eafa681 100644
--- a/include/asm-x86_64/serial.h
+++ b/include/asm-x86_64/serial.h
@@ -22,109 +22,9 @@
 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
 #endif
 
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define FOURPORT_FLAGS ASYNC_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#define HUB6_FLAGS 0
-#endif
-
-#define MCA_COM_FLAGS   (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
-
-/*
- * The following define the access methods for the HUB6 card. All
- * access is through two ports for all 24 possible chips. The card is
- * selected through the high 2 bits, the port on that card with the
- * "middle" 3 bits, and the register on that port with the bottom
- * 3 bits.
- *
- * While the access port and interrupt is configurable, the default
- * port locations are 0x302 for the port control register, and 0x303
- * for the data read/write register. Normally, the interrupt is at irq3
- * but can be anything from 3 to 7 inclusive. Note that using 3 will
- * require disabling com2.
- */
-
-#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
-
-#define STD_SERIAL_PORT_DEFNS                   \
+#define SERIAL_PORT_DFNS                        \
         /* UART CLK   PORT IRQ     FLAGS        */                      \
         { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
         { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define EXTRA_SERIAL_PORT_DEFNS                 \
-        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
-        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
-        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
-        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
-        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
-        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
-        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
-        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
-        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
-        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
-        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
-        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
-        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
-        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
-        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
-        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
-        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
-        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
-        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
-        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
-        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
-        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
-        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
-        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
-        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
-        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
-        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
-#else
-#define EXTRA_SERIAL_PORT_DEFNS
-#endif
-
-/* You can have up to four HUB6's in the system, but I've only
- * included two cards here for a total of twelve ports.
- */
-#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
-#define HUB6_SERIAL_PORT_DFNS           \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
-        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
-#else
-#define HUB6_SERIAL_PORT_DFNS
-#endif
-
-#ifdef CONFIG_MCA
-#define MCA_SERIAL_PORT_DFNS                    \
-        { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS },     \
-        { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
-#else
-#define MCA_SERIAL_PORT_DFNS
-#endif
-
-#define SERIAL_PORT_DFNS                \
-        STD_SERIAL_PORT_DEFNS           \
-        EXTRA_SERIAL_PORT_DEFNS         \
-        HUB6_SERIAL_PORT_DFNS           \
-        MCA_SERIAL_PORT_DFNS
-
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index 96844fecbde8..de8b57b2b62b 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -43,13 +43,15 @@ extern cpumask_t cpu_callout_map;
 extern void smp_alloc_memory(void);
 extern volatile unsigned long smp_invalidate_needed;
 extern int pic_mode;
+extern void lock_ipi_call_lock(void);
+extern void unlock_ipi_call_lock(void);
 extern int smp_num_siblings;
-extern void smp_flush_tlb(void);
-extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
 extern void smp_send_reschedule(int cpu);
-extern void smp_invalidate_rcv(void);           /* Process an NMI */
 extern void zap_low_mappings(void);
 void smp_stop_cpu(void);
+extern int smp_call_function_single(int cpuid, void (*func) (void *info),
+                                void *info, int retry, int wait);
+
 extern cpumask_t cpu_sibling_map[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
 extern u8 phys_proc_id[NR_CPUS];
@@ -68,7 +70,7 @@ static inline int num_booting_cpus(void)
         return cpus_weight(cpu_callout_map);
 }
 
-#define __smp_processor_id() read_pda(cpunumber)
+#define raw_smp_processor_id() read_pda(cpunumber)
 
 extern __inline int hard_smp_processor_id(void)
 {
@@ -77,6 +79,8 @@ extern __inline int hard_smp_processor_id(void)
 }
 
 extern int safe_smp_processor_id(void);
+extern int __cpu_disable(void);
+extern void __cpu_die(unsigned int cpu);
 
 #endif /* !ASSEMBLY */
 
diff --git a/include/asm-x86_64/socket.h b/include/asm-x86_64/socket.h
index d9a252ea8210..f2cdbeae5d5b 100644
--- a/include/asm-x86_64/socket.h
+++ b/include/asm-x86_64/socket.h
@@ -14,6 +14,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
diff --git a/include/asm-x86_64/sparsemem.h b/include/asm-x86_64/sparsemem.h
new file mode 100644
index 000000000000..dabb16714a71
--- /dev/null
+++ b/include/asm-x86_64/sparsemem.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_X86_64_SPARSEMEM_H
+#define _ASM_X86_64_SPARSEMEM_H 1
+
+#ifdef CONFIG_SPARSEMEM
+
+/*
+ * generic non-linear memory support:
+ *
+ * 1) we will not split memory into more chunks than will fit into the flags
+ *    field of the struct page
+ *
+ * SECTION_SIZE_BITS            2^n: size of each section
+ * MAX_PHYSADDR_BITS            2^n: max size of physical address space
+ * MAX_PHYSMEM_BITS             2^n: how much memory we can have in that space
+ *
+ */
+
+#define SECTION_SIZE_BITS       27 /* matt - 128 is convenient right now */
+#define MAX_PHYSADDR_BITS       40
+#define MAX_PHYSMEM_BITS        40
+
+extern int early_pfn_to_nid(unsigned long pfn);
+
+#endif /* CONFIG_SPARSEMEM */
+
+#endif /* _ASM_X86_64_SPARSEMEM_H */
diff --git a/include/asm-x86_64/suspend.h b/include/asm-x86_64/suspend.h
index ec745807feae..bb9f40597d09 100644
--- a/include/asm-x86_64/suspend.h
+++ b/include/asm-x86_64/suspend.h
@@ -16,7 +16,7 @@ arch_prepare_suspend(void)
 struct saved_context {
         u16 ds, es, fs, gs, ss;
         unsigned long gs_base, gs_kernel_base, fs_base;
-        unsigned long cr0, cr2, cr3, cr4;
+        unsigned long cr0, cr2, cr3, cr4, cr8;
         u16 gdt_pad;
         u16 gdt_limit;
         unsigned long gdt_base;
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 76165736e43a..8606e170a7dc 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -116,12 +116,12 @@ struct alt_instr {
 /*
  * Alternative inline assembly with input.
  * 
- * Pecularities:
+ * Peculiarities:
  * No memory clobber here. 
  * Argument numbers start with 1.
  * Best is to use constraints that are fixed size (like (%1) ... "r")
  * If you use variable sized constraints like "m" or "g" in the 
- * replacement maake sure to pad to the worst case length.
+ * replacement make sure to pad to the worst case length.
  */
 #define alternative_input(oldinstr, newinstr, feature, input...)        \
         asm volatile ("661:\n\t" oldinstr "\n662:\n"                    \
@@ -335,9 +335,6 @@ void cpu_idle_wait(void);
 void disable_hlt(void);
 void enable_hlt(void);
 
-#define HAVE_EAT_KEY
-void eat_key(void);
-
 extern unsigned long arch_align_stack(unsigned long sp);
 
 #endif
diff --git a/include/asm-x86_64/thread_info.h b/include/asm-x86_64/thread_info.h
index f4b3b249639c..08eb6e4f3737 100644
--- a/include/asm-x86_64/thread_info.h
+++ b/include/asm-x86_64/thread_info.h
@@ -29,7 +29,7 @@ struct thread_info {
         __u32                   flags;          /* low level flags */
         __u32                   status;         /* thread synchronous flags */
         __u32                   cpu;            /* current CPU */
-        int                     preempt_count;
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
         mm_segment_t            addr_limit;     
         struct restart_block    restart_block;
diff --git a/include/asm-x86_64/timex.h b/include/asm-x86_64/timex.h
index 34f31a18f90b..24ecf6a637cb 100644
--- a/include/asm-x86_64/timex.h
+++ b/include/asm-x86_64/timex.h
@@ -26,6 +26,9 @@ static inline cycles_t get_cycles (void)
 
 extern unsigned int cpu_khz;
 
+extern int read_current_timer(unsigned long *timer_value);
+#define ARCH_HAS_READ_CURRENT_TIMER     1
+
 extern struct vxtime_data vxtime;
 
 #endif
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 2e811ac262af..505b0cf906de 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -22,16 +22,18 @@
  */
 #define __flush_tlb_global()                                            \
         do {                                                            \
-                unsigned long tmpreg;                                   \
+                unsigned long tmpreg, cr4, cr4_orig;                    \
                                                                         \
                 __asm__ __volatile__(                                   \
-                        "movq %1, %%cr4;  # turn off PGE     \n"        \
+                        "movq %%cr4, %2;  # turn off PGE     \n"        \
+                        "movq %2, %1;                        \n"        \
+                        "andq %3, %1;                        \n"        \
+                        "movq %1, %%cr4;                     \n"        \
                         "movq %%cr3, %0;  # flush TLB        \n"        \
                         "movq %0, %%cr3;                     \n"        \
                         "movq %2, %%cr4;  # turn PGE back on \n"        \
-                        : "=&r" (tmpreg)                                \
-                        : "r" (mmu_cr4_features & ~X86_CR4_PGE),        \
-                          "r" (mmu_cr4_features)                        \
+                        : "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
+                        : "i" (~X86_CR4_PGE)                            \
                         : "memory");                                    \
         } while (0)
 
@@ -54,8 +56,9 @@ extern unsigned long pgkern_mask;
  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
  *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
  *
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
  */
 
 #ifndef CONFIG_SMP
@@ -113,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
 static inline void flush_tlb_pgtables(struct mm_struct *mm,
                                       unsigned long start, unsigned long end)
 {
-        /* x86_64 does not keep any page table caches in TLB */
+        /* x86_64 does not keep any page table caches in a software TLB.
+           The CPUs do in their hardware TLBs, but they are handled
+           by the normal TLB flushing algorithms. */
 }
 
 #endif /* _X8664_TLBFLUSH_H */
diff --git a/include/asm-x86_64/topology.h b/include/asm-x86_64/topology.h
index 67f24e0ea819..c1bc3fad482e 100644
--- a/include/asm-x86_64/topology.h
+++ b/include/asm-x86_64/topology.h
@@ -3,7 +3,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifdef CONFIG_NUMA
 
 #include <asm/mpspec.h>
 #include <asm/bitops.h>
@@ -13,8 +13,8 @@
 extern cpumask_t cpu_online_map;
 
 extern unsigned char cpu_to_node[];
+extern unsigned char pci_bus_to_node[];
 extern cpumask_t     node_to_cpumask[];
-extern cpumask_t pci_bus_to_cpumask[];
 
 #ifdef CONFIG_ACPI_NUMA
 extern int __node_distance(int, int);
@@ -26,18 +26,9 @@ extern int __node_distance(int, int);
 #define parent_node(node)               (node)
 #define node_to_first_cpu(node)         (__ffs(node_to_cpumask[node]))
 #define node_to_cpumask(node)           (node_to_cpumask[node])
+#define pcibus_to_node(bus)             pci_bus_to_node[(bus)->number]
+#define pcibus_to_cpumask(bus)          node_to_cpumask(pcibus_to_node(bus));
 
-static inline cpumask_t __pcibus_to_cpumask(int bus)
-{
-        cpumask_t busmask = pci_bus_to_cpumask[bus];
-        cpumask_t online = cpu_online_map;
-        cpumask_t res;
-        cpus_and(res, busmask, online);
-        return res;
-}
-#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus->number)
-
-#ifdef CONFIG_NUMA
 /* sched_domains SD_NODE_INIT for x86_64 machines */
 #define SD_NODE_INIT (struct sched_domain) {            \
         .span                   = CPU_MASK_NONE,        \
@@ -48,18 +39,21 @@ static inline cpumask_t __pcibus_to_cpumask(int bus)
         .busy_factor            = 32,                   \
         .imbalance_pct          = 125,                  \
         .cache_hot_time         = (10*1000000),         \
-        .cache_nice_tries       = 1,                    \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 0,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
         .per_cpu_gain           = 100,                  \
         .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_NEWIDLE    \
+                                | SD_BALANCE_FORK       \
                                 | SD_BALANCE_EXEC       \
-                                | SD_WAKE_IDLE          \
                                 | SD_WAKE_BALANCE,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
         .nr_balance_failed      = 0,                    \
 }
-#endif
 
 #endif
 
diff --git a/include/asm-x86_64/types.h b/include/asm-x86_64/types.h
index 32bd1426b523..c86c2e6793e2 100644
--- a/include/asm-x86_64/types.h
+++ b/include/asm-x86_64/types.h
@@ -51,8 +51,6 @@ typedef u64 dma_addr_t;
 typedef u64 sector_t;
 #define HAVE_SECTOR_T
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-x86_64/uaccess.h b/include/asm-x86_64/uaccess.h
index 48f292752c96..1bb8b8a24436 100644
--- a/include/asm-x86_64/uaccess.h
+++ b/include/asm-x86_64/uaccess.h
@@ -49,13 +49,6 @@
 
 #define access_ok(type, addr, size) (__range_not_ok(addr,size) == 0)
 
-/* this function will go away soon - use access_ok() instead */
-extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
-{
-        return access_ok(type,addr,size) ? 0 : -EFAULT;
-}
-
-
 /*
  * The exception table consists of pairs of addresses: the first is the
  * address of an instruction that is allowed to fault, and the second is
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index 3c9af6fd4332..11ba931cf82f 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -552,7 +552,7 @@ __SYSCALL(__NR_mq_notify, sys_mq_notify)
 #define __NR_mq_getsetattr      245
 __SYSCALL(__NR_mq_getsetattr, sys_mq_getsetattr)
 #define __NR_kexec_load         246
-__SYSCALL(__NR_kexec_load, sys_ni_syscall)
+__SYSCALL(__NR_kexec_load, sys_kexec_load)
 #define __NR_waitid             247
 __SYSCALL(__NR_waitid, sys_waitid)
 #define __NR_add_key            248
@@ -561,8 +561,18 @@ __SYSCALL(__NR_add_key, sys_add_key)
 __SYSCALL(__NR_request_key, sys_request_key)
 #define __NR_keyctl             250
 __SYSCALL(__NR_keyctl, sys_keyctl)
-
-#define __NR_syscall_max __NR_keyctl
+#define __NR_ioprio_set         251
+__SYSCALL(__NR_ioprio_set, sys_ioprio_set)
+#define __NR_ioprio_get         252
+__SYSCALL(__NR_ioprio_get, sys_ioprio_get)
+#define __NR_inotify_init       253
+__SYSCALL(__NR_inotify_init, sys_inotify_init)
+#define __NR_inotify_add_watch  254
+__SYSCALL(__NR_inotify_add_watch, sys_inotify_add_watch)
+#define __NR_inotify_rm_watch   255
+__SYSCALL(__NR_inotify_rm_watch, sys_inotify_rm_watch)
+
+#define __NR_syscall_max __NR_inotify_rm_watch
 #ifndef __NO_STUBS
 
 /* user-visible error numbers are in the range -1 - -4095 */
diff --git a/include/asm-xtensa/a.out.h b/include/asm-xtensa/a.out.h
new file mode 100644
index 000000000000..3be701dfe098
--- /dev/null
+++ b/include/asm-xtensa/a.out.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-xtensa/addrspace.h
+ *
+ * Dummy a.out file. Xtensa does not support the a.out format, but the kernel
+ * seems to depend on it.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_A_OUT_H
+#define _XTENSA_A_OUT_H
+
+/* Note: the kernel needs the a.out definitions, even if only ELF is used. */
+
+#define STACK_TOP       TASK_SIZE
+
+struct exec
+{
+  unsigned long a_info;
+  unsigned a_text;
+  unsigned a_data;
+  unsigned a_bss;
+  unsigned a_syms;
+  unsigned a_entry;
+  unsigned a_trsize;
+  unsigned a_drsize;
+};
+
+#endif /* _XTENSA_A_OUT_H */
diff --git a/include/asm-xtensa/atomic.h b/include/asm-xtensa/atomic.h
new file mode 100644
index 000000000000..24f86f0e43cf
--- /dev/null
+++ b/include/asm-xtensa/atomic.h
@@ -0,0 +1,272 @@
+/*
+ * include/asm-xtensa/atomic.h
+ *
+ * Atomic operations that C can't guarantee us.  Useful for resource counting..
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ATOMIC_H
+#define _XTENSA_ATOMIC_H
+
+#include <linux/config.h>
+#include <linux/stringify.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#ifdef __KERNEL__
+#include <asm/processor.h>
+#include <asm/system.h>
+
+#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+
+/*
+ * This Xtensa implementation assumes that the right mechanism
+ * for exclusion is for locking interrupts to level 1.
+ *
+ * Locking interrupts looks like this:
+ *
+ *    rsil a15, 1
+ *    <code>
+ *    wsr  a15, PS
+ *    rsync
+ *
+ * Note that a15 is used here because the register allocation
+ * done by the compiler is not guaranteed and a window overflow
+ * may not occur between the rsil and wsr instructions. By using
+ * a15 in the rsil, the machine is guaranteed to be in a state
+ * where no register reference will cause an overflow.
+ */
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+#define atomic_read(v)          ((v)->counter)
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+#define atomic_set(v,i)         ((v)->counter = (i))
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, atomic_t * v)
+{
+    unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0              \n\t"
+        "add     %0, %0, %1             \n\t"
+        "s32i    %0, %2, 0              \n\t"
+        "wsr     a15, "__stringify(PS)"       \n\t"
+        "rsync                          \n"
+        : "=&a" (vval)
+        : "a" (i), "a" (v)
+        : "a15", "memory"
+        );
+}
+
+/**
+ * atomic_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, atomic_t *v)
+{
+    unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0              \n\t"
+        "sub     %0, %0, %1             \n\t"
+        "s32i    %0, %2, 0              \n\t"
+        "wsr     a15, "__stringify(PS)"       \n\t"
+        "rsync                          \n"
+        : "=&a" (vval)
+        : "a" (i), "a" (v)
+        : "a15", "memory"
+        );
+}
+
+/*
+ * We use atomic_{add|sub}_return to define other functions.
+ */
+
+static inline int atomic_add_return(int i, atomic_t * v)
+{
+     unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0             \n\t"
+        "add     %0, %0, %1            \n\t"
+        "s32i    %0, %2, 0             \n\t"
+        "wsr     a15, "__stringify(PS)"      \n\t"
+        "rsync                         \n"
+        : "=&a" (vval)
+        : "a" (i), "a" (v)
+        : "a15", "memory"
+        );
+
+    return vval;
+}
+
+static inline int atomic_sub_return(int i, atomic_t * v)
+{
+    unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0             \n\t"
+        "sub     %0, %0, %1            \n\t"
+        "s32i    %0, %2, 0             \n\t"
+        "wsr     a15, "__stringify(PS)"       \n\t"
+        "rsync                         \n"
+        : "=&a" (vval)
+        : "a" (i), "a" (v)
+        : "a15", "memory"
+        );
+
+    return vval;
+}
+
+/**
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc(v) atomic_add(1,(v))
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc_return(v) atomic_add_return(1,(v))
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic_dec(v) atomic_sub(1,(v))
+
+/**
+ * atomic_dec_return - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic_dec_return(v) atomic_sub_return(1,(v))
+
+/**
+ * atomic_dec_and_test - decrement and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define atomic_dec_and_test(v) (atomic_sub_return(1,(v)) == 0)
+
+/**
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_add_return(1,(v)) == 0)
+
+/**
+ * atomic_add_negative - add and test if negative
+ * @v: pointer of type atomic_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0)
+
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+    unsigned int all_f = -1;
+    unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0             \n\t"
+        "xor     %1, %4, %3            \n\t"
+        "and     %0, %0, %4            \n\t"
+        "s32i    %0, %2, 0             \n\t"
+        "wsr     a15, "__stringify(PS)"      \n\t"
+        "rsync                         \n"
+        : "=&a" (vval), "=a" (mask)
+        : "a" (v), "a" (all_f), "1" (mask)
+        : "a15", "memory"
+        );
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+    unsigned int vval;
+
+    __asm__ __volatile__(
+        "rsil    a15,"__stringify(LOCKLEVEL)"\n\t"
+        "l32i    %0, %2, 0             \n\t"
+        "or      %0, %0, %1            \n\t"
+        "s32i    %0, %2, 0             \n\t"
+        "wsr     a15, "__stringify(PS)"       \n\t"
+        "rsync                         \n"
+        : "=&a" (vval)
+        : "a" (mask), "a" (v)
+        : "a15", "memory"
+        );
+}
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#endif /* __KERNEL__ */
+
+#endif /* _XTENSA_ATOMIC_H */
+
diff --git a/include/asm-xtensa/auxvec.h b/include/asm-xtensa/auxvec.h
new file mode 100644
index 000000000000..257dec75c5af
--- /dev/null
+++ b/include/asm-xtensa/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __XTENSA_AUXVEC_H
+#define __XTENSA_AUXVEC_H
+
+#endif
diff --git a/include/asm-xtensa/bitops.h b/include/asm-xtensa/bitops.h
new file mode 100644
index 000000000000..d395ef226c32
--- /dev/null
+++ b/include/asm-xtensa/bitops.h
@@ -0,0 +1,446 @@
+/*
+ * include/asm-xtensa/bitops.h
+ *
+ * Atomic operations that C can't guarantee us.Useful for resource counting etc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_BITOPS_H
+#define _XTENSA_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SMP
+# error SMP not supported on this architecture
+#endif
+
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *a |= mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile unsigned long * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+
+        *a |= mask;
+}
+
+static __inline__ void clear_bit(int nr, volatile void * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *a &= ~mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+
+        *a &= ~mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+
+static __inline__ void change_bit(int nr, volatile void * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *a ^= mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+
+        *a ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+        unsigned long retval;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+        unsigned long retval;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+
+        retval = (mask & *a) != 0;
+        *a |= mask;
+
+        return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+        unsigned long retval;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a &= ~mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long old = *a;
+
+        *a = old & ~mask;
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+        unsigned long retval;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        retval = (mask & *a) != 0;
+        *a ^= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+/*
+ * non-atomic version; can be reordered
+ */
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long old = *a;
+
+        *a = old ^ mask;
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_bit(int nr, const volatile void *addr)
+{
+        return 1UL & (((const volatile unsigned int *)addr)[nr>>5] >> (nr&31));
+}
+
+#if XCHAL_HAVE_NSAU
+
+static __inline__ int __cntlz (unsigned long x)
+{
+        int lz;
+        asm ("nsau %0, %1" : "=r" (lz) : "r" (x));
+        return 31 - lz;
+}
+
+#else
+
+static __inline__ int __cntlz (unsigned long x)
+{
+        unsigned long sum, x1, x2, x4, x8, x16;
+        x1  = x & 0xAAAAAAAA;
+        x2  = x & 0xCCCCCCCC;
+        x4  = x & 0xF0F0F0F0;
+        x8  = x & 0xFF00FF00;
+        x16 = x & 0xFFFF0000;
+        sum = x2 ? 2 : 0;
+        sum += (x16 != 0) * 16;
+        sum += (x8 != 0) * 8;
+        sum += (x4 != 0) * 4;
+        sum += (x1 != 0);
+
+        return sum;
+}
+
+#endif
+
+/*
+ * ffz: Find first zero in word. Undefined if no zero exists.
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+
+static __inline__ int ffz(unsigned long x)
+{
+        if ((x = ~x) == 0)
+                return 32;
+        return __cntlz(x & -x);
+}
+
+/*
+ * __ffs: Find first bit set in word. Return 0 for bit 0
+ */
+
+static __inline__ int __ffs(unsigned long x)
+{
+        return __cntlz(x & -x);
+}
+
+/*
+ * ffs: Find first bit set in word. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+static __inline__ int ffs(unsigned long x)
+{
+        return __cntlz(x & -x) + 1;
+}
+
+/*
+ * fls: Find last (most-significant) bit set in word.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
+static __inline__ int fls (unsigned int x)
+{
+        return __cntlz(x);
+}
+
+static __inline__ int
+find_next_bit(const unsigned long *addr, int size, int offset)
+{
+        const unsigned long *p = addr + (offset >> 5);
+        unsigned long result = offset & ~31UL;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if (offset) {
+                tmp = *p++;
+                tmp &= ~0UL << offset;
+                if (size < 32)
+                        goto found_first;
+                if (tmp)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while (size >= 32) {
+                if ((tmp = *p++) != 0)
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        tmp &= ~0UL >> (32 - size);
+        if (tmp == 0UL) /* Are any bits set? */
+                return result + size;   /* Nope. */
+found_middle:
+        return result + __ffs(tmp);
+}
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+
+#define find_first_bit(addr, size) \
+        find_next_bit((addr), (size), 0)
+
+static __inline__ int
+find_next_zero_bit(const unsigned long *addr, int size, int offset)
+{
+        const unsigned long *p = addr + (offset >> 5);
+        unsigned long result = offset & ~31UL;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if (offset) {
+                tmp = *p++;
+                tmp |= ~0UL >> (32-offset);
+                if (size < 32)
+                        goto found_first;
+                if (~tmp)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while (size & ~31UL) {
+                if (~(tmp = *p++))
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        tmp |= ~0UL << size;
+found_middle:
+        return result + ffz(tmp);
+}
+
+#define find_first_zero_bit(addr, size) \
+        find_next_zero_bit((addr), (size), 0)
+
+#ifdef __XTENSA_EL__
+# define ext2_set_bit(nr,addr) __test_and_set_bit((nr), (addr))
+# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr),(addr))
+# define ext2_clear_bit(nr,addr) __test_and_clear_bit((nr), (addr))
+# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr),(addr))
+# define ext2_test_bit(nr,addr) test_bit((nr), (addr))
+# define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr),(size))
+# define ext2_find_next_zero_bit(addr, size, offset) \
+                find_next_zero_bit((addr), (size), (offset))
+#elif defined(__XTENSA_EB__)
+# define ext2_set_bit(nr,addr) __test_and_set_bit((nr) ^ 0x18, (addr))
+# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr) ^ 0x18, (addr))
+# define ext2_clear_bit(nr,addr) __test_and_clear_bit((nr) ^ 18, (addr))
+# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr)^0x18,(addr))
+# define ext2_test_bit(nr,addr) test_bit((nr) ^ 0x18, (addr))
+# define ext2_find_first_zero_bit(addr, size) \
+        ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+        unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+        unsigned long result = offset & ~31UL;
+        unsigned long tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if(offset) {
+                /* We hold the little endian value in tmp, but then the
+                 * shift is illegal. So we could keep a big endian value
+                 * in tmp, like this:
+                 *
+                 * tmp = __swab32(*(p++));
+                 * tmp |= ~0UL >> (32-offset);
+                 *
+                 * but this would decrease preformance, so we change the
+                 * shift:
+                 */
+                tmp = *(p++);
+                tmp |= __swab32(~0UL >> (32-offset));
+                if(size < 32)
+                        goto found_first;
+                if(~tmp)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while(size & ~31UL) {
+                if(~(tmp = *(p++)))
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if(!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        /* tmp is little endian, so we would have to swab the shift,
+         * see above. But then we have to swab tmp below for ffz, so
+         * we might as well do this here.
+         */
+        return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+        return result + ffz(__swab32(tmp));
+}
+
+#else
+# error processor byte order undefined!
+#endif
+
+
+#define hweight32(x)    generic_hweight32(x)
+#define hweight16(x)    generic_hweight16(x)
+#define hweight8(x)     generic_hweight8(x)
+
+/*
+ * Find the first bit set in a 140-bit bitmap.
+ * The first 100 bits are unlikely to be set.
+ */
+
+static inline int sched_find_first_bit(const unsigned long *b)
+{
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 32;
+        if (unlikely(b[2]))
+                return __ffs(b[2]) + 64;
+        if (b[3])
+                return __ffs(b[3]) + 96;
+        return __ffs(b[4]) + 128;
+}
+
+
+/* Bitmap functions for the minix filesystem.  */
+
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _XTENSA_BITOPS_H */
diff --git a/include/asm-xtensa/bootparam.h b/include/asm-xtensa/bootparam.h
new file mode 100644
index 000000000000..9983f2c1b7ee
--- /dev/null
+++ b/include/asm-xtensa/bootparam.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-xtensa/bootparam.h
+ *
+ * Definition of the Linux/Xtensa boot parameter structure
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005  Tensilica Inc.
+ *
+ * (Concept borrowed from the 68K port)
+ */
+
+#ifndef _XTENSA_BOOTPARAM_H
+#define _XTENSA_BOOTPARAM_H
+
+#define BP_VERSION 0x0001
+
+#define BP_TAG_COMMAND_LINE     0x1001  /* command line (0-terminated string)*/
+#define BP_TAG_INITRD           0x1002  /* ramdisk addr and size (bp_meminfo) */
+#define BP_TAG_MEMORY           0x1003  /* memory addr and size (bp_meminfo) */
+#define BP_TAG_SERIAL_BAUSRATE  0x1004  /* baud rate of current console. */
+#define BP_TAG_SERIAL_PORT      0x1005  /* serial device of current console */
+
+#define BP_TAG_FIRST            0x7B0B  /* first tag with a version number */
+#define BP_TAG_LAST             0x7E0B  /* last tag */
+
+#ifndef __ASSEMBLY__
+
+/* All records are aligned to 4 bytes */
+
+typedef struct bp_tag {
+  unsigned short id;            /* tag id */
+  unsigned short size;          /* size of this record excluding the structure*/
+  unsigned long data[0];        /* data */
+} bp_tag_t;
+
+typedef struct meminfo {
+  unsigned long type;
+  unsigned long start;
+  unsigned long end;
+} meminfo_t;
+
+#define SYSMEM_BANKS_MAX 5
+
+#define MEMORY_TYPE_CONVENTIONAL        0x1000
+#define MEMORY_TYPE_NONE                0x2000
+
+typedef struct sysmem_info {
+  int nr_banks;
+  meminfo_t bank[SYSMEM_BANKS_MAX];
+} sysmem_info_t;
+
+extern sysmem_info_t sysmem;
+
+#endif
+#endif
+
+
+
diff --git a/include/asm-xtensa/bug.h b/include/asm-xtensa/bug.h
new file mode 100644
index 000000000000..56703659b204
--- /dev/null
+++ b/include/asm-xtensa/bug.h
@@ -0,0 +1,41 @@
+/*
+ * include/asm-xtensa/bug.h
+ *
+ * Macros to cause a 'bug' message.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_BUG_H
+#define _XTENSA_BUG_H
+
+#include <linux/stringify.h>
+
+#define ILL     __asm__ __volatile__ (".byte 0,0,0\n")
+
+#ifdef CONFIG_KALLSYMS
+# define BUG() do {                                                     \
+        printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__);           \
+        ILL;                                                            \
+} while (0)
+#else
+# define BUG() do {                                                     \
+        printk("kernel BUG!\n");                                        \
+        ILL;                                                            \
+} while (0)
+#endif
+
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+#define PAGE_BUG(page) do {  BUG(); } while (0)
+#define WARN_ON(condition) do {                                            \
+  if (unlikely((condition)!=0)) {                                          \
+    printk ("Warning in %s at %s:%d\n", __FUNCTION__, __FILE__, __LINE__); \
+      dump_stack();                                                        \
+  }                                                                        \
+} while (0)
+
+#endif  /* _XTENSA_BUG_H */
diff --git a/include/asm-xtensa/bugs.h b/include/asm-xtensa/bugs.h
new file mode 100644
index 000000000000..c42285320133
--- /dev/null
+++ b/include/asm-xtensa/bugs.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-xtensa/bugs.h
+ *
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Xtensa processors don't have any bugs.  :)
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ */
+
+#ifndef _XTENSA_BUGS_H
+#define _XTENSA_BUGS_H
+
+#include <asm/processor.h>
+
+static void __init check_bugs(void)
+{
+}
+
+#endif /* _XTENSA_BUGS_H */
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h
new file mode 100644
index 000000000000..0b1552569aae
--- /dev/null
+++ b/include/asm-xtensa/byteorder.h
@@ -0,0 +1,82 @@
+/*
+ * include/asm-xtensa/byteorder.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_BYTEORDER_H
+#define _XTENSA_BYTEORDER_H
+
+#include <asm/processor.h>
+#include <asm/types.h>
+
+static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
+{
+    __u32 res;
+    /* instruction sequence from Xtensa ISA release 2/2000 */
+    __asm__("ssai     8           \n\t"
+            "srli     %0, %1, 16  \n\t"
+            "src      %0, %0, %1  \n\t"
+            "src      %0, %0, %0  \n\t"
+            "src      %0, %1, %0  \n"
+            : "=&a" (res)
+            : "a" (x)
+            );
+    return res;
+}
+
+static __inline__ __const__ __u16 ___arch__swab16(__u16 x)
+{
+    /* Given that 'short' values are signed (i.e., can be negative),
+     * we cannot assume that the upper 16-bits of the register are
+     * zero.  We are careful to mask values after shifting.
+     */
+
+    /* There exists an anomaly between xt-gcc and xt-xcc.  xt-gcc
+     * inserts an extui instruction after putting this function inline
+     * to ensure that it uses only the least-significant 16 bits of
+     * the result.  xt-xcc doesn't use an extui, but assumes the
+     * __asm__ macro follows convention that the upper 16 bits of an
+     * 'unsigned short' result are still zero.  This macro doesn't
+     * follow convention; indeed, it leaves garbage in the upport 16
+     * bits of the register.
+
+     * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
+     * types while the return type of the function is a 16-bit type
+     * forces both compilers to insert exactly one extui instruction
+     * (or equivalent) to mask off the upper 16 bits. */
+
+    __u32 res;
+    __u32 tmp;
+
+    __asm__("extui    %1, %2, 8, 8\n\t"
+            "slli     %0, %2, 8   \n\t"
+            "or       %0, %0, %1  \n"
+            : "=&a" (res), "=&a" (tmp)
+            : "a" (x)
+            );
+
+    return res;
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __XTENSA_EL__
+# include <linux/byteorder/little_endian.h>
+#elif defined(__XTENSA_EB__)
+# include <linux/byteorder/big_endian.h>
+#else
+# error processor byte order undefined!
+#endif
+
+#endif /* __ASM_XTENSA_BYTEORDER_H */
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h
new file mode 100644
index 000000000000..5aae3f12407c
--- /dev/null
+++ b/include/asm-xtensa/cache.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-xtensa/cacheflush.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 2 of the License, or (at your option) any later version.
+ *
+ * (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CACHE_H
+#define _XTENSA_CACHE_H
+
+#include <xtensa/config/core.h>
+
+#if XCHAL_ICACHE_SIZE > 0
+# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0
+#  error cache configuration outside expected/supported range!
+# endif
+#endif
+
+#if XCHAL_DCACHE_SIZE > 0
+# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0
+#  error cache configuration outside expected/supported range!
+# endif
+#endif
+
+#define L1_CACHE_SHIFT          XCHAL_CACHE_LINEWIDTH_MAX
+#define L1_CACHE_BYTES          XCHAL_CACHE_LINESIZE_MAX
+
+#endif  /* _XTENSA_CACHE_H */
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
new file mode 100644
index 000000000000..44a36e087844
--- /dev/null
+++ b/include/asm-xtensa/cacheflush.h
@@ -0,0 +1,122 @@
+/*
+ * include/asm-xtensa/cacheflush.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CACHEFLUSH_H
+#define _XTENSA_CACHEFLUSH_H
+
+#ifdef __KERNEL__
+
+#include <linux/mm.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+/*
+ * flush and invalidate data cache, invalidate instruction cache:
+ *
+ * __flush_invalidate_cache_all()
+ * __flush_invalidate_cache_range(from,sze)
+ *
+ * invalidate data or instruction cache:
+ *
+ * __invalidate_icache_all()
+ * __invalidate_icache_page(adr)
+ * __invalidate_dcache_page(adr)
+ * __invalidate_icache_range(from,size)
+ * __invalidate_dcache_range(from,size)
+ *
+ * flush data cache:
+ *
+ * __flush_dcache_page(adr)
+ *
+ * flush and invalidate data cache:
+ *
+ * __flush_invalidate_dcache_all()
+ * __flush_invalidate_dcache_page(adr)
+ * __flush_invalidate_dcache_range(from,size)
+ */
+
+extern void __flush_invalidate_cache_all(void);
+extern void __flush_invalidate_cache_range(unsigned long, unsigned long);
+extern void __flush_invalidate_dcache_all(void);
+extern void __invalidate_icache_all(void);
+
+extern void __invalidate_dcache_page(unsigned long);
+extern void __invalidate_icache_page(unsigned long);
+extern void __invalidate_icache_range(unsigned long, unsigned long);
+extern void __invalidate_dcache_range(unsigned long, unsigned long);
+
+#if XCHAL_DCACHE_IS_WRITEBACK
+extern void __flush_dcache_page(unsigned long);
+extern void __flush_invalidate_dcache_page(unsigned long);
+extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
+#else
+# define __flush_dcache_page(p)                         do { } while(0)
+# define __flush_invalidate_dcache_page(p)              do { } while(0)
+# define __flush_invalidate_dcache_range(p,s)           do { } while(0)
+#endif
+
+/*
+ * We have physically tagged caches - nothing to do here -
+ * unless we have cache aliasing.
+ *
+ * Pages can get remapped. Because this might change the 'color' of that page,
+ * we have to flush the cache before the PTE is changed.
+ * (see also Documentation/cachetlb.txt)
+ */
+
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
+
+#define flush_cache_all()               __flush_invalidate_cache_all();
+#define flush_cache_mm(mm)              __flush_invalidate_cache_all();
+
+#define flush_cache_vmap(start,end)     __flush_invalidate_cache_all();
+#define flush_cache_vunmap(start,end)   __flush_invalidate_cache_all();
+
+extern void flush_dcache_page(struct page*);
+
+extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
+extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
+
+#else
+
+#define flush_cache_all()                               do { } while (0)
+#define flush_cache_mm(mm)                              do { } while (0)
+
+#define flush_cache_vmap(start,end)                     do { } while (0)
+#define flush_cache_vunmap(start,end)                   do { } while (0)
+
+#define flush_dcache_page(page)                         do { } while (0)
+
+#define flush_cache_page(vma,addr,pfn)                  do { } while (0)
+#define flush_cache_range(vma,start,end)                do { } while (0)
+
+#endif
+
+#define flush_icache_range(start,end)                                   \
+        __invalidate_icache_range(start,(end)-(start))
+
+/* This is not required, see Documentation/cachetlb.txt */
+
+#define flush_icache_page(vma,page)                     do { } while(0)
+
+#define flush_dcache_mmap_lock(mapping)                 do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)               do { } while (0)
+
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+#endif /* __KERNEL__ */
+
+#endif /* _XTENSA_CACHEFLUSH_H */
+
diff --git a/include/asm-xtensa/checksum.h b/include/asm-xtensa/checksum.h
new file mode 100644
index 000000000000..81a797ae3abe
--- /dev/null
+++ b/include/asm-xtensa/checksum.h
@@ -0,0 +1,264 @@
+/*
+ * include/asm-xtensa/checksum.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CHECKSUM_H
+#define _XTENSA_CHECKSUM_H
+
+#include <linux/config.h>
+#include <linux/in6.h>
+#include <xtensa/config/core.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums, and handles user-space pointer exceptions correctly, when needed.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+asmlinkage unsigned int csum_partial_copy_generic( const char *src, char *dst, int len, int sum,
+                                                   int *src_err_ptr, int *dst_err_ptr);
+
+/*
+ *      Note: when you get a NULL pointer exception here this means someone
+ *      passed in an incorrect kernel address to one of these functions.
+ *
+ *      If you use these functions directly please don't forget the
+ *      verify_area().
+ */
+static inline
+unsigned int csum_partial_copy_nocheck ( const char *src, char *dst,
+                                        int len, int sum)
+{
+        return csum_partial_copy_generic ( src, dst, len, sum, NULL, NULL);
+}
+
+static inline
+unsigned int csum_partial_copy_from_user ( const char *src, char *dst,
+                                                int len, int sum, int *err_ptr)
+{
+        return csum_partial_copy_generic ( src, dst, len, sum, err_ptr, NULL);
+}
+
+/*
+ * These are the old (and unsafe) way of doing checksums, a warning message will be
+ * printed if they are used and an exeption occurs.
+ *
+ * these functions should go away after some time.
+ */
+
+#define csum_partial_copy_fromuser csum_partial_copy
+unsigned int csum_partial_copy( const char *src, char *dst, int len, int sum);
+
+/*
+ *      Fold a partial checksum
+ */
+
+static __inline__ unsigned int csum_fold(unsigned int sum)
+{
+        unsigned int __dummy;
+        __asm__("extui  %1, %0, 16, 16\n\t"
+                "extui  %0 ,%0, 0, 16\n\t"
+                "add    %0, %0, %1\n\t"
+                "slli   %1, %0, 16\n\t"
+                "add    %0, %0, %1\n\t"
+                "extui  %0, %0, 16, 16\n\t"
+                "neg    %0, %0\n\t"
+                "addi   %0, %0, -1\n\t"
+                "extui  %0, %0, 0, 16\n\t"
+                : "=r" (sum), "=&r" (__dummy)
+                : "0" (sum));
+        return sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ */
+static __inline__ unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl)
+{
+        unsigned int sum, tmp, endaddr;
+
+        __asm__ __volatile__(
+                "sub            %0, %0, %0\n\t"
+#if XCHAL_HAVE_LOOPS
+                "loopgtz        %2, 2f\n\t"
+#else
+                "beqz           %2, 2f\n\t"
+                "slli           %4, %2, 2\n\t"
+                "add            %4, %4, %1\n\t"
+                "0:\t"
+#endif
+                "l32i           %3, %1, 0\n\t"
+                "add            %0, %0, %3\n\t"
+                "bgeu           %0, %3, 1f\n\t"
+                "addi           %0, %0, 1\n\t"
+                "1:\t"
+                "addi           %1, %1, 4\n\t"
+#if !XCHAL_HAVE_LOOPS
+                "blt            %1, %4, 0b\n\t"
+#endif
+                "2:\t"
+        /* Since the input registers which are loaded with iph and ihl
+           are modified, we must also specify them as outputs, or gcc
+           will assume they contain their original values. */
+                : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmp), "=&r" (endaddr)
+                : "1" (iph), "2" (ihl));
+
+        return  csum_fold(sum);
+}
+
+static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr,
+                                                   unsigned long daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   unsigned int sum)
+{
+
+#ifdef __XTENSA_EL__
+        unsigned long len_proto = (ntohs(len)<<16)+proto*256;
+#elif defined(__XTENSA_EB__)
+        unsigned long len_proto = (proto<<16)+len;
+#else
+# error processor byte order undefined!
+#endif
+        __asm__("add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "add    %0, %0, %2\n\t"
+                "bgeu   %0, %2, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "add    %0, %0, %3\n\t"
+                "bgeu   %0, %3, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                : "=r" (sum), "=r" (len_proto)
+                : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum));
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static __inline__ unsigned short int csum_tcpudp_magic(unsigned long saddr,
+                                                       unsigned long daddr,
+                                                       unsigned short len,
+                                                       unsigned short proto,
+                                                       unsigned int sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len)
+{
+    return csum_fold (csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
+                                                     struct in6_addr *daddr,
+                                                     __u32 len,
+                                                     unsigned short proto,
+                                                     unsigned int sum)
+{
+        unsigned int __dummy;
+        __asm__("l32i   %1, %2, 0\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %2, 4\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %2, 8\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %2, 12\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %3, 0\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %3, 4\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %3, 8\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "l32i   %1, %3, 12\n\t"
+                "add    %0, %0, %1\n\t"
+                "bgeu   %0, %1, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "add    %0, %0, %4\n\t"
+                "bgeu   %0, %4, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                "add    %0, %0, %5\n\t"
+                "bgeu   %0, %5, 1f\n\t"
+                "addi   %0, %0, 1\n\t"
+                "1:\t"
+                : "=r" (sum), "=&r" (__dummy)
+                : "r" (saddr), "r" (daddr),
+                  "r" (htonl(len)), "r" (htonl(proto)), "0" (sum));
+
+        return csum_fold(sum);
+}
+
+/*
+ *      Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static __inline__ unsigned int csum_and_copy_to_user (const char *src, char *dst,
+                                    int len, int sum, int *err_ptr)
+{
+        if (access_ok(VERIFY_WRITE, dst, len))
+                return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr);
+
+        if (len)
+                *err_ptr = -EFAULT;
+
+        return -1; /* invalid checksum */
+}
+#endif
diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h
new file mode 100644
index 000000000000..a91b96dc0efe
--- /dev/null
+++ b/include/asm-xtensa/coprocessor.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm-xtensa/cpextra.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_COPROCESSOR_H
+#define _XTENSA_COPROCESSOR_H
+
+#include <xtensa/config/core.h>
+
+#define XTOFS(last_start,last_size,align) \
+        ((last_start+last_size+align-1) & -align)
+
+#define XTENSA_CP_EXTRA_OFFSET  0
+#define XTENSA_CP_EXTRA_ALIGN   XCHAL_EXTRA_SA_ALIGN
+
+#define XTENSA_CPE_CP0_OFFSET   \
+        XTOFS(XTENSA_CP_EXTRA_OFFSET, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
+#define XTENSA_CPE_CP1_OFFSET   \
+        XTOFS(XTENSA_CPE_CP0_OFFSET, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
+#define XTENSA_CPE_CP2_OFFSET   \
+        XTOFS(XTENSA_CPE_CP1_OFFSET, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
+#define XTENSA_CPE_CP3_OFFSET   \
+        XTOFS(XTENSA_CPE_CP2_OFFSET, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
+#define XTENSA_CPE_CP4_OFFSET   \
+        XTOFS(XTENSA_CPE_CP3_OFFSET, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
+#define XTENSA_CPE_CP5_OFFSET   \
+        XTOFS(XTENSA_CPE_CP4_OFFSET, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
+#define XTENSA_CPE_CP6_OFFSET   \
+        XTOFS(XTENSA_CPE_CP5_OFFSET, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
+#define XTENSA_CPE_CP7_OFFSET   \
+        XTOFS(XTENSA_CPE_CP6_OFFSET, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
+#define XTENSA_CP_EXTRA_SIZE    \
+        XTOFS(XTENSA_CPE_CP7_OFFSET, XCHAL_CP7_SA_SIZE, 16)
+
+#if XCHAL_CP_NUM > 0
+# ifndef __ASSEMBLY__
+/*
+ * Tasks that own contents of (last user) each coprocessor.
+ * Entries are 0 for not-owned or non-existent coprocessors.
+ * Note: The size of this structure is fixed to 8 bytes in entry.S
+ */
+typedef struct {
+        struct task_struct *owner;      /* owner */
+        int offset;                     /* offset in cpextra space. */
+} coprocessor_info_t;
+# else
+#  define COPROCESSOR_INFO_OWNER 0
+#  define COPROCESSOR_INFO_OFFSET 4
+#  define COPROCESSOR_INFO_SIZE 8
+# endif
+#endif
+
+
+#ifndef __ASSEMBLY__
+# if XCHAL_CP_NUM > 0
+struct task_struct;
+extern void release_coprocessors (struct task_struct*);
+extern void save_coprocessor_registers(void*, int);
+# else
+#  define release_coprocessors(task)
+# endif
+#endif
+
+#endif  /* _XTENSA_COPROCESSOR_H */
diff --git a/include/asm-xtensa/cpumask.h b/include/asm-xtensa/cpumask.h
new file mode 100644
index 000000000000..ebeede397db3
--- /dev/null
+++ b/include/asm-xtensa/cpumask.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/cpumask.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CPUMASK_H
+#define _XTENSA_CPUMASK_H
+
+#include <asm-generic/cpumask.h>
+
+#endif /* _XTENSA_CPUMASK_H */
diff --git a/include/asm-xtensa/cputime.h b/include/asm-xtensa/cputime.h
new file mode 100644
index 000000000000..a7fb864a50ae
--- /dev/null
+++ b/include/asm-xtensa/cputime.h
@@ -0,0 +1,6 @@
+#ifndef _XTENSA_CPUTIME_H
+#define _XTENSA_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* _XTENSA_CPUTIME_H */
diff --git a/include/asm-xtensa/current.h b/include/asm-xtensa/current.h
new file mode 100644
index 000000000000..8d1eb5d78649
--- /dev/null
+++ b/include/asm-xtensa/current.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-xtensa/current.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CURRENT_H
+#define _XTENSA_CURRENT_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct *get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current get_current()
+
+#else
+
+#define CURRENT_SHIFT 13
+
+#define GET_CURRENT(reg,sp)             \
+        GET_THREAD_INFO(reg,sp);        \
+        l32i reg, reg, TI_TASK          \
+
+#endif
+
+
+#endif /* XTENSA_CURRENT_H */
diff --git a/include/asm-xtensa/delay.h b/include/asm-xtensa/delay.h
new file mode 100644
index 000000000000..1bc601ec3621
--- /dev/null
+++ b/include/asm-xtensa/delay.h
@@ -0,0 +1,50 @@
+/*
+ * include/asm-xtensa/delay.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ *
+ */
+
+#ifndef _XTENSA_DELAY_H
+#define _XTENSA_DELAY_H
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/param.h>
+
+extern unsigned long loops_per_jiffy;
+
+static inline void __delay(unsigned long loops)
+{
+  /* 2 cycles per loop. */
+  __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
+                        : "=r" (loops) : "0" (loops));
+}
+
+static __inline__ u32 xtensa_get_ccount(void)
+{
+        u32 ccount;
+        asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount));
+        return ccount;
+}
+
+/* For SMP/NUMA systems, change boot_cpu_data to something like
+ * local_cpu_data->... where local_cpu_data points to the current
+ * cpu. */
+
+static __inline__ void udelay (unsigned long usecs)
+{
+        unsigned long start = xtensa_get_ccount();
+        unsigned long cycles = usecs * (loops_per_jiffy / (1000000UL / HZ));
+
+        /* Note: all variables are unsigned (can wrap around)! */
+        while (((unsigned long)xtensa_get_ccount()) - start < cycles)
+                ;
+}
+
+#endif
+
diff --git a/include/asm-xtensa/div64.h b/include/asm-xtensa/div64.h
new file mode 100644
index 000000000000..c4a105776383
--- /dev/null
+++ b/include/asm-xtensa/div64.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm-xtensa/div64.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_DIV64_H
+#define _XTENSA_DIV64_H
+
+#define do_div(n,base) ({ \
+        int __res = n % ((unsigned int) base); \
+        n /= (unsigned int) base; \
+        __res; })
+
+#endif
diff --git a/include/asm-xtensa/dma-mapping.h b/include/asm-xtensa/dma-mapping.h
new file mode 100644
index 000000000000..e86a206f1209
--- /dev/null
+++ b/include/asm-xtensa/dma-mapping.h
@@ -0,0 +1,182 @@
+/*
+ * include/asm-xtensa/dma_mapping.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_DMA_MAPPING_H
+#define _XTENSA_DMA_MAPPING_H
+
+#include <asm/scatterlist.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <linux/mm.h>
+
+/*
+ * DMA-consistent mapping functions.
+ */
+
+extern void *consistent_alloc(int, size_t, dma_addr_t, unsigned long);
+extern void consistent_free(void*, size_t, dma_addr_t);
+extern void consistent_sync(void*, size_t, int);
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, int flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+               enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+        consistent_sync(ptr, size, direction);
+        return virt_to_phys(ptr);
+}
+
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                 enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+}
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+           enum dma_data_direction direction)
+{
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for (i = 0; i < nents; i++, sg++ ) {
+                BUG_ON(!sg->page);
+
+                sg->dma_address = page_to_phys(sg->page) + sg->offset;
+                consistent_sync(page_address(sg->page) + sg->offset,
+                                sg->length, direction);
+        }
+
+        return nents;
+}
+
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page, unsigned long offset,
+             size_t size, enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+        return (dma_addr_t)(page_to_pfn(page)) * PAGE_SIZE + offset;
+}
+
+static inline void
+dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
+               enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+}
+
+
+static inline void
+dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
+             enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+}
+
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
+{
+        consistent_sync((void *)bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
+{
+        consistent_sync((void *)bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                      unsigned long offset, size_t size,
+                      enum dma_data_direction direction)
+{
+
+        consistent_sync((void *)bus_to_virt(dma_handle)+offset,size,direction);
+}
+
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+                      unsigned long offset, size_t size,
+                      enum dma_data_direction direction)
+{
+
+        consistent_sync((void *)bus_to_virt(dma_handle)+offset,size,direction);
+}
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
+                 enum dma_data_direction dir)
+{
+        int i;
+        for (i = 0; i < nelems; i++, sg++)
+                consistent_sync(page_address(sg->page) + sg->offset,
+                                sg->length, dir);
+}
+
+static inline void
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
+                 enum dma_data_direction dir)
+{
+        int i;
+        for (i = 0; i < nelems; i++, sg++)
+                consistent_sync(page_address(sg->page) + sg->offset,
+                                sg->length, dir);
+}
+static inline int
+dma_mapping_error(dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+static inline int
+dma_supported(struct device *dev, u64 mask)
+{
+        return 1;
+}
+
+static inline int
+dma_set_mask(struct device *dev, u64 mask)
+{
+        if(!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+static inline int
+dma_get_cache_alignment(void)
+{
+        return L1_CACHE_BYTES;
+}
+
+#define dma_is_consistent(d)    (1)
+
+static inline void
+dma_cache_sync(void *vaddr, size_t size,
+               enum dma_data_direction direction)
+{
+        consistent_sync(vaddr, size, direction);
+}
+
+#endif  /* _XTENSA_DMA_MAPPING_H */
diff --git a/include/asm-xtensa/dma.h b/include/asm-xtensa/dma.h
new file mode 100644
index 000000000000..1c22b0234586
--- /dev/null
+++ b/include/asm-xtensa/dma.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-xtensa/dma.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_DMA_H
+#define _XTENSA_DMA_H
+
+#include <linux/config.h>
+#include <asm/io.h>             /* need byte IO */
+#include <xtensa/config/core.h>
+
+/*
+ * This is only to be defined if we have PC-like DMA.
+ * By default this is not true on an Xtensa processor,
+ * however on boards with a PCI bus, such functionality
+ * might be emulated externally.
+ *
+ * NOTE:  there still exists driver code that assumes
+ * this is defined, eg. drivers/sound/soundcard.c (as of 2.4).
+ */
+#define MAX_DMA_CHANNELS        8
+
+/*
+ * The maximum virtual address to which DMA transfers
+ * can be performed on this platform.
+ *
+ * NOTE: This is board (platform) specific, not processor-specific!
+ *
+ * NOTE: This assumes DMA transfers can only be performed on
+ *      the section of physical memory contiguously mapped in virtual
+ *      space for the kernel.  For the Xtensa architecture, this
+ *      means the maximum possible size of this DMA area is
+ *      the size of the statically mapped kernel segment
+ *      (XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB.
+ *
+ * NOTE: When the entire KSEG area is DMA capable, we substract
+ *      one from the max address so that the virt_to_phys() macro
+ *      works correctly on the address (otherwise the address
+ *      enters another area, and virt_to_phys() may not return
+ *      the value desired).
+ */
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + XCHAL_KSEG_CACHED_SIZE - 1)
+
+/* Reserve and release a DMA channel */
+extern int request_dma(unsigned int dmanr, const char * device_id);
+extern void free_dma(unsigned int dmanr);
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+
+#endif
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
new file mode 100644
index 000000000000..64f1f53874fe
--- /dev/null
+++ b/include/asm-xtensa/elf.h
@@ -0,0 +1,222 @@
+/*
+ * include/asm-xtensa/elf.h
+ *
+ * ELF register definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ELF_H
+#define _XTENSA_ELF_H
+
+#include <asm/ptrace.h>
+#include <asm/coprocessor.h>
+#include <xtensa/config/core.h>
+
+/* Xtensa processor ELF architecture-magic number */
+
+#define EM_XTENSA       94
+#define EM_XTENSA_OLD   0xABC7
+
+/* ELF register definitions. This is needed for core dump support.  */
+
+/*
+ * elf_gregset_t contains the application-level state in the following order:
+ * Processor info:      config_version, cpuxy
+ * Processor state:     pc, ps, exccause, excvaddr, wb, ws,
+ *                      lbeg, lend, lcount, sar
+ * GP regs:             ar0 - arXX
+ */
+
+typedef unsigned long elf_greg_t;
+
+typedef struct {
+        elf_greg_t xchal_config_id0;
+        elf_greg_t xchal_config_id1;
+        elf_greg_t cpux;
+        elf_greg_t cpuy;
+        elf_greg_t pc;
+        elf_greg_t ps;
+        elf_greg_t exccause;
+        elf_greg_t excvaddr;
+        elf_greg_t windowbase;
+        elf_greg_t windowstart;
+        elf_greg_t lbeg;
+        elf_greg_t lend;
+        elf_greg_t lcount;
+        elf_greg_t sar;
+        elf_greg_t syscall;
+        elf_greg_t ar[XCHAL_NUM_AREGS];
+} xtensa_gregset_t;
+
+#define ELF_NGREG       (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/*
+ *  Compute the size of the coprocessor and extra state layout (register info)
+ *  table (in bytes).
+ *  This is actually the maximum size of the table, as opposed to the size,
+ *  which is available from the _xtensa_reginfo_table_size global variable.
+ *
+ *  (See also arch/xtensa/kernel/coprocessor.S)
+ *
+ */
+
+#ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
+# define XTENSA_CPE_LTABLE_SIZE         0
+#else
+# define XTENSA_CPE_SEGMENT(num)        (num ? (1+num) : 0)
+# define XTENSA_CPE_LTABLE_ENTRIES      \
+                ( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM)   \
+                + XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM)   \
+                + 1             /* final entry */                       \
+                )
+# define XTENSA_CPE_LTABLE_SIZE         (XTENSA_CPE_LTABLE_ENTRIES * 8)
+#endif
+
+
+/*
+ * Instantiations of the elf_fpregset_t type contain, in most
+ * architectures, the floating point (FPU) register set.
+ * For Xtensa, this type is extended to contain all custom state,
+ * ie. coprocessor and "extra" (non-coprocessor) state (including,
+ * for example, TIE-defined states and register files; as well
+ * as other optional processor state).
+ * This includes FPU state if a floating-point coprocessor happens
+ * to have been configured within the Xtensa processor.
+ *
+ * TOTAL_FPREGS_SIZE is the required size (without rounding)
+ * of elf_fpregset_t.  It provides space for the following:
+ *
+ *  a)  32-bit mask of active coprocessors for this task (similar
+ *      to CPENABLE in single-threaded Xtensa processor systems)
+ *
+ *  b)  table describing the layout of custom states (ie. of
+ *      individual registers, etc) within the save areas
+ *
+ *  c)  save areas for each coprocessor and for non-coprocessor
+ *      ("extra") state
+ *
+ * Note that save areas may require up to 16-byte alignment when
+ * accessed by save/restore sequences.  We do not need to ensure
+ * such alignment in an elf_fpregset_t structure because custom
+ * state is not directly loaded/stored into it; rather, save area
+ * contents are copied to elf_fpregset_t from the active save areas
+ * (see 'struct task_struct' definition in processor.h for that)
+ * using memcpy().  But we do allow space for such alignment,
+ * to allow optimizations of layout and copying.
+ */
+
+#define TOTAL_FPREGS_SIZE                                               \
+        (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
+#define ELF_NFPREG                                                      \
+        ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
+
+typedef unsigned int elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+#define ELF_CORE_COPY_REGS(_eregs, _pregs)                              \
+        xtensa_elf_core_copy_regs (&_eregs, _pregs);
+
+extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+
+#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA )  || \
+                            ( (x)->e_machine == EM_XTENSA_OLD ) )
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+
+#ifdef __XTENSA_EL__
+# define ELF_DATA       ELFDATA2LSB
+#elif defined(__XTENSA_EB__)
+# define ELF_DATA       ELFDATA2MSB
+#else
+# error processor byte order undefined!
+#endif
+
+#define ELF_CLASS       ELFCLASS32
+#define ELF_ARCH        EM_XTENSA
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/*
+ * This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+ * use of this is to invoke "./ld.so someprog" to test out a new version of
+ * the loader.  We need to make sure that it is out of the way of the program
+ * that it will "exec", and that there is sufficient room for the brk.
+ */
+
+#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
+
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this CPU supports.  This could be done in user space,
+ * but it's not easy, and we've already done it here.
+ */
+
+#define ELF_HWCAP       (0)
+
+/*
+ * This yields a string that ld.so will use to load implementation
+ * specific libraries for optimization.  This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
+ * For the moment, we have only optimizations for the Intel generations,
+ * but that could change...
+ */
+
+#define ELF_PLATFORM  (NULL)
+
+/*
+ * The Xtensa processor ABI says that when the program starts, a2
+ * contains a pointer to a function which might be registered using
+ * `atexit'.  This provides a mean for the dynamic linker to call
+ * DT_FINI functions for shared libraries that have been loaded before
+ * the code runs.
+ *
+ * A value of 0 tells we have no such handler.
+ *
+ * We might as well make sure everything else is cleared too (except
+ * for the stack pointer in a1), just to make things more
+ * deterministic.  Also, clearing a0 terminates debugger backtraces.
+ */
+
+#define ELF_PLAT_INIT(_r, load_addr) \
+  do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0;  _r->areg[3]=0;  \
+       _r->areg[4]=0;  _r->areg[5]=0;    _r->areg[6]=0;  _r->areg[7]=0;  \
+       _r->areg[8]=0;  _r->areg[9]=0;    _r->areg[10]=0; _r->areg[11]=0; \
+       _r->areg[12]=0; _r->areg[13]=0;   _r->areg[14]=0; _r->areg[15]=0; \
+  } while (0)
+
+#ifdef __KERNEL__
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
+
+extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*,
+                          struct task_struct*);
+extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*,
+                             struct task_struct*);
+extern void do_save_fpregs (elf_fpregset_t*, struct pt_regs*,
+                            struct task_struct*);
+extern int do_restore_fpregs (elf_fpregset_t*, struct pt_regs*,
+                              struct task_struct*);
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_ELF_H */
diff --git a/include/asm-xtensa/emergency-restart.h b/include/asm-xtensa/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-xtensa/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-xtensa/errno.h b/include/asm-xtensa/errno.h
new file mode 100644
index 000000000000..a0f3b96b79b4
--- /dev/null
+++ b/include/asm-xtensa/errno.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/errno.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2002 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_ERRNO_H
+#define _XTENSA_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif  /* _XTENSA_ERRNO_H */
diff --git a/include/asm-xtensa/fcntl.h b/include/asm-xtensa/fcntl.h
new file mode 100644
index 000000000000..ec066ae96caf
--- /dev/null
+++ b/include/asm-xtensa/fcntl.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-xtensa/fcntl.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_FCNTL_H
+#define _XTENSA_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_APPEND        0x0008
+#define O_SYNC          0x0010
+#define O_NONBLOCK      0x0080
+#define O_CREAT         0x0100  /* not fcntl */
+#define O_EXCL          0x0400  /* not fcntl */
+#define O_NOCTTY        0x0800  /* not fcntl */
+#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
+#define O_LARGEFILE     0x2000  /* allow large file opens - currently ignored */
+#define O_DIRECT        0x8000  /* direct disk access hint - currently ignored*/
+#define O_NOATIME       0x100000
+
+#define F_GETLK         14
+#define F_GETLK64       15
+#define F_SETLK         6
+#define F_SETLKW        7
+#define F_SETLK64       16
+#define F_SETLKW64      17
+
+#define F_SETOWN        24      /*  for sockets. */
+#define F_GETOWN        23      /*  for sockets. */
+
+typedef struct flock {
+        short l_type;
+        short l_whence;
+        __kernel_off_t l_start;
+        __kernel_off_t l_len;
+        long  l_sysid;
+        __kernel_pid_t l_pid;
+        long  pad[4];
+} flock_t;
+
+struct flock64 {
+        short  l_type;
+        short  l_whence;
+        __kernel_off_t l_start;
+        __kernel_off_t l_len;
+        pid_t  l_pid;
+};
+
+#define HAVE_ARCH_STRUCT_FLOCK
+#define HAVE_ARCH_STRUCT_FLOCK64
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _XTENSA_FCNTL_H */
diff --git a/include/asm-xtensa/fixmap.h b/include/asm-xtensa/fixmap.h
new file mode 100644
index 000000000000..4423b8ad4954
--- /dev/null
+++ b/include/asm-xtensa/fixmap.h
@@ -0,0 +1,252 @@
+/*
+ * include/asm-xtensa/fixmap.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_FIXMAP_H
+#define _XTENSA_FIXMAP_H
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_MMU
+
+/*
+ * Here we define all the compile-time virtual addresses.
+ */
+
+#if XCHAL_SEG_MAPPABLE_VADDR != 0
+# error "Current port requires virtual user space starting at 0"
+#endif
+#if XCHAL_SEG_MAPPABLE_SIZE < 0x80000000
+# error "Current port requires at least 0x8000000 bytes for user space"
+#endif
+
+/* Verify instruction/data ram/rom and xlmi don't overlay vmalloc space. */
+
+#define __IN_VMALLOC(addr)                                              \
+        (((addr) >= VMALLOC_START) && ((addr) < VMALLOC_END))
+#define __SPAN_VMALLOC(start,end)                                       \
+        (((start) < VMALLOC_START) && ((end) >= VMALLOC_END))
+#define INSIDE_VMALLOC(start,end)                                       \
+        (__IN_VMALLOC((start)) || __IN_VMALLOC(end) || __SPAN_VMALLOC((start),(end)))
+
+#if XCHAL_NUM_INSTROM
+# if XCHAL_NUM_INSTROM == 1
+#  if INSIDE_VMALLOC(XCHAL_INSTROM0_VADDR,XCHAL_INSTROM0_VADDR+XCHAL_INSTROM0_SIZE)
+#   error vmalloc range conflicts with instrom0
+#  endif
+# endif
+# if XCHAL_NUM_INSTROM == 2
+#  if INSIDE_VMALLOC(XCHAL_INSTROM1_VADDR,XCHAL_INSTROM1_VADDR+XCHAL_INSTROM1_SIZE)
+#   error vmalloc range conflicts with instrom1
+#  endif
+# endif
+#endif
+
+#if XCHAL_NUM_INSTRAM
+# if XCHAL_NUM_INSTRAM == 1
+#  if INSIDE_VMALLOC(XCHAL_INSTRAM0_VADDR,XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE)
+#   error vmalloc range conflicts with instram0
+#  endif
+# endif
+# if XCHAL_NUM_INSTRAM == 2
+#  if INSIDE_VMALLOC(XCHAL_INSTRAM1_VADDR,XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE)
+#   error vmalloc range conflicts with instram1
+#  endif
+# endif
+#endif
+
+#if XCHAL_NUM_DATAROM
+# if XCHAL_NUM_DATAROM == 1
+#  if INSIDE_VMALLOC(XCHAL_DATAROM0_VADDR,XCHAL_DATAROM0_VADDR+XCHAL_DATAROM0_SIZE)
+#   error vmalloc range conflicts with datarom0
+#  endif
+# endif
+# if XCHAL_NUM_DATAROM == 2
+#  if INSIDE_VMALLOC(XCHAL_DATAROM1_VADDR,XCHAL_DATAROM1_VADDR+XCHAL_DATAROM1_SIZE)
+#   error vmalloc range conflicts with datarom1
+#  endif
+# endif
+#endif
+
+#if XCHAL_NUM_DATARAM
+# if XCHAL_NUM_DATARAM == 1
+#  if INSIDE_VMALLOC(XCHAL_DATARAM0_VADDR,XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE)
+#   error vmalloc range conflicts with dataram0
+#  endif
+# endif
+# if XCHAL_NUM_DATARAM == 2
+#  if INSIDE_VMALLOC(XCHAL_DATARAM1_VADDR,XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE)
+#   error vmalloc range conflicts with dataram1
+#  endif
+# endif
+#endif
+
+#if XCHAL_NUM_XLMI
+# if XCHAL_NUM_XLMI == 1
+#  if INSIDE_VMALLOC(XCHAL_XLMI0_VADDR,XCHAL_XLMI0_VADDR+XCHAL_XLMI0_SIZE)
+#   error vmalloc range conflicts with xlmi0
+#  endif
+# endif
+# if XCHAL_NUM_XLMI == 2
+#  if INSIDE_VMALLOC(XCHAL_XLMI1_VADDR,XCHAL_XLMI1_VADDR+XCHAL_XLMI1_SIZE)
+#   error vmalloc range conflicts with xlmi1
+#  endif
+# endif
+#endif
+
+#if (XCHAL_NUM_INSTROM > 2) || \
+    (XCHAL_NUM_INSTRAM > 2) || \
+    (XCHAL_NUM_DATARAM > 2) || \
+    (XCHAL_NUM_DATAROM > 2) || \
+    (XCHAL_NUM_XLMI    > 2)
+# error Insufficient checks on vmalloc above for more than 2 devices
+#endif
+
+/*
+ * USER_VM_SIZE does not necessarily equal TASK_SIZE.  We bumped
+ * TASK_SIZE down to 0x4000000 to simplify the handling of windowed
+ * call instructions (currently limited to a range of 1 GByte).  User
+ * tasks may very well reclaim the VM space from 0x40000000 to
+ * 0x7fffffff in the future, so we do not want the kernel becoming
+ * accustomed to having any of its stuff (e.g., page tables) in this
+ * region.  This VM region is no-man's land for now.
+ */
+
+#define USER_VM_START           XCHAL_SEG_MAPPABLE_VADDR
+#define USER_VM_SIZE            0x80000000
+
+/*  Size of page table:  */
+
+#define PGTABLE_SIZE_BITS       (32 - XCHAL_MMU_MIN_PTE_PAGE_SIZE + 2)
+#define PGTABLE_SIZE            (1L << PGTABLE_SIZE_BITS)
+
+/*  All kernel-mappable space:  */
+
+#define KERNEL_ALLMAP_START     (USER_VM_START + USER_VM_SIZE)
+#define KERNEL_ALLMAP_SIZE      (XCHAL_SEG_MAPPABLE_SIZE - KERNEL_ALLMAP_START)
+
+/*  Carve out page table at start of kernel-mappable area:  */
+
+#if KERNEL_ALLMAP_SIZE < PGTABLE_SIZE
+#error "Gimme some space for page table!"
+#endif
+#define PGTABLE_START           KERNEL_ALLMAP_START
+
+/*  Remaining kernel-mappable space:  */
+
+#define KERNEL_MAPPED_START     (KERNEL_ALLMAP_START + PGTABLE_SIZE)
+#define KERNEL_MAPPED_SIZE      (KERNEL_ALLMAP_SIZE - PGTABLE_SIZE)
+
+#if KERNEL_MAPPED_SIZE < 0x01000000     /* 16 MB is arbitrary for now */
+# error "Shouldn't the kernel have at least *some* mappable space?"
+#endif
+
+#define MAX_LOW_MEMORY          XCHAL_KSEG_CACHED_SIZE
+
+#endif
+
+/*
+ *  Some constants used elsewhere, but perhaps only in Xtensa header
+ *  files, so maybe we can get rid of some and access compile-time HAL
+ *  directly...
+ *
+ *  Note:  We assume that system RAM is located at the very start of the
+ *         kernel segments !!
+ */
+#define KERNEL_VM_LOW           XCHAL_KSEG_CACHED_VADDR
+#define KERNEL_VM_HIGH          XCHAL_KSEG_BYPASS_VADDR
+#define KERNEL_SPACE            XCHAL_KSEG_CACHED_VADDR
+
+/*
+ * Returns the physical/virtual addresses of the kernel space
+ * (works with the cached kernel segment only, which is the
+ *  one normally used for kernel operation).
+ */
+
+/*                      PHYSICAL        BYPASS          CACHED
+ *
+ *  bypass vaddr        bypass paddr    *               cached vaddr
+ *  cached vaddr        cached paddr    bypass vaddr    *
+ *  bypass paddr        *               bypass vaddr    cached vaddr
+ *  cached paddr        *               bypass vaddr    cached vaddr
+ *  other               *               *               *
+ */
+
+#define PHYSADDR(a)                                                           \
+(((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR                                    \
+  && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
+    (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_BYPASS_PADDR :       \
+    ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR                                 \
+     && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
+        (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_CACHED_PADDR :   \
+        (unsigned)(a))
+
+#define BYPASS_ADDR(a)                                                        \
+(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR                                    \
+  && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
+    (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_VADDR :       \
+    ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR                                 \
+     && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
+        (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_BYPASS_VADDR :   \
+        ((unsigned)(a) >= XCHAL_KSEG_CACHED_VADDR                             \
+         && (unsigned)(a) < XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_CACHED_SIZE)?  \
+            (unsigned)(a) - XCHAL_KSEG_CACHED_VADDR+XCHAL_KSEG_BYPASS_VADDR:  \
+            (unsigned)(a))
+
+#define CACHED_ADDR(a)                                                        \
+(((unsigned)(a) >= XCHAL_KSEG_BYPASS_PADDR                                    \
+  && (unsigned)(a) < XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_BYPASS_SIZE) ?      \
+    (unsigned)(a) - XCHAL_KSEG_BYPASS_PADDR + XCHAL_KSEG_CACHED_VADDR :       \
+    ((unsigned)(a) >= XCHAL_KSEG_CACHED_PADDR                                 \
+     && (unsigned)(a) < XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_SIZE) ?   \
+        (unsigned)(a) - XCHAL_KSEG_CACHED_PADDR + XCHAL_KSEG_CACHED_VADDR :   \
+        ((unsigned)(a) >= XCHAL_KSEG_BYPASS_VADDR                             \
+         && (unsigned)(a) < XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_BYPASS_SIZE) ? \
+            (unsigned)(a) - XCHAL_KSEG_BYPASS_VADDR+XCHAL_KSEG_CACHED_VADDR : \
+            (unsigned)(a))
+
+#define PHYSADDR_IO(a)                                                        \
+(((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR                                     \
+  && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
+    (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_PADDR :         \
+    ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR                                  \
+     && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ?     \
+        (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_PADDR :     \
+        (unsigned)(a))
+
+#define BYPASS_ADDR_IO(a)                                                     \
+(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR                                     \
+  && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
+    (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_VADDR :         \
+    ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR                                  \
+     && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ?     \
+        (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_BYPASS_VADDR :     \
+        ((unsigned)(a) >= XCHAL_KIO_CACHED_VADDR                              \
+         && (unsigned)(a) < XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_CACHED_SIZE) ? \
+            (unsigned)(a) - XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_BYPASS_VADDR : \
+            (unsigned)(a))
+
+#define CACHED_ADDR_IO(a)                                                     \
+(((unsigned)(a) >= XCHAL_KIO_BYPASS_PADDR                                     \
+  && (unsigned)(a) < XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_BYPASS_SIZE) ?        \
+    (unsigned)(a) - XCHAL_KIO_BYPASS_PADDR + XCHAL_KIO_CACHED_VADDR :         \
+    ((unsigned)(a) >= XCHAL_KIO_CACHED_PADDR                                  \
+     && (unsigned)(a) < XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_SIZE) ?     \
+        (unsigned)(a) - XCHAL_KIO_CACHED_PADDR + XCHAL_KIO_CACHED_VADDR :     \
+        ((unsigned)(a) >= XCHAL_KIO_BYPASS_VADDR                              \
+         && (unsigned)(a) < XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_BYPASS_SIZE) ? \
+            (unsigned)(a) - XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_CACHED_VADDR : \
+            (unsigned)(a))
+
+#endif /* _XTENSA_ADDRSPACE_H */
+
+
+
+
+
diff --git a/include/asm-xtensa/hardirq.h b/include/asm-xtensa/hardirq.h
new file mode 100644
index 000000000000..e07c76c36b95
--- /dev/null
+++ b/include/asm-xtensa/hardirq.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-xtensa/hardirq.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2002 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_HARDIRQ_H
+#define _XTENSA_HARDIRQ_H
+
+#include <linux/config.h>
+#include <linux/cache.h>
+#include <asm/irq.h>
+
+/* headers.S is sensitive to the offsets of these fields */
+typedef struct {
+        unsigned int __softirq_pending;
+        unsigned int __syscall_count;
+        struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
+        unsigned int __nmi_count;              /* arch dependent */
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+#endif  /* _XTENSA_HARDIRQ_H */
diff --git a/include/asm-xtensa/highmem.h b/include/asm-xtensa/highmem.h
new file mode 100644
index 000000000000..0a046ca5a687
--- /dev/null
+++ b/include/asm-xtensa/highmem.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-xtensa/highmem.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_HIGHMEM_H
+#define _XTENSA_HIGHMEM_H
+
+extern void flush_cache_kmaps(void);
+
+#endif
+
diff --git a/include/asm-xtensa/hw_irq.h b/include/asm-xtensa/hw_irq.h
new file mode 100644
index 000000000000..ccf436249eaa
--- /dev/null
+++ b/include/asm-xtensa/hw_irq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-xtensa/hw_irq.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2002 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_HW_IRQ_H
+#define _XTENSA_HW_IRQ_H
+
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
+{
+}
+
+#endif
diff --git a/include/asm-xtensa/ide.h b/include/asm-xtensa/ide.h
new file mode 100644
index 000000000000..b523cd4a486e
--- /dev/null
+++ b/include/asm-xtensa/ide.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-xtensa/ide.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1996  Linus Torvalds & authors
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_IDE_H
+#define _XTENSA_IDE_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#ifndef MAX_HWIFS
+# define MAX_HWIFS      1
+#endif
+
+static __inline__ int ide_default_irq(unsigned long base)
+{
+        /* Unsupported! */
+        return 0;
+}
+
+static __inline__ unsigned long ide_default_io_base(int index)
+{
+        /* Unsupported! */
+        return 0;
+}
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_IDE_H */
diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h
new file mode 100644
index 000000000000..c5c13985bbe1
--- /dev/null
+++ b/include/asm-xtensa/io.h
@@ -0,0 +1,197 @@
+/*
+ * linux/include/asm-xtensa/io.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_IO_H
+#define _XTENSA_IO_H
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <asm/byteorder.h>
+
+#include <linux/types.h>
+#include <asm/fixmap.h>
+
+#define _IO_BASE 0
+
+
+/*
+ * swap functions to change byte order from little-endian to big-endian and
+ * vice versa.
+ */
+
+static inline unsigned short _swapw (unsigned short v)
+{
+        return (v << 8) | (v >> 8);
+}
+
+static inline unsigned int _swapl (unsigned int v)
+{
+        return (v << 24) | ((v & 0xff00) << 8) | ((v >> 8) & 0xff00) | (v >> 24);
+}
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are trivial on the 1:1 Linux/Xtensa mapping
+ */
+
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+        return PHYSADDR((unsigned long)address);
+}
+
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void*) CACHED_ADDR(address);
+}
+
+/*
+ * IO bus memory addresses are also 1:1 with the physical address
+ */
+
+static inline unsigned long virt_to_bus(volatile void * address)
+{
+        return PHYSADDR((unsigned long)address);
+}
+
+static inline void * bus_to_virt (unsigned long address)
+{
+        return (void *) CACHED_ADDR(address);
+}
+
+/*
+ * Change "struct page" to physical address.
+ */
+
+static inline void *ioremap(unsigned long offset, unsigned long size)
+{
+        return (void *) CACHED_ADDR_IO(offset);
+}
+
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+{
+        return (void *) BYPASS_ADDR_IO(offset);
+}
+
+static inline void iounmap(void *addr)
+{
+}
+
+/*
+ * Generic I/O
+ */
+
+#define readb(addr) \
+        ({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
+#define readw(addr) \
+        ({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
+#define readl(addr) \
+        ({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
+#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b))
+
+static inline __u8 __raw_readb(const volatile void __iomem *addr)
+{
+          return *(__force volatile __u8 *)(addr);
+}
+static inline __u16 __raw_readw(const volatile void __iomem *addr)
+{
+          return *(__force volatile __u16 *)(addr);
+}
+static inline __u32 __raw_readl(const volatile void __iomem *addr)
+{
+          return *(__force volatile __u32 *)(addr);
+}
+static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
+{
+          *(__force volatile __u8 *)(addr) = b;
+}
+static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
+{
+          *(__force volatile __u16 *)(addr) = b;
+}
+static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
+{
+          *(__force volatile __u32 *)(addr) = b;
+}
+
+
+
+
+/* These are the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl, the "string" versions
+ * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
+ * inb_p/inw_p/...
+ * The macros don't do byte-swapping.
+ */
+
+#define inb(port)               readb((u8 *)((port)+_IO_BASE))
+#define outb(val, port)         writeb((val),(u8 *)((unsigned long)(port)+_IO_BASE))
+#define inw(port)               readw((u16 *)((port)+_IO_BASE))
+#define outw(val, port)         writew((val),(u16 *)((unsigned long)(port)+_IO_BASE))
+#define inl(port)               readl((u32 *)((port)+_IO_BASE))
+#define outl(val, port)         writel((val),(u32 *)((unsigned long)(port)))
+
+#define inb_p(port)             inb((port))
+#define outb_p(val, port)       outb((val), (port))
+#define inw_p(port)             inw((port))
+#define outw_p(val, port)       outw((val), (port))
+#define inl_p(port)             inl((port))
+#define outl_p(val, port)       outl((val), (port))
+
+extern void insb (unsigned long port, void *dst, unsigned long count);
+extern void insw (unsigned long port, void *dst, unsigned long count);
+extern void insl (unsigned long port, void *dst, unsigned long count);
+extern void outsb (unsigned long port, const void *src, unsigned long count);
+extern void outsw (unsigned long port, const void *src, unsigned long count);
+extern void outsl (unsigned long port, const void *src, unsigned long count);
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+
+/* At this point the Xtensa doesn't provide byte swap instructions */
+
+#ifdef __XTENSA_EB__
+# define in_8(addr) (*(u8*)(addr))
+# define in_le16(addr) _swapw(*(u16*)(addr))
+# define in_le32(addr) _swapl(*(u32*)(addr))
+# define out_8(b, addr) *(u8*)(addr) = (b)
+# define out_le16(b, addr) *(u16*)(addr) = _swapw(b)
+# define out_le32(b, addr) *(u32*)(addr) = _swapl(b)
+#elif defined(__XTENSA_EL__)
+# define in_8(addr)  (*(u8*)(addr))
+# define in_le16(addr) (*(u16*)(addr))
+# define in_le32(addr) (*(u32*)(addr))
+# define out_8(b, addr) *(u8*)(addr) = (b)
+# define out_le16(b, addr) *(u16*)(addr) = (b)
+# define out_le32(b, addr) *(u32*)(addr) = (b)
+#else
+# error processor byte order undefined!
+#endif
+
+
+/*
+ *  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ *   * access
+ *    */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ *  * Convert a virtual cached pointer to an uncached pointer
+ *   */
+#define xlate_dev_kmem_ptr(p)   p
+
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _XTENSA_IO_H */
diff --git a/include/asm-xtensa/ioctl.h b/include/asm-xtensa/ioctl.h
new file mode 100644
index 000000000000..856c605d62b1
--- /dev/null
+++ b/include/asm-xtensa/ioctl.h
@@ -0,0 +1,83 @@
+/*
+ * include/asm-xtensa/ioctl.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ *
+ * Derived from "include/asm-i386/ioctl.h"
+ */
+
+#ifndef _XTENSA_IOCTL_H
+#define _XTENSA_IOCTL_H
+
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms.  The i386 ioctl numbering scheme doesn't really enforce
+ * a type field.  De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here.  Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS     8
+#define _IOC_TYPEBITS   8
+#define _IOC_SIZEBITS   14
+#define _IOC_DIRBITS    2
+
+#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT    0
+#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits.
+ */
+#define _IOC_NONE       0U
+#define _IOC_WRITE      1U
+#define _IOC_READ       2U
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+/* used to create numbers */
+#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif
diff --git a/include/asm-xtensa/ioctls.h b/include/asm-xtensa/ioctls.h
new file mode 100644
index 000000000000..10c443435c11
--- /dev/null
+++ b/include/asm-xtensa/ioctls.h
@@ -0,0 +1,112 @@
+/*
+ * include/asm-xtensa/ioctl.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 - 2005 Tensilica Inc.
+ *
+ * Derived from "include/asm-i386/ioctls.h"
+ */
+
+#ifndef _XTENSA_IOCTLS_H
+#define _XTENSA_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+
+#define TCGETA          _IOR('t', 23, struct termio)
+#define TCSETA          _IOW('t', 24, struct termio)
+#define TCSETAW         _IOW('t', 25, struct termio)
+#define TCSETAF         _IOW('t', 28, struct termio)
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        _IO('T', 12)
+#define TIOCNXCL        _IO('T', 13)
+#define TIOCSCTTY       _IO('T', 14)
+
+#define TIOCSTI         _IOW('T', 18, char)
+#define TIOCMGET        _IOR('T', 21, unsigned int)
+#define TIOCMBIS        _IOW('T', 22, unsigned int)
+#define TIOCMBIC        _IOW('T', 23, unsigned int)
+#define TIOCMSET        _IOW('T', 24, unsigned int)
+# define TIOCM_LE       0x001
+# define TIOCM_DTR      0x002
+# define TIOCM_RTS      0x004
+# define TIOCM_ST       0x008
+# define TIOCM_SR       0x010
+# define TIOCM_CTS      0x020
+# define TIOCM_CAR      0x040
+# define TIOCM_RNG      0x080
+# define TIOCM_DSR      0x100
+# define TIOCM_CD       TIOCM_CAR
+# define TIOCM_RI       TIOCM_RNG
+
+#define TIOCGSOFTCAR    _IOR('T', 25, unsigned int)
+#define TIOCSSOFTCAR    _IOW('T', 26, unsigned int)
+#define TIOCLINUX       _IOW('T', 28, char)
+#define TIOCCONS        _IO('T', 29)
+#define TIOCGSERIAL     _IOR('T', 30, struct serial_struct)
+#define TIOCSSERIAL     _IOW('T', 31, struct serial_struct)
+#define TIOCPKT         _IOW('T', 32, int)
+# define TIOCPKT_DATA            0
+# define TIOCPKT_FLUSHREAD       1
+# define TIOCPKT_FLUSHWRITE      2
+# define TIOCPKT_STOP            4
+# define TIOCPKT_START           8
+# define TIOCPKT_NOSTOP         16
+# define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY       _IO('T', 34)
+#define TIOCSETD        _IOW('T', 35, int)
+#define TIOCGETD        _IOR('T', 36, int)
+#define TCSBRKP         _IOW('T', 37, int)   /* Needed for POSIX tcsendbreak()*/
+#define TIOCTTYGSTRUCT  _IOR('T', 38, struct tty_struct) /* For debugging only*/
+#define TIOCSBRK        _IO('T', 39)         /* BSD compatibility */
+#define TIOCCBRK        _IO('T', 40)         /* BSD compatibility */
+#define TIOCGSID        _IOR('T', 41, pid_t) /* Return the session ID of FD*/
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define TIOCSERCONFIG   _IO('T', 83)
+#define TIOCSERGWILD    _IOR('T', 84,  int)
+#define TIOCSERSWILD    _IOW('T', 85,  int)
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458               /* For debugging only */
+#define TIOCSERGETLSR   _IOR('T', 89, unsigned int) /* Get line status reg. */
+  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+# define TIOCSER_TEMT    0x01                /* Transmitter physically empty */
+#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* Get multiport config  */
+#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* Set multiport config */
+
+#define TIOCMIWAIT      _IO('T', 92) /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     _IOR('T', 93, struct async_icount) /* read serial port inline interrupt counts */
+
+#endif /* _XTENSA_IOCTLS_H */
diff --git a/include/asm-xtensa/ipcbuf.h b/include/asm-xtensa/ipcbuf.h
new file mode 100644
index 000000000000..c33aa6a42145
--- /dev/null
+++ b/include/asm-xtensa/ipcbuf.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-xtensa/ipcbuf.h
+ *
+ * The ipc64_perm structure for the Xtensa architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_IPCBUF_H
+#define _XTENSA_IPCBUF_H
+
+/*
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned long           seq;
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* _XTENSA_IPCBUF_H */
diff --git a/include/asm-xtensa/irq.h b/include/asm-xtensa/irq.h
new file mode 100644
index 000000000000..d984e955938f
--- /dev/null
+++ b/include/asm-xtensa/irq.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-xtensa/irq.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_IRQ_H
+#define _XTENSA_IRQ_H
+
+#include <linux/config.h>
+#include <asm/platform/hardware.h>
+
+#include <xtensa/config/core.h>
+
+#ifndef PLATFORM_NR_IRQS
+# define PLATFORM_NR_IRQS 0
+#endif
+#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
+#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
+
+static __inline__ int irq_canonicalize(int irq)
+{
+        return (irq);
+}
+
+struct irqaction;
+#if 0 // FIXME
+extern void disable_irq_nosync(unsigned int);
+extern void disable_irq(unsigned int);
+extern void enable_irq(unsigned int);
+#endif
+
+#endif  /* _XTENSA_IRQ_H */
diff --git a/include/asm-xtensa/kmap_types.h b/include/asm-xtensa/kmap_types.h
new file mode 100644
index 000000000000..9e822d2e3bce
--- /dev/null
+++ b/include/asm-xtensa/kmap_types.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-xtensa/kmap_types.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_KMAP_TYPES_H
+#define _XTENSA_KMAP_TYPES_H
+
+enum km_type {
+  KM_BOUNCE_READ,
+  KM_SKB_SUNRPC_DATA,
+  KM_SKB_DATA_SOFTIRQ,
+  KM_USER0,
+  KM_USER1,
+  KM_BIO_SRC_IRQ,
+  KM_BIO_DST_IRQ,
+  KM_PTE0,
+  KM_PTE1,
+  KM_IRQ0,
+  KM_IRQ1,
+  KM_SOFTIRQ0,
+  KM_SOFTIRQ1,
+  KM_TYPE_NR
+};
+
+#endif  /* _XTENSA_KMAP_TYPES_H */
diff --git a/include/asm-xtensa/linkage.h b/include/asm-xtensa/linkage.h
new file mode 100644
index 000000000000..bf2128a99d79
--- /dev/null
+++ b/include/asm-xtensa/linkage.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/linkage.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_LINKAGE_H
+#define _XTENSA_LINKAGE_H
+
+/* Nothing to do here ... */
+
+#endif  /* _XTENSA_LINKAGE_H */
diff --git a/include/asm-xtensa/local.h b/include/asm-xtensa/local.h
new file mode 100644
index 000000000000..48723e550d14
--- /dev/null
+++ b/include/asm-xtensa/local.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/local.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_LOCAL_H
+#define _XTENSA_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* _XTENSA_LOCAL_H */
diff --git a/include/asm-xtensa/mman.h b/include/asm-xtensa/mman.h
new file mode 100644
index 000000000000..9a95a45df996
--- /dev/null
+++ b/include/asm-xtensa/mman.h
@@ -0,0 +1,80 @@
+/*
+ * include/asm-xtensa/mman.h
+ *
+ * Xtensa Processor memory-manager definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_MMAN_H
+#define _XTENSA_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+
+#define PROT_NONE       0x0             /* page can not be accessed */
+#define PROT_READ       0x1             /* page can be read */
+#define PROT_WRITE      0x2             /* page can be written */
+#define PROT_EXEC       0x4             /* page can be executed */
+
+#define PROT_SEM        0x10            /* page may be used for atomic ops */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end fo growsup vma */
+
+/*
+ * Flags for mmap
+ */
+#define MAP_SHARED      0x001           /* Share changes */
+#define MAP_PRIVATE     0x002           /* Changes are private */
+#define MAP_TYPE        0x00f           /* Mask for type of mapping */
+#define MAP_FIXED       0x010           /* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME      0x020           /* Assign page to file */
+#define MAP_AUTOGROW    0x040           /* File may grow by writing */
+#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
+#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE   0x0400          /* don't check for reservations */
+#define MAP_ANONYMOUS   0x0800          /* don't use a file */
+#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
+#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
+#define MAP_LOCKED      0x8000          /* pages are locked */
+#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x20000         /* do not block on IO */
+
+/*
+ * Flags for msync
+ */
+#define MS_ASYNC        0x0001          /* sync memory asynchronously */
+#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
+#define MS_SYNC         0x0004          /* synchronous memory sync */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#define MADV_NORMAL     0x0             /* default page-in behavior */
+#define MADV_RANDOM     0x1             /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2             /* read-ahead aggressively */
+#define MADV_WILLNEED   0x3             /* pre-fault pages */
+#define MADV_DONTNEED   0x4             /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON       MAP_ANONYMOUS
+#define MAP_FILE       0
+
+#endif /* _XTENSA_MMAN_H */
diff --git a/include/asm-xtensa/mmu.h b/include/asm-xtensa/mmu.h
new file mode 100644
index 000000000000..44c5bb04c55c
--- /dev/null
+++ b/include/asm-xtensa/mmu.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-xtensa/mmu.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_MMU_H
+#define _XTENSA_MMU_H
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+
+#endif  /* _XTENSA_MMU_H */
diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h
new file mode 100644
index 000000000000..364a7b057bfa
--- /dev/null
+++ b/include/asm-xtensa/mmu_context.h
@@ -0,0 +1,330 @@
+/*
+ * include/asm-xtensa/mmu_context.h
+ *
+ * Switch an MMU context.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_MMU_CONTEXT_H
+#define _XTENSA_MMU_CONTEXT_H
+
+#include <linux/config.h>
+#include <linux/stringify.h>
+
+#include <asm/pgtable.h>
+#include <asm/mmu_context.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Linux was ported to Xtensa assuming all auto-refill ways in set 0
+ * had the same properties (a very likely assumption).  Multiple sets
+ * of auto-refill ways will still work properly, but not as optimally
+ * as the Xtensa designer may have assumed.
+ *
+ * We make this case a hard #error, killing the kernel build, to alert
+ * the developer to this condition (which is more likely an error).
+ * You super-duper clever developers can change it to a warning or
+ * remove it altogether if you think you know what you're doing.  :)
+ */
+
+#if (XCHAL_HAVE_TLBS != 1)
+# error "Linux must have an MMU!"
+#endif
+
+#if ((XCHAL_ITLB_ARF_WAYS == 0) || (XCHAL_DTLB_ARF_WAYS == 0))
+# error "MMU must have auto-refill ways"
+#endif
+
+#if ((XCHAL_ITLB_ARF_SETS != 1) || (XCHAL_DTLB_ARF_SETS != 1))
+# error Linux may not use all auto-refill ways as efficiently as you think
+#endif
+
+#if (XCHAL_MMU_MAX_PTE_PAGE_SIZE != XCHAL_MMU_MIN_PTE_PAGE_SIZE)
+# error Only one page size allowed!
+#endif
+
+extern unsigned long asid_cache;
+extern pgd_t *current_pgd;
+
+/*
+ * Define the number of entries per auto-refill way in set 0 of both I and D
+ * TLBs.  We deal only with set 0 here (an assumption further explained in
+ * assertions.h).  Also, define the total number of ARF entries in both TLBs.
+ */
+
+#define ITLB_ENTRIES_PER_ARF_WAY  (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES))
+#define DTLB_ENTRIES_PER_ARF_WAY  (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES))
+
+#define ITLB_ENTRIES                                                    \
+        (ITLB_ENTRIES_PER_ARF_WAY * (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,WAYS)))
+#define DTLB_ENTRIES                                                    \
+        (DTLB_ENTRIES_PER_ARF_WAY * (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,WAYS)))
+
+
+/*
+ * SMALLEST_NTLB_ENTRIES is the smaller of ITLB_ENTRIES and DTLB_ENTRIES.
+ * In practice, they are probably equal.  This macro simplifies function
+ * flush_tlb_range().
+ */
+
+#if (DTLB_ENTRIES < ITLB_ENTRIES)
+# define SMALLEST_NTLB_ENTRIES  DTLB_ENTRIES
+#else
+# define SMALLEST_NTLB_ENTRIES  ITLB_ENTRIES
+#endif
+
+
+/*
+ * asid_cache tracks only the ASID[USER_RING] field of the RASID special
+ * register, which is the current user-task asid allocation value.
+ * mm->context has the same meaning.  When it comes time to write the
+ * asid_cache or mm->context values to the RASID special register, we first
+ * shift the value left by 8, then insert the value.
+ * ASID[0] always contains the kernel's asid value, and we reserve three
+ * other asid values that we never assign to user tasks.
+ */
+
+#define ASID_INC        0x1
+#define ASID_MASK       ((1 << XCHAL_MMU_ASID_BITS) - 1)
+
+/*
+ * XCHAL_MMU_ASID_INVALID is a configurable Xtensa processor constant
+ * indicating invalid address space.  XCHAL_MMU_ASID_KERNEL is a configurable
+ * Xtensa processor constant indicating the kernel address space.  They can
+ * be arbitrary values.
+ *
+ * We identify three more unique, reserved ASID values to use in the unused
+ * ring positions.  No other user process will be assigned these reserved
+ * ASID values.
+ *
+ * For example, given that
+ *
+ *      XCHAL_MMU_ASID_INVALID == 0
+ *      XCHAL_MMU_ASID_KERNEL  == 1
+ *
+ * the following maze of #if statements would generate
+ *
+ *      ASID_RESERVED_1        == 2
+ *      ASID_RESERVED_2        == 3
+ *      ASID_RESERVED_3        == 4
+ *      ASID_FIRST_NONRESERVED == 5
+ */
+
+#if (XCHAL_MMU_ASID_INVALID != XCHAL_MMU_ASID_KERNEL + 1)
+# define ASID_RESERVED_1         ((XCHAL_MMU_ASID_KERNEL + 1) & ASID_MASK)
+#else
+# define ASID_RESERVED_1         ((XCHAL_MMU_ASID_KERNEL + 2) & ASID_MASK)
+#endif
+
+#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_1 + 1)
+# define ASID_RESERVED_2         ((ASID_RESERVED_1 + 1) & ASID_MASK)
+#else
+# define ASID_RESERVED_2         ((ASID_RESERVED_1 + 2) & ASID_MASK)
+#endif
+
+#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_2 + 1)
+# define ASID_RESERVED_3         ((ASID_RESERVED_2 + 1) & ASID_MASK)
+#else
+# define ASID_RESERVED_3         ((ASID_RESERVED_2 + 2) & ASID_MASK)
+#endif
+
+#if (XCHAL_MMU_ASID_INVALID != ASID_RESERVED_3 + 1)
+# define ASID_FIRST_NONRESERVED  ((ASID_RESERVED_3 + 1) & ASID_MASK)
+#else
+# define ASID_FIRST_NONRESERVED  ((ASID_RESERVED_3 + 2) & ASID_MASK)
+#endif
+
+#define ASID_ALL_RESERVED ( ((ASID_RESERVED_1) << 24) + \
+                            ((ASID_RESERVED_2) << 16) + \
+                            ((ASID_RESERVED_3) <<  8) + \
+                            ((XCHAL_MMU_ASID_KERNEL))   )
+
+
+/*
+ * NO_CONTEXT is the invalid ASID value that we don't ever assign to
+ * any user or kernel context.  NO_CONTEXT is a better mnemonic than
+ * XCHAL_MMU_ASID_INVALID, so we use it in code instead.
+ */
+
+#define NO_CONTEXT   XCHAL_MMU_ASID_INVALID
+
+#if (KERNEL_RING != 0)
+# error The KERNEL_RING really should be zero.
+#endif
+
+#if (USER_RING >= XCHAL_MMU_RINGS)
+# error USER_RING cannot be greater than the highest numbered ring.
+#endif
+
+#if (USER_RING == KERNEL_RING)
+# error The user and kernel rings really should not be equal.
+#endif
+
+#if (USER_RING == 1)
+#define ASID_INSERT(x) ( ((ASID_RESERVED_1)   << 24) + \
+                         ((ASID_RESERVED_2)   << 16) + \
+                         (((x) & (ASID_MASK)) <<  8) + \
+                         ((XCHAL_MMU_ASID_KERNEL))   )
+
+#elif (USER_RING == 2)
+#define ASID_INSERT(x) ( ((ASID_RESERVED_1)   << 24) + \
+                         (((x) & (ASID_MASK)) << 16) + \
+                         ((ASID_RESERVED_2)   <<  8) + \
+                         ((XCHAL_MMU_ASID_KERNEL))   )
+
+#elif (USER_RING == 3)
+#define ASID_INSERT(x) ( (((x) & (ASID_MASK)) << 24) + \
+                         ((ASID_RESERVED_1)   << 16) + \
+                         ((ASID_RESERVED_2)   <<  8) + \
+                         ((XCHAL_MMU_ASID_KERNEL))   )
+
+#else
+#error Goofy value for USER_RING
+
+#endif /* USER_RING == 1 */
+
+
+/*
+ *  All unused by hardware upper bits will be considered
+ *  as a software asid extension.
+ */
+
+#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
+#define ASID_FIRST_VERSION                                              \
+        ((unsigned long)(~ASID_VERSION_MASK) + 1 + ASID_FIRST_NONRESERVED)
+
+static inline void set_rasid_register (unsigned long val)
+{
+        __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t"
+                              " isync\n" : : "a" (val));
+}
+
+static inline unsigned long get_rasid_register (void)
+{
+        unsigned long tmp;
+        __asm__ __volatile__ (" rsr %0, "__stringify(RASID)"\n\t" : "=a" (tmp));
+        return tmp;
+}
+
+
+#if ((XCHAL_MMU_ASID_INVALID == 0) && (XCHAL_MMU_ASID_KERNEL == 1))
+
+static inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+{
+        extern void flush_tlb_all(void);
+        if (! ((asid += ASID_INC) & ASID_MASK) ) {
+                flush_tlb_all(); /* start new asid cycle */
+                if (!asid)      /* fix version if needed */
+                        asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
+                asid += ASID_FIRST_NONRESERVED;
+        }
+        mm->context = asid_cache = asid;
+}
+
+#else
+#warning ASID_{INVALID,KERNEL} values impose non-optimal get_new_mmu_context implementation
+
+/* XCHAL_MMU_ASID_INVALID == 0 and XCHAL_MMU_ASID_KERNEL ==1 are
+   really the best, but if you insist... */
+
+static inline int validate_asid (unsigned long asid)
+{
+        switch (asid) {
+        case XCHAL_MMU_ASID_INVALID:
+        case XCHAL_MMU_ASID_KERNEL:
+        case ASID_RESERVED_1:
+        case ASID_RESERVED_2:
+        case ASID_RESERVED_3:
+                return 0; /* can't use these values as ASIDs */
+        }
+        return 1; /* valid */
+}
+
+static inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long asid)
+{
+        extern void flush_tlb_all(void);
+        while (1) {
+                asid += ASID_INC;
+                if ( ! (asid & ASID_MASK) ) {
+                        flush_tlb_all(); /* start new asid cycle */
+                        if (!asid)      /* fix version if needed */
+                                asid = ASID_FIRST_VERSION - ASID_FIRST_NONRESERVED;
+                        asid += ASID_FIRST_NONRESERVED;
+                        break; /* no need to validate here */
+                }
+                if (validate_asid (asid & ASID_MASK))
+                        break;
+        }
+        mm->context = asid_cache = asid;
+}
+
+#endif
+
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        mm->context = NO_CONTEXT;
+        return 0;
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned long asid = asid_cache;
+
+        /* Check if our ASID is of an older version and thus invalid */
+
+        if ((next->context ^ asid) & ASID_VERSION_MASK)
+                get_new_mmu_context(next, asid);
+
+        set_rasid_register (ASID_INSERT(next->context));
+        invalidate_page_directory();
+}
+
+#define deactivate_mm(tsk, mm)  do { } while(0)
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        /* Nothing to do. */
+}
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void
+activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        /* Unconditionally get a new ASID.  */
+
+        get_new_mmu_context(next, asid_cache);
+        set_rasid_register (ASID_INSERT(next->context));
+        invalidate_page_directory();
+}
+
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+        /* Nothing to do. */
+
+}
+
+#endif /* _XTENSA_MMU_CONTEXT_H */
diff --git a/include/asm-xtensa/module.h b/include/asm-xtensa/module.h
new file mode 100644
index 000000000000..ffb25bfdf6a1
--- /dev/null
+++ b/include/asm-xtensa/module.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-xtensa/module.h
+ *
+ * This file contains the module code specific to the Xtensa architecture.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_MODULE_H
+#define _XTENSA_MODULE_H
+
+struct mod_arch_specific
+{
+        /* Module support is not completely implemented. */
+};
+
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+
+#endif  /* _XTENSA_MODULE_H */
diff --git a/include/asm-xtensa/msgbuf.h b/include/asm-xtensa/msgbuf.h
new file mode 100644
index 000000000000..693c96755280
--- /dev/null
+++ b/include/asm-xtensa/msgbuf.h
@@ -0,0 +1,48 @@
+/*
+ * include/asm-xtensa/msgbuf.h
+ *
+ * The msqid64_ds structure for the Xtensa architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ */
+
+#ifndef _XTENSA_MSGBUF_H
+#define _XTENSA_MSGBUF_H
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+#ifdef __XTENSA_EB__
+        unsigned int    __unused1;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned int    __unused2;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned int    __unused3;
+        __kernel_time_t msg_ctime;      /* last change time */
+#elif defined(__XTENSA_EL__)
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned int    __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned int    __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned int    __unused3;
+#else
+# error processor byte order undefined!
+#endif
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif  /* _XTENSA_MSGBUF_H */
diff --git a/include/asm-xtensa/namei.h b/include/asm-xtensa/namei.h
new file mode 100644
index 000000000000..3fdff039d27d
--- /dev/null
+++ b/include/asm-xtensa/namei.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-xtensa/namei.h
+ *
+ * Included from linux/fs/namei.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_NAMEI_H
+#define _XTENSA_NAMEI_H
+
+#ifdef __KERNEL__
+
+/* This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ * Look at asm-sparc/namei.h for details.
+ */
+
+#define __emul_prefix() NULL
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_NAMEI_H */
diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h
new file mode 100644
index 000000000000..8ded36f255a2
--- /dev/null
+++ b/include/asm-xtensa/page.h
@@ -0,0 +1,133 @@
+/*
+ * linux/include/asm-xtensa/page.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PAGE_H
+#define _XTENSA_PAGE_H
+
+#ifdef __KERNEL__
+
+#include <asm/processor.h>
+#include <linux/config.h>
+
+/*
+ * PAGE_SHIFT determines the page size
+ * PAGE_ALIGN(x) aligns the pointer to the (next) page boundary
+ */
+
+#define PAGE_SHIFT              XCHAL_MMU_MIN_PTE_PAGE_SIZE
+#define PAGE_SIZE               (1 << PAGE_SHIFT)
+#define PAGE_MASK               (~(PAGE_SIZE-1))
+#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE - 1) & PAGE_MASK)
+
+#define DCACHE_WAY_SIZE         (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
+#define PAGE_OFFSET             XCHAL_KSEG_CACHED_VADDR
+
+#ifdef __ASSEMBLY__
+
+#define __pgprot(x)     (x)
+
+#else
+
+/*
+ * These are used to make use of C type-checking..
+ */
+
+typedef struct { unsigned long pte; } pte_t;            /* page table entry */
+typedef struct { unsigned long pgd; } pgd_t;            /* PGD table entry */
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+/*
+ * Pure 2^n version of get_order
+ */
+
+static inline int get_order(unsigned long size)
+{
+        int order;
+#ifndef XCHAL_HAVE_NSU
+        unsigned long x1, x2, x4, x8, x16;
+
+        size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        x1  = size & 0xAAAAAAAA;
+        x2  = size & 0xCCCCCCCC;
+        x4  = size & 0xF0F0F0F0;
+        x8  = size & 0xFF00FF00;
+        x16 = size & 0xFFFF0000;
+        order = x2 ? 2 : 0;
+        order += (x16 != 0) * 16;
+        order += (x8 != 0) * 8;
+        order += (x4 != 0) * 4;
+        order += (x1 != 0);
+
+        return order;
+#else
+        size = (size - 1) >> PAGE_SHIFT;
+        asm ("nsau %0, %1" : "=r" (order) : "r" (size));
+        return 32 - order;
+#endif
+}
+
+
+struct page;
+extern void clear_page(void *page);
+extern void copy_page(void *to, void *from);
+
+/*
+ * If we have cache aliasing and writeback caches, we might have to do
+ * some extra work
+ */
+
+#if (DCACHE_WAY_SIZE > PAGE_SIZE)
+void clear_user_page(void *addr, unsigned long vaddr, struct page* page);
+void copy_user_page(void *to,void* from,unsigned long vaddr,struct page* page);
+#else
+# define clear_user_page(page,vaddr,pg)         clear_page(page)
+# define copy_user_page(to, from, vaddr, pg)    copy_page(to, from)
+#endif
+
+/*
+ * This handles the memory map.  We handle pages at
+ * XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
+ * These macros are for conversion of kernel address, not user
+ * addresses.
+ */
+
+#define __pa(x)                 ((unsigned long) (x) - PAGE_OFFSET)
+#define __va(x)                 ((void *)((unsigned long) (x) + PAGE_OFFSET))
+#define pfn_valid(pfn)          ((unsigned long)pfn < max_mapnr)
+#ifndef CONFIG_DISCONTIGMEM
+# define pfn_to_page(pfn)       (mem_map + (pfn))
+# define page_to_pfn(page)      ((unsigned long)((page) - mem_map))
+#else
+# error CONFIG_DISCONTIGMEM not supported
+#endif
+
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_virt(page)      __va(page_to_pfn(page) << PAGE_SHIFT)
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+#define WANT_PAGE_VIRTUAL
+
+
+#endif /* __ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+#endif /* _XTENSA_PAGE_H */
diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h
new file mode 100644
index 000000000000..c0eec8260b0e
--- /dev/null
+++ b/include/asm-xtensa/param.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-xtensa/param.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PARAM_H
+#define _XTENSA_PARAM_H
+
+#include <xtensa/config/core.h>
+
+#ifdef __KERNEL__
+# define HZ             100             /* internal timer frequency */
+# define USER_HZ        100             /* for user interfaces in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* frequnzy at which times() counts */
+#endif
+
+#define EXEC_PAGESIZE   (1 << XCHAL_MMU_MIN_PTE_PAGE_SIZE)
+
+#ifndef NGROUPS
+#define NGROUPS         32
+#endif
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif /* _XTENSA_PARAM_H */
diff --git a/include/asm-xtensa/pci-bridge.h b/include/asm-xtensa/pci-bridge.h
new file mode 100644
index 000000000000..00fcbd7c534a
--- /dev/null
+++ b/include/asm-xtensa/pci-bridge.h
@@ -0,0 +1,88 @@
+/*
+ * include/asm-xtensa/pci-bridge.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PCI_BRIDGE_H
+#define _XTENSA_PCI_BRIDGE_H
+
+#ifdef __KERNEL__
+
+struct device_node;
+struct pci_controller;
+
+/*
+ * pciauto_bus_scan() enumerates the pci space.
+ */
+
+extern int pciauto_bus_scan(struct pci_controller *, int);
+
+struct pci_space {
+        unsigned long start;
+        unsigned long end;
+        unsigned long base;
+};
+
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+
+struct pci_controller {
+        int index;                      /* used for pci_controller_num */
+        struct pci_controller *next;
+        struct pci_bus *bus;
+        void *arch_data;
+
+        int first_busno;
+        int last_busno;
+
+        struct pci_ops *ops;
+        volatile unsigned int *cfg_addr;
+        volatile unsigned char *cfg_data;
+
+        /* Currently, we limit ourselves to 1 IO range and 3 mem
+         * ranges since the common pci_bus structure can't handle more
+         */
+        struct resource io_resource;
+        struct resource mem_resources[3];
+        int mem_resource_count;
+
+        /* Host bridge I/O and Memory space
+         * Used for BAR placement algorithms
+         */
+        struct pci_space io_space;
+        struct pci_space mem_space;
+
+        /* Return the interrupt number fo a device. */
+        int (*map_irq)(struct pci_dev*, u8, u8);
+
+};
+
+static inline void pcibios_init_resource(struct resource *res,
+                unsigned long start, unsigned long end, int flags, char *name)
+{
+        res->start = start;
+        res->end = end;
+        res->flags = flags;
+        res->name = name;
+        res->parent = NULL;
+        res->sibling = NULL;
+        res->child = NULL;
+}
+
+
+/* These are used for config access before all the PCI probing has been done. */
+int early_read_config_byte(struct pci_controller*, int, int, int, u8*);
+int early_read_config_word(struct pci_controller*, int, int, int, u16*);
+int early_read_config_dword(struct pci_controller*, int, int, int, u32*);
+int early_write_config_byte(struct pci_controller*, int, int, int, u8);
+int early_write_config_word(struct pci_controller*, int, int, int, u16);
+int early_write_config_dword(struct pci_controller*, int, int, int, u32);
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_PCI_BRIDGE_H */
diff --git a/include/asm-xtensa/pci.h b/include/asm-xtensa/pci.h
new file mode 100644
index 000000000000..24eb7fc25da8
--- /dev/null
+++ b/include/asm-xtensa/pci.h
@@ -0,0 +1,89 @@
+/*
+ * linux/include/asm-xtensa/pci.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PCI_H
+#define _XTENSA_PCI_H
+
+#ifdef __KERNEL__
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes
+ * or architectures with incomplete PCI setup by the loader
+ */
+
+#define pcibios_assign_all_busses()     0
+
+extern struct pci_controller* pcibios_alloc_controller(void);
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* Assume some values. (We should revise them, if necessary) */
+
+#define PCIBIOS_MIN_IO          0x2000
+#define PCIBIOS_MIN_MEM         0x10000000
+
+/* Dynamic DMA mapping stuff.
+ * Xtensa has everything mapped statically like x86.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+struct pci_dev;
+
+/* The PCI address space does equal the physical memory address space.
+ * The networking and block device layers use this boolean for bounce buffer
+ * decisions.
+ */
+
+#define PCI_DMA_BUS_IS_PHYS     (1)
+
+/* pci_unmap_{page,single} is a no-op, so */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_ubnmap_len(PTR, LEN_NAME)           (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+/* We cannot access memory above 4GB */
+#define pci_dac_dma_supported(pci_dev, mask)    (0)
+
+/* Map a range of PCI memory or I/O space for a device into user space */
+int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
+                        enum pci_mmap_state mmap_state, int write_combine);
+
+/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
+#define HAVE_PCI_MMAP   1
+
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+
+#endif /* __KERNEL__ */
+
+/* Implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+/* Generic PCI */
+#include <asm-generic/pci.h>
+
+#endif  /* _XTENSA_PCI_H */
diff --git a/include/asm-xtensa/percpu.h b/include/asm-xtensa/percpu.h
new file mode 100644
index 000000000000..6d2bc2ada9d1
--- /dev/null
+++ b/include/asm-xtensa/percpu.h
@@ -0,0 +1,16 @@
+/*
+ * linux/include/asm-xtensa/percpu.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PERCPU__
+#define _XTENSA_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif /* _XTENSA_PERCPU__ */
diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h
new file mode 100644
index 000000000000..734a8d060395
--- /dev/null
+++ b/include/asm-xtensa/pgalloc.h
@@ -0,0 +1,116 @@
+/*
+ * linux/include/asm-xtensa/pgalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2001-2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PGALLOC_H
+#define _XTENSA_PGALLOC_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <linux/threads.h>
+#include <linux/highmem.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+
+
+/* Cache aliasing:
+ *
+ * If the cache size for one way is greater than the page size, we have to
+ * deal with cache aliasing. The cache index is wider than the page size:
+ *
+ *      |cache |
+ * |pgnum |page|        virtual address
+ * |xxxxxX|zzzz|
+ * |      |    |
+ *   \  / |    |
+ *  trans.|    |
+ *   /  \ |    |
+ * |yyyyyY|zzzz|        physical address
+ *
+ * When the page number is translated to the physical page address, the lowest
+ * bit(s) (X) that are also part of the cache index are also translated (Y).
+ * If this translation changes this bit (X), the cache index is also afected,
+ * thus resulting in a different cache line than before.
+ * The kernel does not provide a mechanism to ensure that the page color
+ * (represented by this bit) remains the same when allocated or when pages
+ * are remapped. When user pages are mapped into kernel space, the color of
+ * the page might also change.
+ *
+ * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
+ * to temporarily map a patch so we can match the color.
+ */
+
+#if (DCACHE_WAY_SIZE > PAGE_SIZE)
+# define PAGE_COLOR_MASK        (PAGE_MASK & (DCACHE_WAY_SIZE-1))
+# define PAGE_COLOR(a)          \
+        (((unsigned long)(a)&PAGE_COLOR_MASK) >> PAGE_SHIFT)
+# define PAGE_COLOR_EQ(a,b)     \
+        ((((unsigned long)(a) ^ (unsigned long)(b)) & PAGE_COLOR_MASK) == 0)
+# define PAGE_COLOR_MAP0(v)     \
+        (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK))
+# define PAGE_COLOR_MAP1(v)     \
+        (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK) + DCACHE_WAY_SIZE)
+#endif
+
+/*
+ * Allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+
+#define pgd_free(pgd)   free_page((unsigned long)(pgd))
+
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
+
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *pte)
+{
+        pmd_val(*(pmdp)) = (unsigned long)(pte);
+        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *page)
+{
+        pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page);
+        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
+}
+
+
+
+#else
+
+# define pmd_populate_kernel(mm, pmdp, pte)                                  \
+        (pmd_val(*(pmdp)) = (unsigned long)(pte))
+# define pmd_populate(mm, pmdp, page)                                        \
+        (pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page))
+
+#endif
+
+static inline pgd_t*
+pgd_alloc(struct mm_struct *mm)
+{
+        pgd_t *pgd;
+
+        pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGD_ORDER);
+
+        if (likely(pgd != NULL))
+                __flush_dcache_page((unsigned long)pgd);
+
+        return pgd;
+}
+
+extern pte_t* pte_alloc_one_kernel(struct mm_struct* mm, unsigned long addr);
+extern struct page* pte_alloc_one(struct mm_struct* mm, unsigned long addr);
+
+#define pte_free_kernel(pte) free_page((unsigned long)pte)
+#define pte_free(pte) __free_page(pte)
+
+#endif /* __KERNEL__ */
+#endif /* _XTENSA_PGALLOC_H */
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
new file mode 100644
index 000000000000..883ebc2d75d6
--- /dev/null
+++ b/include/asm-xtensa/pgtable.h
@@ -0,0 +1,468 @@
+/*
+ * linux/include/asm-xtensa/page.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PGTABLE_H
+#define _XTENSA_PGTABLE_H
+
+#include <asm-generic/pgtable-nopmd.h>
+#include <asm/page.h>
+
+/* Assertions. */
+
+#ifdef CONFIG_MMU
+
+
+#if (XCHAL_MMU_RINGS < 2)
+# error Linux build assumes at least 2 ring levels.
+#endif
+
+#if (XCHAL_MMU_CA_BITS != 4)
+# error We assume exactly four bits for CA.
+#endif
+
+#if (XCHAL_MMU_SR_BITS != 0)
+# error We have no room for SR bits.
+#endif
+
+/*
+ * Use the first min-wired way for mapping page-table pages.
+ * Page coloring requires a second min-wired way.
+ */
+
+#if (XCHAL_DTLB_MINWIRED_SETS == 0)
+# error Need a min-wired way for mapping page-table pages
+#endif
+
+#define DTLB_WAY_PGTABLE XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAY)
+
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
+# if XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAYS) >= 2
+#  define DTLB_WAY_DCACHE_ALIAS0 (DTLB_WAY_PGTABLE + 1)
+#  define DTLB_WAY_DCACHE_ALIAS1 (DTLB_WAY_PGTABLE + 2)
+# else
+#  error Page coloring requires its own wired dtlb way!
+# endif
+#endif
+
+#endif /* CONFIG_MMU */
+
+/*
+ * We only use two ring levels, user and kernel space.
+ */
+
+#define USER_RING               1       /* user ring level */
+#define KERNEL_RING             0       /* kernel ring level */
+
+/*
+ * The Xtensa architecture port of Linux has a two-level page table system,
+ * i.e. the logical three-level Linux page table layout are folded.
+ * Each task has the following memory page tables:
+ *
+ *   PGD table (page directory), ie. 3rd-level page table:
+ *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
+ *      (Architectures that don't have the PMD folded point to the PMD tables)
+ *
+ *      The pointer to the PGD table for a given task can be retrieved from
+ *      the task structure (struct task_struct*) t, e.g. current():
+ *        (t->mm ? t->mm : t->active_mm)->pgd
+ *
+ *   PMD tables (page middle-directory), ie. 2nd-level page tables:
+ *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
+ *
+ *   PTE tables (page table entry), ie. 1st-level page tables:
+ *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
+ *      invalid_pte_table for absent mappings.
+ *
+ * The individual pages are 4 kB big with special pages for the empty_zero_page.
+ */
+#define PGDIR_SHIFT     22
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * Entries per page directory level: we use two-level, so
+ * we don't really have any PMD directory physically.
+ */
+#define PTRS_PER_PTE            1024
+#define PTRS_PER_PTE_SHIFT      10
+#define PTRS_PER_PMD            1
+#define PTRS_PER_PGD            1024
+#define PGD_ORDER               0
+#define PMD_ORDER               0
+#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      XCHAL_SEG_MAPPABLE_VADDR
+#define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
+
+/* virtual memory area. We keep a distance to other memory regions to be
+ * on the safe side. We also use this area for cache aliasing.
+ */
+
+// FIXME: virtual memory area must be configuration-dependent
+
+#define VMALLOC_START           0xC0000000
+#define VMALLOC_END             0xC7FF0000
+
+/* Xtensa Linux config PTE layout (when present):
+ *      31-12:  PPN
+ *      11-6:   Software
+ *      5-4:    RING
+ *      3-0:    CA
+ *
+ * Similar to the Alpha and MIPS ports, we need to keep track of the ref
+ * and mod bits in software.  We have a software "you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.  On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page.
+ *
+ * See further below for PTE layout for swapped-out pages.
+ */
+
+#define _PAGE_VALID             (1<<0)  /* hardware: page is accessible */
+#define _PAGE_WRENABLE          (1<<1)  /* hardware: page is writable */
+
+/* None of these cache modes include MP coherency:  */
+#define _PAGE_NO_CACHE          (0<<2)  /* bypass, non-speculative */
+#if XCHAL_DCACHE_IS_WRITEBACK
+# define _PAGE_WRITEBACK        (1<<2)  /* write back */
+# define _PAGE_WRITETHRU        (2<<2)  /* write through */
+#else
+# define _PAGE_WRITEBACK        (1<<2)  /* assume write through */
+# define _PAGE_WRITETHRU        (1<<2)
+#endif
+#define _PAGE_NOALLOC           (3<<2)  /* don't allocate cache,if not cached */
+#define _CACHE_MASK             (3<<2)
+
+#define _PAGE_USER              (1<<4)  /* user access (ring=1) */
+#define _PAGE_KERNEL            (0<<4)  /* kernel access (ring=0) */
+
+/* Software */
+#define _PAGE_RW                (1<<6)  /* software: page writable */
+#define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
+#define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
+#define _PAGE_FILE              (1<<9)  /* nonlinear file mapping*/
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _CACHE_MASK | _PAGE_DIRTY)
+#define _PAGE_PRESENT   ( _PAGE_VALID | _PAGE_WRITEBACK | _PAGE_ACCESSED)
+
+#ifdef CONFIG_MMU
+
+# define PAGE_NONE      __pgprot(_PAGE_PRESENT)
+# define PAGE_SHARED    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_RW)
+# define PAGE_COPY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
+# define PAGE_READONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER)
+# define PAGE_KERNEL    __pgprot(_PAGE_PRESENT | _PAGE_KERNEL | _PAGE_WRENABLE)
+# define PAGE_INVALID   __pgprot(_PAGE_USER)
+
+# if (DCACHE_WAY_SIZE > PAGE_SIZE)
+#  define PAGE_DIRECTORY  __pgprot(_PAGE_VALID | _PAGE_ACCESSED | _PAGE_KERNEL)
+# else
+#  define PAGE_DIRECTORY  __pgprot(_PAGE_PRESENT | _PAGE_KERNEL)
+# endif
+
+#else /* no mmu */
+
+# define PAGE_NONE       __pgprot(0)
+# define PAGE_SHARED     __pgprot(0)
+# define PAGE_COPY       __pgprot(0)
+# define PAGE_READONLY   __pgprot(0)
+# define PAGE_KERNEL     __pgprot(0)
+
+#endif
+
+/*
+ * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
+ * the MMU can't do page protection for execute, and considers that the same as
+ * read.  Also, write permissions may imply read permissions.
+ * What follows is the closest we can get by reasonable means..
+ * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
+ */
+#define __P000  PAGE_NONE       /* private --- */
+#define __P001  PAGE_READONLY   /* private --r */
+#define __P010  PAGE_COPY       /* private -w- */
+#define __P011  PAGE_COPY       /* private -wr */
+#define __P100  PAGE_READONLY   /* private x-- */
+#define __P101  PAGE_READONLY   /* private x-r */
+#define __P110  PAGE_COPY       /* private xw- */
+#define __P111  PAGE_COPY       /* private xwr */
+
+#define __S000  PAGE_NONE       /* shared  --- */
+#define __S001  PAGE_READONLY   /* shared  --r */
+#define __S010  PAGE_SHARED     /* shared  -w- */
+#define __S011  PAGE_SHARED     /* shared  -wr */
+#define __S100  PAGE_READONLY   /* shared  x-- */
+#define __S101  PAGE_READONLY   /* shared  x-r */
+#define __S110  PAGE_SHARED     /* shared  xw- */
+#define __S111  PAGE_SHARED     /* shared  xwr */
+
+#ifndef __ASSEMBLY__
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern unsigned long empty_zero_page[1024];
+
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
+
+/*
+ * The pmd contains the kernel virtual address of the pte page.
+ */
+#define pmd_page_kernel(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
+
+/*
+ * The following only work if pte_present() is true.
+ */
+#define pte_none(pte)    (!(pte_val(pte) ^ _PAGE_USER))
+#define pte_present(pte) (pte_val(pte) & _PAGE_VALID)
+#define pte_clear(mm,addr,ptep)                                         \
+        do { update_pte(ptep, __pte(_PAGE_USER)); } while(0)
+
+#define pmd_none(pmd)    (!pmd_val(pmd))
+#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
+#define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
+#define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
+
+/* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */
+
+static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)  { return pte_val(pte) & _PAGE_FILE; }
+static inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) &= ~(_PAGE_RW | _PAGE_WRENABLE); return pte; }
+static inline pte_t pte_rdprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkread(pte_t pte)       { pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) |= _PAGE_RW; return pte; }
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
+#define pte_same(a,b)           (pte_val(a) == pte_val(b))
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+}
+
+/*
+ * Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void update_pte(pte_t *ptep, pte_t pteval)
+{
+        *ptep = pteval;
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
+        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (ptep));
+#endif
+}
+
+static inline void
+set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
+{
+        update_pte(ptep, pteval);
+}
+
+
+static inline void
+set_pmd(pmd_t *pmdp, pmd_t pmdval)
+{
+        *pmdp = pmdval;
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
+        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
+#endif
+}
+
+
+static inline int
+ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
+                          pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        if (!pte_young(pte))
+                return 0;
+        update_pte(ptep, pte_mkold(pte));
+        return 1;
+}
+
+static inline int
+ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr,
+                          pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        if (!pte_dirty(pte))
+                return 0;
+        update_pte(ptep, pte_mkclean(pte));
+        return 1;
+}
+
+static inline pte_t
+ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        pte_clear(mm, addr, ptep);
+        return pte;
+}
+
+static inline void
+ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        update_pte(ptep, pte_wrprotect(pte));
+}
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
+
+#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(dir,address) ((pmd_t*)(dir))
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir,addr)                                     \
+        ((pte_t*) pmd_page_kernel(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
+
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+
+/*
+ * Encode and decode a swap entry.
+ * Each PTE in a process VM's page table is either:
+ *   "present" -- valid and not swapped out, protection bits are meaningful;
+ *   "not present" -- which further subdivides in these two cases:
+ *      "none" -- no mapping at all; identified by pte_none(), set by pte_clear(
+ *      "swapped out" -- the page is swapped out, and the SWP macros below
+ *                      are used to store swap file info in the PTE itself.
+ *
+ * In the Xtensa processor MMU, any PTE entries in user space (or anywhere
+ * in virtual memory that can map differently across address spaces)
+ * must have a correct ring value that represents the RASID field that
+ * is changed when switching address spaces.  Eg. such PTE entries cannot
+ * be set to ring zero, because that can cause a (global) kernel ASID
+ * entry to be created in the TLBs (even with invalid cache attribute),
+ * potentially causing a multihit exception when going back to another
+ * address space that mapped the same virtual address at another ring.
+ *
+ * SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs.
+ * We also avoid using the _PAGE_VALID bit which must be zero for non-present
+ * pages.
+ *
+ * We end up with the following available bits:  1..3 and 7..31.
+ * We don't bother with 1..3 for now (we can use them later if needed),
+ * and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits
+ * for SWP_OFFSET.  At least 5 bits are needed for SWP_TYPE, because it
+ * is currently implemented as an index into swap_info[MAX_SWAPFILES]
+ * and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>.
+ * However, for some reason all other architectures in the 2.4 kernel
+ * reserve either 6, 7, or 8 bits so I'll not detract from that for now.  :)
+ * SWP_OFFSET is an offset into the swap file in page-size units, so
+ * with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB.
+ *
+ * FIXME:  2 GB isn't very big.  Other bits can be used to allow
+ * larger swap sizes.  In the meantime, it appears relatively easy to get
+ * around the 2 GB limitation by simply using multiple swap files.
+ */
+
+#define __swp_type(entry)       (((entry).val >> 7) & 0x3f)
+#define __swp_offset(entry)     ((entry).val >> 13)
+#define __swp_entry(type,offs)  ((swp_entry_t) {((type) << 7) | ((offs) << 13)})
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
+
+
+#endif /*  !defined (__ASSEMBLY__) */
+
+
+#ifdef __ASSEMBLY__
+
+/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
+ *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
+ *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
+ *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
+ *
+ * Note: We require an additional temporary register which can be the same as
+ *       the register that holds the address.
+ *
+ * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
+ *
+ */
+#define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
+#define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
+
+#define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
+                                        _PGD_INDEX(tmp, adr);           \
+                                        addx4   mm, tmp, mm
+
+#define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
+                                        srli    pmd, pmd, PAGE_SHIFT;   \
+                                        slli    pmd, pmd, PAGE_SHIFT;   \
+                                        addx4   pmd, tmp, pmd
+
+#else
+
+extern void paging_init(void);
+
+#define kern_addr_valid(addr)   (1)
+
+extern  void update_mmu_cache(struct vm_area_struct * vma,
+                              unsigned long address, pte_t pte);
+
+/*
+ * remap a physical address `phys' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+#define io_remap_page_range(vma,from,phys,size,prot) \
+                remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot)
+
+
+/* No page table caches to init */
+
+#define pgtable_cache_init()    do { } while (0)
+
+typedef pte_t *pte_addr_t;
+
+#endif /* !defined (__ASSEMBLY__) */
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+#define __HAVE_ARCH_PTEP_MKDIRTY
+#define __HAVE_ARCH_PTE_SAME
+
+#include <asm-generic/pgtable.h>
+
+#endif /* _XTENSA_PGTABLE_H */
diff --git a/include/asm-xtensa/platform-iss/hardware.h b/include/asm-xtensa/platform-iss/hardware.h
new file mode 100644
index 000000000000..22240f001803
--- /dev/null
+++ b/include/asm-xtensa/platform-iss/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-xtensa/platform-iss/hardware.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Tensilica Inc.
+ */
+
+/*
+ * This file contains the default configuration of ISS.
+ */
+
+#ifndef __ASM_XTENSA_ISS_HARDWARE
+#define __ASM_XTENSA_ISS_HARDWARE
+
+/*
+ * Memory configuration.
+ */
+
+#define PLATFORM_DEFAULT_MEM_START XSHAL_RAM_PADDR
+#define PLATFORM_DEFAULT_MEM_SIZE XSHAL_RAM_VSIZE
+
+/*
+ * Interrupt configuration.
+ */
+
+#endif /* __ASM_XTENSA_ISS_HARDWARE */
diff --git a/include/asm-xtensa/platform.h b/include/asm-xtensa/platform.h
new file mode 100644
index 000000000000..36163894bc20
--- /dev/null
+++ b/include/asm-xtensa/platform.h
@@ -0,0 +1,92 @@
+/*
+ * include/asm-xtensa/platform.h
+ *
+ * Platform specific functions
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PLATFORM_H
+#define _XTENSA_PLATFORM_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+#include <asm/bootparam.h>
+
+/*
+ * platform_init is called before the mmu is initialized to give the
+ * platform a early hook-up. bp_tag_t is a list of configuration tags
+ * passed from the boot-loader.
+ */
+extern void platform_init(bp_tag_t*);
+
+/*
+ * platform_setup is called from setup_arch with a pointer to the command-line
+ * string.
+ */
+extern void platform_setup (char **);
+
+/*
+ * platform_init_irq is called from init_IRQ.
+ */
+extern void platform_init_irq (void);
+
+/*
+ * platform_restart is called to restart the system.
+ */
+extern void platform_restart (void);
+
+/*
+ * platform_halt is called to stop the system and halt.
+ */
+extern void platform_halt (void);
+
+/*
+ * platform_power_off is called to stop the system and power it off.
+ */
+extern void platform_power_off (void);
+
+/*
+ * platform_idle is called from the idle function.
+ */
+extern void platform_idle (void);
+
+/*
+ * platform_heartbeat is called every HZ
+ */
+extern void platform_heartbeat (void);
+
+/*
+ * platform_pcibios_init is called to allow the platform to setup the pci bus.
+ */
+extern void platform_pcibios_init (void);
+
+/*
+ * platform_pcibios_fixup allows to modify the PCI configuration.
+ */
+extern int platform_pcibios_fixup (void);
+
+/*
+ * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE)
+ */
+extern void platform_calibrate_ccount (void);
+
+/*
+ * platform_get_rtc_time returns RTC seconds (returns 0 for no error)
+ */
+extern int platform_get_rtc_time(time_t*);
+
+/*
+ * platform_set_rtc_time set RTC seconds (returns 0 for no error)
+ */
+extern int platform_set_rtc_time(time_t);
+
+
+#endif  /* _XTENSA_PLATFORM_H */
+
diff --git a/include/asm-xtensa/poll.h b/include/asm-xtensa/poll.h
new file mode 100644
index 000000000000..dffe447534e0
--- /dev/null
+++ b/include/asm-xtensa/poll.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-xtensa/poll.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_POLL_H
+#define _XTENSA_POLL_H
+
+
+#define POLLIN          0x0001
+#define POLLPRI         0x0002
+#define POLLOUT         0x0004
+
+#define POLLERR         0x0008
+#define POLLHUP         0x0010
+#define POLLNVAL        0x0020
+
+#define POLLRDNORM      0x0040
+#define POLLRDBAND      0x0080
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      0x0100
+
+#define POLLMSG         0x0400
+#define POLLREMOVE      0x0800
+
+struct pollfd {
+        int fd;
+        short events;
+        short revents;
+};
+
+#endif /* _XTENSA_POLL_H */
diff --git a/include/asm-xtensa/posix_types.h b/include/asm-xtensa/posix_types.h
new file mode 100644
index 000000000000..2c816b0e7762
--- /dev/null
+++ b/include/asm-xtensa/posix_types.h
@@ -0,0 +1,123 @@
+/*
+ * include/asm-xtensa/posix_types.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Largely copied from include/asm-ppc/posix_types.h
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_POSIX_TYPES_H
+#define _XTENSA_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define __FD_ZERO(set)  \
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned int *tmp = (unsigned int *)p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                        case 8:
+                                tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+                                tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+                                return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _XTENSA_POSIX_TYPES_H */
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h
new file mode 100644
index 000000000000..9cab5e4298b9
--- /dev/null
+++ b/include/asm-xtensa/processor.h
@@ -0,0 +1,205 @@
+/*
+ * include/asm-xtensa/processor.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PROCESSOR_H
+#define _XTENSA_PROCESSOR_H
+
+#ifdef __ASSEMBLY__
+#define _ASMLANGUAGE
+#endif
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+#include <xtensa/config/tie.h>
+#include <xtensa/config/system.h>
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+#include <asm/coprocessor.h>
+
+/* Assertions. */
+
+#if (XCHAL_HAVE_WINDOWED != 1)
+#error Linux requires the Xtensa Windowed Registers Option.
+#endif
+
+/*
+ * User space process size: 1 GB.
+ * Windowed call ABI requires caller and callee to be located within the same
+ * 1 GB region. The C compiler places trampoline code on the stack for sources
+ * that take the address of a nested C function (a feature used by glibc), so
+ * the 1 GB requirement applies to the stack as well.
+ */
+
+#define TASK_SIZE       0x40000000
+
+/*
+ * General exception cause assigned to debug exceptions. Debug exceptions go
+ * to their own vector, rather than the general exception vectors (user,
+ * kernel, double); and their specific causes are reported via DEBUGCAUSE
+ * rather than EXCCAUSE.  However it is sometimes convenient to redirect debug
+ * exceptions to the general exception mechanism.  To do this, an otherwise
+ * unused EXCCAUSE value was assigned to debug exceptions for this purpose.
+ */
+
+#define EXCCAUSE_MAPPED_DEBUG   63
+
+/*
+ * We use DEPC also as a flag to distinguish between double and regular
+ * exceptions. For performance reasons, DEPC might contain the value of
+ * EXCCAUSE for regular exceptions, so we use this definition to mark a
+ * valid double exception address.
+ * (Note: We use it in bgeui, so it should be 64, 128, or 256)
+ */
+
+#define VALID_DOUBLE_EXCEPTION_ADDRESS  64
+
+/* LOCKLEVEL defines the interrupt level that masks all
+ * general-purpose interrupts.
+ */
+#define LOCKLEVEL 1
+
+/* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE
+ * registers
+ */
+#define WSBITS  (XCHAL_NUM_AREGS / 4)      /* width of WINDOWSTART in bits */
+#define WBBITS  (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */
+
+#ifndef __ASSEMBLY__
+
+/* Build a valid return address for the specified call winsize.
+ * winsize must be 1 (call4), 2 (call8), or 3 (call12)
+ */
+#define MAKE_RA_FOR_CALL(ra,ws)   (((ra) & 0x3fffffff) | (ws) << 30)
+
+/* Convert return address to a valid pc
+ * Note: We assume that the stack pointer is in the same 1GB ranges as the ra
+ */
+#define MAKE_PC_FROM_RA(ra,sp)    (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
+
+typedef struct {
+    unsigned long seg;
+} mm_segment_t;
+
+struct thread_struct {
+
+        /* kernel's return address and stack pointer for context switching */
+        unsigned long ra; /* kernel's a0: return address and window call size */
+        unsigned long sp; /* kernel's a1: stack pointer */
+
+        mm_segment_t current_ds;    /* see uaccess.h for example uses */
+
+        /* struct xtensa_cpuinfo info; */
+
+        unsigned long bad_vaddr; /* last user fault */
+        unsigned long bad_uaddr; /* last kernel fault accessing user space */
+        unsigned long error_code;
+
+        unsigned long ibreak[XCHAL_NUM_IBREAK];
+        unsigned long dbreaka[XCHAL_NUM_DBREAK];
+        unsigned long dbreakc[XCHAL_NUM_DBREAK];
+
+        /* Allocate storage for extra state and coprocessor state. */
+        unsigned char cp_save[XTENSA_CP_EXTRA_SIZE]
+                __attribute__ ((aligned(XTENSA_CP_EXTRA_ALIGN)));
+
+        /* Make structure 16 bytes aligned. */
+        int align[0] __attribute__ ((aligned(16)));
+};
+
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr()  ({ __label__ _l; _l: &&_l;})
+
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 2)
+
+#define INIT_THREAD  \
+{                                                                       \
+        ra:             0,                                              \
+        sp:             sizeof(init_stack) + (long) &init_stack,        \
+        current_ds:     {0},                                            \
+        /*info:         {0}, */                                         \
+        bad_vaddr:      0,                                              \
+        bad_uaddr:      0,                                              \
+        error_code:     0,                                              \
+}
+
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ * Note: We set-up ps as if we did a call4 to the new pc.
+ *       set_thread_state in signal.c depends on it.
+ */
+#define USER_PS_VALUE ( (1 << XCHAL_PS_WOE_SHIFT) + \
+                        (1 << XCHAL_PS_CALLINC_SHIFT) + \
+                        (USER_RING << XCHAL_PS_RING_SHIFT) + \
+                        (1 << XCHAL_PS_PROGSTACK_SHIFT) + \
+                        (1 << XCHAL_PS_EXCM_SHIFT) )
+
+/* Clearing a0 terminates the backtrace. */
+#define start_thread(regs, new_pc, new_sp) \
+        regs->pc = new_pc; \
+        regs->ps = USER_PS_VALUE; \
+        regs->areg[1] = new_sp; \
+        regs->areg[0] = 0; \
+        regs->wmask = 1; \
+        regs->depc = 0; \
+        regs->windowbase = 0; \
+        regs->windowstart = 1;
+
+/* Forward declaration */
+struct task_struct;
+struct mm_struct;
+
+// FIXME: do we need release_thread for CP??
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+// FIXME: do we need prepare_to_copy (lazy status) for CP??
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Copy and release all segment info associated with a VM */
+
+#define copy_segments(p, mm)    do { } while(0)
+#define release_segments(mm)    do { } while(0)
+#define forget_segments()       do { } while (0)
+
+#define thread_saved_pc(tsk)    (xtensa_pt_regs(tsk)->pc)
+
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)           (xtensa_pt_regs(tsk)->pc)
+#define KSTK_ESP(tsk)           (xtensa_pt_regs(tsk)->areg[1])
+
+#define cpu_relax()  do { } while (0)
+
+/* Special register access. */
+
+#define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
+#define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
+
+#define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
+#define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
+
+#endif  /* __ASSEMBLY__ */
+#endif  /* _XTENSA_PROCESSOR_H */
diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h
new file mode 100644
index 000000000000..2848a5ff8349
--- /dev/null
+++ b/include/asm-xtensa/ptrace.h
@@ -0,0 +1,135 @@
+/*
+ * include/asm-xtensa/ptrace.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PTRACE_H
+#define _XTENSA_PTRACE_H
+
+#include <xtensa/config/core.h>
+
+/*
+ * Kernel stack
+ *
+ *              +-----------------------+  -------- STACK_SIZE
+ *              |     register file     |  |
+ *              +-----------------------+  |
+ *              |    struct pt_regs     |  |
+ *              +-----------------------+  | ------ PT_REGS_OFFSET
+ * double       :  16 bytes spill area  :  |  ^
+ * excetion     :- - - - - - - - - - - -:  |  |
+ * frame        :    struct pt_regs     :  |  |
+ *              :- - - - - - - - - - - -:  |  |
+ *              |                       |  |  |
+ *              |     memory stack      |  |  |
+ *              |                       |  |  |
+ *              ~                       ~  ~  ~
+ *              ~                       ~  ~  ~
+ *              |                       |  |  |
+ *              |                       |  |  |
+ *              +-----------------------+  |  | --- STACK_BIAS
+ *              |  struct task_struct   |  |  |  ^
+ *  current --> +-----------------------+  |  |  |
+ *              |  struct thread_info   |  |  |  |
+ *              +-----------------------+ --------
+ */
+
+#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
+
+/*  Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables). */
+
+#define EXC_TABLE_KSTK          0x004   /* Kernel Stack */
+#define EXC_TABLE_DOUBLE_SAVE   0x008   /* Double exception save area for a0 */
+#define EXC_TABLE_FIXUP         0x00c   /* Fixup handler */
+#define EXC_TABLE_PARAM         0x010   /* For passing a parameter to fixup */
+#define EXC_TABLE_SYSCALL_SAVE  0x014   /* For fast syscall handler */
+#define EXC_TABLE_FAST_USER     0x100   /* Fast user exception handler */
+#define EXC_TABLE_FAST_KERNEL   0x200   /* Fast kernel exception handler */
+#define EXC_TABLE_DEFAULT       0x300   /* Default C-Handler */
+#define EXC_TABLE_SIZE          0x400
+
+/* Registers used by strace */
+
+#define REG_A_BASE      0xfc000000
+#define REG_AR_BASE     0x04000000
+#define REG_PC          0x14000000
+#define REG_PS          0x080000e6
+#define REG_WB          0x08000048
+#define REG_WS          0x08000049
+#define REG_LBEG        0x08000000
+#define REG_LEND        0x08000001
+#define REG_LCOUNT      0x08000002
+#define REG_SAR         0x08000003
+#define REG_DEPC        0x080000c0
+#define REG_EXCCAUSE    0x080000e8
+#define REG_EXCVADDR    0x080000ee
+#define SYSCALL_NR      0x1
+
+#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
+
+/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
+
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_GETFPREGSIZE       18
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+        unsigned long pc;               /*   4 */
+        unsigned long ps;               /*   8 */
+        unsigned long depc;             /*  12 */
+        unsigned long exccause;         /*  16 */
+        unsigned long excvaddr;         /*  20 */
+        unsigned long debugcause;       /*  24 */
+        unsigned long wmask;            /*  28 */
+        unsigned long lbeg;             /*  32 */
+        unsigned long lend;             /*  36 */
+        unsigned long lcount;           /*  40 */
+        unsigned long sar;              /*  44 */
+        unsigned long windowbase;       /*  48 */
+        unsigned long windowstart;      /*  52 */
+        unsigned long syscall;          /*  56 */
+        int reserved[2];                /*  64 */
+
+        /* Make sure the areg field is 16 bytes aligned. */
+        int align[0] __attribute__ ((aligned(16)));
+
+        /* current register frame.
+         * Note: The ESF for kernel exceptions ends after 16 registers!
+         */
+        unsigned long areg[16];         /* 128 (64) */
+};
+
+#ifdef __KERNEL__
+# define xtensa_pt_regs(tsk) ((struct pt_regs*) \
+  (((long)(tsk)->thread_info + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4)) - 1)
+# define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
+# define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+# ifndef CONFIG_SMP
+#  define profile_pc(regs) instruction_pointer(regs)
+# endif
+#endif /* __KERNEL__ */
+
+#else   /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+# include <asm/offsets.h>
+#define PT_REGS_OFFSET    (KERNEL_STACK_SIZE - PT_USER_SIZE)
+#endif
+
+#endif  /* !__ASSEMBLY__ */
+#endif  /* _XTENSA_PTRACE_H */
diff --git a/include/asm-xtensa/resource.h b/include/asm-xtensa/resource.h
new file mode 100644
index 000000000000..17b5ab311771
--- /dev/null
+++ b/include/asm-xtensa/resource.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/resource.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_RESOURCE_H
+#define _XTENSA_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif  /* _XTENSA_RESOURCE_H */
diff --git a/include/asm-xtensa/rmap.h b/include/asm-xtensa/rmap.h
new file mode 100644
index 000000000000..649588b7e9ad
--- /dev/null
+++ b/include/asm-xtensa/rmap.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/rmap.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_RMAP_H
+#define _XTENSA_RMAP_H
+
+#include <asm-generic/rmap.h>
+
+#endif
diff --git a/include/asm-xtensa/rwsem.h b/include/asm-xtensa/rwsem.h
new file mode 100644
index 000000000000..3c02b0e033f0
--- /dev/null
+++ b/include/asm-xtensa/rwsem.h
@@ -0,0 +1,175 @@
+/*
+ * include/asm-xtensa/rwsem.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Largely copied from include/asm-ppc/rwsem.h
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_RWSEM_H
+#define _XTENSA_RWSEM_H
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        signed long             count;
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#if RWSEM_DEBUG
+        int                     debug;
+#endif
+};
+
+/*
+ * initialisation
+ */
+#if RWSEM_DEBUG
+#define __RWSEM_DEBUG_INIT      , 0
+#else
+#define __RWSEM_DEBUG_INIT      /* */
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEBUG_INIT }
+
+#define DECLARE_RWSEM(name)             \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+static inline void init_rwsem(struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+#if RWSEM_DEBUG
+        sem->debug = 0;
+#endif
+}
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        if (atomic_add_return(1,(atomic_t *)(&sem->count)) > 0)
+                smp_wmb();
+        else
+                rwsem_down_read_failed(sem);
+}
+
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg(&sem->count, tmp,
+                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
+                        smp_wmb();
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
+                                (atomic_t *)(&sem->count));
+        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
+                smp_wmb();
+        else
+                rwsem_down_write_failed(sem);
+}
+
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+                      RWSEM_ACTIVE_WRITE_BIAS);
+        smp_wmb();
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_sub_return(1,(atomic_t *)(&sem->count));
+        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        smp_wmb();
+        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
+                              (atomic_t *)(&sem->count)) < 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
+        if (tmp < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        smp_mb();
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+#endif  /* _XTENSA_RWSEM_XADD_H */
diff --git a/include/asm-xtensa/scatterlist.h b/include/asm-xtensa/scatterlist.h
new file mode 100644
index 000000000000..38a2b9acd658
--- /dev/null
+++ b/include/asm-xtensa/scatterlist.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-xtensa/scatterlist.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SCATTERLIST_H
+#define _XTENSA_SCATTERLIST_H
+
+struct scatterlist {
+        struct page     *page;
+        unsigned int    offset;
+        dma_addr_t      dma_address;
+        unsigned int    length;
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+
+#define ISA_DMA_THRESHOLD (~0UL)
+
+#endif  /* _XTENSA_SCATTERLIST_H */
diff --git a/include/asm-xtensa/sections.h b/include/asm-xtensa/sections.h
new file mode 100644
index 000000000000..40b5191b55a2
--- /dev/null
+++ b/include/asm-xtensa/sections.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/sections.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SECTIONS_H
+#define _XTENSA_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif  /* _XTENSA_SECTIONS_H */
diff --git a/include/asm-xtensa/segment.h b/include/asm-xtensa/segment.h
new file mode 100644
index 000000000000..a2eb547a1a75
--- /dev/null
+++ b/include/asm-xtensa/segment.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/segment.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SEGMENT_H
+#define _XTENSA_SEGMENT_H
+
+#include <asm/uaccess.h>
+
+#endif  /* _XTENSA_SEGEMENT_H */
diff --git a/include/asm-xtensa/semaphore.h b/include/asm-xtensa/semaphore.h
new file mode 100644
index 000000000000..db740b8bc6f0
--- /dev/null
+++ b/include/asm-xtensa/semaphore.h
@@ -0,0 +1,129 @@
+/*
+ * linux/include/asm-xtensa/semaphore.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SEMAPHORE_H
+#define _XTENSA_SEMAPHORE_H
+
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <linux/wait.h>
+#include <linux/rwsem.h>
+
+struct semaphore {
+        atomic_t count;
+        int sleepers;
+        wait_queue_head_t wait;
+#if WAITQUEUE_DEBUG
+        long __magic;
+#endif
+};
+
+#if WAITQUEUE_DEBUG
+# define __SEM_DEBUG_INIT(name) \
+                , (int)&(name).__magic
+#else
+# define __SEM_DEBUG_INIT(name)
+#endif
+
+#define __SEMAPHORE_INITIALIZER(name,count)                     \
+        { ATOMIC_INIT(count),                                   \
+          0,                                                    \
+          __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)            \
+        __SEM_DEBUG_INIT(name) }
+
+#define __MUTEX_INITIALIZER(name) \
+        __SEMAPHORE_INITIALIZER(name, 1)
+
+#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
+        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
+
+#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
+#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
+
+static inline void sema_init (struct semaphore *sem, int val)
+{
+/*
+ *      *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val);
+ *
+ * i'd rather use the more flexible initialization above, but sadly
+ * GCC 2.7.2.3 emits a bogus warning. EGCS doesnt. Oh well.
+ */
+        atomic_set(&sem->count, val);
+        init_waitqueue_head(&sem->wait);
+#if WAITQUEUE_DEBUG
+        sem->__magic = (int)&sem->__magic;
+#endif
+}
+
+static inline void init_MUTEX (struct semaphore *sem)
+{
+        sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED (struct semaphore *sem)
+{
+        sema_init(sem, 0);
+}
+
+asmlinkage void __down(struct semaphore * sem);
+asmlinkage int  __down_interruptible(struct semaphore * sem);
+asmlinkage int  __down_trylock(struct semaphore * sem);
+asmlinkage void __up(struct semaphore * sem);
+
+extern spinlock_t semaphore_wake_lock;
+
+static inline void down(struct semaphore * sem)
+{
+#if WAITQUEUE_DEBUG
+        CHECK_MAGIC(sem->__magic);
+#endif
+
+        if (atomic_sub_return(1, &sem->count) < 0)
+                __down(sem);
+}
+
+static inline int down_interruptible(struct semaphore * sem)
+{
+        int ret = 0;
+#if WAITQUEUE_DEBUG
+        CHECK_MAGIC(sem->__magic);
+#endif
+
+        if (atomic_sub_return(1, &sem->count) < 0)
+                ret = __down_interruptible(sem);
+        return ret;
+}
+
+static inline int down_trylock(struct semaphore * sem)
+{
+        int ret = 0;
+#if WAITQUEUE_DEBUG
+        CHECK_MAGIC(sem->__magic);
+#endif
+
+        if (atomic_sub_return(1, &sem->count) < 0)
+                ret = __down_trylock(sem);
+        return ret;
+}
+
+/*
+ * Note! This is subtle. We jump to wake people up only if
+ * the semaphore was negative (== somebody was waiting on it).
+ */
+static inline void up(struct semaphore * sem)
+{
+#if WAITQUEUE_DEBUG
+        CHECK_MAGIC(sem->__magic);
+#endif
+        if (atomic_add_return(1, &sem->count) <= 0)
+                __up(sem);
+}
+
+#endif /* _XTENSA_SEMAPHORE_H */
diff --git a/include/asm-xtensa/sembuf.h b/include/asm-xtensa/sembuf.h
new file mode 100644
index 000000000000..2d26c47666fe
--- /dev/null
+++ b/include/asm-xtensa/sembuf.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-xtensa/sembuf.h
+ *
+ * The semid64_ds structure for Xtensa architecture.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ *
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ *
+ */
+
+#ifndef _XTENSA_SEMBUF_H
+#define _XTENSA_SEMBUF_H
+
+#include <asm/byteorder.h>
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+#if XCHAL_HAVE_LE
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused1;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   __unused2;
+#else
+        unsigned long   __unused1;
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused2;
+        __kernel_time_t sem_ctime;              /* last change time */
+#endif
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* __ASM_XTENSA_SEMBUF_H */
diff --git a/include/asm-xtensa/serial.h b/include/asm-xtensa/serial.h
new file mode 100644
index 000000000000..ec04114fcf0b
--- /dev/null
+++ b/include/asm-xtensa/serial.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-xtensa/serial.h
+ *
+ * Configuration details for 8250, 16450, 16550, etc. serial ports
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SERIAL_H
+#define _XTENSA_SERIAL_H
+
+#include <asm/platform/serial.h>
+
+#endif  /* _XTENSA_SERIAL_H */
diff --git a/include/asm-xtensa/setup.h b/include/asm-xtensa/setup.h
new file mode 100644
index 000000000000..e3636520d8cc
--- /dev/null
+++ b/include/asm-xtensa/setup.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/setup.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SETUP_H
+#define _XTENSA_SETUP_H
+
+#define COMMAND_LINE_SIZE       256
+
+#endif
diff --git a/include/asm-ppc/shmbuf.h b/include/asm-xtensa/shmbuf.h
index 7ac0bd38cbd8..a30b81a4b933 100644
--- a/include/asm-ppc/shmbuf.h
+++ b/include/asm-xtensa/shmbuf.h
@@ -1,25 +1,38 @@
-#ifndef _PPC_SHMBUF_H
-#define _PPC_SHMBUF_H
-
 /*
- * The shmid64_ds structure for PPC architecture.
+ * include/asm-xtensa/shmbuf.h
+ *
+ * The shmid64_ds structure for Xtensa architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
  */
 
+#ifndef _XTENSA_SHMBUF_H
+#define _XTENSA_SHMBUF_H
+
 struct shmid64_ds {
         struct ipc64_perm       shm_perm;       /* operation perms */
-        unsigned int            __unused1;
+        size_t                  shm_segsz;      /* size of segment (bytes) */
         __kernel_time_t         shm_atime;      /* last attach time */
-        unsigned int            __unused2;
+        unsigned long           __unused1;
         __kernel_time_t         shm_dtime;      /* last detach time */
-        unsigned int            __unused3;
+        unsigned long           __unused2;
         __kernel_time_t         shm_ctime;      /* last change time */
-        unsigned int            __unused4;
-        size_t                  shm_segsz;      /* size of segment (bytes) */
+        unsigned long           __unused3;
         __kernel_pid_t          shm_cpid;       /* pid of creator */
         __kernel_pid_t          shm_lpid;       /* pid of last operator */
         unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
         unsigned long           __unused5;
-        unsigned long           __unused6;
 };
 
 struct shminfo64 {
@@ -34,4 +47,4 @@ struct shminfo64 {
         unsigned long   __unused4;
 };
 
-#endif /* _PPC_SHMBUF_H */
+#endif  /* _XTENSA_SHMBUF_H */
diff --git a/include/asm-xtensa/shmparam.h b/include/asm-xtensa/shmparam.h
new file mode 100644
index 000000000000..d3b65bfa71c3
--- /dev/null
+++ b/include/asm-xtensa/shmparam.h
@@ -0,0 +1,23 @@
+/*
+ * include/asm-xtensa/shmparam.h
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ */
+
+#ifndef _XTENSA_SHMPARAM_H
+#define _XTENSA_SHMPARAM_H
+
+#include <asm/processor.h>
+
+/*
+ * Xtensa can have variable size caches, and if
+ * the size of single way is larger than the page size,
+ * then we have to start worrying about cache aliasing
+ * problems.
+ */
+
+#define SHMLBA  ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
+
+#endif /* _XTENSA_SHMPARAM_H */
diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h
new file mode 100644
index 000000000000..a75177291418
--- /dev/null
+++ b/include/asm-xtensa/sigcontext.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-xtensa/sigcontext.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2003 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SIGCONTEXT_H
+#define _XTENSA_SIGCONTEXT_H
+
+#define _ASMLANGUAGE
+#include <asm/processor.h>
+#include <asm/coprocessor.h>
+
+
+struct _cpstate {
+        unsigned char _cpstate[XTENSA_CP_EXTRA_SIZE];
+} __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
+
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+        /* CPU registers */
+        unsigned long sc_pc;
+        unsigned long sc_ps;
+        unsigned long sc_wmask;
+        unsigned long sc_windowbase;
+        unsigned long sc_windowstart;
+        unsigned long sc_lbeg;
+        unsigned long sc_lend;
+        unsigned long sc_lcount;
+        unsigned long sc_sar;
+        unsigned long sc_depc;
+        unsigned long sc_dareg0;
+        unsigned long sc_treg[4];
+        unsigned long sc_areg[XCHAL_NUM_AREGS];
+        struct _cpstate *sc_cpstate;
+};
+
+#endif /* __ASM_XTENSA_SIGCONTEXT_H */
diff --git a/include/asm-xtensa/siginfo.h b/include/asm-xtensa/siginfo.h
new file mode 100644
index 000000000000..44f0ae77b539
--- /dev/null
+++ b/include/asm-xtensa/siginfo.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/processor.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SIGINFO_H
+#define _XTENSA_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif  /* _XTENSA_SIGINFO_H */
diff --git a/include/asm-xtensa/signal.h b/include/asm-xtensa/signal.h
new file mode 100644
index 000000000000..5d6fc9cdf58d
--- /dev/null
+++ b/include/asm-xtensa/signal.h
@@ -0,0 +1,187 @@
+/*
+ * include/asm-xtensa/signal.h
+ *
+ * Swiped from SH.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SIGNAL_H
+#define _XTENSA_SIGNAL_H
+
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#endif
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/* #define SIGLOST              29 */
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        (_NSIG-1)
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002 /* not supported yet */
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+#define SA_INTERRUPT    0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER     0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#ifndef __ASSEMBLY__
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE                SA_ONESHOT
+#define SA_SAMPLE_RANDOM        SA_RESTART
+#define SA_SHIRQ                0x04000000
+#endif
+
+#define SIG_BLOCK          0    /* for blocking signals */
+#define SIG_UNBLOCK        1    /* for unblocking signals */
+#define SIG_SETMASK        2    /* for setting the signal mask */
+
+/* Type of a signal handler.  */
+typedef void (*__sighandler_t)(int);
+
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+#else
+
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif  /* __KERNEL__ */
+#endif  /* __ASSEMBLY__ */
+#endif  /* _XTENSA_SIGNAL_H */
diff --git a/include/asm-xtensa/smp.h b/include/asm-xtensa/smp.h
new file mode 100644
index 000000000000..83c569e3bdbd
--- /dev/null
+++ b/include/asm-xtensa/smp.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-xtensa/smp.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SMP_H
+#define _XTENSA_SMP_H
+
+extern struct xtensa_cpuinfo boot_cpu_data;
+
+#define cpu_data (&boot_cpu_data)
+#define current_cpu_data boot_cpu_data
+
+struct xtensa_cpuinfo {
+        unsigned long   *pgd_cache;
+        unsigned long   *pte_cache;
+        unsigned long   pgtable_cache_sz;
+};
+
+#define cpu_logical_map(cpu)    (cpu)
+
+#endif  /* _XTENSA_SMP_H */
diff --git a/include/asm-ppc/socket.h b/include/asm-xtensa/socket.h
index 4134376b0f66..00f83f3a6d72 100644
--- a/include/asm-ppc/socket.h
+++ b/include/asm-xtensa/socket.h
@@ -1,15 +1,19 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp */
-
-/* For setsockopt(2) */
+/*
+ * include/asm-xtensa/socket.h
+ *
+ * Copied from i386.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _XTENSA_SOCKET_H
+#define _XTENSA_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockoptions(2) */
 #define SOL_SOCKET      1
 
 #define SO_DEBUG        1
@@ -20,6 +24,8 @@
 #define SO_BROADCAST    6
 #define SO_SNDBUF       7
 #define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
 #define SO_KEEPALIVE    9
 #define SO_OOBINLINE    10
 #define SO_NO_CHECK     11
@@ -27,14 +33,15 @@
 #define SO_LINGER       13
 #define SO_BSDCOMPAT    14
 /* To add :#define SO_REUSEPORT 15 */
-#define SO_RCVLOWAT     16
-#define SO_SNDLOWAT     17
-#define SO_RCVTIMEO     18
-#define SO_SNDTIMEO     19
-#define SO_PASSCRED     20
-#define SO_PEERCRED     21
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
 
 /* Security levels - as per NRL IPv6 - don't actually do anything */
+
 #define SO_SECURITY_AUTHENTICATION              22
 #define SO_SECURITY_ENCRYPTION_TRANSPORT        23
 #define SO_SECURITY_ENCRYPTION_NETWORK          24
@@ -42,15 +49,15 @@
 #define SO_BINDTODEVICE 25
 
 /* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
+
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
 
 #define SO_PEERNAME             28
 #define SO_TIMESTAMP            29
 #define SCM_TIMESTAMP           SO_TIMESTAMP
 
 #define SO_ACCEPTCONN           30
-
 #define SO_PEERSEC              31
 
-#endif /* _ASM_SOCKET_H */
+#endif  /* _XTENSA_SOCKET_H */
diff --git a/include/asm-xtensa/sockios.h b/include/asm-xtensa/sockios.h
new file mode 100644
index 000000000000..20d2ba10ecd1
--- /dev/null
+++ b/include/asm-xtensa/sockios.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-xtensa/sockios.h
+ *
+ * Socket-level I/O control calls.  Copied from MIPS.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ * Copyright (C) 2001 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SOCKIOS_H
+#define _XTENSA_SOCKIOS_H
+
+#include <asm/ioctl.h>
+
+/* Socket-level I/O control calls. */
+
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      0x8906          /* Get stamp - linux-specific */
+
+#endif  /* _XTENSA_SOCKIOS_H */
diff --git a/include/asm-xtensa/spinlock.h b/include/asm-xtensa/spinlock.h
new file mode 100644
index 000000000000..8ff23649581b
--- /dev/null
+++ b/include/asm-xtensa/spinlock.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/spinlock.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SPINLOCK_H
+#define _XTENSA_SPINLOCK_H
+
+#include <linux/spinlock.h>
+
+#endif  /* _XTENSA_SPINLOCK_H */
diff --git a/include/asm-xtensa/stat.h b/include/asm-xtensa/stat.h
new file mode 100644
index 000000000000..2f4662ff6c3a
--- /dev/null
+++ b/include/asm-xtensa/stat.h
@@ -0,0 +1,105 @@
+/*
+ * include/asm-xtensa/stat.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_STAT_H
+#define _XTENSA_STAT_H
+
+#include <linux/types.h>
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc-2.2.3. */
+
+struct stat64  {
+#ifdef __XTENSA_EL__
+        unsigned short  st_dev;         /* Device */
+        unsigned char   __pad0[10];
+#else
+        unsigned char   __pad0[6];
+        unsigned short  st_dev;
+        unsigned char   __pad1[2];
+#endif
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long __st_ino;         /* 32bit file serial number. */
+
+        unsigned int  st_mode;          /* File mode. */
+        unsigned int  st_nlink;         /* Link count. */
+        unsigned int  st_uid;           /* User ID of the file's owner. */
+        unsigned int  st_gid;           /* Group ID of the file's group. */
+
+#ifdef __XTENSA_EL__
+        unsigned short  st_rdev;        /* Device number, if device. */
+        unsigned char   __pad3[10];
+#else
+        unsigned char   __pad2[6];
+        unsigned short  st_rdev;
+        unsigned char   __pad3[2];
+#endif
+
+        long long int  st_size;         /* Size of file, in bytes. */
+        long int st_blksize;            /* Optimal block size for I/O. */
+
+#ifdef __XTENSA_EL__
+        unsigned long  st_blocks;       /* Number 512-byte blocks allocated. */
+        unsigned long  __pad4;
+#else
+        unsigned long  __pad4;
+        unsigned long  st_blocks;
+#endif
+
+        unsigned long  __pad5;
+        long int st_atime;              /* Time of last access. */
+        unsigned long  st_atime_nsec;
+        long int st_mtime;              /* Time of last modification. */
+        unsigned long  st_mtime_nsec;
+        long int  st_ctime;             /* Time of last status change. */
+        unsigned long  st_ctime_nsec;
+        unsigned long long int st_ino;  /* File serial number. */
+};
+
+#endif  /* _XTENSA_STAT_H */
diff --git a/include/asm-xtensa/statfs.h b/include/asm-xtensa/statfs.h
new file mode 100644
index 000000000000..9c3d1a213136
--- /dev/null
+++ b/include/asm-xtensa/statfs.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-xtensa/statfs.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_STATFS_H
+#define _XTENSA_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif  /* _XTENSA_STATFS_H */
+
diff --git a/include/asm-xtensa/string.h b/include/asm-xtensa/string.h
new file mode 100644
index 000000000000..5fb8c27cbef5
--- /dev/null
+++ b/include/asm-xtensa/string.h
@@ -0,0 +1,124 @@
+/*
+ * include/asm-xtensa/string.h
+ *
+ * These trivial string functions are considered part of the public domain.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+/* We should optimize these. See arch/xtensa/lib/strncpy_user.S */
+
+#ifndef _XTENSA_STRING_H
+#define _XTENSA_STRING_H
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        __asm__ __volatile__("1:\n\t"
+                "l8ui   %2, %1, 0\n\t"
+                "s8i    %2, %0, 0\n\t"
+                "addi   %1, %1, 1\n\t"
+                "addi   %0, %0, 1\n\t"
+                "bnez   %2, 1b\n\t"
+                : "=r" (__dest), "=r" (__src), "=&r" (__dummy)
+                : "0" (__dest), "1" (__src)
+                : "memory");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        if (__n == 0)
+                return __xdest;
+
+        __asm__ __volatile__(
+                "1:\n\t"
+                "l8ui   %2, %1, 0\n\t"
+                "s8i    %2, %0, 0\n\t"
+                "addi   %1, %1, 1\n\t"
+                "addi   %0, %0, 1\n\t"
+                "beqz   %2, 2f\n\t"
+                "bne    %1, %5, 1b\n"
+                "2:"
+                : "=r" (__dest), "=r" (__src), "=&r" (__dummy)
+                : "0" (__dest), "1" (__src), "r" (__src+__n)
+                : "memory");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "1:\n\t"
+                "l8ui   %3, %1, 0\n\t"
+                "addi   %1, %1, 1\n\t"
+                "l8ui   %2, %0, 0\n\t"
+                "addi   %0, %0, 1\n\t"
+                "beqz   %2, 2f\n\t"
+                "beq    %2, %3, 1b\n"
+                "2:\n\t"
+                "sub    %2, %3, %2"
+                : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
+                : "0" (__cs), "1" (__ct));
+
+        return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "mov    %2, %3\n"
+                "1:\n\t"
+                "beq    %0, %6, 2f\n\t"
+                "l8ui   %3, %1, 0\n\t"
+                "addi   %1, %1, 1\n\t"
+                "l8ui   %2, %0, 0\n\t"
+                "addi   %0, %0, 1\n\t"
+                "beqz   %2, 2f\n\t"
+                "beqz   %3, 2f\n\t"
+                "beq    %2, %3, 1b\n"
+                "2:\n\t"
+                "sub    %2, %3, %2"
+                : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
+                : "0" (__cs), "1" (__ct), "r" (__cs+__n));
+
+        return __res;
+}
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+/* Don't build bcopy at all ...  */
+#define __HAVE_ARCH_BCOPY
+
+#define __HAVE_ARCH_MEMSCAN
+#define memscan memchr
+
+#endif  /* _XTENSA_STRING_H */
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
new file mode 100644
index 000000000000..f09393232e5e
--- /dev/null
+++ b/include/asm-xtensa/system.h
@@ -0,0 +1,252 @@
+/*
+ * include/asm-xtensa/system.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_SYSTEM_H
+#define _XTENSA_SYSTEM_H
+
+#include <linux/config.h>
+#include <linux/stringify.h>
+
+#include <asm/processor.h>
+
+/* interrupt control */
+
+#define local_save_flags(x)                                             \
+        __asm__ __volatile__ ("rsr %0,"__stringify(PS) : "=a" (x));
+#define local_irq_restore(x)    do {                                    \
+        __asm__ __volatile__ ("wsr %0, "__stringify(PS)" ; rsync"       \
+                              :: "a" (x) : "memory"); } while(0);
+#define local_irq_save(x)       do {                                    \
+        __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)         \
+                              : "=a" (x) :: "memory");} while(0);
+
+static inline void local_irq_disable(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)
+                              : "=a" (flags) :: "memory");
+}
+static inline void local_irq_enable(void)
+{
+        unsigned long flags;
+        __asm__ __volatile__ ("rsil %0, 0" : "=a" (flags) :: "memory");
+
+}
+
+static inline int irqs_disabled(void)
+{
+        unsigned long flags;
+        local_save_flags(flags);
+        return flags & 0xf;
+}
+
+#define RSR_CPENABLE(x) do {                                              \
+        __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
+        } while(0);
+#define WSR_CPENABLE(x) do {                                              \
+        __asm__ __volatile__("wsr %0," __stringify(CPENABLE)";rsync"      \
+                             :: "a" (x));} while(0);
+
+#define clear_cpenable() __clear_cpenable()
+
+static inline void __clear_cpenable(void)
+{
+#if XCHAL_HAVE_CP
+        unsigned long i = 0;
+        WSR_CPENABLE(i);
+#endif
+}
+
+static inline void enable_coprocessor(int i)
+{
+#if XCHAL_HAVE_CP
+        int cp;
+        RSR_CPENABLE(cp);
+        cp |= 1 << i;
+        WSR_CPENABLE(cp);
+#endif
+}
+
+static inline void disable_coprocessor(int i)
+{
+#if XCHAL_HAVE_CP
+        int cp;
+        RSR_CPENABLE(cp);
+        cp &= ~(1 << i);
+        WSR_CPENABLE(cp);
+#endif
+}
+
+#define smp_read_barrier_depends() do { } while(0)
+#define read_barrier_depends() do { } while(0)
+
+#define mb()  barrier()
+#define rmb() mb()
+#define wmb() mb()
+
+#ifdef CONFIG_SMP
+#error smp_* not defined
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#endif
+
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
+
+#if !defined (__ASSEMBLY__)
+
+/* * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+extern void *_switch_to(void *last, void *next);
+
+#endif  /* __ASSEMBLY__ */
+
+#define prepare_to_switch()     do { } while(0)
+
+#define switch_to(prev,next,last)               \
+do {                                            \
+        clear_cpenable();                       \
+        (last) = _switch_to(prev, next);        \
+} while(0)
+
+/*
+ * cmpxchg
+ */
+
+static inline unsigned long
+__cmpxchg_u32(volatile int *p, int old, int new)
+{
+  __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
+                       "l32i    %0, %1, 0              \n\t"
+                       "bne     %0, %2, 1f             \n\t"
+                       "s32i    %3, %1, 0              \n\t"
+                       "1:                             \n\t"
+                       "wsr     a15, "__stringify(PS)" \n\t"
+                       "rsync                          \n\t"
+                       : "=&a" (old)
+                       : "a" (p), "a" (old), "r" (new)
+                       : "a15", "memory");
+  return old;
+}
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+        switch (size) {
+        case 4:  return __cmpxchg_u32(ptr, old, new);
+        default: __cmpxchg_called_with_bad_pointer();
+                 return old;
+        }
+}
+
+#define cmpxchg(ptr,o,n)                                                      \
+        ({ __typeof__(*(ptr)) _o_ = (o);                                      \
+           __typeof__(*(ptr)) _n_ = (n);                                      \
+           (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,          \
+                                        (unsigned long)_n_, sizeof (*(ptr))); \
+        })
+
+
+
+
+/*
+ * xchg_u32
+ *
+ * Note that a15 is used here because the register allocation
+ * done by the compiler is not guaranteed and a window overflow
+ * may not occur between the rsil and wsr instructions. By using
+ * a15 in the rsil, the machine is guaranteed to be in a state
+ * where no register reference will cause an overflow.
+ */
+
+static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
+{
+  unsigned long tmp;
+  __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
+                       "l32i    %0, %1, 0              \n\t"
+                       "s32i    %2, %1, 0              \n\t"
+                       "wsr     a15, "__stringify(PS)" \n\t"
+                       "rsync                          \n\t"
+                       : "=&a" (tmp)
+                       : "a" (m), "a" (val)
+                       : "a15", "memory");
+  return tmp;
+}
+
+#define tas(ptr) (xchg((ptr),1))
+
+#if ( __XCC__ == 1 )
+
+/* xt-xcc processes __inline__ differently than xt-gcc and decides to
+ * insert an out-of-line copy of function __xchg.  This presents the
+ * unresolved symbol at link time of __xchg_called_with_bad_pointer,
+ * even though such a function would never be called at run-time.
+ * xt-gcc always inlines __xchg, and optimizes away the undefined
+ * bad_pointer function.
+ */
+
+#define xchg(ptr,x) xchg_u32(ptr,x)
+
+#else  /* assume xt-gcc */
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+/*
+ * This only works if the compiler isn't horribly bad at optimizing.
+ * gcc-2.5.8 reportedly can't handle this, but I define that one to
+ * be dead anyway.
+ */
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+__xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+                case 4:
+                        return xchg_u32(ptr, x);
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+#endif
+
+extern void set_except_vector(int n, void *addr);
+
+static inline void spill_registers(void)
+{
+        unsigned int a0, ps;
+
+        __asm__ __volatile__ (
+                "movi   a14," __stringify (PS_EXCM_MASK) " | 1\n\t"
+                "mov    a12, a0\n\t"
+                "rsr    a13," __stringify(SAR) "\n\t"
+                "xsr    a14," __stringify(PS) "\n\t"
+                "movi   a0, _spill_registers\n\t"
+                "rsync\n\t"
+                "callx0 a0\n\t"
+                "mov    a0, a12\n\t"
+                "wsr    a13," __stringify(SAR) "\n\t"
+                "wsr    a14," __stringify(PS) "\n\t"
+                :: "a" (&a0), "a" (&ps)
+                : "a2", "a3", "a12", "a13", "a14", "a15", "memory");
+}
+
+#define arch_align_stack(x) (x)
+
+#endif  /* _XTENSA_SYSTEM_H */
diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h
new file mode 100644
index 000000000000..c780593ff5f9
--- /dev/null
+++ b/include/asm-xtensa/termbits.h
@@ -0,0 +1,194 @@
+/*
+ * include/asm-xtensa/termbits.h
+ *
+ * Copied from SH.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TERMBITS_H
+#define _XTENSA_TERMBITS_H
+
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+/* c_cc characters */
+
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+/* c_lflag bits */
+
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif  /* _XTENSA_TERMBITS_H */
diff --git a/include/asm-xtensa/termios.h b/include/asm-xtensa/termios.h
new file mode 100644
index 000000000000..83c6aed1d115
--- /dev/null
+++ b/include/asm-xtensa/termios.h
@@ -0,0 +1,122 @@
+/*
+ * include/asm-xtensa/termios.h
+ *
+ * Copied from SH.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TERMIOS_H
+#define _XTENSA_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* Modem lines */
+
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+/* Line disciplines */
+
+#define N_TTY           0
+#define N_SLIP          1
+#define N_MOUSE         2
+#define N_PPP           3
+#define N_STRIP         4
+#define N_AX25          5
+#define N_X25           6       /* X.25 async */
+#define N_6PACK         7
+#define N_MASC          8       /* Reserved for Mobitex module <kaz@cafe.net> */
+#define N_R3964         9       /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA          11      /* Linux IR - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC          13      /* synchronous HDLC */
+#define N_SYNC_PPP      14
+#define N_HCI           15      /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+        unsigned short __tmp; \
+        get_user(__tmp,&(termio)->x); \
+        *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _XTENSA_TERMIOS_H */
diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h
new file mode 100644
index 000000000000..af208d41fd82
--- /dev/null
+++ b/include/asm-xtensa/thread_info.h
@@ -0,0 +1,146 @@
+/*
+ * include/asm-xtensa/thread_info.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_THREAD_INFO_H
+#define _XTENSA_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+# include <asm/processor.h>
+#endif
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ *   must also be changed
+ */
+
+#ifndef __ASSEMBLY__
+
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        unsigned long           status;         /* thread-synchronous flags */
+        __u32                   cpu;            /* current CPU */
+        __s32                   preempt_count;  /* 0 => preemptable,< 0 => BUG*/
+
+        mm_segment_t            addr_limit;     /* thread address space */
+        struct restart_block    restart_block;
+
+
+};
+
+#else /* !__ASSEMBLY__ */
+
+/* offsets into the thread_info struct for assembly code access */
+#define TI_TASK          0x00000000
+#define TI_EXEC_DOMAIN   0x00000004
+#define TI_FLAGS         0x00000008
+#define TI_STATUS        0x0000000C
+#define TI_CPU           0x00000010
+#define TI_PRE_COUNT     0x00000014
+#define TI_ADDR_LIMIT    0x00000018
+#define TI_RESTART_BLOCK 0x000001C
+
+#endif
+
+#define PREEMPT_ACTIVE          0x10000000
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+
+#ifndef __ASSEMBLY__
+
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block = {                      \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+         __asm__("extui %0,a1,0,13\n\t"
+                 "xor %0, a1, %0" : "=&r" (ti) : );
+        return ti;
+}
+
+/* thread information allocation */
+#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
+#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
+#define get_thread_info(ti) get_task_struct((ti)->task)
+#define put_thread_info(ti) put_task_struct((ti)->task)
+
+#else /* !__ASSEMBLY__ */
+
+/* how to get the thread information struct from ASM */
+#define GET_THREAD_INFO(reg,sp) \
+        extui reg, sp, 0, 13; \
+        xor   reg, sp, reg
+#endif
+
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_SINGLESTEP          4       /* restore singlestep on return to user mode */
+#define TIF_IRET                5       /* return with iret */
+#define TIF_MEMDIE              6
+#define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
+#define _TIF_IRET               (1<<TIF_IRET)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
+#define _TIF_ALLWORK_MASK       0x0000FFFF      /* work to do on any return to u-space */
+
+/*
+ * Thread-synchronous status.
+ *
+ * This is different from the flags in that nobody else
+ * ever touches our thread-synchronous status, so we don't
+ * have to worry about atomic accesses.
+ */
+#define TS_USEDFPU              0x0001  /* FPU was used by this task this quantum (SMP) */
+
+#define THREAD_SIZE 8192        //(2*PAGE_SIZE)
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_THREAD_INFO */
diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
new file mode 100644
index 000000000000..d14a3755a12b
--- /dev/null
+++ b/include/asm-xtensa/timex.h
@@ -0,0 +1,94 @@
+/*
+ * include/asm-xtensa/timex.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TIMEX_H
+#define _XTENSA_TIMEX_H
+
+#ifdef __KERNEL__
+
+#include <asm/processor.h>
+#include <linux/stringify.h>
+
+#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
+# define LINUX_TIMER     0
+#elif XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
+# define LINUX_TIMER     1
+#elif XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
+# define LINUX_TIMER     2
+#else
+# error "Bad timer number for Linux configurations!"
+#endif
+
+#define LINUX_TIMER_INT         XCHAL_TIMER_INTERRUPT(LINUX_TIMER)
+#define LINUX_TIMER_MASK        (1L << LINUX_TIMER_INT)
+
+#define CLOCK_TICK_RATE         1193180 /* (everyone is using this value) */
+#define CLOCK_TICK_FACTOR       20 /* Factor of both 10^6 and CLOCK_TICK_RATE */
+#define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
+        (1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
+                << (SHIFT_SCALE-SHIFT_HZ)) / HZ)
+
+#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
+extern unsigned long ccount_per_jiffy;
+extern unsigned long ccount_nsec;
+#define CCOUNT_PER_JIFFY ccount_per_jiffy
+#define CCOUNT_NSEC ccount_nsec
+#else
+#define CCOUNT_PER_JIFFY (CONFIG_XTENSA_CPU_CLOCK*(1000000UL/HZ))
+#define CCOUNT_NSEC (1000000000UL / CONFIG_XTENSA_CPU_CLOCK)
+#endif
+
+
+typedef unsigned long long cycles_t;
+
+/*
+ * Only used for SMP.
+ */
+
+extern cycles_t cacheflush_time;
+
+#define get_cycles()    (0)
+
+
+/*
+ * Register access.
+ */
+
+#define WSR_CCOUNT(r)     __asm__("wsr %0,"__stringify(CCOUNT) :: "a" (r))
+#define RSR_CCOUNT(r)     __asm__("rsr %0,"__stringify(CCOUNT) : "=a" (r))
+#define WSR_CCOMPARE(x,r) __asm__("wsr %0,"__stringify(CCOMPARE_0)"+"__stringify(x) :: "a"(r))
+#define RSR_CCOMPARE(x,r) __asm__("rsr %0,"__stringify(CCOMPARE_0)"+"__stringify(x) : "=a"(r))
+
+static inline unsigned long get_ccount (void)
+{
+        unsigned long ccount;
+        RSR_CCOUNT(ccount);
+        return ccount;
+}
+
+static inline void set_ccount (unsigned long ccount)
+{
+        WSR_CCOUNT(ccount);
+}
+
+static inline unsigned long get_linux_timer (void)
+{
+        unsigned ccompare;
+        RSR_CCOMPARE(LINUX_TIMER, ccompare);
+        return ccompare;
+}
+
+static inline void set_linux_timer (unsigned long ccompare)
+{
+        WSR_CCOMPARE(LINUX_TIMER, ccompare);
+}
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_TIMEX_H */
diff --git a/include/asm-xtensa/tlb.h b/include/asm-xtensa/tlb.h
new file mode 100644
index 000000000000..4562b2dcfbc0
--- /dev/null
+++ b/include/asm-xtensa/tlb.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-xtensa/tlb.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TLB_H
+#define _XTENSA_TLB_H
+
+#define tlb_start_vma(tlb,vma)                  do { } while (0)
+#define tlb_end_vma(tlb,vma)                    do { } while (0)
+#define __tlb_remove_tlb_entry(tlb,pte,addr)    do { } while (0)
+
+#define tlb_flush(tlb)                          flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+#include <asm/page.h>
+
+#define __pte_free_tlb(tlb,pte)                 pte_free(pte)
+
+#endif  /* _XTENSA_TLB_H */
diff --git a/include/asm-xtensa/tlbflush.h b/include/asm-xtensa/tlbflush.h
new file mode 100644
index 000000000000..43f6ec859af9
--- /dev/null
+++ b/include/asm-xtensa/tlbflush.h
@@ -0,0 +1,200 @@
+/*
+ * include/asm-xtensa/tlbflush.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TLBFLUSH_H
+#define _XTENSA_TLBFLUSH_H
+
+#define DEBUG_TLB
+
+#ifdef __KERNEL__
+
+#include <asm/processor.h>
+#include <linux/stringify.h>
+
+/* TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(mm, vmaddr) flushes a single page
+ *  - flush_tlb_range(mm, start, end) flushes a range of pages
+ */
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct*);
+extern void flush_tlb_page(struct vm_area_struct*,unsigned long);
+extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long);
+
+#define flush_tlb_kernel_range(start,end) flush_tlb_all()
+
+
+/* This is calld in munmap when we have freed up some page-table pages.
+ * We don't need to do anything here, there's nothing special about our
+ * page-table pages.
+ */
+
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
+                                      unsigned long start, unsigned long end)
+{
+}
+
+/* TLB operations. */
+
+#define ITLB_WAYS_LOG2      XCHAL_ITLB_WAY_BITS
+#define DTLB_WAYS_LOG2      XCHAL_DTLB_WAY_BITS
+#define ITLB_PROBE_SUCCESS  (1 << ITLB_WAYS_LOG2)
+#define DTLB_PROBE_SUCCESS  (1 << DTLB_WAYS_LOG2)
+
+static inline unsigned long itlb_probe(unsigned long addr)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("pitlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
+        return tmp;
+}
+
+static inline unsigned long dtlb_probe(unsigned long addr)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("pdtlb  %0, %1\n\t" : "=a" (tmp) : "a" (addr));
+        return tmp;
+}
+
+static inline void invalidate_itlb_entry (unsigned long probe)
+{
+        __asm__ __volatile__("iitlb  %0; isync\n\t" : : "a" (probe));
+}
+
+static inline void invalidate_dtlb_entry (unsigned long probe)
+{
+        __asm__ __volatile__("idtlb  %0; dsync\n\t" : : "a" (probe));
+}
+
+/* Use the .._no_isync functions with caution.  Generally, these are
+ * handy for bulk invalidates followed by a single 'isync'.  The
+ * caller must follow up with an 'isync', which can be relatively
+ * expensive on some Xtensa implementations.
+ */
+static inline void invalidate_itlb_entry_no_isync (unsigned entry)
+{
+        /* Caller must follow up with 'isync'. */
+        __asm__ __volatile__ ("iitlb  %0\n" : : "a" (entry) );
+}
+
+static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
+{
+        /* Caller must follow up with 'isync'. */
+        __asm__ __volatile__ ("idtlb  %0\n" : : "a" (entry) );
+}
+
+static inline void set_itlbcfg_register (unsigned long val)
+{
+        __asm__ __volatile__("wsr  %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t"
+                             : : "a" (val));
+}
+
+static inline void set_dtlbcfg_register (unsigned long val)
+{
+        __asm__ __volatile__("wsr  %0, "__stringify(DTLBCFG)"; dsync\n\t"
+                             : : "a" (val));
+}
+
+static inline void set_ptevaddr_register (unsigned long val)
+{
+        __asm__ __volatile__(" wsr  %0, "__stringify(PTEVADDR)"; isync\n"
+                             : : "a" (val));
+}
+
+static inline unsigned long read_ptevaddr_register (void)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("rsr  %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp));
+        return tmp;
+}
+
+static inline void write_dtlb_entry (pte_t entry, int way)
+{
+        __asm__ __volatile__("wdtlb  %1, %0; dsync\n\t"
+                             : : "r" (way), "r" (entry) );
+}
+
+static inline void write_itlb_entry (pte_t entry, int way)
+{
+        __asm__ __volatile__("witlb  %1, %0; isync\n\t"
+                             : : "r" (way), "r" (entry) );
+}
+
+static inline void invalidate_page_directory (void)
+{
+        invalidate_dtlb_entry (DTLB_WAY_PGTABLE);
+}
+
+static inline void invalidate_itlb_mapping (unsigned address)
+{
+        unsigned long tlb_entry;
+        while ((tlb_entry = itlb_probe (address)) & ITLB_PROBE_SUCCESS)
+                invalidate_itlb_entry (tlb_entry);
+}
+
+static inline void invalidate_dtlb_mapping (unsigned address)
+{
+        unsigned long tlb_entry;
+        while ((tlb_entry = dtlb_probe (address)) & DTLB_PROBE_SUCCESS)
+                invalidate_dtlb_entry (tlb_entry);
+}
+
+#define check_pgt_cache()       do { } while (0)
+
+
+#ifdef DEBUG_TLB
+
+/* DO NOT USE THESE FUNCTIONS.  These instructions aren't part of the Xtensa
+ * ISA and exist only for test purposes..
+ * You may find it helpful for MMU debugging, however.
+ *
+ * 'at' is the unmodified input register
+ * 'as' is the output register, as follows (specific to the Linux config):
+ *
+ *      as[31..12] contain the virtual address
+ *      as[11..08] are meaningless
+ *      as[07..00] contain the asid
+ */
+
+static inline unsigned long read_dtlb_virtual (int way)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("rdtlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
+        return tmp;
+}
+
+static inline unsigned long read_dtlb_translation (int way)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("rdtlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
+        return tmp;
+}
+
+static inline unsigned long read_itlb_virtual (int way)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("ritlb0  %0, %1\n\t" : "=a" (tmp), "+a" (way));
+        return tmp;
+}
+
+static inline unsigned long read_itlb_translation (int way)
+{
+        unsigned long tmp;
+        __asm__ __volatile__("ritlb1  %0, %1\n\t" : "=a" (tmp), "+a" (way));
+        return tmp;
+}
+
+#endif  /* DEBUG_TLB */
+
+
+#endif  /* __KERNEL__ */
+#endif  /* _XTENSA_PGALLOC_H */
diff --git a/include/asm-xtensa/topology.h b/include/asm-xtensa/topology.h
new file mode 100644
index 000000000000..7309e38a0ccb
--- /dev/null
+++ b/include/asm-xtensa/topology.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/topology.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TOPOLOGY_H
+#define _XTENSA_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif  /* _XTENSA_TOPOLOGY_H */
diff --git a/include/asm-xtensa/types.h b/include/asm-xtensa/types.h
new file mode 100644
index 000000000000..9d99a8e9e337
--- /dev/null
+++ b/include/asm-xtensa/types.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-xtensa/types.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TYPES_H
+#define _XTENSA_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#endif  /* __KERNEL__ */
+#endif
+
+#endif  /* _XTENSA_TYPES_H */
diff --git a/include/asm-xtensa/uaccess.h b/include/asm-xtensa/uaccess.h
new file mode 100644
index 000000000000..fc268ac923c0
--- /dev/null
+++ b/include/asm-xtensa/uaccess.h
@@ -0,0 +1,532 @@
+/*
+ * include/asm-xtensa/uaccess.h
+ *
+ * User space memory access functions
+ *
+ * These routines provide basic accessing functions to the user memory
+ * space for the kernel. This header file provides fuctions such as:
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_UACCESS_H
+#define _XTENSA_UACCESS_H
+
+#include <linux/errno.h>
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+#ifdef __ASSEMBLY__
+
+#define _ASMLANGUAGE
+#include <asm/current.h>
+#include <asm/offsets.h>
+#include <asm/processor.h>
+
+/*
+ * These assembly macros mirror the C macros that follow below.  They
+ * should always have identical functionality.  See
+ * arch/xtensa/kernel/sys.S for usage.
+ */
+
+#define KERNEL_DS       0
+#define USER_DS         1
+
+#define get_ds          (KERNEL_DS)
+
+/*
+ * get_fs reads current->thread.current_ds into a register.
+ * On Entry:
+ *      <ad>    anything
+ *      <sp>    stack
+ * On Exit:
+ *      <ad>    contains current->thread.current_ds
+ */
+        .macro  get_fs  ad, sp
+        GET_CURRENT(\ad,\sp)
+        l32i    \ad, \ad, THREAD_CURRENT_DS
+        .endm
+
+/*
+ * set_fs sets current->thread.current_ds to some value.
+ * On Entry:
+ *      <at>    anything (temp register)
+ *      <av>    value to write
+ *      <sp>    stack
+ * On Exit:
+ *      <at>    destroyed (actually, current)
+ *      <av>    preserved, value to write
+ */
+        .macro  set_fs  at, av, sp
+        GET_CURRENT(\at,\sp)
+        s32i    \av, \at, THREAD_CURRENT_DS
+        .endm
+
+/*
+ * kernel_ok determines whether we should bypass addr/size checking.
+ * See the equivalent C-macro version below for clarity.
+ * On success, kernel_ok branches to a label indicated by parameter
+ * <success>.  This implies that the macro falls through to the next
+ * insruction on an error.
+ *
+ * Note that while this macro can be used independently, we designed
+ * in for optimal use in the access_ok macro below (i.e., we fall
+ * through on error).
+ *
+ * On Entry:
+ *      <at>            anything (temp register)
+ *      <success>       label to branch to on success; implies
+ *                      fall-through macro on error
+ *      <sp>            stack pointer
+ * On Exit:
+ *      <at>            destroyed (actually, current->thread.current_ds)
+ */
+
+#if ((KERNEL_DS != 0) || (USER_DS == 0))
+# error Assembly macro kernel_ok fails
+#endif
+        .macro  kernel_ok  at, sp, success
+        get_fs  \at, \sp
+        beqz    \at, \success
+        .endm
+
+/*
+ * user_ok determines whether the access to user-space memory is allowed.
+ * See the equivalent C-macro version below for clarity.
+ *
+ * On error, user_ok branches to a label indicated by parameter
+ * <error>.  This implies that the macro falls through to the next
+ * instruction on success.
+ *
+ * Note that while this macro can be used independently, we designed
+ * in for optimal use in the access_ok macro below (i.e., we fall
+ * through on success).
+ *
+ * On Entry:
+ *      <aa>    register containing memory address
+ *      <as>    register containing memory size
+ *      <at>    temp register
+ *      <error> label to branch to on error; implies fall-through
+ *              macro on success
+ * On Exit:
+ *      <aa>    preserved
+ *      <as>    preserved
+ *      <at>    destroyed (actually, (TASK_SIZE + 1 - size))
+ */
+        .macro  user_ok aa, as, at, error
+        movi    \at, (TASK_SIZE+1)
+        bgeu    \as, \at, \error
+        sub     \at, \at, \as
+        bgeu    \aa, \at, \error
+        .endm
+
+/*
+ * access_ok determines whether a memory access is allowed.  See the
+ * equivalent C-macro version below for clarity.
+ *
+ * On error, access_ok branches to a label indicated by parameter
+ * <error>.  This implies that the macro falls through to the next
+ * instruction on success.
+ *
+ * Note that we assume success is the common case, and we optimize the
+ * branch fall-through case on success.
+ *
+ * On Entry:
+ *      <aa>    register containing memory address
+ *      <as>    register containing memory size
+ *      <at>    temp register
+ *      <sp>
+ *      <error> label to branch to on error; implies fall-through
+ *              macro on success
+ * On Exit:
+ *      <aa>    preserved
+ *      <as>    preserved
+ *      <at>    destroyed
+ */
+        .macro  access_ok  aa, as, at, sp, error
+        kernel_ok  \at, \sp, .Laccess_ok_\@
+        user_ok    \aa, \as, \at, \error
+.Laccess_ok_\@:
+        .endm
+
+/*
+ * verify_area determines whether a memory access is allowed.  It's
+ * mostly an unnecessary wrapper for access_ok, but we provide it as a
+ * duplicate of the verify_area() C inline function below.  See the
+ * equivalent C version below for clarity.
+ *
+ * On error, verify_area branches to a label indicated by parameter
+ * <error>.  This implies that the macro falls through to the next
+ * instruction on success.
+ *
+ * Note that we assume success is the common case, and we optimize the
+ * branch fall-through case on success.
+ *
+ * On Entry:
+ *      <aa>    register containing memory address
+ *      <as>    register containing memory size
+ *      <at>    temp register
+ *      <error> label to branch to on error; implies fall-through
+ *              macro on success
+ * On Exit:
+ *      <aa>    preserved
+ *      <as>    preserved
+ *      <at>    destroyed
+ */
+        .macro  verify_area     aa, as, at, sp, error
+        access_ok  \at, \aa, \as, \sp, \error
+        .endm
+
+
+#else /* __ASSEMBLY__ not defined */
+
+#include <linux/sched.h>
+#include <asm/types.h>
+
+/*
+ * The fs value determines whether argument validity checking should
+ * be performed or not.  If get_fs() == USER_DS, checking is
+ * performed, with get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons (Data Segment Register?), these macros are
+ * grossly misnamed.
+ */
+
+#define KERNEL_DS       ((mm_segment_t) { 0 })
+#define USER_DS         ((mm_segment_t) { 1 })
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.current_ds)
+#define set_fs(val)     (current->thread.current_ds = (val))
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
+#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size)))
+#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
+#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
+
+static inline int verify_area(int type, const void * addr, unsigned long size)
+{
+        return access_ok(type,addr,size) ? 0 : -EFAULT;
+}
+
+/*
+ * These are the main single-value transfer routines.  They
+ * automatically use the right size if we just have the right pointer
+ * type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in
+ * "get_user()" and yet we don't want to do any pointers, because that
+ * is too much of a performance impact. Thus we have a few rather ugly
+ * macros here, and hide all the uglyness from the user.
+ *
+ * Careful to not
+ * (a) re-use the arguments for side effects (sizeof is ok)
+ * (b) require any knowledge of processes at this stage
+ */
+#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr)))
+#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ */
+#define __put_user(x,ptr) __put_user_nocheck((x),(ptr),sizeof(*(ptr)))
+#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
+
+
+extern long __put_user_bad(void);
+
+#define __put_user_nocheck(x,ptr,size)                  \
+({                                                      \
+        long __pu_err;                                  \
+        __put_user_size((x),(ptr),(size),__pu_err);     \
+        __pu_err;                                       \
+})
+
+#define __put_user_check(x,ptr,size)                            \
+({                                                              \
+        long __pu_err = -EFAULT;                                \
+        __typeof__(*(ptr)) *__pu_addr = (ptr);                  \
+        if (access_ok(VERIFY_WRITE,__pu_addr,size))             \
+                __put_user_size((x),__pu_addr,(size),__pu_err); \
+        __pu_err;                                               \
+})
+
+#define __put_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1: __put_user_asm(x,ptr,retval,1,"s8i");  break;   \
+        case 2: __put_user_asm(x,ptr,retval,2,"s16i"); break;   \
+        case 4: __put_user_asm(x,ptr,retval,4,"s32i"); break;   \
+        case 8: {                                               \
+                     __typeof__(*ptr) __v64 = x;                \
+                     retval = __copy_to_user(ptr,&__v64,8);     \
+                     break;                                     \
+                }                                               \
+        default: __put_user_bad();                              \
+        }                                                       \
+} while (0)
+
+
+/*
+ * Consider a case of a user single load/store would cause both an
+ * unaligned exception and an MMU-related exception (unaligned
+ * exceptions happen first):
+ *
+ * User code passes a bad variable ptr to a system call.
+ * Kernel tries to access the variable.
+ * Unaligned exception occurs.
+ * Unaligned exception handler tries to make aligned accesses.
+ * Double exception occurs for MMU-related cause (e.g., page not mapped).
+ * do_page_fault() thinks the fault address belongs to the kernel, not the
+ * user, and panics.
+ *
+ * The kernel currently prohibits user unaligned accesses.  We use the
+ * __check_align_* macros to check for unaligned addresses before
+ * accessing user space so we don't crash the kernel.  Both
+ * __put_user_asm and __get_user_asm use these alignment macros, so
+ * macro-specific labels such as 0f, 1f, %0, %2, and %3 must stay in
+ * sync.
+ */
+
+#define __check_align_1  ""
+
+#define __check_align_2                         \
+        "   _bbci.l %2,  0, 1f          \n"     \
+        "   movi    %0, %3              \n"     \
+        "   _j      2f                  \n"
+
+#define __check_align_4                         \
+        "   _bbsi.l %2,  0, 0f          \n"     \
+        "   _bbci.l %2,  1, 1f          \n"     \
+        "0: movi    %0, %3              \n"     \
+        "   _j      2f                  \n"
+
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ *
+ * WARNING: If you modify this macro at all, verify that the
+ * __check_align_* macros still work.
+ */
+#define __put_user_asm(x, addr, err, align, insn) \
+   __asm__ __volatile__(                        \
+        __check_align_##align                   \
+        "1: "insn"  %1, %2, 0           \n"     \
+        "2:                             \n"     \
+        "   .section  .fixup,\"ax\"     \n"     \
+        "   .align 4                    \n"     \
+        "4:                             \n"     \
+        "   .long  2b                   \n"     \
+        "5:                             \n"     \
+        "   l32r   %2, 4b               \n"     \
+        "   movi   %0, %3               \n"     \
+        "   jx     %2                   \n"     \
+        "   .previous                   \n"     \
+        "   .section  __ex_table,\"a\"  \n"     \
+        "   .long       1b, 5b          \n"     \
+        "   .previous"                          \
+        :"=r" (err)                             \
+        :"r" ((int)(x)), "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __get_user_nocheck(x,ptr,size)                          \
+({                                                              \
+        long __gu_err, __gu_val;                                \
+        __get_user_size(__gu_val,(ptr),(size),__gu_err);        \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#define __get_user_check(x,ptr,size)                                    \
+({                                                                      \
+        long __gu_err = -EFAULT, __gu_val = 0;                          \
+        const __typeof__(*(ptr)) *__gu_addr = (ptr);                    \
+        if (access_ok(VERIFY_READ,__gu_addr,size))                      \
+                __get_user_size(__gu_val,__gu_addr,(size),__gu_err);    \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+
+extern long __get_user_bad(void);
+
+#define __get_user_size(x,ptr,size,retval)                              \
+do {                                                                    \
+        retval = 0;                                                     \
+        switch (size) {                                                 \
+          case 1: __get_user_asm(x,ptr,retval,1,"l8ui");  break;        \
+          case 2: __get_user_asm(x,ptr,retval,2,"l16ui"); break;        \
+          case 4: __get_user_asm(x,ptr,retval,4,"l32i");  break;        \
+          case 8: retval = __copy_from_user(&x,ptr,8);    break;        \
+          default: (x) = __get_user_bad();                              \
+        }                                                               \
+} while (0)
+
+
+/*
+ * WARNING: If you modify this macro at all, verify that the
+ * __check_align_* macros still work.
+ */
+#define __get_user_asm(x, addr, err, align, insn) \
+   __asm__ __volatile__(                        \
+        __check_align_##align                   \
+        "1: "insn"  %1, %2, 0           \n"     \
+        "2:                             \n"     \
+        "   .section  .fixup,\"ax\"     \n"     \
+        "   .align 4                    \n"     \
+        "4:                             \n"     \
+        "   .long  2b                   \n"     \
+        "5:                             \n"     \
+        "   l32r   %2, 4b               \n"     \
+        "   movi   %1, 0                \n"     \
+        "   movi   %0, %3               \n"     \
+        "   jx     %2                   \n"     \
+        "   .previous                   \n"     \
+        "   .section  __ex_table,\"a\"  \n"     \
+        "   .long       1b, 5b          \n"     \
+        "   .previous"                          \
+        :"=r" (err), "=r" (x)                   \
+        :"r" (addr), "i" (-EFAULT), "0" (err))
+
+
+/*
+ * Copy to/from user space
+ */
+
+/*
+ * We use a generic, arbitrary-sized copy subroutine.  The Xtensa
+ * architecture would cause heavy code bloat if we tried to inline
+ * these functions and provide __constant_copy_* equivalents like the
+ * i386 versions.  __xtensa_copy_user is quite efficient.  See the
+ * .fixup section of __xtensa_copy_user for a discussion on the
+ * X_zeroing equivalents for Xtensa.
+ */
+
+extern unsigned __xtensa_copy_user(void *to, const void *from, unsigned n);
+#define __copy_user(to,from,size) __xtensa_copy_user(to,from,size)
+
+
+static inline unsigned long
+__generic_copy_from_user_nocheck(void *to, const void *from, unsigned long n)
+{
+        return __copy_user(to,from,n);
+}
+
+static inline unsigned long
+__generic_copy_to_user_nocheck(void *to, const void *from, unsigned long n)
+{
+        return __copy_user(to,from,n);
+}
+
+static inline unsigned long
+__generic_copy_to_user(void *to, const void *from, unsigned long n)
+{
+        prefetch(from);
+        if (access_ok(VERIFY_WRITE, to, n))
+                return __copy_user(to,from,n);
+        return n;
+}
+
+static inline unsigned long
+__generic_copy_from_user(void *to, const void *from, unsigned long n)
+{
+        prefetchw(to);
+        if (access_ok(VERIFY_READ, from, n))
+                return __copy_user(to,from,n);
+        else
+                memset(to, 0, n);
+        return n;
+}
+
+#define copy_to_user(to,from,n) __generic_copy_to_user((to),(from),(n))
+#define copy_from_user(to,from,n) __generic_copy_from_user((to),(from),(n))
+#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n))
+#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n))
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+
+/*
+ * We need to return the number of bytes not cleared.  Our memset()
+ * returns zero if a problem occurs while accessing user-space memory.
+ * In that event, return no memory cleared.  Otherwise, zero for
+ * success.
+ */
+
+static inline unsigned long
+__xtensa_clear_user(void *addr, unsigned long size)
+{
+        if ( ! memset(addr, 0, size) )
+                return size;
+        return 0;
+}
+
+static inline unsigned long
+clear_user(void *addr, unsigned long size)
+{
+        if (access_ok(VERIFY_WRITE, addr, size))
+                return __xtensa_clear_user(addr, size);
+        return size ? -EFAULT : 0;
+}
+
+#define __clear_user  __xtensa_clear_user
+
+
+extern long __strncpy_user(char *, const char *, long);
+#define __strncpy_from_user __strncpy_user
+
+static inline long
+strncpy_from_user(char *dst, const char *src, long count)
+{
+        if (access_ok(VERIFY_READ, src, 1))
+                return __strncpy_from_user(dst, src, count);
+        return -EFAULT;
+}
+
+
+#define strlen_user(str) strnlen_user((str), TASK_SIZE - 1)
+
+/*
+ * Return the size of a string (including the ending 0!)
+ */
+extern long __strnlen_user(const char *, long);
+
+static inline long strnlen_user(const char *str, long len)
+{
+        unsigned long top = __kernel_ok ? ~0UL : TASK_SIZE - 1;
+
+        if ((unsigned long)str > top)
+                return 0;
+        return __strnlen_user(str, len);
+}
+
+
+struct exception_table_entry
+{
+        unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup.unit otherwise.  */
+
+extern unsigned long search_exception_table(unsigned long addr);
+extern void sort_exception_table(void);
+
+/* Returns the new pc */
+#define fixup_exception(map_reg, fixup_unit, pc)                \
+({                                                              \
+        fixup_unit;                                             \
+})
+
+#endif  /* __ASSEMBLY__ */
+#endif  /* _XTENSA_UACCESS_H */
diff --git a/include/asm-xtensa/ucontext.h b/include/asm-xtensa/ucontext.h
new file mode 100644
index 000000000000..94c94ed3e00a
--- /dev/null
+++ b/include/asm-xtensa/ucontext.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-xtensa/ucontext.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_UCONTEXT_H
+#define _XTENSA_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* _XTENSA_UCONTEXT_H */
diff --git a/include/asm-xtensa/unaligned.h b/include/asm-xtensa/unaligned.h
new file mode 100644
index 000000000000..28220890d0a6
--- /dev/null
+++ b/include/asm-xtensa/unaligned.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-xtensa/unaligned.h
+ *
+ * Xtensa doesn't handle unaligned accesses efficiently.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_UNALIGNED_H
+#define _XTENSA_UNALIGNED_H
+
+#include <linux/string.h>
+
+/* Use memmove here, so gcc does not insert a __builtin_memcpy. */
+
+#define get_unaligned(ptr) \
+  ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; })
+
+#define put_unaligned(val, ptr)                         \
+  ({ __typeof__(*(ptr)) __tmp = (val);                  \
+     memmove((ptr), &__tmp, sizeof(*(ptr)));            \
+     (void)0; })
+
+#endif  /* _XTENSA_UNALIGNED_H */
diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h
new file mode 100644
index 000000000000..6b39d6609d9c
--- /dev/null
+++ b/include/asm-xtensa/unistd.h
@@ -0,0 +1,439 @@
+/*
+ * include/asm-xtensa/unistd.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_UNISTD_H
+#define _XTENSA_UNISTD_H
+
+#include <linux/linkage.h>
+
+#define __NR_spill                0
+#define __NR_exit                 1
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_ptrace              26
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_cacheflush         147
+#define __NR_cachectl           148
+#define __NR_sysxtensa          149
+#define __NR_sysdummy           150
+#define __NR_getsid             151
+#define __NR_fdatasync          152
+#define __NR__sysctl            153
+#define __NR_mlock              154
+#define __NR_munlock            155
+#define __NR_mlockall           156
+#define __NR_munlockall         157
+#define __NR_sched_setparam             158
+#define __NR_sched_getparam             159
+#define __NR_sched_setscheduler         160
+#define __NR_sched_getscheduler         161
+#define __NR_sched_yield                162
+#define __NR_sched_get_priority_max     163
+#define __NR_sched_get_priority_min     164
+#define __NR_sched_rr_get_interval      165
+#define __NR_nanosleep          166
+#define __NR_mremap             167
+#define __NR_accept             168
+#define __NR_bind               169
+#define __NR_connect            170
+#define __NR_getpeername        171
+#define __NR_getsockname        172
+#define __NR_getsockopt         173
+#define __NR_listen             174
+#define __NR_recv               175
+#define __NR_recvfrom           176
+#define __NR_recvmsg            177
+#define __NR_send               178
+#define __NR_sendmsg            179
+#define __NR_sendto             180
+#define __NR_setsockopt         181
+#define __NR_shutdown           182
+#define __NR_socket             183
+#define __NR_socketpair         184
+#define __NR_setresuid          185
+#define __NR_getresuid          186
+#define __NR_query_module       187
+#define __NR_poll               188
+#define __NR_nfsservctl         189
+#define __NR_setresgid          190
+#define __NR_getresgid          191
+#define __NR_prctl              192
+#define __NR_rt_sigreturn       193
+#define __NR_rt_sigaction       194
+#define __NR_rt_sigprocmask     195
+#define __NR_rt_sigpending      196
+#define __NR_rt_sigtimedwait    197
+#define __NR_rt_sigqueueinfo    198
+#define __NR_rt_sigsuspend      199
+#define __NR_pread              200
+#define __NR_pwrite             201
+#define __NR_chown              202
+#define __NR_getcwd             203
+#define __NR_capget             204
+#define __NR_capset             205
+#define __NR_sigaltstack        206
+#define __NR_sendfile           207
+#define __NR_mmap2              210
+#define __NR_truncate64         211
+#define __NR_ftruncate64        212
+#define __NR_stat64             213
+#define __NR_lstat64            214
+#define __NR_fstat64            215
+#define __NR_pivot_root         216
+#define __NR_mincore            217
+#define __NR_madvise            218
+#define __NR_getdents64         219
+
+/* Keep this last; should always equal the last valid call number. */
+#define __NR_Linux_syscalls     220
+
+/* user-visible error numbers are in the range -1 - -125: see
+ * <asm-xtensa/errno.h> */
+
+#define SYSXTENSA_RESERVED         0    /* don't use this */
+#define SYSXTENSA_ATOMIC_SET       1    /* set variable */
+#define SYSXTENSA_ATOMIC_EXG_ADD   2    /* exchange memory and add */
+#define SYSXTENSA_ATOMIC_ADD       3    /* add to memory */
+#define SYSXTENSA_ATOMIC_CMP_SWP   4    /* compare and swap */
+
+#define SYSXTENSA_COUNT            5    /* count of syscall0 functions*/
+
+#ifdef __KERNEL__
+#define __syscall_return(type, res) return ((type)(res))
+#else
+#define __syscall_return(type, res) \
+do { \
+        if ((unsigned long)(res) >= (unsigned long)(-125)) { \
+        /* Avoid using "res" which is declared to be in register r2; \
+         * errno might expand to a function call and clobber it.  */ \
+                int __err = -(res); \
+                errno = __err; \
+                res = -1; \
+        } \
+        return (type) (res); \
+} while (0)
+#endif
+
+
+/* Tensilica's xt-xcc compiler is much more agressive at code
+ * optimization than gcc.  Multiple __asm__ statements are
+ * insufficient for xt-xcc because subsequent optimization passes
+ * (beyond the front-end that knows of __asm__ statements and other
+ * such GNU Extensions to C) can modify the register selection for
+ * containment of C variables.
+ *
+ * xt-xcc cannot modify the contents of a single __asm__ statement, so
+ * we create single-asm versions of the syscall macros that are
+ * suitable and optimal for both xt-xcc and gcc.
+ *
+ * Linux takes system-call arguments in registers.  The following
+ * design is optimized for user-land apps (e.g., glibc) which
+ * typically have a function wrapper around the "syscall" assembly
+ * instruction.  It satisfies the Xtensa ABI while minizing argument
+ * shifting.
+ *
+ * The Xtensa ABI and software conventions require the system-call
+ * number in a2.  If an argument exists in a2, we move it to the next
+ * available register.  Note that for improved efficiency, we do NOT
+ * shift all parameters down one register to maintain the original
+ * order.
+ *
+ * At best case (zero arguments), we just write the syscall number to
+ * a2.  At worst case (1 to 6 arguments), we move the argument in a2
+ * to the next available register, then write the syscall number to
+ * a2.
+ *
+ * For clarity, the following truth table enumerates all possibilities.
+ *
+ * arguments    syscall number  arg0, arg1, arg2, arg3, arg4, arg5
+ * ---------    --------------  ----------------------------------
+ *      0             a2
+ *      1             a2        a3
+ *      2             a2        a4,   a3
+ *      3             a2        a5,   a3,   a4
+ *      4             a2        a6,   a3,   a4,   a5
+ *      5             a2        a7,   a3,   a4,   a5,   a6
+ *      6             a2        a8,   a3,   a4,   a5,   a6,   a7
+ */
+
+#define _syscall0(type,name) \
+type name(void) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name) \
+        : "a2" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall1(type,name,type0,arg0) \
+type name(type0 arg0) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a3, %2 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0) \
+        : "a2", "a3" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall2(type,name,type0,arg0,type1,arg1) \
+type name(type0 arg0,type1 arg1) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a4, %2 \n" \
+        "  mov   a3, %3 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0), "a" (arg1) \
+        : "a2", "a3", "a4" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall3(type,name,type0,arg0,type1,arg1,type2,arg2) \
+type name(type0 arg0,type1 arg1,type2 arg2) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a5, %2 \n" \
+        "  mov   a4, %4 \n" \
+        "  mov   a3, %3 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0), "a" (arg1), "a" (arg2) \
+        : "a2", "a3", "a4", "a5" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+#define _syscall4(type,name,type0,arg0,type1,arg1,type2,arg2,type3,arg3) \
+type name(type0 arg0,type1 arg1,type2 arg2,type3 arg3) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a6, %2 \n" \
+        "  mov   a5, %5 \n" \
+        "  mov   a4, %4 \n" \
+        "  mov   a3, %3 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0), "a" (arg1), "a" (arg2), "a" (arg3) \
+        : "a2", "a3", "a4", "a5", "a6" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+/* Note that we save and restore the a7 frame pointer.
+ * Including a7 in the clobber list doesn't do what you'd expect.
+ */
+#define _syscall5(type,name,type0,arg0,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name(type0 arg0,type1 arg1,type2 arg2,type3 arg3,type4 arg4) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a9, a7 \n" \
+        "  mov   a7, %2 \n" \
+        "  mov   a6, %6 \n" \
+        "  mov   a5, %5 \n" \
+        "  mov   a4, %4 \n" \
+        "  mov   a3, %3 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   a7, a9 \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0), "a" (arg1), "a" (arg2), \
+                             "a" (arg3), "a" (arg4) \
+        : "a2", "a3", "a4", "a5", "a6", "a9" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+/* Note that we save and restore the a7 frame pointer.
+ * Including a7 in the clobber list doesn't do what you'd expect.
+ */
+#define _syscall6(type,name,type0,arg0,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
+type name(type0 arg0,type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
+{ \
+long __res; \
+__asm__ __volatile__ ( \
+        "  mov   a9, a7 \n" \
+        "  mov   a8, %2 \n" \
+        "  mov   a7, %7 \n" \
+        "  mov   a6, %6 \n" \
+        "  mov   a5, %5 \n" \
+        "  mov   a4, %4 \n" \
+        "  mov   a3, %3 \n" \
+        "  movi  a2, %1 \n" \
+        "  syscall      \n" \
+        "  mov   a7, a9 \n" \
+        "  mov   %0, a2 \n" \
+        : "=a" (__res) \
+        : "i" (__NR_##name), "a" (arg0), "a" (arg1), "a" (arg2), \
+                             "a" (arg3), "a" (arg4), "a" (arg5)  \
+        : "a2", "a3", "a4", "a5", "a6", "a8", "a9" \
+        ); \
+__syscall_return(type,__res); \
+}
+
+
+#ifdef __KERNEL_SYSCALLS__
+static __inline__ _syscall3(int,execve,const char*,file,char**,argv,char**,envp)
+#endif
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#endif
+
+#endif  /* _XTENSA_UNISTD_H */
diff --git a/include/asm-xtensa/user.h b/include/asm-xtensa/user.h
new file mode 100644
index 000000000000..2c3ed23354a8
--- /dev/null
+++ b/include/asm-xtensa/user.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-xtensa/user.h
+ *
+ * Xtensa Processor version.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_USER_H
+#define _XTENSA_USER_H
+
+/* This file usually defines a 'struct user' structure. However, it it only
+ * used for a.out file, which are not supported on Xtensa.
+ */
+
+#endif  /* _XTENSA_USER_H */
diff --git a/include/asm-xtensa/vga.h b/include/asm-xtensa/vga.h
new file mode 100644
index 000000000000..23d82f6acb57
--- /dev/null
+++ b/include/asm-xtensa/vga.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm-xtensa/vga.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_VGA_H
+#define _XTENSA_VGA_H
+
+#define VGA_MAP_MEM(x) (unsigned long)phys_to_virt(x)
+
+#define vga_readb(x)    (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif
diff --git a/include/asm-xtensa/xor.h b/include/asm-xtensa/xor.h
new file mode 100644
index 000000000000..e7b1f083991d
--- /dev/null
+++ b/include/asm-xtensa/xor.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-xtensa/xor.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2005 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_XOR_H
+#define _XTENSA_XOR_H
+
+#include <asm-generic/xor.h>
+
+#endif
diff --git a/include/asm-xtensa/xtensa/cacheasm.h b/include/asm-xtensa/xtensa/cacheasm.h
new file mode 100644
index 000000000000..0cdbb0bf180e
--- /dev/null
+++ b/include/asm-xtensa/xtensa/cacheasm.h
@@ -0,0 +1,708 @@
+#ifndef XTENSA_CACHEASM_H
+#define XTENSA_CACHEASM_H
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/cacheasm.h -- assembler-specific cache
+ * related definitions that depend on CORE configuration.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/coreasm.h>
+
+
+/*
+ *  This header file defines assembler macros of the form:
+ *      <x>cache_<func>
+ *  where <x> is 'i' or 'd' for instruction and data caches,
+ *  and <func> indicates the function of the macro.
+ *
+ *  The following functions <func> are defined,
+ *  and apply only to the specified cache (I or D):
+ *
+ *  reset
+ *      Resets the cache.
+ *
+ *  sync
+ *      Makes sure any previous cache instructions have been completed;
+ *      ie. makes sure any previous cache control operations
+ *      have had full effect and been synchronized to memory.
+ *      Eg. any invalidate completed [so as not to generate a hit],
+ *      any writebacks or other pipelined writes written to memory, etc.
+ *
+ *  invalidate_line             (single cache line)
+ *  invalidate_region           (specified memory range)
+ *  invalidate_all              (entire cache)
+ *      Invalidates all cache entries that cache
+ *      data from the specified memory range.
+ *      NOTE: locked entries are not invalidated.
+ *
+ *  writeback_line              (single cache line)
+ *  writeback_region            (specified memory range)
+ *  writeback_all               (entire cache)
+ *      Writes back to memory all dirty cache entries
+ *      that cache data from the specified memory range,
+ *      and marks these entries as clean.
+ *      NOTE: on some future implementations, this might
+ *              also invalidate.
+ *      NOTE: locked entries are written back, but never invalidated.
+ *      NOTE: instruction caches never implement writeback.
+ *
+ *  writeback_inv_line          (single cache line)
+ *  writeback_inv_region        (specified memory range)
+ *  writeback_inv_all           (entire cache)
+ *      Writes back to memory all dirty cache entries
+ *      that cache data from the specified memory range,
+ *      and invalidates these entries (including all clean
+ *      cache entries that cache data from that range).
+ *      NOTE: locked entries are written back but not invalidated.
+ *      NOTE: instruction caches never implement writeback.
+ *
+ *  lock_line                   (single cache line)
+ *  lock_region                 (specified memory range)
+ *      Prefetch and lock the specified memory range into cache.
+ *      NOTE:  if any part of the specified memory range cannot
+ *      be locked, a ??? exception occurs.  These macros don't
+ *      do anything special (yet anyway) to handle this situation.
+ *
+ *  unlock_line                 (single cache line)
+ *  unlock_region               (specified memory range)
+ *  unlock_all                  (entire cache)
+ *      Unlock cache entries that cache the specified memory range.
+ *      Entries not already locked are unaffected.
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+
+/*
+ *  The following macros assume the following cache size/parameter limits
+ *  in the current Xtensa core implementation:
+ *      cache size:     1024 bytes minimum
+ *      line size:      16 - 64 bytes
+ *      way count:      1 - 4
+ *
+ *  Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
+ *  Hence the assumption that each loop can execute four cache instructions.
+ *
+ *  Correspondingly, the offset range of instructions is assumed able to cover
+ *  four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
+ *  both hit and indexed cache instructions.  Ie. these offsets are all
+ *  valid:  0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
+ *  This is true of all original cache instructions
+ *  (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
+ *  of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
+ *  This is also true of subsequent cache instructions
+ *  (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
+ *  of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
+ *
+ *  (Maximum cache size, currently 32k, doesn't affect the following macros.
+ *  Cache ways > MMU min page size cause aliasing but that's another matter.)
+ */
+
+
+
+/*
+ *  Macro to apply an 'indexed' cache instruction to the entire cache.
+ *
+ *  Parameters:
+ *      cainst          instruction/ that takes an address register parameter
+ *                      and an offset parameter (in range 0 .. 3*linesize).
+ *      size            size of cache in bytes
+ *      linesize        size of cache line in bytes
+ *      assoc_or1       number of associativities (ways/sets) in cache
+ *                      if all sets affected by cainst,
+ *                      or 1 if only one set (or not all sets) of the cache
+ *                      is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
+ *      aa, ab          unique address registers (temporaries)
+ */
+
+        .macro  cache_index_all         cainst, size, linesize, assoc_or1, aa, ab
+
+        //  Sanity-check on cache parameters:
+        .ifne   (\size % (\linesize * \assoc_or1 * 4))
+        .err    //  cache configuration outside expected/supported range!
+        .endif
+
+        //  \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
+        movi    \aa, (\size / (\linesize * \assoc_or1 * 4))
+        // Possible improvement: need only loop if \aa > 1 ;
+        // however that particular condition is highly unlikely.
+        movi    \ab, 0          // to iterate over cache
+        floop           \aa, cachex\@
+        \cainst         \ab, 0*\linesize
+        \cainst         \ab, 1*\linesize
+        \cainst         \ab, 2*\linesize
+        \cainst         \ab, 3*\linesize
+        addi            \ab, \ab, 4*\linesize   // move to next line
+        floopend        \aa, cachex\@
+
+        .endm
+
+
+/*
+ *  Macro to apply a 'hit' cache instruction to a memory region,
+ *  ie. to any cache entries that cache a specified portion (region) of memory.
+ *  Takes care of the unaligned cases, ie. may apply to one
+ *  more cache line than $asize / lineSize if $aaddr is not aligned.
+ *
+ *
+ *  Parameters are:
+ *      cainst  instruction/macro that takes an address register parameter
+ *              and an offset parameter (currently always zero)
+ *              and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
+ *      linesize_log2   log2(size of cache line in bytes)
+ *      addr    register containing start address of region (clobbered)
+ *      asize   register containing size of the region in bytes (clobbered)
+ *      askew   unique register used as temporary
+ *
+ * !?!?! 2DO: optimization: iterate max(cache_size and \asize) / linesize
+ */
+
+        .macro  cache_hit_region        cainst, linesize_log2, addr, asize, askew
+
+        //  Make \asize the number of iterations:
+        extui   \askew, \addr, 0, \linesize_log2        // get unalignment amount of \addr
+        add     \asize, \asize, \askew                  // ... and add it to \asize
+        addi    \asize, \asize, (1 << \linesize_log2) - 1       // round up!
+        srli    \asize, \asize, \linesize_log2
+
+        //  Iterate over region:
+        floopnez        \asize, cacheh\@
+        \cainst         \addr, 0
+        addi            \addr, \addr, (1 << \linesize_log2)     // move to next line
+        floopend        \asize, cacheh\@
+
+        .endm
+
+
+
+
+
+/***************************   INSTRUCTION CACHE   ***************************/
+
+
+/*
+ *  Reset/initialize the instruction cache by simply invalidating it:
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  icache_reset    aa, ab
+        icache_unlock_all       \aa, \ab
+        icache_invalidate_all   \aa, \ab
+        .endm
+
+
+/*
+ * Synchronize after an instruction cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous instruction cache control operations.
+ *
+ * Parameters are:
+ *      ar      an address register (temporary) (currently unused, but may be used in future)
+ */
+        .macro  icache_sync     ar
+#if XCHAL_ICACHE_SIZE > 0
+        isync
+#endif
+        .endm
+
+
+
+/*
+ *  Invalidate a single line of the instruction cache.
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to invalidate
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  (optional) offset to add to \ar to compute effective address to invalidate
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  icache_invalidate_line  ar, offset
+#if XCHAL_ICACHE_SIZE > 0
+        ihi     \ar, \offset            // invalidate icache line
+        /*
+         *  NOTE:  in some version of the silicon [!!!SHOULD HAVE BEEN DOCUMENTED!!!]
+         *  'ihi' doesn't work, so it had been replaced with 'iii'
+         *  (which would just invalidate more than it should,
+         *  which should be okay other than the performance hit
+         *  because cache locking did not exist in that version,
+         *  unless user somehow relies on something being cached).
+         *  [WHAT VERSION IS IT!!?!?
+         *  IS THERE ANY WAY TO TEST FOR THAT HERE, TO OUTPUT 'III' ONLY IF NEEDED!?!?].
+         *
+         *      iii     \ar, \offset
+         */
+        icache_sync     \ar
+#endif
+        .endm
+
+
+
+
+/*
+ *  Invalidate instruction  cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  icache_invalidate_region        astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0
+        //  Instruction cache region invalidation:
+        cache_hit_region        ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+        icache_sync     \ac
+        //  End of instruction cache region invalidation
+#endif
+        .endm
+
+
+
+/*
+ *  Invalidate entire instruction cache.
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  icache_invalidate_all   aa, ab
+#if XCHAL_ICACHE_SIZE > 0
+        //  Instruction cache invalidation:
+        cache_index_all         iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab
+        icache_sync     \aa
+        //  End of instruction cache invalidation
+#endif
+        .endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to lock
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to lock
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  icache_lock_line        ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+        ipfl    \ar, \offset    /* prefetch and lock icache line */
+        icache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the instruction cache.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  icache_lock_region      astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+        //  Instruction cache region lock:
+        cache_hit_region        ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+        icache_sync     \ac
+        //  End of instruction cache region lock
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to unlock
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to unlock
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  icache_unlock_line      ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+        ihu     \ar, \offset    /* unlock icache line */
+        icache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the instruction cache.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  icache_unlock_region    astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+        //  Instruction cache region unlock:
+        cache_hit_region        ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+        icache_sync     \ac
+        //  End of instruction cache region unlock
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock entire instruction cache.
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  icache_unlock_all       aa, ab
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+        //  Instruction cache unlock:
+        cache_index_all         iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab
+        icache_sync     \aa
+        //  End of instruction cache unlock
+#endif
+        .endm
+
+
+
+
+
+/***************************   DATA CACHE   ***************************/
+
+
+
+/*
+ *  Reset/initialize the data cache by simply invalidating it
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  dcache_reset    aa, ab
+        dcache_unlock_all       \aa, \ab
+        dcache_invalidate_all   \aa, \ab
+        .endm
+
+
+
+
+/*
+ * Synchronize after a data cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous data cache control operations.
+ *
+ * Parameters are:
+ *      ar      an address register (temporary) (currently unused, but may be used in future)
+ */
+        .macro  dcache_sync     ar
+#if XCHAL_DCACHE_SIZE > 0
+        //  This previous sequence errs on the conservative side (too much so); a DSYNC should be sufficient:
+        //memw          // synchronize data cache changes relative to subsequent memory accesses
+        //isync         // be conservative and ISYNC as well (just to be sure)
+
+        dsync
+#endif
+        .endm
+
+
+
+/*
+ * Synchronize after a data store operation,
+ * to be sure the stored data is completely off the processor
+ * (and assuming there is no buffering outside the processor,
+ *  that the data is in memory).  This may be required to
+ * ensure that the processor's write buffers are emptied.
+ * A MEMW followed by a read guarantees this, by definition.
+ * We also try to make sure the read itself completes.
+ *
+ * Parameters are:
+ *      ar      an address register (temporary)
+ */
+        .macro  write_sync      ar
+        memw                    // ensure previous memory accesses are complete prior to subsequent memory accesses
+        l32i    \ar, sp, 0      // completing this read ensures any previous write has completed, because of MEMW
+        //slot
+        add     \ar, \ar, \ar   // use the result of the read to help ensure the read completes (in future architectures)
+        .endm
+
+
+/*
+ *  Invalidate a single line of the data cache.
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to invalidate
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  (optional) offset to add to \ar to compute effective address to invalidate
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  dcache_invalidate_line  ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+        dhi     \ar, \offset
+        dcache_sync     \ar
+#endif
+        .endm
+
+
+
+
+
+/*
+ *  Invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  dcache_invalidate_region        astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0
+        //  Data cache region invalidation:
+        cache_hit_region        dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+        dcache_sync     \ac
+        //  End of data cache region invalidation
+#endif
+        .endm
+
+
+
+#if 0
+/*
+ *  This is a work-around for a bug in SiChip1 (???).
+ *  There should be a proper mechanism for not outputting
+ *  these instructions when not needed.
+ *  To enable work-around, uncomment this and replace 'dii'
+ *  with 'dii_s1' everywhere, eg. in dcache_invalidate_all
+ *  macro below.
+ */
+        .macro  dii_s1  ar, offset
+        dii     \ar, \offset
+        or      \ar, \ar, \ar
+        or      \ar, \ar, \ar
+        or      \ar, \ar, \ar
+        or      \ar, \ar, \ar
+        .endm
+#endif
+
+
+/*
+ *  Invalidate entire data cache.
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  dcache_invalidate_all   aa, ab
+#if XCHAL_DCACHE_SIZE > 0
+        //  Data cache invalidation:
+        cache_index_all         dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab
+        dcache_sync     \aa
+        //  End of data cache invalidation
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback a single line of the data cache.
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to writeback
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to writeback
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  dcache_writeback_line   ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+        dhwb    \ar, \offset
+        dcache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback dirty data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  dcache_writeback_region         astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+        //  Data cache region writeback:
+        cache_hit_region        dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+        dcache_sync     \ac
+        //  End of data cache region writeback
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback entire data cache.
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  dcache_writeback_all    aa, ab
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+        //  Data cache writeback:
+        cache_index_all         diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
+        dcache_sync     \aa
+        //  End of data cache writeback
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback and invalidate a single line of the data cache.
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to writeback and invalidate
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to writeback and invalidate
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  dcache_writeback_inv_line       ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+        dhwbi   \ar, \offset    /* writeback and invalidate dcache line */
+        dcache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback and invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  dcache_writeback_inv_region     astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0
+        //  Data cache region writeback and invalidate:
+        cache_hit_region        dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+        dcache_sync     \ac
+        //  End of data cache region writeback and invalidate
+#endif
+        .endm
+
+
+
+/*
+ *  Writeback and invalidate entire data cache.
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  dcache_writeback_inv_all        aa, ab
+#if XCHAL_DCACHE_SIZE > 0
+        //  Data cache writeback and invalidate:
+#if XCHAL_DCACHE_IS_WRITEBACK
+        cache_index_all         diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
+        dcache_sync     \aa
+#else /*writeback*/
+        //  Data cache does not support writeback, so just invalidate: */
+        dcache_invalidate_all   \aa, \ab
+#endif /*writeback*/
+        //  End of data cache writeback and invalidate
+#endif
+        .endm
+
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the data cache.
+ *
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to lock
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to lock
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  dcache_lock_line        ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+        dpfl    \ar, \offset    /* prefetch and lock dcache line */
+        dcache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the data cache.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  dcache_lock_region      astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+        //  Data cache region lock:
+        cache_hit_region        dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+        dcache_sync     \ac
+        //  End of data cache region lock
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock a single line of the data cache.
+ *
+ *  Parameters are:
+ *      ar      address register that contains (virtual) address to unlock
+ *              (may get clobbered in a future implementation, but not currently)
+ *      offset  offset to add to \ar to compute effective address to unlock
+ *              (note: some number of lsbits are ignored)
+ */
+        .macro  dcache_unlock_line      ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+        dhu     \ar, \offset    /* unlock dcache line */
+        dcache_sync     \ar
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the data cache.
+ *  Parameters are:
+ *      astart  start address (register gets clobbered)
+ *      asize   size of the region in bytes (register gets clobbered)
+ *      ac      unique register used as temporary
+ */
+        .macro  dcache_unlock_region    astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+        //  Data cache region unlock:
+        cache_hit_region        dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+        dcache_sync     \ac
+        //  End of data cache region unlock
+#endif
+        .endm
+
+
+
+/*
+ *  Unlock entire data cache.
+ *
+ *  Parameters:
+ *      aa, ab          unique address registers (temporaries)
+ */
+        .macro  dcache_unlock_all       aa, ab
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+        //  Data cache unlock:
+        cache_index_all         diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
+        dcache_sync     \aa
+        //  End of data cache unlock
+#endif
+        .endm
+
+
+#endif /*XTENSA_CACHEASM_H*/
+
diff --git a/include/asm-xtensa/xtensa/cacheattrasm.h b/include/asm-xtensa/xtensa/cacheattrasm.h
new file mode 100644
index 000000000000..1c3e117b3592
--- /dev/null
+++ b/include/asm-xtensa/xtensa/cacheattrasm.h
@@ -0,0 +1,432 @@
+#ifndef XTENSA_CACHEATTRASM_H
+#define XTENSA_CACHEATTRASM_H
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/cacheattrasm.h -- assembler-specific
+ * CACHEATTR register related definitions that depend on CORE
+ * configuration.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/coreasm.h>
+
+
+/*
+ *  This header file defines assembler macros of the form:
+ *      <x>cacheattr_<func>
+ *  where:
+ *      <x> is 'i', 'd' or absent for instruction, data
+ *              or both caches; and
+ *      <func> indicates the function of the macro.
+ *
+ *  The following functions are defined:
+ *
+ *  icacheattr_get
+ *      Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
+ *
+ *  dcacheattr_get
+ *      Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
+ *      (Note:  for configs with a real CACHEATTR register, the
+ *       above two macros are identical.)
+ *
+ *  cacheattr_set
+ *      Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
+ *      Works even when changing one's own code's attributes.
+ *
+ *  icacheattr_is_enabled  label
+ *      Branches to \label if I-cache appears to have been enabled
+ *      (eg. if CACHEATTR contains a cache-enabled attribute).
+ *      (clobbers a2-a5,SAR)
+ *
+ *  dcacheattr_is_enabled  label
+ *      Branches to \label if D-cache appears to have been enabled
+ *      (eg. if CACHEATTR contains a cache-enabled attribute).
+ *      (clobbers a2-a5,SAR)
+ *
+ *  cacheattr_is_enabled  label
+ *      Branches to \label if either I-cache or D-cache appears to have been enabled
+ *      (eg. if CACHEATTR contains a cache-enabled attribute).
+ *      (clobbers a2-a5,SAR)
+ *
+ *  The following macros are only defined under certain conditions:
+ *
+ *  icacheattr_set      (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *      Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
+ *
+ *  dcacheattr_set      (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *      Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+/*
+ *  _cacheattr_get
+ *
+ *  (Internal macro.)
+ *  Returns value of CACHEATTR register (or closest equivalent) in a2.
+ *
+ *  Entry:
+ *      (none)
+ *  Exit:
+ *      a2      value read from CACHEATTR
+ *      a3-a5   clobbered (temporaries)
+ */
+        .macro  _cacheattr_get  tlb
+#if XCHAL_HAVE_CACHEATTR
+        rsr     a2, CACHEATTR
+#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        //  We have a config that "mimics" CACHEATTR using a simplified
+        //  "MMU" composed of a single statically-mapped way.
+        //  DTLB and ITLB are independent, so there's no single
+        //  cache attribute that can describe both.  So for now
+        //  just return the DTLB state.
+        movi    a5, 0xE0000000
+        movi    a2, 0
+        movi    a3, 0
+1:      add     a3, a3, a5      // next segment
+        r&tlb&1 a4, a3          // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
+        dsync   // interlock???
+        slli    a2, a2, 4
+        extui   a4, a4, 0, 4    // extract CA
+        or      a2, a2, a4
+        bnez    a3, 1b
+#else
+        //  This macro isn't applicable to arbitrary MMU configurations.
+        //  Just return zero.
+        movi    a2, 0
+#endif
+        .endm
+
+        .macro  icacheattr_get
+        _cacheattr_get  itlb
+        .endm
+
+        .macro  dcacheattr_get
+        _cacheattr_get  dtlb
+        .endm
+
+
+#define XCHAL_CACHEATTR_ALL_BYPASS      0x22222222      /* default (powerup/reset) value of CACHEATTR, all BYPASS
+                                                           mode (ie. disabled/bypassed caches) */
+
+#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+
+#define XCHAL_FCA_ENAMASK       0x001A  /* bitmap of fetch attributes that require enabled icache */
+#define XCHAL_LCA_ENAMASK       0x0003  /* bitmap of load  attributes that require enabled dcache */
+#define XCHAL_SCA_ENAMASK       0x0003  /* bitmap of store attributes that require enabled dcache */
+#define XCHAL_LSCA_ENAMASK      (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK)   /* l/s attrs requiring enabled dcache */
+#define XCHAL_ALLCA_ENAMASK     (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK)  /* all attrs requiring enabled caches */
+
+/*
+ *  _cacheattr_is_enabled
+ *
+ *  (Internal macro.)
+ *  Branches to \label if CACHEATTR in a2 indicates an enabled
+ *  cache, using mask in a3.
+ *
+ *  Parameters:
+ *      label   where to branch to if cache is enabled
+ *  Entry:
+ *      a2      contains CACHEATTR value used to determine whether
+ *              caches are enabled
+ *      a3      16-bit constant where each bit correspond to
+ *              one of the 16 possible CA values (in a CACHEATTR mask);
+ *              CA values that indicate the cache is enabled
+ *              have their corresponding bit set in this mask
+ *              (eg. use XCHAL_xCA_ENAMASK , above)
+ *  Exit:
+ *      a2,a4,a5        clobbered
+ *      SAR             clobbered
+ */
+        .macro  _cacheattr_is_enabled   label
+        movi    a4, 8           // loop 8 times
+.Lcaife\@:
+        extui   a5, a2, 0, 4    // get CA nibble
+        ssr     a5              // index into mask according to CA...
+        srl     a5, a3          // ...and get CA's mask bit in a5 bit 0
+        bbsi.l  a5, 0, \label   // if CA indicates cache enabled, jump to label
+        srli    a2, a2, 4       // next nibble
+        addi    a4, a4, -1
+        bnez    a4, .Lcaife\@   // loop for each nibble
+        .endm
+
+#else /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
+        .macro  _cacheattr_is_enabled   label
+        j       \label          // macro not applicable, assume caches always enabled
+        .endm
+#endif /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
+
+
+
+/*
+ *  icacheattr_is_enabled
+ *
+ *  Branches to \label if I-cache is enabled.
+ *
+ *  Parameters:
+ *      label   where to branch to if icache is enabled
+ *  Entry:
+ *      (none)
+ *  Exit:
+ *      a2-a5, SAR      clobbered (temporaries)
+ */
+        .macro  icacheattr_is_enabled   label
+#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        icacheattr_get
+        movi    a3, XCHAL_FCA_ENAMASK
+#endif
+        _cacheattr_is_enabled   \label
+        .endm
+
+/*
+ *  dcacheattr_is_enabled
+ *
+ *  Branches to \label if D-cache is enabled.
+ *
+ *  Parameters:
+ *      label   where to branch to if dcache is enabled
+ *  Entry:
+ *      (none)
+ *  Exit:
+ *      a2-a5, SAR      clobbered (temporaries)
+ */
+        .macro  dcacheattr_is_enabled   label
+#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        dcacheattr_get
+        movi    a3, XCHAL_LSCA_ENAMASK
+#endif
+        _cacheattr_is_enabled   \label
+        .endm
+
+/*
+ *  cacheattr_is_enabled
+ *
+ *  Branches to \label if either I-cache or D-cache is enabled.
+ *
+ *  Parameters:
+ *      label   where to branch to if a cache is enabled
+ *  Entry:
+ *      (none)
+ *  Exit:
+ *      a2-a5, SAR      clobbered (temporaries)
+ */
+        .macro  cacheattr_is_enabled    label
+#if XCHAL_HAVE_CACHEATTR
+        rsr     a2, CACHEATTR
+        movi    a3, XCHAL_ALLCA_ENAMASK
+#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        icacheattr_get
+        movi    a3, XCHAL_FCA_ENAMASK
+        _cacheattr_is_enabled   \label
+        dcacheattr_get
+        movi    a3, XCHAL_LSCA_ENAMASK
+#endif
+        _cacheattr_is_enabled   \label
+        .endm
+
+
+
+/*
+ *  The ISA does not have a defined way to change the
+ *  instruction cache attributes of the running code,
+ *  ie. of the memory area that encloses the current PC.
+ *  However, each micro-architecture (or class of
+ *  configurations within a micro-architecture)
+ *  provides a way to deal with this issue.
+ *
+ *  Here are a few macros used to implement the relevant
+ *  approach taken.
+ */
+
+#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        //  We have a config that "mimics" CACHEATTR using a simplified
+        //  "MMU" composed of a single statically-mapped way.
+
+/*
+ *  icacheattr_set
+ *
+ *  Entry:
+ *      a2              cacheattr value to set
+ *  Exit:
+ *      a2              unchanged
+ *      a3-a8           clobbered (temporaries)
+ */
+        .macro  icacheattr_set
+
+        movi    a5, 0xE0000000  // mask of upper 3 bits
+        movi    a6, 3f          // PC where ITLB is set
+        movi    a3, 0           // start at region 0 (0 .. 7)
+        and     a6, a6, a5      // upper 3 bits of local PC area
+        mov     a7, a2          // copy a2 so it doesn't get clobbered
+        j       3f
+
+# if XCHAL_HAVE_XLT_CACHEATTR
+        //  Can do translations, use generic method:
+1:      sub     a6, a3, a5      // address of some other segment
+        ritlb1  a8, a6          // save its PPN+CA
+        dsync   // interlock??
+        witlb   a4, a6          // make it translate to this code area
+        movi    a6, 5f          // where to jump into it
+        isync
+        sub     a6, a6, a5      // adjust jump address within that other segment
+        jx      a6
+
+        //  Note that in the following code snippet, which runs at a different virtual
+        //  address than it is assembled for, we avoid using literals (eg. via movi/l32r)
+        //  just in case literals end up in a different 512 MB segment, and we avoid
+        //  instructions that rely on the current PC being what is expected.
+        //
+        .align  4
+        _j      6f              // this is at label '5' minus 4 bytes
+        .align  4
+5:      witlb   a4, a3          // we're in other segment, now can write previous segment's CA
+        isync
+        add     a6, a6, a5      // back to previous segment
+        addi    a6, a6, -4      // next jump label
+        jx      a6
+
+6:      sub     a6, a3, a5      // address of some other segment
+        witlb   a8, a6          // restore PPN+CA of other segment
+        mov     a6, a3          // restore a6
+        isync
+# else /* XCHAL_HAVE_XLT_CACHEATTR */
+        //  Use micro-architecture specific method.
+        //  The following 4-instruction sequence is aligned such that
+        //  it all fits within a single I-cache line.  Sixteen byte
+        //  alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
+        //  actually causes problems because that can be greater than
+        //  the alignment of the reset vector, where this macro is often
+        //  invoked, which would cause the linker to align the reset
+        //  vector code away from the reset vector!!).
+        .align  16 /*XCHAL_ICACHE_LINESIZE*/
+1:      _witlb  a4, a3          // write wired PTE (CA, no PPN) of 512MB segment to ITLB
+        _isync
+        nop
+        nop
+# endif /* XCHAL_HAVE_XLT_CACHEATTR */
+        beq     a3, a5, 4f      // done?
+
+        //  Note that in the WITLB loop, we don't do any load/stores
+        //  (may not be an issue here, but it is important in the DTLB case).
+2:      srli    a7, a7, 4       // next CA
+        sub     a3, a3, a5      // next segment (add 0x20000000)
+3:
+# if XCHAL_HAVE_XLT_CACHEATTR   /* if have translation, preserve it */
+        ritlb1  a8, a3          // get current PPN+CA of segment
+        dsync   // interlock???
+        extui   a4, a7, 0, 4    // extract CA to set
+        srli    a8, a8, 4       // clear CA but keep PPN ...
+        slli    a8, a8, 4       // ...
+        add     a4, a4, a8      // combine new CA with PPN to preserve
+# else
+        extui   a4, a7, 0, 4    // extract CA
+# endif
+        beq     a3, a6, 1b      // current PC's region? if so, do it in a safe way
+        witlb   a4, a3          // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
+        bne     a3, a5, 2b
+        isync                   // make sure all ifetch changes take effect
+4:
+        .endm   // icacheattr_set
+
+
+/*
+ *  dcacheattr_set
+ *
+ *  Entry:
+ *      a2              cacheattr value to set
+ *  Exit:
+ *      a2              unchanged
+ *      a3-a8           clobbered (temporaries)
+ */
+
+        .macro  dcacheattr_set
+
+        movi    a5, 0xE0000000  // mask of upper 3 bits
+        movi    a3, 0           // start at region 0 (0 .. 7)
+        mov     a7, a2          // copy a2 so it doesn't get clobbered
+        j       3f
+        //  Note that in the WDTLB loop, we don't do any load/stores
+        //  (including implicit l32r via movi) because it isn't safe.
+2:      srli    a7, a7, 4       // next CA
+        sub     a3, a3, a5      // next segment (add 0x20000000)
+3:
+# if XCHAL_HAVE_XLT_CACHEATTR   /* if have translation, preserve it */
+        rdtlb1  a8, a3          // get current PPN+CA of segment
+        dsync   // interlock???
+        extui   a4, a7, 0, 4    // extract CA to set
+        srli    a8, a8, 4       // clear CA but keep PPN ...
+        slli    a8, a8, 4       // ...
+        add     a4, a4, a8      // combine new CA with PPN to preserve
+# else
+        extui   a4, a7, 0, 4    // extract CA to set
+# endif
+        wdtlb   a4, a3          // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
+        bne     a3, a5, 2b
+        dsync                   // make sure all data path changes take effect
+        .endm   // dcacheattr_set
+
+#endif /* XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
+
+
+
+/*
+ *  cacheattr_set
+ *
+ *  Macro that sets the current CACHEATTR safely
+ *  (both i and d) according to the current contents of a2.
+ *  It works even when changing the cache attributes of
+ *  the currently running code.
+ *
+ *  Entry:
+ *      a2              cacheattr value to set
+ *  Exit:
+ *      a2              unchanged
+ *      a3-a8           clobbered (temporaries)
+ */
+        .macro  cacheattr_set
+
+#if XCHAL_HAVE_CACHEATTR
+# if XCHAL_ICACHE_LINESIZE < 4
+        //  No i-cache, so can always safely write to CACHEATTR:
+        wsr     a2, CACHEATTR
+# else
+        //  The Athens micro-architecture, when using the old
+        //  exception architecture option (ie. with the CACHEATTR register)
+        //  allows changing the cache attributes of the running code
+        //  using the following exact sequence aligned to be within
+        //  an instruction cache line.  (NOTE: using XCHAL_ICACHE_LINESIZE
+        //  alignment actually causes problems because that can be greater
+        //  than the alignment of the reset vector, where this macro is often
+        //  invoked, which would cause the linker to align the reset
+        //  vector code away from the reset vector!!).
+        j       1f
+        .align  16 /*XCHAL_ICACHE_LINESIZE*/    // align to within an I-cache line
+1:      _wsr    a2, CACHEATTR
+        _isync
+        nop
+        nop
+# endif
+#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
+        //  DTLB and ITLB are independent, but to keep semantics
+        //  of this macro we simply write to both.
+        icacheattr_set
+        dcacheattr_set
+#else
+        //  This macro isn't applicable to arbitrary MMU configurations.
+        //  Do nothing in this case.
+#endif
+        .endm
+
+
+#endif /*XTENSA_CACHEATTRASM_H*/
+
diff --git a/include/asm-xtensa/xtensa/config-linux_be/core.h b/include/asm-xtensa/xtensa/config-linux_be/core.h
new file mode 100644
index 000000000000..d54fe5eb1064
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/core.h
@@ -0,0 +1,1270 @@
+/*
+ * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
+ *
+ *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
+ *  It was generated for a specific Xtensa processor configuration.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  It is perfectly normal, however, for the HAL source itself to include this file.
+ */
+
+/*
+ * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+
+#ifndef XTENSA_CONFIG_CORE_H
+#define XTENSA_CONFIG_CORE_H
+
+#include <xtensa/hal.h>
+
+
+/*----------------------------------------------------------------------
+                                GENERAL
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Separators for macros that expand into arrays.
+ *  These can be predefined by files that #include this one,
+ *  when different separators are required.
+ */
+/*  Element separator for macros that expand into 1-dimensional arrays:  */
+#ifndef XCHAL_SEP
+#define XCHAL_SEP                       ,
+#endif
+/*  Array separator for macros that expand into 2-dimensional arrays:  */
+#ifndef XCHAL_SEP2
+#define XCHAL_SEP2                      },{
+#endif
+
+
+/*----------------------------------------------------------------------
+                                ENDIANNESS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE                   1
+#define XCHAL_HAVE_LE                   0
+#define XCHAL_MEMORY_ORDER              XTHAL_BIGENDIAN
+
+
+/*----------------------------------------------------------------------
+                                REGISTER WINDOWS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_WINDOWED             1       /* 1 if windowed registers option configured, 0 otherwise */
+#define XCHAL_NUM_AREGS                 64      /* number of physical address regs */
+#define XCHAL_NUM_AREGS_LOG2            6       /* log2(XCHAL_NUM_AREGS) */
+
+
+/*----------------------------------------------------------------------
+                                ADDRESS ALIGNMENT
+  ----------------------------------------------------------------------*/
+
+/*  These apply to a selected set of core load and store instructions only (see ISA):  */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION  1       /* 1 if unaligned loads cause an exception, 0 otherwise */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 1       /* 1 if unaligned stores cause an exception, 0 otherwise */
+
+
+/*----------------------------------------------------------------------
+                                INTERRUPTS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS           1       /* 1 if interrupt option configured, 0 otherwise */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS   1       /* 1 if high-priority interrupt option configured, 0 otherwise */
+#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
+#define XCHAL_HAVE_NMI                  0       /* 1 if NMI option configured, 0 otherwise */
+#define XCHAL_NUM_INTERRUPTS            17      /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2       5       /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
+#define XCHAL_NUM_EXTINTERRUPTS         10      /* number of external interrupts */
+#define XCHAL_NUM_INTLEVELS             4       /* number of interrupt levels (not including level zero!) */
+#define XCHAL_NUM_LOWPRI_LEVELS         1                       /* number of low-priority interrupt levels (always 1) */
+#define XCHAL_FIRST_HIGHPRI_LEVEL       (XCHAL_NUM_LOWPRI_LEVELS+1)     /* level of first high-priority interrupt (always 2) */
+#define XCHAL_EXCM_LEVEL                1                       /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
+                                                                   for XEA1, where there is no PS.EXCM, this is always 1;
+                                                                   interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
+                                                                   are termed "medium priority" interrupts (post T10xx only) */
+/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL0_MASK            0x00000000
+#define XCHAL_INTLEVEL1_MASK            0x000064F9
+#define XCHAL_INTLEVEL2_MASK            0x00008902
+#define XCHAL_INTLEVEL3_MASK            0x00011204
+#define XCHAL_INTLEVEL4_MASK            0x00000000
+#define XCHAL_INTLEVEL5_MASK            0x00000000
+#define XCHAL_INTLEVEL6_MASK            0x00000000
+#define XCHAL_INTLEVEL7_MASK            0x00000000
+#define XCHAL_INTLEVEL8_MASK            0x00000000
+#define XCHAL_INTLEVEL9_MASK            0x00000000
+#define XCHAL_INTLEVEL10_MASK           0x00000000
+#define XCHAL_INTLEVEL11_MASK           0x00000000
+#define XCHAL_INTLEVEL12_MASK           0x00000000
+#define XCHAL_INTLEVEL13_MASK           0x00000000
+#define XCHAL_INTLEVEL14_MASK           0x00000000
+#define XCHAL_INTLEVEL15_MASK           0x00000000
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_INTLEVEL_MASKS            0x00000000      XCHAL_SEP \
+                                        0x000064F9      XCHAL_SEP \
+                                        0x00008902      XCHAL_SEP \
+                                        0x00011204      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000      XCHAL_SEP \
+                                        0x00000000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL0_ANDBELOW_MASK   0x00000000
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK   0x000064F9
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK   0x0000EDFB
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL8_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL9_ANDBELOW_MASK   0x0001FFFF
+#define XCHAL_INTLEVEL10_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_INTLEVEL11_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_INTLEVEL12_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_INTLEVEL13_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_INTLEVEL14_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_INTLEVEL15_ANDBELOW_MASK  0x0001FFFF
+#define XCHAL_LOWPRI_MASK               XCHAL_INTLEVEL1_ANDBELOW_MASK   /* mask of all low-priority interrupts */
+#define XCHAL_EXCM_MASK                 XCHAL_INTLEVEL1_ANDBELOW_MASK   /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_INTLEVEL_ANDBELOW_MASKS   0x00000000      XCHAL_SEP \
+                                        0x000064F9      XCHAL_SEP \
+                                        0x0000EDFB      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF      XCHAL_SEP \
+                                        0x0001FFFF
+
+/*  Interrupt numbers for each interrupt level at which only one interrupt was configured:  */
+/*#define XCHAL_INTLEVEL1_NUM           ...more than one interrupt at this level...*/
+/*#define XCHAL_INTLEVEL2_NUM           ...more than one interrupt at this level...*/
+/*#define XCHAL_INTLEVEL3_NUM           ...more than one interrupt at this level...*/
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL                1
+#define XCHAL_INT1_LEVEL                2
+#define XCHAL_INT2_LEVEL                3
+#define XCHAL_INT3_LEVEL                1
+#define XCHAL_INT4_LEVEL                1
+#define XCHAL_INT5_LEVEL                1
+#define XCHAL_INT6_LEVEL                1
+#define XCHAL_INT7_LEVEL                1
+#define XCHAL_INT8_LEVEL                2
+#define XCHAL_INT9_LEVEL                3
+#define XCHAL_INT10_LEVEL               1
+#define XCHAL_INT11_LEVEL               2
+#define XCHAL_INT12_LEVEL               3
+#define XCHAL_INT13_LEVEL               1
+#define XCHAL_INT14_LEVEL               1
+#define XCHAL_INT15_LEVEL               2
+#define XCHAL_INT16_LEVEL               3
+#define XCHAL_INT17_LEVEL               0
+#define XCHAL_INT18_LEVEL               0
+#define XCHAL_INT19_LEVEL               0
+#define XCHAL_INT20_LEVEL               0
+#define XCHAL_INT21_LEVEL               0
+#define XCHAL_INT22_LEVEL               0
+#define XCHAL_INT23_LEVEL               0
+#define XCHAL_INT24_LEVEL               0
+#define XCHAL_INT25_LEVEL               0
+#define XCHAL_INT26_LEVEL               0
+#define XCHAL_INT27_LEVEL               0
+#define XCHAL_INT28_LEVEL               0
+#define XCHAL_INT29_LEVEL               0
+#define XCHAL_INT30_LEVEL               0
+#define XCHAL_INT31_LEVEL               0
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_INT_LEVELS                1       XCHAL_SEP \
+                                        2       XCHAL_SEP \
+                                        3       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        2       XCHAL_SEP \
+                                        3       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        2       XCHAL_SEP \
+                                        3       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        1       XCHAL_SEP \
+                                        2       XCHAL_SEP \
+                                        3       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0       XCHAL_SEP \
+                                        0
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT7_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT8_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT9_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT10_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT12_TYPE        XTHAL_INTTYPE_TIMER
+#define XCHAL_INT13_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT14_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT15_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT16_TYPE        XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT17_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT18_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT19_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT20_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT21_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT22_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT23_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT24_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT25_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT26_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT27_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT28_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT29_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT30_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+#define XCHAL_INT31_TYPE        XTHAL_INTTYPE_UNCONFIGURED
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_INT_TYPES         XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_LEVEL      XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
+                                XTHAL_INTTYPE_EXTERN_EDGE       XCHAL_SEP \
+                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
+                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
+                                XTHAL_INTTYPE_TIMER             XCHAL_SEP \
+                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
+                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
+                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
+                                XTHAL_INTTYPE_SOFTWARE          XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED      XCHAL_SEP \
+                                XTHAL_INTTYPE_UNCONFIGURED
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
+#define XCHAL_INTTYPE_MASK_SOFTWARE     0x0001E000
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE  0x00000380
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
+#define XCHAL_INTTYPE_MASK_TIMER        0x00001C00
+#define XCHAL_INTTYPE_MASK_NMI          0x00000000
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_INTTYPE_MASKS             0xFFFE0000      XCHAL_SEP \
+                                        0x0001E000      XCHAL_SEP \
+                                        0x00000380      XCHAL_SEP \
+                                        0x0000007F      XCHAL_SEP \
+                                        0x00001C00      XCHAL_SEP \
+                                        0x00000000
+
+/*  Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned  */
+#define XCHAL_TIMER0_INTERRUPT  10
+#define XCHAL_TIMER1_INTERRUPT  11
+#define XCHAL_TIMER2_INTERRUPT  12
+#define XCHAL_TIMER3_INTERRUPT  XTHAL_TIMER_UNCONFIGURED
+/*  As an array of entries (eg. for C constant arrays):  */
+#define XCHAL_TIMER_INTERRUPTS  10      XCHAL_SEP \
+                                11      XCHAL_SEP \
+                                12      XCHAL_SEP \
+                                XTHAL_TIMER_UNCONFIGURED
+
+/*  Indexing macros:  */
+#define _XCHAL_INTLEVEL_MASK(n)         XCHAL_INTLEVEL ## n ## _MASK
+#define XCHAL_INTLEVEL_MASK(n)          _XCHAL_INTLEVEL_MASK(n)         /* n = 0 .. 15 */
+#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
+#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
+#define _XCHAL_INT_LEVEL(n)             XCHAL_INT ## n ## _LEVEL
+#define XCHAL_INT_LEVEL(n)              _XCHAL_INT_LEVEL(n)             /* n = 0 .. 31 */
+#define _XCHAL_INT_TYPE(n)              XCHAL_INT ## n ## _TYPE
+#define XCHAL_INT_TYPE(n)               _XCHAL_INT_TYPE(n)              /* n = 0 .. 31 */
+#define _XCHAL_TIMER_INTERRUPT(n)       XCHAL_TIMER ## n ## _INTERRUPT
+#define XCHAL_TIMER_INTERRUPT(n)        _XCHAL_TIMER_INTERRUPT(n)       /* n = 0 .. 3 */
+
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM               0       /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM               1       /* (intlevel 2) */
+#define XCHAL_EXTINT2_NUM               2       /* (intlevel 3) */
+#define XCHAL_EXTINT3_NUM               3       /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM               4       /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM               5       /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM               6       /* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM               7       /* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM               8       /* (intlevel 2) */
+#define XCHAL_EXTINT9_NUM               9       /* (intlevel 3) */
+
+/*  Corresponding interrupt masks:  */
+#define XCHAL_EXTINT0_MASK              0x00000001
+#define XCHAL_EXTINT1_MASK              0x00000002
+#define XCHAL_EXTINT2_MASK              0x00000004
+#define XCHAL_EXTINT3_MASK              0x00000008
+#define XCHAL_EXTINT4_MASK              0x00000010
+#define XCHAL_EXTINT5_MASK              0x00000020
+#define XCHAL_EXTINT6_MASK              0x00000040
+#define XCHAL_EXTINT7_MASK              0x00000080
+#define XCHAL_EXTINT8_MASK              0x00000100
+#define XCHAL_EXTINT9_MASK              0x00000200
+
+/*  Core config interrupt levels mapped to each external interrupt:  */
+#define XCHAL_EXTINT0_LEVEL             1       /* (int number 0) */
+#define XCHAL_EXTINT1_LEVEL             2       /* (int number 1) */
+#define XCHAL_EXTINT2_LEVEL             3       /* (int number 2) */
+#define XCHAL_EXTINT3_LEVEL             1       /* (int number 3) */
+#define XCHAL_EXTINT4_LEVEL             1       /* (int number 4) */
+#define XCHAL_EXTINT5_LEVEL             1       /* (int number 5) */
+#define XCHAL_EXTINT6_LEVEL             1       /* (int number 6) */
+#define XCHAL_EXTINT7_LEVEL             1       /* (int number 7) */
+#define XCHAL_EXTINT8_LEVEL             2       /* (int number 8) */
+#define XCHAL_EXTINT9_LEVEL             3       /* (int number 9) */
+
+
+/*----------------------------------------------------------------------
+                        EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_EXCEPTIONS           1       /* 1 if exception option configured, 0 otherwise */
+
+#define XCHAL_XEA_VERSION               2       /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
+#define XCHAL_HAVE_XEA1                 0       /* 1 if XEA1, 0 otherwise */
+#define XCHAL_HAVE_XEA2                 1       /* 1 if XEA2, 0 otherwise */
+/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
+#define XCHAL_HAVE_OLD_EXC_ARCH         XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
+#define XCHAL_HAVE_EXCM                 XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
+
+#define XCHAL_RESET_VECTOR_VADDR        0xFE000020
+#define XCHAL_RESET_VECTOR_PADDR        0xFE000020
+#define XCHAL_USER_VECTOR_VADDR         0xD0000220
+#define XCHAL_PROGRAMEXC_VECTOR_VADDR   XCHAL_USER_VECTOR_VADDR         /* for backward compatibility */
+#define XCHAL_USEREXC_VECTOR_VADDR      XCHAL_USER_VECTOR_VADDR         /* for backward compatibility */
+#define XCHAL_USER_VECTOR_PADDR         0x00000220
+#define XCHAL_PROGRAMEXC_VECTOR_PADDR   XCHAL_USER_VECTOR_PADDR         /* for backward compatibility */
+#define XCHAL_USEREXC_VECTOR_PADDR      XCHAL_USER_VECTOR_PADDR         /* for backward compatibility */
+#define XCHAL_KERNEL_VECTOR_VADDR       0xD0000200
+#define XCHAL_STACKEDEXC_VECTOR_VADDR   XCHAL_KERNEL_VECTOR_VADDR       /* for backward compatibility */
+#define XCHAL_KERNELEXC_VECTOR_VADDR    XCHAL_KERNEL_VECTOR_VADDR       /* for backward compatibility */
+#define XCHAL_KERNEL_VECTOR_PADDR       0x00000200
+#define XCHAL_STACKEDEXC_VECTOR_PADDR   XCHAL_KERNEL_VECTOR_PADDR       /* for backward compatibility */
+#define XCHAL_KERNELEXC_VECTOR_PADDR    XCHAL_KERNEL_VECTOR_PADDR       /* for backward compatibility */
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR    0xD0000290
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR    0x00000290
+#define XCHAL_WINDOW_VECTORS_VADDR      0xD0000000
+#define XCHAL_WINDOW_VECTORS_PADDR      0x00000000
+#define XCHAL_INTLEVEL2_VECTOR_VADDR    0xD0000240
+#define XCHAL_INTLEVEL2_VECTOR_PADDR    0x00000240
+#define XCHAL_INTLEVEL3_VECTOR_VADDR    0xD0000250
+#define XCHAL_INTLEVEL3_VECTOR_PADDR    0x00000250
+#define XCHAL_INTLEVEL4_VECTOR_VADDR    0xFE000520
+#define XCHAL_INTLEVEL4_VECTOR_PADDR    0xFE000520
+#define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR        XCHAL_INTLEVEL4_VECTOR_PADDR
+
+/*  Indexing macros:  */
+#define _XCHAL_INTLEVEL_VECTOR_VADDR(n)         XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
+#define XCHAL_INTLEVEL_VECTOR_VADDR(n)          _XCHAL_INTLEVEL_VECTOR_VADDR(n)         /* n = 0 .. 15 */
+
+/*
+ *  General Exception Causes
+ *  (values of EXCCAUSE special register set by general exceptions,
+ *   which vector to the user, kernel, or double-exception vectors):
+ */
+#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION              0       /* Illegal Instruction (IllegalInstruction) */
+#define XCHAL_EXCCAUSE_SYSTEM_CALL                      1       /* System Call (SystemCall) */
+#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR          2       /* Instruction Fetch Error (InstructionFetchError) */
+#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR                 3       /* Load Store Error (LoadStoreError) */
+#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT                 4       /* Level 1 Interrupt (Level1Interrupt) */
+#define XCHAL_EXCCAUSE_ALLOCA                           5       /* Stack Extension Assist (Alloca) */
+#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO           6       /* Integer Divide by Zero (IntegerDivideByZero) */
+#define XCHAL_EXCCAUSE_SPECULATION                      7       /* Speculation (Speculation) */
+#define XCHAL_EXCCAUSE_PRIVILEGED                       8       /* Privileged Instruction (Privileged) */
+#define XCHAL_EXCCAUSE_UNALIGNED                        9       /* Unaligned Load Store (Unaligned) */
+#define XCHAL_EXCCAUSE_ITLB_MISS                        16      /* ITlb Miss Exception (ITlbMiss) */
+#define XCHAL_EXCCAUSE_ITLB_MULTIHIT                    17      /* ITlb Mutltihit Exception (ITlbMultihit) */
+#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE                   18      /* ITlb Privilege Exception (ITlbPrivilege) */
+#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION            19      /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
+#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE            20      /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
+#define XCHAL_EXCCAUSE_DTLB_MISS                        24      /* DTlb Miss Exception (DTlbMiss) */
+#define XCHAL_EXCCAUSE_DTLB_MULTIHIT                    25      /* DTlb Multihit Exception (DTlbMultihit) */
+#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE                   26      /* DTlb Privilege Exception (DTlbPrivilege) */
+#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION            27      /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
+#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE             28      /* Load Cache Attribute Exception (LoadCacheAttribute) */
+#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE            29      /* Store Cache Attribute Exception (StoreCacheAttribute) */
+#define XCHAL_EXCCAUSE_FLOATING_POINT                   40      /* Floating Point Exception (FloatingPoint) */
+
+
+
+/*----------------------------------------------------------------------
+                                TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_CCOUNT               1       /* 1 if have CCOUNT, 0 otherwise */
+/*#define XCHAL_HAVE_TIMERS             XCHAL_HAVE_CCOUNT*/
+#define XCHAL_NUM_TIMERS                3       /* number of CCOMPAREn regs */
+
+
+
+/*----------------------------------------------------------------------
+                                DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_DEBUG                1       /* 1 if debug option configured, 0 otherwise */
+#define XCHAL_HAVE_OCD                  1       /* 1 if OnChipDebug option configured, 0 otherwise */
+#define XCHAL_NUM_IBREAK                2       /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK                2       /* number of DBREAKn regs */
+#define XCHAL_DEBUGLEVEL                4       /* debug interrupt level */
+/*DebugExternalInterrupt                0               0|1*/
+/*DebugUseDIRArray                      0               0|1*/
+
+
+
+
+/*----------------------------------------------------------------------
+                        COPROCESSORS and EXTRA STATE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_CP                   0       /* 1 if coprocessor option configured (CPENABLE present) */
+#define XCHAL_CP_MAXCFG                 0       /* max allowed cp id plus one (per cfg) */
+
+#include <xtensa/config/tie.h>
+
+
+
+
+/*----------------------------------------------------------------------
+                        INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM               0       /* number of core instruction ROMs configured */
+#define XCHAL_NUM_INSTRAM               0       /* number of core instruction RAMs configured */
+#define XCHAL_NUM_DATAROM               0       /* number of core data ROMs configured */
+#define XCHAL_NUM_DATARAM               0       /* number of core data RAMs configured */
+#define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports configured */
+#define  XCHAL_NUM_IROM                 XCHAL_NUM_INSTROM       /* (DEPRECATED) */
+#define  XCHAL_NUM_IRAM                 XCHAL_NUM_INSTRAM       /* (DEPRECATED) */
+#define  XCHAL_NUM_DROM                 XCHAL_NUM_DATAROM       /* (DEPRECATED) */
+#define  XCHAL_NUM_DRAM                 XCHAL_NUM_DATARAM       /* (DEPRECATED) */
+
+
+
+/*----------------------------------------------------------------------
+                                CACHE
+  ----------------------------------------------------------------------*/
+
+/*  Size of the cache lines in log2(bytes):  */
+#define XCHAL_ICACHE_LINEWIDTH          4
+#define XCHAL_DCACHE_LINEWIDTH          4
+/*  Size of the cache lines in bytes:  */
+#define XCHAL_ICACHE_LINESIZE           16
+#define XCHAL_DCACHE_LINESIZE           16
+/*  Max for both I-cache and D-cache (used for general alignment):  */
+#define XCHAL_CACHE_LINEWIDTH_MAX       4
+#define XCHAL_CACHE_LINESIZE_MAX        16
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH           8
+#define XCHAL_DCACHE_SETWIDTH           8
+/*  Max for both I-cache and D-cache (used for general cache-coherency page alignment):  */
+#define XCHAL_CACHE_SETWIDTH_MAX        8
+#define XCHAL_CACHE_SETSIZE_MAX         256
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS               2
+#define XCHAL_DCACHE_WAYS               2
+
+/*  Size of the caches in bytes (ways * 2^(linewidth + setwidth)):  */
+#define XCHAL_ICACHE_SIZE               8192
+#define XCHAL_DCACHE_SIZE               8192
+
+/*  Cache features:  */
+#define XCHAL_DCACHE_IS_WRITEBACK       0
+/*  Whether cache locking feature is available:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE      0
+#define XCHAL_DCACHE_LINE_LOCKABLE      0
+
+/*  Number of (encoded) cache attribute bits:  */
+#define XCHAL_CA_BITS                   4       /* number of bits needed to hold cache attribute encoding */
+/*  (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?)  */
+
+
+/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
+#define XCHAL_FCA_LIST          XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_BYPASS        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_BYPASS        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_CACHED        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_CACHED        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_CACHED        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_CACHED        XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_FAM_EXCEPTION
+#define XCHAL_LCA_LIST          XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_BYPASSG       XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_BYPASSG       XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_CACHED        XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_CACHED        XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_NACACHED      XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_NACACHED      XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_ISOLATE       XCHAL_SEP \
+                                XTHAL_LAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_LAM_CACHED
+#define XCHAL_SCA_LIST          XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_BYPASS        XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_WRITETHRU     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_WRITETHRU     XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_ISOLATE       XCHAL_SEP \
+                                XTHAL_SAM_EXCEPTION     XCHAL_SEP \
+                                XTHAL_SAM_WRITETHRU
+
+/*  Test:
+        read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
+        read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
+        all:       0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
+        fault:     0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
+        r/w/x cached:
+        r/w/x dcached:
+        I-bypass:  1 + 3
+
+        load guard bit set: 1 + 3
+        load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
+        hit-cache r/w/x: 7 + 11
+
+        fams: 5
+        fams: 0 / 6 / 18 / 1 / 2
+        fams: Bypass / Isolate / Cached / Exception / NACached
+
+        MMU okay:  yes
+*/
+
+
+/*----------------------------------------------------------------------
+                                MMU
+  ----------------------------------------------------------------------*/
+
+/*
+ *  General notes on MMU parameters.
+ *
+ *  Terminology:
+ *      ASID = address-space ID (acts as an "extension" of virtual addresses)
+ *      VPN  = virtual page number
+ *      PPN  = physical page number
+ *      CA   = encoded cache attribute (access modes)
+ *      TLB  = translation look-aside buffer (term is stretched somewhat here)
+ *      I    = instruction (fetch accesses)
+ *      D    = data (load and store accesses)
+ *      way  = each TLB (ITLB and DTLB) consists of a number of "ways"
+ *              that simultaneously match the virtual address of an access;
+ *              a TLB successfully translates a virtual address if exactly
+ *              one way matches the vaddr; if none match, it is a miss;
+ *              if multiple match, one gets a "multihit" exception;
+ *              each way can be independently configured in terms of number of
+ *              entries, page sizes, which fields are writable or constant, etc.
+ *      set  = group of contiguous ways with exactly identical parameters
+ *      ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
+ *              from the page table and storing it in one of the auto-refill ways;
+ *              if this PTE load also misses, a miss exception is posted for s/w.
+ *      min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ *              page arbitrarily under program control; it has a single entry,
+ *              is non-auto-refill (some other way(s) must be auto-refill),
+ *              all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ *              supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ *              restriction is that this be the only page size it supports).
+ *
+ *  TLB way entries are virtually indexed.
+ *  TLB ways that support multiple page sizes:
+ *      - must have all writable VPN and PPN fields;
+ *      - can only use one page size at any given time (eg. setup at startup),
+ *        selected by the respective ITLBCFG or DTLBCFG special register,
+ *        whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ *        (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ *        this list may be sparse for auto-refill ways because auto-refill
+ *        ways have independent lists of supported page sizes sharing a
+ *        common encoding with PTE entries; the encoding is the index into
+ *        this list; unsupported sizes for a given way are zero in the list;
+ *        selecting unsupported sizes results in undefined hardware behaviour;
+ *      - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
+#define XCHAL_HAVE_CACHEATTR            0       /* 1 if CACHEATTR register present, 0 if TLBs present instead */
+#define XCHAL_HAVE_TLBS                 1       /* 1 if TLBs present, 0 if CACHEATTR present instead */
+#define XCHAL_HAVE_MMU                  XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
+#define XCHAL_HAVE_SPANNING_WAY         0       /* 1 if single way maps entire virtual address space in I+D */
+#define XCHAL_HAVE_IDENTITY_MAP         0       /* 1 if virtual addr == physical addr always, 0 otherwise */
+#define XCHAL_HAVE_MIMIC_CACHEATTR      0       /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
+#define XCHAL_HAVE_XLT_CACHEATTR        0       /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
+
+#define XCHAL_MMU_ASID_BITS             8       /* number of bits in ASIDs (address space IDs) */
+#define XCHAL_MMU_ASID_INVALID          0       /* ASID value indicating invalid address space */
+#define XCHAL_MMU_ASID_KERNEL           1       /* ASID value indicating kernel (ring 0) address space */
+#define XCHAL_MMU_RINGS                 4       /* number of rings supported (1..4) */
+#define XCHAL_MMU_RING_BITS             2       /* number of bits needed to hold ring number */
+#define XCHAL_MMU_SR_BITS               0       /* number of size-restriction bits supported */
+#define XCHAL_MMU_CA_BITS               4       /* number of bits needed to hold cache attribute encoding */
+#define XCHAL_MMU_MAX_PTE_PAGE_SIZE     12      /* max page size in a PTE structure (log2) */
+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE     12      /* min page size in a PTE structure (log2) */
+
+
+/***  Instruction TLB:  ***/
+
+#define XCHAL_ITLB_WAY_BITS             3       /* number of bits holding the ways */
+#define XCHAL_ITLB_WAYS                 7       /* number of ways (n-way set-associative TLB) */
+#define XCHAL_ITLB_ARF_WAYS             4       /* number of auto-refill ways */
+#define XCHAL_ITLB_SETS                 4       /* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_ITLB_WAY0_SET             0
+#define XCHAL_ITLB_WAY1_SET             0
+#define XCHAL_ITLB_WAY2_SET             0
+#define XCHAL_ITLB_WAY3_SET             0
+#define XCHAL_ITLB_WAY4_SET             1
+#define XCHAL_ITLB_WAY5_SET             2
+#define XCHAL_ITLB_WAY6_SET             3
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_ITLB_ARF_SETS             1       /* number of auto-refill sets */
+#define XCHAL_ITLB_ARF_SET0             0       /* index of n'th auto-refill set */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_ITLB_MINWIRED_SETS        0       /* number of "min-wired" sets */
+
+
+/*  ITLB way set 0 (group of ways 0 thru 3):  */
+#define XCHAL_ITLB_SET0_WAY                     0       /* index of first way in this way set */
+#define XCHAL_ITLB_SET0_WAYS                    4       /* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET0_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET0_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET0_ARF                     1       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET0_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET0_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET0_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+/*  ITLB way set 1 (group of ways 4 thru 4):  */
+#define XCHAL_ITLB_SET1_WAY                     4       /* index of first way in this way set */
+#define XCHAL_ITLB_SET1_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET1_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET1_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET1_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET1_PAGESIZES               4       /* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET1_PAGESZ_BITS             2       /* number of bits to encode the page size */
+#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN         20      /* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX         26      /* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST        20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26       /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET1_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET1_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET1_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET1_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET1_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET1_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET1_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET1_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+/*  ITLB way set 2 (group of ways 5 thru 5):  */
+#define XCHAL_ITLB_SET2_WAY                     5       /* index of first way in this way set */
+#define XCHAL_ITLB_SET2_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET2_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET2_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET2_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET2_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET2_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN         27      /* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX         27      /* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST        27      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET2_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET2_VPN_CONSTMASK           0xF0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET2_PPN_CONSTMASK           0xF8000000      /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET2_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET2_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET2_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET2_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET2_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET2_E0_ASID_CONST           0x01
+#define XCHAL_ITLB_SET2_E1_ASID_CONST           0x01
+/*  Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET2_E0_VPN_CONST            0xD0000000
+#define XCHAL_ITLB_SET2_E1_VPN_CONST            0xD8000000
+/*  Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET2_E0_PPN_CONST            0x00000000
+#define XCHAL_ITLB_SET2_E1_PPN_CONST            0x00000000
+/*  Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET2_E0_CA_CONST             0x07
+#define XCHAL_ITLB_SET2_E1_CA_CONST             0x03
+
+/*  ITLB way set 3 (group of ways 6 thru 6):  */
+#define XCHAL_ITLB_SET3_WAY                     6       /* index of first way in this way set */
+#define XCHAL_ITLB_SET3_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET3_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET3_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET3_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET3_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET3_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN         28      /* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX         28      /* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST        28      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET3_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET3_VPN_CONSTMASK           0xE0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET3_PPN_CONSTMASK           0xF0000000      /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET3_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET3_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET3_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET3_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET3_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET3_E0_ASID_CONST           0x01
+#define XCHAL_ITLB_SET3_E1_ASID_CONST           0x01
+/*  Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET3_E0_VPN_CONST            0xE0000000
+#define XCHAL_ITLB_SET3_E1_VPN_CONST            0xF0000000
+/*  Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET3_E0_PPN_CONST            0xF0000000
+#define XCHAL_ITLB_SET3_E1_PPN_CONST            0xF0000000
+/*  Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET3_E0_CA_CONST             0x07
+#define XCHAL_ITLB_SET3_E1_CA_CONST             0x03
+
+/*  Indexing macros:  */
+#define _XCHAL_ITLB_SET(n,_what)        XCHAL_ITLB_SET ## n ## _what
+#define XCHAL_ITLB_SET(n,what)          _XCHAL_ITLB_SET(n, _ ## what )
+#define _XCHAL_ITLB_SET_E(n,i,_what)    XCHAL_ITLB_SET ## n ## _E ## i ## _what
+#define XCHAL_ITLB_SET_E(n,i,what)      _XCHAL_ITLB_SET_E(n,i, _ ## what )
+/*
+ *  Example use:  XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ *      to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+
+/***  Data TLB:  ***/
+
+#define XCHAL_DTLB_WAY_BITS             4       /* number of bits holding the ways */
+#define XCHAL_DTLB_WAYS                 10      /* number of ways (n-way set-associative TLB) */
+#define XCHAL_DTLB_ARF_WAYS             4       /* number of auto-refill ways */
+#define XCHAL_DTLB_SETS                 5       /* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_DTLB_WAY0_SET             0
+#define XCHAL_DTLB_WAY1_SET             0
+#define XCHAL_DTLB_WAY2_SET             0
+#define XCHAL_DTLB_WAY3_SET             0
+#define XCHAL_DTLB_WAY4_SET             1
+#define XCHAL_DTLB_WAY5_SET             2
+#define XCHAL_DTLB_WAY6_SET             3
+#define XCHAL_DTLB_WAY7_SET             4
+#define XCHAL_DTLB_WAY8_SET             4
+#define XCHAL_DTLB_WAY9_SET             4
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_DTLB_ARF_SETS             1       /* number of auto-refill sets */
+#define XCHAL_DTLB_ARF_SET0             0       /* index of n'th auto-refill set */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_DTLB_MINWIRED_SETS        1       /* number of "min-wired" sets */
+#define XCHAL_DTLB_MINWIRED_SET0        4       /* index of n'th "min-wired" set */
+
+
+/*  DTLB way set 0 (group of ways 0 thru 3):  */
+#define XCHAL_DTLB_SET0_WAY                     0       /* index of first way in this way set */
+#define XCHAL_DTLB_SET0_WAYS                    4       /* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET0_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET0_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET0_ARF                     1       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET0_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET0_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET0_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+/*  DTLB way set 1 (group of ways 4 thru 4):  */
+#define XCHAL_DTLB_SET1_WAY                     4       /* index of first way in this way set */
+#define XCHAL_DTLB_SET1_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET1_ENTRIES_LOG2            2       /* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET1_ENTRIES                 4       /* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET1_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET1_PAGESIZES               4       /* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET1_PAGESZ_BITS             2       /* number of bits to encode the page size */
+#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN         20      /* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX         26      /* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST        20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26       /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET1_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET1_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET1_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET1_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET1_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET1_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET1_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET1_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+/*  DTLB way set 2 (group of ways 5 thru 5):  */
+#define XCHAL_DTLB_SET2_WAY                     5       /* index of first way in this way set */
+#define XCHAL_DTLB_SET2_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET2_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET2_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET2_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET2_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET2_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN         27      /* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX         27      /* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST        27      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET2_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET2_VPN_CONSTMASK           0xF0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET2_PPN_CONSTMASK           0xF8000000      /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET2_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET2_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET2_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET2_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET2_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET2_E0_ASID_CONST           0x01
+#define XCHAL_DTLB_SET2_E1_ASID_CONST           0x01
+/*  Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET2_E0_VPN_CONST            0xD0000000
+#define XCHAL_DTLB_SET2_E1_VPN_CONST            0xD8000000
+/*  Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET2_E0_PPN_CONST            0x00000000
+#define XCHAL_DTLB_SET2_E1_PPN_CONST            0x00000000
+/*  Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET2_E0_CA_CONST             0x07
+#define XCHAL_DTLB_SET2_E1_CA_CONST             0x03
+
+/*  DTLB way set 3 (group of ways 6 thru 6):  */
+#define XCHAL_DTLB_SET3_WAY                     6       /* index of first way in this way set */
+#define XCHAL_DTLB_SET3_WAYS                    1       /* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET3_ENTRIES_LOG2            1       /* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET3_ENTRIES                 2       /* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET3_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET3_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET3_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN         28      /* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX         28      /* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST        28      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET3_ASID_CONSTMASK          0xFF    /* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET3_VPN_CONSTMASK           0xE0000000      /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET3_PPN_CONSTMASK           0xF0000000      /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET3_CA_CONSTMASK            0x0000000F      /* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET3_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET3_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET3_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET3_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET3_E0_ASID_CONST           0x01
+#define XCHAL_DTLB_SET3_E1_ASID_CONST           0x01
+/*  Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET3_E0_VPN_CONST            0xE0000000
+#define XCHAL_DTLB_SET3_E1_VPN_CONST            0xF0000000
+/*  Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET3_E0_PPN_CONST            0xF0000000
+#define XCHAL_DTLB_SET3_E1_PPN_CONST            0xF0000000
+/*  Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET3_E0_CA_CONST             0x07
+#define XCHAL_DTLB_SET3_E1_CA_CONST             0x03
+
+/*  DTLB way set 4 (group of ways 7 thru 9):  */
+#define XCHAL_DTLB_SET4_WAY                     7       /* index of first way in this way set */
+#define XCHAL_DTLB_SET4_WAYS                    3       /* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET4_ENTRIES_LOG2            0       /* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET4_ENTRIES                 1       /* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET4_ARF                     0       /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET4_PAGESIZES               1       /* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET4_PAGESZ_BITS             0       /* number of bits to encode the page size */
+#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN         12      /* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX         12      /* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST        12      /* list of log2(page size)s, separated by XCHAL_SEP;
+                                                           2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET4_ASID_CONSTMASK          0       /* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET4_VPN_CONSTMASK           0       /* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET4_PPN_CONSTMASK           0       /* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET4_CA_CONSTMASK            0       /* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET4_ASID_RESET              0       /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET4_VPN_RESET               0       /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET4_PPN_RESET               0       /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET4_CA_RESET                0       /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+/*  Indexing macros:  */
+#define _XCHAL_DTLB_SET(n,_what)        XCHAL_DTLB_SET ## n ## _what
+#define XCHAL_DTLB_SET(n,what)          _XCHAL_DTLB_SET(n, _ ## what )
+#define _XCHAL_DTLB_SET_E(n,i,_what)    XCHAL_DTLB_SET ## n ## _E ## i ## _what
+#define XCHAL_DTLB_SET_E(n,i,what)      _XCHAL_DTLB_SET_E(n,i, _ ## what )
+/*
+ *  Example use:  XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
+ *      to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+
+/*
+ *  Determine whether we have a full MMU (with Page Table and Protection)
+ *  usable for an MMU-based OS:
+ */
+#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
+# define XCHAL_HAVE_PTP_MMU             1       /* have full MMU (with page table [autorefill] and protection) */
+#else
+# define XCHAL_HAVE_PTP_MMU             0       /* don't have full MMU */
+#endif
+
+/*
+ *  For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
+ */
+#if XCHAL_HAVE_PTP_MMU
+#define XCHAL_KSEG_CACHED_VADDR         0xD0000000      /* virt.addr of kernel RAM cached static map */
+#define XCHAL_KSEG_CACHED_PADDR         0x00000000      /* phys.addr of kseg_cached */
+#define XCHAL_KSEG_CACHED_SIZE          0x08000000      /* size in bytes of kseg_cached (assumed power of 2!!!) */
+#define XCHAL_KSEG_BYPASS_VADDR         0xD8000000      /* virt.addr of kernel RAM bypass (uncached) static map */
+#define XCHAL_KSEG_BYPASS_PADDR         0x00000000      /* phys.addr of kseg_bypass */
+#define XCHAL_KSEG_BYPASS_SIZE          0x08000000      /* size in bytes of kseg_bypass (assumed power of 2!!!) */
+
+#define XCHAL_KIO_CACHED_VADDR          0xE0000000      /* virt.addr of kernel I/O cached static map */
+#define XCHAL_KIO_CACHED_PADDR          0xF0000000      /* phys.addr of kio_cached */
+#define XCHAL_KIO_CACHED_SIZE           0x10000000      /* size in bytes of kio_cached (assumed power of 2!!!) */
+#define XCHAL_KIO_BYPASS_VADDR          0xF0000000      /* virt.addr of kernel I/O bypass (uncached) static map */
+#define XCHAL_KIO_BYPASS_PADDR          0xF0000000      /* phys.addr of kio_bypass */
+#define XCHAL_KIO_BYPASS_SIZE           0x10000000      /* size in bytes of kio_bypass (assumed power of 2!!!) */
+
+#define XCHAL_SEG_MAPPABLE_VADDR        0x00000000      /* start of largest non-static-mapped virtual addr area */
+#define XCHAL_SEG_MAPPABLE_SIZE         0xD0000000      /* size in bytes of  "  */
+/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size.  */
+#endif
+
+
+/*----------------------------------------------------------------------
+                                MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES   4       /* number of write buffer entries */
+
+#define XCHAL_CORE_ID                   "linux_be"      /* configuration's alphanumeric core identifier
+                                                           (CoreID) set in the Xtensa Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID           0x00003256      /* software build-unique ID (22-bit) */
+
+/*  These definitions describe the hardware targeted by this software:  */
+#define XCHAL_HW_CONFIGID0              0xC103D1FF      /* config ID reg 0 value (upper 32 of 64 bits) */
+#define XCHAL_HW_CONFIGID1              0x00803256      /* config ID reg 1 value (lower 32 of 64 bits) */
+#define XCHAL_CONFIGID0                 XCHAL_HW_CONFIGID0      /* for backward compatibility only -- don't use! */
+#define XCHAL_CONFIGID1                 XCHAL_HW_CONFIGID1      /* for backward compatibility only -- don't use! */
+#define XCHAL_HW_RELEASE_MAJOR          1050    /* major release of targeted hardware */
+#define XCHAL_HW_RELEASE_MINOR          1       /* minor release of targeted hardware */
+#define XCHAL_HW_RELEASE_NAME           "T1050.1"       /* full release name of targeted hardware */
+#define XTHAL_HW_REL_T1050      1
+#define XTHAL_HW_REL_T1050_1    1
+#define XCHAL_HW_CONFIGID_RELIABLE      1
+
+
+/*
+ *  Miscellaneous special register fields:
+ */
+
+
+/*  DBREAKC (special register number 160):  */
+#define XCHAL_DBREAKC_VALIDMASK 0xC000003F      /* bits of DBREAKC that are defined */
+/*  MASK field:  */
+#define XCHAL_DBREAKC_MASK_BITS         6               /* number of bits in MASK field */
+#define XCHAL_DBREAKC_MASK_NUM          64              /* max number of possible causes (2^bits) */
+#define XCHAL_DBREAKC_MASK_SHIFT        0               /* position of MASK bits in DBREAKC, starting from lsbit */
+#define XCHAL_DBREAKC_MASK_MASK         0x0000003F      /* mask of bits in MASK field of DBREAKC */
+/*  LOADBREAK field:  */
+#define XCHAL_DBREAKC_LOADBREAK_BITS    1               /* number of bits in LOADBREAK field */
+#define XCHAL_DBREAKC_LOADBREAK_NUM     2               /* max number of possible causes (2^bits) */
+#define XCHAL_DBREAKC_LOADBREAK_SHIFT   30              /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
+#define XCHAL_DBREAKC_LOADBREAK_MASK    0x40000000      /* mask of bits in LOADBREAK field of DBREAKC */
+/*  STOREBREAK field:  */
+#define XCHAL_DBREAKC_STOREBREAK_BITS   1               /* number of bits in STOREBREAK field */
+#define XCHAL_DBREAKC_STOREBREAK_NUM    2               /* max number of possible causes (2^bits) */
+#define XCHAL_DBREAKC_STOREBREAK_SHIFT  31              /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
+#define XCHAL_DBREAKC_STOREBREAK_MASK   0x80000000      /* mask of bits in STOREBREAK field of DBREAKC */
+
+/*  PS (special register number 230):  */
+#define XCHAL_PS_VALIDMASK      0x00070FFF      /* bits of PS that are defined */
+/*  INTLEVEL field:  */
+#define XCHAL_PS_INTLEVEL_BITS  4               /* number of bits in INTLEVEL field */
+#define XCHAL_PS_INTLEVEL_NUM   16              /* max number of possible causes (2^bits) */
+#define XCHAL_PS_INTLEVEL_SHIFT 0               /* position of INTLEVEL bits in PS, starting from lsbit */
+#define XCHAL_PS_INTLEVEL_MASK  0x0000000F      /* mask of bits in INTLEVEL field of PS */
+/*  EXCM field:  */
+#define XCHAL_PS_EXCM_BITS      1               /* number of bits in EXCM field */
+#define XCHAL_PS_EXCM_NUM       2               /* max number of possible causes (2^bits) */
+#define XCHAL_PS_EXCM_SHIFT     4               /* position of EXCM bits in PS, starting from lsbit */
+#define XCHAL_PS_EXCM_MASK      0x00000010      /* mask of bits in EXCM field of PS */
+/*  PROGSTACK field:  */
+#define XCHAL_PS_PROGSTACK_BITS         1               /* number of bits in PROGSTACK field */
+#define XCHAL_PS_PROGSTACK_NUM          2               /* max number of possible causes (2^bits) */
+#define XCHAL_PS_PROGSTACK_SHIFT        5               /* position of PROGSTACK bits in PS, starting from lsbit */
+#define XCHAL_PS_PROGSTACK_MASK         0x00000020      /* mask of bits in PROGSTACK field of PS */
+/*  RING field:  */
+#define XCHAL_PS_RING_BITS      2               /* number of bits in RING field */
+#define XCHAL_PS_RING_NUM       4               /* max number of possible causes (2^bits) */
+#define XCHAL_PS_RING_SHIFT     6               /* position of RING bits in PS, starting from lsbit */
+#define XCHAL_PS_RING_MASK      0x000000C0      /* mask of bits in RING field of PS */
+/*  OWB field:  */
+#define XCHAL_PS_OWB_BITS       4               /* number of bits in OWB field */
+#define XCHAL_PS_OWB_NUM        16              /* max number of possible causes (2^bits) */
+#define XCHAL_PS_OWB_SHIFT      8               /* position of OWB bits in PS, starting from lsbit */
+#define XCHAL_PS_OWB_MASK       0x00000F00      /* mask of bits in OWB field of PS */
+/*  CALLINC field:  */
+#define XCHAL_PS_CALLINC_BITS   2               /* number of bits in CALLINC field */
+#define XCHAL_PS_CALLINC_NUM    4               /* max number of possible causes (2^bits) */
+#define XCHAL_PS_CALLINC_SHIFT  16              /* position of CALLINC bits in PS, starting from lsbit */
+#define XCHAL_PS_CALLINC_MASK   0x00030000      /* mask of bits in CALLINC field of PS */
+/*  WOE field:  */
+#define XCHAL_PS_WOE_BITS       1               /* number of bits in WOE field */
+#define XCHAL_PS_WOE_NUM        2               /* max number of possible causes (2^bits) */
+#define XCHAL_PS_WOE_SHIFT      18              /* position of WOE bits in PS, starting from lsbit */
+#define XCHAL_PS_WOE_MASK       0x00040000      /* mask of bits in WOE field of PS */
+
+/*  EXCCAUSE (special register number 232):  */
+#define XCHAL_EXCCAUSE_VALIDMASK        0x0000003F      /* bits of EXCCAUSE that are defined */
+/*  EXCCAUSE field:  */
+#define XCHAL_EXCCAUSE_BITS             6               /* number of bits in EXCCAUSE register */
+#define XCHAL_EXCCAUSE_NUM              64              /* max number of possible causes (2^bits) */
+#define XCHAL_EXCCAUSE_SHIFT            0               /* position of EXCCAUSE bits in register, starting from lsbit */
+#define XCHAL_EXCCAUSE_MASK             0x0000003F      /* mask of bits in EXCCAUSE register */
+
+/*  DEBUGCAUSE (special register number 233):  */
+#define XCHAL_DEBUGCAUSE_VALIDMASK      0x0000003F      /* bits of DEBUGCAUSE that are defined */
+/*  ICOUNT field:  */
+#define XCHAL_DEBUGCAUSE_ICOUNT_BITS    1               /* number of bits in ICOUNT field */
+#define XCHAL_DEBUGCAUSE_ICOUNT_NUM     2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT   0               /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_ICOUNT_MASK    0x00000001      /* mask of bits in ICOUNT field of DEBUGCAUSE */
+/*  IBREAK field:  */
+#define XCHAL_DEBUGCAUSE_IBREAK_BITS    1               /* number of bits in IBREAK field */
+#define XCHAL_DEBUGCAUSE_IBREAK_NUM     2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT   1               /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_IBREAK_MASK    0x00000002      /* mask of bits in IBREAK field of DEBUGCAUSE */
+/*  DBREAK field:  */
+#define XCHAL_DEBUGCAUSE_DBREAK_BITS    1               /* number of bits in DBREAK field */
+#define XCHAL_DEBUGCAUSE_DBREAK_NUM     2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT   2               /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_DBREAK_MASK    0x00000004      /* mask of bits in DBREAK field of DEBUGCAUSE */
+/*  BREAK field:  */
+#define XCHAL_DEBUGCAUSE_BREAK_BITS     1               /* number of bits in BREAK field */
+#define XCHAL_DEBUGCAUSE_BREAK_NUM      2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_BREAK_SHIFT    3               /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_BREAK_MASK     0x00000008      /* mask of bits in BREAK field of DEBUGCAUSE */
+/*  BREAKN field:  */
+#define XCHAL_DEBUGCAUSE_BREAKN_BITS    1               /* number of bits in BREAKN field */
+#define XCHAL_DEBUGCAUSE_BREAKN_NUM     2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT   4               /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_BREAKN_MASK    0x00000010      /* mask of bits in BREAKN field of DEBUGCAUSE */
+/*  DEBUGINT field:  */
+#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS  1               /* number of bits in DEBUGINT field */
+#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM   2               /* max number of possible causes (2^bits) */
+#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5               /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
+#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK  0x00000020      /* mask of bits in DEBUGINT field of DEBUGCAUSE */
+
+
+
+/*----------------------------------------------------------------------
+                                ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_DENSITY              1       /* 1 if density option configured, 0 otherwise */
+#define XCHAL_HAVE_LOOPS                1       /* 1 if zero-overhead loops option configured, 0 otherwise */
+/*  Misc instructions:  */
+#define XCHAL_HAVE_NSA                  0       /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
+#define XCHAL_HAVE_MINMAX               0       /* 1 if MIN/MAX instructions option configured, 0 otherwise */
+#define XCHAL_HAVE_SEXT                 0       /* 1 if sign-extend instruction option configured, 0 otherwise */
+#define XCHAL_HAVE_CLAMPS               0       /* 1 if CLAMPS instruction option configured, 0 otherwise */
+#define XCHAL_HAVE_MAC16                0       /* 1 if MAC16 option configured, 0 otherwise */
+#define XCHAL_HAVE_MUL16                0       /* 1 if 16-bit integer multiply option configured, 0 otherwise */
+/*#define XCHAL_HAVE_POPC               0*/     /* 1 if CRC instruction option configured, 0 otherwise */
+/*#define XCHAL_HAVE_CRC                0*/     /* 1 if POPC instruction option configured, 0 otherwise */
+
+#define XCHAL_HAVE_SPECULATION          0       /* 1 if speculation option configured, 0 otherwise */
+/*#define XCHAL_HAVE_MP_SYNC            0*/     /* 1 if multiprocessor sync. option configured, 0 otherwise */
+#define XCHAL_HAVE_PRID                 0       /* 1 if processor ID register configured, 0 otherwise */
+
+#define XCHAL_NUM_MISC_REGS             2       /* number of miscellaneous registers (0..4) */
+
+/*  These relate a bit more to TIE:  */
+#define XCHAL_HAVE_BOOLEANS             0       /* 1 if booleans option configured, 0 otherwise */
+#define XCHAL_HAVE_MUL32                0       /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+#define XCHAL_HAVE_MUL32_HIGH           0       /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+#define XCHAL_HAVE_FP                   0       /* 1 if floating point option configured, 0 otherwise */
+
+
+/*----------------------------------------------------------------------
+                                DERIVED
+  ----------------------------------------------------------------------*/
+
+#if XCHAL_HAVE_BE
+#define XCHAL_INST_ILLN                 0xD60F          /* 2-byte illegal instruction, msb-first */
+#define XCHAL_INST_ILLN_BYTE0           0xD6            /* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1           0x0F            /* 2-byte illegal instruction, 2nd byte */
+#else
+#define XCHAL_INST_ILLN                 0xF06D          /* 2-byte illegal instruction, lsb-first */
+#define XCHAL_INST_ILLN_BYTE0           0x6D            /* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1           0xF0            /* 2-byte illegal instruction, 2nd byte */
+#endif
+/*  Belongs in xtensa/hal.h:  */
+#define XTHAL_INST_ILL                  0x000000        /* 3-byte illegal instruction */
+
+
+/*
+ *  Because information as to exactly which hardware release is targeted
+ *  by a given software build is not always available, compile-time HAL
+ *  Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
+ */
+#ifndef XCHAL_HW_RELEASE_MAJOR
+# define XCHAL_HW_CONFIGID_RELIABLE     0
+#endif
+#if XCHAL_HW_CONFIGID_RELIABLE
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)      (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)      (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT(major,minor)               (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major)               ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
+#else
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)      ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
+                                                        : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
+                                                        : XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)      ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
+                                                        : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
+                                                        : XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT(major,minor)               ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
+                                                           ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major)               XCHAL_HW_RELEASE_AT(major,0)
+#endif
+
+/*
+ *  Specific errata:
+ */
+
+/*
+ *  Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
+ *  relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
+ */
+#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN  (XCHAL_HAVE_XEA1 && \
+                                         (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
+                                          || XCHAL_HW_RELEASE_AT(1050,0)))
+
+
+
+#endif /*XTENSA_CONFIG_CORE_H*/
+
diff --git a/include/asm-xtensa/xtensa/config-linux_be/defs.h b/include/asm-xtensa/xtensa/config-linux_be/defs.h
new file mode 100644
index 000000000000..f7c58b273371
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/defs.h
@@ -0,0 +1,270 @@
+/* Definitions for Xtensa instructions, types, and protos. */
+
+/*
+ * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_BASE_HEADER
+#define _XTENSA_BASE_HEADER
+
+#ifdef __XTENSA__
+#if defined(__GNUC__) && !defined(__XCC__)
+
+#define L8UI_ASM(arr, ars, imm) { \
+  __asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
+}
+
+#define XT_L8UI(ars, imm) \
+({ \
+  unsigned char _arr; \
+  const unsigned char *_ars = ars; \
+  L8UI_ASM(_arr, _ars, imm); \
+  _arr; \
+})
+
+#define L16UI_ASM(arr, ars, imm) { \
+  __asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
+}
+
+#define XT_L16UI(ars, imm) \
+({ \
+  unsigned short _arr; \
+  const unsigned short *_ars = ars; \
+  L16UI_ASM(_arr, _ars, imm); \
+  _arr; \
+})
+
+#define L16SI_ASM(arr, ars, imm) {\
+  __asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
+}
+
+#define XT_L16SI(ars, imm) \
+({ \
+  signed short _arr; \
+  const signed short *_ars = ars; \
+  L16SI_ASM(_arr, _ars, imm); \
+  _arr; \
+})
+
+#define L32I_ASM(arr, ars, imm) { \
+  __asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
+}
+
+#define XT_L32I(ars, imm) \
+({ \
+  unsigned _arr; \
+  const unsigned *_ars = ars; \
+  L32I_ASM(_arr, _ars, imm); \
+  _arr; \
+})
+
+#define S8I_ASM(arr, ars, imm) {\
+  __asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
+}
+
+#define XT_S8I(arr, ars, imm) \
+({ \
+  signed char _arr = arr; \
+  const signed char *_ars = ars; \
+  S8I_ASM(_arr, _ars, imm); \
+})
+
+#define S16I_ASM(arr, ars, imm) {\
+  __asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
+}
+
+#define XT_S16I(arr, ars, imm) \
+({ \
+  signed short _arr = arr; \
+  const signed short *_ars = ars; \
+  S16I_ASM(_arr, _ars, imm); \
+})
+
+#define S32I_ASM(arr, ars, imm) { \
+  __asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
+}
+
+#define XT_S32I(arr, ars, imm) \
+({ \
+  signed int _arr = arr; \
+  const signed int *_ars = ars; \
+  S32I_ASM(_arr, _ars, imm); \
+})
+
+#define ADDI_ASM(art, ars, imm) {\
+   __asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
+}
+
+#define XT_ADDI(ars, imm) \
+({ \
+   unsigned _art; \
+   unsigned _ars = ars; \
+   ADDI_ASM(_art, _ars, imm); \
+   _art; \
+})
+
+#define ABS_ASM(arr, art) {\
+   __asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
+}
+
+#define XT_ABS(art) \
+({ \
+   unsigned _arr; \
+   signed _art = art; \
+   ABS_ASM(_arr, _art); \
+   _arr; \
+})
+
+/* Note: In the following macros that reference SAR, the magic "state"
+   register is used to capture the dependency on SAR.  This is because
+   SAR is a 5-bit register and thus there are no C types that can be
+   used to represent it.  It doesn't appear that the SAR register is
+   even relevant to GCC, but it is marked as "clobbered" just in
+   case.  */
+
+#define SRC_ASM(arr, ars, art) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("src %0, %1, %2" \
+            : "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
+}
+
+#define XT_SRC(ars, art) \
+({ \
+   unsigned _arr; \
+   unsigned _ars = ars; \
+   unsigned _art = art; \
+   SRC_ASM(_arr, _ars, _art); \
+   _arr; \
+})
+
+#define SSR_ASM(ars) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
+}
+
+#define XT_SSR(ars) \
+({ \
+   unsigned _ars = ars; \
+   SSR_ASM(_ars); \
+})
+
+#define SSL_ASM(ars) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
+}
+
+#define XT_SSL(ars) \
+({ \
+   unsigned _ars = ars; \
+   SSL_ASM(_ars); \
+})
+
+#define SSA8B_ASM(ars) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
+}
+
+#define XT_SSA8B(ars) \
+({ \
+   unsigned _ars = ars; \
+   SSA8B_ASM(_ars); \
+})
+
+#define SSA8L_ASM(ars) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
+}
+
+#define XT_SSA8L(ars) \
+({ \
+   unsigned _ars = ars; \
+   SSA8L_ASM(_ars); \
+})
+
+#define SSAI_ASM(imm) {\
+   register int _xt_sar __asm__ ("state"); \
+   __asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
+}
+
+#define XT_SSAI(imm) \
+({ \
+   SSAI_ASM(imm); \
+})
+
+
+
+
+
+
+
+
+#endif /* __GNUC__ && !__XCC__ */
+
+#ifdef __XCC__
+
+/* Core load/store instructions */
+extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
+extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
+extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
+extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
+extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
+extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
+extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
+
+#define XT_L8UI  _TIE_L8UI
+#define XT_L16UI _TIE_L16UI
+#define XT_L16SI _TIE_L16SI
+#define XT_L32I  _TIE_L32I
+#define XT_S8I   _TIE_S8I
+#define XT_S16I  _TIE_S16I
+#define XT_S32I  _TIE_S32I
+
+/* Add-immediate instruction */
+extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
+#define XT_ADDI  _TIE_ADDI
+
+/* Absolute value instruction */
+extern unsigned _TIE_ABS(int art);
+#define XT_ABS _TIE_ABS
+
+/* funnel shift instructions */
+extern unsigned _TIE_SRC(unsigned ars, unsigned art);
+#define XT_SRC _TIE_SRC
+extern void _TIE_SSR(unsigned ars);
+#define XT_SSR _TIE_SSR
+extern void _TIE_SSL(unsigned ars);
+#define XT_SSL _TIE_SSL
+extern void _TIE_SSA8B(unsigned ars);
+#define XT_SSA8B _TIE_SSA8B
+extern void _TIE_SSA8L(unsigned ars);
+#define XT_SSA8L _TIE_SSA8L
+extern void _TIE_SSAI(immediate imm);
+#define XT_SSAI _TIE_SSAI
+
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_BASE_HEADER */
diff --git a/include/asm-xtensa/xtensa/config-linux_be/specreg.h b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
new file mode 100644
index 000000000000..fa4106aa9a02
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
@@ -0,0 +1,99 @@
+/*
+ * Xtensa Special Register symbolic names
+ */
+
+/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
+
+/*
+ * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+#ifndef XTENSA_SPECREG_H
+#define XTENSA_SPECREG_H
+
+/*  Include these special register bitfield definitions, for historical reasons:  */
+#include <xtensa/corebits.h>
+
+
+/*  Special registers:  */
+#define LBEG            0
+#define LEND            1
+#define LCOUNT          2
+#define SAR             3
+#define WINDOWBASE      72
+#define WINDOWSTART     73
+#define PTEVADDR        83
+#define RASID           90
+#define ITLBCFG         91
+#define DTLBCFG         92
+#define IBREAKENABLE    96
+#define DDR             104
+#define IBREAKA_0       128
+#define IBREAKA_1       129
+#define DBREAKA_0       144
+#define DBREAKA_1       145
+#define DBREAKC_0       160
+#define DBREAKC_1       161
+#define EPC_1           177
+#define EPC_2           178
+#define EPC_3           179
+#define EPC_4           180
+#define DEPC            192
+#define EPS_2           194
+#define EPS_3           195
+#define EPS_4           196
+#define EXCSAVE_1       209
+#define EXCSAVE_2       210
+#define EXCSAVE_3       211
+#define EXCSAVE_4       212
+#define INTERRUPT       226
+#define INTENABLE       228
+#define PS              230
+#define EXCCAUSE        232
+#define DEBUGCAUSE      233
+#define CCOUNT          234
+#define ICOUNT          236
+#define ICOUNTLEVEL     237
+#define EXCVADDR        238
+#define CCOMPARE_0      240
+#define CCOMPARE_1      241
+#define CCOMPARE_2      242
+#define MISC_REG_0      244
+#define MISC_REG_1      245
+
+/*  Special cases (bases of special register series):  */
+#define IBREAKA         128
+#define DBREAKA         144
+#define DBREAKC         160
+#define EPC             176
+#define EPS             192
+#define EXCSAVE         208
+#define CCOMPARE        240
+
+/*  Special names for read-only and write-only interrupt registers:  */
+#define INTREAD         226
+#define INTSET          226
+#define INTCLEAR        227
+
+#endif /* XTENSA_SPECREG_H */
+
diff --git a/include/asm-xtensa/xtensa/config-linux_be/system.h b/include/asm-xtensa/xtensa/config-linux_be/system.h
new file mode 100644
index 000000000000..cf9d4d308e3a
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/system.h
@@ -0,0 +1,198 @@
+/*
+ * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
+ *
+ *  NOTE: The location and contents of this file are highly subject to change.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  The HAL itself has historically included this file in some instances,
+ *  but this is not appropriate either, because the HAL is meant to be
+ *  core-specific but system independent.
+ */
+
+/*
+ * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+
+#ifndef XTENSA_CONFIG_SYSTEM_H
+#define XTENSA_CONFIG_SYSTEM_H
+
+/*#include <xtensa/hal.h>*/
+
+
+
+/*----------------------------------------------------------------------
+                                DEVICE ADDRESSES
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Strange place to find these, but the configuration GUI
+ *  allows moving these around to account for various core
+ *  configurations.  Specific boards (and their BSP software)
+ *  will have specific meanings for these components.
+ */
+
+/*  I/O Block areas:  */
+#define XSHAL_IOBLOCK_CACHED_VADDR      0xE0000000
+#define XSHAL_IOBLOCK_CACHED_PADDR      0xF0000000
+#define XSHAL_IOBLOCK_CACHED_SIZE       0x0E000000
+
+#define XSHAL_IOBLOCK_BYPASS_VADDR      0xF0000000
+#define XSHAL_IOBLOCK_BYPASS_PADDR      0xF0000000
+#define XSHAL_IOBLOCK_BYPASS_SIZE       0x0E000000
+
+/*  System ROM:  */
+#define XSHAL_ROM_VADDR         0xEE000000
+#define XSHAL_ROM_PADDR         0xFE000000
+#define XSHAL_ROM_SIZE          0x00400000
+/*  Largest available area (free of vectors):  */
+#define XSHAL_ROM_AVAIL_VADDR   0xEE00052C
+#define XSHAL_ROM_AVAIL_VSIZE   0x003FFAD4
+
+/*  System RAM:  */
+#define XSHAL_RAM_VADDR         0xD0000000
+#define XSHAL_RAM_PADDR         0x00000000
+#define XSHAL_RAM_VSIZE         0x08000000
+#define XSHAL_RAM_PSIZE         0x10000000
+#define XSHAL_RAM_SIZE          XSHAL_RAM_PSIZE
+/*  Largest available area (free of vectors):  */
+#define XSHAL_RAM_AVAIL_VADDR   0xD0000370
+#define XSHAL_RAM_AVAIL_VSIZE   0x07FFFC90
+
+/*
+ *  Shadow system RAM (same device as system RAM, at different address).
+ *  (Emulation boards need this for the SONIC Ethernet driver
+ *   when data caches are configured for writeback mode.)
+ *  NOTE: on full MMU configs, this points to the BYPASS virtual address
+ *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
+ *  addresses are viewed through the BYPASS static map rather than
+ *  the CACHED static map.
+ */
+#define XSHAL_RAM_BYPASS_VADDR          0xD8000000
+#define XSHAL_RAM_BYPASS_PADDR          0x00000000
+#define XSHAL_RAM_BYPASS_PSIZE          0x08000000
+
+/*  Alternate system RAM (different device than system RAM):  */
+#define XSHAL_ALTRAM_VADDR              0xCEE00000
+#define XSHAL_ALTRAM_PADDR              0xC0000000
+#define XSHAL_ALTRAM_SIZE               0x00200000
+
+
+/*----------------------------------------------------------------------
+ *                      DEVICE-ADDRESS DEPENDENT...
+ *
+ *  Values written to CACHEATTR special register (or its equivalent)
+ *  to enable and disable caches in various modes.
+ *----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+                        BACKWARD COMPATIBILITY ...
+  ----------------------------------------------------------------------*/
+
+/*
+ *  NOTE:  the following two macros are DEPRECATED.  Use the latter
+ *  board-specific macros instead, which are specially tuned for the
+ *  particular target environments' memory maps.
+ */
+#define XSHAL_CACHEATTR_BYPASS          XSHAL_XT2000_CACHEATTR_BYPASS   /* disable caches in bypass mode */
+#define XSHAL_CACHEATTR_DEFAULT         XSHAL_XT2000_CACHEATTR_DEFAULT  /* default setting to enable caches (no writeback!) */
+
+/*----------------------------------------------------------------------
+                        ISS (Instruction Set Simulator) SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_ISS_CACHEATTR_WRITEBACK   0x1122222F      /* enable caches in write-back mode */
+#define XSHAL_ISS_CACHEATTR_WRITEALLOC  0x1122222F      /* enable caches in write-allocate mode */
+#define XSHAL_ISS_CACHEATTR_WRITETHRU   0x1122222F      /* enable caches in write-through mode */
+#define XSHAL_ISS_CACHEATTR_BYPASS      0x2222222F      /* disable caches in bypass mode */
+#define XSHAL_ISS_CACHEATTR_DEFAULT     XSHAL_ISS_CACHEATTR_WRITEBACK   /* default setting to enable caches */
+
+/*  For Coware only:  */
+#define XSHAL_COWARE_CACHEATTR_WRITEBACK        0x11222222      /* enable caches in write-back mode */
+#define XSHAL_COWARE_CACHEATTR_WRITEALLOC       0x11222222      /* enable caches in write-allocate mode */
+#define XSHAL_COWARE_CACHEATTR_WRITETHRU        0x11222222      /* enable caches in write-through mode */
+#define XSHAL_COWARE_CACHEATTR_BYPASS           0x22222222      /* disable caches in bypass mode */
+#define XSHAL_COWARE_CACHEATTR_DEFAULT          XSHAL_COWARE_CACHEATTR_WRITEBACK        /* default setting to enable caches */
+
+/*  For BFM and other purposes:  */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK      0x11222222      /* enable caches without any invalid regions */
+#define XSHAL_ALLVALID_CACHEATTR_DEFAULT        XSHAL_ALLVALID_CACHEATTR_WRITEBACK      /* default setting for caches without any invalid regions */
+
+#define XSHAL_ISS_PIPE_REGIONS  0
+#define XSHAL_ISS_SDRAM_REGIONS 0
+
+
+/*----------------------------------------------------------------------
+                        XT2000 BOARD SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_XT2000_CACHEATTR_WRITEBACK        0x22FFFFFF      /* enable caches in write-back mode */
+#define XSHAL_XT2000_CACHEATTR_WRITEALLOC       0x22FFFFFF      /* enable caches in write-allocate mode */
+#define XSHAL_XT2000_CACHEATTR_WRITETHRU        0x22FFFFFF      /* enable caches in write-through mode */
+#define XSHAL_XT2000_CACHEATTR_BYPASS           0x22FFFFFF      /* disable caches in bypass mode */
+#define XSHAL_XT2000_CACHEATTR_DEFAULT          XSHAL_XT2000_CACHEATTR_WRITEBACK        /* default setting to enable caches */
+
+#define XSHAL_XT2000_PIPE_REGIONS       0x00001000      /* BusInt pipeline regions */
+#define XSHAL_XT2000_SDRAM_REGIONS      0x00000005      /* BusInt SDRAM regions */
+
+
+/*----------------------------------------------------------------------
+                                VECTOR SIZES
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Sizes allocated to vectors by the system (memory map) configuration.
+ *  These sizes are constrained by core configuration (eg. one vector's
+ *  code cannot overflow into another vector) but are dependent on the
+ *  system or board (or LSP) memory map configuration.
+ *
+ *  Whether or not each vector happens to be in a system ROM is also
+ *  a system configuration matter, sometimes useful, included here also:
+ */
+#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
+#define XSHAL_RESET_VECTOR_ISROM        1
+#define XSHAL_USER_VECTOR_SIZE  0x0000001C
+#define XSHAL_USER_VECTOR_ISROM 0
+#define XSHAL_PROGRAMEXC_VECTOR_SIZE    XSHAL_USER_VECTOR_SIZE  /* for backward compatibility */
+#define XSHAL_USEREXC_VECTOR_SIZE       XSHAL_USER_VECTOR_SIZE  /* for backward compatibility */
+#define XSHAL_KERNEL_VECTOR_SIZE        0x0000001C
+#define XSHAL_KERNEL_VECTOR_ISROM       0
+#define XSHAL_STACKEDEXC_VECTOR_SIZE    XSHAL_KERNEL_VECTOR_SIZE        /* for backward compatibility */
+#define XSHAL_KERNELEXC_VECTOR_SIZE     XSHAL_KERNEL_VECTOR_SIZE        /* for backward compatibility */
+#define XSHAL_DOUBLEEXC_VECTOR_SIZE     0x000000E0
+#define XSHAL_DOUBLEEXC_VECTOR_ISROM    0
+#define XSHAL_WINDOW_VECTORS_SIZE       0x00000180
+#define XSHAL_WINDOW_VECTORS_ISROM      0
+#define XSHAL_INTLEVEL2_VECTOR_SIZE     0x0000000C
+#define XSHAL_INTLEVEL2_VECTOR_ISROM    0
+#define XSHAL_INTLEVEL3_VECTOR_SIZE     0x0000000C
+#define XSHAL_INTLEVEL3_VECTOR_ISROM    0
+#define XSHAL_INTLEVEL4_VECTOR_SIZE     0x0000000C
+#define XSHAL_INTLEVEL4_VECTOR_ISROM    1
+#define XSHAL_DEBUG_VECTOR_SIZE         XSHAL_INTLEVEL4_VECTOR_SIZE
+#define XSHAL_DEBUG_VECTOR_ISROM        XSHAL_INTLEVEL4_VECTOR_ISROM
+
+
+#endif /*XTENSA_CONFIG_SYSTEM_H*/
+
diff --git a/include/asm-xtensa/xtensa/config-linux_be/tie.h b/include/asm-xtensa/xtensa/config-linux_be/tie.h
new file mode 100644
index 000000000000..3c2e514602f4
--- /dev/null
+++ b/include/asm-xtensa/xtensa/config-linux_be/tie.h
@@ -0,0 +1,275 @@
+/*
+ * xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
+ *
+ *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
+ *  It was generated for a specific Xtensa processor configuration,
+ *  and furthermore for a specific set of TIE source files that extend
+ *  basic core functionality.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  It is perfectly normal, however, for the HAL source itself to include this file.
+ */
+
+/*
+ * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2.1 of the GNU Lesser General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Further, this software is distributed without any warranty that it is
+ * free of the rightful claim of any third person regarding infringement
+ * or the like.  Any license provided herein, whether implied or
+ * otherwise, applies only to this software file.  Patent licenses, if
+ * any, provided herein do not apply to combinations of this program with
+ * other software, or any other product whatsoever.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this program; if not, write the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
+ * USA.
+ */
+
+
+#ifndef XTENSA_CONFIG_TIE_H
+#define XTENSA_CONFIG_TIE_H
+
+#include <xtensa/hal.h>
+
+
+/*----------------------------------------------------------------------
+                                GENERAL
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Separators for macros that expand into arrays.
+ *  These can be predefined by files that #include this one,
+ *  when different separators are required.
+ */
+/*  Element separator for macros that expand into 1-dimensional arrays:  */
+#ifndef XCHAL_SEP
+#define XCHAL_SEP                       ,
+#endif
+/*  Array separator for macros that expand into 2-dimensional arrays:  */
+#ifndef XCHAL_SEP2
+#define XCHAL_SEP2                      },{
+#endif
+
+
+
+
+
+
+/*----------------------------------------------------------------------
+                        COPROCESSORS and EXTRA STATE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_CP_NUM                    0       /* number of coprocessors */
+#define XCHAL_CP_MAX                    0       /* max coprocessor id plus one (0 if none) */
+#define XCHAL_CP_MASK                   0x00    /* bitmask of coprocessors by id */
+
+/*  Space for coprocessors' state save areas:  */
+#define XCHAL_CP0_SA_SIZE               0
+#define XCHAL_CP1_SA_SIZE               0
+#define XCHAL_CP2_SA_SIZE               0
+#define XCHAL_CP3_SA_SIZE               0
+#define XCHAL_CP4_SA_SIZE               0
+#define XCHAL_CP5_SA_SIZE               0
+#define XCHAL_CP6_SA_SIZE               0
+#define XCHAL_CP7_SA_SIZE               0
+/*  Minimum required alignments of CP state save areas:  */
+#define XCHAL_CP0_SA_ALIGN              1
+#define XCHAL_CP1_SA_ALIGN              1
+#define XCHAL_CP2_SA_ALIGN              1
+#define XCHAL_CP3_SA_ALIGN              1
+#define XCHAL_CP4_SA_ALIGN              1
+#define XCHAL_CP5_SA_ALIGN              1
+#define XCHAL_CP6_SA_ALIGN              1
+#define XCHAL_CP7_SA_ALIGN              1
+
+/*  Indexing macros:  */
+#define _XCHAL_CP_SA_SIZE(n)            XCHAL_CP ## n ## _SA_SIZE
+#define XCHAL_CP_SA_SIZE(n)             _XCHAL_CP_SA_SIZE(n)    /* n = 0 .. 7 */
+#define _XCHAL_CP_SA_ALIGN(n)           XCHAL_CP ## n ## _SA_ALIGN
+#define XCHAL_CP_SA_ALIGN(n)            _XCHAL_CP_SA_ALIGN(n)   /* n = 0 .. 7 */
+
+
+/*  Space for "extra" state (user special registers and non-cp TIE) save area:  */
+#define XCHAL_EXTRA_SA_SIZE             0
+#define XCHAL_EXTRA_SA_ALIGN            1
+
+/*  Total save area size (extra + all coprocessors)  */
+/*  (not useful until xthal_{save,restore}_all_extra() is implemented,  */
+/*   but included for Tor2 beta; doesn't account for alignment!):  */
+#define XCHAL_CPEXTRA_SA_SIZE_TOR2      0       /* Tor2Beta temporary definition -- do not use */
+
+/*  Combined required alignment for all CP and EXTRA state save areas  */
+/*  (does not include required alignment for any base config registers):  */
+#define XCHAL_CPEXTRA_SA_ALIGN          1
+
+/* ... */
+
+
+#ifdef _ASMLANGUAGE
+/*
+ *  Assembly-language specific definitions (assembly macros, etc.).
+ */
+#include <xtensa/config/specreg.h>
+
+/********************
+ *  Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
+ */
+
+/* (none) */
+
+
+/********************
+ *  Macros to create functions that save and restore all EXTRA (non-coprocessor) state
+ *  (does not include zero-overhead loop registers and non-optional registers).
+ */
+
+        /*
+         *  Macro that expands to the body of a function that
+         *  stores the extra (non-coprocessor) optional/custom state.
+         *      Entry:  a2 = ptr to save area in which to save extra state
+         *      Exit:   any register a2-a15 (?) may have been clobbered.
+         */
+        .macro  xchal_extra_store_funcbody
+        .endm
+
+
+        /*
+         *  Macro that expands to the body of a function that
+         *  loads the extra (non-coprocessor) optional/custom state.
+         *      Entry:  a2 = ptr to save area from which to restore extra state
+         *      Exit:   any register a2-a15 (?) may have been clobbered.
+         */
+        .macro  xchal_extra_load_funcbody
+        .endm
+
+
+/********************
+ *  Macros to save and restore the state of each TIE coprocessor.
+ */
+
+
+
+/********************
+ *  Macros to create functions that save and restore the state of *any* TIE coprocessor.
+ */
+
+        /*
+         *  Macro that expands to the body of a function
+         *  that stores the selected coprocessor's state (registers etc).
+         *      Entry:  a2 = ptr to save area in which to save cp state
+         *              a3 = coprocessor number
+         *      Exit:   any register a2-a15 (?) may have been clobbered.
+         */
+        .macro  xchal_cpi_store_funcbody
+        .endm
+
+
+        /*
+         *  Macro that expands to the body of a function
+         *  that loads the selected coprocessor's state (registers etc).
+         *      Entry:  a2 = ptr to save area from which to restore cp state
+         *              a3 = coprocessor number
+         *      Exit:   any register a2-a15 (?) may have been clobbered.
+         */
+        .macro  xchal_cpi_load_funcbody
+        .endm
+
+#endif /*_ASMLANGUAGE*/
+
+
+/*
+ *  Contents of save areas in terms of libdb register numbers.
+ *  NOTE:  CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
+ *  it is up to the user of this header file to define these macros
+ *  usefully before each expansion of the CONTENTS_LIBDB macros.
+ *  (Fields rsv[123] are reserved for future additions; they are currently
+ *   set to zero but may be set to some useful values in the future.)
+ *
+ *      CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
+ *      CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
+ *      CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
+ */
+
+#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM       0
+#define XCHAL_EXTRA_SA_CONTENTS_LIBDB   /* empty */
+
+#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP0_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP1_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP2_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP3_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP4_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP5_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP6_SA_CONTENTS_LIBDB     /* empty */
+
+#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
+#define XCHAL_CP7_SA_CONTENTS_LIBDB     /* empty */
+
+
+
+
+
+
+/*----------------------------------------------------------------------
+                                MISC
+  ----------------------------------------------------------------------*/
+
+#if 0   /* is there something equivalent for user TIE? */
+#define XCHAL_CORE_ID                   "linux_be"      /* configuration's alphanumeric core identifier
+                                                           (CoreID) set in the Xtensa Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID           0x00003256      /* software build-unique ID (22-bit) */
+
+/*  These definitions describe the hardware targeted by this software:  */
+#define XCHAL_HW_CONFIGID0              0xC103D1FF      /* config ID reg 0 value (upper 32 of 64 bits) */
+#define XCHAL_HW_CONFIGID1              0x00803256      /* config ID reg 1 value (lower 32 of 64 bits) */
+#define XCHAL_CONFIGID0                 XCHAL_HW_CONFIGID0      /* for backward compatibility only -- don't use! */
+#define XCHAL_CONFIGID1                 XCHAL_HW_CONFIGID1      /* for backward compatibility only -- don't use! */
+#define XCHAL_HW_RELEASE_MAJOR          1050    /* major release of targeted hardware */
+#define XCHAL_HW_RELEASE_MINOR          1       /* minor release of targeted hardware */
+#define XCHAL_HW_RELEASE_NAME           "T1050.1"       /* full release name of targeted hardware */
+#define XTHAL_HW_REL_T1050      1
+#define XTHAL_HW_REL_T1050_1    1
+#define XCHAL_HW_CONFIGID_RELIABLE      1
+#endif /*0*/
+
+
+
+/*----------------------------------------------------------------------
+                                ISA
+  ----------------------------------------------------------------------*/
+
+#if 0   /* these probably don't belong here, but are related to or implemented using TIE */
+#define XCHAL_HAVE_BOOLEANS             0       /* 1 if booleans option configured, 0 otherwise */
+/*  Misc instructions:  */
+#define XCHAL_HAVE_MUL32                0       /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+#define XCHAL_HAVE_MUL32_HIGH           0       /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+
+#define XCHAL_HAVE_FP                   0       /* 1 if floating point option configured, 0 otherwise */
+#endif /*0*/
+
+
+#endif /*XTENSA_CONFIG_TIE_H*/
+
diff --git a/include/asm-xtensa/xtensa/coreasm.h b/include/asm-xtensa/xtensa/coreasm.h
new file mode 100644
index 000000000000..a8cfb54c20a1
--- /dev/null
+++ b/include/asm-xtensa/xtensa/coreasm.h
@@ -0,0 +1,526 @@
+#ifndef XTENSA_COREASM_H
+#define XTENSA_COREASM_H
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/coreasm.h -- assembler-specific
+ * definitions that depend on CORE configuration.
+ *
+ * Source for configuration-independent binaries (which link in a
+ * configuration-specific HAL library) must NEVER include this file.
+ * It is perfectly normal, however, for the HAL itself to include this
+ * file.
+ *
+ * This file must NOT include xtensa/config/system.h.  Any assembler
+ * header file that depends on system information should likely go in
+ * a new systemasm.h (or sysasm.h) header file.
+ *
+ *  NOTE: macro beqi32 is NOT configuration-dependent, and is placed
+ *        here til we will have configuration-independent header file.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+
+/*
+ *  Assembly-language specific definitions (assembly macros, etc.).
+ */
+
+/*----------------------------------------------------------------------
+ *  find_ms_setbit
+ *
+ *  This macro finds the most significant bit that is set in <as>
+ *  and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
+ *  The index counts starting at zero for the lsbit, so the return
+ *  value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
+ *
+ *  Parameters:
+ *      <ad>    destination address register (any register)
+ *      <as>    source address register
+ *      <at>    temporary address register (must be different than <as>)
+ *      <base>  constant value added to result (usually 0 or 1)
+ *  On entry:
+ *      <ad> = undefined if different than <as>
+ *      <as> = value whose most significant set bit is to be found
+ *      <at> = undefined
+ *      no other registers are used by this macro.
+ *  On exit:
+ *      <ad> = <base> + index of msbit set in original <as>,
+ *           = <base> - 1 if original <as> was zero.
+ *      <as> clobbered (if not <ad>)
+ *      <at> clobbered (if not <ad>)
+ *  Example:
+ *      find_ms_setbit a0, a4, a0, 0            -- return in a0 index of msbit set in a4
+ */
+
+        .macro  find_ms_setbit ad, as, at, base
+#if XCHAL_HAVE_NSA
+        movi    \at, 31+\base
+        nsau    \as, \as        // get index of \as, numbered from msbit (32 if absent)
+        sub     \ad, \at, \as   // get numbering from lsbit (0..31, -1 if absent)
+#else /* XCHAL_HAVE_NSA */
+        movi    \at, \base      // start with result of 0 (point to lsbit of 32)
+
+        beqz    \as, 2f         // special case for zero argument: return -1
+        bltui   \as, 0x10000, 1f        // is it one of the 16 lsbits? (if so, check lower 16 bits)
+        addi    \at, \at, 16    // no, increment result to upper 16 bits (of 32)
+        //srli  \as, \as, 16    // check upper half (shift right 16 bits)
+        extui   \as, \as, 16, 16        // check upper half (shift right 16 bits)
+1:      bltui   \as, 0x100, 1f  // is it one of the 8 lsbits? (if so, check lower 8 bits)
+        addi    \at, \at, 8     // no, increment result to upper 8 bits (of 16)
+        srli    \as, \as, 8     // shift right to check upper 8 bits
+1:      bltui   \as, 0x10, 1f   // is it one of the 4 lsbits? (if so, check lower 4 bits)
+        addi    \at, \at, 4     // no, increment result to upper 4 bits (of 8)
+        srli    \as, \as, 4     // shift right 4 bits to check upper half
+1:      bltui   \as, 0x4, 1f    // is it one of the 2 lsbits? (if so, check lower 2 bits)
+        addi    \at, \at, 2     // no, increment result to upper 2 bits (of 4)
+        srli    \as, \as, 2     // shift right 2 bits to check upper half
+1:      bltui   \as, 0x2, 1f    // is it the lsbit?
+        addi    \at, \at, 2     // no, increment result to upper bit (of 2)
+2:      addi    \at, \at, -1    // (from just above: add 1;  from beqz: return -1)
+        //srli  \as, \as, 1
+1:                              // done! \at contains index of msbit set (or -1 if none set)
+        .if     0x\ad - 0x\at   // destination different than \at ? (works because regs are a0-a15)
+        mov     \ad, \at        // then move result to \ad
+        .endif
+#endif /* XCHAL_HAVE_NSA */
+        .endm   // find_ms_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_setbit
+ *
+ *  This macro finds the least significant bit that is set in <as>,
+ *  and return its index in <ad>.
+ *  Usage is the same as for the find_ms_setbit macro.
+ *  Example:
+ *      find_ls_setbit a0, a4, a0, 0    -- return in a0 index of lsbit set in a4
+ */
+
+        .macro  find_ls_setbit ad, as, at, base
+        neg     \at, \as        // keep only the least-significant bit that is set...
+        and     \as, \at, \as   // ... in \as
+        find_ms_setbit  \ad, \as, \at, \base
+        .endm   // find_ls_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_one
+ *
+ *  Same as find_ls_setbit with base zero.
+ *  Source (as) and destination (ad) registers must be different.
+ *  Provided for backward compatibility.
+ */
+
+        .macro  find_ls_one ad, as
+        find_ls_setbit  \ad, \as, \ad, 0
+        .endm   // find_ls_one
+
+/*----------------------------------------------------------------------
+ *  floop, floopnez, floopgtz, floopend
+ *
+ *  These macros are used for fast inner loops that
+ *  work whether or not the Loops options is configured.
+ *  If the Loops option is configured, they simply use
+ *  the zero-overhead LOOP instructions; otherwise
+ *  they use explicit decrement and branch instructions.
+ *
+ *  They are used in pairs, with floop, floopnez or floopgtz
+ *  at the beginning of the loop, and floopend at the end.
+ *
+ *  Each pair of loop macro calls must be given the loop count
+ *  address register and a unique label for that loop.
+ *
+ *  Example:
+ *
+ *      movi     a3, 16     // loop 16 times
+ *      floop    a3, myloop1
+ *      :
+ *      bnez     a7, end1       // exit loop if a7 != 0
+ *      :
+ *      floopend a3, myloop1
+ *  end1:
+ *
+ *  Like the LOOP instructions, these macros cannot be
+ *  nested, must include at least one instruction,
+ *  cannot call functions inside the loop, etc.
+ *  The loop can be exited by jumping to the instruction
+ *  following floopend (or elsewhere outside the loop),
+ *  or continued by jumping to a NOP instruction placed
+ *  immediately before floopend.
+ *
+ *  Unlike LOOP instructions, the register passed to floop*
+ *  cannot be used inside the loop, because it is used as
+ *  the loop counter if the Loops option is not configured.
+ *  And its value is undefined after exiting the loop.
+ *  And because the loop counter register is active inside
+ *  the loop, you can't easily use this construct to loop
+ *  across a register file using ROTW as you might with LOOP
+ *  instructions, unless you copy the loop register along.
+ */
+
+        /*  Named label version of the macros:  */
+
+        .macro  floop           ar, endlabel
+        floop_          \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+        .endm
+
+        .macro  floopnez        ar, endlabel
+        floopnez_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+        .endm
+
+        .macro  floopgtz        ar, endlabel
+        floopgtz_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+        .endm
+
+        .macro  floopend        ar, endlabel
+        floopend_       \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+        .endm
+
+        /*  Numbered local label version of the macros:  */
+#if 0 /*UNTESTED*/
+        .macro  floop89         ar
+        floop_          \ar, 8, 9f
+        .endm
+
+        .macro  floopnez89      ar
+        floopnez_       \ar, 8, 9f
+        .endm
+
+        .macro  floopgtz89      ar
+        floopgtz_       \ar, 8, 9f
+        .endm
+
+        .macro  floopend89      ar
+        floopend_       \ar, 8b, 9
+        .endm
+#endif /*0*/
+
+        /*  Underlying version of the macros:  */
+
+        .macro  floop_  ar, startlabel, endlabelref
+        .ifdef  _infloop_
+        .if     _infloop_
+        .err    // Error: floop cannot be nested
+        .endif
+        .endif
+        .set    _infloop_, 1
+#if XCHAL_HAVE_LOOPS
+        loop    \ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+\startlabel:
+        addi    \ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+        .endm   // floop_
+
+        .macro  floopnez_       ar, startlabel, endlabelref
+        .ifdef  _infloop_
+        .if     _infloop_
+        .err    // Error: floopnez cannot be nested
+        .endif
+        .endif
+        .set    _infloop_, 1
+#if XCHAL_HAVE_LOOPS
+        loopnez \ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+        beqz    \ar, \endlabelref
+\startlabel:
+        addi    \ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+        .endm   // floopnez_
+
+        .macro  floopgtz_       ar, startlabel, endlabelref
+        .ifdef  _infloop_
+        .if     _infloop_
+        .err    // Error: floopgtz cannot be nested
+        .endif
+        .endif
+        .set    _infloop_, 1
+#if XCHAL_HAVE_LOOPS
+        loopgtz \ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+        bltz    \ar, \endlabelref
+        beqz    \ar, \endlabelref
+\startlabel:
+        addi    \ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+        .endm   // floopgtz_
+
+
+        .macro  floopend_       ar, startlabelref, endlabel
+        .ifndef _infloop_
+        .err    // Error: floopend without matching floopXXX
+        .endif
+        .ifeq   _infloop_
+        .err    // Error: floopend without matching floopXXX
+        .endif
+        .set    _infloop_, 0
+#if ! XCHAL_HAVE_LOOPS
+        bnez    \ar, \startlabelref
+#endif /* XCHAL_HAVE_LOOPS */
+\endlabel:
+        .endm   // floopend_
+
+/*----------------------------------------------------------------------
+ *  crsil  --  conditional RSIL (read/set interrupt level)
+ *
+ *  Executes the RSIL instruction if it exists, else just reads PS.
+ *  The RSIL instruction does not exist in the new exception architecture
+ *  if the interrupt option is not selected.
+ */
+
+        .macro  crsil   ar, newlevel
+#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
+        rsil    \ar, \newlevel
+#else
+        rsr     \ar, PS
+#endif
+        .endm   // crsil
+
+/*----------------------------------------------------------------------
+ *  window_spill{4,8,12}
+ *
+ *  These macros spill callers' register windows to the stack.
+ *  They work for both privileged and non-privileged tasks.
+ *  Must be called from a windowed ABI context, eg. within
+ *  a windowed ABI function (ie. valid stack frame, window
+ *  exceptions enabled, not in exception mode, etc).
+ *
+ *  This macro requires a single invocation of the window_spill_common
+ *  macro in the same assembly unit and section.
+ *
+ *  Note that using window_spill{4,8,12} macros is more efficient
+ *  than calling a function implemented using window_spill_function,
+ *  because the latter needs extra code to figure out the size of
+ *  the call to the spilling function.
+ *
+ *  Example usage:
+ *
+ *              .text
+ *              .align  4
+ *              .global some_function
+ *              .type   some_function,@function
+ *      some_function:
+ *              entry   a1, 16
+ *              :
+ *              :
+ *
+ *              window_spill4   // spill windows of some_function's callers; preserves a0..a3 only;
+ *                              // to use window_spill{8,12} in this example function we'd have
+ *                              // to increase space allocated by the entry instruction, because
+ *                              // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
+ *                              // for call8/window_spill8 or call12/window_spill12 respectively.
+ *              :
+ *
+ *              retw
+ *
+ *              window_spill_common     // instantiates code used by window_spill4
+ *
+ *
+ *  On entry:
+ *      none (if window_spill4)
+ *      stack frame has enough space allocated for call8 (if window_spill8)
+ *      stack frame has enough space allocated for call12 (if window_spill12)
+ *  On exit:
+ *       a4..a15 clobbered (if window_spill4)
+ *       a8..a15 clobbered (if window_spill8)
+ *      a12..a15 clobbered (if window_spill12)
+ *      no caller windows are in live registers
+ */
+
+        .macro  window_spill4
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+        movi    a15, 0                  // for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+        call4   .L__wdwspill_assist28   // call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+        call4   .L__wdwspill_assist60   // call deep enough to clear out any live callers
+# endif
+#endif
+        .endm   // window_spill4
+
+        .macro  window_spill8
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+        movi    a15, 0                  // for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+        call8   .L__wdwspill_assist24   // call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+        call8   .L__wdwspill_assist56   // call deep enough to clear out any live callers
+# endif
+#endif
+        .endm   // window_spill8
+
+        .macro  window_spill12
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+        movi    a15, 0                  // for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+        call12  .L__wdwspill_assist20   // call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+        call12  .L__wdwspill_assist52   // call deep enough to clear out any live callers
+# endif
+#endif
+        .endm   // window_spill12
+
+/*----------------------------------------------------------------------
+ *  window_spill_function
+ *
+ *  This macro outputs a function that will spill its caller's callers'
+ *  register windows to the stack.  Eg. it could be used to implement
+ *  a version of xthal_window_spill() that works in non-privileged tasks.
+ *  This works for both privileged and non-privileged tasks.
+ *
+ *  Typical usage:
+ *
+ *              .text
+ *              .align  4
+ *              .global my_spill_function
+ *              .type   my_spill_function,@function
+ *      my_spill_function:
+ *              window_spill_function
+ *
+ *  On entry to resulting function:
+ *      none
+ *  On exit from resulting function:
+ *      none (no caller windows are in live registers)
+ */
+
+        .macro  window_spill_function
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 32
+        entry   sp, 48
+        bbci.l  a0, 31, 1f              // branch if called with call4
+        bbsi.l  a0, 30, 2f              // branch if called with call12
+        call8   .L__wdwspill_assist16   // called with call8, only need another 8
+        retw
+1:      call12  .L__wdwspill_assist16   // called with call4, only need another 12
+        retw
+2:      call4   .L__wdwspill_assist16   // called with call12, only need another 4
+        retw
+# elif XCHAL_NUM_AREGS == 64
+        entry   sp, 48
+        bbci.l  a0, 31, 1f              // branch if called with call4
+        bbsi.l  a0, 30, 2f              // branch if called with call12
+        call4   .L__wdwspill_assist52   // called with call8, only need a call4
+        retw
+1:      call8   .L__wdwspill_assist52   // called with call4, only need a call8
+        retw
+2:      call12  .L__wdwspill_assist40   // called with call12, can skip a call12
+        retw
+# elif XCHAL_NUM_AREGS == 16
+        entry   sp, 16
+        bbci.l  a0, 31, 1f      // branch if called with call4
+        bbsi.l  a0, 30, 2f      // branch if called with call12
+        movi    a7, 0           // called with call8
+        retw
+1:      movi    a11, 0          // called with call4
+2:      retw                    // if called with call12, everything already spilled
+
+//      movi    a15, 0          // trick to spill all but the direct caller
+//      j       1f
+//      //  The entry instruction is magical in the assembler (gets auto-aligned)
+//      //  so we have to jump to it to avoid falling through the padding.
+//      //  We need entry/retw to know where to return.
+//1:    entry   sp, 16
+//      retw
+# else
+#  error "unrecognized address register file size"
+# endif
+#endif /* XCHAL_HAVE_WINDOWED */
+        window_spill_common
+        .endm   // window_spill_function
+
+/*----------------------------------------------------------------------
+ *  window_spill_common
+ *
+ *  Common code used by any number of invocations of the window_spill##
+ *  and window_spill_function macros.
+ *
+ *  Must be instantiated exactly once within a given assembly unit,
+ *  within call/j range of and same section as window_spill##
+ *  macro invocations for that assembly unit.
+ *  (Is automatically instantiated by the window_spill_function macro.)
+ */
+
+        .macro  window_spill_common
+#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
+        .ifndef .L__wdwspill_defined
+# if XCHAL_NUM_AREGS >= 64
+.L__wdwspill_assist60:
+        entry   sp, 32
+        call8   .L__wdwspill_assist52
+        retw
+.L__wdwspill_assist56:
+        entry   sp, 16
+        call4   .L__wdwspill_assist52
+        retw
+.L__wdwspill_assist52:
+        entry   sp, 48
+        call12  .L__wdwspill_assist40
+        retw
+.L__wdwspill_assist40:
+        entry   sp, 48
+        call12  .L__wdwspill_assist28
+        retw
+# endif
+.L__wdwspill_assist28:
+        entry   sp, 48
+        call12  .L__wdwspill_assist16
+        retw
+.L__wdwspill_assist24:
+        entry   sp, 32
+        call8   .L__wdwspill_assist16
+        retw
+.L__wdwspill_assist20:
+        entry   sp, 16
+        call4   .L__wdwspill_assist16
+        retw
+.L__wdwspill_assist16:
+        entry   sp, 16
+        movi    a15, 0
+        retw
+        .set    .L__wdwspill_defined, 1
+        .endif
+#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
+        .endm   // window_spill_common
+
+/*----------------------------------------------------------------------
+ *  beqi32
+ *
+ *  macro implements version of beqi for arbitrary 32-bit immidiate value
+ *
+ *     beqi32 ax, ay, imm32, label
+ *
+ *  Compares value in register ax with imm32 value and jumps to label if
+ *  equal. Clobberes register ay if needed
+ *
+ */
+   .macro beqi32        ax, ay, imm, label
+    .ifeq ((\imm-1) & ~7)       // 1..8 ?
+                beqi    \ax, \imm, \label
+    .else
+      .ifeq (\imm+1)            // -1 ?
+                beqi    \ax, \imm, \label
+      .else
+        .ifeq (\imm)            // 0 ?
+                beqz    \ax, \label
+        .else
+                //  We could also handle immediates 10,12,16,32,64,128,256
+                //  but it would be a long macro...
+                movi    \ay, \imm
+                beq     \ax, \ay, \label
+        .endif
+      .endif
+    .endif
+   .endm // beqi32
+
+#endif /*XTENSA_COREASM_H*/
+
diff --git a/include/asm-xtensa/xtensa/corebits.h b/include/asm-xtensa/xtensa/corebits.h
new file mode 100644
index 000000000000..e578ade41632
--- /dev/null
+++ b/include/asm-xtensa/xtensa/corebits.h
@@ -0,0 +1,77 @@
+#ifndef XTENSA_COREBITS_H
+#define XTENSA_COREBITS_H
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * xtensa/corebits.h - Xtensa Special Register field positions and masks.
+ *
+ * (In previous releases, these were defined in specreg.h, a generated file.
+ *  This file is not generated, i.e. it is processor configuration independent.)
+ */
+
+
+/*  EXCCAUSE register fields:  */
+#define EXCCAUSE_EXCCAUSE_SHIFT 0
+#define EXCCAUSE_EXCCAUSE_MASK  0x3F
+/*  Exception causes (mostly incomplete!):  */
+#define EXCCAUSE_ILLEGAL                0
+#define EXCCAUSE_SYSCALL                1
+#define EXCCAUSE_IFETCHERROR            2
+#define EXCCAUSE_LOADSTOREERROR         3
+#define EXCCAUSE_LEVEL1INTERRUPT        4
+#define EXCCAUSE_ALLOCA                 5
+
+/*  PS register fields:  */
+#define PS_WOE_SHIFT            18
+#define PS_WOE_MASK             0x00040000
+#define PS_WOE                  PS_WOE_MASK
+#define PS_CALLINC_SHIFT        16
+#define PS_CALLINC_MASK         0x00030000
+#define PS_CALLINC(n)           (((n)&3)<<PS_CALLINC_SHIFT)     /* n = 0..3 */
+#define PS_OWB_SHIFT            8
+#define PS_OWB_MASK             0x00000F00
+#define PS_OWB(n)               (((n)&15)<<PS_OWB_SHIFT)        /* n = 0..15 (or 0..7) */
+#define PS_RING_SHIFT           6
+#define PS_RING_MASK            0x000000C0
+#define PS_RING(n)              (((n)&3)<<PS_RING_SHIFT)        /* n = 0..3 */
+#define PS_UM_SHIFT             5
+#define PS_UM_MASK              0x00000020
+#define PS_UM                   PS_UM_MASK
+#define PS_EXCM_SHIFT           4
+#define PS_EXCM_MASK            0x00000010
+#define PS_EXCM                 PS_EXCM_MASK
+#define PS_INTLEVEL_SHIFT       0
+#define PS_INTLEVEL_MASK        0x0000000F
+#define PS_INTLEVEL(n)          ((n)&PS_INTLEVEL_MASK)          /* n = 0..15 */
+/*  Backward compatibility (deprecated):  */
+#define PS_PROGSTACK_SHIFT      PS_UM_SHIFT
+#define PS_PROGSTACK_MASK       PS_UM_MASK
+#define PS_PROG_SHIFT           PS_UM_SHIFT
+#define PS_PROG_MASK            PS_UM_MASK
+#define PS_PROG                 PS_UM
+
+/*  DBREAKCn register fields:  */
+#define DBREAKC_MASK_SHIFT              0
+#define DBREAKC_MASK_MASK               0x0000003F
+#define DBREAKC_LOADBREAK_SHIFT         30
+#define DBREAKC_LOADBREAK_MASK          0x40000000
+#define DBREAKC_STOREBREAK_SHIFT        31
+#define DBREAKC_STOREBREAK_MASK         0x80000000
+
+/*  DEBUGCAUSE register fields:  */
+#define DEBUGCAUSE_DEBUGINT_SHIFT       5
+#define DEBUGCAUSE_DEBUGINT_MASK        0x20    /* debug interrupt */
+#define DEBUGCAUSE_BREAKN_SHIFT         4
+#define DEBUGCAUSE_BREAKN_MASK          0x10    /* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_SHIFT          3
+#define DEBUGCAUSE_BREAK_MASK           0x08    /* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_SHIFT         2
+#define DEBUGCAUSE_DBREAK_MASK          0x04    /* DBREAK match */
+#define DEBUGCAUSE_IBREAK_SHIFT         1
+#define DEBUGCAUSE_IBREAK_MASK          0x02    /* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_SHIFT         0
+#define DEBUGCAUSE_ICOUNT_MASK          0x01    /* ICOUNT would increment to zero */
+
+#endif /*XTENSA_COREBITS_H*/
+
diff --git a/include/asm-xtensa/xtensa/hal.h b/include/asm-xtensa/xtensa/hal.h
new file mode 100644
index 000000000000..d10472505454
--- /dev/null
+++ b/include/asm-xtensa/xtensa/hal.h
@@ -0,0 +1,822 @@
+#ifndef XTENSA_HAL_H
+#define XTENSA_HAL_H
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/hal.h -- contains a definition of the
+ * Core HAL interface.
+ *
+ * All definitions in this header file are independent of any specific
+ * Xtensa processor configuration.  Thus an OS or other software can
+ * include this header file and be compiled into configuration-
+ * independent objects that can be distributed and eventually linked
+ * to the HAL library (libhal.a) to create a configuration-specific
+ * final executable.
+ *
+ * Certain definitions, however, are release-specific -- such as the
+ * XTHAL_RELEASE_xxx macros (or additions made in later releases).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+/*----------------------------------------------------------------------
+                         Constant Definitions
+                        (shared with assembly)
+  ----------------------------------------------------------------------*/
+
+/*  Software release information (not configuration-specific!):  */
+#define XTHAL_RELEASE_MAJOR     1050
+#define XTHAL_RELEASE_MINOR     0
+#define XTHAL_RELEASE_NAME      "T1050.0-2002-08-06-eng0"
+#define XTHAL_RELEASE_INTERNAL  "2002-08-06-eng0"
+#define XTHAL_REL_T1050 1
+#define XTHAL_REL_T1050_0       1
+#define XTHAL_REL_T1050_0_2002  1
+#define XTHAL_REL_T1050_0_2002_08       1
+#define XTHAL_REL_T1050_0_2002_08_06    1
+#define XTHAL_REL_T1050_0_2002_08_06_ENG0       1
+
+/*  HAL version numbers (these names are for backward compatibility):  */
+#define XTHAL_MAJOR_REV         XTHAL_RELEASE_MAJOR
+#define XTHAL_MINOR_REV         XTHAL_RELEASE_MINOR
+/*
+ *  A bit of software release history on values of XTHAL_{MAJOR,MINOR}_REV:
+ *
+ *      Release         MAJOR   MINOR           Comment
+ *      =======         =====   =====           =======
+ *      T1015.n         n/a     n/a             (HAL not yet available)
+ *      T1020.{0,1,2}   0       1               (HAL beta)
+ *      T1020.{3,4}     0       2               First release.
+ *      T1020.n (n>4)   0       2 or >3         (TBD)
+ *      T1030.0         0       1               (HAL beta)
+ *      T1030.{1,2}     0       3               Equivalent to first release.
+ *      T1030.n (n>=3)  0       >= 3            (TBD)
+ *      T1040.n         1040    n               Full CHAL available from T1040.2
+ *      T1050.n         1050    n               Current release.
+ *
+ *
+ *  Note:  there is a distinction between the software release with
+ *  which something is compiled (accessible using XTHAL_RELEASE_* macros)
+ *  and the software release with which the HAL library was compiled
+ *  (accessible using Xthal_release_* global variables).  This
+ *  distinction is particularly relevant for vendors that distribute
+ *  configuration-independent binaries (eg. an OS), where their customer
+ *  might link it with a HAL of a different Xtensa software release.
+ *  In this case, it may be appropriate for the OS to verify at run-time
+ *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
+ *  [Guidelines as to which release is compatible with which are not
+ *  currently provided explicitly, but might be inferred from reading
+ *  OSKit documentation for all releases -- compatibility is also highly
+ *  dependent on which HAL features are used.  Each release is usually
+ *  backward compatible, with very few exceptions if any.]
+ *
+ *  Notes:
+ *      Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
+ *      Tornado 2.0.2 supported in T1040.2+, and T1050.
+ *      Compile-time HAL port of NucleusPlus supported by T1040.2+ and T1050.
+ */
+
+
+/*
+ *  Architectural limits, independent of configuration.
+ *  Note that these are ISA-defined limits, not micro-architecture implementation
+ *  limits enforced by the Xtensa Processor Generator (which may be stricter than
+ *  these below).
+ */
+#define XTHAL_MAX_CPS           8       /* max number of coprocessors (0..7) */
+#define XTHAL_MAX_INTERRUPTS    32      /* max number of interrupts (0..31) */
+#define XTHAL_MAX_INTLEVELS     16      /* max number of interrupt levels (0..15) */
+                                        /* (as of T1040, implementation limit is 7: 0..6) */
+#define XTHAL_MAX_TIMERS        4       /* max number of timers (CCOMPARE0..CCOMPARE3) */
+                                        /* (as of T1040, implementation limit is 3: 0..2) */
+
+/*  Misc:  */
+#define XTHAL_LITTLEENDIAN              0
+#define XTHAL_BIGENDIAN                 1
+
+
+/*  Interrupt types:  */
+#define XTHAL_INTTYPE_UNCONFIGURED      0
+#define XTHAL_INTTYPE_SOFTWARE          1
+#define XTHAL_INTTYPE_EXTERN_EDGE       2
+#define XTHAL_INTTYPE_EXTERN_LEVEL      3
+#define XTHAL_INTTYPE_TIMER             4
+#define XTHAL_INTTYPE_NMI               5
+#define XTHAL_MAX_INTTYPES              6       /* number of interrupt types */
+
+/*  Timer related:  */
+#define XTHAL_TIMER_UNCONFIGURED        -1      /* Xthal_timer_interrupt[] value for non-existent timers */
+#define XTHAL_TIMER_UNASSIGNED  XTHAL_TIMER_UNCONFIGURED        /* (for backwards compatibility only) */
+
+
+/*  Access Mode bits (tentative):  */   /* bit abbr unit short_name       PPC equ - Description */
+#define XTHAL_AMB_EXCEPTION     0       /* 001 E EX fls: EXception        none    - generate exception on any access (aka "illegal") */
+#define XTHAL_AMB_HITCACHE      1       /* 002 C CH fls: use Cache on Hit ~(I CI) - use cache on hit -- way from tag match [or H HC, or U UC] (ISA: same, except for Isolate case) */
+#define XTHAL_AMB_ALLOCATE      2       /* 004 A AL fl?: ALlocate         none    - refill cache on miss -- way from LRU [or F FI fill] (ISA: Read/Write Miss Refill) */
+#define XTHAL_AMB_WRITETHRU     3       /* 008 W WT --s: WriteThrough     W WT    - store immediately to memory (ISA: same) */
+#define XTHAL_AMB_ISOLATE       4       /* 010 I IS fls: ISolate          none    - use cache regardless of hit-vs-miss -- way from vaddr (ISA: use-cache-on-miss+hit) */
+#define XTHAL_AMB_GUARD         5       /* 020 G GU ?l?: GUard            G *     - non-speculative; spec/replay refs not permitted */
+#if 0
+#define XTHAL_AMB_ORDERED       x       /* 000 O OR fls: ORdered          G *     - mem accesses cannot be out of order */
+#define XTHAL_AMB_FUSEWRITES    x       /* 000 F FW --s: FuseWrites       none    - allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */
+#define XTHAL_AMB_COHERENT      x       /* 000 M MC fl?: Mem/MP Coherent  M       - on reads, other CPUs/bus-masters may need to supply data */
+#define XTHAL_AMB_TRUSTED       x       /* 000 T TR ?l?: TRusted          none    - memory will not bus error (if it does, handle as fatal imprecise interrupt) */
+#define XTHAL_AMB_PREFETCH      x       /* 000 P PR fl?: PRefetch         none    - on refill, read line+1 into prefetch buffers */
+#define XTHAL_AMB_STREAM        x       /* 000 S ST ???: STreaming        none    - access one of N stream buffers */
+#endif /*0*/
+
+#define XTHAL_AM_EXCEPTION      (1<<XTHAL_AMB_EXCEPTION)
+#define XTHAL_AM_HITCACHE       (1<<XTHAL_AMB_HITCACHE)
+#define XTHAL_AM_ALLOCATE       (1<<XTHAL_AMB_ALLOCATE)
+#define XTHAL_AM_WRITETHRU      (1<<XTHAL_AMB_WRITETHRU)
+#define XTHAL_AM_ISOLATE        (1<<XTHAL_AMB_ISOLATE)
+#define XTHAL_AM_GUARD          (1<<XTHAL_AMB_GUARD)
+#if 0
+#define XTHAL_AM_ORDERED        (1<<XTHAL_AMB_ORDERED)
+#define XTHAL_AM_FUSEWRITES     (1<<XTHAL_AMB_FUSEWRITES)
+#define XTHAL_AM_COHERENT       (1<<XTHAL_AMB_COHERENT)
+#define XTHAL_AM_TRUSTED        (1<<XTHAL_AMB_TRUSTED)
+#define XTHAL_AM_PREFETCH       (1<<XTHAL_AMB_PREFETCH)
+#define XTHAL_AM_STREAM         (1<<XTHAL_AMB_STREAM)
+#endif /*0*/
+
+/*
+ *  Allowed Access Modes (bit combinations).
+ *
+ *  Columns are:
+ *  "FOGIWACE"
+ *      Access mode bits (see XTHAL_AMB_xxx above).
+ *      <letter> = bit is set
+ *      '-'      = bit is clear
+ *      '.'      = bit is irrelevant / don't care, as follows:
+ *                      E=1 makes all others irrelevant
+ *                      W,F relevant only for stores
+ *  "2345"
+ *      Indicates which Xtensa releases support the corresponding
+ *      access mode.  Releases for each character column are:
+ *              2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1
+ *              3 = T1020.2 and later:  T1020.2+, T1030
+ *              4 = T1040
+ *              5 = T1050 (maybe)
+ *      And the character column contents are:
+ *              <number> = support by release(s)
+ *              "." = unsupported by release(s)
+ *              "?" = support unknown
+ */
+                                        /* FOGIWACE 2345 */
+/*  For instruction fetch:  */
+#define XTHAL_FAM_EXCEPTION     0x001   /* .......E 2345 exception */
+#define XTHAL_FAM_ISOLATE       0x012   /* .--I.-C- .... isolate */
+#define XTHAL_FAM_BYPASS        0x000   /* .---.--- 2345 bypass */
+#define XTHAL_FAM_NACACHED      0x002   /* .---.-C- .... cached no-allocate (frozen) */
+#define XTHAL_FAM_CACHED        0x006   /* .---.AC- 2345 cached */
+/*  For data load:  */
+#define XTHAL_LAM_EXCEPTION     0x001   /* .......E 2345 exception */
+#define XTHAL_LAM_ISOLATE       0x012   /* .--I.-C- 2345 isolate */
+#define XTHAL_LAM_BYPASS        0x000   /* .O--.--- 2... bypass speculative */
+#define XTHAL_LAM_BYPASSG       0x020   /* .OG-.--- .345 bypass guarded */
+#define XTHAL_LAM_NACACHED      0x002   /* .O--.-C- 2... cached no-allocate speculative */
+#define XTHAL_LAM_NACACHEDG     0x022   /* .OG-.-C- .345 cached no-allocate guarded */
+#define XTHAL_LAM_CACHED        0x006   /* .---.AC- 2345 cached speculative */
+#define XTHAL_LAM_CACHEDG       0x026   /* .?G-.AC- .... cached guarded */
+/*  For data store:  */
+#define XTHAL_SAM_EXCEPTION     0x001   /* .......E 2345 exception */
+#define XTHAL_SAM_ISOLATE       0x032   /* .-GI--C- 2345 isolate */
+#define XTHAL_SAM_BYPASS        0x028   /* -OG-W--- 2345 bypass */
+/*efine XTHAL_SAM_BYPASSF       0x028*/ /* F-G-W--- ...? bypass write-combined */
+#define XTHAL_SAM_WRITETHRU     0x02A   /* -OG-W-C- 234? writethrough */
+/*efine XTHAL_SAM_WRITETHRUF    0x02A*/ /* F-G-W-C- ...5 writethrough write-combined */
+#define XTHAL_SAM_WRITEALLOC    0x02E   /* -OG-WAC- ...? writethrough-allocate */
+/*efine XTHAL_SAM_WRITEALLOCF   0x02E*/ /* F-G-WAC- ...? writethrough-allocate write-combined */
+#define XTHAL_SAM_WRITEBACK     0x026   /* F-G--AC- ...5 writeback */
+
+#if 0
+/*
+    Cache attribute encoding for CACHEATTR (per ISA):
+    (Note:  if this differs from ISA Ref Manual, ISA has precedence)
+
+        Inst-fetches    Loads           Stores
+        -------------   ------------    -------------
+0x0     FCA_EXCEPTION  ?LCA_NACACHED_G* SCA_WRITETHRU   "uncached"
+0x1     FCA_CACHED      LCA_CACHED      SCA_WRITETHRU   cached
+0x2     FCA_BYPASS      LCA_BYPASS_G*   SCA_BYPASS      bypass
+0x3     FCA_CACHED      LCA_CACHED      SCA_WRITEALLOCF write-allocate
+                     or LCA_EXCEPTION   SCA_EXCEPTION   (if unimplemented)
+0x4     FCA_CACHED      LCA_CACHED      SCA_WRITEBACK   write-back
+                     or LCA_EXCEPTION   SCA_EXCEPTION   (if unimplemented)
+0x5..D  FCA_EXCEPTION   LCA_EXCEPTION   SCA_EXCEPTION   (reserved)
+0xE     FCA_EXCEPTION   LCA_ISOLATE     SCA_ISOLATE     isolate
+0xF     FCA_EXCEPTION   LCA_EXCEPTION   SCA_EXCEPTION   illegal
+     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
+*/
+#endif /*0*/
+
+
+#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------
+                             HAL
+  ----------------------------------------------------------------------*/
+
+/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
+extern const unsigned int Xthal_rev_no;
+
+
+/*----------------------------------------------------------------------
+                        Processor State
+  ----------------------------------------------------------------------*/
+/* save & restore the extra processor state */
+extern void xthal_save_extra(void *base);
+extern void xthal_restore_extra(void *base);
+
+extern void xthal_save_cpregs(void *base, int);
+extern void xthal_restore_cpregs(void *base, int);
+
+/*extern void xthal_save_all_extra(void *base);*/
+/*extern void xthal_restore_all_extra(void *base);*/
+
+/* space for processor state */
+extern const unsigned int Xthal_extra_size;
+extern const unsigned int Xthal_extra_align;
+/* space for TIE register files */
+extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
+
+/* total of space for the processor state (for Tor2) */
+extern const unsigned int Xthal_all_extra_size;
+extern const unsigned int Xthal_all_extra_align;
+
+/* initialize the extra processor */
+/*extern void xthal_init_extra(void);*/
+/* initialize the TIE coprocessor */
+/*extern void xthal_init_cp(int);*/
+
+/* initialize the extra processor */
+extern void xthal_init_mem_extra(void *);
+/* initialize the TIE coprocessor */
+extern void xthal_init_mem_cp(void *, int);
+
+/* validate & invalidate the TIE register file */
+extern void xthal_validate_cp(int);
+extern void xthal_invalidate_cp(int);
+
+/* the number of TIE coprocessors contiguous from zero (for Tor2) */
+extern const unsigned int Xthal_num_coprocessors;
+
+/* actual number of coprocessors */
+extern const unsigned char Xthal_cp_num;
+/* index of highest numbered coprocessor, plus one */
+extern const unsigned char Xthal_cp_max;
+/* index of highest allowed coprocessor number, per cfg, plus one */
+/*extern const unsigned char Xthal_cp_maxcfg;*/
+/* bitmask of which coprocessors are present */
+extern const unsigned int  Xthal_cp_mask;
+
+/* read and write cpenable register */
+extern void xthal_set_cpenable(unsigned);
+extern unsigned xthal_get_cpenable(void);
+
+/* read & write extra state register */
+/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
+
+/* read & write a TIE coprocessor register */
+/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
+
+/* return coprocessor number based on register */
+/*extern int xthal_which_cp(unsigned reg);*/
+
+/*----------------------------------------------------------------------
+                                Interrupts
+  ----------------------------------------------------------------------*/
+
+/* the number of interrupt levels */
+extern const unsigned char Xthal_num_intlevels;
+/* the number of interrupts */
+extern const unsigned char Xthal_num_interrupts;
+
+/* mask for level of interrupts */
+extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
+/* mask for level 0 to N interrupts */
+extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
+
+/* level of each interrupt */
+extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
+
+/* type per interrupt */
+extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
+
+/* masks of each type of interrupt */
+extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
+
+/* interrupt numbers assigned to each timer interrupt */
+extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
+
+/***  Virtual interrupt prioritization:  ***/
+
+/*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */
+extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
+extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
+
+/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */
+extern unsigned xthal_int_enable(unsigned);
+extern unsigned xthal_int_disable(unsigned);
+
+/*  Set/get virtual priority of an interrupt:  */
+extern int      xthal_set_int_vpri(int intnum, int vpri);
+extern int      xthal_get_int_vpri(int intnum);
+
+/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */
+extern void     xthal_set_vpri_locklevel(unsigned intlevel);
+extern unsigned xthal_get_vpri_locklevel(void);
+
+/*  Set/get current virtual interrupt priority:  */
+extern unsigned xthal_set_vpri(unsigned vpri);
+extern unsigned xthal_get_vpri(unsigned vpri);
+extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
+extern unsigned xthal_set_vpri_lock(void);
+
+
+
+/*----------------------------------------------------------------------
+                        Generic Interrupt Trampolining Support
+  ----------------------------------------------------------------------*/
+
+typedef void (XtHalVoidFunc)(void);
+
+/*
+ *  Bitmask of interrupts currently trampolining down:
+ */
+extern unsigned Xthal_tram_pending;
+
+/*
+ *  Bitmask of which interrupts currently trampolining down
+ *  synchronously are actually enabled; this bitmask is necessary
+ *  because INTENABLE cannot hold that state (sync-trampolining
+ *  interrupts must be kept disabled while trampolining);
+ *  in the current implementation, any bit set here is not set
+ *  in INTENABLE, and vice-versa; once a sync-trampoline is
+ *  handled (at level one), its enable bit must be moved from
+ *  here to INTENABLE:
+ */
+extern unsigned Xthal_tram_enabled;
+
+/*
+ *  Bitmask of interrupts configured for sync trampolining:
+ */
+extern unsigned Xthal_tram_sync;
+
+
+/*  Trampoline support functions:  */
+extern unsigned  xthal_tram_pending_to_service( void );
+extern void      xthal_tram_done( unsigned serviced_mask );
+extern int       xthal_tram_set_sync( int intnum, int sync );
+extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
+
+/*  INTENABLE,INTREAD,INTSET,INTCLEAR register access functions:  */
+extern unsigned  xthal_get_intenable( void );
+extern void      xthal_set_intenable( unsigned );
+extern unsigned  xthal_get_intread( void );
+extern void      xthal_set_intset( unsigned );
+extern void      xthal_set_intclear( unsigned );
+
+
+/*----------------------------------------------------------------------
+                                Register Windows
+  ----------------------------------------------------------------------*/
+
+/* number of registers in register window */
+extern const unsigned int  Xthal_num_aregs;
+extern const unsigned char Xthal_num_aregs_log2;
+
+/*  This spill any live register windows (other than the caller's):  */
+extern void      xthal_window_spill( void );
+
+
+/*----------------------------------------------------------------------
+                                Cache
+  ----------------------------------------------------------------------*/
+
+/* size of the cache lines in log2(bytes) */
+extern const unsigned char Xthal_icache_linewidth;
+extern const unsigned char Xthal_dcache_linewidth;
+/* size of the cache lines in bytes */
+extern const unsigned short Xthal_icache_linesize;
+extern const unsigned short Xthal_dcache_linesize;
+/* number of cache sets in log2(lines per way) */
+extern const unsigned char Xthal_icache_setwidth;
+extern const unsigned char Xthal_dcache_setwidth;
+/* cache set associativity (number of ways) */
+extern const unsigned int  Xthal_icache_ways;
+extern const unsigned int  Xthal_dcache_ways;
+/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
+extern const unsigned int  Xthal_icache_size;
+extern const unsigned int  Xthal_dcache_size;
+/* cache features */
+extern const unsigned char Xthal_dcache_is_writeback;
+extern const unsigned char Xthal_icache_line_lockable;
+extern const unsigned char Xthal_dcache_line_lockable;
+
+/* cache attribute register control (used by other HAL routines) */
+extern unsigned xthal_get_cacheattr( void );
+extern unsigned xthal_get_icacheattr( void );
+extern unsigned xthal_get_dcacheattr( void );
+extern void     xthal_set_cacheattr( unsigned );
+extern void     xthal_set_icacheattr( unsigned );
+extern void     xthal_set_dcacheattr( unsigned );
+
+/* initialize cache support (must be called once at startup, before all other cache calls) */
+/*extern void xthal_cache_startinit( void );*/
+/* reset caches */
+/*extern void xthal_icache_reset( void );*/
+/*extern void xthal_dcache_reset( void );*/
+/* enable caches */
+extern void xthal_icache_enable( void );        /* DEPRECATED */
+extern void xthal_dcache_enable( void );        /* DEPRECATED */
+/* disable caches */
+extern void xthal_icache_disable( void );       /* DEPRECATED */
+extern void xthal_dcache_disable( void );       /* DEPRECATED */
+
+/* invalidate the caches */
+extern void xthal_icache_all_invalidate( void );
+extern void xthal_dcache_all_invalidate( void );
+extern void xthal_icache_region_invalidate( void *addr, unsigned size );
+extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
+extern void xthal_icache_line_invalidate(void *addr);
+extern void xthal_dcache_line_invalidate(void *addr);
+/* write dirty data back */
+extern void xthal_dcache_all_writeback( void );
+extern void xthal_dcache_region_writeback( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback(void *addr);
+/* write dirty data back and invalidate */
+extern void xthal_dcache_all_writeback_inv( void );
+extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback_inv(void *addr);
+/* prefetch and lock specified memory range into cache */
+extern void xthal_icache_region_lock( void *addr, unsigned size );
+extern void xthal_dcache_region_lock( void *addr, unsigned size );
+extern void xthal_icache_line_lock(void *addr);
+extern void xthal_dcache_line_lock(void *addr);
+/* unlock from cache */
+extern void xthal_icache_all_unlock( void );
+extern void xthal_dcache_all_unlock( void );
+extern void xthal_icache_region_unlock( void *addr, unsigned size );
+extern void xthal_dcache_region_unlock( void *addr, unsigned size );
+extern void xthal_icache_line_unlock(void *addr);
+extern void xthal_dcache_line_unlock(void *addr);
+
+
+/* sync icache and memory */
+extern void xthal_icache_sync( void );
+/* sync dcache and memory */
+extern void xthal_dcache_sync( void );
+
+/*----------------------------------------------------------------------
+                                Debug
+  ----------------------------------------------------------------------*/
+
+/*  1 if debug option configured, 0 if not:  */
+extern const int Xthal_debug_configured;
+
+/*  Number of instruction and data break registers:  */
+extern const int Xthal_num_ibreak;
+extern const int Xthal_num_dbreak;
+
+/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */
+extern unsigned int xthal_set_soft_break(void *addr);
+extern void         xthal_remove_soft_break(void *addr, unsigned int);
+
+
+/*----------------------------------------------------------------------
+                                Disassembler
+  ----------------------------------------------------------------------*/
+
+/*  Max expected size of the return buffer for a disassembled instruction (hint only):  */
+#define XTHAL_DISASM_BUFSIZE    80
+
+/*  Disassembly option bits for selecting what to return:  */
+#define XTHAL_DISASM_OPT_ADDR   0x0001  /* display address */
+#define XTHAL_DISASM_OPT_OPHEX  0x0002  /* display opcode bytes in hex */
+#define XTHAL_DISASM_OPT_OPCODE 0x0004  /* display opcode name (mnemonic) */
+#define XTHAL_DISASM_OPT_PARMS  0x0008  /* display parameters */
+#define XTHAL_DISASM_OPT_ALL    0x0FFF  /* display everything */
+
+/* routine to get a string for the disassembled instruction */
+extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
+                       char *buffer, unsigned buflen, unsigned options );
+
+/* routine to get the size of the next instruction. Returns 0 for
+   illegal instruction */
+extern int xthal_disassemble_size( unsigned char *instr_buf );
+
+
+/*----------------------------------------------------------------------
+                                Core Counter
+  ----------------------------------------------------------------------*/
+
+/* counter info */
+extern const unsigned char Xthal_have_ccount;   /* set if CCOUNT register present */
+extern const unsigned char Xthal_num_ccompare;  /* number of CCOMPAREn registers */
+
+/* get CCOUNT register (if not present return 0) */
+extern unsigned xthal_get_ccount(void);
+
+/* set and get CCOMPAREn registers (if not present, get returns 0) */
+extern void     xthal_set_ccompare(int, unsigned);
+extern unsigned xthal_get_ccompare(int);
+
+
+/*----------------------------------------------------------------------
+                        Instruction/Data RAM/ROM Access
+  ----------------------------------------------------------------------*/
+
+extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
+extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
+
+/*----------------------------------------------------------------------
+                           MP Synchronization
+  ----------------------------------------------------------------------*/
+extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );
+extern unsigned xthal_get_prid( void );
+
+/*extern const char  Xthal_have_s32c1i;*/
+extern const unsigned char Xthal_have_prid;
+
+
+/*----------------------------------------------------------------------
+                             Miscellaneous
+  ----------------------------------------------------------------------*/
+
+extern const unsigned int  Xthal_release_major;
+extern const unsigned int  Xthal_release_minor;
+extern const char * const  Xthal_release_name;
+extern const char * const  Xthal_release_internal;
+
+extern const unsigned char Xthal_memory_order;
+extern const unsigned char Xthal_have_windowed;
+extern const unsigned char Xthal_have_density;
+extern const unsigned char Xthal_have_booleans;
+extern const unsigned char Xthal_have_loops;
+extern const unsigned char Xthal_have_nsa;
+extern const unsigned char Xthal_have_minmax;
+extern const unsigned char Xthal_have_sext;
+extern const unsigned char Xthal_have_clamps;
+extern const unsigned char Xthal_have_mac16;
+extern const unsigned char Xthal_have_mul16;
+extern const unsigned char Xthal_have_fp;
+extern const unsigned char Xthal_have_speculation;
+extern const unsigned char Xthal_have_exceptions;
+extern const unsigned char Xthal_xea_version;
+extern const unsigned char Xthal_have_interrupts;
+extern const unsigned char Xthal_have_highlevel_interrupts;
+extern const unsigned char Xthal_have_nmi;
+
+extern const unsigned short Xthal_num_writebuffer_entries;
+
+extern const unsigned int  Xthal_build_unique_id;
+/*  Release info for hardware targeted by software upgrades:  */
+extern const unsigned int  Xthal_hw_configid0;
+extern const unsigned int  Xthal_hw_configid1;
+extern const unsigned int  Xthal_hw_release_major;
+extern const unsigned int  Xthal_hw_release_minor;
+extern const char * const  Xthal_hw_release_name;
+extern const char * const  Xthal_hw_release_internal;
+
+
+/*  Internal memories...  */
+
+extern const unsigned char Xthal_num_instrom;
+extern const unsigned char Xthal_num_instram;
+extern const unsigned char Xthal_num_datarom;
+extern const unsigned char Xthal_num_dataram;
+extern const unsigned char Xthal_num_xlmi;
+extern const unsigned int  Xthal_instrom_vaddr[1];
+extern const unsigned int  Xthal_instrom_paddr[1];
+extern const unsigned int  Xthal_instrom_size [1];
+extern const unsigned int  Xthal_instram_vaddr[1];
+extern const unsigned int  Xthal_instram_paddr[1];
+extern const unsigned int  Xthal_instram_size [1];
+extern const unsigned int  Xthal_datarom_vaddr[1];
+extern const unsigned int  Xthal_datarom_paddr[1];
+extern const unsigned int  Xthal_datarom_size [1];
+extern const unsigned int  Xthal_dataram_vaddr[1];
+extern const unsigned int  Xthal_dataram_paddr[1];
+extern const unsigned int  Xthal_dataram_size [1];
+extern const unsigned int  Xthal_xlmi_vaddr[1];
+extern const unsigned int  Xthal_xlmi_paddr[1];
+extern const unsigned int  Xthal_xlmi_size [1];
+
+
+
+/*----------------------------------------------------------------------
+                         Memory Management Unit
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_spanning_way;
+extern const unsigned char Xthal_have_identity_map;
+extern const unsigned char Xthal_have_mimic_cacheattr;
+extern const unsigned char Xthal_have_xlt_cacheattr;
+extern const unsigned char Xthal_have_cacheattr;
+extern const unsigned char Xthal_have_tlbs;
+
+extern const unsigned char Xthal_mmu_asid_bits;         /* 0 .. 8 */
+extern const unsigned char Xthal_mmu_asid_kernel;
+extern const unsigned char Xthal_mmu_rings;             /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
+extern const unsigned char Xthal_mmu_ring_bits;
+extern const unsigned char Xthal_mmu_sr_bits;
+extern const unsigned char Xthal_mmu_ca_bits;
+extern const unsigned int  Xthal_mmu_max_pte_page_size;
+extern const unsigned int  Xthal_mmu_min_pte_page_size;
+
+extern const unsigned char Xthal_itlb_way_bits;
+extern const unsigned char Xthal_itlb_ways;
+extern const unsigned char Xthal_itlb_arf_ways;
+extern const unsigned char Xthal_dtlb_way_bits;
+extern const unsigned char Xthal_dtlb_ways;
+extern const unsigned char Xthal_dtlb_arf_ways;
+
+/*  Convert between virtual and physical addresses (through static maps only):  */
+/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
+extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
+extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
+
+#if 0
+/*******************   EXPERIMENTAL AND TENTATIVE ONLY   ********************/
+
+#define XTHAL_MMU_PAGESZ_COUNT_MAX      8       /* maximum number of different page sizes */
+extern const char       Xthal_mmu_pagesz_count;         /* 0 .. 8               number of different page sizes configured */
+
+/*  Note:  the following table doesn't necessarily have page sizes in increasing order: */
+extern const char       Xthal_mmu_pagesz_log2[XTHAL_MMU_PAGESZ_COUNT_MAX];      /* 10 .. 28 (0 past count) */
+
+/*  Sorted (increasing) table of page sizes, that indexes into the above table: */
+extern const char       Xthal_mmu_pagesz_sorted[XTHAL_MMU_PAGESZ_COUNT_MAX];    /* 0 .. 7 (0 past count) */
+
+/*u32   Xthal_virtual_exceptions;*/     /* bitmask of which exceptions execute in virtual mode... */
+
+extern const char       Xthal_mmu_pte_pagesz_log2_min;  /* ?? minimum page size in PTEs */
+extern const char       Xthal_mmu_pte_pagesz_log2_max;  /* ?? maximum page size in PTEs */
+
+/*  Cache Attribute Bits Implemented by the Cache (part of the cache abstraction) */
+extern const char       Xthal_icache_fca_bits_implemented;      /* ITLB/UTLB only! */
+extern const char       Xthal_dcache_lca_bits_implemented;      /* DTLB/UTLB only! */
+extern const char       Xthal_dcache_sca_bits_implemented;      /* DTLB/UTLB only! */
+
+/*  Per TLB Parameters (Instruction, Data, Unified)  */
+struct XtHalMmuTlb      Xthal_itlb;     /* description of MMU I-TLB generic features */
+struct XtHalMmuTlb      Xthal_dtlb;     /* description of MMU D-TLB generic features */
+struct XtHalMmuTlb      Xthal_utlb;     /* description of MMU U-TLB generic features */
+
+#define XTHAL_MMU_WAYS_MAX      8       /* maximum number of ways (associativities) for each TLB */
+
+/*  Structure for common information described for each possible TLB (instruction, data and unified): */
+typedef struct XtHalMmuTlb {
+    u8          va_bits;                /* 32           (number of virtual address bits) */
+    u8          pa_bits;                /* 32           (number of physical address bits) */
+    bool        tlb_va_indexed;         /* 1    (set if TLB is indexed by virtual address) */
+    bool        tlb_va_tagged;          /* 0    (set if TLB is tagged by virtual address) */
+    bool        cache_va_indexed;       /* 1    (set if cache is indexed by virtual address) */
+    bool        cache_va_tagged;        /* 0    (set if cache is tagged by virtual address) */
+    /*bool      (whether page tables are traversed in vaddr sorted order, paddr sorted order, ...) */
+    /*u8        (set of available page attribute bits, other than cache attribute bits defined above) */
+    /*u32       (various masks for pages, MMU table/TLB entries, etc.) */
+    u8          way_count;              /* 0 .. 8       (number of ways, a.k.a. associativities, for this TLB) */
+    XtHalMmuTlbWay *    ways[XTHAL_MMU_WAYS_MAX];       /* pointers to per-way parms for each way */
+} XtHalMmuTlb;
+
+/*  Per TLB Way (Per Associativity) Parameters  */
+typedef struct XtHalMmuTlbWay {
+     u32        index_count_log2;       /* 0 .. 4 */
+     u32        pagesz_mask;            /* 0 .. 2^pagesz_count - 1      (each bit corresponds to a size */
+                                        /*              defined in the Xthal_mmu_pagesz_log2[] table) */
+     u32        vpn_const_mask;
+     u32        vpn_const_value;
+     u64        ppn_const_mask;         /* future may support pa_bits > 32 */
+     u64        ppn_const_value;
+     u32        ppn_id_mask;            /* paddr bits taken directly from vaddr */
+     bool       backgnd_match;          /* 0 or 1 */
+     /*  These are defined in terms of the XTHAL_CACHE_xxx bits: */
+     u8         fca_const_mask;         /* ITLB/UTLB only! */
+     u8         fca_const_value;        /* ITLB/UTLB only! */
+     u8         lca_const_mask;         /* DTLB/UTLB only! */
+     u8         lca_const_value;        /* DTLB/UTLB only! */
+     u8         sca_const_mask;         /* DTLB/UTLB only! */
+     u8         sca_const_value;        /* DTLB/UTLB only! */
+     /*  These define an encoding that map 5 bits in TLB and PTE entries to */
+     /*  8 bits (FCA, ITLB), 16 bits (LCA+SCA, DTLB) or 24 bits (FCA+LCA+SCA, UTLB): */
+     /*  (they may be moved to struct XtHalMmuTlb) */
+     u8         ca_bits;                /* number of bits in TLB/PTE entries for cache attributes */
+     u32 *      ca_map;                 /* pointer to array of 2^ca_bits entries of FCA+LCA+SCA bits */
+} XtHalMmuTlbWay;
+
+/*
+ *  The way to determine whether protection support is present in core
+ *  is to [look at Xthal_mmu_rings ???].
+ *  Give info on memory requirements for MMU tables and other in-memory
+ *  data structures (globally, per task, base and per page, etc.) - whatever bounds can be calculated.
+ */
+
+
+/*  Default vectors:  */
+xthal_immu_fetch_miss_vector
+xthal_dmmu_load_miss_vector
+xthal_dmmu_store_miss_vector
+
+/*  Functions called when a fault is detected:  */
+typedef void (XtHalMmuFaultFunc)( unsigned vaddr, ...context... );
+/*  Or, */
+/*      a? = vaddr */
+/*      a? = context... */
+/*      PS.xxx = xxx */
+XtHalMMuFaultFunc *Xthal_immu_fetch_fault_func;
+XtHalMMuFaultFunc *Xthal_dmmu_load_fault_func;
+XtHalMMuFaultFunc *Xthal_dmmu_store_fault_func;
+
+/*  Default Handlers:  */
+/*  The user and/or kernel exception handlers may jump to these handlers to handle the relevant exceptions,
+ *  according to the value of EXCCAUSE.  The exact register state on entry to these handlers is TBD.  */
+/*  When multiple TLB entries match (hit) on the same access:  */
+xthal_immu_fetch_multihit_handler
+xthal_dmmu_load_multihit_handler
+xthal_dmmu_store_multihit_handler
+/*  Protection violations according to cache attributes, and other cache attribute mismatches:  */
+xthal_immu_fetch_attr_handler
+xthal_dmmu_load_attr_handler
+xthal_dmmu_store_attr_handler
+/*  Protection violations due to insufficient ring level:  */
+xthal_immu_fetch_priv_handler
+xthal_dmmu_load_priv_handler
+xthal_dmmu_store_priv_handler
+/*  Alignment exception handlers (if supported by the particular Xtensa MMU configuration):  */
+xthal_dmmu_load_align_handler
+xthal_dmmu_store_align_handler
+
+/*  Or, alternatively, the OS user and/or kernel exception handlers may simply jump to the
+ *  following entry points which will handle any values of EXCCAUSE not handled by the OS:  */
+xthal_user_exc_default_handler
+xthal_kernel_exc_default_handler
+
+#endif /*0*/
+
+#ifdef INCLUDE_DEPRECATED_HAL_CODE
+extern const unsigned char Xthal_have_old_exc_arch;
+extern const unsigned char Xthal_have_mmu;
+extern const unsigned int  Xthal_num_regs;
+extern const unsigned char Xthal_num_iroms;
+extern const unsigned char Xthal_num_irams;
+extern const unsigned char Xthal_num_droms;
+extern const unsigned char Xthal_num_drams;
+extern const unsigned int  Xthal_configid0;
+extern const unsigned int  Xthal_configid1;
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
+#define XTHAL_24_BIT_BREAK              0x80000000
+#define XTHAL_16_BIT_BREAK              0x40000000
+extern const unsigned short     Xthal_ill_inst_16[16];
+#define XTHAL_DEST_REG          0xf0000000      /* Mask for destination register */
+#define XTHAL_DEST_REG_INST     0x08000000      /* Branch address is in register */
+#define XTHAL_DEST_REL_INST     0x04000000      /* Branch address is relative */
+#define XTHAL_RFW_INST          0x00000800
+#define XTHAL_RFUE_INST         0x00000400
+#define XTHAL_RFI_INST          0x00000200
+#define XTHAL_RFE_INST          0x00000100
+#define XTHAL_RET_INST          0x00000080
+#define XTHAL_BREAK_INST        0x00000040
+#define XTHAL_SYSCALL_INST      0x00000020
+#define XTHAL_LOOP_END          0x00000010      /* Not set by xthal_inst_type */
+#define XTHAL_JUMP_INST         0x00000008      /* Call or jump instruction */
+#define XTHAL_BRANCH_INST       0x00000004      /* Branch instruction */
+#define XTHAL_24_BIT_INST       0x00000002
+#define XTHAL_16_BIT_INST   0x00000001
+typedef struct xthal_state {
+    unsigned    pc;
+    unsigned    ar[16];
+    unsigned    lbeg;
+    unsigned    lend;
+    unsigned    lcount;
+    unsigned    extra_ptr;
+    unsigned    cpregs_ptr[XTHAL_MAX_CPS];
+} XTHAL_STATE;
+extern unsigned int xthal_inst_type(void *addr);
+extern unsigned int xthal_branch_addr(void *addr);
+extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
+#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!__ASSEMBLY__ */
+
+#endif /*XTENSA_HAL_H*/
+
diff --git a/include/asm-xtensa/xtensa/simcall.h b/include/asm-xtensa/xtensa/simcall.h
new file mode 100644
index 000000000000..a2b868929a49
--- /dev/null
+++ b/include/asm-xtensa/xtensa/simcall.h
@@ -0,0 +1,130 @@
+#ifndef SIMCALL_INCLUDED
+#define SIMCALL_INCLUDED
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/simcall.h  -  Simulator call numbers
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+/*
+ *  System call like services offered by the simulator host.
+ *  These are modeled after the Linux 2.4 kernel system calls
+ *  for Xtensa processors.  However not all system calls and
+ *  not all functionality of a given system call are implemented,
+ *  or necessarily have well defined or equivalent semantics in
+ *  the context of a simulation (as opposed to a Unix kernel).
+ *
+ *  These services behave largely as if they had been invoked
+ *  as a task in the simulator host's operating system
+ *  (eg. files accessed are those of the simulator host).
+ *  However, these SIMCALLs model a virtual operating system
+ *  so that various definitions, bit assignments etc
+ *  (eg. open mode bits, errno values, etc) are independent
+ *  of the host operating system used to run the simulation.
+ *  Rather these definitions are specific to the Xtensa ISS.
+ *  This way Xtensa ISA code written to use these SIMCALLs
+ *  can (in principle) be simulated on any host.
+ *
+ *  Up to 6 parameters are passed in registers a3 to a8
+ *  (note the 6th parameter isn't passed on the stack,
+ *   unlike windowed function calling conventions).
+ *  The return value is in a2.  A negative value in the
+ *  range -4096 to -1 indicates a negated error code to be
+ *  reported in errno with a return value of -1, otherwise
+ *  the value in a2 is returned as is.
+ */
+
+/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
+
+#define SYS_nop         0       /* n/a - setup; used to flush register windows */
+#define SYS_exit        1       /*x*/
+#define SYS_fork        2
+#define SYS_read        3       /*x*/
+#define SYS_write       4       /*x*/
+#define SYS_open        5       /*x*/
+#define SYS_close       6       /*x*/
+#define SYS_rename      7       /*x 38 - waitpid */
+#define SYS_creat       8       /*x*/
+#define SYS_link        9       /*x (not implemented on WIN32) */
+#define SYS_unlink      10      /*x*/
+#define SYS_execv       11      /* n/a - execve */
+#define SYS_execve      12      /* 11 - chdir */
+#define SYS_pipe        13      /* 42 - time */
+#define SYS_stat        14      /* 106 - mknod */
+#define SYS_chmod       15
+#define SYS_chown       16      /* 202 - lchown */
+#define SYS_utime       17      /* 30 - break */
+#define SYS_wait        18      /* n/a - oldstat */
+#define SYS_lseek       19      /*x*/
+#define SYS_getpid      20
+#define SYS_isatty      21      /* n/a - mount */
+#define SYS_fstat       22      /* 108 - oldumount */
+#define SYS_time        23      /* 13 - setuid */
+#define SYS_gettimeofday 24     /*x 78 - getuid (not implemented on WIN32) */
+#define SYS_times       25      /*X 43 - stime (Xtensa-specific implementation) */
+#define SYS_socket      26
+#define SYS_sendto      27
+#define SYS_recvfrom    28
+#define SYS_select_one  29      /* not compitible select, one file descriptor at the time */
+#define SYS_bind        30
+#define SYS_ioctl       31
+
+/*
+ *  Other...
+ */
+#define SYS_iss_argc      1000  /* returns value of argc */
+#define SYS_iss_argv_size 1001  /* bytes needed for argv & arg strings */
+#define SYS_iss_set_argv  1002  /* saves argv & arg strings at given addr */
+
+/*
+ * SIMCALLs for the ferret memory debugger. All are invoked by
+ * libferret.a ...  ( Xtensa/Target-Libs/ferret )
+ */
+#define SYS_ferret           1010
+#define SYS_malloc           1011
+#define SYS_free             1012
+#define SYS_more_heap        1013
+#define SYS_no_heap          1014
+
+
+/*
+ *  Extra SIMCALLs for GDB:
+ */
+#define SYS_gdb_break         -1        /* invoked by XTOS on user exceptions if EPC points
+                                           to a break.n/break, regardless of cause! */
+#define SYS_xmon_out          -2        /* invoked by XMON: ... */
+#define SYS_xmon_in           -3        /* invoked by XMON: ... */
+#define SYS_xmon_flush        -4        /* invoked by XMON: ... */
+#define SYS_gdb_abort         -5        /* invoked by XTOS in _xtos_panic() */
+#define SYS_gdb_illegal_inst  -6        /* invoked by XTOS for illegal instructions (too deeply) */
+#define SYS_xmon_init         -7        /* invoked by XMON: ... */
+#define SYS_gdb_enter_sktloop -8        /* invoked by XTOS on debug exceptions */
+
+/*
+ *  SIMCALLs for vxWorks xtiss BSP:
+ */
+#define SYS_setup_ppp_pipes   -83
+#define SYS_log_msg           -84
+
+/*
+ *  Test SIMCALLs:
+ */
+#define SYS_test_write_state  -100
+#define SYS_test_read_state   -101
+
+/*
+ * SYS_select_one specifiers
+ */
+#define  XTISS_SELECT_ONE_READ    1
+#define  XTISS_SELECT_ONE_WRITE   2
+#define  XTISS_SELECT_ONE_EXCEPT  3
+
+#endif /* !SIMCALL_INCLUDED */
diff --git a/include/asm-xtensa/xtensa/xt2000-uart.h b/include/asm-xtensa/xtensa/xt2000-uart.h
new file mode 100644
index 000000000000..0154460f0ed8
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xt2000-uart.h
@@ -0,0 +1,155 @@
+#ifndef _uart_h_included_
+#define _uart_h_included_
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/xt2000-uart.h -- NatSemi PC16552D DUART
+ * definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/xt2000.h>
+
+
+/* 16550 UART DEVICE REGISTERS
+   The XT2000 board aligns each register to a 32-bit word but the UART device only uses
+   one byte of the word, which is the least-significant byte regardless of the
+   endianness of the core (ie. byte offset 0 for little-endian and 3 for big-endian).
+   So if using word accesses then endianness doesn't matter.
+   The macros provided here do that.
+*/
+struct uart_dev_s {
+  union {
+    unsigned int rxb;   /* DLAB=0: receive buffer, read-only */
+    unsigned int txb;   /* DLAB=0: transmit buffer, write-only */
+    unsigned int dll;   /* DLAB=1: divisor, least-significant byte latch (was write-only?) */
+  } w0;
+  union {
+    unsigned int ier;   /* DLAB=0: interrupt-enable register (was write-only?) */
+    unsigned int dlm;   /* DLAB=1: divisor, most-significant byte latch (was write-only?) */
+  } w1;
+
+  union {
+    unsigned int isr;   /* DLAB=0: interrupt status register, read-only */
+    unsigned int fcr;   /* DLAB=0: FIFO control register, write-only */
+    unsigned int afr;   /* DLAB=1: alternate function register */
+  } w2;
+
+  unsigned int lcr;     /* line control-register, write-only */
+  unsigned int mcr;     /* modem control-regsiter, write-only */
+  unsigned int lsr;     /* line status register, read-only */
+  unsigned int msr;     /* modem status register, read-only */
+  unsigned int scr;     /* scratch regsiter, read/write */
+};
+
+#define _RXB(u) ((u)->w0.rxb)
+#define _TXB(u) ((u)->w0.txb)
+#define _DLL(u) ((u)->w0.dll)
+#define _IER(u) ((u)->w1.ier)
+#define _DLM(u) ((u)->w1.dlm)
+#define _ISR(u) ((u)->w2.isr)
+#define _FCR(u) ((u)->w2.fcr)
+#define _AFR(u) ((u)->w2.afr)
+#define _LCR(u) ((u)->lcr)
+#define _MCR(u) ((u)->mcr)
+#define _LSR(u) ((u)->lsr)
+#define _MSR(u) ((u)->msr)
+#define _SCR(u) ((u)->scr)
+
+typedef volatile struct uart_dev_s uart_dev_t;
+
+/* IER bits */
+#define RCVR_DATA_REG_INTENABLE 0x01
+#define XMIT_HOLD_REG_INTENABLE    0x02
+#define RCVR_STATUS_INTENABLE   0x04
+#define MODEM_STATUS_INTENABLE     0x08
+
+/* FCR bits */
+#define _FIFO_ENABLE      0x01
+#define RCVR_FIFO_RESET  0x02
+#define XMIT_FIFO_RESET  0x04
+#define DMA_MODE_SELECT  0x08
+#define RCVR_TRIGGER_LSB 0x40
+#define RCVR_TRIGGER_MSB 0x80
+
+/* AFR bits */
+#define AFR_CONC_WRITE  0x01
+#define AFR_BAUDOUT_SEL 0x02
+#define AFR_RXRDY_SEL   0x04
+
+/* ISR bits */
+#define INT_STATUS(r)   ((r)&1)
+#define INT_PRIORITY(r) (((r)>>1)&0x7)
+
+/* LCR bits */
+#define WORD_LENGTH(n)  (((n)-5)&0x3)
+#define STOP_BIT_ENABLE 0x04
+#define PARITY_ENABLE   0x08
+#define EVEN_PARITY     0x10
+#define FORCE_PARITY    0x20
+#define XMIT_BREAK      0x40
+#define DLAB_ENABLE     0x80
+
+/* MCR bits */
+#define _DTR 0x01
+#define _RTS 0x02
+#define _OP1 0x04
+#define _OP2 0x08
+#define LOOP_BACK 0x10
+
+/* LSR Bits */
+#define RCVR_DATA_READY 0x01
+#define OVERRUN_ERROR   0x02
+#define PARITY_ERROR    0x04
+#define FRAMING_ERROR   0x08
+#define BREAK_INTERRUPT 0x10
+#define XMIT_HOLD_EMPTY 0x20
+#define XMIT_EMPTY      0x40
+#define FIFO_ERROR      0x80
+#define RCVR_READY(u)   (_LSR(u)&RCVR_DATA_READY)
+#define XMIT_READY(u)   (_LSR(u)&XMIT_HOLD_EMPTY)
+
+/* MSR bits */
+#define _RDR       0x01
+#define DELTA_DSR 0x02
+#define DELTA_RI  0x04
+#define DELTA_CD  0x08
+#define _CTS       0x10
+#define _DSR       0x20
+#define _RI        0x40
+#define _CD        0x80
+
+/* prototypes */
+void uart_init( uart_dev_t *u, int bitrate );
+void uart_out( uart_dev_t *u, char c );
+void uart_puts( uart_dev_t *u, char *s );
+char uart_in( uart_dev_t *u );
+void uart_enable_rcvr_int( uart_dev_t *u );
+void uart_disable_rcvr_int( uart_dev_t *u );
+
+#ifdef DUART16552_1_VADDR
+/*  DUART present.  */
+#define DUART_1_BASE    (*(uart_dev_t*)DUART16552_1_VADDR)
+#define DUART_2_BASE    (*(uart_dev_t*)DUART16552_2_VADDR)
+#define UART1_PUTS(s)   uart_puts( &DUART_1_BASE, s )
+#define UART2_PUTS(s)   uart_puts( &DUART_2_BASE, s )
+#else
+/*  DUART not configured, use dummy placeholders to allow compiles to work.  */
+#define DUART_1_BASE    (*(uart_dev_t*)0)
+#define DUART_2_BASE    (*(uart_dev_t*)0)
+#define UART1_PUTS(s)
+#define UART2_PUTS(s)
+#endif
+
+/*  Compute 16-bit divisor for baudrate generator, with rounding:  */
+#define DUART_DIVISOR(crystal,speed)    (((crystal)/16 + (speed)/2)/(speed))
+
+#endif /*_uart_h_included_*/
+
diff --git a/include/asm-xtensa/xtensa/xt2000.h b/include/asm-xtensa/xtensa/xt2000.h
new file mode 100644
index 000000000000..703a45002f8f
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xt2000.h
@@ -0,0 +1,408 @@
+#ifndef _INC_XT2000_H_
+#define _INC_XT2000_H_
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ * include/asm-xtensa/xtensa/xt2000.h - Definitions specific to the
+ * Tensilica XT2000 Emulation Board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h>
+
+
+/*
+ *  Default assignment of XT2000 devices to external interrupts.
+ */
+
+/*  Ethernet interrupt:  */
+#ifdef XCHAL_EXTINT3_NUM
+#define SONIC83934_INTNUM       XCHAL_EXTINT3_NUM
+#define SONIC83934_INTLEVEL     XCHAL_EXTINT3_LEVEL
+#define SONIC83934_INTMASK      XCHAL_EXTINT3_MASK
+#else
+#define SONIC83934_INTMASK      0
+#endif
+
+/*  DUART channel 1 interrupt (P1 - console):  */
+#ifdef XCHAL_EXTINT4_NUM
+#define DUART16552_1_INTNUM     XCHAL_EXTINT4_NUM
+#define DUART16552_1_INTLEVEL   XCHAL_EXTINT4_LEVEL
+#define DUART16552_1_INTMASK    XCHAL_EXTINT4_MASK
+#else
+#define DUART16552_1_INTMASK    0
+#endif
+
+/*  DUART channel 2 interrupt (P2 - 2nd serial port):  */
+#ifdef XCHAL_EXTINT5_NUM
+#define DUART16552_2_INTNUM     XCHAL_EXTINT5_NUM
+#define DUART16552_2_INTLEVEL   XCHAL_EXTINT5_LEVEL
+#define DUART16552_2_INTMASK    XCHAL_EXTINT5_MASK
+#else
+#define DUART16552_2_INTMASK    0
+#endif
+
+/*  FPGA-combined PCI/etc interrupts:  */
+#ifdef XCHAL_EXTINT6_NUM
+#define XT2000_FPGAPCI_INTNUM   XCHAL_EXTINT6_NUM
+#define XT2000_FPGAPCI_INTLEVEL XCHAL_EXTINT6_LEVEL
+#define XT2000_FPGAPCI_INTMASK  XCHAL_EXTINT6_MASK
+#else
+#define XT2000_FPGAPCI_INTMASK  0
+#endif
+
+
+
+/*
+ *  Device addresses.
+ *
+ *  Note:  for endianness-independence, use 32-bit loads and stores for all
+ *  register accesses to Ethernet, DUART and LED devices.  Undefined bits
+ *  may need to be masked out if needed when reading if the actual register
+ *  size is smaller than 32 bits.
+ *
+ *  Note:  XT2000 bus byte lanes are defined in terms of msbyte and lsbyte
+ *  relative to the processor.  So 32-bit registers are accessed consistently
+ *  from both big and little endian processors.  However, this means byte
+ *  sequences are not consistent between big and little endian processors.
+ *  This is fine for RAM, and for ROM if ROM is created for a specific
+ *  processor (and thus has correct byte sequences).  However this may be
+ *  unexpected for Flash, which might contain a file-system that one wants
+ *  to use for multiple processor configurations (eg. the Flash might contain
+ *  the Ethernet card's address, endianness-independent application data, etc).
+ *  That is, byte sequences written in Flash by a core of a given endianness
+ *  will be byte-swapped when seen by a core of the other endianness.
+ *  Someone implementing an endianness-independent Flash file system will
+ *  likely handle this byte-swapping issue in the Flash driver software.
+ */
+
+#define DUART16552_XTAL_FREQ    18432000        /* crystal frequency in Hz */
+#define XTBOARD_FLASH_MAXSIZE   0x4000000       /* 64 MB (max; depends on what is socketed!) */
+#define XTBOARD_EPROM_MAXSIZE   0x0400000       /* 4 MB (max; depends on what is socketed!) */
+#define XTBOARD_EEPROM_MAXSIZE  0x0080000       /* 512 kB (max; depends on what is socketed!) */
+#define XTBOARD_ASRAM_SIZE      0x0100000       /* 1 MB */
+#define XTBOARD_PCI_MEM_SIZE    0x8000000       /* 128 MB (allocated) */
+#define XTBOARD_PCI_IO_SIZE     0x1000000       /* 16 MB (allocated) */
+
+#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
+/*  PCI memory space:  */
+# define XTBOARD_PCI_MEM_PADDR  (XSHAL_IOBLOCK_BYPASS_PADDR+0x0000000)
+/*  Socketed Flash (eg. 2 x 16-bit devices):  */
+# define XTBOARD_FLASH_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0x8000000)
+/*  PCI I/O space:  */
+# define XTBOARD_PCI_IO_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xC000000)
+/*  V3 PCI interface chip register/config space:  */
+# define XTBOARD_V3PCI_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD000000)
+/*  Bus Interface registers:  */
+# define XTBOARD_BUSINT_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xD010000)
+/*  FPGA registers:  */
+# define XT2000_FPGAREGS_PADDR  (XSHAL_IOBLOCK_BYPASS_PADDR+0xD020000)
+/*  SONIC SN83934 Ethernet controller/transceiver:  */
+# define SONIC83934_PADDR       (XSHAL_IOBLOCK_BYPASS_PADDR+0xD030000)
+/*  8-character bitmapped LED display:  */
+# define XTBOARD_LED_PADDR      (XSHAL_IOBLOCK_BYPASS_PADDR+0xD040000)
+/*  National-Semi PC16552D DUART:  */
+# define DUART16552_1_PADDR     (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050020)  /* channel 1 (P1 - console) */
+# define DUART16552_2_PADDR     (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050000)  /* channel 2 (P2) */
+/*  Asynchronous Static RAM:  */
+# define XTBOARD_ASRAM_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD400000)
+/*  8-bit EEPROM:  */
+# define XTBOARD_EEPROM_PADDR   (XSHAL_IOBLOCK_BYPASS_PADDR+0xD600000)
+/*  2 x 16-bit EPROMs:  */
+# define XTBOARD_EPROM_PADDR    (XSHAL_IOBLOCK_BYPASS_PADDR+0xD800000)
+#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
+
+/*  These devices might be accessed cached:  */
+#ifdef XSHAL_IOBLOCK_CACHED_PADDR
+# define XTBOARD_PCI_MEM_CACHED_PADDR   (XSHAL_IOBLOCK_CACHED_PADDR+0x0000000)
+# define XTBOARD_FLASH_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0x8000000)
+# define XTBOARD_ASRAM_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0xD400000)
+# define XTBOARD_EEPROM_CACHED_PADDR    (XSHAL_IOBLOCK_CACHED_PADDR+0xD600000)
+# define XTBOARD_EPROM_CACHED_PADDR     (XSHAL_IOBLOCK_CACHED_PADDR+0xD800000)
+#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
+
+
+/***  Same thing over again, this time with virtual addresses:  ***/
+
+#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
+/*  PCI memory space:  */
+# define XTBOARD_PCI_MEM_VADDR  (XSHAL_IOBLOCK_BYPASS_VADDR+0x0000000)
+/*  Socketed Flash (eg. 2 x 16-bit devices):  */
+# define XTBOARD_FLASH_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0x8000000)
+/*  PCI I/O space:  */
+# define XTBOARD_PCI_IO_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xC000000)
+/*  V3 PCI interface chip register/config space:  */
+# define XTBOARD_V3PCI_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD000000)
+/*  Bus Interface registers:  */
+# define XTBOARD_BUSINT_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xD010000)
+/*  FPGA registers:  */
+# define XT2000_FPGAREGS_VADDR  (XSHAL_IOBLOCK_BYPASS_VADDR+0xD020000)
+/*  SONIC SN83934 Ethernet controller/transceiver:  */
+# define SONIC83934_VADDR       (XSHAL_IOBLOCK_BYPASS_VADDR+0xD030000)
+/*  8-character bitmapped LED display:  */
+# define XTBOARD_LED_VADDR      (XSHAL_IOBLOCK_BYPASS_VADDR+0xD040000)
+/*  National-Semi PC16552D DUART:  */
+# define DUART16552_1_VADDR     (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050020)  /* channel 1 (P1 - console) */
+# define DUART16552_2_VADDR     (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050000)  /* channel 2 (P2) */
+/*  Asynchronous Static RAM:  */
+# define XTBOARD_ASRAM_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD400000)
+/*  8-bit EEPROM:  */
+# define XTBOARD_EEPROM_VADDR   (XSHAL_IOBLOCK_BYPASS_VADDR+0xD600000)
+/*  2 x 16-bit EPROMs:  */
+# define XTBOARD_EPROM_VADDR    (XSHAL_IOBLOCK_BYPASS_VADDR+0xD800000)
+#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
+
+/*  These devices might be accessed cached:  */
+#ifdef XSHAL_IOBLOCK_CACHED_VADDR
+# define XTBOARD_PCI_MEM_CACHED_VADDR   (XSHAL_IOBLOCK_CACHED_VADDR+0x0000000)
+# define XTBOARD_FLASH_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0x8000000)
+# define XTBOARD_ASRAM_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0xD400000)
+# define XTBOARD_EEPROM_CACHED_VADDR    (XSHAL_IOBLOCK_CACHED_VADDR+0xD600000)
+# define XTBOARD_EPROM_CACHED_VADDR     (XSHAL_IOBLOCK_CACHED_VADDR+0xD800000)
+#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
+
+
+/*  System ROM:  */
+#define XTBOARD_ROM_SIZE                XSHAL_ROM_SIZE
+#ifdef XSHAL_ROM_VADDR
+#define XTBOARD_ROM_VADDR               XSHAL_ROM_VADDR
+#endif
+#ifdef XSHAL_ROM_PADDR
+#define XTBOARD_ROM_PADDR               XSHAL_ROM_PADDR
+#endif
+
+/*  System RAM:  */
+#define XTBOARD_RAM_SIZE                XSHAL_RAM_SIZE
+#ifdef XSHAL_RAM_VADDR
+#define XTBOARD_RAM_VADDR               XSHAL_RAM_VADDR
+#endif
+#ifdef XSHAL_RAM_PADDR
+#define XTBOARD_RAM_PADDR               XSHAL_RAM_PADDR
+#endif
+#define XTBOARD_RAM_BYPASS_VADDR        XSHAL_RAM_BYPASS_VADDR
+#define XTBOARD_RAM_BYPASS_PADDR        XSHAL_RAM_BYPASS_PADDR
+
+
+
+/*
+ *  Things that depend on device addresses.
+ */
+
+
+#define XTBOARD_CACHEATTR_WRITEBACK     XSHAL_XT2000_CACHEATTR_WRITEBACK
+#define XTBOARD_CACHEATTR_WRITEALLOC    XSHAL_XT2000_CACHEATTR_WRITEALLOC
+#define XTBOARD_CACHEATTR_WRITETHRU     XSHAL_XT2000_CACHEATTR_WRITETHRU
+#define XTBOARD_CACHEATTR_BYPASS        XSHAL_XT2000_CACHEATTR_BYPASS
+#define XTBOARD_CACHEATTR_DEFAULT       XSHAL_XT2000_CACHEATTR_DEFAULT
+
+#define XTBOARD_BUSINT_PIPE_REGIONS     XSHAL_XT2000_PIPE_REGIONS
+#define XTBOARD_BUSINT_SDRAM_REGIONS    XSHAL_XT2000_SDRAM_REGIONS
+
+
+
+/*
+ *  BusLogic (FPGA) registers.
+ *  All these registers are normally accessed using 32-bit loads/stores.
+ */
+
+/*  Register offsets:  */
+#define XT2000_DATECD_OFS       0x00    /* date code (read-only) */
+#define XT2000_STSREG_OFS       0x04    /* status (read-only) */
+#define XT2000_SYSLED_OFS       0x08    /* system LED */
+#define XT2000_WRPROT_OFS       0x0C    /* write protect */
+#define XT2000_SWRST_OFS        0x10    /* software reset */
+#define XT2000_SYSRST_OFS       0x14    /* system (peripherals) reset */
+#define XT2000_IMASK_OFS        0x18    /* interrupt mask */
+#define XT2000_ISTAT_OFS        0x1C    /* interrupt status */
+#define XT2000_V3CFG_OFS        0x20    /* V3 config (V320 PCI) */
+
+/*  Physical register addresses:  */
+#ifdef XT2000_FPGAREGS_PADDR
+#define XT2000_DATECD_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_DATECD_OFS)
+#define XT2000_STSREG_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_STSREG_OFS)
+#define XT2000_SYSLED_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_SYSLED_OFS)
+#define XT2000_WRPROT_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_WRPROT_OFS)
+#define XT2000_SWRST_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_SWRST_OFS)
+#define XT2000_SYSRST_PADDR     (XT2000_FPGAREGS_PADDR+XT2000_SYSRST_OFS)
+#define XT2000_IMASK_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_IMASK_OFS)
+#define XT2000_ISTAT_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_ISTAT_OFS)
+#define XT2000_V3CFG_PADDR      (XT2000_FPGAREGS_PADDR+XT2000_V3CFG_OFS)
+#endif
+
+/*  Virtual register addresses:  */
+#ifdef XT2000_FPGAREGS_VADDR
+#define XT2000_DATECD_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_DATECD_OFS)
+#define XT2000_STSREG_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_STSREG_OFS)
+#define XT2000_SYSLED_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_SYSLED_OFS)
+#define XT2000_WRPROT_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_WRPROT_OFS)
+#define XT2000_SWRST_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_SWRST_OFS)
+#define XT2000_SYSRST_VADDR     (XT2000_FPGAREGS_VADDR+XT2000_SYSRST_OFS)
+#define XT2000_IMASK_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_IMASK_OFS)
+#define XT2000_ISTAT_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_ISTAT_OFS)
+#define XT2000_V3CFG_VADDR      (XT2000_FPGAREGS_VADDR+XT2000_V3CFG_OFS)
+/*  Register access (for C code):  */
+#define XT2000_DATECD_REG       (*(volatile unsigned*) XT2000_DATECD_VADDR)
+#define XT2000_STSREG_REG       (*(volatile unsigned*) XT2000_STSREG_VADDR)
+#define XT2000_SYSLED_REG       (*(volatile unsigned*) XT2000_SYSLED_VADDR)
+#define XT2000_WRPROT_REG       (*(volatile unsigned*) XT2000_WRPROT_VADDR)
+#define XT2000_SWRST_REG        (*(volatile unsigned*) XT2000_SWRST_VADDR)
+#define XT2000_SYSRST_REG       (*(volatile unsigned*) XT2000_SYSRST_VADDR)
+#define XT2000_IMASK_REG        (*(volatile unsigned*) XT2000_IMASK_VADDR)
+#define XT2000_ISTAT_REG        (*(volatile unsigned*) XT2000_ISTAT_VADDR)
+#define XT2000_V3CFG_REG        (*(volatile unsigned*) XT2000_V3CFG_VADDR)
+#endif
+
+/*  DATECD (date code) bit fields:  */
+
+/*  BCD-coded month (01..12):  */
+#define XT2000_DATECD_MONTH_SHIFT       24
+#define XT2000_DATECD_MONTH_BITS        8
+#define XT2000_DATECD_MONTH_MASK        0xFF000000
+/*  BCD-coded day (01..31):  */
+#define XT2000_DATECD_DAY_SHIFT         16
+#define XT2000_DATECD_DAY_BITS          8
+#define XT2000_DATECD_DAY_MASK          0x00FF0000
+/*  BCD-coded year (2001..9999):  */
+#define XT2000_DATECD_YEAR_SHIFT        0
+#define XT2000_DATECD_YEAR_BITS         16
+#define XT2000_DATECD_YEAR_MASK         0x0000FFFF
+
+/*  STSREG (status) bit fields:  */
+
+/*  Switch SW3 setting bit fields (0=off/up, 1=on/down):  */
+#define XT2000_STSREG_SW3_SHIFT         0
+#define XT2000_STSREG_SW3_BITS          4
+#define XT2000_STSREG_SW3_MASK          0x0000000F
+/*  Boot-select bits of switch SW3:  */
+#define XT2000_STSREG_BOOTSEL_SHIFT     0
+#define XT2000_STSREG_BOOTSEL_BITS      2
+#define XT2000_STSREG_BOOTSEL_MASK      0x00000003
+/*  Boot-select values:  */
+#define XT2000_STSREG_BOOTSEL_FLASH     0
+#define XT2000_STSREG_BOOTSEL_EPROM16   1
+#define XT2000_STSREG_BOOTSEL_PROM8     2
+#define XT2000_STSREG_BOOTSEL_ASRAM     3
+/*  User-defined bits of switch SW3:  */
+#define XT2000_STSREG_SW3_2_SHIFT       2
+#define XT2000_STSREG_SW3_2_MASK        0x00000004
+#define XT2000_STSREG_SW3_3_SHIFT       3
+#define XT2000_STSREG_SW3_3_MASK        0x00000008
+
+/*  SYSLED (system LED) bit fields:  */
+
+/*  LED control bit (0=off, 1=on):  */
+#define XT2000_SYSLED_LEDON_SHIFT       0
+#define XT2000_SYSLED_LEDON_MASK        0x00000001
+
+/*  WRPROT (write protect) bit fields (0=writable, 1=write-protected [default]):  */
+
+/*  Flash write protect:  */
+#define XT2000_WRPROT_FLWP_SHIFT        0
+#define XT2000_WRPROT_FLWP_MASK         0x00000001
+/*  Reserved but present write protect bits:  */
+#define XT2000_WRPROT_WRP_SHIFT         1
+#define XT2000_WRPROT_WRP_BITS          7
+#define XT2000_WRPROT_WRP_MASK          0x000000FE
+
+/*  SWRST (software reset; allows s/w to generate power-on equivalent reset):  */
+
+/*  Software reset bits:  */
+#define XT2000_SWRST_SWR_SHIFT          0
+#define XT2000_SWRST_SWR_BITS           16
+#define XT2000_SWRST_SWR_MASK           0x0000FFFF
+/*  Software reset value -- writing this value resets the board:  */
+#define XT2000_SWRST_RESETVALUE         0x0000DEAD
+
+/*  SYSRST (system reset; controls reset of individual peripherals):  */
+
+/*  All-device reset:  */
+#define XT2000_SYSRST_ALL_SHIFT         0
+#define XT2000_SYSRST_ALL_BITS          4
+#define XT2000_SYSRST_ALL_MASK          0x0000000F
+/*  HDSP-2534 LED display reset (1=reset, 0=nothing):  */
+#define XT2000_SYSRST_LED_SHIFT         0
+#define XT2000_SYSRST_LED_MASK          0x00000001
+/*  Sonic DP83934 Ethernet controller reset (1=reset, 0=nothing):  */
+#define XT2000_SYSRST_SONIC_SHIFT       1
+#define XT2000_SYSRST_SONIC_MASK        0x00000002
+/*  DP16552 DUART reset (1=reset, 0=nothing):  */
+#define XT2000_SYSRST_DUART_SHIFT       2
+#define XT2000_SYSRST_DUART_MASK        0x00000004
+/*  V3 V320 PCI bridge controller reset (1=reset, 0=nothing):  */
+#define XT2000_SYSRST_V3_SHIFT          3
+#define XT2000_SYSRST_V3_MASK           0x00000008
+
+/*  IMASK (interrupt mask; 0=disable, 1=enable):  */
+/*  ISTAT (interrupt status; 0=inactive, 1=pending):  */
+
+/*  PCI INTP interrupt:  */
+#define XT2000_INTMUX_PCI_INTP_SHIFT    2
+#define XT2000_INTMUX_PCI_INTP_MASK     0x00000004
+/*  PCI INTS interrupt:  */
+#define XT2000_INTMUX_PCI_INTS_SHIFT    3
+#define XT2000_INTMUX_PCI_INTS_MASK     0x00000008
+/*  PCI INTD interrupt:  */
+#define XT2000_INTMUX_PCI_INTD_SHIFT    4
+#define XT2000_INTMUX_PCI_INTD_MASK     0x00000010
+/*  V320 PCI controller interrupt:  */
+#define XT2000_INTMUX_V3_SHIFT          5
+#define XT2000_INTMUX_V3_MASK           0x00000020
+/*  PCI ENUM interrupt:  */
+#define XT2000_INTMUX_PCI_ENUM_SHIFT    6
+#define XT2000_INTMUX_PCI_ENUM_MASK     0x00000040
+/*  PCI DEG interrupt:  */
+#define XT2000_INTMUX_PCI_DEG_SHIFT     7
+#define XT2000_INTMUX_PCI_DEG_MASK      0x00000080
+
+/*  V3CFG (V3 config, V320 PCI controller):  */
+
+/*  V3 address control (0=pass-thru, 1=V3 address bits 31:28 set to 4'b0001 [default]):  */
+#define XT2000_V3CFG_V3ADC_SHIFT        0
+#define XT2000_V3CFG_V3ADC_MASK         0x00000001
+
+/* I2C Devices */
+
+#define XT2000_I2C_RTC_ID               0x68
+#define XT2000_I2C_NVRAM0_ID            0x56    /* 1st 256 byte block */
+#define XT2000_I2C_NVRAM1_ID            0x57    /* 2nd 256 byte block */
+
+/*  NVRAM Board Info structure:  */
+
+#define XT2000_NVRAM_SIZE               512
+
+#define XT2000_NVRAM_BINFO_START        0x100
+#define XT2000_NVRAM_BINFO_SIZE         0x20
+#define XT2000_NVRAM_BINFO_VERSION      0x10    /* version 1.0 */
+#if 0
+#define XT2000_NVRAM_BINFO_VERSION_OFFSET       0x00
+#define XT2000_NVRAM_BINFO_VERSION_SIZE                 0x1
+#define XT2000_NVRAM_BINFO_ETH_ADDR_OFFSET      0x02
+#define XT2000_NVRAM_BINFO_ETH_ADDR_SIZE                0x6
+#define XT2000_NVRAM_BINFO_SN_OFFSET            0x10
+#define XT2000_NVRAM_BINFO_SN_SIZE                      0xE
+#define XT2000_NVRAM_BINFO_CRC_OFFSET           0x1E
+#define XT2000_NVRAM_BINFO_CRC_SIZE                     0x2
+#endif /*0*/
+
+#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
+typedef struct xt2000_nvram_binfo {
+    unsigned char       version;
+    unsigned char       reserved1;
+    unsigned char       eth_addr[6];
+    unsigned char       reserved8[8];
+    unsigned char       serialno[14];
+    unsigned char       crc[2];         /* 16-bit CRC */
+} xt2000_nvram_binfo;
+#endif /*!__ASSEMBLY__ && !_NOCLANGUAGE*/
+
+
+#endif /*_INC_XT2000_H_*/
+
diff --git a/include/asm-xtensa/xtensa/xtboard.h b/include/asm-xtensa/xtensa/xtboard.h
new file mode 100644
index 000000000000..22469c175307
--- /dev/null
+++ b/include/asm-xtensa/xtensa/xtboard.h
@@ -0,0 +1,120 @@
+#ifndef _xtboard_h_included_
+#define _xtboard_h_included_
+
+/*
+ * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
+ *
+ *  xtboard.h  --  Routines for getting useful information from the board.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 Tensilica Inc.
+ */
+
+
+#include <xtensa/xt2000.h>
+
+#define XTBOARD_RTC_ERROR       -1
+#define XTBOARD_RTC_STOPPED     -2
+
+
+/*  xt2000-i2cdev.c:  */
+typedef void XtboardDelayFunc( unsigned );
+extern XtboardDelayFunc* xtboard_set_nsdelay_func( XtboardDelayFunc *delay_fn );
+extern int xtboard_i2c_read (unsigned id, unsigned char *buf, unsigned addr, unsigned size);
+extern int xtboard_i2c_write(unsigned id, unsigned char *buf, unsigned addr, unsigned size);
+extern int xtboard_i2c_wait_nvram_ack(unsigned id, unsigned swtimer);
+
+/*  xtboard.c:  */
+extern int xtboard_nvram_read (unsigned addr, unsigned len, unsigned char *buf);
+extern int xtboard_nvram_write(unsigned addr, unsigned len, unsigned char *buf);
+extern int xtboard_nvram_binfo_read (xt2000_nvram_binfo *buf);
+extern int xtboard_nvram_binfo_write(xt2000_nvram_binfo *buf);
+extern int xtboard_nvram_binfo_valid(xt2000_nvram_binfo *buf);
+extern int xtboard_ethermac_get(unsigned char *buf);
+extern int xtboard_ethermac_set(unsigned char *buf);
+
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_get_rtc_time
+/
+/ Description:  Get time stored in real-time clock.
+/
+/ Returns: time in seconds stored in real-time clock.
+/-**----------------------------------------------------------------------------*/
+
+extern unsigned xtboard_get_rtc_time(void);
+
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_set_rtc_time
+/
+/ Description:  Set time stored in real-time clock.
+/
+/ Parameters:   time -- time in seconds to store to real-time clock
+/
+/ Returns: 0 on success, xtboard_i2c_write() error code otherwise.
+/-**----------------------------------------------------------------------------*/
+
+extern int xtboard_set_rtc_time(unsigned time);
+
+
+/*  xtfreq.c:  */
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_measure_sys_clk
+/
+/ Description:  Get frequency of system clock.
+/
+/ Parameters:   none
+/
+/ Returns: frequency of system clock.
+/-**----------------------------------------------------------------------------*/
+
+extern unsigned xtboard_measure_sys_clk(void);
+
+
+#if 0   /* old stuff from xtboard.c: */
+
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_nvram valid
+/
+/ Description:  Determines if data in NVRAM is valid.
+/
+/ Parameters:   delay -- 10us delay function
+/
+/ Returns: 1 if NVRAM is valid, 0 otherwise
+/-**----------------------------------------------------------------------------*/
+
+extern unsigned xtboard_nvram_valid(void (*delay)( void ));
+
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_get_nvram_contents
+/
+/ Description:  Returns contents of NVRAM.
+/
+/ Parameters:   buf -- buffer to NVRAM contents.
+/               delay -- 10us delay function
+/
+/ Returns: 1 if NVRAM is valid, 0 otherwise
+/-**----------------------------------------------------------------------------*/
+
+extern unsigned xtboard_get_nvram_contents(unsigned char *buf, void (*delay)( void ));
+
+/*+*----------------------------------------------------------------------------
+/ Function: xtboard_get_ether_addr
+/
+/ Description:  Returns ethernet address of board.
+/
+/ Parameters:   buf -- buffer to store ethernet address
+/               delay -- 10us delay function
+/
+/ Returns: nothing.
+/-**----------------------------------------------------------------------------*/
+
+extern void xtboard_get_ether_addr(unsigned char *buf, void (*delay)( void ));
+
+#endif /*0*/
+
+
+#endif /*_xtboard_h_included_*/
+
diff --git a/include/linux/8250_pci.h b/include/linux/8250_pci.h
index 5f3ab21b339b..3209dd46ea7d 100644
--- a/include/linux/8250_pci.h
+++ b/include/linux/8250_pci.h
@@ -1,2 +1,37 @@
-int pci_siig10x_fn(struct pci_dev *dev, int enable);
-int pci_siig20x_fn(struct pci_dev *dev, int enable);
+/*
+ * Definitions for PCI support.
+ */
+#define FL_BASE_MASK            0x0007
+#define FL_BASE0                0x0000
+#define FL_BASE1                0x0001
+#define FL_BASE2                0x0002
+#define FL_BASE3                0x0003
+#define FL_BASE4                0x0004
+#define FL_GET_BASE(x)          (x & FL_BASE_MASK)
+
+/* Use successive BARs (PCI base address registers),
+   else use offset into some specified BAR */
+#define FL_BASE_BARS            0x0008
+
+/* do not assign an irq */
+#define FL_NOIRQ                0x0080
+
+/* Use the Base address register size to cap number of ports */
+#define FL_REGION_SZ_CAP        0x0100
+
+struct pciserial_board {
+        unsigned int flags;
+        unsigned int num_ports;
+        unsigned int base_baud;
+        unsigned int uart_offset;
+        unsigned int reg_shift;
+        unsigned int first_offset;
+};
+
+struct serial_private;
+
+struct serial_private *
+pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board);
+void pciserial_remove_ports(struct serial_private *priv);
+void pciserial_suspend_ports(struct serial_private *priv);
+void pciserial_resume_ports(struct serial_private *priv);
diff --git a/include/linux/a.out.h b/include/linux/a.out.h
index af8a1dfa5c32..f913cc3e1b0d 100644
--- a/include/linux/a.out.h
+++ b/include/linux/a.out.h
@@ -138,7 +138,7 @@ enum machine_type {
 #endif
 #endif
 
-#define _N_SEGMENT_ROUND(x) (((x) + SEGMENT_SIZE - 1) & ~(SEGMENT_SIZE - 1))
+#define _N_SEGMENT_ROUND(x) ALIGN(x, SEGMENT_SIZE)
 
 #define _N_TXTENDADDR(x) (N_TXTADDR(x)+(x).a_text)
 
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index b123cc08773d..026c3c011dc0 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -41,7 +41,7 @@
 #include <asm/acpi.h>
 
 
-#ifdef CONFIG_ACPI_BOOT
+#ifdef CONFIG_ACPI
 
 enum acpi_irq_model_id {
         ACPI_IRQ_MODEL_PIC = 0,
@@ -206,7 +206,10 @@ struct acpi_table_plat_int_src {
         u8                      eid;
         u8                      iosapic_vector;
         u32                     global_irq;
-        u32                     reserved;
+        struct {
+                u32                     cpei_override_flag:1;
+                u32                     reserved:31;
+        }                       plint_flags;
 } __attribute__ ((packed));
 
 enum acpi_interrupt_id {
@@ -342,11 +345,19 @@ struct acpi_table_ecdt {
 
 /* PCI MMCONFIG */
 
+/* Defined in PCI Firmware Specification 3.0 */
+struct acpi_table_mcfg_config {
+        u32                             base_address;
+        u32                             base_reserved;
+        u16                             pci_segment_group_number;
+        u8                              start_bus_number;
+        u8                              end_bus_number;
+        u8                              reserved[4];
+} __attribute__ ((packed));
 struct acpi_table_mcfg {
         struct acpi_table_header        header;
         u8                              reserved[8];
-        u32                             base_address;
-        u32                             base_reserved;
+        struct acpi_table_mcfg_config   config[0];
 } __attribute__ ((packed));
 
 /* Table Handlers */
@@ -391,6 +402,7 @@ int acpi_table_parse (enum acpi_table_id id, acpi_table_handler handler);
 int acpi_get_table_header_early (enum acpi_table_id id, struct acpi_table_header **header);
 int acpi_table_parse_madt (enum acpi_madt_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries);
 int acpi_table_parse_srat (enum acpi_srat_entry_id id, acpi_madt_entry_handler handler, unsigned int max_entries);
+int acpi_parse_mcfg (unsigned long phys_addr, unsigned long size);
 void acpi_table_print (struct acpi_table_header *header, unsigned long phys_addr);
 void acpi_table_print_madt_entry (acpi_table_entry_header *madt);
 void acpi_table_print_srat_entry (acpi_table_entry_header *srat);
@@ -407,29 +419,23 @@ int acpi_map_lsapic(acpi_handle handle, int *pcpu);
 int acpi_unmap_lsapic(int cpu);
 #endif /* CONFIG_ACPI_HOTPLUG_CPU */
 
+int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base);
+int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base);
+
 extern int acpi_mp_config;
 
-extern u32 pci_mmcfg_base_addr;
+extern struct acpi_table_mcfg_config *pci_mmcfg_config;
+extern int pci_mmcfg_config_num;
 
 extern int sbf_port ;
 
-#else   /*!CONFIG_ACPI_BOOT*/
+#else   /* !CONFIG_ACPI */
 
 #define acpi_mp_config  0
 
-static inline int acpi_boot_init(void)
-{
-        return 0;
-}
+#endif  /* !CONFIG_ACPI */
 
-static inline int acpi_boot_table_init(void)
-{
-        return 0;
-}
-
-#endif  /*!CONFIG_ACPI_BOOT*/
-
-unsigned int acpi_register_gsi (u32 gsi, int edge_level, int active_high_low);
+int acpi_register_gsi (u32 gsi, int edge_level, int active_high_low);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
 /*
@@ -437,11 +443,9 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
  * If this matches the last registration, any IRQ resources for gsi
  * are freed.
  */
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 void acpi_unregister_gsi (u32 gsi);
-#endif
 
-#ifdef CONFIG_ACPI_PCI
+#ifdef CONFIG_ACPI
 
 struct acpi_prt_entry {
         struct list_head        node;
@@ -462,11 +466,9 @@ struct acpi_prt_list {
 struct pci_dev;
 
 int acpi_pci_irq_enable (struct pci_dev *dev);
-void acpi_penalize_isa_irq(int irq);
+void acpi_penalize_isa_irq(int irq, int active);
 
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 void acpi_pci_irq_disable (struct pci_dev *dev);
-#endif
 
 struct acpi_pci_driver {
         struct acpi_pci_driver *next;
@@ -477,7 +479,7 @@ struct acpi_pci_driver {
 int acpi_pci_register_driver(struct acpi_pci_driver *driver);
 void acpi_pci_unregister_driver(struct acpi_pci_driver *driver);
 
-#endif /*CONFIG_ACPI_PCI*/
+#endif /* CONFIG_ACPI */
 
 #ifdef CONFIG_ACPI_EC
 
@@ -486,20 +488,9 @@ extern int ec_write(u8 addr, u8 val);
 
 #endif /*CONFIG_ACPI_EC*/
 
-#ifdef CONFIG_ACPI_INTERPRETER
-
 extern int acpi_blacklisted(void);
 extern void acpi_bios_year(char *s);
 
-#else /*!CONFIG_ACPI_INTERPRETER*/
-
-static inline int acpi_blacklisted(void)
-{
-        return 0;
-}
-
-#endif /*!CONFIG_ACPI_INTERPRETER*/
-
 #define ACPI_CSTATE_LIMIT_DEFINED       /* for driver builds */
 #ifdef  CONFIG_ACPI
 
@@ -537,5 +528,17 @@ static inline int acpi_get_pxm(acpi_handle handle)
 
 extern int pnpacpi_disabled;
 
+#else   /* CONFIG_ACPI */
+
+static inline int acpi_boot_init(void)
+{
+        return 0;
+}
+
+static inline int acpi_boot_table_init(void)
+{
+        return 0;
+}
+
 #endif  /* CONFIG_ACPI */
 #endif  /*_LINUX_ACPI_H*/
diff --git a/include/linux/arcfb.h b/include/linux/arcfb.h
new file mode 100644
index 000000000000..721e7654daeb
--- /dev/null
+++ b/include/linux/arcfb.h
@@ -0,0 +1,8 @@
+#ifndef __LINUX_ARCFB_H__
+#define __LINUX_ARCFB_H__
+
+#define FBIO_WAITEVENT          _IO('F', 0x88)
+#define FBIO_GETCONTROL2        _IOR('F', 0x89, size_t)
+
+#endif
+
diff --git a/include/linux/ata.h b/include/linux/ata.h
index f178894edd04..a5b74efab067 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -1,24 +1,29 @@
 
 /*
-   Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
-   Copyright 2003-2004 Jeff Garzik
-
-   The contents of this file are subject to the Open
-   Software License version 1.1 that can be found at
-   http://www.opensource.org/licenses/osl-1.1.txt and is included herein
-   by reference.
-
-   Alternatively, the contents of this file may be used under the terms
-   of the GNU General Public License version 2 (the "GPL") as distributed
-   in the kernel source COPYING file, in which case the provisions of
-   the GPL are applicable instead of the above.  If you wish to allow
-   the use of your version of this file only under the terms of the
-   GPL and not to allow others to use your version of this file under
-   the OSL, indicate your decision by deleting the provisions above and
-   replace them with the notice and other provisions required by the GPL.
-   If you do not delete the provisions above, a recipient may use your
-   version of this file under either the OSL or the GPL.
-
+ *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
+ *  Copyright 2003-2004 Jeff Garzik
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *  libata documentation is available via 'make {ps|pdf}docs',
+ *  as Documentation/DocBook/libata.*
+ *
+ *  Hardware documentation available from http://www.t13.org/
+ *
  */
 
 #ifndef __LINUX_ATA_H__
@@ -108,6 +113,8 @@ enum {
 
         /* ATA device commands */
         ATA_CMD_CHK_POWER       = 0xE5, /* check power mode */
+        ATA_CMD_STANDBY         = 0xE2, /* place in standby power mode */
+        ATA_CMD_IDLE            = 0xE3, /* place in idle power mode */
         ATA_CMD_EDD             = 0x90, /* execute device diagnostic */
         ATA_CMD_FLUSH           = 0xE7,
         ATA_CMD_FLUSH_EXT       = 0xEA,
@@ -224,6 +231,7 @@ struct ata_taskfile {
 };
 
 #define ata_id_is_ata(id)       (((id)[0] & (1 << 15)) == 0)
+#define ata_id_is_sata(id)      ((id)[93] == 0)
 #define ata_id_rahead_enabled(id) ((id)[85] & (1 << 6))
 #define ata_id_wcache_enabled(id) ((id)[85] & (1 << 5))
 #define ata_id_has_flush(id) ((id)[83] & (1 << 12))
diff --git a/include/linux/atalk.h b/include/linux/atalk.h
index 31d3fc25ccbd..911c09cb9bf9 100644
--- a/include/linux/atalk.h
+++ b/include/linux/atalk.h
@@ -1,6 +1,8 @@
 #ifndef __LINUX_ATALK_H__
 #define __LINUX_ATALK_H__
 
+#include <asm/byteorder.h>
+
 /*
  * AppleTalk networking structures
  *
@@ -20,7 +22,7 @@
 #define SIOCATALKDIFADDR       (SIOCPROTOPRIVATE + 0)
 
 struct atalk_addr {
-        __u16   s_net;
+        __be16  s_net;
         __u8    s_node;
 };
 
@@ -33,8 +35,8 @@ struct sockaddr_at {
 
 struct atalk_netrange {
         __u8    nr_phase;
-        __u16   nr_firstnet;
-        __u16   nr_lastnet;
+        __be16  nr_firstnet;
+        __be16  nr_lastnet;
 };
 
 #ifdef __KERNEL__
@@ -70,8 +72,8 @@ struct atalk_iface {
 struct atalk_sock {
         /* struct sock has to be the first member of atalk_sock */
         struct sock     sk;
-        unsigned short  dest_net;
-        unsigned short  src_net;
+        __be16          dest_net;
+        __be16          src_net;
         unsigned char   dest_node;
         unsigned char   src_node;
         unsigned char   dest_port;
@@ -95,9 +97,9 @@ struct ddpehdr {
                 deh_hops:4,
                 deh_len:10;
 #endif
-        __u16   deh_sum;
-        __u16   deh_dnet;
-        __u16   deh_snet;
+        __be16  deh_sum;
+        __be16  deh_dnet;
+        __be16  deh_snet;
         __u8    deh_dnode;
         __u8    deh_snode;
         __u8    deh_dport;
@@ -142,24 +144,24 @@ struct ddpshdr {
 
 /* AppleTalk AARP headers */
 struct elapaarp {
-        __u16   hw_type;
+        __be16  hw_type;
 #define AARP_HW_TYPE_ETHERNET           1
 #define AARP_HW_TYPE_TOKENRING          2
-        __u16   pa_type;
+        __be16  pa_type;
         __u8    hw_len;
         __u8    pa_len;
 #define AARP_PA_ALEN                    4
-        __u16   function;
+        __be16  function;
 #define AARP_REQUEST                    1
 #define AARP_REPLY                      2
 #define AARP_PROBE                      3
         __u8    hw_src[ETH_ALEN]        __attribute__ ((packed));
         __u8    pa_src_zero             __attribute__ ((packed));
-        __u16   pa_src_net              __attribute__ ((packed));
+        __be16  pa_src_net              __attribute__ ((packed));
         __u8    pa_src_node             __attribute__ ((packed));
         __u8    hw_dst[ETH_ALEN]        __attribute__ ((packed));
         __u8    pa_dst_zero             __attribute__ ((packed));
-        __u16   pa_dst_net              __attribute__ ((packed));
+        __be16  pa_dst_net              __attribute__ ((packed));
         __u8    pa_dst_node             __attribute__ ((packed));       
 };
 
diff --git a/include/linux/attribute_container.h b/include/linux/attribute_container.h
index af1010b6dab7..93bfb0beb62a 100644
--- a/include/linux/attribute_container.h
+++ b/include/linux/attribute_container.h
@@ -11,10 +11,12 @@
 
 #include <linux/device.h>
 #include <linux/list.h>
+#include <linux/klist.h>
+#include <linux/spinlock.h>
 
 struct attribute_container {
         struct list_head        node;
-        struct list_head        containers;
+        struct klist            containers;
         struct class            *class;
         struct class_device_attribute **attrs;
         int (*match)(struct attribute_container *, struct device *);
@@ -62,12 +64,8 @@ int attribute_container_add_class_device_adapter(struct attribute_container *con
                                                  struct class_device *classdev);
 void attribute_container_remove_attrs(struct class_device *classdev);
 void attribute_container_class_device_del(struct class_device *classdev);
-
-
-
-
-
-
+struct attribute_container *attribute_container_classdev_to_container(struct class_device *);
+struct class_device *attribute_container_find_class_device(struct attribute_container *, struct device *);
 struct class_device_attribute **attribute_container_classdev_to_attrs(const struct class_device *classdev);
 
 #endif
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 19f04b049798..68aba0c02e49 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -27,15 +27,52 @@
 #include <linux/sched.h>
 #include <linux/elf.h>
 
-/* Request and reply types */
-#define AUDIT_GET      1000     /* Get status */
-#define AUDIT_SET      1001     /* Set status (enable/disable/auditd) */
-#define AUDIT_LIST     1002     /* List filtering rules */
-#define AUDIT_ADD      1003     /* Add filtering rule */
-#define AUDIT_DEL      1004     /* Delete filtering rule */
-#define AUDIT_USER     1005     /* Send a message from user-space */
-#define AUDIT_LOGIN    1006     /* Define the login id and informaiton */
-#define AUDIT_KERNEL   2000     /* Asynchronous audit record. NOT A REQUEST. */
+/* The netlink messages for the audit system is divided into blocks:
+ * 1000 - 1099 are for commanding the audit system
+ * 1100 - 1199 user space trusted application messages
+ * 1200 - 1299 messages internal to the audit daemon
+ * 1300 - 1399 audit event messages
+ * 1400 - 1499 SE Linux use
+ * 1500 - 1999 future use
+ * 2000 is for otherwise unclassified kernel audit messages
+ *
+ * Messages from 1000-1199 are bi-directional. 1200-1299 are exclusively user
+ * space. Anything over that is kernel --> user space communication.
+ */
+#define AUDIT_GET               1000    /* Get status */
+#define AUDIT_SET               1001    /* Set status (enable/disable/auditd) */
+#define AUDIT_LIST              1002    /* List syscall filtering rules */
+#define AUDIT_ADD               1003    /* Add syscall filtering rule */
+#define AUDIT_DEL               1004    /* Delete syscall filtering rule */
+#define AUDIT_USER              1005    /* Message from userspace -- deprecated */
+#define AUDIT_LOGIN             1006    /* Define the login id and information */
+#define AUDIT_WATCH_INS         1007    /* Insert file/dir watch entry */
+#define AUDIT_WATCH_REM         1008    /* Remove file/dir watch entry */
+#define AUDIT_WATCH_LIST        1009    /* List all file/dir watches */
+#define AUDIT_SIGNAL_INFO       1010    /* Get info about sender of signal to auditd */
+
+#define AUDIT_FIRST_USER_MSG    1100    /* Userspace messages uninteresting to kernel */
+#define AUDIT_LAST_USER_MSG     1199
+ 
+#define AUDIT_DAEMON_START      1200    /* Daemon startup record */
+#define AUDIT_DAEMON_END        1201    /* Daemon normal stop record */
+#define AUDIT_DAEMON_ABORT      1202    /* Daemon error stop record */
+#define AUDIT_DAEMON_CONFIG     1203    /* Daemon config change */
+
+#define AUDIT_SYSCALL           1300    /* Syscall event */
+#define AUDIT_FS_WATCH          1301    /* Filesystem watch event */
+#define AUDIT_PATH              1302    /* Filename path information */
+#define AUDIT_IPC               1303    /* IPC record */
+#define AUDIT_SOCKETCALL        1304    /* sys_socketcall arguments */
+#define AUDIT_CONFIG_CHANGE     1305    /* Audit system configuration change */
+#define AUDIT_SOCKADDR          1306    /* sockaddr copied as syscall arg */
+#define AUDIT_CWD               1307    /* Current working directory */
+
+#define AUDIT_AVC               1400    /* SE Linux avc denial or grant */
+#define AUDIT_SELINUX_ERR       1401    /* Internal SE Linux Errors */
+#define AUDIT_AVC_PATH          1402    /* dentry, vfsmount pair from avc */
+
+#define AUDIT_KERNEL            2000    /* Asynchronous audit record. NOT A REQUEST. */
 
 /* Rule flags */
 #define AUDIT_PER_TASK 0x01     /* Apply rule at task creation (not syscall) */
@@ -128,20 +165,13 @@
 #define AUDIT_ARCH_SH64         (EM_SH|__AUDIT_ARCH_64BIT)
 #define AUDIT_ARCH_SHEL64       (EM_SH|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
 #define AUDIT_ARCH_SPARC        (EM_SPARC)
-#define AUDIT_ARCH_SPARC64      (EM_SPARC64|__AUDIT_ARCH_64BIT)
+#define AUDIT_ARCH_SPARC64      (EM_SPARCV9|__AUDIT_ARCH_64BIT)
 #define AUDIT_ARCH_V850         (EM_V850|__AUDIT_ARCH_LE)
 #define AUDIT_ARCH_X86_64       (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
 
-#ifndef __KERNEL__
-struct audit_message {
-        struct nlmsghdr nlh;
-        char            data[1200];
-};
-#endif
-
 struct audit_status {
         __u32           mask;           /* Bit mask for valid entries */
-        __u32           enabled;        /* 1 = enabled, 0 = disbaled */
+        __u32           enabled;        /* 1 = enabled, 0 = disabled */
         __u32           failure;        /* Failure-to-log action */
         __u32           pid;            /* pid of auditd process */
         __u32           rate_limit;     /* messages rate limit (per second) */
@@ -161,6 +191,11 @@ struct audit_rule {		/* for AUDIT_LIST, AUDIT_ADD, and AUDIT_DEL */
 
 #ifdef __KERNEL__
 
+struct audit_sig_info {
+        uid_t           uid;
+        pid_t           pid;
+};
+
 struct audit_buffer;
 struct audit_context;
 struct inode;
@@ -185,11 +220,16 @@ extern void audit_inode(const char *name, const struct inode *inode);
                                 /* Private API (for audit.c only) */
 extern int  audit_receive_filter(int type, int pid, int uid, int seq,
                                  void *data, uid_t loginuid);
-extern void audit_get_stamp(struct audit_context *ctx,
-                            struct timespec *t, unsigned int *serial);
+extern unsigned int audit_serial(void);
+extern void auditsc_get_stamp(struct audit_context *ctx,
+                              struct timespec *t, unsigned int *serial);
 extern int  audit_set_loginuid(struct task_struct *task, uid_t loginuid);
 extern uid_t audit_get_loginuid(struct audit_context *ctx);
 extern int audit_ipc_perms(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mode);
+extern int audit_socketcall(int nargs, unsigned long *args);
+extern int audit_sockaddr(int len, void *addr);
+extern int audit_avc_path(struct dentry *dentry, struct vfsmount *mnt);
+extern void audit_signal_info(int sig, struct task_struct *t);
 #else
 #define audit_alloc(t) ({ 0; })
 #define audit_free(t) do { ; } while (0)
@@ -198,18 +238,24 @@ extern int audit_ipc_perms(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mo
 #define audit_getname(n) do { ; } while (0)
 #define audit_putname(n) do { ; } while (0)
 #define audit_inode(n,i) do { ; } while (0)
+#define audit_receive_filter(t,p,u,s,d,l) ({ -EOPNOTSUPP; })
+#define auditsc_get_stamp(c,t,s) do { BUG(); } while (0)
 #define audit_get_loginuid(c) ({ -1; })
 #define audit_ipc_perms(q,u,g,m) ({ 0; })
+#define audit_socketcall(n,a) ({ 0; })
+#define audit_sockaddr(len, addr) ({ 0; })
+#define audit_avc_path(dentry, mnt) ({ 0; })
+#define audit_signal_info(s,t) do { ; } while (0)
 #endif
 
 #ifdef CONFIG_AUDIT
 /* These are defined in audit.c */
                                 /* Public API */
-extern void                 audit_log(struct audit_context *ctx,
+extern void                 audit_log(struct audit_context *ctx, int type,
                                       const char *fmt, ...)
-                            __attribute__((format(printf,2,3)));
+                            __attribute__((format(printf,3,4)));
 
-extern struct audit_buffer *audit_log_start(struct audit_context *ctx);
+extern struct audit_buffer *audit_log_start(struct audit_context *ctx,int type);
 extern void                 audit_log_format(struct audit_buffer *ab,
                                              const char *fmt, ...)
                             __attribute__((format(printf,2,3)));
@@ -229,8 +275,8 @@ extern void		    audit_send_reply(int pid, int seq, int type,
                                              void *payload, int size);
 extern void                 audit_log_lost(const char *message);
 #else
-#define audit_log(t,f,...) do { ; } while (0)
-#define audit_log_start(t) ({ NULL; })
+#define audit_log(c,t,f,...) do { ; } while (0)
+#define audit_log_start(c,t) ({ NULL; })
 #define audit_log_vformat(b,f,a) do { ; } while (0)
 #define audit_log_format(b,f,...) do { ; } while (0)
 #define audit_log_end(b) do { ; } while (0)
diff --git a/include/linux/auto_fs4.h b/include/linux/auto_fs4.h
index a1657fb99516..9343c89d843c 100644
--- a/include/linux/auto_fs4.h
+++ b/include/linux/auto_fs4.h
@@ -23,7 +23,7 @@
 #define AUTOFS_MIN_PROTO_VERSION        3
 #define AUTOFS_MAX_PROTO_VERSION        4
 
-#define AUTOFS_PROTO_SUBVERSION         6
+#define AUTOFS_PROTO_SUBVERSION         7
 
 /* Mask for expire behaviour */
 #define AUTOFS_EXP_IMMEDIATE            1
diff --git a/include/linux/auxvec.h b/include/linux/auxvec.h
new file mode 100644
index 000000000000..9a7b374c9fb4
--- /dev/null
+++ b/include/linux/auxvec.h
@@ -0,0 +1,31 @@
+#ifndef _LINUX_AUXVEC_H
+#define _LINUX_AUXVEC_H
+
+#include <asm/auxvec.h>
+
+/* Symbolic values for the entries in the auxiliary table
+   put on the initial stack */
+#define AT_NULL   0     /* end of vector */
+#define AT_IGNORE 1     /* entry should be ignored */
+#define AT_EXECFD 2     /* file descriptor of program */
+#define AT_PHDR   3     /* program headers for program */
+#define AT_PHENT  4     /* size of program header entry */
+#define AT_PHNUM  5     /* number of program headers */
+#define AT_PAGESZ 6     /* system page size */
+#define AT_BASE   7     /* base address of interpreter */
+#define AT_FLAGS  8     /* flags */
+#define AT_ENTRY  9     /* entry point of program */
+#define AT_NOTELF 10    /* program is not ELF */
+#define AT_UID    11    /* real uid */
+#define AT_EUID   12    /* effective uid */
+#define AT_GID    13    /* real gid */
+#define AT_EGID   14    /* effective gid */
+#define AT_PLATFORM 15  /* string identifying CPU for optimizations */
+#define AT_HWCAP  16    /* arch dependent hints at CPU capabilities */
+#define AT_CLKTCK 17    /* frequency at which times() increments */
+
+#define AT_SECURE 23   /* secure mode boolean */
+
+#define AT_VECTOR_SIZE  42 /* Size of auxiliary table.  */
+
+#endif /* _LINUX_AUXVEC_H */
diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h
index 7e736e201c46..c1e82c514443 100644
--- a/include/linux/binfmts.h
+++ b/include/linux/binfmts.h
@@ -69,6 +69,11 @@ extern void remove_arg_zero(struct linux_binprm *);
 extern int search_binary_handler(struct linux_binprm *,struct pt_regs *);
 extern int flush_old_exec(struct linux_binprm * bprm);
 
+extern int suid_dumpable;
+#define SUID_DUMP_DISABLE       0       /* No setuid dumping */
+#define SUID_DUMP_USER          1       /* Dump as user of process */
+#define SUID_DUMP_ROOT          2       /* Dump as root */
+
 /* Stack area protections */
 #define EXSTACK_DEFAULT   0     /* Whatever the arch defaults to */
 #define EXSTACK_DISABLE_X 1     /* Disable executable stacks */
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 038022763f09..cdaf03a14a51 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -22,6 +22,7 @@
 
 #include <linux/highmem.h>
 #include <linux/mempool.h>
+#include <linux/ioprio.h>
 
 /* Platforms may set this to teach the BIO layer about IOMMU hardware. */
 #include <asm/io.h>
@@ -110,7 +111,6 @@ struct bio {
         void                    *bi_private;
 
         bio_destructor_t        *bi_destructor; /* destructor */
-        struct bio_set          *bi_set;        /* memory pools set */
 };
 
 /*
@@ -150,6 +150,19 @@ struct bio {
 #define BIO_RW_SYNC     4
 
 /*
+ * upper 16 bits of bi_rw define the io priority of this bio
+ */
+#define BIO_PRIO_SHIFT  (8 * sizeof(unsigned long) - IOPRIO_BITS)
+#define bio_prio(bio)   ((bio)->bi_rw >> BIO_PRIO_SHIFT)
+#define bio_prio_valid(bio)     ioprio_valid(bio_prio(bio))
+
+#define bio_set_prio(bio, prio)         do {                    \
+        WARN_ON(prio >= (1 << IOPRIO_BITS));                    \
+        (bio)->bi_rw &= ((1UL << BIO_PRIO_SHIFT) - 1);          \
+        (bio)->bi_rw |= ((unsigned long) (prio) << BIO_PRIO_SHIFT);     \
+} while (0)
+
+/*
  * various member access, note that bio_data should of course not be used
  * on highmem page vectors
  */
@@ -266,6 +279,7 @@ extern void bioset_free(struct bio_set *);
 extern struct bio *bio_alloc(unsigned int __nocast, int);
 extern struct bio *bio_alloc_bioset(unsigned int __nocast, int, struct bio_set *);
 extern void bio_put(struct bio *);
+extern void bio_free(struct bio *, struct bio_set *);
 
 extern void bio_endio(struct bio *, unsigned int, int);
 struct request_queue;
@@ -281,7 +295,13 @@ extern int bio_add_page(struct bio *, struct page *, unsigned int,unsigned int);
 extern int bio_get_nr_vecs(struct block_device *);
 extern struct bio *bio_map_user(struct request_queue *, struct block_device *,
                                 unsigned long, unsigned int, int);
+struct sg_iovec;
+extern struct bio *bio_map_user_iov(struct request_queue *,
+                                    struct block_device *,
+                                    struct sg_iovec *, int, int);
 extern void bio_unmap_user(struct bio *);
+extern struct bio *bio_map_kern(struct request_queue *, void *, unsigned int,
+                                unsigned int);
 extern void bio_set_pages_dirty(struct bio *bio);
 extern void bio_check_pages_dirty(struct bio *bio);
 extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index ef1afc178c0a..aefa26fbae8a 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -54,16 +54,23 @@ struct as_io_context {
 
 struct cfq_queue;
 struct cfq_io_context {
-        void (*dtor)(struct cfq_io_context *);
-        void (*exit)(struct cfq_io_context *);
-
-        struct io_context *ioc;
-
         /*
          * circular list of cfq_io_contexts belonging to a process io context
          */
         struct list_head list;
         struct cfq_queue *cfqq;
+        void *key;
+
+        struct io_context *ioc;
+
+        unsigned long last_end_request;
+        unsigned long last_queue;
+        unsigned long ttime_total;
+        unsigned long ttime_samples;
+        unsigned long ttime_mean;
+
+        void (*dtor)(struct cfq_io_context *);
+        void (*exit)(struct cfq_io_context *);
 };
 
 /*
@@ -73,7 +80,9 @@ struct cfq_io_context {
  */
 struct io_context {
         atomic_t refcount;
-        pid_t pid;
+        struct task_struct *task;
+
+        int (*set_ioprio)(struct io_context *, unsigned int);
 
         /*
          * For request batching
@@ -81,14 +90,13 @@ struct io_context {
         unsigned long last_waited; /* Time last woken after wait for request */
         int nr_batch_requests;     /* Number of requests left in the batch */
 
-        spinlock_t lock;
-
         struct as_io_context *aic;
         struct cfq_io_context *cic;
 };
 
 void put_io_context(struct io_context *ioc);
 void exit_io_context(void);
+struct io_context *current_io_context(int gfp_flags);
 struct io_context *get_io_context(int gfp_flags);
 void copy_io_context(struct io_context **pdst, struct io_context **psrc);
 void swap_io_context(struct io_context **ioc1, struct io_context **ioc2);
@@ -134,6 +142,8 @@ struct request {
 
         void *elevator_private;
 
+        unsigned short ioprio;
+
         int rq_status;  /* should split this into a few status bits */
         struct gendisk *rq_disk;
         int errors;
@@ -285,9 +295,6 @@ enum blk_queue_state {
         Queue_up,
 };
 
-#define BLK_TAGS_PER_LONG       (sizeof(unsigned long) * 8)
-#define BLK_TAGS_MASK           (BLK_TAGS_PER_LONG - 1)
-
 struct blk_queue_tag {
         struct request **tag_index;     /* map of busy tags */
         unsigned long *tag_map;         /* bit map of free/busy tags */
@@ -396,6 +403,7 @@ struct request_queue
          */
         unsigned int            sg_timeout;
         unsigned int            sg_reserved_size;
+        int                     node;
 
         struct list_head        drain_list;
 
@@ -542,15 +550,12 @@ extern void generic_make_request(struct bio *bio);
 extern void blk_put_request(struct request *);
 extern void blk_end_sync_rq(struct request *rq);
 extern void blk_attempt_remerge(request_queue_t *, struct request *);
-extern void __blk_attempt_remerge(request_queue_t *, struct request *);
 extern struct request *blk_get_request(request_queue_t *, int, int);
-extern void blk_insert_request(request_queue_t *, struct request *, int, void *, int);
+extern void blk_insert_request(request_queue_t *, struct request *, int, void *);
 extern void blk_requeue_request(request_queue_t *, struct request *);
 extern void blk_plug_device(request_queue_t *);
 extern int blk_remove_plug(request_queue_t *);
 extern void blk_recount_segments(request_queue_t *, struct bio *);
-extern int blk_phys_contig_segment(request_queue_t *q, struct bio *, struct bio *);
-extern int blk_hw_contig_segment(request_queue_t *q, struct bio *, struct bio *);
 extern int scsi_cmd_ioctl(struct file *, struct gendisk *, unsigned int, void __user *);
 extern void blk_start_queue(request_queue_t *q);
 extern void blk_stop_queue(request_queue_t *q);
@@ -558,10 +563,12 @@ extern void blk_sync_queue(struct request_queue *q);
 extern void __blk_stop_queue(request_queue_t *q);
 extern void blk_run_queue(request_queue_t *);
 extern void blk_queue_activity_fn(request_queue_t *, activity_fn *, void *);
-extern struct request *blk_rq_map_user(request_queue_t *, int, void __user *, unsigned int);
-extern int blk_rq_unmap_user(struct request *, struct bio *, unsigned int);
-extern int blk_execute_rq(request_queue_t *, struct gendisk *, struct request *);
-
+extern int blk_rq_map_user(request_queue_t *, struct request *, void __user *, unsigned int);
+extern int blk_rq_unmap_user(struct bio *, unsigned int);
+extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, unsigned int);
+extern int blk_rq_map_user_iov(request_queue_t *, struct request *, struct sg_iovec *, int);
+extern int blk_execute_rq(request_queue_t *, struct gendisk *,
+                          struct request *, int);
 static inline request_queue_t *bdev_get_queue(struct block_device *bdev)
 {
         return bdev->bd_disk->queue;
@@ -615,6 +622,8 @@ static inline void blkdev_dequeue_request(struct request *req)
 /*
  * Access functions for manipulating queue properties
  */
+extern request_queue_t *blk_init_queue_node(request_fn_proc *rfn,
+                                        spinlock_t *lock, int node_id);
 extern request_queue_t *blk_init_queue(request_fn_proc *, spinlock_t *);
 extern void blk_cleanup_queue(request_queue_t *);
 extern void blk_queue_make_request(request_queue_t *, make_request_fn *);
@@ -632,7 +641,6 @@ extern void blk_queue_dma_alignment(request_queue_t *, int);
 extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
 extern void blk_queue_ordered(request_queue_t *, int);
 extern void blk_queue_issue_flush_fn(request_queue_t *, issue_flush_fn *);
-extern int blkdev_scsi_issue_flush_fn(request_queue_t *, struct gendisk *, sector_t *);
 extern struct request *blk_start_pre_flush(request_queue_t *,struct request *);
 extern int blk_complete_barrier_rq(request_queue_t *, struct request *, int);
 extern int blk_complete_barrier_rq_locked(request_queue_t *, struct request *, int);
@@ -646,7 +654,8 @@ extern void blk_wait_queue_drained(request_queue_t *, int);
 extern void blk_finish_queue_drain(request_queue_t *);
 
 int blk_get_queue(request_queue_t *);
-request_queue_t *blk_alloc_queue(int);
+request_queue_t *blk_alloc_queue(int gfp_mask);
+request_queue_t *blk_alloc_queue_node(int,int);
 #define blk_put_queue(q) blk_cleanup_queue((q))
 
 /*
@@ -675,8 +684,6 @@ extern int blkdev_issue_flush(struct block_device *, sector_t *);
 
 #define blkdev_entry_to_request(entry) list_entry((entry), struct request, queuelist)
 
-extern void drive_stat_acct(struct request *, int, int);
-
 static inline int queue_hardsect_size(request_queue_t *q)
 {
         int retval = 512;
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 0dd8ca1a3d5a..82bd8842d11c 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -22,6 +22,10 @@ extern unsigned long min_low_pfn;
  */
 extern unsigned long max_pfn;
 
+#ifdef CONFIG_CRASH_DUMP
+extern unsigned long saved_max_pfn;
+#endif
+
 /*
  * node_bootmem_map is a map pointer - the bits represent all physical 
  * memory pages (including holes) on the node.
@@ -67,6 +71,15 @@ extern void * __init __alloc_bootmem_node (pg_data_t *pgdat, unsigned long size,
         __alloc_bootmem_node((pgdat), (x), PAGE_SIZE, 0)
 #endif /* !CONFIG_HAVE_ARCH_BOOTMEM_NODE */
 
+#ifdef CONFIG_HAVE_ARCH_ALLOC_REMAP
+extern void *alloc_remap(int nid, unsigned long size);
+#else
+static inline void *alloc_remap(int nid, unsigned long size)
+{
+        return NULL;
+}
+#endif
+
 extern unsigned long __initdata nr_kernel_pages;
 extern unsigned long __initdata nr_all_pages;
 
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index 802c91e9b3da..90828493791f 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -19,6 +19,9 @@ enum bh_state_bits {
         BH_Dirty,       /* Is dirty */
         BH_Lock,        /* Is locked */
         BH_Req,         /* Has been submitted for I/O */
+        BH_Uptodate_Lock,/* Used by the first bh in a page, to serialise
+                          * IO completion of other buffers in the page
+                          */
 
         BH_Mapped,      /* Has a disk mapping */
         BH_New,         /* Disk mapping was newly created by get_block */
diff --git a/include/linux/byteorder/swabb.h b/include/linux/byteorder/swabb.h
index d28d9a804d3b..d5f2a3205109 100644
--- a/include/linux/byteorder/swabb.h
+++ b/include/linux/byteorder/swabb.h
@@ -92,29 +92,32 @@
 #endif /* OPTIMIZE */
 
 
-static __inline__ __const__ __u32 __fswahw32(__u32 x)
+static inline __u32 __fswahw32(__u32 x)
 {
         return __arch__swahw32(x);
 }
-static __inline__ __u32 __swahw32p(__u32 *x)
+
+static inline __u32 __swahw32p(__u32 *x)
 {
         return __arch__swahw32p(x);
 }
-static __inline__ void __swahw32s(__u32 *addr)
+
+static inline void __swahw32s(__u32 *addr)
 {
         __arch__swahw32s(addr);
 }
 
-
-static __inline__ __const__ __u32 __fswahb32(__u32 x)
+static inline __u32 __fswahb32(__u32 x)
 {
         return __arch__swahb32(x);
 }
-static __inline__ __u32 __swahb32p(__u32 *x)
+
+static inline __u32 __swahb32p(__u32 *x)
 {
         return __arch__swahb32p(x);
 }
-static __inline__ void __swahb32s(__u32 *addr)
+
+static inline void __swahb32s(__u32 *addr)
 {
         __arch__swahb32s(addr);
 }
diff --git a/include/linux/cache.h b/include/linux/cache.h
index 4d767b93738a..f6b5a46c5f82 100644
--- a/include/linux/cache.h
+++ b/include/linux/cache.h
@@ -13,6 +13,12 @@
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 #endif
 
+#if defined(CONFIG_X86) || defined(CONFIG_SPARC64)
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+#else
+#define __read_mostly
+#endif
+
 #ifndef ____cacheline_aligned
 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
 #endif
diff --git a/include/linux/capability.h b/include/linux/capability.h
index 8d139f4acf23..6b4618902d3d 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -233,6 +233,7 @@ typedef __u32 kernel_cap_t;
 /* Allow enabling/disabling tagged queuing on SCSI controllers and sending
    arbitrary SCSI commands */
 /* Allow setting encryption key on loopback filesystem */
+/* Allow setting zone reclaim policy */
 
 #define CAP_SYS_ADMIN        21
 
diff --git a/include/linux/cciss_ioctl.h b/include/linux/cciss_ioctl.h
index ee0c6e8995da..424d5e622b43 100644
--- a/include/linux/cciss_ioctl.h
+++ b/include/linux/cciss_ioctl.h
@@ -10,6 +10,7 @@
 typedef struct _cciss_pci_info_struct
 {
         unsigned char   bus;
+        unsigned short  domain;
         unsigned char   dev_fn;
         __u32           board_id;
 } cciss_pci_info_struct; 
diff --git a/include/linux/chio.h b/include/linux/chio.h
new file mode 100644
index 000000000000..63035ae67e63
--- /dev/null
+++ b/include/linux/chio.h
@@ -0,0 +1,168 @@
+/*
+ * ioctl interface for the scsi media changer driver
+ */
+
+/* changer element types */
+#define CHET_MT   0     /* media transport element (robot) */
+#define CHET_ST   1     /* storage element (media slots) */
+#define CHET_IE   2     /* import/export element */
+#define CHET_DT   3     /* data transfer element (tape/cdrom/whatever) */
+#define CHET_V1   4     /* vendor specific #1 */
+#define CHET_V2   5     /* vendor specific #2 */
+#define CHET_V3   6     /* vendor specific #3 */
+#define CHET_V4   7     /* vendor specific #4 */
+
+
+/*
+ * CHIOGPARAMS
+ *    query changer properties
+ *
+ * CHIOVGPARAMS
+ *    query vendor-specific element types
+ *
+ *    accessing elements works by specifing type and unit of the element.
+ *    for eample, storage elements are addressed with type = CHET_ST and
+ *    unit = 0 .. cp_nslots-1
+ *
+ */
+struct changer_params {
+        int cp_curpicker;  /* current transport element */
+        int cp_npickers;   /* number of transport elements      (CHET_MT) */
+        int cp_nslots;     /* number of storage elements        (CHET_ST) */
+        int cp_nportals;   /* number of import/export elements  (CHET_IE) */
+        int cp_ndrives;    /* number of data transfer elements  (CHET_DT) */
+};
+struct changer_vendor_params {
+        int  cvp_n1;       /* number of vendor specific elems   (CHET_V1) */
+        char cvp_label1[16];
+        int  cvp_n2;       /* number of vendor specific elems   (CHET_V2) */
+        char cvp_label2[16];
+        int  cvp_n3;       /* number of vendor specific elems   (CHET_V3) */
+        char cvp_label3[16];
+        int  cvp_n4;       /* number of vendor specific elems   (CHET_V4) */
+        char cvp_label4[16];
+        int  reserved[8];
+};
+
+
+/*
+ * CHIOMOVE
+ *    move a medium from one element to another
+ */
+struct changer_move {
+        int cm_fromtype;        /* type/unit of source element */
+        int cm_fromunit;        
+        int cm_totype;  /* type/unit of destination element */
+        int cm_tounit;
+        int cm_flags;
+};
+#define CM_INVERT   1   /* flag: rotate media (for double-sided like MOD) */
+
+
+/*
+ * CHIOEXCHANGE
+ *    move one medium from element #1 to element #2,
+ *    and another one from element #2 to element #3.
+ *    element #1 and #3 are allowed to be identical.
+ */
+struct changer_exchange {
+        int ce_srctype;     /* type/unit of element #1 */
+        int ce_srcunit;
+        int ce_fdsttype;    /* type/unit of element #2 */
+        int ce_fdstunit;
+        int ce_sdsttype;    /* type/unit of element #3 */
+        int ce_sdstunit;
+        int ce_flags;
+};
+#define CE_INVERT1   1
+#define CE_INVERT2   2
+
+
+/*
+ * CHIOPOSITION
+ *    move the transport element (robot arm) to a specific element.
+ */
+struct changer_position {
+        int cp_type;
+        int cp_unit;
+        int cp_flags;
+};
+#define CP_INVERT   1
+
+
+/*
+ * CHIOGSTATUS
+ *    get element status for all elements of a specific type
+ */
+struct changer_element_status {
+        int             ces_type;
+        unsigned char   *ces_data;
+};
+#define CESTATUS_FULL     0x01 /* full */
+#define CESTATUS_IMPEXP   0x02  /* media was imported (inserted by sysop) */
+#define CESTATUS_EXCEPT   0x04  /* error condition */
+#define CESTATUS_ACCESS   0x08  /* access allowed */
+#define CESTATUS_EXENAB   0x10  /* element can export media */
+#define CESTATUS_INENAB   0x20  /* element can import media */
+
+
+/*
+ * CHIOGELEM
+ *    get more detailed status informtion for a single element
+ */
+struct changer_get_element {
+        int     cge_type;        /* type/unit */
+        int     cge_unit;
+        int     cge_status;      /* status */
+        int     cge_errno;       /* errno */
+        int     cge_srctype;     /* source element of the last move/exchange */
+        int     cge_srcunit;
+        int     cge_id;          /* scsi id  (for data transfer elements) */
+        int     cge_lun;         /* scsi lun (for data transfer elements) */
+        char    cge_pvoltag[36]; /* primary volume tag */
+        char    cge_avoltag[36]; /* alternate volume tag */
+        int     cge_flags;
+};
+/* flags */
+#define CGE_ERRNO     0x01       /* errno available       */
+#define CGE_INVERT    0x02       /* media inverted        */
+#define CGE_SRC       0x04       /* media src available   */
+#define CGE_IDLUN     0x08       /* ID+LUN available      */
+#define CGE_PVOLTAG   0x10       /* primary volume tag available */
+#define CGE_AVOLTAG   0x20       /* alternate volume tag available */
+
+
+/*
+ * CHIOSVOLTAG
+ *    set volume tag
+ */
+struct changer_set_voltag {
+        int     csv_type;        /* type/unit */
+        int     csv_unit;
+        char    csv_voltag[36];  /* volume tag */
+        int     csv_flags;
+};
+#define CSV_PVOLTAG   0x01       /* primary volume tag */
+#define CSV_AVOLTAG   0x02       /* alternate volume tag */
+#define CSV_CLEARTAG  0x04       /* clear volume tag */
+
+/* ioctls */
+#define CHIOMOVE       _IOW('c', 1,struct changer_move)
+#define CHIOEXCHANGE   _IOW('c', 2,struct changer_exchange)
+#define CHIOPOSITION   _IOW('c', 3,struct changer_position)
+#define CHIOGPICKER    _IOR('c', 4,int)                        /* not impl. */
+#define CHIOSPICKER    _IOW('c', 5,int)                        /* not impl. */
+#define CHIOGPARAMS    _IOR('c', 6,struct changer_params)
+#define CHIOGSTATUS    _IOW('c', 8,struct changer_element_status)
+#define CHIOGELEM      _IOW('c',16,struct changer_get_element)
+#define CHIOINITELEM   _IO('c',17)
+#define CHIOSVOLTAG    _IOW('c',18,struct changer_set_voltag)
+#define CHIOGVPARAMS   _IOR('c',19,struct changer_vendor_params)
+
+/* ---------------------------------------------------------------------- */
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/include/linux/compat.h b/include/linux/compat.h
index b58b7d6f2fdb..f9ca534787e2 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -18,6 +18,9 @@
 #define compat_jiffies_to_clock_t(x)    \
                 (((unsigned long)(x) * COMPAT_USER_HZ) / HZ)
 
+typedef __compat_uid32_t        compat_uid_t;
+typedef __compat_gid32_t        compat_gid_t;
+
 struct rusage;
 
 struct compat_itimerspec { 
diff --git a/include/linux/compat_ioctl.h b/include/linux/compat_ioctl.h
index 70a4ebb5d964..ecb0d39c0798 100644
--- a/include/linux/compat_ioctl.h
+++ b/include/linux/compat_ioctl.h
@@ -346,10 +346,27 @@ COMPATIBLE_IOCTL(PPPOEIOCDFWD)
 /* LP */
 COMPATIBLE_IOCTL(LPGETSTATUS)
 /* ppdev */
+COMPATIBLE_IOCTL(PPSETMODE)
+COMPATIBLE_IOCTL(PPRSTATUS)
+COMPATIBLE_IOCTL(PPRCONTROL)
+COMPATIBLE_IOCTL(PPWCONTROL)
+COMPATIBLE_IOCTL(PPFCONTROL)
+COMPATIBLE_IOCTL(PPRDATA)
+COMPATIBLE_IOCTL(PPWDATA)
 COMPATIBLE_IOCTL(PPCLAIM)
 COMPATIBLE_IOCTL(PPRELEASE)
-COMPATIBLE_IOCTL(PPEXCL)
 COMPATIBLE_IOCTL(PPYIELD)
+COMPATIBLE_IOCTL(PPEXCL)
+COMPATIBLE_IOCTL(PPDATADIR)
+COMPATIBLE_IOCTL(PPNEGOT)
+COMPATIBLE_IOCTL(PPWCTLONIRQ)
+COMPATIBLE_IOCTL(PPCLRIRQ)
+COMPATIBLE_IOCTL(PPSETPHASE)
+COMPATIBLE_IOCTL(PPGETMODES)
+COMPATIBLE_IOCTL(PPGETMODE)
+COMPATIBLE_IOCTL(PPGETPHASE)
+COMPATIBLE_IOCTL(PPGETFLAGS)
+COMPATIBLE_IOCTL(PPSETFLAGS)
 /* CDROM stuff */
 COMPATIBLE_IOCTL(CDROMPAUSE)
 COMPATIBLE_IOCTL(CDROMRESUME)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index fe0298e5dae1..86980c68234a 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -8,7 +8,7 @@
  * Basic handling of the devices is done in drivers/base/cpu.c
  * and system devices are handled in drivers/base/sys.c. 
  *
- * CPUs are exported via driverfs in the class/cpu/devices/
+ * CPUs are exported via sysfs in the class/cpu/devices/
  * directory. 
  *
  * Per-cpu interfaces can be implemented using a struct device_interface. 
@@ -69,6 +69,7 @@ extern struct semaphore cpucontrol;
         register_cpu_notifier(&fn##_nb);                        \
 }
 int cpu_down(unsigned int cpu);
+extern int __attribute__((weak)) smp_prepare_cpu(int cpu);
 #define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
 #else
 #define lock_cpu_hotplug()      do { } while (0)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 927daa86c9b3..ff7f80f48df1 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -201,7 +201,7 @@ struct cpufreq_driver {
 
         /* optional */
         int     (*exit)         (struct cpufreq_policy *policy);
-        int     (*suspend)      (struct cpufreq_policy *policy, u32 state);
+        int     (*suspend)      (struct cpufreq_policy *policy, pm_message_t pmsg);
         int     (*resume)       (struct cpufreq_policy *policy);
         struct freq_attr        **attr;
 };
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index 3438233305a3..24062a1dbf61 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -23,7 +23,8 @@ void cpuset_init_current_mems_allowed(void);
 void cpuset_update_current_mems_allowed(void);
 void cpuset_restrict_to_mems_allowed(unsigned long *nodes);
 int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl);
-int cpuset_zone_allowed(struct zone *z);
+extern int cpuset_zone_allowed(struct zone *z, unsigned int __nocast gfp_mask);
+extern int cpuset_excl_nodes_overlap(const struct task_struct *p);
 extern struct file_operations proc_cpuset_operations;
 extern char *cpuset_task_status_allowed(struct task_struct *task, char *buffer);
 
@@ -48,7 +49,13 @@ static inline int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl)
         return 1;
 }
 
-static inline int cpuset_zone_allowed(struct zone *z)
+static inline int cpuset_zone_allowed(struct zone *z,
+                                        unsigned int __nocast gfp_mask)
+{
+        return 1;
+}
+
+static inline int cpuset_excl_nodes_overlap(const struct task_struct *p)
 {
         return 1;
 }
diff --git a/include/linux/crash_dump.h b/include/linux/crash_dump.h
new file mode 100644
index 000000000000..534d750d922d
--- /dev/null
+++ b/include/linux/crash_dump.h
@@ -0,0 +1,18 @@
+#ifndef LINUX_CRASH_DUMP_H
+#define LINUX_CRASH_DUMP_H
+
+#ifdef CONFIG_CRASH_DUMP
+#include <linux/kexec.h>
+#include <linux/smp_lock.h>
+#include <linux/device.h>
+#include <linux/proc_fs.h>
+
+#define ELFCORE_ADDR_MAX        (-1ULL)
+extern unsigned long long elfcorehdr_addr;
+extern ssize_t copy_oldmem_page(unsigned long, char *, size_t,
+                                                unsigned long, int);
+extern struct file_operations proc_vmcore_operations;
+extern struct proc_dir_entry *proc_vmcore;
+
+#endif /* CONFIG_CRASH_DUMP */
+#endif /* LINUX_CRASHDUMP_H */
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 387da6a3e58c..3c89df6e7768 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -45,6 +45,7 @@
 #define CRYPTO_TFM_MODE_CTR             0x00000008
 
 #define CRYPTO_TFM_REQ_WEAK_KEY         0x00000100
+#define CRYPTO_TFM_REQ_MAY_SLEEP        0x00000200
 #define CRYPTO_TFM_RES_WEAK_KEY         0x00100000
 #define CRYPTO_TFM_RES_BAD_KEY_LEN      0x00200000
 #define CRYPTO_TFM_RES_BAD_KEY_SCHED    0x00400000
@@ -61,6 +62,15 @@
 #define CRYPTO_DIR_DECRYPT              0
 
 struct scatterlist;
+struct crypto_tfm;
+
+struct cipher_desc {
+        struct crypto_tfm *tfm;
+        void (*crfn)(void *ctx, u8 *dst, const u8 *src);
+        unsigned int (*prfn)(const struct cipher_desc *desc, u8 *dst,
+                             const u8 *src, unsigned int nbytes);
+        void *info;
+};
 
 /*
  * Algorithms: modular crypto algorithm implementations, managed
@@ -73,6 +83,19 @@ struct cipher_alg {
                           unsigned int keylen, u32 *flags);
         void (*cia_encrypt)(void *ctx, u8 *dst, const u8 *src);
         void (*cia_decrypt)(void *ctx, u8 *dst, const u8 *src);
+
+        unsigned int (*cia_encrypt_ecb)(const struct cipher_desc *desc,
+                                        u8 *dst, const u8 *src,
+                                        unsigned int nbytes);
+        unsigned int (*cia_decrypt_ecb)(const struct cipher_desc *desc,
+                                        u8 *dst, const u8 *src,
+                                        unsigned int nbytes);
+        unsigned int (*cia_encrypt_cbc)(const struct cipher_desc *desc,
+                                        u8 *dst, const u8 *src,
+                                        unsigned int nbytes);
+        unsigned int (*cia_decrypt_cbc)(const struct cipher_desc *desc,
+                                        u8 *dst, const u8 *src,
+                                        unsigned int nbytes);
 };
 
 struct digest_alg {
@@ -102,6 +125,7 @@ struct crypto_alg {
         u32 cra_flags;
         unsigned int cra_blocksize;
         unsigned int cra_ctxsize;
+        unsigned int cra_alignmask;
         const char cra_name[CRYPTO_MAX_ALG_NAME];
 
         union {
@@ -136,7 +160,6 @@ static inline int crypto_alg_available(const char *name, u32 flags)
  * and core processing logic.  Managed via crypto_alloc_tfm() and
  * crypto_free_tfm(), as well as the various helpers below.
  */
-struct crypto_tfm;
 
 struct cipher_tfm {
         void *cit_iv;
@@ -266,6 +289,16 @@ static inline unsigned int crypto_tfm_alg_digestsize(struct crypto_tfm *tfm)
         return tfm->__crt_alg->cra_digest.dia_digestsize;
 }
 
+static inline unsigned int crypto_tfm_alg_alignmask(struct crypto_tfm *tfm)
+{
+        return tfm->__crt_alg->cra_alignmask;
+}
+
+static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm)
+{
+        return (void *)&tfm[1];
+}
+
 /*
  * API wrappers.
  */
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 50be290d24d2..ab04b4f9b0db 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -88,8 +88,9 @@ struct dentry {
                                          * negative */
         /*
          * The next three fields are touched by __d_lookup.  Place them here
-         * so they all fit in a 16-byte range, with 16-byte alignment.
+         * so they all fit in a cache line.
          */
+        struct hlist_node d_hash;       /* lookup hash list */
         struct dentry *d_parent;        /* parent directory */
         struct qstr d_name;
 
@@ -103,7 +104,6 @@ struct dentry {
         void *d_fsdata;                 /* fs-specific data */
         struct rcu_head d_rcu;
         struct dcookie_struct *d_cookie; /* cookie, if any */
-        struct hlist_node d_hash;       /* lookup hash list */  
         int d_mounted;
         unsigned char d_iname[DNAME_INLINE_LEN_MIN];    /* small names */
 };
diff --git a/include/linux/dccp.h b/include/linux/dccp.h
new file mode 100644
index 000000000000..007c290f74d4
--- /dev/null
+++ b/include/linux/dccp.h
@@ -0,0 +1,456 @@
+#ifndef _LINUX_DCCP_H
+#define _LINUX_DCCP_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/* Structure describing an Internet (DCCP) socket address. */
+struct sockaddr_dccp {
+        __u16   sdccp_family;   /* Address family   */
+        __u16   sdccp_port;     /* Port number      */
+        __u32   sdccp_addr;     /* Internet address */
+        __u32   sdccp_service;  /* Service          */
+        /* Pad to size of `struct sockaddr': 16 bytes . */
+        __u32   sdccp_pad;
+};
+
+/**
+ * struct dccp_hdr - generic part of DCCP packet header
+ *
+ * @dccph_sport - Relevant port on the endpoint that sent this packet
+ * @dccph_dport - Relevant port on the other endpoint
+ * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
+ * @dccph_ccval - Used by the HC-Sender CCID
+ * @dccph_cscov - Parts of the packet that are covered by the Checksum field
+ * @dccph_checksum - Internet checksum, depends on dccph_cscov
+ * @dccph_x - 0 = 24 bit sequence number, 1 = 48
+ * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
+ * @dccph_seq - sequence number high or low order 24 bits, depends on dccph_x
+ */
+struct dccp_hdr {
+        __u16   dccph_sport,
+                dccph_dport;
+        __u8    dccph_doff;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        __u8    dccph_cscov:4,
+                dccph_ccval:4;
+#elif defined(__BIG_ENDIAN_BITFIELD)
+        __u8    dccph_ccval:4,
+                dccph_cscov:4;
+#else
+#error  "Adjust your <asm/byteorder.h> defines"
+#endif
+        __u16   dccph_checksum;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        __u32   dccph_x:1,
+                dccph_type:4,
+                dccph_reserved:3,
+                dccph_seq:24;
+#elif defined(__BIG_ENDIAN_BITFIELD)
+        __u32   dccph_reserved:3,
+                dccph_type:4,
+                dccph_x:1,
+                dccph_seq:24;
+#else
+#error  "Adjust your <asm/byteorder.h> defines"
+#endif
+};
+
+/**
+ * struct dccp_hdr_ext - the low bits of a 48 bit seq packet
+ *
+ * @dccph_seq_low - low 24 bits of a 48 bit seq packet
+ */
+struct dccp_hdr_ext {
+        __u32   dccph_seq_low;
+};
+
+/**
+ * struct dccp_hdr_request - Conection initiation request header
+ *
+ * @dccph_req_service - Service to which the client app wants to connect
+ * @dccph_req_options - list of options (must be a multiple of 32 bits
+ */
+struct dccp_hdr_request {
+        __u32   dccph_req_service;
+};
+/**
+ * struct dccp_hdr_ack_bits - acknowledgment bits common to most packets
+ *
+ * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR
+ * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR
+ */
+struct dccp_hdr_ack_bits {
+        __u32   dccph_reserved1:8,
+                dccph_ack_nr_high:24;
+        __u32   dccph_ack_nr_low;
+};
+/**
+ * struct dccp_hdr_response - Conection initiation response header
+ *
+ * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR
+ * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR
+ * @dccph_resp_service - Echoes the Service Code on a received DCCP-Request
+ * @dccph_resp_options - list of options (must be a multiple of 32 bits
+ */
+struct dccp_hdr_response {
+        struct dccp_hdr_ack_bits        dccph_resp_ack;
+        __u32                           dccph_resp_service;
+};
+
+/**
+ * struct dccp_hdr_reset - Unconditionally shut down a connection
+ *
+ * @dccph_reset_service - Echoes the Service Code on a received DCCP-Request
+ * @dccph_reset_options - list of options (must be a multiple of 32 bits
+ */
+struct dccp_hdr_reset {
+        struct dccp_hdr_ack_bits        dccph_reset_ack;
+        __u8                            dccph_reset_code,
+                                        dccph_reset_data[3];
+};
+
+enum dccp_pkt_type {
+        DCCP_PKT_REQUEST = 0,
+        DCCP_PKT_RESPONSE,
+        DCCP_PKT_DATA,
+        DCCP_PKT_ACK,
+        DCCP_PKT_DATAACK,
+        DCCP_PKT_CLOSEREQ,
+        DCCP_PKT_CLOSE,
+        DCCP_PKT_RESET,
+        DCCP_PKT_SYNC,
+        DCCP_PKT_SYNCACK,
+        DCCP_PKT_INVALID,
+};
+
+#define DCCP_NR_PKT_TYPES DCCP_PKT_INVALID
+
+static inline unsigned int dccp_packet_hdr_len(const __u8 type)
+{
+        if (type == DCCP_PKT_DATA)
+                return 0;
+        if (type == DCCP_PKT_DATAACK    ||
+            type == DCCP_PKT_ACK        ||
+            type == DCCP_PKT_SYNC       ||
+            type == DCCP_PKT_SYNCACK    ||
+            type == DCCP_PKT_CLOSE      ||
+            type == DCCP_PKT_CLOSEREQ)
+                return sizeof(struct dccp_hdr_ack_bits);
+        if (type == DCCP_PKT_REQUEST)
+                return sizeof(struct dccp_hdr_request);
+        if (type == DCCP_PKT_RESPONSE)
+                return sizeof(struct dccp_hdr_response);
+        return sizeof(struct dccp_hdr_reset);
+}
+enum dccp_reset_codes {
+        DCCP_RESET_CODE_UNSPECIFIED = 0,
+        DCCP_RESET_CODE_CLOSED,
+        DCCP_RESET_CODE_ABORTED,
+        DCCP_RESET_CODE_NO_CONNECTION,
+        DCCP_RESET_CODE_PACKET_ERROR,
+        DCCP_RESET_CODE_OPTION_ERROR,
+        DCCP_RESET_CODE_MANDATORY_ERROR,
+        DCCP_RESET_CODE_CONNECTION_REFUSED,
+        DCCP_RESET_CODE_BAD_SERVICE_CODE,
+        DCCP_RESET_CODE_TOO_BUSY,
+        DCCP_RESET_CODE_BAD_INIT_COOKIE,
+        DCCP_RESET_CODE_AGGRESSION_PENALTY,
+};
+
+/* DCCP options */
+enum {
+        DCCPO_PADDING = 0,
+        DCCPO_MANDATORY = 1,
+        DCCPO_MIN_RESERVED = 3,
+        DCCPO_MAX_RESERVED = 31,
+        DCCPO_NDP_COUNT = 37,
+        DCCPO_ACK_VECTOR_0 = 38,
+        DCCPO_ACK_VECTOR_1 = 39,
+        DCCPO_TIMESTAMP = 41,
+        DCCPO_TIMESTAMP_ECHO = 42,
+        DCCPO_ELAPSED_TIME = 43,
+        DCCPO_MAX = 45,
+        DCCPO_MIN_CCID_SPECIFIC = 128,
+        DCCPO_MAX_CCID_SPECIFIC = 255,
+};
+
+/* DCCP features */
+enum {
+        DCCPF_RESERVED = 0,
+        DCCPF_SEQUENCE_WINDOW = 3,
+        DCCPF_SEND_ACK_VECTOR = 6,
+        DCCPF_SEND_NDP_COUNT = 7,
+        /* 10-127 reserved */
+        DCCPF_MIN_CCID_SPECIFIC = 128,
+        DCCPF_MAX_CCID_SPECIFIC = 255,
+};
+
+/* DCCP socket options */
+#define DCCP_SOCKOPT_PACKET_SIZE        1
+
+#ifdef __KERNEL__
+
+#include <linux/in.h>
+#include <linux/list.h>
+#include <linux/uio.h>
+#include <linux/workqueue.h>
+
+#include <net/inet_connection_sock.h>
+#include <net/inet_timewait_sock.h>
+#include <net/sock.h>
+#include <net/tcp_states.h>
+#include <net/tcp.h>
+
+enum dccp_state {
+        DCCP_OPEN       = TCP_ESTABLISHED,
+        DCCP_REQUESTING = TCP_SYN_SENT,
+        DCCP_PARTOPEN   = TCP_FIN_WAIT1, /* FIXME:
+                                            This mapping is horrible, but TCP has
+                                            no matching state for DCCP_PARTOPEN,
+                                            as TCP_SYN_RECV is already used by
+                                            DCCP_RESPOND, why don't stop using TCP
+                                            mapping of states? OK, now we don't use
+                                            sk_stream_sendmsg anymore, so doesn't
+                                            seem to exist any reason for us to
+                                            do the TCP mapping here */
+        DCCP_LISTEN     = TCP_LISTEN,
+        DCCP_RESPOND    = TCP_SYN_RECV,
+        DCCP_CLOSING    = TCP_CLOSING,
+        DCCP_TIME_WAIT  = TCP_TIME_WAIT,
+        DCCP_CLOSED     = TCP_CLOSE,
+        DCCP_MAX_STATES = TCP_MAX_STATES,
+};
+
+#define DCCP_STATE_MASK 0xf
+#define DCCP_ACTION_FIN (1<<7)
+
+enum {
+        DCCPF_OPEN       = TCPF_ESTABLISHED,
+        DCCPF_REQUESTING = TCPF_SYN_SENT,
+        DCCPF_PARTOPEN   = TCPF_FIN_WAIT1,
+        DCCPF_LISTEN     = TCPF_LISTEN,
+        DCCPF_RESPOND    = TCPF_SYN_RECV,
+        DCCPF_CLOSING    = TCPF_CLOSING,
+        DCCPF_TIME_WAIT  = TCPF_TIME_WAIT,
+        DCCPF_CLOSED     = TCPF_CLOSE,
+};
+
+static inline struct dccp_hdr *dccp_hdr(const struct sk_buff *skb)
+{
+        return (struct dccp_hdr *)skb->h.raw;
+}
+
+static inline struct dccp_hdr_ext *dccp_hdrx(const struct sk_buff *skb)
+{
+        return (struct dccp_hdr_ext *)(skb->h.raw + sizeof(struct dccp_hdr));
+}
+
+static inline unsigned int __dccp_basic_hdr_len(const struct dccp_hdr *dh)
+{
+        return sizeof(*dh) + (dh->dccph_x ? sizeof(struct dccp_hdr_ext) : 0);
+}
+
+static inline unsigned int dccp_basic_hdr_len(const struct sk_buff *skb)
+{
+        const struct dccp_hdr *dh = dccp_hdr(skb);
+        return __dccp_basic_hdr_len(dh);
+}
+
+static inline __u64 dccp_hdr_seq(const struct sk_buff *skb)
+{
+        const struct dccp_hdr *dh = dccp_hdr(skb);
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        __u64 seq_nr = ntohl(dh->dccph_seq << 8);
+#elif defined(__BIG_ENDIAN_BITFIELD)
+        __u64 seq_nr = ntohl(dh->dccph_seq);
+#else
+#error  "Adjust your <asm/byteorder.h> defines"
+#endif
+
+        if (dh->dccph_x != 0)
+                seq_nr = (seq_nr << 32) + ntohl(dccp_hdrx(skb)->dccph_seq_low);
+
+        return seq_nr;
+}
+
+static inline struct dccp_hdr_request *dccp_hdr_request(struct sk_buff *skb)
+{
+        return (struct dccp_hdr_request *)(skb->h.raw + dccp_basic_hdr_len(skb));
+}
+
+static inline struct dccp_hdr_ack_bits *dccp_hdr_ack_bits(const struct sk_buff *skb)
+{
+        return (struct dccp_hdr_ack_bits *)(skb->h.raw + dccp_basic_hdr_len(skb));
+}
+
+static inline u64 dccp_hdr_ack_seq(const struct sk_buff *skb)
+{
+        const struct dccp_hdr_ack_bits *dhack = dccp_hdr_ack_bits(skb);
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        return (((u64)ntohl(dhack->dccph_ack_nr_high << 8)) << 32) + ntohl(dhack->dccph_ack_nr_low);
+#elif defined(__BIG_ENDIAN_BITFIELD)
+        return (((u64)ntohl(dhack->dccph_ack_nr_high)) << 32) + ntohl(dhack->dccph_ack_nr_low);
+#else
+#error  "Adjust your <asm/byteorder.h> defines"
+#endif
+}
+
+static inline struct dccp_hdr_response *dccp_hdr_response(struct sk_buff *skb)
+{
+        return (struct dccp_hdr_response *)(skb->h.raw + dccp_basic_hdr_len(skb));
+}
+
+static inline struct dccp_hdr_reset *dccp_hdr_reset(struct sk_buff *skb)
+{
+        return (struct dccp_hdr_reset *)(skb->h.raw + dccp_basic_hdr_len(skb));
+}
+
+static inline unsigned int __dccp_hdr_len(const struct dccp_hdr *dh)
+{
+        return __dccp_basic_hdr_len(dh) +
+               dccp_packet_hdr_len(dh->dccph_type);
+}
+
+static inline unsigned int dccp_hdr_len(const struct sk_buff *skb)
+{
+        return __dccp_hdr_len(dccp_hdr(skb));
+}
+
+
+/* initial values for each feature */
+#define DCCPF_INITIAL_SEQUENCE_WINDOW           100
+/* FIXME: for now we're using CCID 3 (TFRC) */
+#define DCCPF_INITIAL_CCID                      3
+#define DCCPF_INITIAL_SEND_ACK_VECTOR           0
+/* FIXME: for now we're default to 1 but it should really be 0 */
+#define DCCPF_INITIAL_SEND_NDP_COUNT            1
+
+#define DCCP_NDP_LIMIT 0xFFFFFF
+
+/**
+  * struct dccp_options - option values for a DCCP connection
+  *     @dccpo_sequence_window - Sequence Window Feature (section 7.5.2)
+  *     @dccpo_ccid - Congestion Control Id (CCID) (section 10)
+  *     @dccpo_send_ack_vector - Send Ack Vector Feature (section 11.5)
+  *     @dccpo_send_ndp_count - Send NDP Count Feature (7.7.2)
+  */
+struct dccp_options {
+        __u64   dccpo_sequence_window;
+        __u8    dccpo_ccid;
+        __u8    dccpo_send_ack_vector;
+        __u8    dccpo_send_ndp_count;
+};
+
+extern void __dccp_options_init(struct dccp_options *dccpo);
+extern void dccp_options_init(struct dccp_options *dccpo);
+extern int dccp_parse_options(struct sock *sk, struct sk_buff *skb);
+
+struct dccp_request_sock {
+        struct inet_request_sock dreq_inet_rsk;
+        __u64                    dreq_iss;
+        __u64                    dreq_isr;
+        __u32                    dreq_service;
+};
+
+static inline struct dccp_request_sock *dccp_rsk(const struct request_sock *req)
+{
+        return (struct dccp_request_sock *)req;
+}
+
+extern struct inet_timewait_death_row dccp_death_row;
+
+/* Read about the ECN nonce to see why it is 253 */
+#define DCCP_MAX_ACK_VECTOR_LEN 253
+
+struct dccp_options_received {
+        u32     dccpor_ndp:24,
+                dccpor_ack_vector_len:8;
+        u32     dccpor_ack_vector_idx:10;
+        /* 22 bits hole, try to pack */
+        u32     dccpor_timestamp;
+        u32     dccpor_timestamp_echo;
+        u32     dccpor_elapsed_time;
+};
+
+struct ccid;
+
+enum dccp_role {
+        DCCP_ROLE_UNDEFINED,
+        DCCP_ROLE_LISTEN,
+        DCCP_ROLE_CLIENT,
+        DCCP_ROLE_SERVER,
+};
+
+/**
+ * struct dccp_sock - DCCP socket state
+ *
+ * @dccps_swl - sequence number window low
+ * @dccps_swh - sequence number window high
+ * @dccps_awl - acknowledgement number window low
+ * @dccps_awh - acknowledgement number window high
+ * @dccps_iss - initial sequence number sent
+ * @dccps_isr - initial sequence number received
+ * @dccps_osr - first OPEN sequence number received
+ * @dccps_gss - greatest sequence number sent
+ * @dccps_gsr - greatest valid sequence number received
+ * @dccps_gar - greatest valid ack number received on a non-Sync; initialized to %dccps_iss
+ * @dccps_timestamp_time - time of latest TIMESTAMP option
+ * @dccps_timestamp_echo - latest timestamp received on a TIMESTAMP option
+ * @dccps_ext_header_len - network protocol overhead (IP/IPv6 options)
+ * @dccps_pmtu_cookie - Last pmtu seen by socket
+ * @dccps_packet_size - Set thru setsockopt
+ * @dccps_role - Role of this sock, one of %dccp_role
+ * @dccps_ndp_count - number of Non Data Packets since last data packet
+ * @dccps_hc_rx_ackpkts - receiver half connection acked packets
+ */
+struct dccp_sock {
+        /* inet_connection_sock has to be the first member of dccp_sock */
+        struct inet_connection_sock     dccps_inet_connection;
+        __u64                           dccps_swl;
+        __u64                           dccps_swh;
+        __u64                           dccps_awl;
+        __u64                           dccps_awh;
+        __u64                           dccps_iss;
+        __u64                           dccps_isr;
+        __u64                           dccps_osr;
+        __u64                           dccps_gss;
+        __u64                           dccps_gsr;
+        __u64                           dccps_gar;
+        unsigned long                   dccps_service;
+        struct timeval                  dccps_timestamp_time;
+        __u32                           dccps_timestamp_echo;
+        __u32                           dccps_packet_size;
+        unsigned long                   dccps_ndp_count;
+        __u16                           dccps_ext_header_len;
+        __u32                           dccps_pmtu_cookie;
+        __u32                           dccps_mss_cache;
+        struct dccp_options             dccps_options;
+        struct dccp_ackpkts             *dccps_hc_rx_ackpkts;
+        void                            *dccps_hc_rx_ccid_private;
+        void                            *dccps_hc_tx_ccid_private;
+        struct ccid                     *dccps_hc_rx_ccid;
+        struct ccid                     *dccps_hc_tx_ccid;
+        struct dccp_options_received    dccps_options_received;
+        enum dccp_role                  dccps_role:2;
+};
+ 
+static inline struct dccp_sock *dccp_sk(const struct sock *sk)
+{
+        return (struct dccp_sock *)sk;
+}
+
+static inline const char *dccp_role(const struct sock *sk)
+{
+        switch (dccp_sk(sk)->dccps_role) {
+        case DCCP_ROLE_UNDEFINED: return "undefined";
+        case DCCP_ROLE_LISTEN:    return "listen";
+        case DCCP_ROLE_SERVER:    return "server";
+        case DCCP_ROLE_CLIENT:    return "client";
+        }
+        return NULL;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_DCCP_H */
diff --git a/include/linux/dcookies.h b/include/linux/dcookies.h
index c28050136164..1d68428c925d 100644
--- a/include/linux/dcookies.h
+++ b/include/linux/dcookies.h
@@ -48,12 +48,12 @@ int get_dcookie(struct dentry * dentry, struct vfsmount * vfsmnt,
 
 #else
 
-struct dcookie_user * dcookie_register(void)
+static inline struct dcookie_user * dcookie_register(void)
 {
         return NULL;
 }
 
-void dcookie_unregister(struct dcookie_user * user)
+static inline void dcookie_unregister(struct dcookie_user * user)
 {
         return;
 }
diff --git a/include/linux/device.h b/include/linux/device.h
index df94c0de53f2..06e5d42f2c7b 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -14,6 +14,7 @@
 #include <linux/config.h>
 #include <linux/ioport.h>
 #include <linux/kobject.h>
+#include <linux/klist.h>
 #include <linux/list.h>
 #include <linux/types.h>
 #include <linux/module.h>
@@ -44,14 +45,15 @@ struct device;
 struct device_driver;
 struct class;
 struct class_device;
-struct class_simple;
 
 struct bus_type {
-        char                    * name;
+        const char              * name;
 
         struct subsystem        subsys;
         struct kset             drivers;
         struct kset             devices;
+        struct klist            klist_devices;
+        struct klist            klist_drivers;
 
         struct bus_attribute    * bus_attrs;
         struct device_attribute * dev_attrs;
@@ -67,7 +69,7 @@ struct bus_type {
 extern int bus_register(struct bus_type * bus);
 extern void bus_unregister(struct bus_type * bus);
 
-extern int bus_rescan_devices(struct bus_type * bus);
+extern void bus_rescan_devices(struct bus_type * bus);
 
 extern struct bus_type * get_bus(struct bus_type * bus);
 extern void put_bus(struct bus_type * bus);
@@ -78,6 +80,8 @@ extern struct bus_type * find_bus(char * name);
 
 int bus_for_each_dev(struct bus_type * bus, struct device * start, void * data,
                      int (*fn)(struct device *, void *));
+struct device * bus_find_device(struct bus_type *bus, struct device *start,
+                                void *data, int (*match)(struct device *, void *));
 
 int bus_for_each_drv(struct bus_type * bus, struct device_driver * start, 
                      void * data, int (*fn)(struct device_driver *, void *));
@@ -98,17 +102,18 @@ extern int bus_create_file(struct bus_type *, struct bus_attribute *);
 extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
 
 struct device_driver {
-        char                    * name;
+        const char              * name;
         struct bus_type         * bus;
 
         struct completion       unloaded;
         struct kobject          kobj;
-        struct list_head        devices;
+        struct klist            klist_devices;
+        struct klist_node       knode_bus;
 
-        struct module           * owner;
+        struct module           * owner;
 
         int     (*probe)        (struct device * dev);
-        int     (*remove)       (struct device * dev);
+        int     (*remove)       (struct device * dev);
         void    (*shutdown)     (struct device * dev);
         int     (*suspend)      (struct device * dev, pm_message_t state, u32 level);
         int     (*resume)       (struct device * dev, u32 level);
@@ -137,12 +142,19 @@ struct driver_attribute driver_attr_##_name = __ATTR(_name,_mode,_show,_store)
 extern int driver_create_file(struct device_driver *, struct driver_attribute *);
 extern void driver_remove_file(struct device_driver *, struct driver_attribute *);
 
+extern int driver_for_each_device(struct device_driver * drv, struct device * start,
+                                  void * data, int (*fn)(struct device *, void *));
+struct device * driver_find_device(struct device_driver *drv,
+                                   struct device *start, void *data,
+                                   int (*match)(struct device *, void *));
+
 
 /*
  * device classes
  */
 struct class {
-        char                    * name;
+        const char              * name;
+        struct module           * owner;
 
         struct subsystem        subsys;
         struct list_head        children;
@@ -185,6 +197,7 @@ struct class_device {
         struct kobject          kobj;
         struct class            * class;        /* required */
         dev_t                   devt;           /* dev_t, creates the sysfs "dev" */
+        struct class_device_attribute *devt_attr;
         struct device           * dev;          /* not necessary, but nice to have */
         void                    * class_data;   /* class-specific data */
 
@@ -245,32 +258,36 @@ struct class_interface {
 extern int class_interface_register(struct class_interface *);
 extern void class_interface_unregister(struct class_interface *);
 
-/* interface for class simple stuff */
-extern struct class_simple *class_simple_create(struct module *owner, char *name);
-extern void class_simple_destroy(struct class_simple *cs);
-extern struct class_device *class_simple_device_add(struct class_simple *cs, dev_t dev, struct device *device, const char *fmt, ...)
-        __attribute__((format(printf,4,5)));
-extern int class_simple_set_hotplug(struct class_simple *, 
-        int (*hotplug)(struct class_device *dev, char **envp, int num_envp, char *buffer, int buffer_size));
-extern void class_simple_device_remove(dev_t dev);
+extern struct class *class_create(struct module *owner, char *name);
+extern void class_destroy(struct class *cls);
+extern struct class_device *class_device_create(struct class *cls, dev_t devt,
+                                                struct device *device, char *fmt, ...)
+                                        __attribute__((format(printf,4,5)));
+extern void class_device_destroy(struct class *cls, dev_t devt);
 
 
 struct device {
-        struct list_head node;          /* node in sibling list */
-        struct list_head bus_list;      /* node in bus's list */
-        struct list_head driver_list;
-        struct list_head children;
+        struct klist            klist_children;
+        struct klist_node       knode_parent;           /* node in sibling list */
+        struct klist_node       knode_driver;
+        struct klist_node       knode_bus;
         struct device   * parent;
 
         struct kobject kobj;
         char    bus_id[BUS_ID_SIZE];    /* position on parent bus */
 
+        struct semaphore        sem;    /* semaphore to synchronize calls to
+                                         * its driver.
+                                         */
+
         struct bus_type * bus;          /* type of bus device is on */
         struct device_driver *driver;   /* which driver has allocated this
                                            device */
         void            *driver_data;   /* data private to the driver */
-        void            *platform_data; /* Platform specific data (e.g. ACPI,
-                                           BIOS data relevant to device) */
+        void            *platform_data; /* Platform specific data, device
+                                           core doesn't touch it */
+        void            *firmware_data; /* Firmware specific data (e.g. ACPI,
+                                           BIOS data),reserved for device core*/
         struct dev_pm_info      power;
 
         u64             *dma_mask;      /* dma mask (if dma'able device) */
@@ -288,12 +305,6 @@ struct device {
         void    (*release)(struct device * dev);
 };
 
-static inline struct device *
-list_to_dev(struct list_head *node)
-{
-        return list_entry(node, struct device, node);
-}
-
 static inline void *
 dev_get_drvdata (struct device *dev)
 {
@@ -321,7 +332,6 @@ extern int device_for_each_child(struct device *, void *,
  * Manual binding of a device to driver. See drivers/base/bus.c
  * for information on use.
  */
-extern int  driver_probe_device(struct device_driver * drv, struct device * dev);
 extern void device_bind_driver(struct device * dev);
 extern void device_release_driver(struct device * dev);
 extern int  device_attach(struct device * dev);
@@ -332,8 +342,10 @@ extern void driver_attach(struct device_driver * drv);
 
 struct device_attribute {
         struct attribute        attr;
-        ssize_t (*show)(struct device * dev, char * buf);
-        ssize_t (*store)(struct device * dev, const char * buf, size_t count);
+        ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+                        char *buf);
+        ssize_t (*store)(struct device *dev, struct device_attribute *attr,
+                         const char *buf, size_t count);
 };
 
 #define DEVICE_ATTR(_name,_mode,_show,_store) \
@@ -360,13 +372,12 @@ extern int (*platform_notify_remove)(struct device * dev);
  */
 extern struct device * get_device(struct device * dev);
 extern void put_device(struct device * dev);
-extern struct device *device_find(const char *name, struct bus_type *bus);
 
 
 /* drivers/base/platform.c */
 
 struct platform_device {
-        char            * name;
+        const char      * name;
         u32             id;
         struct device   dev;
         u32             num_resources;
diff --git a/include/linux/dm9000.h b/include/linux/dm9000.h
new file mode 100644
index 000000000000..0008e2ad0c9f
--- /dev/null
+++ b/include/linux/dm9000.h
@@ -0,0 +1,36 @@
+/* include/linux/dm9000.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for dm9000 platform data
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#ifndef __DM9000_PLATFORM_DATA
+#define __DM9000_PLATFORM_DATA __FILE__
+
+/* IO control flags */
+
+#define DM9000_PLATF_8BITONLY   (0x0001)
+#define DM9000_PLATF_16BITONLY  (0x0002)
+#define DM9000_PLATF_32BITONLY  (0x0004)
+
+/* platfrom data for platfrom device structure's platfrom_data field */
+
+struct dm9000_plat_data {
+        unsigned int    flags;
+
+        /* allow replacement IO routines */
+
+        void    (*inblk)(void __iomem *reg, void *data, int len);
+        void    (*outblk)(void __iomem *reg, void *data, int len);
+        void    (*dumpblk)(void __iomem *reg, int len);
+};
+
+#endif /* __DM9000_PLATFORM_DATA */
+
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 806c305332c1..2d80cc761a15 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -14,7 +14,12 @@ enum dma_data_direction {
 };
 
 #define DMA_64BIT_MASK  0xffffffffffffffffULL
+#define DMA_40BIT_MASK  0x000000ffffffffffULL
+#define DMA_39BIT_MASK  0x0000007fffffffffULL
 #define DMA_32BIT_MASK  0x00000000ffffffffULL
+#define DMA_31BIT_MASK  0x000000007fffffffULL
+#define DMA_30BIT_MASK  0x000000003fffffffULL
+#define DMA_29BIT_MASK  0x000000001fffffffULL
 
 #include <asm/dma-mapping.h>
 
diff --git a/include/linux/dmi.h b/include/linux/dmi.h
index d2bcf556088b..c30175e8dec6 100644
--- a/include/linux/dmi.h
+++ b/include/linux/dmi.h
@@ -1,6 +1,8 @@
 #ifndef __DMI_H__
 #define __DMI_H__
 
+#include <linux/list.h>
+
 enum dmi_field {
         DMI_NONE,
         DMI_BIOS_VENDOR,
@@ -9,12 +11,31 @@ enum dmi_field {
         DMI_SYS_VENDOR,
         DMI_PRODUCT_NAME,
         DMI_PRODUCT_VERSION,
+        DMI_PRODUCT_SERIAL,
         DMI_BOARD_VENDOR,
         DMI_BOARD_NAME,
         DMI_BOARD_VERSION,
         DMI_STRING_MAX,
 };
 
+enum dmi_device_type {
+        DMI_DEV_TYPE_ANY = 0,
+        DMI_DEV_TYPE_OTHER,
+        DMI_DEV_TYPE_UNKNOWN,
+        DMI_DEV_TYPE_VIDEO,
+        DMI_DEV_TYPE_SCSI,
+        DMI_DEV_TYPE_ETHERNET,
+        DMI_DEV_TYPE_TOKENRING,
+        DMI_DEV_TYPE_SOUND,
+        DMI_DEV_TYPE_IPMI = -1
+};
+
+struct dmi_header {
+        u8 type;
+        u8 length;
+        u16 handle;
+};
+
 /*
  *      DMI callbacks for problem boards
  */
@@ -25,22 +46,32 @@ struct dmi_strmatch {
 
 struct dmi_system_id {
         int (*callback)(struct dmi_system_id *);
-        char *ident;
+        const char *ident;
         struct dmi_strmatch matches[4];
         void *driver_data;
 };
 
-#define DMI_MATCH(a,b)  { a, b }
+#define DMI_MATCH(a, b) { a, b }
+
+struct dmi_device {
+        struct list_head list;
+        int type;
+        const char *name;
+        void *device_data;      /* Type specific data */
+};
 
 #if defined(CONFIG_X86) && !defined(CONFIG_X86_64)
 
 extern int dmi_check_system(struct dmi_system_id *list);
 extern char * dmi_get_system_info(int field);
-
+extern struct dmi_device * dmi_find_device(int type, const char *name,
+        struct dmi_device *from);
 #else
 
 static inline int dmi_check_system(struct dmi_system_id *list) { return 0; }
 static inline char * dmi_get_system_info(int field) { return NULL; }
+static struct dmi_device * dmi_find_device(int type, const char *name,
+        struct dmi_device *from) { return NULL; }
 
 #endif
 
diff --git a/include/linux/dqblk_v1.h b/include/linux/dqblk_v1.h
index 42fbf4797156..57f1250d5a52 100644
--- a/include/linux/dqblk_v1.h
+++ b/include/linux/dqblk_v1.h
@@ -11,6 +11,12 @@
 /* Root squash turned on */
 #define V1_DQF_RSQUASH 1
 
+/* Numbers of blocks needed for updates */
+#define V1_INIT_ALLOC 1
+#define V1_INIT_REWRITE 1
+#define V1_DEL_ALLOC 0
+#define V1_DEL_REWRITE 2
+
 /* Special information about quotafile */
 struct v1_mem_dqinfo {
 };
diff --git a/include/linux/dqblk_v2.h b/include/linux/dqblk_v2.h
index 4a6c5f6867bb..4f853322cb7f 100644
--- a/include/linux/dqblk_v2.h
+++ b/include/linux/dqblk_v2.h
@@ -10,6 +10,12 @@
 /* id numbers of quota format */
 #define QFMT_VFS_V0 2
 
+/* Numbers of blocks needed for updates */
+#define V2_INIT_ALLOC 4
+#define V2_INIT_REWRITE 2
+#define V2_DEL_ALLOC 0
+#define V2_DEL_REWRITE 6
+
 /* Inmemory copy of version specific information */
 struct v2_mem_dqinfo {
         unsigned int dqi_blocks;
diff --git a/include/linux/efi.h b/include/linux/efi.h
index 047e7222df7a..c7c5dd316182 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -91,11 +91,6 @@ typedef	struct {
 
 #define EFI_PAGE_SHIFT          12
 
-/*
- * For current x86 implementations of EFI, there is
- * additional padding in the mem descriptors.  This is not
- * the case in ia64.  Need to have this fixed in the f/w.
- */
 typedef struct {
         u32 type;
         u32 pad;
@@ -103,9 +98,6 @@ typedef struct {
         u64 virt_addr;
         u64 num_pages;
         u64 attribute;
-#if defined (__i386__)
-        u64 pad1;
-#endif
 } efi_memory_desc_t;
 
 typedef int (*efi_freemem_callback_t) (unsigned long start, unsigned long end, void *arg);
@@ -240,10 +232,12 @@ typedef struct {
 } efi_system_table_t;
 
 struct efi_memory_map {
-        efi_memory_desc_t *phys_map;
-        efi_memory_desc_t *map;
+        void *phys_map;
+        void *map;
+        void *map_end;
         int nr_map;
         unsigned long desc_version;
+        unsigned long desc_size;
 };
 
 /*
@@ -315,7 +309,7 @@ extern struct efi_memory_map memmap;
  */
 static inline int efi_range_is_wc(unsigned long start, unsigned long len)
 {
-        int i;
+        unsigned long i;
 
         for (i = 0; i < len; i += (1UL << EFI_PAGE_SHIFT)) {
                 unsigned long paddr = __pa(start + i);
diff --git a/include/linux/elevator.h b/include/linux/elevator.h
index ee54f81faad5..ea6bbc2d7407 100644
--- a/include/linux/elevator.h
+++ b/include/linux/elevator.h
@@ -16,9 +16,9 @@ typedef void (elevator_remove_req_fn) (request_queue_t *, struct request *);
 typedef void (elevator_requeue_req_fn) (request_queue_t *, struct request *);
 typedef struct request *(elevator_request_list_fn) (request_queue_t *, struct request *);
 typedef void (elevator_completed_req_fn) (request_queue_t *, struct request *);
-typedef int (elevator_may_queue_fn) (request_queue_t *, int);
+typedef int (elevator_may_queue_fn) (request_queue_t *, int, struct bio *);
 
-typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, int);
+typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, struct bio *, int);
 typedef void (elevator_put_req_fn) (request_queue_t *, struct request *);
 typedef void (elevator_deactivate_req_fn) (request_queue_t *, struct request *);
 
@@ -96,9 +96,9 @@ extern struct request *elv_former_request(request_queue_t *, struct request *);
 extern struct request *elv_latter_request(request_queue_t *, struct request *);
 extern int elv_register_queue(request_queue_t *q);
 extern void elv_unregister_queue(request_queue_t *q);
-extern int elv_may_queue(request_queue_t *, int);
+extern int elv_may_queue(request_queue_t *, int, struct bio *);
 extern void elv_completed_request(request_queue_t *, struct request *);
-extern int elv_set_request(request_queue_t *, struct request *, int);
+extern int elv_set_request(request_queue_t *, struct request *, struct bio *, int);
 extern void elv_put_request(request_queue_t *, struct request *);
 
 /*
diff --git a/include/linux/elf.h b/include/linux/elf.h
index f5b3ba5a317d..ff955dbf510d 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -2,6 +2,7 @@
 #define _LINUX_ELF_H
 
 #include <linux/types.h>
+#include <linux/auxvec.h>
 #include <asm/elf.h>
 
 #ifndef elf_read_implies_exec
@@ -158,29 +159,6 @@ typedef __s64	Elf64_Sxword;
 #define ELF64_ST_BIND(x)        ELF_ST_BIND(x)
 #define ELF64_ST_TYPE(x)        ELF_ST_TYPE(x)
 
-/* Symbolic values for the entries in the auxiliary table
-   put on the initial stack */
-#define AT_NULL   0     /* end of vector */
-#define AT_IGNORE 1     /* entry should be ignored */
-#define AT_EXECFD 2     /* file descriptor of program */
-#define AT_PHDR   3     /* program headers for program */
-#define AT_PHENT  4     /* size of program header entry */
-#define AT_PHNUM  5     /* number of program headers */
-#define AT_PAGESZ 6     /* system page size */
-#define AT_BASE   7     /* base address of interpreter */
-#define AT_FLAGS  8     /* flags */
-#define AT_ENTRY  9     /* entry point of program */
-#define AT_NOTELF 10    /* program is not ELF */
-#define AT_UID    11    /* real uid */
-#define AT_EUID   12    /* effective uid */
-#define AT_GID    13    /* real gid */
-#define AT_EGID   14    /* effective gid */
-#define AT_PLATFORM 15  /* string identifying CPU for optimizations */
-#define AT_HWCAP  16    /* arch dependent hints at CPU capabilities */
-#define AT_CLKTCK 17    /* frequency at which times() increments */
-
-#define AT_SECURE 23   /* secure mode boolean */
-
 typedef struct dynamic{
   Elf32_Sword d_tag;
   union{
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index a1478258d002..4522c7186bf3 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -25,6 +25,7 @@
 #define _LINUX_ETHERDEVICE_H
 
 #include <linux/if_ether.h>
+#include <linux/netdevice.h>
 #include <linux/random.h>
 
 #ifdef __KERNEL__
@@ -32,7 +33,7 @@ extern int		eth_header(struct sk_buff *skb, struct net_device *dev,
                                    unsigned short type, void *daddr,
                                    void *saddr, unsigned len);
 extern int              eth_rebuild_header(struct sk_buff *skb);
-extern unsigned short   eth_type_trans(struct sk_buff *skb, struct net_device *dev);
+extern __be16           eth_type_trans(struct sk_buff *skb, struct net_device *dev);
 extern void             eth_header_cache_update(struct hh_cache *hh, struct net_device *dev,
                                                 unsigned char * haddr);
 extern int              eth_header_cache(struct neighbour *neigh,
@@ -65,7 +66,13 @@ static inline int is_zero_ether_addr(const u8 *addr)
  */
 static inline int is_multicast_ether_addr(const u8 *addr)
 {
-        return addr[0] & 0x01;
+        return ((addr[0] != 0xff) && (0x01 & addr[0]));
+}
+
+static inline int is_broadcast_ether_addr(const u8 *addr)
+{
+        return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&  
+                (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
 }
 
 /**
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index a0ab26aab450..ed1440ea4c91 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -250,6 +250,12 @@ struct ethtool_stats {
         u64     data[0];
 };
 
+struct ethtool_perm_addr {
+        u32     cmd;            /* ETHTOOL_GPERMADDR */
+        u32     size;
+        u8      data[0];
+};
+
 struct net_device;
 
 /* Some generic methods drivers may use in their ethtool_ops */
@@ -261,6 +267,8 @@ u32 ethtool_op_get_sg(struct net_device *dev);
 int ethtool_op_set_sg(struct net_device *dev, u32 data);
 u32 ethtool_op_get_tso(struct net_device *dev);
 int ethtool_op_set_tso(struct net_device *dev, u32 data);
+int ethtool_op_get_perm_addr(struct net_device *dev, 
+                             struct ethtool_perm_addr *addr, u8 *data);
 
 /**
  * &ethtool_ops - Alter and report network device settings
@@ -294,7 +302,8 @@ int ethtool_op_set_tso(struct net_device *dev, u32 data);
  * get_strings: Return a set of strings that describe the requested objects 
  * phys_id: Identify the device
  * get_stats: Return statistics about the device
- *
+ * get_perm_addr: Gets the permanent hardware address
+ * 
  * Description:
  *
  * get_settings:
@@ -352,6 +361,7 @@ struct ethtool_ops {
         int     (*phys_id)(struct net_device *, u32);
         int     (*get_stats_count)(struct net_device *);
         void    (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);
+        int     (*get_perm_addr)(struct net_device *, struct ethtool_perm_addr *, u8 *);
         int     (*begin)(struct net_device *);
         void    (*complete)(struct net_device *);
 };
@@ -389,6 +399,7 @@ struct ethtool_ops {
 #define ETHTOOL_GSTATS          0x0000001d /* get NIC-specific statistics */
 #define ETHTOOL_GTSO            0x0000001e /* Get TSO enable (ethtool_value) */
 #define ETHTOOL_STSO            0x0000001f /* Set TSO enable (ethtool_value) */
+#define ETHTOOL_GPERMADDR       0x00000020 /* Get permanent hardware address */
 
 /* compatibility with older code */
 #define SPARC_ETH_GSET          ETHTOOL_GSET
@@ -408,6 +419,8 @@ struct ethtool_ops {
 #define SUPPORTED_FIBRE                 (1 << 10)
 #define SUPPORTED_BNC                   (1 << 11)
 #define SUPPORTED_10000baseT_Full       (1 << 12)
+#define SUPPORTED_Pause                 (1 << 13)
+#define SUPPORTED_Asym_Pause            (1 << 14)
 
 /* Indicates what features are advertised by the interface. */
 #define ADVERTISED_10baseT_Half         (1 << 0)
@@ -423,6 +436,8 @@ struct ethtool_ops {
 #define ADVERTISED_FIBRE                (1 << 10)
 #define ADVERTISED_BNC                  (1 << 11)
 #define ADVERTISED_10000baseT_Full      (1 << 12)
+#define ADVERTISED_Pause                (1 << 13)
+#define ADVERTISED_Asym_Pause           (1 << 14)
 
 /* The following are all involved in forcing a particular link
  * mode for the device for setting things.  When getting the
diff --git a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
index fab43527e597..f7bd1c7ebefb 100644
--- a/include/linux/ext2_fs.h
+++ b/include/linux/ext2_fs.h
@@ -300,18 +300,22 @@ struct ext2_inode {
 /*
  * Mount flags
  */
-#define EXT2_MOUNT_CHECK                0x0001  /* Do mount-time checks */
-#define EXT2_MOUNT_OLDALLOC             0x0002  /* Don't use the new Orlov allocator */
-#define EXT2_MOUNT_GRPID                0x0004  /* Create files with directory's group */
-#define EXT2_MOUNT_DEBUG                0x0008  /* Some debugging messages */
-#define EXT2_MOUNT_ERRORS_CONT          0x0010  /* Continue on errors */
-#define EXT2_MOUNT_ERRORS_RO            0x0020  /* Remount fs ro on errors */
-#define EXT2_MOUNT_ERRORS_PANIC         0x0040  /* Panic on errors */
-#define EXT2_MOUNT_MINIX_DF             0x0080  /* Mimics the Minix statfs */
-#define EXT2_MOUNT_NOBH                 0x0100  /* No buffer_heads */
-#define EXT2_MOUNT_NO_UID32             0x0200  /* Disable 32-bit UIDs */
-#define EXT2_MOUNT_XATTR_USER           0x4000  /* Extended user attributes */
-#define EXT2_MOUNT_POSIX_ACL            0x8000  /* POSIX Access Control Lists */
+#define EXT2_MOUNT_CHECK                0x000001  /* Do mount-time checks */
+#define EXT2_MOUNT_OLDALLOC             0x000002  /* Don't use the new Orlov allocator */
+#define EXT2_MOUNT_GRPID                0x000004  /* Create files with directory's group */
+#define EXT2_MOUNT_DEBUG                0x000008  /* Some debugging messages */
+#define EXT2_MOUNT_ERRORS_CONT          0x000010  /* Continue on errors */
+#define EXT2_MOUNT_ERRORS_RO            0x000020  /* Remount fs ro on errors */
+#define EXT2_MOUNT_ERRORS_PANIC         0x000040  /* Panic on errors */
+#define EXT2_MOUNT_MINIX_DF             0x000080  /* Mimics the Minix statfs */
+#define EXT2_MOUNT_NOBH                 0x000100  /* No buffer_heads */
+#define EXT2_MOUNT_NO_UID32             0x000200  /* Disable 32-bit UIDs */
+#define EXT2_MOUNT_XATTR_USER           0x004000  /* Extended user attributes */
+#define EXT2_MOUNT_POSIX_ACL            0x008000  /* POSIX Access Control Lists */
+#define EXT2_MOUNT_XIP                  0x010000  /* Execute in place */
+#define EXT2_MOUNT_USRQUOTA             0x020000 /* user quota */
+#define EXT2_MOUNT_GRPQUOTA             0x040000 /* group quota */
+
 
 #define clear_opt(o, opt)               o &= ~EXT2_MOUNT_##opt
 #define set_opt(o, opt)                 o |= EXT2_MOUNT_##opt
diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h
index 74ad31781e3e..c0272d73ab20 100644
--- a/include/linux/ext3_fs.h
+++ b/include/linux/ext3_fs.h
@@ -239,6 +239,20 @@ struct ext3_new_group_data {
 #define EXT3_IOC_SETRSVSZ               _IOW('f', 6, long)
 
 /*
+ *  Mount options
+ */
+struct ext3_mount_options {
+        unsigned long s_mount_opt;
+        uid_t s_resuid;
+        gid_t s_resgid;
+        unsigned long s_commit_interval;
+#ifdef CONFIG_QUOTA
+        int s_jquota_fmt;
+        char *s_qf_names[MAXQUOTAS];
+#endif
+};
+
+/*
  * Structure of an inode on the disk
  */
 struct ext3_inode {
@@ -358,6 +372,9 @@ struct ext3_inode {
 #define EXT3_MOUNT_RESERVATION          0x10000 /* Preallocation */
 #define EXT3_MOUNT_BARRIER              0x20000 /* Use block barriers */
 #define EXT3_MOUNT_NOBH                 0x40000 /* No bufferheads */
+#define EXT3_MOUNT_QUOTA                0x80000 /* Some quota option set */
+#define EXT3_MOUNT_USRQUOTA             0x100000 /* "old" user quota */
+#define EXT3_MOUNT_GRPQUOTA             0x200000 /* "old" group quota */
 
 /* Compatibility, for having both ext2_fs.h and ext3_fs.h included at once */
 #ifndef _LINUX_EXT2_FS_H
diff --git a/include/linux/ext3_jbd.h b/include/linux/ext3_jbd.h
index e8292af9033b..c8307c02dd07 100644
--- a/include/linux/ext3_jbd.h
+++ b/include/linux/ext3_jbd.h
@@ -42,15 +42,15 @@
  * superblock only gets updated once, of course, so don't bother
  * counting that again for the quota updates. */
 
-#define EXT3_DATA_TRANS_BLOCKS          (EXT3_SINGLEDATA_TRANS_BLOCKS + \
+#define EXT3_DATA_TRANS_BLOCKS(sb)      (EXT3_SINGLEDATA_TRANS_BLOCKS + \
                                          EXT3_XATTR_TRANS_BLOCKS - 2 + \
-                                         2*EXT3_QUOTA_TRANS_BLOCKS)
+                                         2*EXT3_QUOTA_TRANS_BLOCKS(sb))
 
 /* Delete operations potentially hit one directory's namespace plus an
  * entire inode, plus arbitrary amounts of bitmap/indirection data.  Be
  * generous.  We can grow the delete transaction later if necessary. */
 
-#define EXT3_DELETE_TRANS_BLOCKS        (2 * EXT3_DATA_TRANS_BLOCKS + 64)
+#define EXT3_DELETE_TRANS_BLOCKS(sb)    (2 * EXT3_DATA_TRANS_BLOCKS(sb) + 64)
 
 /* Define an arbitrary limit for the amount of data we will anticipate
  * writing to any given transaction.  For unbounded transactions such as
@@ -74,14 +74,17 @@
 #ifdef CONFIG_QUOTA
 /* Amount of blocks needed for quota update - we know that the structure was
  * allocated so we need to update only inode+data */
-#define EXT3_QUOTA_TRANS_BLOCKS 2
+#define EXT3_QUOTA_TRANS_BLOCKS(sb) (test_opt(sb, QUOTA) ? 2 : 0)
 /* Amount of blocks needed for quota insert/delete - we do some block writes
  * but inode, sb and group updates are done only once */
-#define EXT3_QUOTA_INIT_BLOCKS (DQUOT_MAX_WRITES*\
-                                (EXT3_SINGLEDATA_TRANS_BLOCKS-3)+3)
+#define EXT3_QUOTA_INIT_BLOCKS(sb) (test_opt(sb, QUOTA) ? (DQUOT_INIT_ALLOC*\
+                (EXT3_SINGLEDATA_TRANS_BLOCKS-3)+3+DQUOT_INIT_REWRITE) : 0)
+#define EXT3_QUOTA_DEL_BLOCKS(sb) (test_opt(sb, QUOTA) ? (DQUOT_DEL_ALLOC*\
+                (EXT3_SINGLEDATA_TRANS_BLOCKS-3)+3+DQUOT_DEL_REWRITE) : 0)
 #else
-#define EXT3_QUOTA_TRANS_BLOCKS 0
-#define EXT3_QUOTA_INIT_BLOCKS 0
+#define EXT3_QUOTA_TRANS_BLOCKS(sb) 0
+#define EXT3_QUOTA_INIT_BLOCKS(sb) 0
+#define EXT3_QUOTA_DEL_BLOCKS(sb) 0
 #endif
 
 int
diff --git a/include/linux/fadvise.h b/include/linux/fadvise.h
index 6fc656dfb93d..e8e747139b9a 100644
--- a/include/linux/fadvise.h
+++ b/include/linux/fadvise.h
@@ -5,7 +5,17 @@
 #define POSIX_FADV_RANDOM       1 /* Expect random page references.  */
 #define POSIX_FADV_SEQUENTIAL   2 /* Expect sequential page references.  */
 #define POSIX_FADV_WILLNEED     3 /* Will need these pages.  */
+
+/*
+ * The advise values for POSIX_FADV_DONTNEED and POSIX_ADV_NOREUSE
+ * for s390-64 differ from the values for the rest of the world.
+ */
+#if defined(__s390x__)
+#define POSIX_FADV_DONTNEED     6 /* Don't need these pages.  */
+#define POSIX_FADV_NOREUSE      7 /* Data will be accessed once.  */
+#else
 #define POSIX_FADV_DONTNEED     4 /* Don't need these pages.  */
 #define POSIX_FADV_NOREUSE      5 /* Data will be accessed once.  */
+#endif
 
 #endif  /* FADVISE_H_INCLUDED */
diff --git a/include/linux/fb.h b/include/linux/fb.h
index b468bf496547..bc24beeed971 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -524,11 +524,11 @@ struct fb_pixmap {
         u32 offset;             /* current offset to buffer             */
         u32 buf_align;          /* byte alignment of each bitmap        */
         u32 scan_align;         /* alignment per scanline               */
-        u32 access_align;       /* alignment per read/write             */
+        u32 access_align;       /* alignment per read/write (bits)      */
         u32 flags;              /* see FB_PIXMAP_*                      */
         /* access methods */
-        void (*outbuf)(struct fb_info *info, u8 *addr, u8 *src, unsigned int size);
-        u8   (*inbuf) (struct fb_info *info, u8 *addr);
+        void (*writeio)(struct fb_info *info, void __iomem *dst, void *src, unsigned int size);
+        void (*readio) (struct fb_info *info, void *dst, void __iomem *src, unsigned int size);
 };
 
 
@@ -816,18 +816,9 @@ extern int unregister_framebuffer(struct fb_info *fb_info);
 extern int fb_prepare_logo(struct fb_info *fb_info);
 extern int fb_show_logo(struct fb_info *fb_info);
 extern char* fb_get_buffer_offset(struct fb_info *info, struct fb_pixmap *buf, u32 size);
-extern void fb_iomove_buf_unaligned(struct fb_info *info, struct fb_pixmap *buf,
-                                u8 *dst, u32 d_pitch, u8 *src, u32 idx,
+extern void fb_pad_unaligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 idx,
                                 u32 height, u32 shift_high, u32 shift_low, u32 mod);
-extern void fb_iomove_buf_aligned(struct fb_info *info, struct fb_pixmap *buf,
-                                u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch,
-                                u32 height);
-extern void fb_sysmove_buf_unaligned(struct fb_info *info, struct fb_pixmap *buf,
-                                u8 *dst, u32 d_pitch, u8 *src, u32 idx,
-                                u32 height, u32 shift_high, u32 shift_low, u32 mod);
-extern void fb_sysmove_buf_aligned(struct fb_info *info, struct fb_pixmap *buf,
-                                u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch,
-                                u32 height);
+extern void fb_pad_aligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch, u32 height);
 extern void fb_set_suspend(struct fb_info *info, int state);
 extern int fb_get_color_depth(struct fb_var_screeninfo *var);
 extern int fb_get_options(char *name, char **option);
diff --git a/include/linux/fcntl.h b/include/linux/fcntl.h
index 704fb76b6334..8a7c82151de9 100644
--- a/include/linux/fcntl.h
+++ b/include/linux/fcntl.h
@@ -25,6 +25,10 @@
 
 #ifdef __KERNEL__
 
+#ifndef force_o_largefile
+#define force_o_largefile() (BITS_PER_LONG != 32)
+#endif
+
 #if BITS_PER_LONG == 32
 #define IS_GETLK32(cmd)         ((cmd) == F_GETLK)
 #define IS_SETLK32(cmd)         ((cmd) == F_SETLK)
diff --git a/include/linux/fddidevice.h b/include/linux/fddidevice.h
index 002f6367697d..e61e42dfd317 100644
--- a/include/linux/fddidevice.h
+++ b/include/linux/fddidevice.h
@@ -25,7 +25,7 @@
 #include <linux/if_fddi.h>
 
 #ifdef __KERNEL__
-extern unsigned short   fddi_type_trans(struct sk_buff *skb,
+extern __be16   fddi_type_trans(struct sk_buff *skb,
                                 struct net_device *dev);
 extern struct net_device *alloc_fddidev(int sizeof_priv);
 #endif
diff --git a/include/linux/firmware.h b/include/linux/firmware.h
index 886255b69bb9..2063c0839d4f 100644
--- a/include/linux/firmware.h
+++ b/include/linux/firmware.h
@@ -3,6 +3,9 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #define FIRMWARE_NAME_MAX 30 
+#define FW_ACTION_NOHOTPLUG 0
+#define FW_ACTION_HOTPLUG 1
+
 struct firmware {
         size_t size;
         u8 *data;
@@ -11,7 +14,7 @@ struct device;
 int request_firmware(const struct firmware **fw, const char *name,
                      struct device *device);
 int request_firmware_nowait(
-        struct module *module,
+        struct module *module, int hotplug,
         const char *name, struct device *device, void *context,
         void (*cont)(const struct firmware *fw, void *context));
 
diff --git a/include/linux/font.h b/include/linux/font.h
index fc2d690c9d5f..8fc80a7d78ac 100644
--- a/include/linux/font.h
+++ b/include/linux/font.h
@@ -25,19 +25,23 @@ struct font_desc {
 #define VGA8x16_IDX     1
 #define PEARL8x8_IDX    2
 #define VGA6x11_IDX     3
-#define SUN8x16_IDX     4
-#define SUN12x22_IDX    5
-#define ACORN8x8_IDX    6
-#define MINI4x6_IDX     7
+#define FONT7x14_IDX    4
+#define FONT10x18_IDX   5
+#define SUN8x16_IDX     6
+#define SUN12x22_IDX    7
+#define ACORN8x8_IDX    8
+#define MINI4x6_IDX     9
 
 extern struct font_desc font_vga_8x8,
-                                font_vga_8x16,
-                                font_pearl_8x8,
-                                font_vga_6x11,
-                                font_sun_8x16,
-                                font_sun_12x22,
-                                font_acorn_8x8,
-                                font_mini_4x6;
+                        font_vga_8x16,
+                        font_pearl_8x8,
+                        font_vga_6x11,
+                        font_7x14,
+                        font_10x18,
+                        font_sun_8x16,
+                        font_sun_12x22,
+                        font_acorn_8x8,
+                        font_mini_4x6;
 
 /* Find a font with a specific name */
 
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 0180102dace1..fd93ab7da905 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -69,6 +69,7 @@ extern int dir_notify_enable;
 #define READ 0
 #define WRITE 1
 #define READA 2         /* read-ahead  - don't block if no resources */
+#define SWRITE 3        /* for ll_rw_block() - wait for buffer lock */
 #define SPECIAL 4       /* For non-blockdevice requests in request queue */
 #define READ_SYNC       (READ | (1 << BIO_RW_SYNC))
 #define WRITE_SYNC      (WRITE | (1 << BIO_RW_SYNC))
@@ -213,6 +214,7 @@ extern int dir_notify_enable;
 #include <linux/radix-tree.h>
 #include <linux/prio_tree.h>
 #include <linux/init.h>
+#include <linux/sched.h>
 
 #include <asm/atomic.h>
 #include <asm/semaphore.h>
@@ -220,6 +222,7 @@ extern int dir_notify_enable;
 
 struct iovec;
 struct nameidata;
+struct kiocb;
 struct pipe_inode_info;
 struct poll_table_struct;
 struct kstatfs;
@@ -240,7 +243,7 @@ typedef int (get_block_t)(struct inode *inode, sector_t iblock,
 typedef int (get_blocks_t)(struct inode *inode, sector_t iblock,
                         unsigned long max_blocks,
                         struct buffer_head *bh_result, int create);
-typedef void (dio_iodone_t)(struct inode *inode, loff_t offset,
+typedef void (dio_iodone_t)(struct kiocb *iocb, loff_t offset,
                         ssize_t bytes, void *private);
 
 /*
@@ -279,19 +282,9 @@ struct iattr {
         struct timespec ia_atime;
         struct timespec ia_mtime;
         struct timespec ia_ctime;
-        unsigned int    ia_attr_flags;
 };
 
 /*
- * This is the inode attributes flag definitions
- */
-#define ATTR_FLAG_SYNCRONOUS    1       /* Syncronous write */
-#define ATTR_FLAG_NOATIME       2       /* Don't update atime */
-#define ATTR_FLAG_APPEND        4       /* Append-only file */
-#define ATTR_FLAG_IMMUTABLE     8       /* Immutable file */
-#define ATTR_FLAG_NODIRATIME    16      /* Don't update atime for directory */
-
-/*
  * Includes for diskquotas.
  */
 #include <linux/quota.h>
@@ -302,7 +295,6 @@ struct iattr {
 struct page;
 struct address_space;
 struct writeback_control;
-struct kiocb;
 
 struct address_space_operations {
         int (*writepage)(struct page *page, struct writeback_control *wbc);
@@ -330,6 +322,8 @@ struct address_space_operations {
         int (*releasepage) (struct page *, int);
         ssize_t (*direct_IO)(int, struct kiocb *, const struct iovec *iov,
                         loff_t offset, unsigned long nr_segs);
+        struct page* (*get_xip_page)(struct address_space *, sector_t,
+                        int);
 };
 
 struct backing_dev_info;
@@ -471,6 +465,11 @@ struct inode {
         struct dnotify_struct   *i_dnotify; /* for directory notifications */
 #endif
 
+#ifdef CONFIG_INOTIFY
+        struct list_head        inotify_watches; /* watches on this inode */
+        struct semaphore        inotify_sem;    /* protects the watches list */
+#endif
+
         unsigned long           i_state;
         unsigned long           dirtied_when;   /* jiffies of first dirtying */
 
@@ -581,13 +580,11 @@ struct file {
         atomic_t                f_count;
         unsigned int            f_flags;
         mode_t                  f_mode;
-        int                     f_error;
         loff_t                  f_pos;
         struct fown_struct      f_owner;
         unsigned int            f_uid, f_gid;
         struct file_ra_state    f_ra;
 
-        size_t                  f_maxcount;
         unsigned long           f_version;
         void                    *f_security;
 
@@ -674,6 +671,7 @@ struct file_lock {
         struct lock_manager_operations *fl_lmops;       /* Callbacks for lockmanagers */
         union {
                 struct nfs_lock_info    nfs_fl;
+                struct nfs4_lock_info   nfs4_fl;
         } fl_u;
 };
 
@@ -689,11 +687,13 @@ extern struct list_head file_lock_list;
 #include <linux/fcntl.h>
 
 extern int fcntl_getlk(struct file *, struct flock __user *);
-extern int fcntl_setlk(struct file *, unsigned int, struct flock __user *);
+extern int fcntl_setlk(unsigned int, struct file *, unsigned int,
+                        struct flock __user *);
 
 #if BITS_PER_LONG == 32
 extern int fcntl_getlk64(struct file *, struct flock64 __user *);
-extern int fcntl_setlk64(struct file *, unsigned int, struct flock64 __user *);
+extern int fcntl_setlk64(unsigned int, struct file *, unsigned int,
+                        struct flock64 __user *);
 #endif
 
 extern void send_sigio(struct fown_struct *fown, int fd, int band);
@@ -820,16 +820,34 @@ enum {
 #define vfs_check_frozen(sb, level) \
         wait_event((sb)->s_wait_unfrozen, ((sb)->s_frozen < (level)))
 
+static inline void get_fs_excl(void)
+{
+        atomic_inc(&current->fs_excl);
+}
+
+static inline void put_fs_excl(void)
+{
+        atomic_dec(&current->fs_excl);
+}
+
+static inline int has_fs_excl(void)
+{
+        return atomic_read(&current->fs_excl);
+}
+
+
 /*
  * Superblock locking.
  */
 static inline void lock_super(struct super_block * sb)
 {
+        get_fs_excl();
         down(&sb->s_lock);
 }
 
 static inline void unlock_super(struct super_block * sb)
 {
+        put_fs_excl();
         up(&sb->s_lock);
 }
 
@@ -883,7 +901,9 @@ struct block_device_operations {
         int (*open) (struct inode *, struct file *);
         int (*release) (struct inode *, struct file *);
         int (*ioctl) (struct inode *, struct file *, unsigned, unsigned long);
+        long (*unlocked_ioctl) (struct file *, unsigned, unsigned long);
         long (*compat_ioctl) (struct file *, unsigned, unsigned long);
+        int (*direct_access) (struct block_device *, sector_t, unsigned long *);
         int (*media_changed) (struct gendisk *);
         int (*revalidate_disk) (struct gendisk *);
         struct module *owner;
@@ -963,8 +983,8 @@ struct inode_operations {
         int (*rename) (struct inode *, struct dentry *,
                         struct inode *, struct dentry *);
         int (*readlink) (struct dentry *, char __user *,int);
-        int (*follow_link) (struct dentry *, struct nameidata *);
-        void (*put_link) (struct dentry *, struct nameidata *);
+        void * (*follow_link) (struct dentry *, struct nameidata *);
+        void (*put_link) (struct dentry *, struct nameidata *, void *);
         void (*truncate) (struct inode *);
         int (*permission) (struct inode *, int, struct nameidata *);
         int (*setattr) (struct dentry *, struct iattr *);
@@ -1024,6 +1044,7 @@ struct super_operations {
 #define I_FREEING               16
 #define I_CLEAR                 32
 #define I_NEW                   64
+#define I_WILL_FREE             128
 
 #define I_DIRTY (I_DIRTY_SYNC | I_DIRTY_DATASYNC | I_DIRTY_PAGES)
 
@@ -1260,6 +1281,7 @@ static inline int break_lease(struct inode *inode, unsigned int mode)
 /* fs/open.c */
 
 extern int do_truncate(struct dentry *, loff_t start);
+extern long do_sys_open(const char __user *filename, int flags, int mode);
 extern struct file *filp_open(const char *, int, int);
 extern struct file * dentry_open(struct dentry *, struct vfsmount *, int);
 extern int filp_close(struct file *, fl_owner_t id);
@@ -1369,7 +1391,6 @@ extern void emergency_remount(void);
 extern int do_remount_sb(struct super_block *sb, int flags,
                          void *data, int force);
 extern sector_t bmap(struct inode *, sector_t);
-extern int setattr_mask(unsigned int);
 extern int notify_change(struct dentry *, struct iattr *);
 extern int permission(struct inode *, int, struct nameidata *);
 extern int generic_permission(struct inode *, int,
@@ -1411,7 +1432,11 @@ extern struct inode * igrab(struct inode *);
 extern ino_t iunique(struct super_block *, ino_t);
 extern int inode_needs_sync(struct inode *inode);
 extern void generic_delete_inode(struct inode *inode);
+extern void generic_drop_inode(struct inode *inode);
 
+extern struct inode *ilookup5_nowait(struct super_block *sb,
+                unsigned long hashval, int (*test)(struct inode *, void *),
+                void *data);
 extern struct inode *ilookup5(struct super_block *sb, unsigned long hashval,
                 int (*test)(struct inode *, void *), void *data);
 extern struct inode *ilookup(struct super_block *sb, unsigned long ino);
@@ -1494,6 +1519,23 @@ extern loff_t remote_llseek(struct file *file, loff_t offset, int origin);
 extern int generic_file_open(struct inode * inode, struct file * filp);
 extern int nonseekable_open(struct inode * inode, struct file * filp);
 
+#ifdef CONFIG_FS_XIP
+extern ssize_t xip_file_read(struct file *filp, char __user *buf, size_t len,
+                             loff_t *ppos);
+extern ssize_t xip_file_sendfile(struct file *in_file, loff_t *ppos,
+                                 size_t count, read_actor_t actor,
+                                 void *target);
+extern int xip_file_mmap(struct file * file, struct vm_area_struct * vma);
+extern ssize_t xip_file_write(struct file *filp, const char __user *buf,
+                              size_t len, loff_t *ppos);
+extern int xip_truncate_page(struct address_space *mapping, loff_t from);
+#else
+static inline int xip_truncate_page(struct address_space *mapping, loff_t from)
+{
+        return 0;
+}
+#endif
+
 static inline void do_generic_file_read(struct file * filp, loff_t *ppos,
                                         read_descriptor_t * desc,
                                         read_actor_t actor)
@@ -1551,8 +1593,8 @@ extern struct file_operations generic_ro_fops;
 extern int vfs_readlink(struct dentry *, char __user *, int, const char *);
 extern int vfs_follow_link(struct nameidata *, const char *);
 extern int page_readlink(struct dentry *, char __user *, int);
-extern int page_follow_link_light(struct dentry *, struct nameidata *);
-extern void page_put_link(struct dentry *, struct nameidata *);
+extern void *page_follow_link_light(struct dentry *, struct nameidata *);
+extern void page_put_link(struct dentry *, struct nameidata *, void *);
 extern int page_symlink(struct inode *inode, const char *symname, int len);
 extern struct inode_operations page_symlink_inode_operations;
 extern int generic_readlink(struct dentry *, char __user *, int);
@@ -1657,6 +1699,52 @@ static inline void simple_transaction_set(struct file *file, size_t n)
         ar->size = n;
 }
 
+/*
+ * simple attribute files
+ *
+ * These attributes behave similar to those in sysfs:
+ *
+ * Writing to an attribute immediately sets a value, an open file can be
+ * written to multiple times.
+ *
+ * Reading from an attribute creates a buffer from the value that might get
+ * read with multiple read calls. When the attribute has been read
+ * completely, no further read calls are possible until the file is opened
+ * again.
+ *
+ * All attributes contain a text representation of a numeric value
+ * that are accessed with the get() and set() functions.
+ */
+#define DEFINE_SIMPLE_ATTRIBUTE(__fops, __get, __set, __fmt)            \
+static int __fops ## _open(struct inode *inode, struct file *file)      \
+{                                                                       \
+        __simple_attr_check_format(__fmt, 0ull);                        \
+        return simple_attr_open(inode, file, __get, __set, __fmt);      \
+}                                                                       \
+static struct file_operations __fops = {                                \
+        .owner   = THIS_MODULE,                                         \
+        .open    = __fops ## _open,                                     \
+        .release = simple_attr_close,                                   \
+        .read    = simple_attr_read,                                    \
+        .write   = simple_attr_write,                                   \
+};
+
+static inline void __attribute__((format(printf, 1, 2)))
+__simple_attr_check_format(const char *fmt, ...)
+{
+        /* don't do anything, just let the compiler check the arguments; */
+}
+
+int simple_attr_open(struct inode *inode, struct file *file,
+                     u64 (*get)(void *), void (*set)(void *, u64),
+                     const char *fmt);
+int simple_attr_close(struct inode *inode, struct file *file);
+ssize_t simple_attr_read(struct file *file, char __user *buf,
+                         size_t len, loff_t *ppos);
+ssize_t simple_attr_write(struct file *file, const char __user *buf,
+                          size_t len, loff_t *ppos);
+
+
 #ifdef CONFIG_SECURITY
 static inline char *alloc_secdata(void)
 {
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index faaff4c64559..70f54af87b9f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -51,6 +51,7 @@ struct gianfar_platform_data {
 
         /* board specific information */
         u32 board_flags;
+        u32 phy_flags;
         u32 phyid;
         u32 interruptPHY;
         u8 mac_addr[6];
@@ -61,9 +62,14 @@ struct gianfar_platform_data {
 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
 #define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
+#define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
+#define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
+#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
+#define FSL_GIANFAR_DEV_HAS_PADDING             0x00000080
 
 /* Flags in gianfar_platform_data */
-#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001      /* if not set use a timer */
+#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001 /* set or use a timer */
+#define FSL_GIANFAR_BRD_IS_REDUCED      0x00000002 /* Set if RGMII, RMII */
 
 struct fsl_i2c_platform_data {
         /* device specific information */
diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h
new file mode 100644
index 000000000000..03b8e7932b83
--- /dev/null
+++ b/include/linux/fsnotify.h
@@ -0,0 +1,251 @@
+#ifndef _LINUX_FS_NOTIFY_H
+#define _LINUX_FS_NOTIFY_H
+
+/*
+ * include/linux/fsnotify.h - generic hooks for filesystem notification, to
+ * reduce in-source duplication from both dnotify and inotify.
+ *
+ * We don't compile any of this away in some complicated menagerie of ifdefs.
+ * Instead, we rely on the code inside to optimize away as needed.
+ *
+ * (C) Copyright 2005 Robert Love
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/dnotify.h>
+#include <linux/inotify.h>
+
+/*
+ * fsnotify_move - file old_name at old_dir was moved to new_name at new_dir
+ */
+static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir,
+                                 const char *old_name, const char *new_name,
+                                 int isdir, struct inode *target, struct inode *source)
+{
+        u32 cookie = inotify_get_cookie();
+
+        if (old_dir == new_dir)
+                inode_dir_notify(old_dir, DN_RENAME);
+        else {
+                inode_dir_notify(old_dir, DN_DELETE);
+                inode_dir_notify(new_dir, DN_CREATE);
+        }
+
+        if (isdir)
+                isdir = IN_ISDIR;
+        inotify_inode_queue_event(old_dir, IN_MOVED_FROM|isdir,cookie,old_name);
+        inotify_inode_queue_event(new_dir, IN_MOVED_TO|isdir, cookie, new_name);
+
+        if (target) {
+                inotify_inode_queue_event(target, IN_DELETE_SELF, 0, NULL);
+                inotify_inode_is_dead(target);
+        }
+
+        if (source) {
+                inotify_inode_queue_event(source, IN_MOVE_SELF, 0, NULL);
+        }
+}
+
+/*
+ * fsnotify_nameremove - a filename was removed from a directory
+ */
+static inline void fsnotify_nameremove(struct dentry *dentry, int isdir)
+{
+        if (isdir)
+                isdir = IN_ISDIR;
+        dnotify_parent(dentry, DN_DELETE);
+        inotify_dentry_parent_queue_event(dentry, IN_DELETE|isdir, 0, dentry->d_name.name);
+}
+
+/*
+ * fsnotify_inoderemove - an inode is going away
+ */
+static inline void fsnotify_inoderemove(struct inode *inode)
+{
+        inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL);
+        inotify_inode_is_dead(inode);
+}
+
+/*
+ * fsnotify_create - 'name' was linked in
+ */
+static inline void fsnotify_create(struct inode *inode, const char *name)
+{
+        inode_dir_notify(inode, DN_CREATE);
+        inotify_inode_queue_event(inode, IN_CREATE, 0, name);
+}
+
+/*
+ * fsnotify_mkdir - directory 'name' was created
+ */
+static inline void fsnotify_mkdir(struct inode *inode, const char *name)
+{
+        inode_dir_notify(inode, DN_CREATE);
+        inotify_inode_queue_event(inode, IN_CREATE | IN_ISDIR, 0, name);
+}
+
+/*
+ * fsnotify_access - file was read
+ */
+static inline void fsnotify_access(struct dentry *dentry)
+{
+        struct inode *inode = dentry->d_inode;
+        u32 mask = IN_ACCESS;
+
+        if (S_ISDIR(inode->i_mode))
+                mask |= IN_ISDIR;
+
+        dnotify_parent(dentry, DN_ACCESS);
+        inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name);
+        inotify_inode_queue_event(inode, mask, 0, NULL);
+}
+
+/*
+ * fsnotify_modify - file was modified
+ */
+static inline void fsnotify_modify(struct dentry *dentry)
+{
+        struct inode *inode = dentry->d_inode;
+        u32 mask = IN_MODIFY;
+
+        if (S_ISDIR(inode->i_mode))
+                mask |= IN_ISDIR;
+
+        dnotify_parent(dentry, DN_MODIFY);
+        inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name);
+        inotify_inode_queue_event(inode, mask, 0, NULL);
+}
+
+/*
+ * fsnotify_open - file was opened
+ */
+static inline void fsnotify_open(struct dentry *dentry)
+{
+        struct inode *inode = dentry->d_inode;
+        u32 mask = IN_OPEN;
+
+        if (S_ISDIR(inode->i_mode))
+                mask |= IN_ISDIR;
+
+        inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name);
+        inotify_inode_queue_event(inode, mask, 0, NULL);        
+}
+
+/*
+ * fsnotify_close - file was closed
+ */
+static inline void fsnotify_close(struct file *file)
+{
+        struct dentry *dentry = file->f_dentry;
+        struct inode *inode = dentry->d_inode;
+        const char *name = dentry->d_name.name;
+        mode_t mode = file->f_mode;
+        u32 mask = (mode & FMODE_WRITE) ? IN_CLOSE_WRITE : IN_CLOSE_NOWRITE;
+
+        if (S_ISDIR(inode->i_mode))
+                mask |= IN_ISDIR;
+
+        inotify_dentry_parent_queue_event(dentry, mask, 0, name);
+        inotify_inode_queue_event(inode, mask, 0, NULL);
+}
+
+/*
+ * fsnotify_xattr - extended attributes were changed
+ */
+static inline void fsnotify_xattr(struct dentry *dentry)
+{
+        struct inode *inode = dentry->d_inode;
+        u32 mask = IN_ATTRIB;
+
+        if (S_ISDIR(inode->i_mode))
+                mask |= IN_ISDIR;
+
+        inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name);
+        inotify_inode_queue_event(inode, mask, 0, NULL);
+}
+
+/*
+ * fsnotify_change - notify_change event.  file was modified and/or metadata
+ * was changed.
+ */
+static inline void fsnotify_change(struct dentry *dentry, unsigned int ia_valid)
+{
+        struct inode *inode = dentry->d_inode;
+        int dn_mask = 0;
+        u32 in_mask = 0;
+
+        if (ia_valid & ATTR_UID) {
+                in_mask |= IN_ATTRIB;
+                dn_mask |= DN_ATTRIB;
+        }
+        if (ia_valid & ATTR_GID) {
+                in_mask |= IN_ATTRIB;
+                dn_mask |= DN_ATTRIB;
+        }
+        if (ia_valid & ATTR_SIZE) {
+                in_mask |= IN_MODIFY;
+                dn_mask |= DN_MODIFY;
+        }
+        /* both times implies a utime(s) call */
+        if ((ia_valid & (ATTR_ATIME | ATTR_MTIME)) == (ATTR_ATIME | ATTR_MTIME))
+        {
+                in_mask |= IN_ATTRIB;
+                dn_mask |= DN_ATTRIB;
+        } else if (ia_valid & ATTR_ATIME) {
+                in_mask |= IN_ACCESS;
+                dn_mask |= DN_ACCESS;
+        } else if (ia_valid & ATTR_MTIME) {
+                in_mask |= IN_MODIFY;
+                dn_mask |= DN_MODIFY;
+        }
+        if (ia_valid & ATTR_MODE) {
+                in_mask |= IN_ATTRIB;
+                dn_mask |= DN_ATTRIB;
+        }
+
+        if (dn_mask)
+                dnotify_parent(dentry, dn_mask);
+        if (in_mask) {
+                if (S_ISDIR(inode->i_mode))
+                        in_mask |= IN_ISDIR;
+                inotify_inode_queue_event(inode, in_mask, 0, NULL);
+                inotify_dentry_parent_queue_event(dentry, in_mask, 0,
+                                                  dentry->d_name.name);
+        }
+}
+
+#ifdef CONFIG_INOTIFY   /* inotify helpers */
+
+/*
+ * fsnotify_oldname_init - save off the old filename before we change it
+ */
+static inline const char *fsnotify_oldname_init(const char *name)
+{
+        return kstrdup(name, GFP_KERNEL);
+}
+
+/*
+ * fsnotify_oldname_free - free the name we got from fsnotify_oldname_init
+ */
+static inline void fsnotify_oldname_free(const char *old_name)
+{
+        kfree(old_name);
+}
+
+#else   /* CONFIG_INOTIFY */
+
+static inline const char *fsnotify_oldname_init(const char *name)
+{
+        return NULL;
+}
+
+static inline void fsnotify_oldname_free(const char *old_name)
+{
+}
+
+#endif  /* ! CONFIG_INOTIFY */
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _LINUX_FS_NOTIFY_H */
diff --git a/include/linux/ftape.h b/include/linux/ftape.h
index c6b38d5b9186..72faeec9f6e1 100644
--- a/include/linux/ftape.h
+++ b/include/linux/ftape.h
@@ -165,7 +165,7 @@ typedef union {
 #  undef  CONFIG_FT_FDC_DMA
 #  define CONFIG_FT_FDC_DMA 2
 # endif
-#elif CONFIG_FT_ALT_FDC == 1  /* CONFIG_FT_MACH2 */
+#elif defined(CONFIG_FT_ALT_FDC)  /* CONFIG_FT_MACH2 */
 # if CONFIG_FT_FDC_BASE == 0
 #  undef  CONFIG_FT_FDC_BASE
 #  define CONFIG_FT_FDC_BASE 0x370
diff --git a/include/linux/futex.h b/include/linux/futex.h
index 65d6cfdb6d39..10f96c31971e 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -4,14 +4,40 @@
 /* Second argument to futex syscall */
 
 
-#define FUTEX_WAIT (0)
-#define FUTEX_WAKE (1)
-#define FUTEX_FD (2)
-#define FUTEX_REQUEUE (3)
-#define FUTEX_CMP_REQUEUE (4)
+#define FUTEX_WAIT              0
+#define FUTEX_WAKE              1
+#define FUTEX_FD                2
+#define FUTEX_REQUEUE           3
+#define FUTEX_CMP_REQUEUE       4
+#define FUTEX_WAKE_OP           5
 
 long do_futex(unsigned long uaddr, int op, int val,
                 unsigned long timeout, unsigned long uaddr2, int val2,
                 int val3);
 
+#define FUTEX_OP_SET            0       /* *(int *)UADDR2 = OPARG; */
+#define FUTEX_OP_ADD            1       /* *(int *)UADDR2 += OPARG; */
+#define FUTEX_OP_OR             2       /* *(int *)UADDR2 |= OPARG; */
+#define FUTEX_OP_ANDN           3       /* *(int *)UADDR2 &= ~OPARG; */
+#define FUTEX_OP_XOR            4       /* *(int *)UADDR2 ^= OPARG; */
+
+#define FUTEX_OP_OPARG_SHIFT    8       /* Use (1 << OPARG) instead of OPARG.  */
+
+#define FUTEX_OP_CMP_EQ         0       /* if (oldval == CMPARG) wake */
+#define FUTEX_OP_CMP_NE         1       /* if (oldval != CMPARG) wake */
+#define FUTEX_OP_CMP_LT         2       /* if (oldval < CMPARG) wake */
+#define FUTEX_OP_CMP_LE         3       /* if (oldval <= CMPARG) wake */
+#define FUTEX_OP_CMP_GT         4       /* if (oldval > CMPARG) wake */
+#define FUTEX_OP_CMP_GE         5       /* if (oldval >= CMPARG) wake */
+
+/* FUTEX_WAKE_OP will perform atomically
+   int oldval = *(int *)UADDR2;
+   *(int *)UADDR2 = oldval OP OPARG;
+   if (oldval CMP CMPARG)
+     wake UADDR2;  */
+
+#define FUTEX_OP(op, oparg, cmp, cmparg) \
+  (((op & 0xf) << 28) | ((cmp & 0xf) << 24)             \
+   | ((oparg & 0xfff) << 12) | (cmparg & 0xfff))
+
 #endif
diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h
new file mode 100644
index 000000000000..7fd0576a4454
--- /dev/null
+++ b/include/linux/genalloc.h
@@ -0,0 +1,40 @@
+/*
+ * Basic general purpose allocator for managing special purpose memory
+ * not managed by the regular kmalloc/kfree interface.
+ * Uses for this includes on-device special memory, uncached memory
+ * etc.
+ *
+ * This code is based on the buddy allocator found in the sym53c8xx_2
+ * driver, adapted for general purpose use.
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2.  See the file COPYING for more details.
+ */
+
+#include <linux/spinlock.h>
+
+#define ALLOC_MIN_SHIFT         5 /* 32 bytes minimum */
+/*
+ *  Link between free memory chunks of a given size.
+ */
+struct gen_pool_link {
+        struct gen_pool_link *next;
+};
+
+/*
+ *  Memory pool descriptor.
+ */
+struct gen_pool {
+        spinlock_t lock;
+        unsigned long (*get_new_chunk)(struct gen_pool *);
+        struct gen_pool *next;
+        struct gen_pool_link *h;
+        unsigned long private;
+        int max_chunk_shift;
+};
+
+unsigned long gen_pool_alloc(struct gen_pool *poolp, int size);
+void gen_pool_free(struct gen_pool *mp, unsigned long ptr, int size);
+struct gen_pool *gen_pool_create(int nr_chunks, int max_chunk_shift,
+                                 unsigned long (*fp)(struct gen_pool *),
+                                 unsigned long data);
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 47dedaf971d6..01796c41c951 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -224,7 +224,7 @@ static inline void free_disk_stats(struct gendisk *disk)
 extern void disk_round_stats(struct gendisk *disk);
 
 /* drivers/block/genhd.c */
-extern int get_blkdev_list(char *);
+extern int get_blkdev_list(char *, int);
 extern void add_disk(struct gendisk *disk);
 extern void del_gendisk(struct gendisk *gp);
 extern void unlink_gendisk(struct gendisk *gp);
@@ -403,6 +403,7 @@ extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev);
 extern void add_partition(struct gendisk *, int, sector_t, sector_t);
 extern void delete_partition(struct gendisk *, int);
 
+extern struct gendisk *alloc_disk_node(int minors, int node_id);
 extern struct gendisk *alloc_disk(int minors);
 extern struct kobject *get_disk(struct gendisk *disk);
 extern void put_disk(struct gendisk *disk);
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index af7407e8cfc5..4dc990f3b5cc 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -12,8 +12,8 @@ struct vm_area_struct;
  * GFP bitmasks..
  */
 /* Zone modifiers in GFP_ZONEMASK (see linux/mmzone.h - low two bits) */
-#define __GFP_DMA       0x01
-#define __GFP_HIGHMEM   0x02
+#define __GFP_DMA       0x01u
+#define __GFP_HIGHMEM   0x02u
 
 /*
  * Action modifiers - doesn't change the zoning
@@ -39,6 +39,8 @@ struct vm_area_struct;
 #define __GFP_COMP      0x4000u /* Add compound page metadata */
 #define __GFP_ZERO      0x8000u /* Return zeroed page on success */
 #define __GFP_NOMEMALLOC 0x10000u /* Don't use emergency reserves */
+#define __GFP_NORECLAIM  0x20000u /* No realy zone reclaim during allocation */
+#define __GFP_HARDWALL   0x40000u /* Enforce hardwall cpuset memory allocs */
 
 #define __GFP_BITS_SHIFT 20     /* Room for 20 __GFP_FOO bits */
 #define __GFP_BITS_MASK ((1 << __GFP_BITS_SHIFT) - 1)
@@ -47,14 +49,15 @@ struct vm_area_struct;
 #define GFP_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_FS| \
                         __GFP_COLD|__GFP_NOWARN|__GFP_REPEAT| \
                         __GFP_NOFAIL|__GFP_NORETRY|__GFP_NO_GROW|__GFP_COMP| \
-                        __GFP_NOMEMALLOC)
+                        __GFP_NOMEMALLOC|__GFP_NORECLAIM|__GFP_HARDWALL)
 
 #define GFP_ATOMIC      (__GFP_HIGH)
 #define GFP_NOIO        (__GFP_WAIT)
 #define GFP_NOFS        (__GFP_WAIT | __GFP_IO)
 #define GFP_KERNEL      (__GFP_WAIT | __GFP_IO | __GFP_FS)
-#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS)
-#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HIGHMEM)
+#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
+#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
+                         __GFP_HIGHMEM)
 
 /* Flag - indicates that the buffer will be suitable for DMA.  Ignored on some
    platforms, used as appropriate on others */
@@ -132,5 +135,10 @@ extern void FASTCALL(free_cold_page(struct page *page));
 #define free_page(addr) free_pages((addr),0)
 
 void page_alloc_init(void);
+#ifdef CONFIG_NUMA
+void drain_remote_pages(void);
+#else
+static inline void drain_remote_pages(void) { };
+#endif
 
 #endif /* __LINUX_GFP_H */
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 8336dba18971..5912874ca83c 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -2,6 +2,7 @@
 #define LINUX_HARDIRQ_H
 
 #include <linux/config.h>
+#include <linux/preempt.h>
 #include <linux/smp_lock.h>
 #include <asm/hardirq.h>
 #include <asm/system.h>
diff --git a/include/linux/hdlc.h b/include/linux/hdlc.h
index 503194e62fe1..df695e9ae327 100644
--- a/include/linux/hdlc.h
+++ b/include/linux/hdlc.h
@@ -1,7 +1,7 @@
 /*
  * Generic HDLC support routines for Linux
  *
- * Copyright (C) 1999-2003 Krzysztof Halasa <khc@pm.waw.pl>
+ * Copyright (C) 1999-2005 Krzysztof Halasa <khc@pm.waw.pl>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of version 2 of the GNU General Public License
@@ -41,6 +41,7 @@
 #define LMI_NONE                1 /* No LMI, all PVCs are static */
 #define LMI_ANSI                2 /* ANSI Annex D */
 #define LMI_CCITT               3 /* ITU-T Annex A */
+#define LMI_CISCO               4 /* The "original" LMI, aka Gang of Four */
 
 #define HDLC_MAX_MTU 1500       /* Ethernet 1500 bytes */
 #define HDLC_MAX_MRU (HDLC_MAX_MTU + 10 + 14 + 4) /* for ETH+VLAN over FR */
@@ -89,6 +90,7 @@ typedef struct pvc_device_struct {
                 unsigned int deleted: 1;
                 unsigned int fecn: 1;
                 unsigned int becn: 1;
+                unsigned int bandwidth; /* Cisco LMI reporting only */
         }state;
 }pvc_device;
 
@@ -240,8 +242,8 @@ static __inline__ struct net_device_stats *hdlc_stats(struct net_device *dev)
 }
 
 
-static __inline__ unsigned short hdlc_type_trans(struct sk_buff *skb,
-                                                 struct net_device *dev)
+static __inline__ __be16 hdlc_type_trans(struct sk_buff *skb,
+                                         struct net_device *dev)
 {
         hdlc_device *hdlc = dev_to_hdlc(dev);
 
diff --git a/include/linux/highmem.h b/include/linux/highmem.h
index 2a7e6c65c882..6bece9280eb7 100644
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -28,6 +28,7 @@ static inline void *kmap(struct page *page)
 
 #define kmap_atomic(page, idx)          page_address(page)
 #define kunmap_atomic(addr, idx)        do { } while (0)
+#define kmap_atomic_pfn(pfn, idx)       page_address(pfn_to_page(pfn))
 #define kmap_atomic_to_page(ptr)        virt_to_page(ptr)
 
 #endif /* CONFIG_HIGHMEM */
diff --git a/include/linux/hippidevice.h b/include/linux/hippidevice.h
index 9debe6bbe5f0..bab303dafd6e 100644
--- a/include/linux/hippidevice.h
+++ b/include/linux/hippidevice.h
@@ -26,8 +26,12 @@
 #include <linux/if_hippi.h>
 
 #ifdef __KERNEL__
-extern unsigned short hippi_type_trans(struct sk_buff *skb,
-                                       struct net_device *dev);
+
+struct hippi_cb {
+        __u32   ifield;
+};
+
+extern __be16 hippi_type_trans(struct sk_buff *skb, struct net_device *dev);
 
 extern struct net_device *alloc_hippi_dev(int sizeof_priv);
 #endif
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6af1ae4a8211..e670b0d13fe0 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -4,6 +4,7 @@
 #ifdef CONFIG_HUGETLB_PAGE
 
 #include <linux/mempolicy.h>
+#include <asm/tlbflush.h>
 
 struct ctl_table;
 
@@ -22,12 +23,6 @@ int hugetlb_report_meminfo(char *);
 int hugetlb_report_node_meminfo(int, char *);
 int is_hugepage_mem_enough(size_t);
 unsigned long hugetlb_total_pages(void);
-struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
-                              int write);
-struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
-                                pmd_t *pmd, int write);
-int is_aligned_hugepage_range(unsigned long addr, unsigned long len);
-int pmd_huge(pmd_t pmd);
 struct page *alloc_huge_page(void);
 void free_huge_page(struct page *);
 
@@ -35,6 +30,17 @@ extern unsigned long max_huge_pages;
 extern const unsigned long hugetlb_zero, hugetlb_infinity;
 extern int sysctl_hugetlb_shm_group;
 
+/* arch callbacks */
+
+pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr);
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr);
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+                              int write);
+struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+                                pmd_t *pmd, int write);
+int is_aligned_hugepage_range(unsigned long addr, unsigned long len);
+int pmd_huge(pmd_t pmd);
+
 #ifndef ARCH_HAS_HUGEPAGE_ONLY_RANGE
 #define is_hugepage_only_range(mm, addr, len)   0
 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
@@ -48,6 +54,22 @@ extern int sysctl_hugetlb_shm_group;
 int prepare_hugepage_range(unsigned long addr, unsigned long len);
 #endif
 
+#ifndef ARCH_HAS_SETCLEAR_HUGE_PTE
+#define set_huge_pte_at(mm, addr, ptep, pte)    set_pte_at(mm, addr, ptep, pte)
+#define huge_ptep_get_and_clear(mm, addr, ptep) ptep_get_and_clear(mm, addr, ptep)
+#else
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                     pte_t *ptep, pte_t pte);
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep);
+#endif
+
+#ifndef ARCH_HAS_HUGETLB_PREFAULT_HOOK
+#define hugetlb_prefault_arch_hook(mm)          do { } while (0)
+#else
+void hugetlb_prefault_arch_hook(struct mm_struct *mm);
+#endif
+
 #else /* !CONFIG_HUGETLB_PAGE */
 
 static inline int is_vm_hugetlb_page(struct vm_area_struct *vma)
diff --git a/include/linux/hwmon-sysfs.h b/include/linux/hwmon-sysfs.h
new file mode 100644
index 000000000000..7eb4004b3601
--- /dev/null
+++ b/include/linux/hwmon-sysfs.h
@@ -0,0 +1,51 @@
+/*
+ *  hwmon-sysfs.h - hardware monitoring chip driver sysfs defines
+ *
+ *  Copyright (C) 2005 Yani Ioannou <yani.ioannou@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _LINUX_HWMON_SYSFS_H
+#define _LINUX_HWMON_SYSFS_H
+
+struct sensor_device_attribute{
+        struct device_attribute dev_attr;
+        int index;
+};
+#define to_sensor_dev_attr(_dev_attr) \
+        container_of(_dev_attr, struct sensor_device_attribute, dev_attr)
+
+#define SENSOR_DEVICE_ATTR(_name,_mode,_show,_store,_index)     \
+struct sensor_device_attribute sensor_dev_attr_##_name = {      \
+        .dev_attr =     __ATTR(_name,_mode,_show,_store),       \
+        .index =        _index,                                 \
+}
+
+struct sensor_device_attribute_2 {
+        struct device_attribute dev_attr;
+        u8 index;
+        u8 nr;
+};
+#define to_sensor_dev_attr_2(_dev_attr) \
+        container_of(_dev_attr, struct sensor_device_attribute_2, dev_attr)
+
+#define SENSOR_DEVICE_ATTR_2(_name,_mode,_show,_store,_nr,_index)       \
+struct sensor_device_attribute_2 sensor_dev_attr_##_name = {    \
+        .dev_attr =     __ATTR(_name,_mode,_show,_store),       \
+        .index =        _index,                                 \
+        .nr =           _nr,                                    \
+}
+
+#endif /* _LINUX_HWMON_SYSFS_H */
diff --git a/include/linux/hwmon-vid.h b/include/linux/hwmon-vid.h
new file mode 100644
index 000000000000..cd4b7a042b86
--- /dev/null
+++ b/include/linux/hwmon-vid.h
@@ -0,0 +1,45 @@
+/*
+    hwmon-vid.h - VID/VRM/VRD voltage conversions
+
+    Originally part of lm_sensors
+    Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
+    With assistance from Trent Piepho <xyzzy@speakeasy.org>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef _LINUX_HWMON_VID_H
+#define _LINUX_HWMON_VID_H
+
+int vid_from_reg(int val, int vrm);
+int vid_which_vrm(void);
+
+/* vrm is the VRM/VRD document version multiplied by 10.
+   val is in mV to avoid floating point in the kernel.
+   Returned value is the 4-, 5- or 6-bit VID code.
+   Note that only VRM 9.x is supported for now. */
+static inline int vid_to_reg(int val, int vrm)
+{
+        switch (vrm) {
+        case 91:                /* VRM 9.1 */
+        case 90:                /* VRM 9.0 */
+                return ((val >= 1100) && (val <= 1850) ?
+                        ((18499 - val * 10) / 25 + 5) / 10 : -1);
+        default:
+                return -1;
+        }
+}
+
+#endif /* _LINUX_HWMON_VID_H */
diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h
new file mode 100644
index 000000000000..0efd994c37f1
--- /dev/null
+++ b/include/linux/hwmon.h
@@ -0,0 +1,35 @@
+/*
+    hwmon.h - part of lm_sensors, Linux kernel modules for hardware monitoring
+
+    This file declares helper functions for the sysfs class "hwmon",
+    for use by sensors drivers.
+
+    Copyright (C) 2005 Mark M. Hoffman <mhoffman@lightlink.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; version 2 of the License.
+*/
+
+#ifndef _HWMON_H_
+#define _HWMON_H_
+
+#include <linux/device.h>
+
+struct class_device *hwmon_device_register(struct device *dev);
+
+void hwmon_device_unregister(struct class_device *cdev);
+
+/* Scale user input to sensible values */
+static inline int SENSORS_LIMIT(long value, long low, long high)
+{
+        if (value < low)
+                return low;
+        else if (value > high)
+                return high;
+        else
+                return value;
+}
+
+#endif
+
diff --git a/include/linux/i2c-dev.h b/include/linux/i2c-dev.h
index d228230ffe5d..541695679762 100644
--- a/include/linux/i2c-dev.h
+++ b/include/linux/i2c-dev.h
@@ -25,6 +25,7 @@
 #define _LINUX_I2C_DEV_H
 
 #include <linux/types.h>
+#include <linux/compiler.h>
 
 /* Some IOCTL commands are defined in <linux/i2c.h> */
 /* Note: 10-bit addresses are NOT supported! */
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 74d6dc942715..44f30876a1c9 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -1,6 +1,6 @@
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
-/* i2c.h - definitions for the i2c-bus interface                             */
+/* i2c-id.h - identifier values for i2c drivers and adapters                 */
 /*                                                                           */
 /* ------------------------------------------------------------------------- */
 /*   Copyright (C) 1995-1999 Simon G. Vogl
@@ -24,16 +24,6 @@
 #define LINUX_I2C_ID_H
 
 /*
- * This file is part of the i2c-bus package and contains the identifier
- * values for drivers, adapters and other folk populating these serial
- * worlds. 
- *
- * These will change often (i.e. additions) , therefore this has been 
- * separated from the functional interface definitions of the i2c api.
- *
- */
-
-/*
  * ---- Driver types -----------------------------------------------------
  *       device id name + number        function description, i2c address(es)
  *
@@ -108,6 +98,7 @@
 #define I2C_DRIVERID_TDA7313    62      /* TDA7313 audio processor      */
 #define I2C_DRIVERID_MAX6900    63      /* MAX6900 real-time clock      */
 #define I2C_DRIVERID_SAA7114H   64      /* video decoder                */
+#define I2C_DRIVERID_DS1374     65      /* DS1374 real time clock       */
 
 
 #define I2C_DRIVERID_EXP0       0xF0    /* experimental use id's        */
@@ -169,152 +160,113 @@
 
 /*
  * ---- Adapter types ----------------------------------------------------
- *
- * First, we distinguish between several algorithms to access the hardware
- * interface types, as a PCF 8584 needs other care than a bit adapter.
- */
-
-#define I2C_ALGO_NONE   0x000000
-#define I2C_ALGO_BIT    0x010000        /* bit style adapters           */
-#define I2C_ALGO_PCF    0x020000        /* PCF 8584 style adapters      */
-#define I2C_ALGO_ATI    0x030000        /* ATI video card               */
-#define I2C_ALGO_SMBUS  0x040000
-#define I2C_ALGO_ISA    0x050000        /* lm_sensors ISA pseudo-adapter */
-#define I2C_ALGO_SAA7146 0x060000       /* SAA 7146 video decoder bus   */
-#define I2C_ALGO_ACB    0x070000        /* ACCESS.bus algorithm         */
-#define I2C_ALGO_IIC    0x080000        /* ITE IIC bus */
-#define I2C_ALGO_SAA7134 0x090000
-#define I2C_ALGO_MPC824X 0x0a0000       /* Motorola 8240 / 8245         */
-#define I2C_ALGO_IPMI   0x0b0000        /* IPMI dummy adapter */
-#define I2C_ALGO_IPMB   0x0c0000        /* IPMB adapter */
-#define I2C_ALGO_MPC107 0x0d0000
-#define I2C_ALGO_EC     0x100000        /* ACPI embedded controller     */
-
-#define I2C_ALGO_MPC8XX 0x110000        /* MPC8xx PowerPC I2C algorithm */
-#define I2C_ALGO_OCP    0x120000        /* IBM or otherwise On-chip I2C algorithm */
-#define I2C_ALGO_BITHS  0x130000        /* enhanced bit style adapters  */
-#define I2C_ALGO_IOP3XX 0x140000        /* XSCALE IOP3XX On-chip I2C alg */
-#define I2C_ALGO_SIBYTE 0x150000        /* Broadcom SiByte SOCs         */
-#define I2C_ALGO_SGI    0x160000        /* SGI algorithm                */
-
-#define I2C_ALGO_USB    0x170000        /* USB algorithm                */
-#define I2C_ALGO_VIRT   0x180000        /* Virtual bus adapter          */
-
-#define I2C_ALGO_MV64XXX 0x190000       /* Marvell mv64xxx i2c ctlr     */
-#define I2C_ALGO_PCA    0x1a0000        /* PCA 9564 style adapters      */
-#define I2C_ALGO_AU1550 0x1b0000        /* Au1550 PSC algorithm         */
-#define I2C_ALGO_PXA    0x1c0000        /* Intel PXA I2C algorithm      */
-
-#define I2C_ALGO_EXP    0x800000        /* experimental                 */
-
-#define I2C_ALGO_MASK   0xff0000        /* Mask for algorithms          */
-#define I2C_ALGO_SHIFT  0x10    /* right shift to get index values      */
-
-#define I2C_HW_ADAPS    0x10000         /* # adapter types              */
-#define I2C_HW_MASK     0xffff          
-
-
-/* hw specific modules that are defined per algorithm layer
  */
 
 /* --- Bit algorithm adapters                                           */
-#define I2C_HW_B_LP     0x00    /* Parallel port Philips style adapter  */
-#define I2C_HW_B_LPC    0x01    /* Parallel port, over control reg.     */
-#define I2C_HW_B_SER    0x02    /* Serial line interface                */
-#define I2C_HW_B_ELV    0x03    /* ELV Card                             */
-#define I2C_HW_B_VELLE  0x04    /* Vellemann K8000                      */
-#define I2C_HW_B_BT848  0x05    /* BT848 video boards                   */
-#define I2C_HW_B_WNV    0x06    /* Winnov Videums                       */
-#define I2C_HW_B_VIA    0x07    /* Via vt82c586b                        */
-#define I2C_HW_B_HYDRA  0x08    /* Apple Hydra Mac I/O                  */
-#define I2C_HW_B_G400   0x09    /* Matrox G400                          */
-#define I2C_HW_B_I810   0x0a    /* Intel I810                           */
-#define I2C_HW_B_VOO    0x0b    /* 3dfx Voodoo 3 / Banshee              */
-#define I2C_HW_B_PPORT  0x0c    /* Primitive parallel port adapter      */
-#define I2C_HW_B_SAVG   0x0d    /* Savage 4                             */
-#define I2C_HW_B_SCX200 0x0e    /* Nat'l Semi SCx200 I2C                */
-#define I2C_HW_B_RIVA   0x10    /* Riva based graphics cards            */
-#define I2C_HW_B_IOC    0x11    /* IOC bit-wiggling                     */
-#define I2C_HW_B_TSUNA  0x12    /* DEC Tsunami chipset                  */
-#define I2C_HW_B_FRODO  0x13    /* 2d3D, Inc. SA-1110 Development Board */
-#define I2C_HW_B_OMAHA  0x14    /* Omaha I2C interface (ARM)            */
-#define I2C_HW_B_GUIDE  0x15    /* Guide bit-basher                     */
-#define I2C_HW_B_IXP2000 0x16   /* GPIO on IXP2000 systems              */
-#define I2C_HW_B_IXP4XX 0x17    /* GPIO on IXP4XX systems               */
-#define I2C_HW_B_S3VIA  0x18    /* S3Via ProSavage adapter              */
-#define I2C_HW_B_ZR36067 0x19   /* Zoran-36057/36067 based boards       */
-#define I2C_HW_B_PCILYNX 0x1a   /* TI PCILynx I2C adapter               */
-#define I2C_HW_B_CX2388x 0x1b   /* connexant 2388x based tv cards       */
+#define I2C_HW_B_LP             0x010000 /* Parallel port Philips style */
+#define I2C_HW_B_LPC            0x010001 /* Parallel port control reg. */
+#define I2C_HW_B_SER            0x010002 /* Serial line interface */
+#define I2C_HW_B_ELV            0x010003 /* ELV Card */
+#define I2C_HW_B_VELLE          0x010004 /* Vellemann K8000 */
+#define I2C_HW_B_BT848          0x010005 /* BT848 video boards */
+#define I2C_HW_B_WNV            0x010006 /* Winnov Videums */
+#define I2C_HW_B_VIA            0x010007 /* Via vt82c586b */
+#define I2C_HW_B_HYDRA          0x010008 /* Apple Hydra Mac I/O */
+#define I2C_HW_B_G400           0x010009 /* Matrox G400 */
+#define I2C_HW_B_I810           0x01000a /* Intel I810 */
+#define I2C_HW_B_VOO            0x01000b /* 3dfx Voodoo 3 / Banshee */
+#define I2C_HW_B_PPORT          0x01000c /* Primitive parallel port adapter */
+#define I2C_HW_B_SAVG           0x01000d /* Savage 4 */
+#define I2C_HW_B_SCX200         0x01000e /* Nat'l Semi SCx200 I2C */
+#define I2C_HW_B_RIVA           0x010010 /* Riva based graphics cards */
+#define I2C_HW_B_IOC            0x010011 /* IOC bit-wiggling */
+#define I2C_HW_B_TSUNA          0x010012 /* DEC Tsunami chipset */
+#define I2C_HW_B_FRODO          0x010013 /* 2d3D SA-1110 Development Board */
+#define I2C_HW_B_OMAHA          0x010014 /* Omaha I2C interface (ARM) */
+#define I2C_HW_B_GUIDE          0x010015 /* Guide bit-basher */
+#define I2C_HW_B_IXP2000        0x010016 /* GPIO on IXP2000 systems */
+#define I2C_HW_B_IXP4XX         0x010017 /* GPIO on IXP4XX systems */
+#define I2C_HW_B_S3VIA          0x010018 /* S3Via ProSavage adapter */
+#define I2C_HW_B_ZR36067        0x010019 /* Zoran-36057/36067 based boards */
+#define I2C_HW_B_PCILYNX        0x01001a /* TI PCILynx I2C adapter */
+#define I2C_HW_B_CX2388x        0x01001b /* connexant 2388x based tv cards */
+#define I2C_HW_B_NVIDIA         0x01001c /* nvidia framebuffer driver */
+#define I2C_HW_B_SAVAGE         0x01001d /* savage framebuffer driver */
+#define I2C_HW_B_RADEON         0x01001e /* radeon framebuffer driver */
 
 /* --- PCF 8584 based algorithms                                        */
-#define I2C_HW_P_LP     0x00    /* Parallel port interface              */
-#define I2C_HW_P_ISA    0x01    /* generic ISA Bus inteface card        */
-#define I2C_HW_P_ELEK   0x02    /* Elektor ISA Bus inteface card        */
+#define I2C_HW_P_LP             0x020000 /* Parallel port interface */
+#define I2C_HW_P_ISA            0x020001 /* generic ISA Bus inteface card */
+#define I2C_HW_P_ELEK           0x020002 /* Elektor ISA Bus inteface card */
 
 /* --- PCA 9564 based algorithms */
-#define I2C_HW_A_ISA    0x00    /* generic ISA Bus interface card       */
+#define I2C_HW_A_ISA            0x1a0000 /* generic ISA Bus interface card */
 
 /* --- ACPI Embedded controller algorithms                              */
-#define I2C_HW_ACPI_EC          0x00
+#define I2C_HW_ACPI_EC          0x1f0000
 
 /* --- MPC824x PowerPC adapters                                         */
-#define I2C_HW_MPC824X 0x00     /* Motorola 8240 / 8245                 */
+#define I2C_HW_MPC824X          0x100001 /* Motorola 8240 / 8245 */
 
 /* --- MPC8xx PowerPC adapters                                          */
-#define I2C_HW_MPC8XX_EPON 0x00 /* Eponymous MPC8xx I2C adapter         */
+#define I2C_HW_MPC8XX_EPON      0x110000 /* Eponymous MPC8xx I2C adapter */
 
 /* --- ITE based algorithms                                             */
-#define I2C_HW_I_IIC    0x00    /* controller on the ITE */
+#define I2C_HW_I_IIC            0x080000 /* controller on the ITE */
 
 /* --- PowerPC on-chip adapters                                         */
-#define I2C_HW_OCP 0x00 /* IBM on-chip I2C adapter      */
+#define I2C_HW_OCP              0x120000 /* IBM on-chip I2C adapter */
 
 /* --- Broadcom SiByte adapters                                         */
-#define I2C_HW_SIBYTE   0x00
+#define I2C_HW_SIBYTE           0x150000
 
 /* --- SGI adapters                                                     */
-#define I2C_HW_SGI_VINO 0x00
-#define I2C_HW_SGI_MACE 0x01
+#define I2C_HW_SGI_VINO         0x160000
+#define I2C_HW_SGI_MACE         0x160001
 
 /* --- XSCALE on-chip adapters                          */
-#define I2C_HW_IOP3XX 0x00
+#define I2C_HW_IOP3XX           0x140000
 
 /* --- Au1550 PSC adapters adapters                                     */
-#define I2C_HW_AU1550_PSC       0x00
+#define I2C_HW_AU1550_PSC       0x1b0000
 
 /* --- SMBus only adapters                                              */
-#define I2C_HW_SMBUS_PIIX4      0x00
-#define I2C_HW_SMBUS_ALI15X3    0x01
-#define I2C_HW_SMBUS_VIA2       0x02
-#define I2C_HW_SMBUS_VOODOO3    0x03
-#define I2C_HW_SMBUS_I801       0x04
-#define I2C_HW_SMBUS_AMD756     0x05
-#define I2C_HW_SMBUS_SIS5595    0x06
-#define I2C_HW_SMBUS_ALI1535    0x07
-#define I2C_HW_SMBUS_SIS630     0x08
-#define I2C_HW_SMBUS_SIS96X     0x09
-#define I2C_HW_SMBUS_AMD8111    0x0a
-#define I2C_HW_SMBUS_SCX200     0x0b
-#define I2C_HW_SMBUS_NFORCE2    0x0c
-#define I2C_HW_SMBUS_W9968CF    0x0d
-#define I2C_HW_SMBUS_OV511      0x0e    /* OV511(+) USB 1.1 webcam ICs  */
-#define I2C_HW_SMBUS_OV518      0x0f    /* OV518(+) USB 1.1 webcam ICs  */
-#define I2C_HW_SMBUS_OV519      0x10    /* OV519 USB 1.1 webcam IC      */
-#define I2C_HW_SMBUS_OVFX2      0x11    /* Cypress/OmniVision FX2 webcam */
+#define I2C_HW_SMBUS_PIIX4      0x040000
+#define I2C_HW_SMBUS_ALI15X3    0x040001
+#define I2C_HW_SMBUS_VIA2       0x040002
+#define I2C_HW_SMBUS_VOODOO3    0x040003
+#define I2C_HW_SMBUS_I801       0x040004
+#define I2C_HW_SMBUS_AMD756     0x040005
+#define I2C_HW_SMBUS_SIS5595    0x040006
+#define I2C_HW_SMBUS_ALI1535    0x040007
+#define I2C_HW_SMBUS_SIS630     0x040008
+#define I2C_HW_SMBUS_SIS96X     0x040009
+#define I2C_HW_SMBUS_AMD8111    0x04000a
+#define I2C_HW_SMBUS_SCX200     0x04000b
+#define I2C_HW_SMBUS_NFORCE2    0x04000c
+#define I2C_HW_SMBUS_W9968CF    0x04000d
+#define I2C_HW_SMBUS_OV511      0x04000e /* OV511(+) USB 1.1 webcam ICs */
+#define I2C_HW_SMBUS_OV518      0x04000f /* OV518(+) USB 1.1 webcam ICs */
+#define I2C_HW_SMBUS_OV519      0x040010 /* OV519 USB 1.1 webcam IC */
+#define I2C_HW_SMBUS_OVFX2      0x040011 /* Cypress/OmniVision FX2 webcam */
 
 /* --- ISA pseudo-adapter                                               */
-#define I2C_HW_ISA 0x00
+#define I2C_HW_ISA              0x050000
 
 /* --- IPMI pseudo-adapter                                              */
-#define I2C_HW_IPMI 0x00
+#define I2C_HW_IPMI             0x0b0000
 
 /* --- IPMB adapter                                             */
-#define I2C_HW_IPMB 0x00
+#define I2C_HW_IPMB             0x0c0000
 
 /* --- MCP107 adapter */
-#define I2C_HW_MPC107 0x00
+#define I2C_HW_MPC107           0x0d0000
 
 /* --- Marvell mv64xxx i2c adapter */
-#define I2C_HW_MV64XXX 0x00
+#define I2C_HW_MV64XXX          0x190000
+
+/* --- Miscellaneous adapters */
+#define I2C_HW_SAA7146          0x060000 /* SAA7146 video decoder bus */
+#define I2C_HW_SAA7134          0x090000 /* SAA7134 video decoder bus */
 
 #endif /* LINUX_I2C_ID_H */
diff --git a/include/linux/i2c-isa.h b/include/linux/i2c-isa.h
new file mode 100644
index 000000000000..67e3598c4cec
--- /dev/null
+++ b/include/linux/i2c-isa.h
@@ -0,0 +1,36 @@
+/*
+ * i2c-isa.h - definitions for the i2c-isa pseudo-i2c-adapter interface
+ *
+ * Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _LINUX_I2C_ISA_H
+#define _LINUX_I2C_ISA_H
+
+#include <linux/i2c.h>
+
+extern int i2c_isa_add_driver(struct i2c_driver *driver);
+extern int i2c_isa_del_driver(struct i2c_driver *driver);
+
+/* Detect whether we are on the isa bus. This is only useful to hybrid
+   (i2c+isa) drivers. */
+#define i2c_is_isa_adapter(adapptr) \
+        ((adapptr)->id == I2C_HW_ISA)
+#define i2c_is_isa_client(clientptr) \
+        i2c_is_isa_adapter((clientptr)->adapter)
+
+#endif /* _LINUX_I2C_ISA_H */
diff --git a/include/linux/i2c-sensor.h b/include/linux/i2c-sensor.h
deleted file mode 100644
index 21b625204956..000000000000
--- a/include/linux/i2c-sensor.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
-    i2c-sensor.h - Part of the i2c package
-    was originally sensors.h - Part of lm_sensors, Linux kernel modules
-                               for hardware monitoring
-    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-#ifndef _LINUX_I2C_SENSOR_H
-#define _LINUX_I2C_SENSOR_H
-
-/* A structure containing detect information.
-   Force variables overrule all other variables; they force a detection on
-   that place. If a specific chip is given, the module blindly assumes this
-   chip type is present; if a general force (kind == 0) is given, the module
-   will still try to figure out what type of chip is present. This is useful
-   if for some reasons the detect for SMBus or ISA address space filled
-   fails.
-   probe: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values.
-     A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for
-     the ISA bus, -1 for any I2C bus), the second is the address. 
-   kind: The kind of chip. 0 equals any chip.
-*/
-struct i2c_force_data {
-        unsigned short *force;
-        unsigned short kind;
-};
-
-/* A structure containing the detect information.
-   normal_i2c: filled in by the module writer. Terminated by I2C_CLIENT_ISA_END.
-     A list of I2C addresses which should normally be examined.
-   normal_isa: filled in by the module writer. Terminated by SENSORS_ISA_END.
-     A list of ISA addresses which should normally be examined.
-   probe: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values.
-     A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for
-     the ISA bus, -1 for any I2C bus), the second is the address. These
-     addresses are also probed, as if they were in the 'normal' list.
-   ignore: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values.
-     A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for
-     the ISA bus, -1 for any I2C bus), the second is the I2C address. These
-     addresses are never probed. This parameter overrules 'normal' and 
-     'probe', but not the 'force' lists.
-   force_data: insmod parameters. A list, ending with an element of which
-     the force field is NULL.
-*/
-struct i2c_address_data {
-        unsigned short *normal_i2c;
-        unsigned int *normal_isa;
-        unsigned short *probe;
-        unsigned short *ignore;
-        struct i2c_force_data *forces;
-};
-
-#define SENSORS_MODULE_PARM_FORCE(name) \
-  I2C_CLIENT_MODULE_PARM(force_ ## name, \
-                      "List of adapter,address pairs which are unquestionably" \
-                      " assumed to contain a `" # name "' chip")
-
-
-/* This defines several insmod variables, and the addr_data structure */
-#define SENSORS_INSMOD \
-  I2C_CLIENT_MODULE_PARM(probe, \
-                      "List of adapter,address pairs to scan additionally"); \
-  I2C_CLIENT_MODULE_PARM(ignore, \
-                      "List of adapter,address pairs not to scan"); \
-        static struct i2c_address_data addr_data = {                    \
-                        .normal_i2c =           normal_i2c,             \
-                        .normal_isa =           normal_isa,             \
-                        .probe =                probe,                  \
-                        .ignore =               ignore,                 \
-                        .forces =               forces,                 \
-                }
-
-/* The following functions create an enum with the chip names as elements. 
-   The first element of the enum is any_chip. These are the only macros
-   a module will want to use. */
-
-#define SENSORS_INSMOD_0 \
-  enum chips { any_chip }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  static struct i2c_force_data forces[] = {{force,any_chip},{NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_1(chip1) \
-  enum chips { any_chip, chip1 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  static struct i2c_force_data forces[] = {{force,any_chip},\
-                                                 {force_ ## chip1,chip1}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_2(chip1,chip2) \
-  enum chips { any_chip, chip1, chip2 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_3(chip1,chip2,chip3) \
-  enum chips { any_chip, chip1, chip2, chip3 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_4(chip1,chip2,chip3,chip4) \
-  enum chips { any_chip, chip1, chip2, chip3, chip4 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  SENSORS_MODULE_PARM_FORCE(chip4); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {force_ ## chip4,chip4}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_5(chip1,chip2,chip3,chip4,chip5) \
-  enum chips { any_chip, chip1, chip2, chip3, chip4, chip5 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  SENSORS_MODULE_PARM_FORCE(chip4); \
-  SENSORS_MODULE_PARM_FORCE(chip5); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {force_ ## chip4,chip4}, \
-                                                 {force_ ## chip5,chip5}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_6(chip1,chip2,chip3,chip4,chip5,chip6) \
-  enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  SENSORS_MODULE_PARM_FORCE(chip4); \
-  SENSORS_MODULE_PARM_FORCE(chip5); \
-  SENSORS_MODULE_PARM_FORCE(chip6); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {force_ ## chip4,chip4}, \
-                                                 {force_ ## chip5,chip5}, \
-                                                 {force_ ## chip6,chip6}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_7(chip1,chip2,chip3,chip4,chip5,chip6,chip7) \
-  enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, chip7 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  SENSORS_MODULE_PARM_FORCE(chip4); \
-  SENSORS_MODULE_PARM_FORCE(chip5); \
-  SENSORS_MODULE_PARM_FORCE(chip6); \
-  SENSORS_MODULE_PARM_FORCE(chip7); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {force_ ## chip4,chip4}, \
-                                                 {force_ ## chip5,chip5}, \
-                                                 {force_ ## chip6,chip6}, \
-                                                 {force_ ## chip7,chip7}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-#define SENSORS_INSMOD_8(chip1,chip2,chip3,chip4,chip5,chip6,chip7,chip8) \
-  enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8 }; \
-  I2C_CLIENT_MODULE_PARM(force, \
-                      "List of adapter,address pairs to boldly assume " \
-                      "to be present"); \
-  SENSORS_MODULE_PARM_FORCE(chip1); \
-  SENSORS_MODULE_PARM_FORCE(chip2); \
-  SENSORS_MODULE_PARM_FORCE(chip3); \
-  SENSORS_MODULE_PARM_FORCE(chip4); \
-  SENSORS_MODULE_PARM_FORCE(chip5); \
-  SENSORS_MODULE_PARM_FORCE(chip6); \
-  SENSORS_MODULE_PARM_FORCE(chip7); \
-  SENSORS_MODULE_PARM_FORCE(chip8); \
-  static struct i2c_force_data forces[] = {{force,any_chip}, \
-                                                 {force_ ## chip1,chip1}, \
-                                                 {force_ ## chip2,chip2}, \
-                                                 {force_ ## chip3,chip3}, \
-                                                 {force_ ## chip4,chip4}, \
-                                                 {force_ ## chip5,chip5}, \
-                                                 {force_ ## chip6,chip6}, \
-                                                 {force_ ## chip7,chip7}, \
-                                                 {force_ ## chip8,chip8}, \
-                                                 {NULL}}; \
-  SENSORS_INSMOD
-
-/* Detect function. It iterates over all possible addresses itself. For
-   SMBus addresses, it will only call found_proc if some client is connected
-   to the SMBus (unless a 'force' matched); for ISA detections, this is not
-   done. */
-extern int i2c_detect(struct i2c_adapter *adapter,
-                      struct i2c_address_data *address_data,
-                      int (*found_proc) (struct i2c_adapter *, int, int));
-
-
-/* This macro is used to scale user-input to sensible values in almost all
-   chip drivers. */
-static inline int SENSORS_LIMIT(long value, long low, long high)
-{
-        if (value < low)
-                return low;
-        else if (value > high)
-                return high;
-        else
-                return value;
-}
-#endif                          /* def _LINUX_I2C_SENSOR_H */
diff --git a/include/linux/i2c-vid.h b/include/linux/i2c-vid.h
deleted file mode 100644
index 974835e3530f..000000000000
--- a/include/linux/i2c-vid.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
-    i2c-vid.h - Part of lm_sensors, Linux kernel modules for hardware
-                monitoring
-    Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
-    With assistance from Trent Piepho <xyzzy@speakeasy.org>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-
-/*
-    This file contains common code for decoding VID pins.
-    This file is #included in various chip drivers in this directory.
-    As the user is unlikely to load more than one driver which
-    includes this code we don't worry about the wasted space.
-    Reference: VRM x.y DC-DC Converter Design Guidelines,
-    available at http://developer.intel.com
-*/
-
-/*
-    AMD Opteron processors don't follow the Intel VRM spec.
-    I'm going to "make up" 2.4 as the VRM spec for the Opterons.
-    No good reason just a mnemonic for the 24x Opteron processor
-    series
-
-    Opteron VID encoding is:
-
-       00000  =  1.550 V
-       00001  =  1.525 V
-        . . . .
-       11110  =  0.800 V
-       11111  =  0.000 V (off)
- */
-
-/*
-    Legal val values 0x00 - 0x1f; except for VRD 10.0, 0x00 - 0x3f.
-    vrm is the Intel VRM document version.
-    Note: vrm version is scaled by 10 and the return value is scaled by 1000
-    to avoid floating point in the kernel.
-*/
-
-int i2c_which_vrm(void);
-
-#define DEFAULT_VRM     82
-
-static inline int vid_from_reg(int val, int vrm)
-{
-        int vid;
-
-        switch(vrm) {
-
-        case  0:
-                return 0;
-
-        case 100:               /* VRD 10.0 */
-                if((val & 0x1f) == 0x1f)
-                        return 0;
-                if((val & 0x1f) <= 0x09 || val == 0x0a)
-                        vid = 10875 - (val & 0x1f) * 250;
-                else
-                        vid = 18625 - (val & 0x1f) * 250;
-                if(val & 0x20)
-                        vid -= 125;
-                vid /= 10;      /* only return 3 dec. places for now */
-                return vid;
-
-        case 24:                /* Opteron processor */
-                return(val == 0x1f ? 0 : 1550 - val * 25);
-
-        case 91:                /* VRM 9.1 */
-        case 90:                /* VRM 9.0 */
-                return(val == 0x1f ? 0 :
-                                       1850 - val * 25);
-
-        case 85:                /* VRM 8.5 */
-                return((val & 0x10  ? 25 : 0) +
-                       ((val & 0x0f) > 0x04 ? 2050 : 1250) -
-                       ((val & 0x0f) * 50));
-
-        case 84:                /* VRM 8.4 */
-                val &= 0x0f;
-                                /* fall through */
-        default:                /* VRM 8.2 */
-                return(val == 0x1f ? 0 :
-                       val & 0x10  ? 5100 - (val) * 100 :
-                                     2050 - (val) * 50);
-        }
-}
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index ebcd745f4cd6..be35332b67e6 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -34,6 +34,13 @@
 #include <linux/device.h>       /* for struct device */
 #include <asm/semaphore.h>
 
+/* --- For i2c-isa ---------------------------------------------------- */
+
+extern void i2c_adapter_dev_release(struct device *dev);
+extern struct device_driver i2c_adapter_driver;
+extern struct class i2c_adapter_class;
+extern struct bus_type i2c_bus_type;
+
 /* --- General options ------------------------------------------------ */
 
 struct i2c_msg;
@@ -41,7 +48,6 @@ struct i2c_algorithm;
 struct i2c_adapter;
 struct i2c_client;
 struct i2c_driver;
-struct i2c_client_address_data;
 union i2c_smbus_data;
 
 /*
@@ -143,12 +149,9 @@ struct i2c_driver {
  */
 struct i2c_client {
         unsigned int flags;             /* div., see below              */
-        unsigned int addr;              /* chip address - NOTE: 7bit    */
+        unsigned short addr;            /* chip address - NOTE: 7bit    */
                                         /* addresses are stored in the  */
-                                        /* _LOWER_ 7 bits of this char  */
-        /* addr: unsigned int to make lm_sensors i2c-isa adapter work
-          more cleanly. It does not take any more memory space, due to
-          alignment considerations */
+                                        /* _LOWER_ 7 bits               */
         struct i2c_adapter *adapter;    /* the adapter we sit on        */
         struct i2c_driver *driver;      /* and our access routines      */
         int usage_count;                /* How many accesses currently  */
@@ -160,6 +163,11 @@ struct i2c_client {
 };
 #define to_i2c_client(d) container_of(d, struct i2c_client, dev)
 
+static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj)
+{
+        return to_i2c_client(container_of(kobj, struct device, kobj));
+}
+
 static inline void *i2c_get_clientdata (struct i2c_client *dev)
 {
         return dev_get_drvdata (&dev->dev);
@@ -170,13 +178,6 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data)
         dev_set_drvdata (&dev->dev, data);
 }
 
-#define I2C_DEVNAME(str)        .name = str
-
-static inline char *i2c_clientname(struct i2c_client *c)
-{
-        return &c->name[0];
-}
-
 /*
  * The following structs are for those who like to implement new bus drivers:
  * i2c_algorithm is the interface to a class of hardware solutions which can
@@ -184,9 +185,6 @@ static inline char *i2c_clientname(struct i2c_client *c)
  * to name two of the most common.
  */
 struct i2c_algorithm {
-        char name[32];                          /* textual description  */
-        unsigned int id;
-
         /* If an adapter algorithm can't do I2C-level access, set master_xfer
            to NULL. If an adapter algorithm can do SMBus access, set 
            smbus_xfer. If set to NULL, the SMBus protocol is simulated
@@ -214,8 +212,7 @@ struct i2c_algorithm {
  */
 struct i2c_adapter {
         struct module *owner;
-        unsigned int id;/* == is algo->id | hwdep.struct->id,           */
-                        /* for registered values see below              */
+        unsigned int id;
         unsigned int class;
         struct i2c_algorithm *algo;/* the algorithm to access the bus   */
         void *algo_data;
@@ -290,17 +287,13 @@ static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data)
  */
 struct i2c_client_address_data {
         unsigned short *normal_i2c;
-        unsigned short *normal_i2c_range;
         unsigned short *probe;
-        unsigned short *probe_range;
         unsigned short *ignore;
-        unsigned short *ignore_range;
-        unsigned short *force;
+        unsigned short **forces;
 };
 
 /* Internal numbers to terminate lists */
 #define I2C_CLIENT_END          0xfffeU
-#define I2C_CLIENT_ISA_END      0xfffefffeU
 
 /* The numbers to use to set I2C bus address */
 #define ANY_I2C_BUS             0xffff
@@ -359,10 +352,6 @@ extern int i2c_probe(struct i2c_adapter *adapter,
  */
 extern int i2c_control(struct i2c_client *,unsigned int, unsigned long);
 
-/* This call returns a unique low identifier for each registered adapter,
- * or -1 if the adapter was not registered. 
- */
-extern int i2c_adapter_id(struct i2c_adapter *adap);
 extern struct i2c_adapter* i2c_get_adapter(int id);
 extern void i2c_put_adapter(struct i2c_adapter *adap);
 
@@ -379,6 +368,12 @@ static inline int i2c_check_functionality(struct i2c_adapter *adap, u32 func)
         return (func & i2c_get_functionality(adap)) == func;
 }
 
+/* Return id number for a specific adapter */
+static inline int i2c_adapter_id(struct i2c_adapter *adap)
+{
+        return adap->nr;
+}
+
 /*
  * I2C Message - used for pure i2c transaction, also from /dev interface
  */
@@ -513,9 +508,6 @@ union i2c_smbus_data {
 #define I2C_FUNCS       0x0705  /* Get the adapter functionality */
 #define I2C_RDWR        0x0707  /* Combined R/W transfer (one stop only)*/
 #define I2C_PEC         0x0708  /* != 0 for SMBus PEC                   */
-#if 0
-#define I2C_ACK_TEST    0x0710  /* See if a slave is at a specific address */
-#endif
 
 #define I2C_SMBUS       0x0720  /* SMBus-level access */
 
@@ -559,36 +551,148 @@ union i2c_smbus_data {
   module_param_array(var, short, &var##_num, 0); \
   MODULE_PARM_DESC(var,desc)
 
-/* This is the one you want to use in your own modules */
+#define I2C_CLIENT_MODULE_PARM_FORCE(name)                              \
+I2C_CLIENT_MODULE_PARM(force_##name,                                    \
+                       "List of adapter,address pairs which are "       \
+                       "unquestionably assumed to contain a `"          \
+                       # name "' chip")
+
+
+#define I2C_CLIENT_INSMOD_COMMON                                        \
+I2C_CLIENT_MODULE_PARM(probe, "List of adapter,address pairs to scan "  \
+                       "additionally");                                 \
+I2C_CLIENT_MODULE_PARM(ignore, "List of adapter,address pairs not to "  \
+                       "scan");                                         \
+static struct i2c_client_address_data addr_data = {                     \
+        .normal_i2c     = normal_i2c,                                   \
+        .probe          = probe,                                        \
+        .ignore         = ignore,                                       \
+        .forces         = forces,                                       \
+}
+
+/* These are the ones you want to use in your own drivers. Pick the one
+   which matches the number of devices the driver differenciates between. */
 #define I2C_CLIENT_INSMOD \
-  I2C_CLIENT_MODULE_PARM(probe, \
-                      "List of adapter,address pairs to scan additionally"); \
-  I2C_CLIENT_MODULE_PARM(probe_range, \
-                      "List of adapter,start-addr,end-addr triples to scan " \
-                      "additionally"); \
-  I2C_CLIENT_MODULE_PARM(ignore, \
-                      "List of adapter,address pairs not to scan"); \
-  I2C_CLIENT_MODULE_PARM(ignore_range, \
-                      "List of adapter,start-addr,end-addr triples not to " \
-                      "scan"); \
   I2C_CLIENT_MODULE_PARM(force, \
                       "List of adapter,address pairs to boldly assume " \
                       "to be present"); \
-        static struct i2c_client_address_data addr_data = {             \
-                        .normal_i2c =           normal_i2c,             \
-                        .normal_i2c_range =     normal_i2c_range,       \
-                        .probe =                probe,                  \
-                        .probe_range =          probe_range,            \
-                        .ignore =               ignore,                 \
-                        .ignore_range =         ignore_range,           \
-                        .force =                force,                  \
-                }
-
-/* Detect whether we are on the isa bus. If this returns true, all i2c
-   access will fail! */
-#define i2c_is_isa_client(clientptr) \
-        ((clientptr)->adapter->algo->id == I2C_ALGO_ISA)
-#define i2c_is_isa_adapter(adapptr) \
-        ((adapptr)->algo->id == I2C_ALGO_ISA)
+        static unsigned short *forces[] = {                             \
+                        force,                                          \
+                        NULL                                            \
+                };                                                      \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_1(chip1)                                      \
+enum chips { any_chip, chip1 };                                         \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+static unsigned short *forces[] = { force, force_##chip1, NULL };       \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_2(chip1, chip2)                               \
+enum chips { any_chip, chip1, chip2 };                                  \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, NULL };              \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_3(chip1, chip2, chip3)                        \
+enum chips { any_chip, chip1, chip2, chip3 };                           \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    NULL };                             \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_4(chip1, chip2, chip3, chip4)                 \
+enum chips { any_chip, chip1, chip2, chip3, chip4 };                    \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    force_##chip4, NULL};               \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_5(chip1, chip2, chip3, chip4, chip5)          \
+enum chips { any_chip, chip1, chip2, chip3, chip4, chip5 };             \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    force_##chip4, force_##chip5,       \
+                                    NULL };                             \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_6(chip1, chip2, chip3, chip4, chip5, chip6)   \
+enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6 };      \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    force_##chip4, force_##chip5,       \
+                                    force_##chip6, NULL };              \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_7(chip1, chip2, chip3, chip4, chip5, chip6, chip7) \
+enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6,        \
+             chip7 };                                                   \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip7);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    force_##chip4, force_##chip5,       \
+                                    force_##chip6, force_##chip7,       \
+                                    NULL };                             \
+I2C_CLIENT_INSMOD_COMMON
+
+#define I2C_CLIENT_INSMOD_8(chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8) \
+enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6,        \
+             chip7, chip8 };                                            \
+I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+                       "boldly assume to be present");                  \
+I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip7);                                    \
+I2C_CLIENT_MODULE_PARM_FORCE(chip8);                                    \
+static unsigned short *forces[] = { force, force_##chip1,               \
+                                    force_##chip2, force_##chip3,       \
+                                    force_##chip4, force_##chip5,       \
+                                    force_##chip6, force_##chip7,       \
+                                    force_##chip8, NULL };              \
+I2C_CLIENT_INSMOD_COMMON
 
 #endif /* _LINUX_I2C_H */
diff --git a/include/linux/i2o-dev.h b/include/linux/i2o-dev.h
index ef7f644dd873..36fd18cdad28 100644
--- a/include/linux/i2o-dev.h
+++ b/include/linux/i2o-dev.h
@@ -24,6 +24,13 @@
 #define MAX_I2O_CONTROLLERS     32
 
 //#include <linux/ioctl.h>
+#ifndef __KERNEL__
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#endif                          /* __KERNEL__ */
 
 /*
  * I2O Control IOCTLs and structures
@@ -113,6 +120,10 @@ struct i2o_evt_get {
         int lost;
 };
 
+typedef struct i2o_sg_io_hdr {
+        unsigned int flags;     /* see I2O_DPT_SG_IO_FLAGS */
+} i2o_sg_io_hdr_t;
+
 /**************************************************************************
  * HRT related constants and structures
  **************************************************************************/
@@ -126,14 +137,6 @@ struct i2o_evt_get {
 #define I2O_BUS_CARDBUS 7
 #define I2O_BUS_UNKNOWN 0x80
 
-#ifndef __KERNEL__
-
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned int u32;
-
-#endif                          /* __KERNEL__ */
-
 typedef struct _i2o_pci_bus {
         u8 PciFunctionNumber;
         u8 PciDeviceNumber;
@@ -333,7 +336,7 @@ typedef struct _i2o_status_block {
 #define I2O_CLASS_ATE_PERIPHERAL                0x061
 #define I2O_CLASS_FLOPPY_CONTROLLER             0x070
 #define I2O_CLASS_FLOPPY_DEVICE                 0x071
-#define I2O_CLASS_BUS_ADAPTER_PORT              0x080
+#define I2O_CLASS_BUS_ADAPTER                   0x080
 #define I2O_CLASS_PEER_TRANSPORT_AGENT          0x090
 #define I2O_CLASS_PEER_TRANSPORT                0x091
 #define I2O_CLASS_END                           0xfff
@@ -399,4 +402,26 @@ typedef struct _i2o_status_block {
 #define ADAPTER_STATE_FAILED                    0x10
 #define ADAPTER_STATE_FAULTED                   0x11
 
+/*
+ *      Software module types
+ */
+#define I2O_SOFTWARE_MODULE_IRTOS               0x11
+#define I2O_SOFTWARE_MODULE_IOP_PRIVATE         0x22
+#define I2O_SOFTWARE_MODULE_IOP_CONFIG          0x23
+
+/*
+ *      Vendors
+ */
+#define I2O_VENDOR_DPT                          0x001b
+
+/*
+ * DPT / Adaptec specific values for i2o_sg_io_hdr flags.
+ */
+#define I2O_DPT_SG_FLAG_INTERPRET               0x00010000
+#define I2O_DPT_SG_FLAG_PHYSICAL                0x00020000
+
+#define I2O_DPT_FLASH_FRAG_SIZE                 0x10000
+#define I2O_DPT_FLASH_READ                      0x0101
+#define I2O_DPT_FLASH_WRITE                     0x0102
+
 #endif                          /* _I2O_DEV_H */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index ea9a3ad4b67f..bdc286ec947c 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -119,12 +119,21 @@ struct i2o_driver {
 };
 
 /*
- *      Contains all information which are necessary for DMA operations
+ *      Contains DMA mapped address information
  */
 struct i2o_dma {
         void *virt;
         dma_addr_t phys;
-        u32 len;
+        size_t len;
+};
+
+/*
+ *      Contains IO mapped address information
+ */
+struct i2o_io {
+        void __iomem *virt;
+        unsigned long phys;
+        unsigned long len;
 };
 
 /*
@@ -147,28 +156,25 @@ struct i2o_controller {
 
         struct pci_dev *pdev;   /* PCI device */
 
-        unsigned int short_req:1;       /* use small block sizes */
+        unsigned int promise:1; /* Promise controller */
+        unsigned int adaptec:1; /* DPT / Adaptec controller */
+        unsigned int raptor:1;  /* split bar */
         unsigned int no_quiesce:1;      /* dont quiesce before reset */
-        unsigned int raptor:1;          /* split bar */
-        unsigned int promise:1;         /* Promise controller */
-
-#ifdef CONFIG_MTRR
-        int mtrr_reg0;
-        int mtrr_reg1;
-#endif
+        unsigned int short_req:1;       /* use small block sizes */
+        unsigned int limit_sectors:1;   /* limit number of sectors / request */
+        unsigned int pae_support:1;     /* controller has 64-bit SGL support */
 
         struct list_head devices;       /* list of I2O devices */
-
-        struct notifier_block *event_notifer;   /* Events */
-        atomic_t users;
         struct list_head list;  /* Controller list */
-        void __iomem *post_port;        /* Inbout port address */
-        void __iomem *reply_port;       /* Outbound port address */
-        void __iomem *irq_mask;         /* Interrupt register address */
+
+        void __iomem *in_port;  /* Inbout port address */
+        void __iomem *out_port; /* Outbound port address */
+        void __iomem *irq_status;       /* Interrupt status register address */
+        void __iomem *irq_mask; /* Interrupt mask register address */
 
         /* Dynamic LCT related data */
 
-        struct i2o_dma status;  /* status of IOP */
+        struct i2o_dma status;  /* IOP status block */
 
         struct i2o_dma hrt;     /* HW Resource Table */
         i2o_lct *lct;           /* Logical Config Table */
@@ -176,21 +182,19 @@ struct i2o_controller {
         struct semaphore lct_lock;      /* Lock for LCT updates */
         struct i2o_dma status_block;    /* IOP status block */
 
-        struct i2o_dma base;    /* controller messaging unit */
-        struct i2o_dma in_queue;        /* inbound message queue Host->IOP */
+        struct i2o_io base;     /* controller messaging unit */
+        struct i2o_io in_queue; /* inbound message queue Host->IOP */
         struct i2o_dma out_queue;       /* outbound message queue IOP->Host */
 
-        unsigned int battery:1;         /* Has a battery backup */
+        unsigned int battery:1; /* Has a battery backup */
         unsigned int io_alloc:1;        /* An I/O resource was allocated */
         unsigned int mem_alloc:1;       /* A memory resource was allocated */
 
         struct resource io_resource;    /* I/O resource allocated to the IOP */
         struct resource mem_resource;   /* Mem resource allocated to the IOP */
 
-        struct proc_dir_entry *proc_entry;      /* /proc dir */
-
-        struct list_head bus_list;      /* list of busses on IOP */
         struct device device;
+        struct class_device classdev;   /* I2O controller class */
         struct i2o_device *exec;        /* Executive */
 #if BITS_PER_LONG == 64
         spinlock_t context_list_lock;   /* lock for context_list */
@@ -241,9 +245,10 @@ struct i2o_sys_tbl {
 extern struct list_head i2o_controllers;
 
 /* Message functions */
-static inline u32 i2o_msg_get(struct i2o_controller *, struct i2o_message __iomem **);
-extern u32 i2o_msg_get_wait(struct i2o_controller *, struct i2o_message __iomem **,
-                            int);
+static inline u32 i2o_msg_get(struct i2o_controller *,
+                              struct i2o_message __iomem **);
+extern u32 i2o_msg_get_wait(struct i2o_controller *,
+                            struct i2o_message __iomem **, int);
 static inline void i2o_msg_post(struct i2o_controller *, u32);
 static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
                                     unsigned long);
@@ -252,15 +257,6 @@ extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
 extern void i2o_msg_nop(struct i2o_controller *, u32);
 static inline void i2o_flush_reply(struct i2o_controller *, u32);
 
-/* DMA handling functions */
-static inline int i2o_dma_alloc(struct device *, struct i2o_dma *, size_t,
-                                unsigned int);
-static inline void i2o_dma_free(struct device *, struct i2o_dma *);
-int i2o_dma_realloc(struct device *, struct i2o_dma *, size_t, unsigned int);
-
-static inline int i2o_dma_map(struct device *, struct i2o_dma *);
-static inline void i2o_dma_unmap(struct device *, struct i2o_dma *);
-
 /* IOP functions */
 extern int i2o_status_get(struct i2o_controller *);
 
@@ -285,6 +281,16 @@ static inline u32 i2o_ptr_high(void *ptr)
 {
         return (u32) ((u64) ptr >> 32);
 };
+
+static inline u32 i2o_dma_low(dma_addr_t dma_addr)
+{
+        return (u32) (u64) dma_addr;
+};
+
+static inline u32 i2o_dma_high(dma_addr_t dma_addr)
+{
+        return (u32) ((u64) dma_addr >> 32);
+};
 #else
 static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
 {
@@ -315,8 +321,246 @@ static inline u32 i2o_ptr_high(void *ptr)
 {
         return 0;
 };
+
+static inline u32 i2o_dma_low(dma_addr_t dma_addr)
+{
+        return (u32) dma_addr;
+};
+
+static inline u32 i2o_dma_high(dma_addr_t dma_addr)
+{
+        return 0;
+};
 #endif
 
+/**
+ *      i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
+ *      @c: I2O controller for which the calculation should be done
+ *      @body_size: maximum body size used for message in 32-bit words.
+ *
+ *      Return the maximum number of SG elements in a SG list.
+ */
+static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
+{
+        i2o_status_block *sb = c->status_block.virt;
+        u16 sg_count =
+            (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
+            body_size;
+
+        if (c->pae_support) {
+                /*
+                 * for 64-bit a SG attribute element must be added and each
+                 * SG element needs 12 bytes instead of 8.
+                 */
+                sg_count -= 2;
+                sg_count /= 3;
+        } else
+                sg_count /= 2;
+
+        if (c->short_req && (sg_count > 8))
+                sg_count = 8;
+
+        return sg_count;
+};
+
+/**
+ *      i2o_dma_map_single - Map pointer to controller and fill in I2O message.
+ *      @c: I2O controller
+ *      @ptr: pointer to the data which should be mapped
+ *      @size: size of data in bytes
+ *      @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
+ *      @sg_ptr: pointer to the SG list inside the I2O message
+ *
+ *      This function does all necessary DMA handling and also writes the I2O
+ *      SGL elements into the I2O message. For details on DMA handling see also
+ *      dma_map_single(). The pointer sg_ptr will only be set to the end of the
+ *      SG list if the allocation was successful.
+ *
+ *      Returns DMA address which must be checked for failures using
+ *      dma_mapping_error().
+ */
+static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
+                                            size_t size,
+                                            enum dma_data_direction direction,
+                                            u32 __iomem ** sg_ptr)
+{
+        u32 sg_flags;
+        u32 __iomem *mptr = *sg_ptr;
+        dma_addr_t dma_addr;
+
+        switch (direction) {
+        case DMA_TO_DEVICE:
+                sg_flags = 0xd4000000;
+                break;
+        case DMA_FROM_DEVICE:
+                sg_flags = 0xd0000000;
+                break;
+        default:
+                return 0;
+        }
+
+        dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
+        if (!dma_mapping_error(dma_addr)) {
+#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
+                if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
+                        writel(0x7C020002, mptr++);
+                        writel(PAGE_SIZE, mptr++);
+                }
+#endif
+
+                writel(sg_flags | size, mptr++);
+                writel(i2o_dma_low(dma_addr), mptr++);
+#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
+                if ((sizeof(dma_addr_t) > 4) && c->pae_support)
+                        writel(i2o_dma_high(dma_addr), mptr++);
+#endif
+                *sg_ptr = mptr;
+        }
+        return dma_addr;
+};
+
+/**
+ *      i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
+ *      @c: I2O controller
+ *      @sg: SG list to be mapped
+ *      @sg_count: number of elements in the SG list
+ *      @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
+ *      @sg_ptr: pointer to the SG list inside the I2O message
+ *
+ *      This function does all necessary DMA handling and also writes the I2O
+ *      SGL elements into the I2O message. For details on DMA handling see also
+ *      dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
+ *      list if the allocation was successful.
+ *
+ *      Returns 0 on failure or 1 on success.
+ */
+static inline int i2o_dma_map_sg(struct i2o_controller *c,
+                                 struct scatterlist *sg, int sg_count,
+                                 enum dma_data_direction direction,
+                                 u32 __iomem ** sg_ptr)
+{
+        u32 sg_flags;
+        u32 __iomem *mptr = *sg_ptr;
+
+        switch (direction) {
+        case DMA_TO_DEVICE:
+                sg_flags = 0x14000000;
+                break;
+        case DMA_FROM_DEVICE:
+                sg_flags = 0x10000000;
+                break;
+        default:
+                return 0;
+        }
+
+        sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
+        if (!sg_count)
+                return 0;
+
+#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
+        if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
+                writel(0x7C020002, mptr++);
+                writel(PAGE_SIZE, mptr++);
+        }
+#endif
+
+        while (sg_count-- > 0) {
+                if (!sg_count)
+                        sg_flags |= 0xC0000000;
+                writel(sg_flags | sg_dma_len(sg), mptr++);
+                writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
+#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
+                if ((sizeof(dma_addr_t) > 4) && c->pae_support)
+                        writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
+#endif
+                sg++;
+        }
+        *sg_ptr = mptr;
+
+        return 1;
+};
+
+/**
+ *      i2o_dma_alloc - Allocate DMA memory
+ *      @dev: struct device pointer to the PCI device of the I2O controller
+ *      @addr: i2o_dma struct which should get the DMA buffer
+ *      @len: length of the new DMA memory
+ *      @gfp_mask: GFP mask
+ *
+ *      Allocate a coherent DMA memory and write the pointers into addr.
+ *
+ *      Returns 0 on success or -ENOMEM on failure.
+ */
+static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
+                                size_t len, unsigned int gfp_mask)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        int dma_64 = 0;
+
+        if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
+                dma_64 = 1;
+                if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
+                        return -ENOMEM;
+        }
+
+        addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
+
+        if ((sizeof(dma_addr_t) > 4) && dma_64)
+                if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
+                        printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
+
+        if (!addr->virt)
+                return -ENOMEM;
+
+        memset(addr->virt, 0, len);
+        addr->len = len;
+
+        return 0;
+};
+
+/**
+ *      i2o_dma_free - Free DMA memory
+ *      @dev: struct device pointer to the PCI device of the I2O controller
+ *      @addr: i2o_dma struct which contains the DMA buffer
+ *
+ *      Free a coherent DMA memory and set virtual address of addr to NULL.
+ */
+static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
+{
+        if (addr->virt) {
+                if (addr->phys)
+                        dma_free_coherent(dev, addr->len, addr->virt,
+                                          addr->phys);
+                else
+                        kfree(addr->virt);
+                addr->virt = NULL;
+        }
+};
+
+/**
+ *      i2o_dma_realloc - Realloc DMA memory
+ *      @dev: struct device pointer to the PCI device of the I2O controller
+ *      @addr: pointer to a i2o_dma struct DMA buffer
+ *      @len: new length of memory
+ *      @gfp_mask: GFP mask
+ *
+ *      If there was something allocated in the addr, free it first. If len > 0
+ *      than try to allocate it and write the addresses back to the addr
+ *      structure. If len == 0 set the virtual address to NULL.
+ *
+ *      Returns the 0 on success or negative error code on failure.
+ */
+static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
+                                  size_t len, unsigned int gfp_mask)
+{
+        i2o_dma_free(dev, addr);
+
+        if (len)
+                return i2o_dma_alloc(dev, addr, len, gfp_mask);
+
+        return 0;
+};
+
 /* I2O driver (OSM) functions */
 extern int i2o_driver_register(struct i2o_driver *);
 extern void i2o_driver_unregister(struct i2o_driver *);
@@ -385,49 +629,11 @@ extern int i2o_device_claim_release(struct i2o_device *);
 /* Exec OSM functions */
 extern int i2o_exec_lct_get(struct i2o_controller *);
 
-/* device to i2o_device and driver to i2o_driver convertion functions */
+/* device / driver / kobject conversion functions */
 #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
 #define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
-
-/*
- *      Messenger inlines
- */
-static inline u32 I2O_POST_READ32(struct i2o_controller *c)
-{
-        rmb();
-        return readl(c->post_port);
-};
-
-static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val)
-{
-        wmb();
-        writel(val, c->post_port);
-};
-
-static inline u32 I2O_REPLY_READ32(struct i2o_controller *c)
-{
-        rmb();
-        return readl(c->reply_port);
-};
-
-static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val)
-{
-        wmb();
-        writel(val, c->reply_port);
-};
-
-static inline u32 I2O_IRQ_READ32(struct i2o_controller *c)
-{
-        rmb();
-        return readl(c->irq_mask);
-};
-
-static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
-{
-        wmb();
-        writel(val, c->irq_mask);
-        wmb();
-};
+#define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
+#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
 
 /**
  *      i2o_msg_get - obtain an I2O message from the IOP
@@ -443,11 +649,11 @@ static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
  *      available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
  */
 static inline u32 i2o_msg_get(struct i2o_controller *c,
-                              struct i2o_message __iomem **msg)
+                              struct i2o_message __iomem ** msg)
 {
-        u32 m;
+        u32 m = readl(c->in_port);
 
-        if ((m = I2O_POST_READ32(c)) != I2O_QUEUE_EMPTY)
+        if (m != I2O_QUEUE_EMPTY)
                 *msg = c->in_queue.virt + m;
 
         return m;
@@ -462,7 +668,7 @@ static inline u32 i2o_msg_get(struct i2o_controller *c,
  */
 static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
 {
-        I2O_POST_WRITE32(c, m);
+        writel(m, c->in_port);
 };
 
 /**
@@ -491,12 +697,10 @@ static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
  *      The I2O controller must be informed that the reply message is not needed
  *      anymore. If you forget to flush the reply, the message frame can't be
  *      used by the controller anymore and is therefore lost.
- *
- *      FIXME: is there a timeout after which the controller reuse the message?
  */
 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
 {
-        I2O_REPLY_WRITE32(c, m);
+        writel(m, c->out_port);
 };
 
 /**
@@ -530,97 +734,13 @@ static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
  *      work for receive side messages as they are kmalloc objects
  *      in a different pool.
  */
-static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct i2o_controller *c,
-                                                     u32 m)
+static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
+                                                             i2o_controller *c,
+                                                             u32 m)
 {
         return c->in_queue.virt + m;
 };
 
-/**
- *      i2o_dma_alloc - Allocate DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which should get the DMA buffer
- *      @len: length of the new DMA memory
- *      @gfp_mask: GFP mask
- *
- *      Allocate a coherent DMA memory and write the pointers into addr.
- *
- *      Returns 0 on success or -ENOMEM on failure.
- */
-static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
-                                size_t len, unsigned int gfp_mask)
-{
-        addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
-        if (!addr->virt)
-                return -ENOMEM;
-
-        memset(addr->virt, 0, len);
-        addr->len = len;
-
-        return 0;
-};
-
-/**
- *      i2o_dma_free - Free DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which contains the DMA buffer
- *
- *      Free a coherent DMA memory and set virtual address of addr to NULL.
- */
-static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
-{
-        if (addr->virt) {
-                if (addr->phys)
-                        dma_free_coherent(dev, addr->len, addr->virt,
-                                          addr->phys);
-                else
-                        kfree(addr->virt);
-                addr->virt = NULL;
-        }
-};
-
-/**
- *      i2o_dma_map - Map the memory to DMA
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which should be mapped
- *
- *      Map the memory in addr->virt to coherent DMA memory and write the
- *      physical address into addr->phys.
- *
- *      Returns 0 on success or -ENOMEM on failure.
- */
-static inline int i2o_dma_map(struct device *dev, struct i2o_dma *addr)
-{
-        if (!addr->virt)
-                return -EFAULT;
-
-        if (!addr->phys)
-                addr->phys = dma_map_single(dev, addr->virt, addr->len,
-                                            DMA_BIDIRECTIONAL);
-        if (!addr->phys)
-                return -ENOMEM;
-
-        return 0;
-};
-
-/**
- *      i2o_dma_unmap - Unmap the DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which should be unmapped
- *
- *      Unmap the memory in addr->virt from DMA memory.
- */
-static inline void i2o_dma_unmap(struct device *dev, struct i2o_dma *addr)
-{
-        if (!addr->virt)
-                return;
-
-        if (addr->phys) {
-                dma_unmap_single(dev, addr->phys, addr->len, DMA_BIDIRECTIONAL);
-                addr->phys = 0;
-        }
-};
-
 /*
  *      Endian handling wrapped into the macro - keeps the core code
  *      cleaner.
@@ -773,6 +893,14 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define I2O_CMD_SCSI_BUSRESET           0x27
 
 /*
+ * Bus Adapter Class
+ */
+#define I2O_CMD_BUS_ADAPTER_RESET       0x85
+#define I2O_CMD_BUS_RESET               0x87
+#define I2O_CMD_BUS_SCAN                0x89
+#define I2O_CMD_BUS_QUIESCE             0x8b
+
+/*
  * Random Block Storage Class
  */
 #define I2O_CMD_BLOCK_READ              0x30
@@ -784,7 +912,7 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define I2O_CMD_BLOCK_MEJECT            0x43
 #define I2O_CMD_BLOCK_POWER             0x70
 
-#define I2O_PRIVATE_MSG                 0xFF
+#define I2O_CMD_PRIVATE                 0xFF
 
 /* Command status values  */
 
@@ -922,7 +1050,7 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define I2OVER15        0x0001
 #define I2OVER20        0x0002
 
-/* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */
+/* Default is 1.5 */
 #define I2OVERSION      I2OVER15
 
 #define SGL_OFFSET_0    I2OVERSION
@@ -933,9 +1061,9 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define SGL_OFFSET_8    (0x0080 | I2OVERSION)
 #define SGL_OFFSET_9    (0x0090 | I2OVERSION)
 #define SGL_OFFSET_10   (0x00A0 | I2OVERSION)
-
-#define TRL_OFFSET_5    (0x0050 | I2OVERSION)
-#define TRL_OFFSET_6    (0x0060 | I2OVERSION)
+#define SGL_OFFSET_11   (0x00B0 | I2OVERSION)
+#define SGL_OFFSET_12   (0x00C0 | I2OVERSION)
+#define SGL_OFFSET(x)   (((x)<<4) | I2OVERSION)
 
 /* Transaction Reply Lists (TRL) Control Word structure */
 #define TRL_SINGLE_FIXED_LENGTH         0x00
@@ -962,17 +1090,13 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define ELEVEN_WORD_MSG_SIZE    0x000B0000
 #define I2O_MESSAGE_SIZE(x)     ((x)<<16)
 
-/* Special TID Assignments */
-
+/* special TID assignments */
 #define ADAPTER_TID             0
 #define HOST_TID                1
 
-#define MSG_FRAME_SIZE          128     /* i2o_scsi assumes >= 32 */
-#define REPLY_FRAME_SIZE        17
-#define SG_TABLESIZE            30
-#define NMBR_MSG_FRAMES         128
-
-#define MSG_POOL_SIZE           (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
+/* outbound queue defines */
+#define I2O_MAX_OUTBOUND_MSG_FRAMES     128
+#define I2O_OUTBOUND_MSG_FRAME_SIZE     128     /* in 32-bit words */
 
 #define I2O_POST_WAIT_OK        0
 #define I2O_POST_WAIT_TIMEOUT   -ETIMEDOUT
@@ -993,11 +1117,10 @@ extern void i2o_debug_state(struct i2o_controller *c);
 #define I2O_HRT_GET_TRIES               3
 #define I2O_LCT_GET_TRIES               3
 
-/* request queue sizes */
+/* defines for max_sectors and max_phys_segments */
 #define I2O_MAX_SECTORS                 1024
-#define I2O_MAX_SEGMENTS                128
-
-#define I2O_REQ_MEMPOOL_SIZE            32
+#define I2O_MAX_SECTORS_LIMITED         256
+#define I2O_MAX_PHYS_SEGMENTS           MAX_PHYS_SEGMENTS
 
 #endif                          /* __KERNEL__ */
 #endif                          /* _I2O_H */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 336d6e509f59..a6dbb51ecd7b 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -917,7 +917,7 @@ typedef struct hwif_s {
         unsigned dma;
 
         void (*led_act)(void *data, int rw);
-} ide_hwif_t;
+} ____cacheline_maxaligned_in_smp ide_hwif_t;
 
 /*
  *  internal ide interrupt handler type
@@ -1501,4 +1501,10 @@ extern struct bus_type ide_bus_type;
 #define ide_id_has_flush_cache_ext(id)  \
         (((id)->cfs_enable_2 & 0x2400) == 0x2400)
 
+static inline int hwif_to_node(ide_hwif_t *hwif)
+{
+        struct pci_dev *dev = hwif->pci_dev;
+        return dev ? pcibus_to_node(dev->bus) : -1;
+}
+
 #endif /* _IDE_H */
diff --git a/include/linux/if.h b/include/linux/if.h
index d73a9d62f208..ce627d9092ef 100644
--- a/include/linux/if.h
+++ b/include/linux/if.h
@@ -33,7 +33,7 @@
 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
-#define IFF_RUNNING     0x40            /* resources allocated          */
+#define IFF_RUNNING     0x40            /* interface running and carrier ok */
 #define IFF_NOARP       0x80            /* no ARP protocol              */
 #define IFF_PROMISC     0x100           /* receive all packets          */
 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
diff --git a/include/linux/if_bonding.h b/include/linux/if_bonding.h
index 57024ce2c74f..84598fa2e9de 100644
--- a/include/linux/if_bonding.h
+++ b/include/linux/if_bonding.h
@@ -35,6 +35,9 @@
  *
  * 2003/12/01 - Shmulik Hen <shmulik.hen at intel dot com>
  *      - Code cleanup and style changes
+ *
+ * 2005/05/05 - Jason Gabler <jygabler at lbl dot gov>
+ *      - added definitions for various XOR hashing policies
  */
 
 #ifndef _LINUX_IF_BONDING_H
@@ -80,6 +83,10 @@
 
 #define BOND_DEFAULT_MAX_BONDS  1   /* Default maximum number of devices to support */
 
+/* hashing types */
+#define BOND_XMIT_POLICY_LAYER2         0 /* layer 2 (MAC only), default */
+#define BOND_XMIT_POLICY_LAYER34        1 /* layer 3+4 (IP ^ MAC) */
+
 typedef struct ifbond {
         __s32 bond_mode;
         __s32 num_slaves;
diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h
index b5b58e9c054c..fc2d4c8225aa 100644
--- a/include/linux/if_ether.h
+++ b/include/linux/if_ether.h
@@ -110,6 +110,8 @@ static inline struct ethhdr *eth_hdr(const struct sk_buff *skb)
 {
         return (struct ethhdr *)skb->mac.raw;
 }
+
+extern struct ctl_table ether_table[];
 #endif
 
 #endif  /* _LINUX_IF_ETHER_H */
diff --git a/include/linux/if_fc.h b/include/linux/if_fc.h
index 33330b458b95..376a34ea4723 100644
--- a/include/linux/if_fc.h
+++ b/include/linux/if_fc.h
@@ -44,7 +44,7 @@ struct fcllc {
         __u8  ssap;                     /* source SAP */
         __u8  llc;                      /* LLC control field */
         __u8  protid[3];                /* protocol id */
-        __u16 ethertype;                /* ether type field */
+        __be16 ethertype;               /* ether type field */
 };
 
 #endif  /* _LINUX_IF_FC_H */
diff --git a/include/linux/if_fddi.h b/include/linux/if_fddi.h
index a912818e6361..1288a161bc0b 100644
--- a/include/linux/if_fddi.h
+++ b/include/linux/if_fddi.h
@@ -85,7 +85,7 @@ struct fddi_snap_hdr
         __u8    ssap;                                   /* always 0xAA */
         __u8    ctrl;                                   /* always 0x03 */
         __u8    oui[FDDI_K_OUI_LEN];    /* organizational universal id */
-        __u16   ethertype;                              /* packet type ID field */
+        __be16  ethertype;                              /* packet type ID field */
         } __attribute__ ((packed));
 
 /* Define FDDI LLC frame header */
diff --git a/include/linux/if_frad.h b/include/linux/if_frad.h
index 3c94b1736570..511999c7eeda 100644
--- a/include/linux/if_frad.h
+++ b/include/linux/if_frad.h
@@ -191,10 +191,12 @@ struct frad_local
    int               buffer;            /* current buffer for S508 firmware */
 };
 
-extern void dlci_ioctl_set(int (*hook)(unsigned int, void __user *));
-
 #endif /* __KERNEL__ */
 
 #endif /* CONFIG_DLCI || CONFIG_DLCI_MODULE */
 
+#ifdef __KERNEL__
+extern void dlci_ioctl_set(int (*hook)(unsigned int, void __user *));
+#endif
+
 #endif
diff --git a/include/linux/if_hippi.h b/include/linux/if_hippi.h
index c8ca72c46f76..94d31ca7d71a 100644
--- a/include/linux/if_hippi.h
+++ b/include/linux/if_hippi.h
@@ -102,9 +102,9 @@ struct hippi_fp_hdr
 #error  "Please fix <asm/byteorder.h>"
 #endif
 #else
-        __u32           fixed;
+        __be32          fixed;
 #endif
-        __u32           d2_size;
+        __be32          d2_size;
 } __attribute__ ((packed));
 
 struct hippi_le_hdr
@@ -144,7 +144,7 @@ struct hippi_snap_hdr
         __u8    ssap;                   /* always 0xAA */
         __u8    ctrl;                   /* always 0x03 */
         __u8    oui[HIPPI_OUI_LEN];     /* organizational universal id (zero)*/
-        __u16   ethertype;              /* packet type ID field */
+        __be16  ethertype;              /* packet type ID field */
 } __attribute__ ((packed));
 
 struct hippi_hdr
diff --git a/include/linux/if_shaper.h b/include/linux/if_shaper.h
index 004e6f09a6e2..68c896a36a34 100644
--- a/include/linux/if_shaper.h
+++ b/include/linux/if_shaper.h
@@ -23,7 +23,7 @@ struct shaper
         __u32 shapeclock;
         unsigned long recovery; /* Time we can next clock a packet out on
                                    an empty queue */
-        struct semaphore sem;
+        spinlock_t lock;
         struct net_device_stats stats;
         struct net_device *dev;
         int  (*hard_start_xmit) (struct sk_buff *skb,
diff --git a/include/linux/if_tr.h b/include/linux/if_tr.h
index 6688b414c529..5502f597cf0e 100644
--- a/include/linux/if_tr.h
+++ b/include/linux/if_tr.h
@@ -19,6 +19,8 @@
 #ifndef _LINUX_IF_TR_H
 #define _LINUX_IF_TR_H
 
+#include <asm/byteorder.h>      /* For __be16 */
+
 /* IEEE 802.5 Token-Ring magic constants.  The frame sizes omit the preamble
    and FCS/CRC (frame check sequence). */
 #define TR_ALEN         6               /* Octets in one token-ring addr */
@@ -41,12 +43,16 @@ struct trh_hdr {
 };
 
 #ifdef __KERNEL__
+#include <linux/config.h>
 #include <linux/skbuff.h>
 
 static inline struct trh_hdr *tr_hdr(const struct sk_buff *skb)
 {
         return (struct trh_hdr *)skb->mac.raw;
 }
+#ifdef CONFIG_SYSCTL
+extern struct ctl_table tr_table[];
+#endif
 #endif
 
 /* This is an Token-Ring LLC structure */
diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h
index 096a85a58ae5..88aef7b86ef4 100644
--- a/include/linux/if_tun.h
+++ b/include/linux/if_tun.h
@@ -77,6 +77,7 @@ struct tun_struct {
 #define TUNSETIFF     _IOW('T', 202, int) 
 #define TUNSETPERSIST _IOW('T', 203, int) 
 #define TUNSETOWNER   _IOW('T', 204, int)
+#define TUNSETLINK    _IOW('T', 205, int)
 
 /* TUNSETIFF ifr flags */
 #define IFF_TUN         0x0001
diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h
index 62a9d89dfbe2..17d0c0d40b0e 100644
--- a/include/linux/if_vlan.h
+++ b/include/linux/if_vlan.h
@@ -155,7 +155,6 @@ static inline int __vlan_hwaccel_rx(struct sk_buff *skb,
 {
         struct net_device_stats *stats;
 
-        skb->real_dev = skb->dev;
         skb->dev = grp->vlan_devices[vlan_tag & VLAN_VID_MASK];
         if (skb->dev == NULL) {
                 dev_kfree_skb_any(skb);
diff --git a/include/linux/igmp.h b/include/linux/igmp.h
index 390e760a96d3..28f4f3b36950 100644
--- a/include/linux/igmp.h
+++ b/include/linux/igmp.h
@@ -129,6 +129,9 @@ struct igmpv3_query {
 #include <linux/skbuff.h>
 #include <linux/in.h>
 
+extern int sysctl_igmp_max_memberships;
+extern int sysctl_igmp_max_msf;
+
 struct ip_sf_socklist
 {
         unsigned int            sl_max;
@@ -148,7 +151,6 @@ struct ip_sf_socklist
 struct ip_mc_socklist
 {
         struct ip_mc_socklist   *next;
-        int                     count;
         struct ip_mreqn         multi;
         unsigned int            sfmode;         /* MCAST_{INCLUDE,EXCLUDE} */
         struct ip_sf_socklist   *sflist;
diff --git a/include/linux/in.h b/include/linux/in.h
index fb88c66d748d..ba355384016a 100644
--- a/include/linux/in.h
+++ b/include/linux/in.h
@@ -32,6 +32,7 @@ enum {
   IPPROTO_PUP = 12,             /* PUP protocol                         */
   IPPROTO_UDP = 17,             /* User Datagram Protocol               */
   IPPROTO_IDP = 22,             /* XNS IDP protocol                     */
+  IPPROTO_DCCP = 33,            /* Datagram Congestion Control Protocol */
   IPPROTO_RSVP = 46,            /* RSVP protocol                        */
   IPPROTO_GRE = 47,             /* Cisco GRE tunnels (rfc 1701,1702)    */
 
diff --git a/include/linux/in6.h b/include/linux/in6.h
index f8256c582845..dcf5720ffcbb 100644
--- a/include/linux/in6.h
+++ b/include/linux/in6.h
@@ -156,7 +156,7 @@ struct in6_flowlabel_req
 #define IPV6_CHECKSUM           7
 #define IPV6_HOPLIMIT           8
 #define IPV6_NEXTHOP            9
-#define IPV6_AUTHHDR            10
+#define IPV6_AUTHHDR            10      /* obsolete */
 #define IPV6_FLOWINFO           11
 
 #define IPV6_UNICAST_HOPS       16
diff --git a/include/linux/inet_diag.h b/include/linux/inet_diag.h
new file mode 100644
index 000000000000..a4606e5810e5
--- /dev/null
+++ b/include/linux/inet_diag.h
@@ -0,0 +1,138 @@
+#ifndef _INET_DIAG_H_
+#define _INET_DIAG_H_ 1
+
+/* Just some random number */
+#define TCPDIAG_GETSOCK 18
+#define DCCPDIAG_GETSOCK 19
+
+#define INET_DIAG_GETSOCK_MAX 24
+
+/* Socket identity */
+struct inet_diag_sockid {
+        __u16   idiag_sport;
+        __u16   idiag_dport;
+        __u32   idiag_src[4];
+        __u32   idiag_dst[4];
+        __u32   idiag_if;
+        __u32   idiag_cookie[2];
+#define INET_DIAG_NOCOOKIE (~0U)
+};
+
+/* Request structure */
+
+struct inet_diag_req {
+        __u8    idiag_family;           /* Family of addresses. */
+        __u8    idiag_src_len;
+        __u8    idiag_dst_len;
+        __u8    idiag_ext;              /* Query extended information */
+
+        struct inet_diag_sockid id;
+
+        __u32   idiag_states;           /* States to dump */
+        __u32   idiag_dbs;              /* Tables to dump (NI) */
+};
+
+enum {
+        INET_DIAG_REQ_NONE,
+        INET_DIAG_REQ_BYTECODE,
+};
+
+#define INET_DIAG_REQ_MAX INET_DIAG_REQ_BYTECODE
+
+/* Bytecode is sequence of 4 byte commands followed by variable arguments.
+ * All the commands identified by "code" are conditional jumps forward:
+ * to offset cc+"yes" or to offset cc+"no". "yes" is supposed to be
+ * length of the command and its arguments.
+ */
+ 
+struct inet_diag_bc_op {
+        unsigned char   code;
+        unsigned char   yes;
+        unsigned short  no;
+};
+
+enum {
+        INET_DIAG_BC_NOP,
+        INET_DIAG_BC_JMP,
+        INET_DIAG_BC_S_GE,
+        INET_DIAG_BC_S_LE,
+        INET_DIAG_BC_D_GE,
+        INET_DIAG_BC_D_LE,
+        INET_DIAG_BC_AUTO,
+        INET_DIAG_BC_S_COND,
+        INET_DIAG_BC_D_COND,
+};
+
+struct inet_diag_hostcond {
+        __u8    family;
+        __u8    prefix_len;
+        int     port;
+        __u32   addr[0];
+};
+
+/* Base info structure. It contains socket identity (addrs/ports/cookie)
+ * and, alas, the information shown by netstat. */
+struct inet_diag_msg {
+        __u8    idiag_family;
+        __u8    idiag_state;
+        __u8    idiag_timer;
+        __u8    idiag_retrans;
+
+        struct inet_diag_sockid id;
+
+        __u32   idiag_expires;
+        __u32   idiag_rqueue;
+        __u32   idiag_wqueue;
+        __u32   idiag_uid;
+        __u32   idiag_inode;
+};
+
+/* Extensions */
+
+enum {
+        INET_DIAG_NONE,
+        INET_DIAG_MEMINFO,
+        INET_DIAG_INFO,
+        INET_DIAG_VEGASINFO,
+        INET_DIAG_CONG,
+};
+
+#define INET_DIAG_MAX INET_DIAG_CONG
+
+
+/* INET_DIAG_MEM */
+
+struct inet_diag_meminfo {
+        __u32   idiag_rmem;
+        __u32   idiag_wmem;
+        __u32   idiag_fmem;
+        __u32   idiag_tmem;
+};
+
+/* INET_DIAG_VEGASINFO */
+
+struct tcpvegas_info {
+        __u32   tcpv_enabled;
+        __u32   tcpv_rttcnt;
+        __u32   tcpv_rtt;
+        __u32   tcpv_minrtt;
+};
+
+#ifdef __KERNEL__
+struct sock;
+struct inet_hashinfo;
+
+struct inet_diag_handler {
+        struct inet_hashinfo    *idiag_hashinfo;
+        void                    (*idiag_get_info)(struct sock *sk,
+                                                  struct inet_diag_msg *r,
+                                                  void *info);
+        __u16                   idiag_info_size;
+        __u16                   idiag_type;
+};
+
+extern int  inet_diag_register(const struct inet_diag_handler *handler);
+extern void inet_diag_unregister(const struct inet_diag_handler *handler);
+#endif /* __KERNEL__ */
+
+#endif /* _INET_DIAG_H_ */
diff --git a/include/linux/init.h b/include/linux/init.h
index 05c83e0521ca..59008c3826cf 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -229,6 +229,18 @@ void __init parse_early_param(void);
 #define __devexitdata __exitdata
 #endif
 
+#ifdef CONFIG_HOTPLUG_CPU
+#define __cpuinit
+#define __cpuinitdata
+#define __cpuexit
+#define __cpuexitdata
+#else
+#define __cpuinit       __init
+#define __cpuinitdata __initdata
+#define __cpuexit __exit
+#define __cpuexitdata   __exitdata
+#endif
+
 /* Functions marked as __devexit may be discarded at kernel link time, depending
    on config options.  Newer versions of binutils detect references from
    retained sections to discarded sections and flag an error.  Pointers to
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index a6a8c1a38d5e..c727c195a91a 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -81,6 +81,7 @@ extern struct group_info init_groups;
         .mm             = NULL,                                         \
         .active_mm      = &init_mm,                                     \
         .run_list       = LIST_HEAD_INIT(tsk.run_list),                 \
+        .ioprio         = 0,                                            \
         .time_slice     = HZ,                                           \
         .tasks          = LIST_HEAD_INIT(tsk.tasks),                    \
         .ptrace_children= LIST_HEAD_INIT(tsk.ptrace_children),          \
@@ -108,9 +109,9 @@ extern struct group_info init_groups;
         .blocked        = {{0}},                                        \
         .alloc_lock     = SPIN_LOCK_UNLOCKED,                           \
         .proc_lock      = SPIN_LOCK_UNLOCKED,                           \
-        .switch_lock    = SPIN_LOCK_UNLOCKED,                           \
         .journal_info   = NULL,                                         \
         .cpu_timers     = INIT_CPU_TIMERS(tsk.cpu_timers),              \
+        .fs_excl        = ATOMIC_INIT(0),                               \
 }
 
 
diff --git a/include/linux/inotify.h b/include/linux/inotify.h
new file mode 100644
index 000000000000..ee5b239092ed
--- /dev/null
+++ b/include/linux/inotify.h
@@ -0,0 +1,111 @@
+/*
+ * Inode based directory notification for Linux
+ *
+ * Copyright (C) 2005 John McCutchan
+ */
+
+#ifndef _LINUX_INOTIFY_H
+#define _LINUX_INOTIFY_H
+
+#include <linux/types.h>
+
+/*
+ * struct inotify_event - structure read from the inotify device for each event
+ *
+ * When you are watching a directory, you will receive the filename for events
+ * such as IN_CREATE, IN_DELETE, IN_OPEN, IN_CLOSE, ..., relative to the wd.
+ */
+struct inotify_event {
+        __s32           wd;             /* watch descriptor */
+        __u32           mask;           /* watch mask */
+        __u32           cookie;         /* cookie to synchronize two events */
+        __u32           len;            /* length (including nulls) of name */
+        char            name[0];        /* stub for possible name */
+};
+
+/* the following are legal, implemented events that user-space can watch for */
+#define IN_ACCESS               0x00000001      /* File was accessed */
+#define IN_MODIFY               0x00000002      /* File was modified */
+#define IN_ATTRIB               0x00000004      /* Metadata changed */
+#define IN_CLOSE_WRITE          0x00000008      /* Writtable file was closed */
+#define IN_CLOSE_NOWRITE        0x00000010      /* Unwrittable file closed */
+#define IN_OPEN                 0x00000020      /* File was opened */
+#define IN_MOVED_FROM           0x00000040      /* File was moved from X */
+#define IN_MOVED_TO             0x00000080      /* File was moved to Y */
+#define IN_CREATE               0x00000100      /* Subfile was created */
+#define IN_DELETE               0x00000200      /* Subfile was deleted */
+#define IN_DELETE_SELF          0x00000400      /* Self was deleted */
+#define IN_MOVE_SELF            0x00000800      /* Self was moved */
+
+/* the following are legal events.  they are sent as needed to any watch */
+#define IN_UNMOUNT              0x00002000      /* Backing fs was unmounted */
+#define IN_Q_OVERFLOW           0x00004000      /* Event queued overflowed */
+#define IN_IGNORED              0x00008000      /* File was ignored */
+
+/* helper events */
+#define IN_CLOSE                (IN_CLOSE_WRITE | IN_CLOSE_NOWRITE) /* close */
+#define IN_MOVE                 (IN_MOVED_FROM | IN_MOVED_TO) /* moves */
+
+/* special flags */
+#define IN_MASK_ADD             0x20000000      /* add to the mask of an already existing watch */
+#define IN_ISDIR                0x40000000      /* event occurred against dir */
+#define IN_ONESHOT              0x80000000      /* only send event once */
+
+/*
+ * All of the events - we build the list by hand so that we can add flags in
+ * the future and not break backward compatibility.  Apps will get only the
+ * events that they originally wanted.  Be sure to add new events here!
+ */
+#define IN_ALL_EVENTS   (IN_ACCESS | IN_MODIFY | IN_ATTRIB | IN_CLOSE_WRITE | \
+                         IN_CLOSE_NOWRITE | IN_OPEN | IN_MOVED_FROM | \
+                         IN_MOVED_TO | IN_DELETE | IN_CREATE | IN_DELETE_SELF | \
+                         IN_MOVE_SELF)
+
+#ifdef __KERNEL__
+
+#include <linux/dcache.h>
+#include <linux/fs.h>
+#include <linux/config.h>
+
+#ifdef CONFIG_INOTIFY
+
+extern void inotify_inode_queue_event(struct inode *, __u32, __u32,
+                                      const char *);
+extern void inotify_dentry_parent_queue_event(struct dentry *, __u32, __u32,
+                                              const char *);
+extern void inotify_unmount_inodes(struct list_head *);
+extern void inotify_inode_is_dead(struct inode *);
+extern u32 inotify_get_cookie(void);
+
+#else
+
+static inline void inotify_inode_queue_event(struct inode *inode,
+                                             __u32 mask, __u32 cookie,
+                                             const char *filename)
+{
+}
+
+static inline void inotify_dentry_parent_queue_event(struct dentry *dentry,
+                                                     __u32 mask, __u32 cookie,
+                                                     const char *filename)
+{
+}
+
+static inline void inotify_unmount_inodes(struct list_head *list)
+{
+}
+
+static inline void inotify_inode_is_dead(struct inode *inode)
+{
+}
+
+static inline u32 inotify_get_cookie(void)
+{
+        return 0;
+}
+
+#endif  /* CONFIG_INOTIFY */
+
+#endif  /* __KERNEL __ */
+
+#endif  /* _LINUX_INOTIFY_H */
diff --git a/include/linux/input.h b/include/linux/input.h
index 72731d7d189e..4767e5429534 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -66,6 +66,7 @@ struct input_absinfo {
 #define EVIOCGKEY(len)          _IOC(_IOC_READ, 'E', 0x18, len)         /* get global keystate */
 #define EVIOCGLED(len)          _IOC(_IOC_READ, 'E', 0x19, len)         /* get all LEDs */
 #define EVIOCGSND(len)          _IOC(_IOC_READ, 'E', 0x1a, len)         /* get all sounds status */
+#define EVIOCGSW(len)           _IOC(_IOC_READ, 'E', 0x1b, len)         /* get all switch states */
 
 #define EVIOCGBIT(ev,len)       _IOC(_IOC_READ, 'E', 0x20 + ev, len)    /* get event bits */
 #define EVIOCGABS(abs)          _IOR('E', 0x40 + abs, struct input_absinfo)             /* get abs value/limits */
@@ -86,6 +87,7 @@ struct input_absinfo {
 #define EV_REL                  0x02
 #define EV_ABS                  0x03
 #define EV_MSC                  0x04
+#define EV_SW                   0x05
 #define EV_LED                  0x11
 #define EV_SND                  0x12
 #define EV_REP                  0x14
@@ -551,6 +553,20 @@ struct input_absinfo {
 #define ABS_MAX                 0x3f
 
 /*
+ * Switch events
+ */
+
+#define SW_0            0x00
+#define SW_1            0x01
+#define SW_2            0x02
+#define SW_3            0x03
+#define SW_4            0x04
+#define SW_5            0x05
+#define SW_6            0x06
+#define SW_7            0x07
+#define SW_MAX          0x0f
+
+/*
  * Misc events
  */
 
@@ -811,9 +827,9 @@ struct input_dev {
 
         void *private;
 
-        char *name;
-        char *phys;
-        char *uniq;
+        const char *name;
+        const char *phys;
+        const char *uniq;
         struct input_id id;
 
         unsigned long evbit[NBITS(EV_MAX)];
@@ -824,6 +840,7 @@ struct input_dev {
         unsigned long ledbit[NBITS(LED_MAX)];
         unsigned long sndbit[NBITS(SND_MAX)];
         unsigned long ffbit[NBITS(FF_MAX)];
+        unsigned long swbit[NBITS(SW_MAX)];
         int ff_effects_max;
 
         unsigned int keycodemax;
@@ -844,6 +861,7 @@ struct input_dev {
         unsigned long key[NBITS(KEY_MAX)];
         unsigned long led[NBITS(LED_MAX)];
         unsigned long snd[NBITS(SND_MAX)];
+        unsigned long sw[NBITS(SW_MAX)];
 
         int absmax[ABS_MAX + 1];
         int absmin[ABS_MAX + 1];
@@ -859,6 +877,10 @@ struct input_dev {
         int (*erase_effect)(struct input_dev *dev, int effect_id);
 
         struct input_handle *grab;
+
+        struct semaphore sem;   /* serializes open and close operations */
+        unsigned int users;
+
         struct device *dev;
 
         struct list_head        h_list;
@@ -882,6 +904,7 @@ struct input_dev {
 #define INPUT_DEVICE_ID_MATCH_LEDBIT    0x200
 #define INPUT_DEVICE_ID_MATCH_SNDBIT    0x400
 #define INPUT_DEVICE_ID_MATCH_FFBIT     0x800
+#define INPUT_DEVICE_ID_MATCH_SWBIT     0x1000
 
 #define INPUT_DEVICE_ID_MATCH_DEVICE\
         (INPUT_DEVICE_ID_MATCH_BUS | INPUT_DEVICE_ID_MATCH_VENDOR | INPUT_DEVICE_ID_MATCH_PRODUCT)
@@ -902,6 +925,7 @@ struct input_device_id {
         unsigned long ledbit[NBITS(LED_MAX)];
         unsigned long sndbit[NBITS(SND_MAX)];
         unsigned long ffbit[NBITS(FF_MAX)];
+        unsigned long swbit[NBITS(SW_MAX)];
 
         unsigned long driver_info;
 };
@@ -994,6 +1018,11 @@ static inline void input_report_ff_status(struct input_dev *dev, unsigned int co
         input_event(dev, EV_FF_STATUS, code, value);
 }
 
+static inline void input_report_switch(struct input_dev *dev, unsigned int code, int value)
+{
+        input_event(dev, EV_SW, code, !!value);
+}
+
 static inline void input_regs(struct input_dev *dev, struct pt_regs *regs)
 {
         dev->regs = regs;
@@ -1015,7 +1044,7 @@ static inline void input_set_abs_params(struct input_dev *dev, int axis, int min
         dev->absbit[LONG(axis)] |= BIT(axis);
 }
 
-extern struct class_simple *input_class;
+extern struct class *input_class;
 
 #endif
 #endif
diff --git a/include/linux/ioc4.h b/include/linux/ioc4.h
new file mode 100644
index 000000000000..3dd18b785ebd
--- /dev/null
+++ b/include/linux/ioc4.h
@@ -0,0 +1,179 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2005 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#ifndef _LINUX_IOC4_H
+#define _LINUX_IOC4_H
+
+#include <linux/interrupt.h>
+
+/***************
+ * Definitions *
+ ***************/
+
+/* Miscellaneous values inherent to hardware */
+
+#define IOC4_EXTINT_COUNT_DIVISOR 520   /* PCI clocks per COUNT tick */
+
+/***********************************
+ * Structures needed by subdrivers *
+ ***********************************/
+
+/* This structure fully describes the IOC4 miscellaneous registers which
+ * appear at bar[0]+0x00000 through bar[0]+0x0005c.  The corresponding
+ * PCI resource is managed by the main IOC4 driver because it contains
+ * registers of interest to many different IOC4 subdrivers.
+ */
+struct ioc4_misc_regs {
+        /* Miscellaneous IOC4 registers */
+        union ioc4_pci_err_addr_l {
+                uint32_t raw;
+                struct {
+                        uint32_t valid:1;       /* Address captured */
+                        uint32_t master_id:4;   /* Unit causing error
+                                                 * 0/1: Serial port 0 TX/RX
+                                                 * 2/3: Serial port 1 TX/RX
+                                                 * 4/5: Serial port 2 TX/RX
+                                                 * 6/7: Serial port 3 TX/RX
+                                                 * 8: ATA/ATAPI
+                                                 * 9-15: Undefined
+                                                 */
+                        uint32_t mul_err:1;     /* Multiple errors occurred */
+                        uint32_t addr:26;       /* Bits 31-6 of error addr */
+                } fields;
+        } pci_err_addr_l;
+        uint32_t pci_err_addr_h;        /* Bits 63-32 of error addr */
+        union ioc4_sio_int {
+                uint32_t raw;
+                struct {
+                        uint8_t tx_mt:1;        /* TX ring buffer empty */
+                        uint8_t rx_full:1;      /* RX ring buffer full */
+                        uint8_t rx_high:1;      /* RX high-water exceeded */
+                        uint8_t rx_timer:1;     /* RX timer has triggered */
+                        uint8_t delta_dcd:1;    /* DELTA_DCD seen */
+                        uint8_t delta_cts:1;    /* DELTA_CTS seen */
+                        uint8_t intr_pass:1;    /* Interrupt pass-through */
+                        uint8_t tx_explicit:1;  /* TX, MCW, or delay complete */
+                } fields[4];
+        } sio_ir;               /* Serial interrupt state */
+        union ioc4_other_int {
+                uint32_t raw;
+                struct {
+                        uint32_t ata_int:1;     /* ATA port passthru */
+                        uint32_t ata_memerr:1;  /* ATA halted by mem error */
+                        uint32_t memerr:4;      /* Serial halted by mem err */
+                        uint32_t kbd_int:1;     /* kbd/mouse intr asserted */
+                        uint32_t reserved:16;   /* zero */
+                        uint32_t rt_int:1;      /* INT_OUT section latch */
+                        uint32_t gen_int:8;     /* Intr. from generic pins */
+                } fields;
+        } other_ir;             /* Other interrupt state */
+        union ioc4_sio_int sio_ies;     /* Serial interrupt enable set */
+        union ioc4_other_int other_ies; /* Other interrupt enable set */
+        union ioc4_sio_int sio_iec;     /* Serial interrupt enable clear */
+        union ioc4_other_int other_iec; /* Other interrupt enable clear */
+        union ioc4_sio_cr {
+                uint32_t raw;
+                struct {
+                        uint32_t cmd_pulse:4;   /* Bytebus strobe width */
+                        uint32_t arb_diag:3;    /* PCI bus requester */
+                        uint32_t sio_diag_idle:1;       /* Active ser req? */
+                        uint32_t ata_diag_idle:1;       /* Active ATA req? */
+                        uint32_t ata_diag_active:1;     /* ATA req is winner */
+                        uint32_t reserved:22;   /* zero */
+                } fields;
+        } sio_cr;
+        uint32_t unused1;
+        union ioc4_int_out {
+                uint32_t raw;
+                struct {
+                        uint32_t count:16;      /* Period control */
+                        uint32_t mode:3;        /* Output signal shape */
+                        uint32_t reserved:11;   /* zero */
+                        uint32_t diag:1;        /* Timebase control */
+                        uint32_t int_out:1;     /* Current value */
+                } fields;
+        } int_out;              /* External interrupt output control */
+        uint32_t unused2;
+        union ioc4_gpcr {
+                uint32_t raw;
+                struct {
+                        uint32_t dir:8; /* Pin direction */
+                        uint32_t edge:8;        /* Edge/level mode */
+                        uint32_t reserved1:4;   /* zero */
+                        uint32_t int_out_en:1;  /* INT_OUT enable */
+                        uint32_t reserved2:11;  /* zero */
+                } fields;
+        } gpcr_s;               /* Generic PIO control set */
+        union ioc4_gpcr gpcr_c; /* Generic PIO control clear */
+        union ioc4_gpdr {
+                uint32_t raw;
+                struct {
+                        uint32_t gen_pin:8;     /* State of pins */
+                        uint32_t reserved:24;
+                } fields;
+        } gpdr;                 /* Generic PIO data */
+        uint32_t unused3;
+        union ioc4_gppr {
+                uint32_t raw;
+                struct {
+                        uint32_t gen_pin:1;     /* Single pin state */
+                        uint32_t reserved:31;
+                } fields;
+        } gppr[8];              /* Generic PIO pins */
+};
+
+/* Masks for GPCR DIR pins */
+#define IOC4_GPCR_DIR_0 0x01    /* External interrupt output */
+#define IOC4_GPCR_DIR_1 0x02    /* External interrupt input */
+#define IOC4_GPCR_DIR_2 0x04
+#define IOC4_GPCR_DIR_3 0x08    /* Keyboard/mouse presence */
+#define IOC4_GPCR_DIR_4 0x10    /* Ser. port 0 xcvr select (0=232, 1=422) */
+#define IOC4_GPCR_DIR_5 0x20    /* Ser. port 1 xcvr select (0=232, 1=422) */
+#define IOC4_GPCR_DIR_6 0x40    /* Ser. port 2 xcvr select (0=232, 1=422) */
+#define IOC4_GPCR_DIR_7 0x80    /* Ser. port 3 xcvr select (0=232, 1=422) */
+
+/* Masks for GPCR EDGE pins */
+#define IOC4_GPCR_EDGE_0 0x01
+#define IOC4_GPCR_EDGE_1 0x02   /* External interrupt input */
+#define IOC4_GPCR_EDGE_2 0x04
+#define IOC4_GPCR_EDGE_3 0x08
+#define IOC4_GPCR_EDGE_4 0x10
+#define IOC4_GPCR_EDGE_5 0x20
+#define IOC4_GPCR_EDGE_6 0x40
+#define IOC4_GPCR_EDGE_7 0x80
+
+/* One of these per IOC4 */
+struct ioc4_driver_data {
+        struct list_head idd_list;
+        unsigned long idd_bar0;
+        struct pci_dev *idd_pdev;
+        const struct pci_device_id *idd_pci_id;
+        struct __iomem ioc4_misc_regs *idd_misc_regs;
+        unsigned long count_period;
+        void *idd_serial_data;
+};
+
+/* One per submodule */
+struct ioc4_submodule {
+        struct list_head is_list;
+        char *is_name;
+        struct module *is_owner;
+        int (*is_probe) (struct ioc4_driver_data *);
+        int (*is_remove) (struct ioc4_driver_data *);
+};
+
+#define IOC4_NUM_CARDS          8       /* max cards per partition */
+
+/**********************************
+ * Functions needed by submodules *
+ **********************************/
+
+extern int ioc4_register_submodule(struct ioc4_submodule *);
+extern void ioc4_unregister_submodule(struct ioc4_submodule *);
+
+#endif                          /* _LINUX_IOC4_H */
diff --git a/include/linux/ioc4_common.h b/include/linux/ioc4_common.h
deleted file mode 100644
index b03bcc46df55..000000000000
--- a/include/linux/ioc4_common.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2005 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-#ifndef _LINUX_IOC4_COMMON_H
-#define _LINUX_IOC4_COMMON_H
-
-/* prototypes */
-
-int ioc4_serial_init(void);
-
-int ioc4_serial_attach_one(struct pci_dev *pdev, const struct
-                                pci_device_id *pci_id);
-int ioc4_ide_attach_one(struct pci_dev *pdev, const struct
-                                pci_device_id *pci_id);
-
-#endif  /* _LINUX_IOC4_COMMON_H */
diff --git a/include/linux/ioctl32.h b/include/linux/ioctl32.h
index e8c4af32b3bb..948809d99917 100644
--- a/include/linux/ioctl32.h
+++ b/include/linux/ioctl32.h
@@ -14,26 +14,4 @@ struct ioctl_trans {
         struct ioctl_trans *next;
 };
 
-/* 
- * Register an 32bit ioctl translation handler for ioctl cmd.
- *
- * handler == NULL: use 64bit ioctl handler.
- * arguments to handler:  fd: file descriptor
- *                        cmd: ioctl command.
- *                        arg: ioctl argument
- *                        struct file *file: file descriptor pointer.
- */ 
-
-#ifdef CONFIG_COMPAT
-extern int __deprecated register_ioctl32_conversion(unsigned int cmd,
-                                ioctl_trans_handler_t handler);
-extern int __deprecated unregister_ioctl32_conversion(unsigned int cmd);
-
-#else
-
-#define register_ioctl32_conversion(cmd, handler)       ({ 0; })
-#define unregister_ioctl32_conversion(cmd)              ({ 0; })
-
-#endif
-
 #endif
diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h
new file mode 100644
index 000000000000..88d5961f7a3f
--- /dev/null
+++ b/include/linux/ioprio.h
@@ -0,0 +1,85 @@
+#ifndef IOPRIO_H
+#define IOPRIO_H
+
+#include <linux/sched.h>
+
+/*
+ * Gives us 8 prio classes with 13-bits of data for each class
+ */
+#define IOPRIO_BITS             (16)
+#define IOPRIO_CLASS_SHIFT      (13)
+#define IOPRIO_PRIO_MASK        ((1UL << IOPRIO_CLASS_SHIFT) - 1)
+
+#define IOPRIO_PRIO_CLASS(mask) ((mask) >> IOPRIO_CLASS_SHIFT)
+#define IOPRIO_PRIO_DATA(mask)  ((mask) & IOPRIO_PRIO_MASK)
+#define IOPRIO_PRIO_VALUE(class, data)  (((class) << IOPRIO_CLASS_SHIFT) | data)
+
+#define ioprio_valid(mask)      (IOPRIO_PRIO_CLASS((mask)) != IOPRIO_CLASS_NONE)
+
+/*
+ * These are the io priority groups as implemented by CFQ. RT is the realtime
+ * class, it always gets premium service. BE is the best-effort scheduling
+ * class, the default for any process. IDLE is the idle scheduling class, it
+ * is only served when no one else is using the disk.
+ */
+enum {
+        IOPRIO_CLASS_NONE,
+        IOPRIO_CLASS_RT,
+        IOPRIO_CLASS_BE,
+        IOPRIO_CLASS_IDLE,
+};
+
+/*
+ * 8 best effort priority levels are supported
+ */
+#define IOPRIO_BE_NR    (8)
+
+enum {
+        IOPRIO_WHO_PROCESS = 1,
+        IOPRIO_WHO_PGRP,
+        IOPRIO_WHO_USER,
+};
+
+/*
+ * if process has set io priority explicitly, use that. if not, convert
+ * the cpu scheduler nice value to an io priority
+ */
+#define IOPRIO_NORM     (4)
+static inline int task_ioprio(struct task_struct *task)
+{
+        WARN_ON(!ioprio_valid(task->ioprio));
+        return IOPRIO_PRIO_DATA(task->ioprio);
+}
+
+static inline int task_nice_ioprio(struct task_struct *task)
+{
+        return (task_nice(task) + 20) / 5;
+}
+
+/*
+ * For inheritance, return the highest of the two given priorities
+ */
+static inline int ioprio_best(unsigned short aprio, unsigned short bprio)
+{
+        unsigned short aclass = IOPRIO_PRIO_CLASS(aprio);
+        unsigned short bclass = IOPRIO_PRIO_CLASS(bprio);
+
+        if (!ioprio_valid(aprio))
+                return bprio;
+        if (!ioprio_valid(bprio))
+                return aprio;
+
+        if (aclass == IOPRIO_CLASS_NONE)
+                aclass = IOPRIO_CLASS_BE;
+        if (bclass == IOPRIO_CLASS_NONE)
+                bclass = IOPRIO_CLASS_BE;
+
+        if (aclass == bclass)
+                return min(aprio, bprio);
+        if (aclass > bclass)
+                return bprio;
+        else
+                return aprio;
+}
+
+#endif
diff --git a/include/linux/ip.h b/include/linux/ip.h
index 8438c68591f9..33e8a19a1a0f 100644
--- a/include/linux/ip.h
+++ b/include/linux/ip.h
@@ -81,6 +81,7 @@
 #ifdef __KERNEL__
 #include <linux/config.h>
 #include <linux/types.h>
+#include <net/request_sock.h>
 #include <net/sock.h>
 #include <linux/igmp.h>
 #include <net/flow.h>
@@ -107,6 +108,26 @@ struct ip_options {
 
 #define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
 
+struct inet_request_sock {
+        struct request_sock     req;
+        u32                     loc_addr;
+        u32                     rmt_addr;
+        u16                     rmt_port;
+        u16                     snd_wscale : 4, 
+                                rcv_wscale : 4, 
+                                tstamp_ok  : 1,
+                                sack_ok    : 1,
+                                wscale_ok  : 1,
+                                ecn_ok     : 1,
+                                acked      : 1;
+        struct ip_options       *opt;
+};
+
+static inline struct inet_request_sock *inet_rsk(const struct request_sock *sk)
+{
+        return (struct inet_request_sock *)sk;
+}
+
 struct ipv6_pinfo;
 
 struct inet_sock {
@@ -175,6 +196,8 @@ static inline void inet_sk_copy_descendant(struct sock *sk_to,
 #endif
 #endif
 
+extern int inet_sk_rebuild_header(struct sock *sk);
+
 struct iphdr {
 #if defined(__LITTLE_ENDIAN_BITFIELD)
         __u8    ihl:4,
diff --git a/include/linux/ipmi.h b/include/linux/ipmi.h
index 2ec265e1045f..938d55b813a5 100644
--- a/include/linux/ipmi.h
+++ b/include/linux/ipmi.h
@@ -35,6 +35,7 @@
 #define __LINUX_IPMI_H
 
 #include <linux/ipmi_msgdefs.h>
+#include <linux/compiler.h>
 
 /*
  * This file describes an interface to an IPMI driver.  You have to
@@ -209,6 +210,11 @@ struct kernel_ipmi_msg
 #include <linux/list.h>
 #include <linux/module.h>
 
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+extern struct proc_dir_entry *proc_ipmi_root;
+#endif /* CONFIG_PROC_FS */
+
 /* Opaque type for a IPMI message user.  One of these is needed to
    send and receive messages. */
 typedef struct ipmi_user *ipmi_user_t;
@@ -236,7 +242,8 @@ struct ipmi_recv_msg
         /* The user_msg_data is the data supplied when a message was
            sent, if this is a response to a sent message.  If this is
            not a response to a sent message, then user_msg_data will
-           be NULL. */
+           be NULL.  If the user above is NULL, then this will be the
+           intf. */
         void             *user_msg_data;
 
         /* Call this when done with the message.  It will presumably free
@@ -293,13 +300,19 @@ void ipmi_get_version(ipmi_user_t   user,
    this user, so it will affect all users of this interface.  This is
    so some initialization code can come in and do the OEM-specific
    things it takes to determine your address (if not the BMC) and set
-   it for everyone else. */
-void ipmi_set_my_address(ipmi_user_t   user,
-                         unsigned char address);
-unsigned char ipmi_get_my_address(ipmi_user_t user);
-void ipmi_set_my_LUN(ipmi_user_t   user,
-                     unsigned char LUN);
-unsigned char ipmi_get_my_LUN(ipmi_user_t user);
+   it for everyone else.  Note that each channel can have its own address. */
+int ipmi_set_my_address(ipmi_user_t   user,
+                        unsigned int  channel,
+                        unsigned char address);
+int ipmi_get_my_address(ipmi_user_t   user,
+                        unsigned int  channel,
+                        unsigned char *address);
+int ipmi_set_my_LUN(ipmi_user_t   user,
+                    unsigned int  channel,
+                    unsigned char LUN);
+int ipmi_get_my_LUN(ipmi_user_t   user,
+                    unsigned int  channel,
+                    unsigned char *LUN);
 
 /*
  * Like ipmi_request, but lets you specify the number of retries and
@@ -580,6 +593,16 @@ struct ipmi_cmdspec
  * things it takes to determine your address (if not the BMC) and set
  * it for everyone else.  You should probably leave the LUN alone.
  */
+struct ipmi_channel_lun_address_set
+{
+        unsigned short channel;
+        unsigned char  value;
+};
+#define IPMICTL_SET_MY_CHANNEL_ADDRESS_CMD _IOR(IPMI_IOC_MAGIC, 24, struct ipmi_channel_lun_address_set)
+#define IPMICTL_GET_MY_CHANNEL_ADDRESS_CMD _IOR(IPMI_IOC_MAGIC, 25, struct ipmi_channel_lun_address_set)
+#define IPMICTL_SET_MY_CHANNEL_LUN_CMD     _IOR(IPMI_IOC_MAGIC, 26, struct ipmi_channel_lun_address_set)
+#define IPMICTL_GET_MY_CHANNEL_LUN_CMD     _IOR(IPMI_IOC_MAGIC, 27, struct ipmi_channel_lun_address_set)
+/* Legacy interfaces, these only set IPMB 0. */
 #define IPMICTL_SET_MY_ADDRESS_CMD      _IOR(IPMI_IOC_MAGIC, 17, unsigned int)
 #define IPMICTL_GET_MY_ADDRESS_CMD      _IOR(IPMI_IOC_MAGIC, 18, unsigned int)
 #define IPMICTL_SET_MY_LUN_CMD          _IOR(IPMI_IOC_MAGIC, 19, unsigned int)
diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h
index ab0d0efbf240..3c7dbc6a0a70 100644
--- a/include/linux/ipv6.h
+++ b/include/linux/ipv6.h
@@ -193,6 +193,24 @@ struct inet6_skb_parm {
 
 #define IP6CB(skb)      ((struct inet6_skb_parm*)((skb)->cb))
 
+static inline int inet6_iif(const struct sk_buff *skb)
+{
+        return IP6CB(skb)->iif;
+}
+
+struct tcp6_request_sock {
+        struct tcp_request_sock req;
+        struct in6_addr         loc_addr;
+        struct in6_addr         rmt_addr;
+        struct sk_buff          *pktopts;
+        int                     iif;
+};
+
+static inline struct tcp6_request_sock *tcp6_rsk(const struct request_sock *sk)
+{
+        return (struct tcp6_request_sock *)sk;
+}
+
 /**
  * struct ipv6_pinfo - ipv6 private area
  *
@@ -295,6 +313,36 @@ static inline void inet_sk_copy_descendant(struct sock *sk_to,
 
 #define __ipv6_only_sock(sk)    (inet6_sk(sk)->ipv6only)
 #define ipv6_only_sock(sk)      ((sk)->sk_family == PF_INET6 && __ipv6_only_sock(sk))
+
+#include <linux/tcp.h>
+
+struct tcp6_timewait_sock {
+        struct tcp_timewait_sock tw_v6_sk;
+        struct in6_addr          tw_v6_daddr;
+        struct in6_addr          tw_v6_rcv_saddr;
+};
+
+static inline struct tcp6_timewait_sock *tcp6_twsk(const struct sock *sk)
+{
+        return (struct tcp6_timewait_sock *)sk;
+}
+
+static inline struct in6_addr *__tcp_v6_rcv_saddr(const struct sock *sk)
+{
+        return likely(sk->sk_state != TCP_TIME_WAIT) ?
+                &inet6_sk(sk)->rcv_saddr : &tcp6_twsk(sk)->tw_v6_rcv_saddr;
+}
+
+static inline struct in6_addr *tcp_v6_rcv_saddr(const struct sock *sk)
+{
+        return sk->sk_family == AF_INET6 ? __tcp_v6_rcv_saddr(sk) : NULL;
+}
+
+static inline int inet_v6_ipv6only(const struct sock *sk)
+{
+        return likely(sk->sk_state != TCP_TIME_WAIT) ?
+                ipv6_only_sock(sk) : inet_twsk(sk)->tw_ipv6only;
+}
 #else
 #define __ipv6_only_sock(sk)    0
 #define ipv6_only_sock(sk)      0
@@ -309,8 +357,19 @@ static inline struct raw6_sock *raw6_sk(const struct sock *sk)
         return NULL;
 }
 
-#endif
+#define __tcp_v6_rcv_saddr(__sk)        NULL
+#define tcp_v6_rcv_saddr(__sk)          NULL
+#define tcp_twsk_ipv6only(__sk)         0
+#define inet_v6_ipv6only(__sk)          0
+#endif /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */
 
-#endif
+#define INET6_MATCH(__sk, __saddr, __daddr, __ports, __dif)        \
+        (((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports))   && \
+         ((__sk)->sk_family             == AF_INET6)            && \
+         ipv6_addr_equal(&inet6_sk(__sk)->daddr, (__saddr))     && \
+         ipv6_addr_equal(&inet6_sk(__sk)->rcv_saddr, (__daddr)) && \
+         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
 
-#endif
+#endif /* __KERNEL__ */
+
+#endif /* _IPV6_H */
diff --git a/include/linux/irq.h b/include/linux/irq.h
index c3ff4d101667..69681c3b1f05 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -32,7 +32,12 @@
 #define IRQ_WAITING     32      /* IRQ not yet seen - for autodetection */
 #define IRQ_LEVEL       64      /* IRQ level triggered */
 #define IRQ_MASKED      128     /* IRQ masked - shouldn't be seen again */
-#define IRQ_PER_CPU     256     /* IRQ is per CPU */
+#if defined(ARCH_HAS_IRQ_PER_CPU)
+# define IRQ_PER_CPU    256     /* IRQ is per CPU */
+# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
+#else
+# define CHECK_IRQ_PER_CPU(var) 0
+#endif
 
 /*
  * Interrupt controller descriptor. This is all we need
@@ -47,6 +52,10 @@ struct hw_interrupt_type {
         void (*ack)(unsigned int irq);
         void (*end)(unsigned int irq);
         void (*set_affinity)(unsigned int irq, cpumask_t dest);
+        /* Currently used only by UML, might disappear one day.*/
+#ifdef CONFIG_IRQ_RELEASE_METHOD
+        void (*release)(unsigned int irq, void *dev_id);
+#endif
 };
 
 typedef struct hw_interrupt_type  hw_irq_controller;
@@ -67,24 +76,147 @@ typedef struct irq_desc {
         unsigned int irq_count;         /* For detecting broken interrupts */
         unsigned int irqs_unhandled;
         spinlock_t lock;
+#if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE)
+        unsigned int move_irq;          /* Flag need to re-target intr dest*/
+#endif
 } ____cacheline_aligned irq_desc_t;
 
 extern irq_desc_t irq_desc [NR_IRQS];
 
+/* Return a pointer to the irq descriptor for IRQ.  */
+static inline irq_desc_t *
+irq_descp (int irq)
+{
+        return irq_desc + irq;
+}
+
 #include <asm/hw_irq.h> /* the arch dependent stuff */
 
 extern int setup_irq(unsigned int irq, struct irqaction * new);
 
 #ifdef CONFIG_GENERIC_HARDIRQS
 extern cpumask_t irq_affinity[NR_IRQS];
+
+#ifdef CONFIG_SMP
+static inline void set_native_irq_info(int irq, cpumask_t mask)
+{
+        irq_affinity[irq] = mask;
+}
+#else
+static inline void set_native_irq_info(int irq, cpumask_t mask)
+{
+}
+#endif
+
+#ifdef CONFIG_SMP
+
+#if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE)
+extern cpumask_t pending_irq_cpumask[NR_IRQS];
+
+static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
+{
+        irq_desc_t *desc = irq_desc + irq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&desc->lock, flags);
+        desc->move_irq = 1;
+        pending_irq_cpumask[irq] = mask;
+        spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+static inline void
+move_native_irq(int irq)
+{
+        cpumask_t tmp;
+        irq_desc_t *desc = irq_descp(irq);
+
+        if (likely (!desc->move_irq))
+                return;
+
+        desc->move_irq = 0;
+
+        if (likely(cpus_empty(pending_irq_cpumask[irq])))
+                return;
+
+        if (!desc->handler->set_affinity)
+                return;
+
+        /* note - we hold the desc->lock */
+        cpus_and(tmp, pending_irq_cpumask[irq], cpu_online_map);
+
+        /*
+         * If there was a valid mask to work with, please
+         * do the disable, re-program, enable sequence.
+         * This is *not* particularly important for level triggered
+         * but in a edge trigger case, we might be setting rte
+         * when an active trigger is comming in. This could
+         * cause some ioapics to mal-function.
+         * Being paranoid i guess!
+         */
+        if (unlikely(!cpus_empty(tmp))) {
+                desc->handler->disable(irq);
+                desc->handler->set_affinity(irq,tmp);
+                desc->handler->enable(irq);
+        }
+        cpus_clear(pending_irq_cpumask[irq]);
+}
+
+#ifdef CONFIG_PCI_MSI
+/*
+ * Wonder why these are dummies?
+ * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
+ * counter part after translating the vector to irq info. We need to perform
+ * this operation on the real irq, when we dont use vector, i.e when
+ * pci_use_vector() is false.
+ */
+static inline void move_irq(int irq)
+{
+}
+
+static inline void set_irq_info(int irq, cpumask_t mask)
+{
+}
+
+#else // CONFIG_PCI_MSI
+
+static inline void move_irq(int irq)
+{
+        move_native_irq(irq);
+}
+
+static inline void set_irq_info(int irq, cpumask_t mask)
+{
+        set_native_irq_info(irq, mask);
+}
+#endif // CONFIG_PCI_MSI
+
+#else   // CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE
+
+#define move_irq(x)
+#define move_native_irq(x)
+#define set_pending_irq(x,y)
+static inline void set_irq_info(int irq, cpumask_t mask)
+{
+        set_native_irq_info(irq, mask);
+}
+
+#endif // CONFIG_GENERIC_PENDING_IRQ
+
+#else // CONFIG_SMP
+
+#define move_irq(x)
+#define move_native_irq(x)
+
+#endif // CONFIG_SMP
+
 extern int no_irq_affinity;
 extern int noirqdebug_setup(char *str);
 
 extern fastcall int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
-                                       struct irqaction *action);
+                                        struct irqaction *action);
 extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern void note_interrupt(unsigned int irq, irq_desc_t *desc, int action_ret);
-extern void report_bad_irq(unsigned int irq, irq_desc_t *desc, int action_ret);
+extern void note_interrupt(unsigned int irq, irq_desc_t *desc,
+                                        int action_ret, struct pt_regs *regs);
 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
 
 extern void init_irq_proc(void);
diff --git a/include/linux/isdn.h b/include/linux/isdn.h
index 862083eb58ab..53eaee96065b 100644
--- a/include/linux/isdn.h
+++ b/include/linux/isdn.h
@@ -150,7 +150,6 @@ typedef struct {
 #include <linux/errno.h>
 #include <linux/fs.h>
 #include <linux/major.h>
-#include <asm/segment.h>
 #include <asm/io.h>
 #include <linux/kernel.h>
 #include <linux/signal.h>
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index 593407e865b1..84321a4cac93 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -914,7 +914,6 @@ extern int	   journal_wipe       (journal_t *, int);
 extern int         journal_skip_recovery        (journal_t *);
 extern void        journal_update_superblock    (journal_t *, int);
 extern void        __journal_abort_hard (journal_t *);
-extern void        __journal_abort_soft (journal_t *, int);
 extern void        journal_abort      (journal_t *, int);
 extern int         journal_errno      (journal_t *);
 extern void        journal_ack_err    (journal_t *);
diff --git a/include/linux/jffs2_fs_sb.h b/include/linux/jffs2_fs_sb.h
index 4afc8d8c2e9e..1e21546622de 100644
--- a/include/linux/jffs2_fs_sb.h
+++ b/include/linux/jffs2_fs_sb.h
@@ -1,4 +1,4 @@
-/* $Id: jffs2_fs_sb.h,v 1.48 2004/11/20 10:41:12 dwmw2 Exp $ */
+/* $Id: jffs2_fs_sb.h,v 1.52 2005/05/19 16:12:17 gleixner Exp $ */
 
 #ifndef _JFFS2_FS_SB
 #define _JFFS2_FS_SB
@@ -14,7 +14,8 @@
 #include <linux/rwsem.h>
 
 #define JFFS2_SB_FLAG_RO 1
-#define JFFS2_SB_FLAG_MOUNTING 2
+#define JFFS2_SB_FLAG_SCANNING 2 /* Flash scanning is in progress */
+#define JFFS2_SB_FLAG_BUILDING 4 /* File system building is in progress */
 
 struct jffs2_inodirty;
 
@@ -31,7 +32,7 @@ struct jffs2_sb_info {
         unsigned int flags;
 
         struct task_struct *gc_task;    /* GC task struct */
-        struct semaphore gc_thread_start; /* GC thread start mutex */
+        struct completion gc_thread_start; /* GC thread start completion */
         struct completion gc_thread_exit; /* GC thread exit completion port */
 
         struct semaphore alloc_sem;     /* Used to protect all the following 
@@ -94,7 +95,7 @@ struct jffs2_sb_info {
            to an obsoleted node. I don't like this. Alternatives welcomed. */
         struct semaphore erase_free_sem;
 
-#if defined CONFIG_JFFS2_FS_NAND || defined CONFIG_JFFS2_FS_NOR_ECC
+#ifdef CONFIG_JFFS2_FS_WRITEBUFFER
         /* Write-behind buffer for NAND flash */
         unsigned char *wbuf;
         uint32_t wbuf_ofs;
diff --git a/include/linux/joystick.h b/include/linux/joystick.h
index b7e0ab622cd7..06b9af77eb7f 100644
--- a/include/linux/joystick.h
+++ b/include/linux/joystick.h
@@ -111,18 +111,35 @@ struct js_corr {
 #define JS_SET_ALL              8
 
 struct JS_DATA_TYPE {
-        int buttons;
-        int x;
-        int y;
+        __s32 buttons;
+        __s32 x;
+        __s32 y;
 };
 
-struct JS_DATA_SAVE_TYPE {
-        int JS_TIMEOUT;
-        int BUSY;
-        long JS_EXPIRETIME;
-        long JS_TIMELIMIT;
+struct JS_DATA_SAVE_TYPE_32 {
+        __s32 JS_TIMEOUT;
+        __s32 BUSY;
+        __s32 JS_EXPIRETIME;
+        __s32 JS_TIMELIMIT;
         struct JS_DATA_TYPE JS_SAVE;
         struct JS_DATA_TYPE JS_CORR;
 };
 
+struct JS_DATA_SAVE_TYPE_64 {
+        __s32 JS_TIMEOUT;
+        __s32 BUSY;
+        __s64 JS_EXPIRETIME;
+        __s64 JS_TIMELIMIT;
+        struct JS_DATA_TYPE JS_SAVE;
+        struct JS_DATA_TYPE JS_CORR;
+};
+
+#if BITS_PER_LONG == 64
+#define JS_DATA_SAVE_TYPE JS_DATA_SAVE_TYPE_64
+#elif BITS_PER_LONG == 32
+#define JS_DATA_SAVE_TYPE JS_DATA_SAVE_TYPE_32
+#else
+#error Unexpected BITS_PER_LONG
+#endif
+
 #endif /* _LINUX_JOYSTICK_H */
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index e25b97062ce1..687ba8c9973d 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -58,15 +58,23 @@ struct completion;
  * be biten later when the calling function happens to sleep when it is not
  * supposed to.
  */
+#ifdef CONFIG_PREEMPT_VOLUNTARY
+extern int cond_resched(void);
+# define might_resched() cond_resched()
+#else
+# define might_resched() do { } while (0)
+#endif
+
 #ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
-#define might_sleep() __might_sleep(__FILE__, __LINE__)
-#define might_sleep_if(cond) do { if (unlikely(cond)) might_sleep(); } while (0)
-void __might_sleep(char *file, int line);
+  void __might_sleep(char *file, int line);
+# define might_sleep() \
+        do { __might_sleep(__FILE__, __LINE__); might_resched(); } while (0)
 #else
-#define might_sleep() do {} while(0)
-#define might_sleep_if(cond) do {} while (0)
+# define might_sleep() do { might_resched(); } while (0)
 #endif
 
+#define might_sleep_if(cond) do { if (unlikely(cond)) might_sleep(); } while (0)
+
 #define abs(x) ({                               \
                 int __x = (x);                  \
                 (__x < 0) ? -__x : __x;         \
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
new file mode 100644
index 000000000000..c8468472aec0
--- /dev/null
+++ b/include/linux/kexec.h
@@ -0,0 +1,135 @@
+#ifndef LINUX_KEXEC_H
+#define LINUX_KEXEC_H
+
+#ifdef CONFIG_KEXEC
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/linkage.h>
+#include <linux/compat.h>
+#include <asm/kexec.h>
+
+/* Verify architecture specific macros are defined */
+
+#ifndef KEXEC_SOURCE_MEMORY_LIMIT
+#error KEXEC_SOURCE_MEMORY_LIMIT not defined
+#endif
+
+#ifndef KEXEC_DESTINATION_MEMORY_LIMIT
+#error KEXEC_DESTINATION_MEMORY_LIMIT not defined
+#endif
+
+#ifndef KEXEC_CONTROL_MEMORY_LIMIT
+#error KEXEC_CONTROL_MEMORY_LIMIT not defined
+#endif
+
+#ifndef KEXEC_CONTROL_CODE_SIZE
+#error KEXEC_CONTROL_CODE_SIZE not defined
+#endif
+
+#ifndef KEXEC_ARCH
+#error KEXEC_ARCH not defined
+#endif
+
+/*
+ * This structure is used to hold the arguments that are used when loading
+ * kernel binaries.
+ */
+
+typedef unsigned long kimage_entry_t;
+#define IND_DESTINATION  0x1
+#define IND_INDIRECTION  0x2
+#define IND_DONE         0x4
+#define IND_SOURCE       0x8
+
+#define KEXEC_SEGMENT_MAX 8
+struct kexec_segment {
+        void __user *buf;
+        size_t bufsz;
+        unsigned long mem;      /* User space sees this as a (void *) ... */
+        size_t memsz;
+};
+
+#ifdef CONFIG_COMPAT
+struct compat_kexec_segment {
+        compat_uptr_t buf;
+        compat_size_t bufsz;
+        compat_ulong_t mem;     /* User space sees this as a (void *) ... */
+        compat_size_t memsz;
+};
+#endif
+
+struct kimage {
+        kimage_entry_t head;
+        kimage_entry_t *entry;
+        kimage_entry_t *last_entry;
+
+        unsigned long destination;
+
+        unsigned long start;
+        struct page *control_code_page;
+
+        unsigned long nr_segments;
+        struct kexec_segment segment[KEXEC_SEGMENT_MAX];
+
+        struct list_head control_pages;
+        struct list_head dest_pages;
+        struct list_head unuseable_pages;
+
+        /* Address of next control page to allocate for crash kernels. */
+        unsigned long control_page;
+
+        /* Flags to indicate special processing */
+        unsigned int type : 1;
+#define KEXEC_TYPE_DEFAULT 0
+#define KEXEC_TYPE_CRASH   1
+};
+
+
+
+/* kexec interface functions */
+extern NORET_TYPE void machine_kexec(struct kimage *image) ATTRIB_NORET;
+extern int machine_kexec_prepare(struct kimage *image);
+extern void machine_kexec_cleanup(struct kimage *image);
+extern asmlinkage long sys_kexec_load(unsigned long entry,
+                                        unsigned long nr_segments,
+                                        struct kexec_segment __user *segments,
+                                        unsigned long flags);
+#ifdef CONFIG_COMPAT
+extern asmlinkage long compat_sys_kexec_load(unsigned long entry,
+                                unsigned long nr_segments,
+                                struct compat_kexec_segment __user *segments,
+                                unsigned long flags);
+#endif
+extern struct page *kimage_alloc_control_pages(struct kimage *image,
+                                                unsigned int order);
+extern void crash_kexec(struct pt_regs *);
+int kexec_should_crash(struct task_struct *);
+extern struct kimage *kexec_image;
+
+#define KEXEC_ON_CRASH  0x00000001
+#define KEXEC_ARCH_MASK 0xffff0000
+
+/* These values match the ELF architecture values.
+ * Unless there is a good reason that should continue to be the case.
+ */
+#define KEXEC_ARCH_DEFAULT ( 0 << 16)
+#define KEXEC_ARCH_386     ( 3 << 16)
+#define KEXEC_ARCH_X86_64  (62 << 16)
+#define KEXEC_ARCH_PPC     (20 << 16)
+#define KEXEC_ARCH_PPC64   (21 << 16)
+#define KEXEC_ARCH_IA_64   (50 << 16)
+#define KEXEC_ARCH_S390    (22 << 16)
+
+#define KEXEC_FLAGS    (KEXEC_ON_CRASH)  /* List of defined/legal kexec flags */
+
+/* Location of a reserved region to hold the crash kernel.
+ */
+extern struct resource crashk_res;
+
+#else /* !CONFIG_KEXEC */
+struct pt_regs;
+struct task_struct;
+static inline void crash_kexec(struct pt_regs *regs) { }
+static inline int kexec_should_crash(struct task_struct *p) { return 0; }
+#endif /* CONFIG_KEXEC */
+#endif /* LINUX_KEXEC_H */
diff --git a/include/linux/key-ui.h b/include/linux/key-ui.h
index 60cc7b762e78..cc326174a808 100644
--- a/include/linux/key-ui.h
+++ b/include/linux/key-ui.h
@@ -1,4 +1,4 @@
-/* key-ui.h: key userspace interface stuff for use by keyfs
+/* key-ui.h: key userspace interface stuff
  *
  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
@@ -31,8 +31,10 @@ extern spinlock_t key_serial_lock;
  * subscribed
  */
 struct keyring_list {
-        unsigned        maxkeys;        /* max keys this list can hold */
-        unsigned        nkeys;          /* number of keys currently held */
+        struct rcu_head rcu;            /* RCU deletion hook */
+        unsigned short  maxkeys;        /* max keys this list can hold */
+        unsigned short  nkeys;          /* number of keys currently held */
+        unsigned short  delkey;         /* key to be unlinked by RCU */
         struct key      *keys[0];
 };
 
@@ -82,8 +84,45 @@ static inline int key_any_permission(const struct key *key, key_perm_t perm)
         return kperm != 0;
 }
 
+static inline int key_task_groups_search(struct task_struct *tsk, gid_t gid)
+{
+        int ret;
+
+        task_lock(tsk);
+        ret = groups_search(tsk->group_info, gid);
+        task_unlock(tsk);
+        return ret;
+}
+
+static inline int key_task_permission(const struct key *key,
+                                      struct task_struct *context,
+                                      key_perm_t perm)
+{
+        key_perm_t kperm;
+
+        if (key->uid == context->fsuid) {
+                kperm = key->perm >> 16;
+        }
+        else if (key->gid != -1 &&
+                 key->perm & KEY_GRP_ALL && (
+                         key->gid == context->fsgid ||
+                         key_task_groups_search(context, key->gid)
+                         )
+                 ) {
+                kperm = key->perm >> 8;
+        }
+        else {
+                kperm = key->perm;
+        }
+
+        kperm = kperm & perm & KEY_ALL;
+
+        return kperm == perm;
+
+}
 
-extern struct key *lookup_user_key(key_serial_t id, int create, int part,
+extern struct key *lookup_user_key(struct task_struct *context,
+                                   key_serial_t id, int create, int partial,
                                    key_perm_t perm);
 
 extern long join_session_keyring(const char *name);
diff --git a/include/linux/key.h b/include/linux/key.h
index 6aa46d0e812f..970bbd916cf4 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -18,7 +18,7 @@
 #include <linux/types.h>
 #include <linux/list.h>
 #include <linux/rbtree.h>
-#include <linux/spinlock.h>
+#include <linux/rcupdate.h>
 #include <asm/atomic.h>
 
 #ifdef __KERNEL__
@@ -78,7 +78,6 @@ struct key {
         key_serial_t            serial;         /* key serial number */
         struct rb_node          serial_node;
         struct key_type         *type;          /* type of key */
-        rwlock_t                lock;           /* examination vs change lock */
         struct rw_semaphore     sem;            /* change vs change sem */
         struct key_user         *user;          /* owner of this key */
         time_t                  expiry;         /* time at which key expires (or 0) */
@@ -86,14 +85,10 @@ struct key {
         gid_t                   gid;
         key_perm_t              perm;           /* access permissions */
         unsigned short          quotalen;       /* length added to quota */
-        unsigned short          datalen;        /* payload data length */
-        unsigned short          flags;          /* status flags (change with lock writelocked) */
-#define KEY_FLAG_INSTANTIATED   0x00000001      /* set if key has been instantiated */
-#define KEY_FLAG_DEAD           0x00000002      /* set if key type has been deleted */
-#define KEY_FLAG_REVOKED        0x00000004      /* set if key had been revoked */
-#define KEY_FLAG_IN_QUOTA       0x00000008      /* set if key consumes quota */
-#define KEY_FLAG_USER_CONSTRUCT 0x00000010      /* set if key is being constructed in userspace */
-#define KEY_FLAG_NEGATIVE       0x00000020      /* set if key is negative */
+        unsigned short          datalen;        /* payload data length
+                                                 * - may not match RCU dereferenced payload
+                                                 * - payload should contain own length
+                                                 */
 
 #ifdef KEY_DEBUGGING
         unsigned                magic;
@@ -101,6 +96,14 @@ struct key {
 #define KEY_DEBUG_MAGIC_X       0xf8e9dacbu
 #endif
 
+        unsigned long           flags;          /* status flags (change with bitops) */
+#define KEY_FLAG_INSTANTIATED   0       /* set if key has been instantiated */
+#define KEY_FLAG_DEAD           1       /* set if key type has been deleted */
+#define KEY_FLAG_REVOKED        2       /* set if key had been revoked */
+#define KEY_FLAG_IN_QUOTA       3       /* set if key consumes quota */
+#define KEY_FLAG_USER_CONSTRUCT 4       /* set if key is being constructed in userspace */
+#define KEY_FLAG_NEGATIVE       5       /* set if key is negative */
+
         /* the description string
          * - this is used to match a key against search criteria
          * - this should be a printable string
@@ -196,10 +199,12 @@ extern int key_payload_reserve(struct key *key, size_t datalen);
 extern int key_instantiate_and_link(struct key *key,
                                     const void *data,
                                     size_t datalen,
-                                    struct key *keyring);
+                                    struct key *keyring,
+                                    struct key *instkey);
 extern int key_negate_and_link(struct key *key,
                                unsigned timeout,
-                               struct key *keyring);
+                               struct key *keyring,
+                               struct key *instkey);
 extern void key_revoke(struct key *key);
 extern void key_put(struct key *key);
 
@@ -242,14 +247,13 @@ extern struct key *keyring_search(struct key *keyring,
                                   struct key_type *type,
                                   const char *description);
 
-extern struct key *search_process_keyrings(struct key_type *type,
-                                           const char *description);
-
 extern int keyring_add_key(struct key *keyring,
                            struct key *key);
 
 extern struct key *key_lookup(key_serial_t id);
 
+extern void keyring_replace_payload(struct key *key, void *replacement);
+
 #define key_serial(key) ((key) ? (key)->serial : 0)
 
 /*
@@ -268,14 +272,22 @@ extern void key_fsuid_changed(struct task_struct *tsk);
 extern void key_fsgid_changed(struct task_struct *tsk);
 extern void key_init(void);
 
+#define __install_session_keyring(tsk, keyring)                 \
+({                                                              \
+        struct key *old_session = tsk->signal->session_keyring; \
+        tsk->signal->session_keyring = keyring;                 \
+        old_session;                                            \
+})
+
 #else /* CONFIG_KEYS */
 
 #define key_validate(k)                 0
 #define key_serial(k)                   0
-#define key_get(k)                      NULL
+#define key_get(k)                      ({ NULL; })
 #define key_put(k)                      do { } while(0)
 #define alloc_uid_keyring(u)            0
 #define switch_uid_keyring(u)           do { } while(0)
+#define __install_session_keyring(t, k) ({ NULL; })
 #define copy_keys(f,t)                  0
 #define copy_thread_group_keys(t)       0
 #define exit_keys(t)                    do { } while(0)
diff --git a/include/linux/keyctl.h b/include/linux/keyctl.h
index 381dedc370a3..8d7c59a29e09 100644
--- a/include/linux/keyctl.h
+++ b/include/linux/keyctl.h
@@ -20,6 +20,16 @@
 #define KEY_SPEC_USER_SESSION_KEYRING   -5      /* - key ID for UID-session keyring */
 #define KEY_SPEC_GROUP_KEYRING          -6      /* - key ID for GID-specific keyring */
 
+/* request-key default keyrings */
+#define KEY_REQKEY_DEFL_NO_CHANGE               -1
+#define KEY_REQKEY_DEFL_DEFAULT                 0
+#define KEY_REQKEY_DEFL_THREAD_KEYRING          1
+#define KEY_REQKEY_DEFL_PROCESS_KEYRING         2
+#define KEY_REQKEY_DEFL_SESSION_KEYRING         3
+#define KEY_REQKEY_DEFL_USER_KEYRING            4
+#define KEY_REQKEY_DEFL_USER_SESSION_KEYRING    5
+#define KEY_REQKEY_DEFL_GROUP_KEYRING           6
+
 /* keyctl commands */
 #define KEYCTL_GET_KEYRING_ID           0       /* ask for a keyring's ID */
 #define KEYCTL_JOIN_SESSION_KEYRING     1       /* join or start named session keyring */
@@ -35,5 +45,6 @@
 #define KEYCTL_READ                     11      /* read a key or keyring's contents */
 #define KEYCTL_INSTANTIATE              12      /* instantiate a partially constructed key */
 #define KEYCTL_NEGATE                   13      /* negate a partially constructed key */
+#define KEYCTL_SET_REQKEY_KEYRING       14      /* set default request-key keyring */
 
 #endif /*  _LINUX_KEYCTL_H */
diff --git a/include/linux/klist.h b/include/linux/klist.h
new file mode 100644
index 000000000000..74071254c9d3
--- /dev/null
+++ b/include/linux/klist.h
@@ -0,0 +1,61 @@
+/*
+ *      klist.h - Some generic list helpers, extending struct list_head a bit.
+ *
+ *      Implementations are found in lib/klist.c
+ *
+ *
+ *      Copyright (C) 2005 Patrick Mochel
+ *
+ *      This file is rleased under the GPL v2.
+ */
+
+#ifndef _LINUX_KLIST_H
+#define _LINUX_KLIST_H
+
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/kref.h>
+#include <linux/list.h>
+
+struct klist_node;
+struct klist {
+        spinlock_t              k_lock;
+        struct list_head        k_list;
+        void                    (*get)(struct klist_node *);
+        void                    (*put)(struct klist_node *);
+};
+
+
+extern void klist_init(struct klist * k, void (*get)(struct klist_node *),
+                       void (*put)(struct klist_node *));
+
+struct klist_node {
+        struct klist            * n_klist;
+        struct list_head        n_node;
+        struct kref             n_ref;
+        struct completion       n_removed;
+};
+
+extern void klist_add_tail(struct klist_node * n, struct klist * k);
+extern void klist_add_head(struct klist_node * n, struct klist * k);
+
+extern void klist_del(struct klist_node * n);
+extern void klist_remove(struct klist_node * n);
+
+extern int klist_node_attached(struct klist_node * n);
+
+
+struct klist_iter {
+        struct klist            * i_klist;
+        struct list_head        * i_head;
+        struct klist_node       * i_cur;
+};
+
+
+extern void klist_iter_init(struct klist * k, struct klist_iter * i);
+extern void klist_iter_init_node(struct klist * k, struct klist_iter * i, 
+                                 struct klist_node * n);
+extern void klist_iter_exit(struct klist_iter * i);
+extern struct klist_node * klist_next(struct klist_iter * i);
+
+#endif
diff --git a/include/linux/kmod.h b/include/linux/kmod.h
index 95d0e4b0814d..e4a231549407 100644
--- a/include/linux/kmod.h
+++ b/include/linux/kmod.h
@@ -19,6 +19,7 @@
  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/stddef.h>
 #include <linux/config.h>
 #include <linux/errno.h>
 #include <linux/compiler.h>
@@ -34,7 +35,17 @@ static inline int request_module(const char * name, ...) { return -ENOSYS; }
 #endif
 
 #define try_then_request_module(x, mod...) ((x) ?: (request_module(mod), (x)))
-extern int call_usermodehelper(char *path, char *argv[], char *envp[], int wait);
+
+struct key;
+extern int call_usermodehelper_keys(char *path, char *argv[], char *envp[],
+                                    struct key *session_keyring, int wait);
+
+static inline int
+call_usermodehelper(char *path, char **argv, char **envp, int wait)
+{
+        return call_usermodehelper_keys(path, argv, envp, NULL, wait);
+}
+
 extern void usermodehelper_init(void);
 
 #endif /* __LINUX_KMOD_H__ */
diff --git a/include/linux/kobject.h b/include/linux/kobject.h
index 765d660d3bea..3b22304f12fd 100644
--- a/include/linux/kobject.h
+++ b/include/linux/kobject.h
@@ -33,7 +33,7 @@
 extern u64 hotplug_seqnum;
 
 struct kobject {
-        char                    * k_name;
+        const char              * k_name;
         char                    name[KOBJ_NAME_LEN];
         struct kref             kref;
         struct list_head        entry;
@@ -46,7 +46,7 @@ struct kobject {
 extern int kobject_set_name(struct kobject *, const char *, ...)
         __attribute__((format(printf,2,3)));
 
-static inline char * kobject_name(struct kobject * kobj)
+static inline const char * kobject_name(const struct kobject * kobj)
 {
         return kobj->k_name;
 }
@@ -57,7 +57,7 @@ extern void kobject_cleanup(struct kobject *);
 extern int kobject_add(struct kobject *);
 extern void kobject_del(struct kobject *);
 
-extern int kobject_rename(struct kobject *, char *new_name);
+extern int kobject_rename(struct kobject *, const char *new_name);
 
 extern int kobject_register(struct kobject *);
 extern void kobject_unregister(struct kobject *);
@@ -94,7 +94,7 @@ struct kobj_type {
  */
 struct kset_hotplug_ops {
         int (*filter)(struct kset *kset, struct kobject *kobj);
-        char *(*name)(struct kset *kset, struct kobject *kobj);
+        const char *(*name)(struct kset *kset, struct kobject *kobj);
         int (*hotplug)(struct kset *kset, struct kobject *kobj, char **envp,
                         int num_envp, char *buffer, int buffer_size);
 };
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 99ddba5a4e00..e30afdca7917 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -25,27 +25,48 @@
  *              Rusty Russell).
  * 2004-July    Suparna Bhattacharya <suparna@in.ibm.com> added jumper probes
  *              interface to access function arguments.
+ * 2005-May     Hien Nguyen <hien@us.ibm.com> and Jim Keniston
+ *              <jkenisto@us.ibm.com>  and Prasanna S Panchamukhi
+ *              <prasanna@in.ibm.com> added function-return probes.
  */
 #include <linux/config.h>
 #include <linux/list.h>
 #include <linux/notifier.h>
 #include <linux/smp.h>
+
 #include <asm/kprobes.h>
 
+/* kprobe_status settings */
+#define KPROBE_HIT_ACTIVE       0x00000001
+#define KPROBE_HIT_SS           0x00000002
+#define KPROBE_REENTER          0x00000004
+#define KPROBE_HIT_SSDONE       0x00000008
+
+/* Attach to insert probes on any functions which should be ignored*/
+#define __kprobes       __attribute__((__section__(".kprobes.text")))
+
 struct kprobe;
 struct pt_regs;
+struct kretprobe;
+struct kretprobe_instance;
 typedef int (*kprobe_pre_handler_t) (struct kprobe *, struct pt_regs *);
 typedef int (*kprobe_break_handler_t) (struct kprobe *, struct pt_regs *);
 typedef void (*kprobe_post_handler_t) (struct kprobe *, struct pt_regs *,
                                        unsigned long flags);
 typedef int (*kprobe_fault_handler_t) (struct kprobe *, struct pt_regs *,
                                        int trapnr);
+typedef int (*kretprobe_handler_t) (struct kretprobe_instance *,
+                                    struct pt_regs *);
+
 struct kprobe {
         struct hlist_node hlist;
 
         /* list of kprobes for multi-handler support */
         struct list_head list;
 
+        /*count the number of times this probe was temporarily disarmed */
+        unsigned long nmissed;
+
         /* location of the probe point */
         kprobe_opcode_t *addr;
 
@@ -85,6 +106,41 @@ struct jprobe {
         kprobe_opcode_t *entry; /* probe handling code to jump to */
 };
 
+#ifdef ARCH_SUPPORTS_KRETPROBES
+extern void arch_prepare_kretprobe(struct kretprobe *rp, struct pt_regs *regs);
+#else /* ARCH_SUPPORTS_KRETPROBES */
+static inline void arch_prepare_kretprobe(struct kretprobe *rp,
+                                        struct pt_regs *regs)
+{
+}
+#endif /* ARCH_SUPPORTS_KRETPROBES */
+/*
+ * Function-return probe -
+ * Note:
+ * User needs to provide a handler function, and initialize maxactive.
+ * maxactive - The maximum number of instances of the probed function that
+ * can be active concurrently.
+ * nmissed - tracks the number of times the probed function's return was
+ * ignored, due to maxactive being too low.
+ *
+ */
+struct kretprobe {
+        struct kprobe kp;
+        kretprobe_handler_t handler;
+        int maxactive;
+        int nmissed;
+        struct hlist_head free_instances;
+        struct hlist_head used_instances;
+};
+
+struct kretprobe_instance {
+        struct hlist_node uflist; /* either on free list or used list */
+        struct hlist_node hlist;
+        struct kretprobe *rp;
+        kprobe_opcode_t *ret_addr;
+        struct task_struct *task;
+};
+
 #ifdef CONFIG_KPROBES
 /* Locks kprobe: irq must be disabled */
 void lock_kprobes(void);
@@ -99,11 +155,17 @@ static inline int kprobe_running(void)
 
 extern int arch_prepare_kprobe(struct kprobe *p);
 extern void arch_copy_kprobe(struct kprobe *p);
+extern void arch_arm_kprobe(struct kprobe *p);
+extern void arch_disarm_kprobe(struct kprobe *p);
 extern void arch_remove_kprobe(struct kprobe *p);
+extern int arch_init_kprobes(void);
 extern void show_registers(struct pt_regs *regs);
+extern kprobe_opcode_t *get_insn_slot(void);
+extern void free_insn_slot(kprobe_opcode_t *slot);
 
 /* Get the kprobe at this addr (if any).  Must have called lock_kprobes */
 struct kprobe *get_kprobe(void *addr);
+struct hlist_head * kretprobe_inst_table_head(struct task_struct *tsk);
 
 int register_kprobe(struct kprobe *p);
 void unregister_kprobe(struct kprobe *p);
@@ -113,7 +175,14 @@ int register_jprobe(struct jprobe *p);
 void unregister_jprobe(struct jprobe *p);
 void jprobe_return(void);
 
-#else
+int register_kretprobe(struct kretprobe *rp);
+void unregister_kretprobe(struct kretprobe *rp);
+
+struct kretprobe_instance *get_free_rp_inst(struct kretprobe *rp);
+void add_rp_inst(struct kretprobe_instance *ri);
+void kprobe_flush_task(struct task_struct *tk);
+void recycle_rp_inst(struct kretprobe_instance *ri);
+#else /* CONFIG_KPROBES */
 static inline int kprobe_running(void)
 {
         return 0;
@@ -135,5 +204,15 @@ static inline void unregister_jprobe(struct jprobe *p)
 static inline void jprobe_return(void)
 {
 }
-#endif
+static inline int register_kretprobe(struct kretprobe *rp)
+{
+        return -ENOSYS;
+}
+static inline void unregister_kretprobe(struct kretprobe *rp)
+{
+}
+static inline void kprobe_flush_task(struct task_struct *tk)
+{
+}
+#endif                          /* CONFIG_KPROBES */
 #endif                          /* _LINUX_KPROBES_H */
diff --git a/include/linux/libata.h b/include/linux/libata.h
index b009f801e7c5..022105c745fc 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -1,23 +1,26 @@
 /*
-   Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
-   Copyright 2003-2004 Jeff Garzik
-
-   The contents of this file are subject to the Open
-   Software License version 1.1 that can be found at
-   http://www.opensource.org/licenses/osl-1.1.txt and is included herein
-   by reference.
-
-   Alternatively, the contents of this file may be used under the terms
-   of the GNU General Public License version 2 (the "GPL") as distributed
-   in the kernel source COPYING file, in which case the provisions of
-   the GPL are applicable instead of the above.  If you wish to allow
-   the use of your version of this file only under the terms of the
-   GPL and not to allow others to use your version of this file under
-   the OSL, indicate your decision by deleting the provisions above and
-   replace them with the notice and other provisions required by the GPL.
-   If you do not delete the provisions above, a recipient may use your
-   version of this file under either the OSL or the GPL.
-
+ *  Copyright 2003-2005 Red Hat, Inc.  All rights reserved.
+ *  Copyright 2003-2005 Jeff Garzik
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ *  libata documentation is available via 'make {ps|pdf}docs',
+ *  as Documentation/DocBook/libata.*
+ *
  */
 
 #ifndef __LINUX_LIBATA_H__
@@ -37,7 +40,6 @@
 #undef ATA_VERBOSE_DEBUG        /* yet more debugging output */
 #undef ATA_IRQ_TRAP             /* define to ack screaming irqs */
 #undef ATA_NDEBUG               /* define to disable quick runtime checks */
-#undef ATA_ENABLE_ATAPI         /* define to enable ATAPI support */
 #undef ATA_ENABLE_PATA          /* define to enable PATA support in some
                                  * low-level drivers */
 #undef ATAPI_ENABLE_DMADIR      /* enables ATAPI DMADIR bridge support */
@@ -113,6 +115,8 @@ enum {
         ATA_FLAG_MMIO           = (1 << 6), /* use MMIO, not PIO */
         ATA_FLAG_SATA_RESET     = (1 << 7), /* use COMRESET */
         ATA_FLAG_PIO_DMA        = (1 << 8), /* PIO cmds via DMA */
+        ATA_FLAG_NOINTR         = (1 << 9), /* FIXME: Remove this once
+                                             * proper HSM is in place. */
 
         ATA_QCFLAG_ACTIVE       = (1 << 1), /* cmd not yet ack'd to scsi lyer */
         ATA_QCFLAG_SG           = (1 << 3), /* have s/g table? */
@@ -363,7 +367,7 @@ struct ata_port_operations {
 
         void (*host_stop) (struct ata_host_set *host_set);
 
-        void (*bmdma_stop) (struct ata_port *ap);
+        void (*bmdma_stop) (struct ata_queued_cmd *qc);
         u8   (*bmdma_status) (struct ata_port *ap);
 };
 
@@ -421,9 +425,10 @@ extern void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
 extern unsigned int ata_dev_classify(struct ata_taskfile *tf);
 extern void ata_dev_id_string(u16 *id, unsigned char *s,
                               unsigned int ofs, unsigned int len);
+extern void ata_dev_config(struct ata_port *ap, unsigned int i);
 extern void ata_bmdma_setup (struct ata_queued_cmd *qc);
 extern void ata_bmdma_start (struct ata_queued_cmd *qc);
-extern void ata_bmdma_stop(struct ata_port *ap);
+extern void ata_bmdma_stop(struct ata_queued_cmd *qc);
 extern u8   ata_bmdma_status(struct ata_port *ap);
 extern void ata_bmdma_irq_clear(struct ata_port *ap);
 extern void ata_qc_complete(struct ata_queued_cmd *qc, u8 drv_stat);
@@ -444,6 +449,7 @@ struct pci_bits {
         unsigned long           val;
 };
 
+extern void ata_pci_host_stop (struct ata_host_set *host_set);
 extern struct ata_probe_ent *
 ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port);
 extern int pci_test_config_bits(struct pci_dev *pdev, struct pci_bits *bits);
@@ -643,7 +649,7 @@ static inline void scr_write(struct ata_port *ap, unsigned int reg, u32 val)
         ap->ops->scr_write(ap, reg, val);
 }
 
-static inline void scr_write_flush(struct ata_port *ap, unsigned int reg, 
+static inline void scr_write_flush(struct ata_port *ap, unsigned int reg,
                                    u32 val)
 {
         ap->ops->scr_write(ap, reg, val);
diff --git a/include/linux/libps2.h b/include/linux/libps2.h
index 923bdbc6d9e4..a710bddda4eb 100644
--- a/include/linux/libps2.h
+++ b/include/linux/libps2.h
@@ -41,6 +41,7 @@ struct ps2dev {
 
 void ps2_init(struct ps2dev *ps2dev, struct serio *serio);
 int ps2_sendbyte(struct ps2dev *ps2dev, unsigned char byte, int timeout);
+void ps2_drain(struct ps2dev *ps2dev, int maxbytes, int timeout);
 int ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command);
 int ps2_schedule_command(struct ps2dev *ps2dev, unsigned char *param, int command);
 int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data);
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 338f7795d8a0..147eb01e0d4b 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -33,6 +33,13 @@
   ALIGN; \
   name:
 
+#define KPROBE_ENTRY(name) \
+  .section .kprobes.text, "ax"; \
+  .globl name; \
+  ALIGN; \
+  name:
+
+
 #endif
 
 #define NORET_TYPE    /**/
diff --git a/include/linux/list.h b/include/linux/list.h
index 399b51d17218..e6ec59682274 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -185,7 +185,7 @@ static inline void list_del(struct list_head *entry)
  * list_for_each_entry_rcu().
  *
  * Note that the caller is not permitted to immediately free
- * the newly deleted entry.  Instead, either synchronize_kernel()
+ * the newly deleted entry.  Instead, either synchronize_rcu()
  * or call_rcu() must be used to defer freeing until an RCU
  * grace period has elapsed.
  */
@@ -419,6 +419,20 @@ static inline void list_splice_init(struct list_head *list,
              pos = n, n = list_entry(n->member.next, typeof(*n), member))
 
 /**
+ * list_for_each_entry_safe_continue -  iterate over list of given type
+ *                      continuing after existing point safe against removal of list entry
+ * @pos:        the type * to use as a loop counter.
+ * @n:          another type * to use as temporary storage
+ * @head:       the head for your list.
+ * @member:     the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe_continue(pos, n, head, member)                 \
+        for (pos = list_entry(pos->member.next, typeof(*pos), member),          \
+                n = list_entry(pos->member.next, typeof(*pos), member);         \
+             &pos->member != (head);                                            \
+             pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
  * list_for_each_rcu    -       iterate over an rcu-protected list
  * @pos:        the &struct list_head to use as a loop counter.
  * @head:       the head for your list.
@@ -620,6 +634,57 @@ static inline void hlist_add_after(struct hlist_node *n,
                 next->next->pprev  = &next->next;
 }
 
+/**
+ * hlist_add_before_rcu - adds the specified element to the specified hlist
+ * before the specified node while permitting racing traversals.
+ * @n: the new element to add to the hash list.
+ * @next: the existing element to add the new element before.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.
+ */
+static inline void hlist_add_before_rcu(struct hlist_node *n,
+                                        struct hlist_node *next)
+{
+        n->pprev = next->pprev;
+        n->next = next;
+        smp_wmb();
+        next->pprev = &n->next;
+        *(n->pprev) = n;
+}
+
+/**
+ * hlist_add_after_rcu - adds the specified element to the specified hlist
+ * after the specified node while permitting racing traversals.
+ * @prev: the existing element to add the new element after.
+ * @n: the new element to add to the hash list.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_add_head_rcu()
+ * or hlist_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_for_each_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.
+ */
+static inline void hlist_add_after_rcu(struct hlist_node *prev,
+                                       struct hlist_node *n)
+{
+        n->next = prev->next;
+        n->pprev = &prev->next;
+        smp_wmb();
+        prev->next = n;
+        if (n->next)
+                n->next->pprev = &n->next;
+}
+
 #define hlist_entry(ptr, type, member) container_of(ptr,type,member)
 
 #define hlist_for_each(pos, head) \
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index 0d9d22578212..16d4e5a08e1d 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -72,6 +72,8 @@ struct nlm_lockowner {
         uint32_t pid;
 };
 
+struct nlm_wait;
+
 /*
  * Memory chunk for NLM client RPC request.
  */
@@ -81,6 +83,7 @@ struct nlm_rqst {
         struct nlm_host *       a_host;         /* host handle */
         struct nlm_args         a_args;         /* arguments */
         struct nlm_res          a_res;          /* result */
+        struct nlm_wait *       a_block;
         char                    a_owner[NLMCLNT_OHSIZE];
 };
 
@@ -142,7 +145,9 @@ extern unsigned long		nlmsvc_timeout;
  * Lockd client functions
  */
 struct nlm_rqst * nlmclnt_alloc_call(void);
-int               nlmclnt_block(struct nlm_host *, struct file_lock *, u32 *);
+int               nlmclnt_prepare_block(struct nlm_rqst *req, struct nlm_host *host, struct file_lock *fl);
+void              nlmclnt_finish_block(struct nlm_rqst *req);
+long              nlmclnt_block(struct nlm_rqst *req, long timeout);
 int               nlmclnt_cancel(struct nlm_host *, struct file_lock *);
 u32               nlmclnt_grant(struct nlm_lock *);
 void              nlmclnt_recovery(struct nlm_host *, u32);
diff --git a/include/linux/loop.h b/include/linux/loop.h
index 8220d9c9da00..53fa51595443 100644
--- a/include/linux/loop.h
+++ b/include/linux/loop.h
@@ -61,7 +61,7 @@ struct loop_device {
         struct semaphore        lo_sem;
         struct semaphore        lo_ctl_mutex;
         struct semaphore        lo_bh_mutex;
-        atomic_t                lo_pending;
+        int                     lo_pending;
 
         request_queue_t         *lo_queue;
 };
diff --git a/include/linux/major.h b/include/linux/major.h
index 4b62c42b842c..e36a46702d94 100644
--- a/include/linux/major.h
+++ b/include/linux/major.h
@@ -100,6 +100,7 @@
 #define I2O_MAJOR               80      /* 80->87 */
 
 #define SHMIQ_MAJOR             85   /* Linux/mips, SGI /dev/shmiq */
+#define SCSI_CHANGER_MAJOR      86
 
 #define IDE6_MAJOR              88
 #define IDE7_MAJOR              89
diff --git a/include/linux/mbcache.h b/include/linux/mbcache.h
index 8e5a10410a30..9263d2db2d67 100644
--- a/include/linux/mbcache.h
+++ b/include/linux/mbcache.h
@@ -29,7 +29,7 @@ struct mb_cache_op {
 
 struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t,
                                   int, int);
-void mb_cache_shrink(struct mb_cache *, struct block_device *);
+void mb_cache_shrink(struct block_device *);
 void mb_cache_destroy(struct mb_cache *);
 
 /* Functions on cache entries */
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 8480aef10e62..94a46f38c532 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -150,6 +150,9 @@ void mpol_free_shared_policy(struct shared_policy *p);
 struct mempolicy *mpol_shared_policy_lookup(struct shared_policy *sp,
                                             unsigned long idx);
 
+struct mempolicy *get_vma_policy(struct task_struct *task,
+                        struct vm_area_struct *vma, unsigned long addr);
+
 extern void numa_default_policy(void);
 extern void numa_policy_init(void);
 
diff --git a/include/linux/mempool.h b/include/linux/mempool.h
index 4a36edf1c974..796220ce47cc 100644
--- a/include/linux/mempool.h
+++ b/include/linux/mempool.h
@@ -20,9 +20,14 @@ typedef struct mempool_s {
         mempool_free_t *free;
         wait_queue_head_t wait;
 } mempool_t;
-extern mempool_t * mempool_create(int min_nr, mempool_alloc_t *alloc_fn,
-                                 mempool_free_t *free_fn, void *pool_data);
-extern int mempool_resize(mempool_t *pool, int new_min_nr, unsigned int __nocast gfp_mask);
+
+extern mempool_t *mempool_create(int min_nr, mempool_alloc_t *alloc_fn,
+                        mempool_free_t *free_fn, void *pool_data);
+extern mempool_t *mempool_create_node(int min_nr, mempool_alloc_t *alloc_fn,
+                        mempool_free_t *free_fn, void *pool_data, int nid);
+
+extern int mempool_resize(mempool_t *pool, int new_min_nr,
+                        unsigned int __nocast gfp_mask);
 extern void mempool_destroy(mempool_t *pool);
 extern void * mempool_alloc(mempool_t *pool, unsigned int __nocast gfp_mask);
 extern void mempool_free(void *element, mempool_t *pool);
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 374b615ea9ea..9b8d0476988a 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -22,6 +22,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
+#define MII_ESTATUS         0x0f        /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -54,7 +55,10 @@
 #define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
-#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_RESV               0x00c0  /* Unused...                   */
+#define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
+#define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
@@ -114,6 +118,9 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
+#define ESTATUS_1000_TFULL      0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF      0x1000  /* Can do 1000BT Half */
+
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
 #define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 17518fe0b311..82d7024f0765 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -395,19 +395,81 @@ static inline void put_page(struct page *page)
 /*
  * The zone field is never updated after free_area_init_core()
  * sets it, so none of the operations on it need to be atomic.
- * We'll have up to (MAX_NUMNODES * MAX_NR_ZONES) zones total,
- * so we use (MAX_NODES_SHIFT + MAX_ZONES_SHIFT) here to get enough bits.
  */
-#define NODEZONE_SHIFT (sizeof(page_flags_t)*8 - MAX_NODES_SHIFT - MAX_ZONES_SHIFT)
-#define NODEZONE(node, zone)    ((node << ZONES_SHIFT) | zone)
+
+
+/*
+ * page->flags layout:
+ *
+ * There are three possibilities for how page->flags get
+ * laid out.  The first is for the normal case, without
+ * sparsemem.  The second is for sparsemem when there is
+ * plenty of space for node and section.  The last is when
+ * we have run out of space and have to fall back to an
+ * alternate (slower) way of determining the node.
+ *
+ *        No sparsemem: |       NODE     | ZONE | ... | FLAGS |
+ * with space for node: | SECTION | NODE | ZONE | ... | FLAGS |
+ *   no space for node: | SECTION |     ZONE    | ... | FLAGS |
+ */
+#ifdef CONFIG_SPARSEMEM
+#define SECTIONS_WIDTH          SECTIONS_SHIFT
+#else
+#define SECTIONS_WIDTH          0
+#endif
+
+#define ZONES_WIDTH             ZONES_SHIFT
+
+#if SECTIONS_WIDTH+ZONES_WIDTH+NODES_SHIFT <= FLAGS_RESERVED
+#define NODES_WIDTH             NODES_SHIFT
+#else
+#define NODES_WIDTH             0
+#endif
+
+/* Page flags: | [SECTION] | [NODE] | ZONE | ... | FLAGS | */
+#define SECTIONS_PGOFF          ((sizeof(page_flags_t)*8) - SECTIONS_WIDTH)
+#define NODES_PGOFF             (SECTIONS_PGOFF - NODES_WIDTH)
+#define ZONES_PGOFF             (NODES_PGOFF - ZONES_WIDTH)
+
+/*
+ * We are going to use the flags for the page to node mapping if its in
+ * there.  This includes the case where there is no node, so it is implicit.
+ */
+#define FLAGS_HAS_NODE          (NODES_WIDTH > 0 || NODES_SHIFT == 0)
+
+#ifndef PFN_SECTION_SHIFT
+#define PFN_SECTION_SHIFT 0
+#endif
+
+/*
+ * Define the bit shifts to access each section.  For non-existant
+ * sections we define the shift as 0; that plus a 0 mask ensures
+ * the compiler will optimise away reference to them.
+ */
+#define SECTIONS_PGSHIFT        (SECTIONS_PGOFF * (SECTIONS_WIDTH != 0))
+#define NODES_PGSHIFT           (NODES_PGOFF * (NODES_WIDTH != 0))
+#define ZONES_PGSHIFT           (ZONES_PGOFF * (ZONES_WIDTH != 0))
+
+/* NODE:ZONE or SECTION:ZONE is used to lookup the zone from a page. */
+#if FLAGS_HAS_NODE
+#define ZONETABLE_SHIFT         (NODES_SHIFT + ZONES_SHIFT)
+#else
+#define ZONETABLE_SHIFT         (SECTIONS_SHIFT + ZONES_SHIFT)
+#endif
+#define ZONETABLE_PGSHIFT       ZONES_PGSHIFT
+
+#if SECTIONS_WIDTH+NODES_WIDTH+ZONES_WIDTH > FLAGS_RESERVED
+#error SECTIONS_WIDTH+NODES_WIDTH+ZONES_WIDTH > FLAGS_RESERVED
+#endif
+
+#define ZONES_MASK              ((1UL << ZONES_WIDTH) - 1)
+#define NODES_MASK              ((1UL << NODES_WIDTH) - 1)
+#define SECTIONS_MASK           ((1UL << SECTIONS_WIDTH) - 1)
+#define ZONETABLE_MASK          ((1UL << ZONETABLE_SHIFT) - 1)
 
 static inline unsigned long page_zonenum(struct page *page)
 {
-        return (page->flags >> NODEZONE_SHIFT) & (~(~0UL << ZONES_SHIFT));
-}
-static inline unsigned long page_to_nid(struct page *page)
-{
-        return (page->flags >> (NODEZONE_SHIFT + ZONES_SHIFT));
+        return (page->flags >> ZONES_PGSHIFT) & ZONES_MASK;
 }
 
 struct zone;
@@ -415,13 +477,44 @@ extern struct zone *zone_table[];
 
 static inline struct zone *page_zone(struct page *page)
 {
-        return zone_table[page->flags >> NODEZONE_SHIFT];
+        return zone_table[(page->flags >> ZONETABLE_PGSHIFT) &
+                        ZONETABLE_MASK];
+}
+
+static inline unsigned long page_to_nid(struct page *page)
+{
+        if (FLAGS_HAS_NODE)
+                return (page->flags >> NODES_PGSHIFT) & NODES_MASK;
+        else
+                return page_zone(page)->zone_pgdat->node_id;
+}
+static inline unsigned long page_to_section(struct page *page)
+{
+        return (page->flags >> SECTIONS_PGSHIFT) & SECTIONS_MASK;
+}
+
+static inline void set_page_zone(struct page *page, unsigned long zone)
+{
+        page->flags &= ~(ZONES_MASK << ZONES_PGSHIFT);
+        page->flags |= (zone & ZONES_MASK) << ZONES_PGSHIFT;
+}
+static inline void set_page_node(struct page *page, unsigned long node)
+{
+        page->flags &= ~(NODES_MASK << NODES_PGSHIFT);
+        page->flags |= (node & NODES_MASK) << NODES_PGSHIFT;
+}
+static inline void set_page_section(struct page *page, unsigned long section)
+{
+        page->flags &= ~(SECTIONS_MASK << SECTIONS_PGSHIFT);
+        page->flags |= (section & SECTIONS_MASK) << SECTIONS_PGSHIFT;
 }
 
-static inline void set_page_zone(struct page *page, unsigned long nodezone_num)
+static inline void set_page_links(struct page *page, unsigned long zone,
+        unsigned long node, unsigned long pfn)
 {
-        page->flags &= ~(~0UL << NODEZONE_SHIFT);
-        page->flags |= nodezone_num << NODEZONE_SHIFT;
+        set_page_zone(page, zone);
+        set_page_node(page, node);
+        set_page_section(page, pfn_to_section_nr(pfn));
 }
 
 #ifndef CONFIG_DISCONTIGMEM
@@ -532,10 +625,16 @@ static inline int page_mapped(struct page *page)
  * Used to decide whether a process gets delivered SIGBUS or
  * just gets major/minor fault counters bumped up.
  */
-#define VM_FAULT_OOM    (-1)
-#define VM_FAULT_SIGBUS 0
-#define VM_FAULT_MINOR  1
-#define VM_FAULT_MAJOR  2
+#define VM_FAULT_OOM    0x00
+#define VM_FAULT_SIGBUS 0x01
+#define VM_FAULT_MINOR  0x02
+#define VM_FAULT_MAJOR  0x03
+
+/* 
+ * Special case for get_user_pages.
+ * Must be in a distinct bit from the above VM_FAULT_ flags.
+ */
+#define VM_FAULT_WRITE  0x10
 
 #define offset_in_page(p)       ((unsigned long)(p) & ~PAGE_MASK)
 
@@ -611,7 +710,13 @@ extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsign
 extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
 extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot);
 extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot);
-extern int handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
+extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
+
+static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, int write_access)
+{
+        return __handle_mm_fault(mm, vma, address, write_access) & (~VM_FAULT_WRITE);
+}
+
 extern int make_pages_present(unsigned long addr, unsigned long end);
 extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write);
 void install_arg_page(struct vm_area_struct *, struct page *, unsigned long);
@@ -691,6 +796,12 @@ extern void show_mem(void);
 extern void si_meminfo(struct sysinfo * val);
 extern void si_meminfo_node(struct sysinfo *val, int nid);
 
+#ifdef CONFIG_NUMA
+extern void setup_per_cpu_pageset(void);
+#else
+static inline void setup_per_cpu_pageset(void) {}
+#endif
+
 /* prio_tree.c */
 void vma_prio_tree_add(struct vm_area_struct *, struct vm_area_struct *old);
 void vma_prio_tree_insert(struct vm_area_struct *, struct prio_tree_root *);
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index aefedf04b9bb..18fc77f682de 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -33,6 +33,13 @@ struct mmc_csd {
         unsigned int            capacity;
 };
 
+struct sd_scr {
+        unsigned char           sda_vsn;
+        unsigned char           bus_widths;
+#define SD_SCR_BUS_WIDTH_1      (1<<0)
+#define SD_SCR_BUS_WIDTH_4      (1<<2)
+};
+
 struct mmc_host;
 
 /*
@@ -47,19 +54,27 @@ struct mmc_card {
 #define MMC_STATE_PRESENT       (1<<0)          /* present in sysfs */
 #define MMC_STATE_DEAD          (1<<1)          /* device no longer in stack */
 #define MMC_STATE_BAD           (1<<2)          /* unrecognised device */
+#define MMC_STATE_SDCARD        (1<<3)          /* is an SD card */
+#define MMC_STATE_READONLY      (1<<4)          /* card is read-only */
         u32                     raw_cid[4];     /* raw card CID */
         u32                     raw_csd[4];     /* raw card CSD */
+        u32                     raw_scr[2];     /* raw card SCR */
         struct mmc_cid          cid;            /* card identification */
         struct mmc_csd          csd;            /* card specific */
+        struct sd_scr           scr;            /* extra SD information */
 };
 
 #define mmc_card_present(c)     ((c)->state & MMC_STATE_PRESENT)
 #define mmc_card_dead(c)        ((c)->state & MMC_STATE_DEAD)
 #define mmc_card_bad(c)         ((c)->state & MMC_STATE_BAD)
+#define mmc_card_sd(c)          ((c)->state & MMC_STATE_SDCARD)
+#define mmc_card_readonly(c)    ((c)->state & MMC_STATE_READONLY)
 
 #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
 #define mmc_card_set_dead(c)    ((c)->state |= MMC_STATE_DEAD)
 #define mmc_card_set_bad(c)     ((c)->state |= MMC_STATE_BAD)
+#define mmc_card_set_sd(c)      ((c)->state |= MMC_STATE_SDCARD)
+#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
 
 #define mmc_card_name(c)        ((c)->cid.prod_name)
 #define mmc_card_id(c)          ((c)->dev.bus_id)
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index f90f674eb3b0..c1f021eddffa 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -46,16 +46,28 @@ struct mmc_ios {
 #define MMC_BUSMODE_OPENDRAIN   1
 #define MMC_BUSMODE_PUSHPULL    2
 
+        unsigned char   chip_select;            /* SPI chip select */
+
+#define MMC_CS_DONTCARE         0
+#define MMC_CS_HIGH             1
+#define MMC_CS_LOW              2
+
         unsigned char   power_mode;             /* power supply mode */
 
 #define MMC_POWER_OFF           0
 #define MMC_POWER_UP            1
 #define MMC_POWER_ON            2
+
+        unsigned char   bus_width;              /* data bus width */
+
+#define MMC_BUS_WIDTH_1         0
+#define MMC_BUS_WIDTH_4         2
 };
 
 struct mmc_host_ops {
         void    (*request)(struct mmc_host *host, struct mmc_request *req);
         void    (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
+        int     (*get_ro)(struct mmc_host *host);
 };
 
 struct mmc_card;
@@ -63,11 +75,16 @@ struct device;
 
 struct mmc_host {
         struct device           *dev;
+        struct class_device     class_dev;
+        int                     index;
         struct mmc_host_ops     *ops;
         unsigned int            f_min;
         unsigned int            f_max;
         u32                     ocr_avail;
-        char                    host_name[8];
+
+        unsigned long           caps;           /* Host capabilities */
+
+#define MMC_CAP_4_BIT_DATA      (1 << 0)        /* Can the host do 4 bit transfers */
 
         /* host specific block data */
         unsigned int            max_seg_size;   /* see blk_queue_max_segment_size */
@@ -80,6 +97,10 @@ struct mmc_host {
         struct mmc_ios          ios;            /* current io bus settings */
         u32                     ocr;            /* the current OCR setting */
 
+        unsigned int            mode;           /* current card mode of host */
+#define MMC_MODE_MMC            0
+#define MMC_MODE_SD             1
+
         struct list_head        cards;          /* devices attached to this host */
 
         wait_queue_head_t       wq;
@@ -88,6 +109,8 @@ struct mmc_host {
         struct mmc_card         *card_selected; /* the selected MMC card */
 
         struct work_struct      detect;
+
+        unsigned long           private[0] ____cacheline_aligned;
 };
 
 extern struct mmc_host *mmc_alloc_host(int extra, struct device *);
@@ -95,13 +118,18 @@ extern int mmc_add_host(struct mmc_host *);
 extern void mmc_remove_host(struct mmc_host *);
 extern void mmc_free_host(struct mmc_host *);
 
-#define mmc_priv(x)     ((void *)((x) + 1))
+static inline void *mmc_priv(struct mmc_host *host)
+{
+        return (void *)host->private;
+}
+
 #define mmc_dev(x)      ((x)->dev)
+#define mmc_hostname(x) ((x)->class_dev.class_id)
 
 extern int mmc_suspend_host(struct mmc_host *, pm_message_t);
 extern int mmc_resume_host(struct mmc_host *);
 
-extern void mmc_detect_change(struct mmc_host *);
+extern void mmc_detect_change(struct mmc_host *, unsigned long delay);
 extern void mmc_request_done(struct mmc_host *, struct mmc_request *);
 
 #endif
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 0d35d4ffb360..1ab78e8d6c53 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -88,6 +88,8 @@ struct mmc_card;
 
 extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
 extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
+extern int mmc_wait_for_app_cmd(struct mmc_host *, unsigned int,
+        struct mmc_command *, int);
 
 extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card);
 
diff --git a/include/linux/mmc/protocol.h b/include/linux/mmc/protocol.h
index 896342817b97..f819cae92266 100644
--- a/include/linux/mmc/protocol.h
+++ b/include/linux/mmc/protocol.h
@@ -236,5 +236,12 @@ struct _mmc_csd {
 #define CSD_SPEC_VER_2      2           /* Implements system specification 2.0 - 2.2 */
 #define CSD_SPEC_VER_3      3           /* Implements system specification 3.1 */
 
+
+/*
+ * SD bus widths
+ */
+#define SD_BUS_WIDTH_1      0
+#define SD_BUS_WIDTH_4      2
+
 #endif  /* MMC_MMC_PROTOCOL_H */
 
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index e530c6c092f1..5ed471b58f4f 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -63,6 +63,12 @@ struct per_cpu_pageset {
 #endif
 } ____cacheline_aligned_in_smp;
 
+#ifdef CONFIG_NUMA
+#define zone_pcp(__z, __cpu) ((__z)->pageset[(__cpu)])
+#else
+#define zone_pcp(__z, __cpu) (&(__z)->pageset[(__cpu)])
+#endif
+
 #define ZONE_DMA                0
 #define ZONE_NORMAL             1
 #define ZONE_HIGHMEM            2
@@ -122,8 +128,11 @@ struct zone {
          */
         unsigned long           lowmem_reserve[MAX_NR_ZONES];
 
+#ifdef CONFIG_NUMA
+        struct per_cpu_pageset  *pageset[NR_CPUS];
+#else
         struct per_cpu_pageset  pageset[NR_CPUS];
-
+#endif
         /*
          * free areas of different sizes
          */
@@ -145,6 +154,14 @@ struct zone {
         int                     all_unreclaimable; /* All pages pinned */
 
         /*
+         * Does the allocator try to reclaim pages from the zone as soon
+         * as it fails a watermark_ok() in __alloc_pages?
+         */
+        int                     reclaim_pages;
+        /* A count of how many reclaimers are scanning this zone */
+        atomic_t                reclaim_in_progress;
+
+        /*
          * prev_priority holds the scanning priority for this zone.  It is
          * defined as the scanning priority at which we achieved our reclaim
          * target at the previous try_to_free_pages() or balance_pgdat()
@@ -252,7 +269,9 @@ typedef struct pglist_data {
         struct zone node_zones[MAX_NR_ZONES];
         struct zonelist node_zonelists[GFP_ZONETYPES];
         int nr_zones;
+#ifdef CONFIG_FLAT_NODE_MEM_MAP
         struct page *node_mem_map;
+#endif
         struct bootmem_data *bdata;
         unsigned long node_start_pfn;
         unsigned long node_present_pages; /* total number of physical pages */
@@ -267,6 +286,12 @@ typedef struct pglist_data {
 
 #define node_present_pages(nid) (NODE_DATA(nid)->node_present_pages)
 #define node_spanned_pages(nid) (NODE_DATA(nid)->node_spanned_pages)
+#ifdef CONFIG_FLAT_NODE_MEM_MAP
+#define pgdat_page_nr(pgdat, pagenr)    ((pgdat)->node_mem_map + (pagenr))
+#else
+#define pgdat_page_nr(pgdat, pagenr)    pfn_to_page((pgdat)->node_start_pfn + (pagenr))
+#endif
+#define nid_page_nr(nid, pagenr)        pgdat_page_nr(NODE_DATA(nid),(pagenr))
 
 extern struct pglist_data *pgdat_list;
 
@@ -381,9 +406,9 @@ int lowmem_reserve_ratio_sysctl_handler(struct ctl_table *, int, struct file *,
 
 #include <linux/topology.h>
 /* Returns the number of the current Node. */
-#define numa_node_id()          (cpu_to_node(_smp_processor_id()))
+#define numa_node_id()          (cpu_to_node(raw_smp_processor_id()))
 
-#ifndef CONFIG_DISCONTIGMEM
+#ifndef CONFIG_NEED_MULTIPLE_NODES
 
 extern struct pglist_data contig_page_data;
 #define NODE_DATA(nid)          (&contig_page_data)
@@ -391,36 +416,194 @@ extern struct pglist_data contig_page_data;
 #define MAX_NODES_SHIFT         1
 #define pfn_to_nid(pfn)         (0)
 
-#else /* CONFIG_DISCONTIGMEM */
+#else /* CONFIG_NEED_MULTIPLE_NODES */
 
 #include <asm/mmzone.h>
 
+#endif /* !CONFIG_NEED_MULTIPLE_NODES */
+
+#ifdef CONFIG_SPARSEMEM
+#include <asm/sparsemem.h>
+#endif
+
 #if BITS_PER_LONG == 32 || defined(ARCH_HAS_ATOMIC_UNSIGNED)
 /*
  * with 32 bit page->flags field, we reserve 8 bits for node/zone info.
  * there are 3 zones (2 bits) and this leaves 8-2=6 bits for nodes.
  */
-#define MAX_NODES_SHIFT         6
+#define FLAGS_RESERVED          8
+
 #elif BITS_PER_LONG == 64
 /*
  * with 64 bit flags field, there's plenty of room.
  */
-#define MAX_NODES_SHIFT         10
+#define FLAGS_RESERVED          32
+
+#else
+
+#error BITS_PER_LONG not defined
+
+#endif
+
+#ifndef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
+#define early_pfn_to_nid(nid)  (0UL)
+#endif
+
+#define pfn_to_section_nr(pfn) ((pfn) >> PFN_SECTION_SHIFT)
+#define section_nr_to_pfn(sec) ((sec) << PFN_SECTION_SHIFT)
+
+#ifdef CONFIG_SPARSEMEM
+
+/*
+ * SECTION_SHIFT                #bits space required to store a section #
+ *
+ * PA_SECTION_SHIFT             physical address to/from section number
+ * PFN_SECTION_SHIFT            pfn to/from section number
+ */
+#define SECTIONS_SHIFT          (MAX_PHYSMEM_BITS - SECTION_SIZE_BITS)
+
+#define PA_SECTION_SHIFT        (SECTION_SIZE_BITS)
+#define PFN_SECTION_SHIFT       (SECTION_SIZE_BITS - PAGE_SHIFT)
+
+#define NR_MEM_SECTIONS         (1UL << SECTIONS_SHIFT)
+
+#define PAGES_PER_SECTION       (1UL << PFN_SECTION_SHIFT)
+#define PAGE_SECTION_MASK       (~(PAGES_PER_SECTION-1))
+
+#if (MAX_ORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS
+#error Allocator MAX_ORDER exceeds SECTION_SIZE
+#endif
+
+struct page;
+struct mem_section {
+        /*
+         * This is, logically, a pointer to an array of struct
+         * pages.  However, it is stored with some other magic.
+         * (see sparse.c::sparse_init_one_section())
+         *
+         * Making it a UL at least makes someone do a cast
+         * before using it wrong.
+         */
+        unsigned long section_mem_map;
+};
+
+#ifdef CONFIG_SPARSEMEM_EXTREME
+#define SECTIONS_PER_ROOT       (PAGE_SIZE / sizeof (struct mem_section))
+#else
+#define SECTIONS_PER_ROOT       1
+#endif
+
+#define SECTION_NR_TO_ROOT(sec) ((sec) / SECTIONS_PER_ROOT)
+#define NR_SECTION_ROOTS        (NR_MEM_SECTIONS / SECTIONS_PER_ROOT)
+#define SECTION_ROOT_MASK       (SECTIONS_PER_ROOT - 1)
+
+#ifdef CONFIG_SPARSEMEM_EXTREME
+extern struct mem_section *mem_section[NR_SECTION_ROOTS];
+#else
+extern struct mem_section mem_section[NR_SECTION_ROOTS][SECTIONS_PER_ROOT];
 #endif
 
-#endif /* !CONFIG_DISCONTIGMEM */
+static inline struct mem_section *__nr_to_section(unsigned long nr)
+{
+        if (!mem_section[SECTION_NR_TO_ROOT(nr)])
+                return NULL;
+        return &mem_section[SECTION_NR_TO_ROOT(nr)][nr & SECTION_ROOT_MASK];
+}
+
+/*
+ * We use the lower bits of the mem_map pointer to store
+ * a little bit of information.  There should be at least
+ * 3 bits here due to 32-bit alignment.
+ */
+#define SECTION_MARKED_PRESENT  (1UL<<0)
+#define SECTION_HAS_MEM_MAP     (1UL<<1)
+#define SECTION_MAP_LAST_BIT    (1UL<<2)
+#define SECTION_MAP_MASK        (~(SECTION_MAP_LAST_BIT-1))
+
+static inline struct page *__section_mem_map_addr(struct mem_section *section)
+{
+        unsigned long map = section->section_mem_map;
+        map &= SECTION_MAP_MASK;
+        return (struct page *)map;
+}
+
+static inline int valid_section(struct mem_section *section)
+{
+        return (section && (section->section_mem_map & SECTION_MARKED_PRESENT));
+}
+
+static inline int section_has_mem_map(struct mem_section *section)
+{
+        return (section && (section->section_mem_map & SECTION_HAS_MEM_MAP));
+}
+
+static inline int valid_section_nr(unsigned long nr)
+{
+        return valid_section(__nr_to_section(nr));
+}
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define kvaddr_to_nid(kaddr)    pfn_to_nid(__pa(kaddr) >> PAGE_SHIFT)
 
-#if NODES_SHIFT > MAX_NODES_SHIFT
-#error NODES_SHIFT > MAX_NODES_SHIFT
+static inline struct mem_section *__pfn_to_section(unsigned long pfn)
+{
+        return __nr_to_section(pfn_to_section_nr(pfn));
+}
+
+#define pfn_to_page(pfn)                                                \
+({                                                                      \
+        unsigned long __pfn = (pfn);                                    \
+        __section_mem_map_addr(__pfn_to_section(__pfn)) + __pfn;        \
+})
+#define page_to_pfn(page)                                               \
+({                                                                      \
+        page - __section_mem_map_addr(__nr_to_section(                  \
+                page_to_section(page)));                                \
+})
+
+static inline int pfn_valid(unsigned long pfn)
+{
+        if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS)
+                return 0;
+        return valid_section(__nr_to_section(pfn_to_section_nr(pfn)));
+}
+
+/*
+ * These are _only_ used during initialisation, therefore they
+ * can use __initdata ...  They could have names to indicate
+ * this restriction.
+ */
+#ifdef CONFIG_NUMA
+#define pfn_to_nid              early_pfn_to_nid
 #endif
 
-/* There are currently 3 zones: DMA, Normal & Highmem, thus we need 2 bits */
-#define MAX_ZONES_SHIFT         2
+#define pfn_to_pgdat(pfn)                                               \
+({                                                                      \
+        NODE_DATA(pfn_to_nid(pfn));                                     \
+})
+
+#define early_pfn_valid(pfn)    pfn_valid(pfn)
+void sparse_init(void);
+#else
+#define sparse_init()   do {} while (0)
+#define sparse_index_init(_sec, _nid)  do {} while (0)
+#endif /* CONFIG_SPARSEMEM */
+
+#ifdef CONFIG_NODES_SPAN_OTHER_NODES
+#define early_pfn_in_nid(pfn, nid)      (early_pfn_to_nid(pfn) == (nid))
+#else
+#define early_pfn_in_nid(pfn, nid)      (1)
+#endif
 
-#if ZONES_SHIFT > MAX_ZONES_SHIFT
-#error ZONES_SHIFT > MAX_ZONES_SHIFT
+#ifndef early_pfn_valid
+#define early_pfn_valid(pfn)    (1)
 #endif
 
+void memory_present(int nid, unsigned long start, unsigned long end);
+unsigned long __init node_memmap_size_bytes(int, unsigned long, unsigned long);
+
 #endif /* !__ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _LINUX_MMZONE_H */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index d6eb7b2efc04..47da39ba3f03 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -1,6 +1,6 @@
 /*
  * Device tables which are exported to userspace via
- * scripts/table2alias.c.  You must keep that file in sync with this
+ * scripts/mod/file2alias.c.  You must keep that file in sync with this
  * header.
  */
 
@@ -33,7 +33,8 @@ struct ieee1394_device_id {
         __u32 model_id;
         __u32 specifier_id;
         __u32 version;
-        kernel_ulong_t driver_data;
+        kernel_ulong_t driver_data
+                __attribute__((aligned(sizeof(kernel_ulong_t))));
 };
 
 
@@ -174,5 +175,72 @@ struct serio_device_id {
         __u8 proto;
 };
 
+/*
+ * Struct used for matching a device
+ */
+struct of_device_id
+{
+        char    name[32];
+        char    type[32];
+        char    compatible[128];
+#if __KERNEL__
+        void    *data;
+#else
+        kernel_ulong_t data;
+#endif
+};
+
+/* VIO */
+struct vio_device_id {
+        char type[32];
+        char compat[32];
+};
+
+/* PCMCIA */
+
+struct pcmcia_device_id {
+        __u16           match_flags;
+
+        __u16           manf_id;
+        __u16           card_id;
+
+        __u8            func_id;
+
+        /* for real multi-function devices */
+        __u8            function;
+
+        /* for pseude multi-function devices */
+        __u8            device_no;
+
+        __u32           prod_id_hash[4];
+
+        /* not matched against in kernelspace*/
+#ifdef __KERNEL__
+        const char *    prod_id[4];
+#else
+        kernel_ulong_t  prod_id[4]
+                __attribute__((aligned(sizeof(kernel_ulong_t))));
+#endif
+
+        /* not matched against */
+        kernel_ulong_t  driver_info;
+#ifdef __KERNEL__
+        char *          cisfile;
+#else
+        kernel_ulong_t  cisfile;
+#endif
+};
+
+#define PCMCIA_DEV_ID_MATCH_MANF_ID     0x0001
+#define PCMCIA_DEV_ID_MATCH_CARD_ID     0x0002
+#define PCMCIA_DEV_ID_MATCH_FUNC_ID     0x0004
+#define PCMCIA_DEV_ID_MATCH_FUNCTION    0x0008
+#define PCMCIA_DEV_ID_MATCH_PROD_ID1    0x0010
+#define PCMCIA_DEV_ID_MATCH_PROD_ID2    0x0020
+#define PCMCIA_DEV_ID_MATCH_PROD_ID3    0x0040
+#define PCMCIA_DEV_ID_MATCH_PROD_ID4    0x0080
+#define PCMCIA_DEV_ID_MATCH_DEVICE_NO   0x0100
+#define PCMCIA_DEV_ID_MATCH_FAKE_CIS    0x0200
+#define PCMCIA_DEV_ID_MATCH_ANONYMOUS   0x0400
 
 #endif /* LINUX_MOD_DEVICETABLE_H */
diff --git a/include/linux/module.h b/include/linux/module.h
index 0e432a0f4aee..f05372b7fe77 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -51,6 +51,9 @@ struct module_attribute {
         ssize_t (*show)(struct module_attribute *, struct module *, char *);
         ssize_t (*store)(struct module_attribute *, struct module *,
                          const char *, size_t count);
+        void (*setup)(struct module *, const char *);
+        int (*test)(struct module *);
+        void (*free)(struct module *);
 };
 
 struct module_kobject
@@ -239,6 +242,8 @@ struct module
         /* Sysfs stuff. */
         struct module_kobject mkobj;
         struct module_param_attrs *param_attrs;
+        const char *version;
+        const char *srcversion;
 
         /* Exported symbols */
         const struct kernel_symbol *syms;
diff --git a/include/linux/mount.h b/include/linux/mount.h
index 8b8d3b9beefd..f8f39937e301 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -12,6 +12,7 @@
 #define _LINUX_MOUNT_H
 #ifdef __KERNEL__
 
+#include <linux/types.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <asm/atomic.h>
@@ -34,7 +35,7 @@ struct vfsmount
         int mnt_expiry_mark;            /* true if marked for expiry */
         char *mnt_devname;              /* Name of device e.g. /dev/dsk/hda1 */
         struct list_head mnt_list;
-        struct list_head mnt_fslink;    /* link in fs-specific expiry list */
+        struct list_head mnt_expire;    /* link in fs-specific expiry list */
         struct namespace *mnt_namespace; /* containing namespace */
 };
 
@@ -47,7 +48,7 @@ static inline struct vfsmount *mntget(struct vfsmount *mnt)
 
 extern void __mntput(struct vfsmount *mnt);
 
-static inline void _mntput(struct vfsmount *mnt)
+static inline void mntput_no_expire(struct vfsmount *mnt)
 {
         if (mnt) {
                 if (atomic_dec_and_test(&mnt->mnt_count))
@@ -59,7 +60,7 @@ static inline void mntput(struct vfsmount *mnt)
 {
         if (mnt) {
                 mnt->mnt_expiry_mark = 0;
-                _mntput(mnt);
+                mntput_no_expire(mnt);
         }
 }
 
@@ -76,6 +77,7 @@ extern int do_add_mount(struct vfsmount *newmnt, struct nameidata *nd,
 extern void mark_mounts_for_expiry(struct list_head *mounts);
 
 extern spinlock_t vfsmount_lock;
+extern dev_t name_to_dev_t(char *name);
 
 #endif
 #endif /* _LINUX_MOUNT_H */
diff --git a/include/linux/msg.h b/include/linux/msg.h
index 2c4c6aa643ff..903e0ab8101f 100644
--- a/include/linux/msg.h
+++ b/include/linux/msg.h
@@ -77,6 +77,7 @@ struct msg_msg {
 /* one msq_queue structure for each present queue on the system */
 struct msg_queue {
         struct kern_ipc_perm q_perm;
+        int q_id;
         time_t q_stime;                 /* last msgsnd time */
         time_t q_rtime;                 /* last msgrcv time */
         time_t q_ctime;                 /* last change time */
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 2ed8c585021e..e6b6a1c66bd5 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -1,7 +1,7 @@
 
 /* Common Flash Interface structures 
  * See http://support.intel.com/design/flash/technote/index.htm
- * $Id: cfi.h,v 1.50 2004/11/20 12:46:51 dwmw2 Exp $
+ * $Id: cfi.h,v 1.54 2005/06/06 23:04:36 tpoynor Exp $
  */
 
 #ifndef __MTD_CFI_H__
@@ -148,6 +148,14 @@ struct cfi_pri_intelext {
         uint8_t  extra[0];
 } __attribute__((packed));
 
+struct cfi_intelext_otpinfo {
+        uint32_t ProtRegAddr;
+        uint16_t FactGroups;
+        uint8_t  FactProtRegSize;
+        uint16_t UserGroups;
+        uint8_t  UserProtRegSize;
+} __attribute__((packed));
+
 struct cfi_intelext_blockinfo {
         uint16_t NumIdentBlocks;
         uint16_t BlockSize;
@@ -244,7 +252,7 @@ static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int
  * It looks too long to be inline, but in the common case it should almost all
  * get optimised away. 
  */
-static inline map_word cfi_build_cmd(u_char cmd, struct map_info *map, struct cfi_private *cfi)
+static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
 {
         map_word val = { {0} };
         int wordwidth, words_per_bus, chip_mode, chips_per_word;
@@ -307,6 +315,69 @@ static inline map_word cfi_build_cmd(u_char cmd, struct map_info *map, struct cf
 }
 #define CMD(x)  cfi_build_cmd((x), map, cfi)
 
+
+static inline unsigned char cfi_merge_status(map_word val, struct map_info *map, 
+                                           struct cfi_private *cfi)
+{
+        int wordwidth, words_per_bus, chip_mode, chips_per_word;
+        unsigned long onestat, res = 0;
+        int i;
+
+        /* We do it this way to give the compiler a fighting chance 
+           of optimising away all the crap for 'bankwidth' larger than
+           an unsigned long, in the common case where that support is
+           disabled */
+        if (map_bankwidth_is_large(map)) {
+                wordwidth = sizeof(unsigned long);
+                words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
+        } else {
+                wordwidth = map_bankwidth(map);
+                words_per_bus = 1;
+        }
+        
+        chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
+        chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
+
+        onestat = val.x[0];
+        /* Or all status words together */
+        for (i=1; i < words_per_bus; i++) {
+                onestat |= val.x[i];
+        }
+
+        res = onestat;
+        switch(chips_per_word) {
+        default: BUG();
+#if BITS_PER_LONG >= 64
+        case 8:
+                res |= (onestat >> (chip_mode * 32));
+#endif
+        case 4:
+                res |= (onestat >> (chip_mode * 16));
+        case 2:
+                res |= (onestat >> (chip_mode * 8));
+        case 1:
+                ;
+        }
+
+        /* Last, determine what the bit-pattern should be for a single
+           device, according to chip mode and endianness... */
+        switch (chip_mode) {
+        case 1:
+                break;
+        case 2:
+                res = cfi16_to_cpu(res);
+                break;
+        case 4:
+                res = cfi32_to_cpu(res);
+                break;
+        default: BUG();
+        }
+        return res;
+}
+
+#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
+
+
 /*
  * Sends a CFI command to a bank of flash for the given geometry.
  *
@@ -357,16 +428,6 @@ static inline void cfi_udelay(int us)
         }
 }
 
-static inline void cfi_spin_lock(spinlock_t *mutex)
-{
-        spin_lock_bh(mutex);
-}
-
-static inline void cfi_spin_unlock(spinlock_t *mutex)
-{
-        spin_unlock_bh(mutex);
-}
-
 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
                              const char* name);
 struct cfi_fixup {
diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h
index c66ba812bf90..675776fa3e27 100644
--- a/include/linux/mtd/flashchip.h
+++ b/include/linux/mtd/flashchip.h
@@ -6,7 +6,7 @@
  *
  * (C) 2000 Red Hat. GPLd.
  *
- * $Id: flashchip.h,v 1.15 2004/11/05 22:41:06 nico Exp $
+ * $Id: flashchip.h,v 1.17 2005/03/14 18:27:15 bjd Exp $
  *
  */
 
@@ -29,6 +29,7 @@ typedef enum {
         FL_ERASE_SUSPENDED,
         FL_WRITING,
         FL_WRITING_TO_BUFFER,
+        FL_OTP_WRITE,
         FL_WRITE_SUSPENDING,
         FL_WRITE_SUSPENDED,
         FL_PM_SUSPENDED,
@@ -62,8 +63,8 @@ struct flchip {
         flstate_t state;
         flstate_t oldstate;
 
-        int write_suspended:1;
-        int erase_suspended:1;
+        unsigned int write_suspended:1;
+        unsigned int erase_suspended:1;
         unsigned long in_progress_block_addr;
 
         spinlock_t *mutex;
diff --git a/include/linux/mtd/inftl.h b/include/linux/mtd/inftl.h
index b52c8cbd235c..0268125a6271 100644
--- a/include/linux/mtd/inftl.h
+++ b/include/linux/mtd/inftl.h
@@ -3,7 +3,7 @@
  *
  *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
  *
- *      $Id: inftl.h,v 1.6 2004/06/30 14:49:00 dbrown Exp $
+ *      $Id: inftl.h,v 1.7 2005/06/13 13:08:45 sean Exp $
  */
 
 #ifndef __MTD_INFTL_H__
@@ -20,7 +20,7 @@
 #include <mtd/inftl-user.h>
 
 #ifndef INFTL_MAJOR
-#define INFTL_MAJOR 94
+#define INFTL_MAJOR 96
 #endif
 #define INFTL_PARTN_BITS 4
 
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index f0268b99c900..142963f01d29 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -1,6 +1,6 @@
 
 /* Overhauled routines for dealing with different mmap regions of flash */
-/* $Id: map.h,v 1.46 2005/01/05 17:09:44 dwmw2 Exp $ */
+/* $Id: map.h,v 1.52 2005/05/25 10:29:41 gleixner Exp $ */
 
 #ifndef __LINUX_MTD_MAP_H__
 #define __LINUX_MTD_MAP_H__
@@ -263,6 +263,17 @@ static inline map_word map_word_and(struct map_info *map, map_word val1, map_wor
         return r;
 }
 
+static inline map_word map_word_clr(struct map_info *map, map_word val1, map_word val2)
+{
+        map_word r;
+        int i;
+
+        for (i=0; i<map_words(map); i++) {
+                r.x[i] = val1.x[i] & ~val2.x[i];
+        }
+        return r;
+}
+
 static inline map_word map_word_or(struct map_info *map, map_word val1, map_word val2)
 {
         map_word r;
@@ -273,6 +284,7 @@ static inline map_word map_word_or(struct map_info *map, map_word val1, map_word
         }
         return r;
 }
+
 #define map_word_andequal(m, a, b, z) map_word_equal(m, z, map_word_and(m, a, b))
 
 static inline int map_word_bitsset(struct map_info *map, map_word val1, map_word val2)
@@ -328,16 +340,27 @@ static inline map_word map_word_load_partial(struct map_info *map, map_word orig
         return orig;
 }
 
+#if BITS_PER_LONG < 64
+#define MAP_FF_LIMIT 4
+#else
+#define MAP_FF_LIMIT 8
+#endif
+
 static inline map_word map_word_ff(struct map_info *map)
 {
         map_word r;
         int i;
-
-        for (i=0; i<map_words(map); i++) {
-                r.x[i] = ~0UL;
+        
+        if (map_bankwidth(map) < MAP_FF_LIMIT) {
+                int bw = 8 * map_bankwidth(map);
+                r.x[0] = (1 << bw) - 1;
+        } else {
+                for (i=0; i<map_words(map); i++)
+                        r.x[i] = ~0UL;
         }
         return r;
 }
+
 static inline map_word inline_map_read(struct map_info *map, unsigned long ofs)
 {
         map_word r;
@@ -405,7 +428,7 @@ extern void simple_map_init(struct map_info *);
 
 
 #define simple_map_init(map) BUG_ON(!map_bankwidth_supported((map)->bankwidth))
-#define map_is_linear(map) (1)
+#define map_is_linear(map) ({ (void)(map); 1; })
 
 #endif /* !CONFIG_MTD_COMPLEX_MAPPINGS */
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index b3d134392b31..c50c3f3927d9 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,5 +1,5 @@
 /* 
- * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $
+ * $Id: mtd.h,v 1.59 2005/04/11 10:19:02 gleixner Exp $
  *
  * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
  *
@@ -18,6 +18,7 @@
 #include <linux/types.h>
 #include <linux/module.h>
 #include <linux/uio.h>
+#include <linux/notifier.h>
 
 #include <linux/mtd/compatmac.h>
 #include <mtd/mtd-abi.h>
@@ -69,7 +70,6 @@ struct mtd_info {
 
         u_int32_t oobblock;  // Size of OOB blocks (e.g. 512)
         u_int32_t oobsize;   // Amount of OOB data per block (e.g. 16)
-        u_int32_t oobavail;  // Number of bytes in OOB area available for fs 
         u_int32_t ecctype;
         u_int32_t eccsize;
         
@@ -80,6 +80,7 @@ struct mtd_info {
 
         // oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO)
         struct nand_oobinfo oobinfo;
+        u_int32_t oobavail;  // Number of bytes in OOB area available for fs 
 
         /* Data for variable erase regions. If numeraseregions is zero,
          * it means that the whole device has erasesize as given above. 
@@ -113,12 +114,12 @@ struct mtd_info {
          * flash devices. The user data is one time programmable but the
          * factory data is read only. 
          */
-        int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-
+        int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
         int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-
-        /* This function is not yet implemented */
+        int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
+        int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
         int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+        int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len);
 
         /* kvec-based read/write methods. We need these especially for NAND flash,
            with its limited number of write cycles per erase.
@@ -147,6 +148,8 @@ struct mtd_info {
         int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
         int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
 
+        struct notifier_block reboot_notifier;  /* default mode before reboot */
+
         void *priv;
 
         struct module *owner;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 9a19c65abd74..9b5b76217584 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -5,7 +5,7 @@
  *                     Steven J. Hill <sjhill@realitydiluted.com>
  *                     Thomas Gleixner <tglx@linutronix.de>
  *
- * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
+ * $Id: nand.h,v 1.73 2005/05/31 19:39:17 gleixner Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -48,6 +48,10 @@
  *  02-08-2004 tglx     added option field to nand structure for chip anomalities
  *  05-25-2004 tglx     added bad block table support, ST-MICRO manufacturer id
  *                      update of nand_chip structure description
+ *  01-17-2005 dmarlin  added extended commands for AG-AND device and added option 
+ *                      for BBT_AUTO_REFRESH.
+ *  01-20-2005 dmarlin  added optional pointer to hardware specific callback for 
+ *                      extra error status checks.
  */
 #ifndef __LINUX_MTD_NAND_H
 #define __LINUX_MTD_NAND_H
@@ -115,6 +119,25 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 #define NAND_CMD_READSTART      0x30
 #define NAND_CMD_CACHEDPROG     0x15
 
+/* Extended commands for AG-AND device */
+/* 
+ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 
+ *       there is no way to distinguish that from NAND_CMD_READ0
+ *       until the remaining sequence of commands has been completed
+ *       so add a high order bit and mask it off in the command.
+ */
+#define NAND_CMD_DEPLETE1       0x100
+#define NAND_CMD_DEPLETE2       0x38
+#define NAND_CMD_STATUS_MULTI   0x71
+#define NAND_CMD_STATUS_ERROR   0x72
+/* multi-bank error status (banks 0-3) */
+#define NAND_CMD_STATUS_ERROR0  0x73
+#define NAND_CMD_STATUS_ERROR1  0x74
+#define NAND_CMD_STATUS_ERROR2  0x75
+#define NAND_CMD_STATUS_ERROR3  0x76
+#define NAND_CMD_STATUS_RESET   0x7f
+#define NAND_CMD_STATUS_CLEAR   0xff
+
 /* Status bits */
 #define NAND_STATUS_FAIL        0x01
 #define NAND_STATUS_FAIL_N1     0x02
@@ -143,7 +166,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 
 /*
  * Constants for Hardware ECC
-*/
+ */
 /* Reset Hardware ECC for read */
 #define NAND_ECC_READ           0
 /* Reset Hardware ECC for write */
@@ -151,6 +174,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 /* Enable Hardware ECC before syndrom is read back from flash */
 #define NAND_ECC_READSYN        2
 
+/* Bit mask for flags passed to do_nand_read_ecc */
+#define NAND_GET_DEVICE         0x80
+
+
 /* Option constants for bizarre disfunctionality and real
 *  features
 */
@@ -170,6 +197,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 /* Chip has a array of 4 pages which can be read without
  * additional ready /busy waits */
 #define NAND_4PAGE_ARRAY        0x00000040 
+/* Chip requires that BBT is periodically rewritten to prevent
+ * bits from adjacent blocks from 'leaking' in altering data.
+ * This happens with the Renesas AG-AND chips, possibly others.  */
+#define BBT_AUTO_REFRESH        0x00000080
 
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS \
@@ -192,7 +223,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
  * This can only work if we have the ecc bytes directly behind the 
  * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
 #define NAND_HWECC_SYNDROME     0x00020000
-
+/* This option skips the bbt scan during initialization. */
+#define NAND_SKIP_BBTSCAN       0x00040000
 
 /* Options set by nand scan */
 /* Nand scan has allocated oob_buf */
@@ -221,10 +253,13 @@ struct nand_chip;
  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
  * @lock:               protection lock  
  * @active:             the mtd device which holds the controller currently
+ * @wq:                 wait queue to sleep on if a NAND operation is in progress
+ *                      used instead of the per chip wait queue when a hw controller is available
  */
 struct nand_hw_control {
         spinlock_t       lock;
         struct nand_chip *active;
+        wait_queue_head_t wq;
 };
 
 /**
@@ -283,6 +318,8 @@ struct nand_hw_control {
  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan 
  * @controller:         [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
  * @priv:               [OPTIONAL] pointer to private chip date
+ * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks 
+ *                      (determine if errors are correctable)
  */
  
 struct nand_chip {
@@ -338,6 +375,7 @@ struct nand_chip {
         struct nand_bbt_descr   *badblock_pattern;
         struct nand_hw_control  *controller;
         void            *priv;
+        int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 };
 
 /*
@@ -349,6 +387,7 @@ struct nand_chip {
 #define NAND_MFR_NATIONAL       0x8f
 #define NAND_MFR_RENESAS        0x07
 #define NAND_MFR_STMICRO        0x20
+#define NAND_MFR_HYNIX          0xad
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
@@ -459,6 +498,9 @@ extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
 extern int nand_default_bbt (struct mtd_info *mtd);
 extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
 extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
+                             size_t * retlen, u_char * buf, u_char * oob_buf,
+                             struct nand_oobinfo *oobsel, int flags);
 
 /*
 * Constants for oob configuration
diff --git a/include/linux/mtd/plat-ram.h b/include/linux/mtd/plat-ram.h
new file mode 100644
index 000000000000..2332eda07e0e
--- /dev/null
+++ b/include/linux/mtd/plat-ram.h
@@ -0,0 +1,35 @@
+/* linux/include/mtd/plat-ram.h
+ *
+ * (c) 2004 Simtec Electronics
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Generic platform device based RAM map
+ *
+ * $Id: plat-ram.h,v 1.2 2005/01/24 00:37:40 bjd Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __LINUX_MTD_PLATRAM_H
+#define __LINUX_MTD_PLATRAM_H __FILE__
+
+#define PLATRAM_RO (0)
+#define PLATRAM_RW (1)
+
+struct platdata_mtd_ram {
+        char                    *mapname;
+        char                   **probes;
+        struct mtd_partition    *partitions;
+        int                      nr_partitions;
+        int                      bankwidth;
+
+        /* control callbacks */
+
+        void    (*set_rw)(struct device *dev, int to);
+};
+
+#endif /* __LINUX_MTD_PLATRAM_H */
diff --git a/include/linux/mtd/xip.h b/include/linux/mtd/xip.h
index fc071125cbcc..7b7deef6b180 100644
--- a/include/linux/mtd/xip.h
+++ b/include/linux/mtd/xip.h
@@ -58,22 +58,16 @@
  *              returned value is <= the real elapsed time.
  *      note 2: this should be able to cope with a few seconds without
  *              overflowing.
+ *
+ * xip_iprefetch()
+ *  
+ *      Macro to fill instruction prefetch
+ *      e.g. a series of nops:  asm volatile (".rep 8; nop; .endr"); 
  */
 
-#if defined(CONFIG_ARCH_SA1100) || defined(CONFIG_ARCH_PXA)
-
-#include <asm/hardware.h>
-#ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa-regs.h>
-#endif
-
-#define xip_irqpending()        (ICIP & ICMR)
-
-/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()          (OSCR)
-#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+#include <asm/mtd-xip.h>
 
-#else
+#ifndef xip_irqpending
 
 #warning "missing IRQ and timer primitives for XIP MTD support"
 #warning "some of the XIP MTD support code will be disabled"
@@ -85,16 +79,17 @@
 
 #endif
 
+#ifndef xip_iprefetch
+#define xip_iprefetch()         do { } while (0)
+#endif
+
 /*
  * xip_cpu_idle() is used when waiting for a delay equal or larger than
  * the system timer tick period.  This should put the CPU into idle mode
  * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
+ * This should not rely upon standard kernel code.
  */
-
-#if defined(CONFIG_CPU_XSCALE)
-#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
-#else
+#ifndef xip_cpu_idle
 #define xip_cpu_idle()  do { } while (0)
 #endif
 
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index 5773ea42f6e4..0b08cd692201 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -980,7 +980,7 @@
 /* I2C Registers                        */
 /****************************************/
 
-#define MV64XXX_I2C_CTLR_NAME                                   "mv64xxx i2c"
+#define MV64XXX_I2C_CTLR_NAME                                   "mv64xxx_i2c"
 #define MV64XXX_I2C_OFFSET                                          0xc000
 #define MV64XXX_I2C_REG_BLOCK_SIZE                                  0x0020
 
diff --git a/include/linux/namespace.h b/include/linux/namespace.h
index 9eca1558d72f..0e5a86f13b2f 100644
--- a/include/linux/namespace.h
+++ b/include/linux/namespace.h
@@ -12,13 +12,13 @@ struct namespace {
         struct rw_semaphore     sem;
 };
 
-extern void umount_tree(struct vfsmount *);
 extern int copy_namespace(int, struct task_struct *);
 extern void __put_namespace(struct namespace *namespace);
 
 static inline void put_namespace(struct namespace *namespace)
 {
-        if (atomic_dec_and_test(&namespace->count))
+        if (atomic_dec_and_lock(&namespace->count, &vfsmount_lock))
+                /* releases vfsmount_lock */
                 __put_namespace(namespace);
 }
 
diff --git a/include/linux/net.h b/include/linux/net.h
index 20cb226b2268..4e981585a89a 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -84,6 +84,7 @@ enum sock_type {
         SOCK_RAW        = 3,
         SOCK_RDM        = 4,
         SOCK_SEQPACKET  = 5,
+        SOCK_DCCP       = 6,
         SOCK_PACKET     = 10,
 };
 
@@ -282,5 +283,15 @@ static struct proto_ops name##_ops = {			\
 #define MODULE_ALIAS_NETPROTO(proto) \
         MODULE_ALIAS("net-pf-" __stringify(proto))
 
+#define MODULE_ALIAS_NET_PF_PROTO(pf, proto) \
+        MODULE_ALIAS("net-pf-" __stringify(pf) "-proto-" __stringify(proto))
+
+#ifdef CONFIG_SYSCTL
+#include <linux/sysctl.h>
+extern ctl_table net_table[];
+extern int net_msg_cost;
+extern int net_msg_burst;
+#endif
+
 #endif /* __KERNEL__ */
 #endif  /* _LINUX_NET_H */
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index ba5d1236aa17..7c717907896d 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -41,7 +41,7 @@
 struct divert_blk;
 struct vlan_group;
 struct ethtool_ops;
-struct netpoll;
+struct netpoll_info;
                                         /* source back-compat hooks */
 #define SET_ETHTOOL_OPS(netdev,ops) \
         ( (netdev)->ethtool_ops = (ops) )
@@ -164,12 +164,6 @@ struct netif_rx_stats
         unsigned total;
         unsigned dropped;
         unsigned time_squeeze;
-        unsigned throttled;
-        unsigned fastroute_hit;
-        unsigned fastroute_success;
-        unsigned fastroute_defer;
-        unsigned fastroute_deferred_out;
-        unsigned fastroute_latency_reduction;
         unsigned cpu_collision;
 };
 
@@ -250,6 +244,7 @@ struct netdev_boot_setup {
 };
 #define NETDEV_BOOT_SETUP_MAX 8
 
+extern int __init netdev_boot_setup(char *str);
 
 /*
  *      The DEVICE structure.
@@ -342,6 +337,7 @@ struct net_device
         /* Interface address info. */
         unsigned char           broadcast[MAX_ADDR_LEN];        /* hw bcast add */
         unsigned char           dev_addr[MAX_ADDR_LEN]; /* hw address   */
+        unsigned char           perm_addr[MAX_ADDR_LEN]; /* permanent hw address */
         unsigned char           addr_len;       /* hardware address length      */
         unsigned short          dev_id;         /* for shared network cards */
 
@@ -468,7 +464,7 @@ struct net_device
                                                      unsigned char *haddr);
         int                     (*neigh_setup)(struct net_device *dev, struct neigh_parms *);
 #ifdef CONFIG_NETPOLL
-        struct netpoll          *np;
+        struct netpoll_info     *npinfo;
 #endif
 #ifdef CONFIG_NET_POLL_CONTROLLER
         void                    (*poll_controller)(struct net_device *dev);
@@ -503,10 +499,12 @@ static inline void *netdev_priv(struct net_device *dev)
 #define SET_NETDEV_DEV(net, pdev)       ((net)->class_dev.dev = (pdev))
 
 struct packet_type {
-        __be16                  type;   /* This is really htons(ether_type).    */
-        struct net_device               *dev;   /* NULL is wildcarded here              */
-        int                     (*func) (struct sk_buff *, struct net_device *,
-                                         struct packet_type *);
+        __be16                  type;   /* This is really htons(ether_type). */
+        struct net_device       *dev;   /* NULL is wildcarded here           */
+        int                     (*func) (struct sk_buff *,
+                                         struct net_device *,
+                                         struct packet_type *,
+                                         struct net_device *);
         void                    *af_packet_priv;
         struct list_head        list;
 };
@@ -562,12 +560,9 @@ static inline int unregister_gifconf(unsigned int family)
 
 struct softnet_data
 {
-        int                     throttle;
-        int                     cng_level;
-        int                     avg_blog;
+        struct net_device       *output_queue;
         struct sk_buff_head     input_pkt_queue;
         struct list_head        poll_list;
-        struct net_device       *output_queue;
         struct sk_buff          *completion_queue;
 
         struct net_device       backlog_dev;    /* Sorry. 8) */
@@ -680,6 +675,7 @@ extern void		dev_queue_xmit_nit(struct sk_buff *skb, struct net_device *dev);
 extern void             dev_init(void);
 
 extern int              netdev_nit;
+extern int              netdev_budget;
 
 /* Called by rtnetlink.c:rtnl_unlock() */
 extern void netdev_run_todo(void);
@@ -706,19 +702,9 @@ static inline int netif_carrier_ok(const struct net_device *dev)
 
 extern void __netdev_watchdog_up(struct net_device *dev);
 
-static inline void netif_carrier_on(struct net_device *dev)
-{
-        if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->state))
-                linkwatch_fire_event(dev);
-        if (netif_running(dev))
-                __netdev_watchdog_up(dev);
-}
+extern void netif_carrier_on(struct net_device *dev);
 
-static inline void netif_carrier_off(struct net_device *dev)
-{
-        if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->state))
-                linkwatch_fire_event(dev);
-}
+extern void netif_carrier_off(struct net_device *dev);
 
 /* Hot-plugging. */
 static inline int netif_device_present(struct net_device *dev)
@@ -925,10 +911,14 @@ extern int skb_checksum_help(struct sk_buff *skb, int inward);
 extern void             net_enable_timestamp(void);
 extern void             net_disable_timestamp(void);
 
-#ifdef CONFIG_SYSCTL
-extern char *net_sysctl_strdup(const char *s);
+#ifdef CONFIG_PROC_FS
+extern void *dev_seq_start(struct seq_file *seq, loff_t *pos);
+extern void *dev_seq_next(struct seq_file *seq, void *v, loff_t *pos);
+extern void dev_seq_stop(struct seq_file *seq, void *v);
 #endif
 
+extern void linkwatch_run_queue(void);
+
 #endif /* __KERNEL__ */
 
 #endif  /* _LINUX_DEV_H */
diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h
index 2e2045482cb1..be365e70ee99 100644
--- a/include/linux/netfilter.h
+++ b/include/linux/netfilter.h
@@ -21,10 +21,23 @@
 #define NF_STOP 5
 #define NF_MAX_VERDICT NF_STOP
 
+/* we overload the higher bits for encoding auxiliary data such as the queue
+ * number. Not nice, but better than additional function arguments. */
+#define NF_VERDICT_MASK 0x0000ffff
+#define NF_VERDICT_BITS 16
+
+#define NF_VERDICT_QMASK 0xffff0000
+#define NF_VERDICT_QBITS 16
+
+#define NF_QUEUE_NR(x) (((x << NF_VERDICT_QBITS) & NF_VERDICT_QMASK) | NF_QUEUE)
+
+/* only for userspace compatibility */
+#ifndef __KERNEL__
 /* Generic cache responses from hook functions.
    <= 0x2000 is used for protocol-flags. */
 #define NFC_UNKNOWN 0x4000
 #define NFC_ALTERED 0x8000
+#endif
 
 #ifdef __KERNEL__
 #include <linux/config.h>
@@ -101,15 +114,51 @@ void nf_unregister_sockopt(struct nf_sockopt_ops *reg);
 
 extern struct list_head nf_hooks[NPROTO][NF_MAX_HOOKS];
 
-typedef void nf_logfn(unsigned int hooknum,
+/* those NF_LOG_* defines and struct nf_loginfo are legacy definitios that will
+ * disappear once iptables is replaced with pkttables.  Please DO NOT use them
+ * for any new code! */
+#define NF_LOG_TCPSEQ           0x01    /* Log TCP sequence numbers */
+#define NF_LOG_TCPOPT           0x02    /* Log TCP options */
+#define NF_LOG_IPOPT            0x04    /* Log IP options */
+#define NF_LOG_UID              0x08    /* Log UID owning local socket */
+#define NF_LOG_MASK             0x0f
+
+#define NF_LOG_TYPE_LOG         0x01
+#define NF_LOG_TYPE_ULOG        0x02
+
+struct nf_loginfo {
+        u_int8_t type;
+        union {
+                struct {
+                        u_int32_t copy_len;
+                        u_int16_t group;
+                        u_int16_t qthreshold;
+                } ulog;
+                struct {
+                        u_int8_t level;
+                        u_int8_t logflags;
+                } log;
+        } u;
+};
+
+typedef void nf_logfn(unsigned int pf,
+                      unsigned int hooknum,
                       const struct sk_buff *skb,
                       const struct net_device *in,
                       const struct net_device *out,
+                      const struct nf_loginfo *li,
                       const char *prefix);
 
+struct nf_logger {
+        struct module   *me;
+        nf_logfn        *logfn;
+        char            *name;
+};
+
 /* Function to register/unregister log function. */
-int nf_log_register(int pf, nf_logfn *logfn);
-void nf_log_unregister(int pf, nf_logfn *logfn);
+int nf_log_register(int pf, struct nf_logger *logger);
+int nf_log_unregister_pf(int pf);
+void nf_log_unregister_logger(struct nf_logger *logger);
 
 /* Calls the registered backend logging function */
 void nf_log_packet(int pf,
@@ -117,6 +166,7 @@ void nf_log_packet(int pf,
                    const struct sk_buff *skb,
                    const struct net_device *in,
                    const struct net_device *out,
+                   struct nf_loginfo *li,
                    const char *fmt, ...);
                    
 /* Activate hook; either okfn or kfree_skb called, unless a hook
@@ -175,11 +225,16 @@ int nf_getsockopt(struct sock *sk, int pf, int optval, char __user *opt,
                   int *len);
 
 /* Packet queuing */
-typedef int (*nf_queue_outfn_t)(struct sk_buff *skb, 
-                                struct nf_info *info, void *data);
+struct nf_queue_handler {
+        int (*outfn)(struct sk_buff *skb, struct nf_info *info,
+                     unsigned int queuenum, void *data);
+        void *data;
+        char *name;
+};
 extern int nf_register_queue_handler(int pf, 
-                                     nf_queue_outfn_t outfn, void *data);
+                                     struct nf_queue_handler *qh);
 extern int nf_unregister_queue_handler(int pf);
+extern void nf_unregister_queue_handlers(struct nf_queue_handler *qh);
 extern void nf_reinject(struct sk_buff *skb,
                         struct nf_info *info,
                         unsigned int verdict);
@@ -190,6 +245,27 @@ extern void nf_ct_attach(struct sk_buff *, struct sk_buff *);
 /* FIXME: Before cache is ever used, this must be implemented for real. */
 extern void nf_invalidate_cache(int pf);
 
+/* Call this before modifying an existing packet: ensures it is
+   modifiable and linear to the point you care about (writable_len).
+   Returns true or false. */
+extern int skb_make_writable(struct sk_buff **pskb, unsigned int writable_len);
+
+struct nf_queue_rerouter {
+        void (*save)(const struct sk_buff *skb, struct nf_info *info);
+        int (*reroute)(struct sk_buff **skb, const struct nf_info *info);
+        int rer_size;
+};
+
+#define nf_info_reroute(x) ((void *)x + sizeof(struct nf_info))
+
+extern int nf_register_queue_rerouter(int pf, struct nf_queue_rerouter *rer);
+extern int nf_unregister_queue_rerouter(int pf);
+
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+extern struct proc_dir_entry *proc_net_netfilter;
+#endif
+
 #else /* !CONFIG_NETFILTER */
 #define NF_HOOK(pf, hook, skb, indev, outdev, okfn) (okfn)(skb)
 static inline void nf_ct_attach(struct sk_buff *new, struct sk_buff *skb) {}
diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h
new file mode 100644
index 000000000000..1d5b10ae2399
--- /dev/null
+++ b/include/linux/netfilter/nfnetlink.h
@@ -0,0 +1,169 @@
+#ifndef _NFNETLINK_H
+#define _NFNETLINK_H
+#include <linux/types.h>
+
+#ifndef __KERNEL__
+/* nfnetlink groups: Up to 32 maximum - backwards compatibility for userspace */
+#define NF_NETLINK_CONNTRACK_NEW                0x00000001
+#define NF_NETLINK_CONNTRACK_UPDATE             0x00000002
+#define NF_NETLINK_CONNTRACK_DESTROY            0x00000004
+#define NF_NETLINK_CONNTRACK_EXP_NEW            0x00000008
+#define NF_NETLINK_CONNTRACK_EXP_UPDATE         0x00000010
+#define NF_NETLINK_CONNTRACK_EXP_DESTROY        0x00000020
+#endif
+
+enum nfnetlink_groups {
+        NFNLGRP_NONE,
+#define NFNLGRP_NONE                    NFNLGRP_NONE
+        NFNLGRP_CONNTRACK_NEW,
+#define NFNLGRP_CONNTRACK_NEW           NFNLGRP_CONNTRACK_NEW
+        NFNLGRP_CONNTRACK_UPDATE,
+#define NFNLGRP_CONNTRACK_UPDATE        NFNLGRP_CONNTRACK_UPDATE
+        NFNLGRP_CONNTRACK_DESTROY,
+#define NFNLGRP_CONNTRACK_DESTROY       NFNLGRP_CONNTRACK_DESTROY
+        NFNLGRP_CONNTRACK_EXP_NEW,
+#define NFNLGRP_CONNTRACK_EXP_NEW       NFNLGRP_CONNTRACK_EXP_NEW
+        NFNLGRP_CONNTRACK_EXP_UPDATE,
+#define NFNLGRP_CONNTRACK_EXP_UPDATE    NFNLGRP_CONNTRACK_EXP_UPDATE
+        NFNLGRP_CONNTRACK_EXP_DESTROY,
+#define NFNLGRP_CONNTRACK_EXP_DESTROY   NFNLGRP_CONNTRACK_EXP_DESTROY
+        __NFNLGRP_MAX,
+};
+#define NFNLGRP_MAX     (__NFNLGRP_MAX - 1)
+
+/* Generic structure for encapsulation optional netfilter information.
+ * It is reminiscent of sockaddr, but with sa_family replaced
+ * with attribute type. 
+ * ! This should someday be put somewhere generic as now rtnetlink and
+ * ! nfnetlink use the same attributes methods. - J. Schulist.
+ */
+
+struct nfattr
+{
+        u_int16_t nfa_len;
+        u_int16_t nfa_type;
+} __attribute__ ((packed));
+
+/* FIXME: Shamelessly copy and pasted from rtnetlink.h, it's time
+ *        to put this in a generic file */
+
+#define NFA_ALIGNTO     4
+#define NFA_ALIGN(len)  (((len) + NFA_ALIGNTO - 1) & ~(NFA_ALIGNTO - 1))
+#define NFA_OK(nfa,len) ((len) > 0 && (nfa)->nfa_len >= sizeof(struct nfattr) \
+        && (nfa)->nfa_len <= (len))
+#define NFA_NEXT(nfa,attrlen)   ((attrlen) -= NFA_ALIGN((nfa)->nfa_len), \
+        (struct nfattr *)(((char *)(nfa)) + NFA_ALIGN((nfa)->nfa_len)))
+#define NFA_LENGTH(len) (NFA_ALIGN(sizeof(struct nfattr)) + (len))
+#define NFA_SPACE(len)  NFA_ALIGN(NFA_LENGTH(len))
+#define NFA_DATA(nfa)   ((void *)(((char *)(nfa)) + NFA_LENGTH(0)))
+#define NFA_PAYLOAD(nfa) ((int)((nfa)->nfa_len) - NFA_LENGTH(0))
+#define NFA_NEST(skb, type) \
+({      struct nfattr *__start = (struct nfattr *) (skb)->tail; \
+        NFA_PUT(skb, type, 0, NULL); \
+        __start;  })
+#define NFA_NEST_END(skb, start) \
+({      (start)->nfa_len = ((skb)->tail - (unsigned char *) (start)); \
+        (skb)->len; })
+#define NFA_NEST_CANCEL(skb, start) \
+({      if (start) \
+                skb_trim(skb, (unsigned char *) (start) - (skb)->data); \
+        -1; })
+
+/* General form of address family dependent message.
+ */
+struct nfgenmsg {
+        u_int8_t  nfgen_family;         /* AF_xxx */
+        u_int8_t  version;              /* nfnetlink version */
+        u_int16_t res_id;               /* resource id */
+} __attribute__ ((packed));
+
+#define NFNETLINK_V0    0
+
+#define NFM_NFA(n)      ((struct nfattr *)(((char *)(n)) \
+        + NLMSG_ALIGN(sizeof(struct nfgenmsg))))
+#define NFM_PAYLOAD(n)  NLMSG_PAYLOAD(n, sizeof(struct nfgenmsg))
+
+/* netfilter netlink message types are split in two pieces:
+ * 8 bit subsystem, 8bit operation.
+ */
+
+#define NFNL_SUBSYS_ID(x)       ((x & 0xff00) >> 8)
+#define NFNL_MSG_TYPE(x)        (x & 0x00ff)
+
+/* No enum here, otherwise __stringify() trick of MODULE_ALIAS_NFNL_SUBSYS()
+ * won't work anymore */
+#define NFNL_SUBSYS_NONE                0
+#define NFNL_SUBSYS_CTNETLINK           1
+#define NFNL_SUBSYS_CTNETLINK_EXP       2
+#define NFNL_SUBSYS_QUEUE               3
+#define NFNL_SUBSYS_ULOG                4
+#define NFNL_SUBSYS_COUNT               5
+
+#ifdef __KERNEL__
+
+#include <linux/netlink.h>
+#include <linux/capability.h>
+
+struct nfnl_callback
+{
+        int (*call)(struct sock *nl, struct sk_buff *skb, 
+                struct nlmsghdr *nlh, struct nfattr *cda[], int *errp);
+        kernel_cap_t cap_required; /* capabilities required for this msg */
+        u_int16_t attr_count;   /* number of nfattr's */
+};
+
+struct nfnetlink_subsystem
+{
+        const char *name;
+        __u8 subsys_id;         /* nfnetlink subsystem ID */
+        __u8 cb_count;          /* number of callbacks */
+        struct nfnl_callback *cb; /* callback for individual types */
+};
+
+extern void __nfa_fill(struct sk_buff *skb, int attrtype,
+        int attrlen, const void *data);
+#define NFA_PUT(skb, attrtype, attrlen, data) \
+({ if (skb_tailroom(skb) < (int)NFA_SPACE(attrlen)) goto nfattr_failure; \
+   __nfa_fill(skb, attrtype, attrlen, data); })
+
+extern struct semaphore nfnl_sem;
+
+#define nfnl_shlock()           down(&nfnl_sem)
+#define nfnl_shlock_nowait()    down_trylock(&nfnl_sem)
+
+#define nfnl_shunlock()         do { up(&nfnl_sem); \
+                                     if(nfnl && nfnl->sk_receive_queue.qlen) \
+                                            nfnl->sk_data_ready(nfnl, 0); \
+                                } while(0)
+
+extern void nfnl_lock(void);
+extern void nfnl_unlock(void);
+
+extern int nfnetlink_subsys_register(struct nfnetlink_subsystem *n);
+extern int nfnetlink_subsys_unregister(struct nfnetlink_subsystem *n);
+
+extern int nfattr_parse(struct nfattr *tb[], int maxattr, 
+                        struct nfattr *nfa, int len);
+
+#define nfattr_parse_nested(tb, max, nfa) \
+        nfattr_parse((tb), (max), NFA_DATA((nfa)), NFA_PAYLOAD((nfa)))
+
+#define nfattr_bad_size(tb, max, cta_min)                               \
+({      int __i, __res = 0;                                             \
+        for (__i=0; __i<max; __i++)                                     \
+                if (tb[__i] && NFA_PAYLOAD(tb[__i]) < cta_min[__i]){    \
+                        __res = 1;                                      \
+                        break;                                          \
+                }                                                       \
+        __res;                                                          \
+})
+
+extern int nfnetlink_send(struct sk_buff *skb, u32 pid, unsigned group, 
+                          int echo);
+extern int nfnetlink_unicast(struct sk_buff *skb, u_int32_t pid, int flags);
+
+#define MODULE_ALIAS_NFNL_SUBSYS(subsys) \
+        MODULE_ALIAS("nfnetlink-subsys-" __stringify(subsys))
+
+#endif  /* __KERNEL__ */
+#endif  /* _NFNETLINK_H */
diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h
new file mode 100644
index 000000000000..5c55751c78e4
--- /dev/null
+++ b/include/linux/netfilter/nfnetlink_conntrack.h
@@ -0,0 +1,124 @@
+#ifndef _IPCONNTRACK_NETLINK_H
+#define _IPCONNTRACK_NETLINK_H
+#include <linux/netfilter/nfnetlink.h>
+
+enum cntl_msg_types {
+        IPCTNL_MSG_CT_NEW,
+        IPCTNL_MSG_CT_GET,
+        IPCTNL_MSG_CT_DELETE,
+        IPCTNL_MSG_CT_GET_CTRZERO,
+
+        IPCTNL_MSG_MAX
+};
+
+enum ctnl_exp_msg_types {
+        IPCTNL_MSG_EXP_NEW,
+        IPCTNL_MSG_EXP_GET,
+        IPCTNL_MSG_EXP_DELETE,
+
+        IPCTNL_MSG_EXP_MAX
+};
+
+
+enum ctattr_type {
+        CTA_UNSPEC,
+        CTA_TUPLE_ORIG,
+        CTA_TUPLE_REPLY,
+        CTA_STATUS,
+        CTA_PROTOINFO,
+        CTA_HELP,
+        CTA_NAT,
+        CTA_TIMEOUT,
+        CTA_MARK,
+        CTA_COUNTERS_ORIG,
+        CTA_COUNTERS_REPLY,
+        CTA_USE,
+        CTA_ID,
+        __CTA_MAX
+};
+#define CTA_MAX (__CTA_MAX - 1)
+
+enum ctattr_tuple {
+        CTA_TUPLE_UNSPEC,
+        CTA_TUPLE_IP,
+        CTA_TUPLE_PROTO,
+        __CTA_TUPLE_MAX
+};
+#define CTA_TUPLE_MAX (__CTA_TUPLE_MAX - 1)
+
+enum ctattr_ip {
+        CTA_IP_UNSPEC,
+        CTA_IP_V4_SRC,
+        CTA_IP_V4_DST,
+        CTA_IP_V6_SRC,
+        CTA_IP_V6_DST,
+        __CTA_IP_MAX
+};
+#define CTA_IP_MAX (__CTA_IP_MAX - 1)
+
+enum ctattr_l4proto {
+        CTA_PROTO_UNSPEC,
+        CTA_PROTO_NUM,
+        CTA_PROTO_SRC_PORT,
+        CTA_PROTO_DST_PORT,
+        CTA_PROTO_ICMP_ID,
+        CTA_PROTO_ICMP_TYPE,
+        CTA_PROTO_ICMP_CODE,
+        __CTA_PROTO_MAX
+};
+#define CTA_PROTO_MAX (__CTA_PROTO_MAX - 1)
+
+enum ctattr_protoinfo {
+        CTA_PROTOINFO_UNSPEC,
+        CTA_PROTOINFO_TCP_STATE,
+        __CTA_PROTOINFO_MAX
+};
+#define CTA_PROTOINFO_MAX (__CTA_PROTOINFO_MAX - 1)
+
+enum ctattr_counters {
+        CTA_COUNTERS_UNSPEC,
+        CTA_COUNTERS_PACKETS,
+        CTA_COUNTERS_BYTES,
+        __CTA_COUNTERS_MAX
+};
+#define CTA_COUNTERS_MAX (__CTA_COUNTERS_MAX - 1)
+
+enum ctattr_nat {
+        CTA_NAT_UNSPEC,
+        CTA_NAT_MINIP,
+        CTA_NAT_MAXIP,
+        CTA_NAT_PROTO,
+        __CTA_NAT_MAX
+};
+#define CTA_NAT_MAX (__CTA_NAT_MAX - 1)
+
+enum ctattr_protonat {
+        CTA_PROTONAT_UNSPEC,
+        CTA_PROTONAT_PORT_MIN,
+        CTA_PROTONAT_PORT_MAX,
+        __CTA_PROTONAT_MAX
+};
+#define CTA_PROTONAT_MAX (__CTA_PROTONAT_MAX - 1)
+
+enum ctattr_expect {
+        CTA_EXPECT_UNSPEC,
+        CTA_EXPECT_MASTER,
+        CTA_EXPECT_TUPLE,
+        CTA_EXPECT_MASK,
+        CTA_EXPECT_TIMEOUT,
+        CTA_EXPECT_ID,
+        CTA_EXPECT_HELP_NAME,
+        __CTA_EXPECT_MAX
+};
+#define CTA_EXPECT_MAX (__CTA_EXPECT_MAX - 1)
+
+enum ctattr_help {
+        CTA_HELP_UNSPEC,
+        CTA_HELP_NAME,
+        __CTA_HELP_MAX
+};
+#define CTA_HELP_MAX (__CTA_HELP_MAX - 1)
+
+#define CTA_HELP_MAXNAMESIZE    32
+
+#endif /* _IPCONNTRACK_NETLINK_H */
diff --git a/include/linux/netfilter/nfnetlink_log.h b/include/linux/netfilter/nfnetlink_log.h
new file mode 100644
index 000000000000..b04b03880595
--- /dev/null
+++ b/include/linux/netfilter/nfnetlink_log.h
@@ -0,0 +1,88 @@
+#ifndef _NFNETLINK_LOG_H
+#define _NFNETLINK_LOG_H
+
+/* This file describes the netlink messages (i.e. 'protocol packets'),
+ * and not any kind of function definitions.  It is shared between kernel and
+ * userspace.  Don't put kernel specific stuff in here */
+
+#include <linux/types.h>
+#include <linux/netfilter/nfnetlink.h>
+
+enum nfulnl_msg_types {
+        NFULNL_MSG_PACKET,              /* packet from kernel to userspace */
+        NFULNL_MSG_CONFIG,              /* connect to a particular queue */
+
+        NFULNL_MSG_MAX
+};
+
+struct nfulnl_msg_packet_hdr {
+        u_int16_t       hw_protocol;    /* hw protocol (network order) */
+        u_int8_t        hook;           /* netfilter hook */
+        u_int8_t        _pad;
+} __attribute__ ((packed));
+
+struct nfulnl_msg_packet_hw {
+        u_int16_t       hw_addrlen;
+        u_int16_t       _pad;
+        u_int8_t        hw_addr[8];
+} __attribute__ ((packed));
+
+struct nfulnl_msg_packet_timestamp {
+        aligned_u64     sec;
+        aligned_u64     usec;
+} __attribute__ ((packed));
+
+#define NFULNL_PREFIXLEN        30      /* just like old log target */
+
+enum nfulnl_attr_type {
+        NFULA_UNSPEC,
+        NFULA_PACKET_HDR,
+        NFULA_MARK,                     /* u_int32_t nfmark */
+        NFULA_TIMESTAMP,                /* nfulnl_msg_packet_timestamp */
+        NFULA_IFINDEX_INDEV,            /* u_int32_t ifindex */
+        NFULA_IFINDEX_OUTDEV,           /* u_int32_t ifindex */
+        NFULA_IFINDEX_PHYSINDEV,        /* u_int32_t ifindex */
+        NFULA_IFINDEX_PHYSOUTDEV,       /* u_int32_t ifindex */
+        NFULA_HWADDR,                   /* nfulnl_msg_packet_hw */
+        NFULA_PAYLOAD,                  /* opaque data payload */
+        NFULA_PREFIX,                   /* string prefix */
+        NFULA_UID,                      /* user id of socket */
+
+        __NFULA_MAX
+};
+#define NFULA_MAX (__NFULA_MAX - 1)
+
+enum nfulnl_msg_config_cmds {
+        NFULNL_CFG_CMD_NONE,
+        NFULNL_CFG_CMD_BIND,
+        NFULNL_CFG_CMD_UNBIND,
+        NFULNL_CFG_CMD_PF_BIND,
+        NFULNL_CFG_CMD_PF_UNBIND,
+};
+
+struct nfulnl_msg_config_cmd {
+        u_int8_t        command;        /* nfulnl_msg_config_cmds */
+} __attribute__ ((packed));
+
+struct nfulnl_msg_config_mode {
+        u_int32_t       copy_range;
+        u_int8_t        copy_mode;
+        u_int8_t        _pad;
+} __attribute__ ((packed));
+
+enum nfulnl_attr_config {
+        NFULA_CFG_UNSPEC,
+        NFULA_CFG_CMD,                  /* nfulnl_msg_config_cmd */
+        NFULA_CFG_MODE,                 /* nfulnl_msg_config_mode */
+        NFULA_CFG_NLBUFSIZ,             /* u_int32_t buffer size */
+        NFULA_CFG_TIMEOUT,              /* u_int32_t in 1/100 s */
+        NFULA_CFG_QTHRESH,              /* u_int32_t */
+        __NFULA_CFG_MAX
+};
+#define NFULA_CFG_MAX (__NFULA_CFG_MAX -1)
+
+#define NFULNL_COPY_NONE        0x00
+#define NFULNL_COPY_META        0x01
+#define NFULNL_COPY_PACKET      0x02
+
+#endif /* _NFNETLINK_LOG_H */
diff --git a/include/linux/netfilter/nfnetlink_queue.h b/include/linux/netfilter/nfnetlink_queue.h
new file mode 100644
index 000000000000..9e774373244c
--- /dev/null
+++ b/include/linux/netfilter/nfnetlink_queue.h
@@ -0,0 +1,89 @@
+#ifndef _NFNETLINK_QUEUE_H
+#define _NFNETLINK_QUEUE_H
+
+#include <linux/types.h>
+#include <linux/netfilter/nfnetlink.h>
+
+enum nfqnl_msg_types {
+        NFQNL_MSG_PACKET,               /* packet from kernel to userspace */
+        NFQNL_MSG_VERDICT,              /* verdict from userspace to kernel */
+        NFQNL_MSG_CONFIG,               /* connect to a particular queue */
+
+        NFQNL_MSG_MAX
+};
+
+struct nfqnl_msg_packet_hdr {
+        u_int32_t       packet_id;      /* unique ID of packet in queue */
+        u_int16_t       hw_protocol;    /* hw protocol (network order) */
+        u_int8_t        hook;           /* netfilter hook */
+} __attribute__ ((packed));
+
+struct nfqnl_msg_packet_hw {
+        u_int16_t       hw_addrlen;
+        u_int16_t       _pad;
+        u_int8_t        hw_addr[8];
+} __attribute__ ((packed));
+
+struct nfqnl_msg_packet_timestamp {
+        aligned_u64     sec;
+        aligned_u64     usec;
+} __attribute__ ((packed));
+
+enum nfqnl_attr_type {
+        NFQA_UNSPEC,
+        NFQA_PACKET_HDR,
+        NFQA_VERDICT_HDR,               /* nfqnl_msg_verdict_hrd */
+        NFQA_MARK,                      /* u_int32_t nfmark */
+        NFQA_TIMESTAMP,                 /* nfqnl_msg_packet_timestamp */
+        NFQA_IFINDEX_INDEV,             /* u_int32_t ifindex */
+        NFQA_IFINDEX_OUTDEV,            /* u_int32_t ifindex */
+        NFQA_IFINDEX_PHYSINDEV,         /* u_int32_t ifindex */
+        NFQA_IFINDEX_PHYSOUTDEV,        /* u_int32_t ifindex */
+        NFQA_HWADDR,                    /* nfqnl_msg_packet_hw */
+        NFQA_PAYLOAD,                   /* opaque data payload */
+
+        __NFQA_MAX
+};
+#define NFQA_MAX (__NFQA_MAX - 1)
+
+struct nfqnl_msg_verdict_hdr {
+        u_int32_t verdict;
+        u_int32_t id;
+} __attribute__ ((packed));
+
+
+enum nfqnl_msg_config_cmds {
+        NFQNL_CFG_CMD_NONE,
+        NFQNL_CFG_CMD_BIND,
+        NFQNL_CFG_CMD_UNBIND,
+        NFQNL_CFG_CMD_PF_BIND,
+        NFQNL_CFG_CMD_PF_UNBIND,
+};
+
+struct nfqnl_msg_config_cmd {
+        u_int8_t        command;        /* nfqnl_msg_config_cmds */
+        u_int8_t        _pad;
+        u_int16_t       pf;             /* AF_xxx for PF_[UN]BIND */
+} __attribute__ ((packed));
+
+enum nfqnl_config_mode {
+        NFQNL_COPY_NONE,
+        NFQNL_COPY_META,
+        NFQNL_COPY_PACKET,
+};
+
+struct nfqnl_msg_config_params {
+        u_int32_t       copy_range;
+        u_int8_t        copy_mode;      /* enum nfqnl_config_mode */
+} __attribute__ ((packed));
+
+
+enum nfqnl_attr_config {
+        NFQA_CFG_UNSPEC,
+        NFQA_CFG_CMD,                   /* nfqnl_msg_config_cmd */
+        NFQA_CFG_PARAMS,                /* nfqnl_msg_config_params */
+        __NFQA_CFG_MAX
+};
+#define NFQA_CFG_MAX (__NFQA_CFG_MAX-1)
+
+#endif /* _NFNETLINK_QUEUE_H */
diff --git a/include/linux/netfilter_decnet.h b/include/linux/netfilter_decnet.h
index 3064eec9cb8e..6f425369ee29 100644
--- a/include/linux/netfilter_decnet.h
+++ b/include/linux/netfilter_decnet.h
@@ -9,6 +9,8 @@
 
 #include <linux/netfilter.h>
 
+/* only for userspace compatibility */
+#ifndef __KERNEL__
 /* IP Cache bits. */
 /* Src IP address. */
 #define NFC_DN_SRC              0x0001
@@ -18,6 +20,7 @@
 #define NFC_DN_IF_IN            0x0004
 /* Output device. */
 #define NFC_DN_IF_OUT           0x0008
+#endif /* ! __KERNEL__ */
 
 /* DECnet Hooks */
 /* After promisc drops, checksum checks. */
@@ -53,7 +56,21 @@ struct nf_dn_rtmsg {
 
 #define NFDN_RTMSG(r) ((unsigned char *)(r) + NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg)))
 
+#ifndef __KERNEL__
+/* backwards compatibility for userspace */
 #define DNRMG_L1_GROUP 0x01
 #define DNRMG_L2_GROUP 0x02
+#endif
+
+enum {
+        DNRNG_NLGRP_NONE,
+#define DNRNG_NLGRP_NONE        DNRNG_NLGRP_NONE
+        DNRNG_NLGRP_L1,
+#define DNRNG_NLGRP_L1          DNRNG_NLGRP_L1
+        DNRNG_NLGRP_L2,
+#define DNRNG_NLGRP_L2          DNRNG_NLGRP_L2
+        __DNRNG_NLGRP_MAX
+};
+#define DNRNG_NLGRP_MAX (__DNRNG_NLGRP_MAX - 1)
 
 #endif /*__LINUX_DECNET_NETFILTER_H*/
diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h
index 9e5750079e09..fdc4a9527343 100644
--- a/include/linux/netfilter_ipv4.h
+++ b/include/linux/netfilter_ipv4.h
@@ -8,6 +8,8 @@
 #include <linux/config.h>
 #include <linux/netfilter.h>
 
+/* only for userspace compatibility */
+#ifndef __KERNEL__
 /* IP Cache bits. */
 /* Src IP address. */
 #define NFC_IP_SRC              0x0001
@@ -35,6 +37,7 @@
 #define NFC_IP_DST_PT           0x0400
 /* Something else about the proto */
 #define NFC_IP_PROTO_UNKNOWN    0x2000
+#endif /* ! __KERNEL__ */
 
 /* IP Hooks */
 /* After promisc drops, checksum checks. */
@@ -75,19 +78,8 @@ enum nf_ip_hook_priorities {
 #define SO_ORIGINAL_DST 80
 
 #ifdef __KERNEL__
-#ifdef CONFIG_NETFILTER_DEBUG
-void nf_debug_ip_local_deliver(struct sk_buff *skb);
-void nf_debug_ip_loopback_xmit(struct sk_buff *newskb);
-void nf_debug_ip_finish_output2(struct sk_buff *skb);
-#endif /*CONFIG_NETFILTER_DEBUG*/
-
 extern int ip_route_me_harder(struct sk_buff **pskb);
 
-/* Call this before modifying an existing IP packet: ensures it is
-   modifiable and linear to the point you care about (writable_len).
-   Returns true or false. */
-extern int skb_ip_make_writable(struct sk_buff **pskb,
-                                unsigned int writable_len);
 #endif /*__KERNEL__*/
 
 #endif /*__LINUX_IP_NETFILTER_H*/
diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h
index 3781192ce159..7e033e9271a8 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack.h
@@ -65,6 +65,63 @@ enum ip_conntrack_status {
 
         /* Both together */
         IPS_NAT_DONE_MASK = (IPS_DST_NAT_DONE | IPS_SRC_NAT_DONE),
+
+        /* Connection is dying (removed from lists), can not be unset. */
+        IPS_DYING_BIT = 9,
+        IPS_DYING = (1 << IPS_DYING_BIT),
+};
+
+/* Connection tracking event bits */
+enum ip_conntrack_events
+{
+        /* New conntrack */
+        IPCT_NEW_BIT = 0,
+        IPCT_NEW = (1 << IPCT_NEW_BIT),
+
+        /* Expected connection */
+        IPCT_RELATED_BIT = 1,
+        IPCT_RELATED = (1 << IPCT_RELATED_BIT),
+
+        /* Destroyed conntrack */
+        IPCT_DESTROY_BIT = 2,
+        IPCT_DESTROY = (1 << IPCT_DESTROY_BIT),
+
+        /* Timer has been refreshed */
+        IPCT_REFRESH_BIT = 3,
+        IPCT_REFRESH = (1 << IPCT_REFRESH_BIT),
+
+        /* Status has changed */
+        IPCT_STATUS_BIT = 4,
+        IPCT_STATUS = (1 << IPCT_STATUS_BIT),
+
+        /* Update of protocol info */
+        IPCT_PROTOINFO_BIT = 5,
+        IPCT_PROTOINFO = (1 << IPCT_PROTOINFO_BIT),
+
+        /* Volatile protocol info */
+        IPCT_PROTOINFO_VOLATILE_BIT = 6,
+        IPCT_PROTOINFO_VOLATILE = (1 << IPCT_PROTOINFO_VOLATILE_BIT),
+
+        /* New helper for conntrack */
+        IPCT_HELPER_BIT = 7,
+        IPCT_HELPER = (1 << IPCT_HELPER_BIT),
+
+        /* Update of helper info */
+        IPCT_HELPINFO_BIT = 8,
+        IPCT_HELPINFO = (1 << IPCT_HELPINFO_BIT),
+
+        /* Volatile helper info */
+        IPCT_HELPINFO_VOLATILE_BIT = 9,
+        IPCT_HELPINFO_VOLATILE = (1 << IPCT_HELPINFO_VOLATILE_BIT),
+
+        /* NAT info */
+        IPCT_NATINFO_BIT = 10,
+        IPCT_NATINFO = (1 << IPCT_NATINFO_BIT),
+};
+
+enum ip_conntrack_expect_events {
+        IPEXP_NEW_BIT = 0,
+        IPEXP_NEW = (1 << IPEXP_NEW_BIT),
 };
 
 #ifdef __KERNEL__
@@ -152,6 +209,9 @@ struct ip_conntrack
         /* Current number of expected connections */
         unsigned int expecting;
 
+        /* Unique ID that identifies this conntrack*/
+        unsigned int id;
+
         /* Helper, if any. */
         struct ip_conntrack_helper *helper;
 
@@ -171,7 +231,7 @@ struct ip_conntrack
 #endif /* CONFIG_IP_NF_NAT_NEEDED */
 
 #if defined(CONFIG_IP_NF_CONNTRACK_MARK)
-        unsigned long mark;
+        u_int32_t mark;
 #endif
 
         /* Traversed often, so hopefully in different cacheline to top */
@@ -197,6 +257,15 @@ struct ip_conntrack_expect
         /* Timer function; deletes the expectation. */
         struct timer_list timeout;
 
+        /* Usage count. */
+        atomic_t use;
+
+        /* Unique ID */
+        unsigned int id;
+
+        /* Flags */
+        unsigned int flags;
+
 #ifdef CONFIG_IP_NF_NAT_NEEDED
         /* This is the original per-proto part, used to map the
          * expected connection the way the recipient expects. */
@@ -206,6 +275,8 @@ struct ip_conntrack_expect
 #endif
 };
 
+#define IP_CT_EXPECT_PERMANENT  0x1
+
 static inline struct ip_conntrack *
 tuplehash_to_ctrack(const struct ip_conntrack_tuple_hash *hash)
 {
@@ -236,7 +307,12 @@ ip_conntrack_get(const struct sk_buff *skb, enum ip_conntrack_info *ctinfo)
 }
 
 /* decrement reference count on a conntrack */
-extern inline void ip_conntrack_put(struct ip_conntrack *ct);
+static inline void
+ip_conntrack_put(struct ip_conntrack *ct)
+{
+        IP_NF_ASSERT(ct);
+        nf_conntrack_put(&ct->ct_general);
+}
 
 /* call to create an explicit dependency on ip_conntrack. */
 extern void need_ip_conntrack(void);
@@ -271,12 +347,50 @@ extern void
 ip_ct_iterate_cleanup(int (*iter)(struct ip_conntrack *i, void *data),
                       void *data);
 
+extern struct ip_conntrack_helper *
+__ip_conntrack_helper_find_byname(const char *);
+extern struct ip_conntrack_helper *
+ip_conntrack_helper_find_get(const struct ip_conntrack_tuple *tuple);
+extern void ip_conntrack_helper_put(struct ip_conntrack_helper *helper);
+
+extern struct ip_conntrack_protocol *
+__ip_conntrack_proto_find(u_int8_t protocol);
+extern struct ip_conntrack_protocol *
+ip_conntrack_proto_find_get(u_int8_t protocol);
+extern void ip_conntrack_proto_put(struct ip_conntrack_protocol *proto);
+
+extern void ip_ct_remove_expectations(struct ip_conntrack *ct);
+
+extern struct ip_conntrack *ip_conntrack_alloc(struct ip_conntrack_tuple *,
+                                               struct ip_conntrack_tuple *);
+
+extern void ip_conntrack_free(struct ip_conntrack *ct);
+
+extern void ip_conntrack_hash_insert(struct ip_conntrack *ct);
+
+extern struct ip_conntrack_expect *
+__ip_conntrack_expect_find(const struct ip_conntrack_tuple *tuple);
+
+extern struct ip_conntrack_expect *
+ip_conntrack_expect_find_get(const struct ip_conntrack_tuple *tuple);
+
+extern struct ip_conntrack_tuple_hash *
+__ip_conntrack_find(const struct ip_conntrack_tuple *tuple,
+                    const struct ip_conntrack *ignored_conntrack);
+
+extern void ip_conntrack_flush(void);
+
 /* It's confirmed if it is, or has been in the hash table. */
 static inline int is_confirmed(struct ip_conntrack *ct)
 {
         return test_bit(IPS_CONFIRMED_BIT, &ct->status);
 }
 
+static inline int is_dying(struct ip_conntrack *ct)
+{
+        return test_bit(IPS_DYING_BIT, &ct->status);
+}
+
 extern unsigned int ip_conntrack_htable_size;
  
 struct ip_conntrack_stat
@@ -300,6 +414,85 @@ struct ip_conntrack_stat
 
 #define CONNTRACK_STAT_INC(count) (__get_cpu_var(ip_conntrack_stat).count++)
 
+#ifdef CONFIG_IP_NF_CONNTRACK_EVENTS
+#include <linux/notifier.h>
+#include <linux/interrupt.h>
+
+struct ip_conntrack_ecache {
+        struct ip_conntrack *ct;
+        unsigned int events;
+};
+DECLARE_PER_CPU(struct ip_conntrack_ecache, ip_conntrack_ecache);
+
+#define CONNTRACK_ECACHE(x)     (__get_cpu_var(ip_conntrack_ecache).x)
+ 
+extern struct notifier_block *ip_conntrack_chain;
+extern struct notifier_block *ip_conntrack_expect_chain;
+
+static inline int ip_conntrack_register_notifier(struct notifier_block *nb)
+{
+        return notifier_chain_register(&ip_conntrack_chain, nb);
+}
+
+static inline int ip_conntrack_unregister_notifier(struct notifier_block *nb)
+{
+        return notifier_chain_unregister(&ip_conntrack_chain, nb);
+}
+
+static inline int 
+ip_conntrack_expect_register_notifier(struct notifier_block *nb)
+{
+        return notifier_chain_register(&ip_conntrack_expect_chain, nb);
+}
+
+static inline int
+ip_conntrack_expect_unregister_notifier(struct notifier_block *nb)
+{
+        return notifier_chain_unregister(&ip_conntrack_expect_chain, nb);
+}
+
+extern void ip_ct_deliver_cached_events(const struct ip_conntrack *ct);
+extern void __ip_ct_event_cache_init(struct ip_conntrack *ct);
+
+static inline void 
+ip_conntrack_event_cache(enum ip_conntrack_events event,
+                         const struct sk_buff *skb)
+{
+        struct ip_conntrack *ct = (struct ip_conntrack *)skb->nfct;
+        struct ip_conntrack_ecache *ecache;
+        
+        local_bh_disable();
+        ecache = &__get_cpu_var(ip_conntrack_ecache);
+        if (ct != ecache->ct)
+                __ip_ct_event_cache_init(ct);
+        ecache->events |= event;
+        local_bh_enable();
+}
+
+static inline void ip_conntrack_event(enum ip_conntrack_events event,
+                                      struct ip_conntrack *ct)
+{
+        if (is_confirmed(ct) && !is_dying(ct))
+                notifier_call_chain(&ip_conntrack_chain, event, ct);
+}
+
+static inline void 
+ip_conntrack_expect_event(enum ip_conntrack_expect_events event,
+                          struct ip_conntrack_expect *exp)
+{
+        notifier_call_chain(&ip_conntrack_expect_chain, event, exp);
+}
+#else /* CONFIG_IP_NF_CONNTRACK_EVENTS */
+static inline void ip_conntrack_event_cache(enum ip_conntrack_events event, 
+                                            const struct sk_buff *skb) {}
+static inline void ip_conntrack_event(enum ip_conntrack_events event, 
+                                      struct ip_conntrack *ct) {}
+static inline void ip_ct_deliver_cached_events(const struct ip_conntrack *ct) {}
+static inline void 
+ip_conntrack_expect_event(enum ip_conntrack_expect_events event, 
+                          struct ip_conntrack_expect *exp) {}
+#endif /* CONFIG_IP_NF_CONNTRACK_EVENTS */
+
 #ifdef CONFIG_IP_NF_NAT_NEEDED
 static inline int ip_nat_initialized(struct ip_conntrack *conntrack,
                                      enum ip_nat_manip_type manip)
diff --git a/include/linux/netfilter_ipv4/ip_conntrack_core.h b/include/linux/netfilter_ipv4/ip_conntrack_core.h
index d84be02cb4fc..907d4f5ca5dc 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack_core.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack_core.h
@@ -1,7 +1,9 @@
 #ifndef _IP_CONNTRACK_CORE_H
 #define _IP_CONNTRACK_CORE_H
 #include <linux/netfilter.h>
-#include <linux/netfilter_ipv4/lockhelp.h>
+
+#define MAX_IP_CT_PROTO 256
+extern struct ip_conntrack_protocol *ip_ct_protos[MAX_IP_CT_PROTO];
 
 /* This header is used to share core functionality between the
    standalone connection tracking module, and the compatibility layer's use
@@ -39,14 +41,21 @@ extern int __ip_conntrack_confirm(struct sk_buff **pskb);
 /* Confirm a connection: returns NF_DROP if packet must be dropped. */
 static inline int ip_conntrack_confirm(struct sk_buff **pskb)
 {
-        if ((*pskb)->nfct
-            && !is_confirmed((struct ip_conntrack *)(*pskb)->nfct))
-                return __ip_conntrack_confirm(pskb);
-        return NF_ACCEPT;
+        struct ip_conntrack *ct = (struct ip_conntrack *)(*pskb)->nfct;
+        int ret = NF_ACCEPT;
+
+        if (ct) {
+                if (!is_confirmed(ct))
+                        ret = __ip_conntrack_confirm(pskb);
+                ip_ct_deliver_cached_events(ct);
+        }
+        return ret;
 }
 
+extern void ip_ct_unlink_expect(struct ip_conntrack_expect *exp);
+
 extern struct list_head *ip_conntrack_hash;
 extern struct list_head ip_conntrack_expect_list;
-DECLARE_RWLOCK_EXTERN(ip_conntrack_lock);
+extern rwlock_t ip_conntrack_lock;
 #endif /* _IP_CONNTRACK_CORE_H */
 
diff --git a/include/linux/netfilter_ipv4/ip_conntrack_helper.h b/include/linux/netfilter_ipv4/ip_conntrack_helper.h
index b1bbba0a12cb..8d69279ccfe4 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack_helper.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack_helper.h
@@ -24,15 +24,18 @@ struct ip_conntrack_helper
         int (*help)(struct sk_buff **pskb,
                     struct ip_conntrack *ct,
                     enum ip_conntrack_info conntrackinfo);
+
+        int (*to_nfattr)(struct sk_buff *skb, const struct ip_conntrack *ct);
 };
 
 extern int ip_conntrack_helper_register(struct ip_conntrack_helper *);
 extern void ip_conntrack_helper_unregister(struct ip_conntrack_helper *);
 
 /* Allocate space for an expectation: this is mandatory before calling 
-   ip_conntrack_expect_related. */
-extern struct ip_conntrack_expect *ip_conntrack_expect_alloc(void);
-extern void ip_conntrack_expect_free(struct ip_conntrack_expect *exp);
+   ip_conntrack_expect_related.  You will have to call put afterwards. */
+extern struct ip_conntrack_expect *
+ip_conntrack_expect_alloc(struct ip_conntrack *master);
+extern void ip_conntrack_expect_put(struct ip_conntrack_expect *exp);
 
 /* Add an expected connection: can have more than one per connection */
 extern int ip_conntrack_expect_related(struct ip_conntrack_expect *exp);
diff --git a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h
index e20b57c5e1b7..b6b99be8632a 100644
--- a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h
+++ b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h
@@ -2,6 +2,7 @@
 #ifndef _IP_CONNTRACK_PROTOCOL_H
 #define _IP_CONNTRACK_PROTOCOL_H
 #include <linux/netfilter_ipv4/ip_conntrack.h>
+#include <linux/netfilter/nfnetlink_conntrack.h>
 
 struct seq_file;
 
@@ -47,22 +48,22 @@ struct ip_conntrack_protocol
         int (*error)(struct sk_buff *skb, enum ip_conntrack_info *ctinfo,
                      unsigned int hooknum);
 
+        /* convert protoinfo to nfnetink attributes */
+        int (*to_nfattr)(struct sk_buff *skb, struct nfattr *nfa,
+                         const struct ip_conntrack *ct);
+
+        int (*tuple_to_nfattr)(struct sk_buff *skb,
+                               const struct ip_conntrack_tuple *t);
+        int (*nfattr_to_tuple)(struct nfattr *tb[],
+                               struct ip_conntrack_tuple *t);
+
         /* Module (if any) which this is connected to. */
         struct module *me;
 };
 
-#define MAX_IP_CT_PROTO 256
-extern struct ip_conntrack_protocol *ip_ct_protos[MAX_IP_CT_PROTO];
-
 /* Protocol registration. */
 extern int ip_conntrack_protocol_register(struct ip_conntrack_protocol *proto);
 extern void ip_conntrack_protocol_unregister(struct ip_conntrack_protocol *proto);
-
-static inline struct ip_conntrack_protocol *ip_ct_find_proto(u_int8_t protocol)
-{
-        return ip_ct_protos[protocol];
-}
-
 /* Existing built-in protocols */
 extern struct ip_conntrack_protocol ip_conntrack_protocol_tcp;
 extern struct ip_conntrack_protocol ip_conntrack_protocol_udp;
@@ -73,6 +74,11 @@ extern int ip_conntrack_protocol_tcp_init(void);
 /* Log invalid packets */
 extern unsigned int ip_ct_log_invalid;
 
+extern int ip_ct_port_tuple_to_nfattr(struct sk_buff *,
+                                      const struct ip_conntrack_tuple *);
+extern int ip_ct_port_nfattr_to_tuple(struct nfattr *tb[],
+                                      struct ip_conntrack_tuple *);
+
 #ifdef CONFIG_SYSCTL
 #ifdef DEBUG_INVALID_PACKETS
 #define LOG_INVALID(proto) \
diff --git a/include/linux/netfilter_ipv4/ip_logging.h b/include/linux/netfilter_ipv4/ip_logging.h
deleted file mode 100644
index 0c5c52cb6589..000000000000
--- a/include/linux/netfilter_ipv4/ip_logging.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* IPv4 macros for the internal logging interface. */
-#ifndef __IP_LOGGING_H
-#define __IP_LOGGING_H
-
-#ifdef __KERNEL__
-#include <linux/socket.h>
-#include <linux/netfilter_logging.h>
-
-#define nf_log_ip_packet(pskb,hooknum,in,out,fmt,args...) \
-        nf_log_packet(AF_INET,pskb,hooknum,in,out,fmt,##args)
-
-#define nf_log_ip(pfh,len,fmt,args...) \
-        nf_log(AF_INET,pfh,len,fmt,##args)
-
-#define nf_ip_log_register(logging) nf_log_register(AF_INET,logging)
-#define nf_ip_log_unregister(logging) nf_log_unregister(AF_INET,logging)
-        
-#endif /*__KERNEL__*/
-
-#endif /*__IP_LOGGING_H*/
diff --git a/include/linux/netfilter_ipv4/ip_nat.h b/include/linux/netfilter_ipv4/ip_nat.h
index 2b72b86176f0..e201ec6e9905 100644
--- a/include/linux/netfilter_ipv4/ip_nat.h
+++ b/include/linux/netfilter_ipv4/ip_nat.h
@@ -50,10 +50,9 @@ struct ip_nat_multi_range_compat
 
 #ifdef __KERNEL__
 #include <linux/list.h>
-#include <linux/netfilter_ipv4/lockhelp.h>
 
 /* Protects NAT hash tables, and NAT-private part of conntracks. */
-DECLARE_RWLOCK_EXTERN(ip_nat_lock);
+extern rwlock_t ip_nat_lock;
 
 /* The structure embedded in the conntrack structure. */
 struct ip_nat_info
diff --git a/include/linux/netfilter_ipv4/ip_nat_protocol.h b/include/linux/netfilter_ipv4/ip_nat_protocol.h
index 129708c22386..ef63aa991a06 100644
--- a/include/linux/netfilter_ipv4/ip_nat_protocol.h
+++ b/include/linux/netfilter_ipv4/ip_nat_protocol.h
@@ -4,6 +4,9 @@
 #include <linux/init.h>
 #include <linux/list.h>
 
+#include <linux/netfilter_ipv4/ip_nat.h>
+#include <linux/netfilter/nfnetlink_conntrack.h>
+
 struct iphdr;
 struct ip_nat_range;
 
@@ -15,6 +18,8 @@ struct ip_nat_protocol
         /* Protocol number. */
         unsigned int protonum;
 
+        struct module *me;
+
         /* Translate a packet to the target according to manip type.
            Return true if succeeded. */
         int (*manip_pkt)(struct sk_buff **pskb,
@@ -43,19 +48,20 @@ struct ip_nat_protocol
 
         unsigned int (*print_range)(char *buffer,
                                     const struct ip_nat_range *range);
-};
 
-#define MAX_IP_NAT_PROTO 256
-extern struct ip_nat_protocol *ip_nat_protos[MAX_IP_NAT_PROTO];
+        int (*range_to_nfattr)(struct sk_buff *skb,
+                               const struct ip_nat_range *range);
+
+        int (*nfattr_to_range)(struct nfattr *tb[],
+                               struct ip_nat_range *range);
+};
 
 /* Protocol registration. */
 extern int ip_nat_protocol_register(struct ip_nat_protocol *proto);
 extern void ip_nat_protocol_unregister(struct ip_nat_protocol *proto);
 
-static inline struct ip_nat_protocol *ip_nat_find_proto(u_int8_t protocol)
-{
-        return ip_nat_protos[protocol];
-}
+extern struct ip_nat_protocol *ip_nat_proto_find_get(u_int8_t protocol);
+extern void ip_nat_proto_put(struct ip_nat_protocol *proto);
 
 /* Built-in protocols. */
 extern struct ip_nat_protocol ip_nat_protocol_tcp;
@@ -67,4 +73,9 @@ extern int init_protocols(void) __init;
 extern void cleanup_protocols(void);
 extern struct ip_nat_protocol *find_nat_proto(u_int16_t protonum);
 
+extern int ip_nat_port_range_to_nfattr(struct sk_buff *skb,
+                                       const struct ip_nat_range *range);
+extern int ip_nat_port_nfattr_to_range(struct nfattr *tb[],
+                                       struct ip_nat_range *range);
+
 #endif /*_IP_NAT_PROTO_H*/
diff --git a/include/linux/netfilter_ipv4/ip_nat_rule.h b/include/linux/netfilter_ipv4/ip_nat_rule.h
index fecd2a06dcd8..73b9552e6a89 100644
--- a/include/linux/netfilter_ipv4/ip_nat_rule.h
+++ b/include/linux/netfilter_ipv4/ip_nat_rule.h
@@ -19,5 +19,10 @@ extern unsigned int
 alloc_null_binding(struct ip_conntrack *conntrack,
                    struct ip_nat_info *info,
                    unsigned int hooknum);
+
+extern unsigned int
+alloc_null_binding_confirmed(struct ip_conntrack *conntrack,
+                             struct ip_nat_info *info,
+                             unsigned int hooknum);
 #endif
 #endif /* _IP_NAT_RULE_H */
diff --git a/include/linux/netfilter_ipv4/ip_tables.h b/include/linux/netfilter_ipv4/ip_tables.h
index 12ce47808e7d..d19d65cf4530 100644
--- a/include/linux/netfilter_ipv4/ip_tables.h
+++ b/include/linux/netfilter_ipv4/ip_tables.h
@@ -109,7 +109,8 @@ struct ipt_counters
 
 /* Values for "flag" field in struct ipt_ip (general ip structure). */
 #define IPT_F_FRAG              0x01    /* Set if rule is a fragment rule */
-#define IPT_F_MASK              0x01    /* All possible flag bits mask. */
+#define IPT_F_GOTO              0x02    /* Set if jump is a goto */
+#define IPT_F_MASK              0x03    /* All possible flag bits mask. */
 
 /* Values for "inv" field in struct ipt_ip. */
 #define IPT_INV_VIA_IN          0x01    /* Invert the sense of IN IFACE. */
diff --git a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
index baa83e757156..d9bceedfb3dc 100644
--- a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
+++ b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
@@ -18,7 +18,6 @@ struct clusterip_config;
 struct ipt_clusterip_tgt_info {
 
         u_int32_t flags;
-        struct clusterip_config *config;
         
         /* only relevant for new ones */
         u_int8_t clustermac[6];
@@ -27,6 +26,8 @@ struct ipt_clusterip_tgt_info {
         u_int16_t local_nodes[CLUSTERIP_MAX_NODES];
         enum clusterip_hashmode hash_mode;
         u_int32_t hash_initval;
+
+        struct clusterip_config *config;
 };
 
 #endif /*_IPT_CLUSTERIP_H_target*/
diff --git a/include/linux/netfilter_ipv4/ipt_LOG.h b/include/linux/netfilter_ipv4/ipt_LOG.h
index d25f782e57d1..22d16177319b 100644
--- a/include/linux/netfilter_ipv4/ipt_LOG.h
+++ b/include/linux/netfilter_ipv4/ipt_LOG.h
@@ -1,6 +1,7 @@
 #ifndef _IPT_LOG_H
 #define _IPT_LOG_H
 
+/* make sure not to change this without changing netfilter.h:NF_LOG_* (!) */
 #define IPT_LOG_TCPSEQ          0x01    /* Log TCP sequence numbers */
 #define IPT_LOG_TCPOPT          0x02    /* Log TCP options */
 #define IPT_LOG_IPOPT           0x04    /* Log IP options */
diff --git a/include/linux/netfilter_ipv4/ipt_NFQUEUE.h b/include/linux/netfilter_ipv4/ipt_NFQUEUE.h
new file mode 100644
index 000000000000..b5b2943b0c66
--- /dev/null
+++ b/include/linux/netfilter_ipv4/ipt_NFQUEUE.h
@@ -0,0 +1,16 @@
+/* iptables module for using NFQUEUE mechanism
+ *
+ * (C) 2005 Harald Welte <laforge@netfilter.org>
+ *
+ * This software is distributed under GNU GPL v2, 1991
+ * 
+*/
+#ifndef _IPT_NFQ_TARGET_H
+#define _IPT_NFQ_TARGET_H
+
+/* target info */
+struct ipt_NFQ_info {
+        u_int16_t queuenum;
+};
+
+#endif /* _IPT_DSCP_TARGET_H */
diff --git a/include/linux/netfilter_ipv4/ipt_TTL.h b/include/linux/netfilter_ipv4/ipt_TTL.h
new file mode 100644
index 000000000000..ee6611edc112
--- /dev/null
+++ b/include/linux/netfilter_ipv4/ipt_TTL.h
@@ -0,0 +1,21 @@
+/* TTL modification module for IP tables
+ * (C) 2000 by Harald Welte <laforge@netfilter.org> */
+
+#ifndef _IPT_TTL_H
+#define _IPT_TTL_H
+
+enum {
+        IPT_TTL_SET = 0,
+        IPT_TTL_INC,
+        IPT_TTL_DEC
+};
+
+#define IPT_TTL_MAXMODE IPT_TTL_DEC
+
+struct ipt_TTL_info {
+        u_int8_t        mode;
+        u_int8_t        ttl;
+};
+
+
+#endif
diff --git a/include/linux/netfilter_ipv4/ipt_connbytes.h b/include/linux/netfilter_ipv4/ipt_connbytes.h
new file mode 100644
index 000000000000..9e5532f8d8ac
--- /dev/null
+++ b/include/linux/netfilter_ipv4/ipt_connbytes.h
@@ -0,0 +1,25 @@
+#ifndef _IPT_CONNBYTES_H
+#define _IPT_CONNBYTES_H
+
+enum ipt_connbytes_what {
+        IPT_CONNBYTES_PKTS,
+        IPT_CONNBYTES_BYTES,
+        IPT_CONNBYTES_AVGPKT,
+};
+
+enum ipt_connbytes_direction {
+        IPT_CONNBYTES_DIR_ORIGINAL,
+        IPT_CONNBYTES_DIR_REPLY,
+        IPT_CONNBYTES_DIR_BOTH,
+};
+
+struct ipt_connbytes_info
+{
+        struct {
+                aligned_u64 from;       /* count to be matched */
+                aligned_u64 to;         /* count to be matched */
+        } count;
+        u_int8_t what;          /* ipt_connbytes_what */
+        u_int8_t direction;     /* ipt_connbytes_direction */
+};
+#endif
diff --git a/include/linux/netfilter_ipv4/ipt_dccp.h b/include/linux/netfilter_ipv4/ipt_dccp.h
new file mode 100644
index 000000000000..3cb3a522e62b
--- /dev/null
+++ b/include/linux/netfilter_ipv4/ipt_dccp.h
@@ -0,0 +1,23 @@
+#ifndef _IPT_DCCP_H_
+#define _IPT_DCCP_H_
+
+#define IPT_DCCP_SRC_PORTS              0x01
+#define IPT_DCCP_DEST_PORTS             0x02
+#define IPT_DCCP_TYPE                   0x04
+#define IPT_DCCP_OPTION                 0x08
+
+#define IPT_DCCP_VALID_FLAGS            0x0f
+
+struct ipt_dccp_info {
+        u_int16_t dpts[2];  /* Min, Max */
+        u_int16_t spts[2];  /* Min, Max */
+
+        u_int16_t flags;
+        u_int16_t invflags;
+
+        u_int16_t typemask;
+        u_int8_t option;
+};
+
+#endif /* _IPT_DCCP_H_ */
+
diff --git a/include/linux/netfilter_ipv4/ipt_string.h b/include/linux/netfilter_ipv4/ipt_string.h
new file mode 100644
index 000000000000..a265f6e44eab
--- /dev/null
+++ b/include/linux/netfilter_ipv4/ipt_string.h
@@ -0,0 +1,18 @@
+#ifndef _IPT_STRING_H
+#define _IPT_STRING_H
+
+#define IPT_STRING_MAX_PATTERN_SIZE 128
+#define IPT_STRING_MAX_ALGO_NAME_SIZE 16
+
+struct ipt_string_info
+{
+        u_int16_t from_offset;
+        u_int16_t to_offset;
+        char      algo[IPT_STRING_MAX_ALGO_NAME_SIZE];
+        char      pattern[IPT_STRING_MAX_PATTERN_SIZE];
+        u_int8_t  patlen;
+        u_int8_t  invert;
+        struct ts_config __attribute__((aligned(8))) *config;
+};
+
+#endif /*_IPT_STRING_H*/
diff --git a/include/linux/netfilter_ipv4/listhelp.h b/include/linux/netfilter_ipv4/listhelp.h
index f2ae7c5e57bb..360429f48737 100644
--- a/include/linux/netfilter_ipv4/listhelp.h
+++ b/include/linux/netfilter_ipv4/listhelp.h
@@ -2,7 +2,6 @@
 #define _LISTHELP_H
 #include <linux/config.h>
 #include <linux/list.h>
-#include <linux/netfilter_ipv4/lockhelp.h>
 
 /* Header to do more comprehensive job than linux/list.h; assume list
    is first entry in structure. */
diff --git a/include/linux/netfilter_ipv4/lockhelp.h b/include/linux/netfilter_ipv4/lockhelp.h
deleted file mode 100644
index a3288633ab46..000000000000
--- a/include/linux/netfilter_ipv4/lockhelp.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef _LOCKHELP_H
-#define _LOCKHELP_H
-#include <linux/config.h>
-
-#include <linux/spinlock.h>
-#include <asm/atomic.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-
-/* Header to do help in lock debugging. */
-
-#ifdef CONFIG_NETFILTER_DEBUG
-struct spinlock_debug
-{
-        spinlock_t l;
-        atomic_t locked_by;
-};
-
-struct rwlock_debug
-{
-        rwlock_t l;
-        long read_locked_map;
-        long write_locked_map;
-};
-
-#define DECLARE_LOCK(l)                                                 \
-struct spinlock_debug l = { SPIN_LOCK_UNLOCKED, ATOMIC_INIT(-1) }
-#define DECLARE_LOCK_EXTERN(l)                  \
-extern struct spinlock_debug l
-#define DECLARE_RWLOCK(l)                               \
-struct rwlock_debug l = { RW_LOCK_UNLOCKED, 0, 0 }
-#define DECLARE_RWLOCK_EXTERN(l)                \
-extern struct rwlock_debug l
-
-#define MUST_BE_LOCKED(l)                                               \
-do { if (atomic_read(&(l)->locked_by) != smp_processor_id())            \
-        printk("ASSERT %s:%u %s unlocked\n", __FILE__, __LINE__, #l);   \
-} while(0)
-
-#define MUST_BE_UNLOCKED(l)                                             \
-do { if (atomic_read(&(l)->locked_by) == smp_processor_id())            \
-        printk("ASSERT %s:%u %s locked\n", __FILE__, __LINE__, #l);     \
-} while(0)
-
-/* Write locked OK as well. */
-#define MUST_BE_READ_LOCKED(l)                                              \
-do { if (!((l)->read_locked_map & (1UL << smp_processor_id()))              \
-         && !((l)->write_locked_map & (1UL << smp_processor_id())))         \
-        printk("ASSERT %s:%u %s not readlocked\n", __FILE__, __LINE__, #l); \
-} while(0)
-
-#define MUST_BE_WRITE_LOCKED(l)                                              \
-do { if (!((l)->write_locked_map & (1UL << smp_processor_id())))             \
-        printk("ASSERT %s:%u %s not writelocked\n", __FILE__, __LINE__, #l); \
-} while(0)
-
-#define MUST_BE_READ_WRITE_UNLOCKED(l)                                    \
-do { if ((l)->read_locked_map & (1UL << smp_processor_id()))              \
-        printk("ASSERT %s:%u %s readlocked\n", __FILE__, __LINE__, #l);   \
- else if ((l)->write_locked_map & (1UL << smp_processor_id()))            \
-         printk("ASSERT %s:%u %s writelocked\n", __FILE__, __LINE__, #l); \
-} while(0)
-
-#define LOCK_BH(lk)                                             \
-do {                                                            \
-        MUST_BE_UNLOCKED(lk);                                   \
-        spin_lock_bh(&(lk)->l);                                 \
-        atomic_set(&(lk)->locked_by, smp_processor_id());       \
-} while(0)
-
-#define UNLOCK_BH(lk)                           \
-do {                                            \
-        MUST_BE_LOCKED(lk);                     \
-        atomic_set(&(lk)->locked_by, -1);       \
-        spin_unlock_bh(&(lk)->l);               \
-} while(0)
-
-#define READ_LOCK(lk)                                           \
-do {                                                            \
-        MUST_BE_READ_WRITE_UNLOCKED(lk);                        \
-        read_lock_bh(&(lk)->l);                                 \
-        set_bit(smp_processor_id(), &(lk)->read_locked_map);    \
-} while(0)
-
-#define WRITE_LOCK(lk)                                                    \
-do {                                                                      \
-        MUST_BE_READ_WRITE_UNLOCKED(lk);                                  \
-        write_lock_bh(&(lk)->l);                                          \
-        set_bit(smp_processor_id(), &(lk)->write_locked_map);             \
-} while(0)
-
-#define READ_UNLOCK(lk)                                                 \
-do {                                                                    \
-        if (!((lk)->read_locked_map & (1UL << smp_processor_id())))     \
-                printk("ASSERT: %s:%u %s not readlocked\n",             \
-                       __FILE__, __LINE__, #lk);                        \
-        clear_bit(smp_processor_id(), &(lk)->read_locked_map);          \
-        read_unlock_bh(&(lk)->l);                                       \
-} while(0)
-
-#define WRITE_UNLOCK(lk)                                        \
-do {                                                            \
-        MUST_BE_WRITE_LOCKED(lk);                               \
-        clear_bit(smp_processor_id(), &(lk)->write_locked_map); \
-        write_unlock_bh(&(lk)->l);                              \
-} while(0)
-
-#else
-#define DECLARE_LOCK(l) spinlock_t l = SPIN_LOCK_UNLOCKED
-#define DECLARE_LOCK_EXTERN(l) extern spinlock_t l
-#define DECLARE_RWLOCK(l) rwlock_t l = RW_LOCK_UNLOCKED
-#define DECLARE_RWLOCK_EXTERN(l) extern rwlock_t l
-
-#define MUST_BE_LOCKED(l)
-#define MUST_BE_UNLOCKED(l)
-#define MUST_BE_READ_LOCKED(l)
-#define MUST_BE_WRITE_LOCKED(l)
-#define MUST_BE_READ_WRITE_UNLOCKED(l)
-
-#define LOCK_BH(l) spin_lock_bh(l)
-#define UNLOCK_BH(l) spin_unlock_bh(l)
-
-#define READ_LOCK(l) read_lock_bh(l)
-#define WRITE_LOCK(l) write_lock_bh(l)
-#define READ_UNLOCK(l) read_unlock_bh(l)
-#define WRITE_UNLOCK(l) write_unlock_bh(l)
-#endif /*CONFIG_NETFILTER_DEBUG*/
-
-#endif /* _LOCKHELP_H */
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
index bee7a5ec7c66..edcc2c6eb5c7 100644
--- a/include/linux/netfilter_ipv6.h
+++ b/include/linux/netfilter_ipv6.h
@@ -10,6 +10,8 @@
 
 #include <linux/netfilter.h>
 
+/* only for userspace compatibility */
+#ifndef __KERNEL__
 /* IP Cache bits. */
 /* Src IP address. */
 #define NFC_IP6_SRC              0x0001
@@ -38,6 +40,7 @@
 #define NFC_IP6_DST_PT           0x0400
 /* Something else about the proto */
 #define NFC_IP6_PROTO_UNKNOWN    0x2000
+#endif /* ! __KERNEL__ */
 
 
 /* IP6 Hooks */
@@ -68,4 +71,7 @@ enum nf_ip6_hook_priorities {
         NF_IP6_PRI_LAST = INT_MAX,
 };
 
+extern int ipv6_netfilter_init(void);
+extern void ipv6_netfilter_fini(void);
+
 #endif /*__LINUX_IP6_NETFILTER_H*/
diff --git a/include/linux/netfilter_ipv6/ip6_logging.h b/include/linux/netfilter_ipv6/ip6_logging.h
deleted file mode 100644
index a0b2ee3043aa..000000000000
--- a/include/linux/netfilter_ipv6/ip6_logging.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* IPv6 macros for the nternal logging interface. */
-#ifndef __IP6_LOGGING_H
-#define __IP6_LOGGING_H
-
-#ifdef __KERNEL__
-#include <linux/socket.h>
-#include <linux/netfilter_logging.h>
-
-#define nf_log_ip6_packet(pskb,hooknum,in,out,fmt,args...) \
-        nf_log_packet(AF_INET6,pskb,hooknum,in,out,fmt,##args)
-
-#define nf_log_ip6(pfh,len,fmt,args...) \
-        nf_log(AF_INET6,pfh,len,fmt,##args)
-
-#define nf_ip6_log_register(logging) nf_log_register(AF_INET6,logging)
-#define nf_ip6_log_unregister(logging) nf_log_unregister(AF_INET6,logging)
-        
-#endif /*__KERNEL__*/
-
-#endif /*__IP6_LOGGING_H*/
diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h
index f1ce3b009853..58c72a52dc65 100644
--- a/include/linux/netfilter_ipv6/ip6_tables.h
+++ b/include/linux/netfilter_ipv6/ip6_tables.h
@@ -111,7 +111,8 @@ struct ip6t_counters
 #define IP6T_F_PROTO            0x01    /* Set if rule cares about upper 
                                            protocols */
 #define IP6T_F_TOS              0x02    /* Match the TOS. */
-#define IP6T_F_MASK             0x03    /* All possible flag bits mask. */
+#define IP6T_F_GOTO             0x04    /* Set if jump is a goto */
+#define IP6T_F_MASK             0x07    /* All possible flag bits mask. */
 
 /* Values for "inv" field in struct ip6t_ip6. */
 #define IP6T_INV_VIA_IN         0x01    /* Invert the sense of IN IFACE. */
diff --git a/include/linux/netfilter_ipv6/ip6t_HL.h b/include/linux/netfilter_ipv6/ip6t_HL.h
new file mode 100644
index 000000000000..afb7813d45ab
--- /dev/null
+++ b/include/linux/netfilter_ipv6/ip6t_HL.h
@@ -0,0 +1,22 @@
+/* Hop Limit modification module for ip6tables
+ * Maciej Soltysiak <solt@dns.toxicfilms.tv>
+ * Based on HW's TTL module */
+
+#ifndef _IP6T_HL_H
+#define _IP6T_HL_H
+
+enum {
+        IP6T_HL_SET = 0,
+        IP6T_HL_INC,
+        IP6T_HL_DEC
+};
+
+#define IP6T_HL_MAXMODE IP6T_HL_DEC
+
+struct ip6t_HL_info {
+        u_int8_t        mode;
+        u_int8_t        hop_limit;
+};
+
+
+#endif
diff --git a/include/linux/netfilter_ipv6/ip6t_LOG.h b/include/linux/netfilter_ipv6/ip6t_LOG.h
index 42996a43bb39..9008ff5c40ae 100644
--- a/include/linux/netfilter_ipv6/ip6t_LOG.h
+++ b/include/linux/netfilter_ipv6/ip6t_LOG.h
@@ -1,6 +1,7 @@
 #ifndef _IP6T_LOG_H
 #define _IP6T_LOG_H
 
+/* make sure not to change this without changing netfilter.h:NF_LOG_* (!) */
 #define IP6T_LOG_TCPSEQ         0x01    /* Log TCP sequence numbers */
 #define IP6T_LOG_TCPOPT         0x02    /* Log TCP options */
 #define IP6T_LOG_IPOPT          0x04    /* Log IP options */
diff --git a/include/linux/netfilter_ipv6/ip6t_REJECT.h b/include/linux/netfilter_ipv6/ip6t_REJECT.h
new file mode 100644
index 000000000000..6be6504162bb
--- /dev/null
+++ b/include/linux/netfilter_ipv6/ip6t_REJECT.h
@@ -0,0 +1,18 @@
+#ifndef _IP6T_REJECT_H
+#define _IP6T_REJECT_H
+
+enum ip6t_reject_with {
+        IP6T_ICMP6_NO_ROUTE,
+        IP6T_ICMP6_ADM_PROHIBITED,
+        IP6T_ICMP6_NOT_NEIGHBOUR,
+        IP6T_ICMP6_ADDR_UNREACH,
+        IP6T_ICMP6_PORT_UNREACH,
+        IP6T_ICMP6_ECHOREPLY,
+        IP6T_TCP_RESET
+};
+
+struct ip6t_reject_info {
+        u_int32_t       with;   /* reject type */
+};
+
+#endif /*_IP6T_REJECT_H*/
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index b2738ac8bc99..167518668936 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -5,20 +5,20 @@
 #include <linux/types.h>
 
 #define NETLINK_ROUTE           0       /* Routing/device hook                          */
-#define NETLINK_SKIP            1       /* Reserved for ENskip                          */
+#define NETLINK_W1              1       /* 1-wire subsystem                             */
 #define NETLINK_USERSOCK        2       /* Reserved for user mode socket protocols      */
 #define NETLINK_FIREWALL        3       /* Firewalling hook                             */
-#define NETLINK_TCPDIAG         4       /* TCP socket monitoring                        */
+#define NETLINK_INET_DIAG       4       /* INET socket monitoring                       */
 #define NETLINK_NFLOG           5       /* netfilter/iptables ULOG */
 #define NETLINK_XFRM            6       /* ipsec */
 #define NETLINK_SELINUX         7       /* SELinux event notifications */
-#define NETLINK_ARPD            8
+#define NETLINK_ISCSI           8       /* Open-iSCSI */
 #define NETLINK_AUDIT           9       /* auditing */
-#define NETLINK_ROUTE6          11      /* af_inet6 route comm channel */
+#define NETLINK_FIB_LOOKUP      10      
+#define NETLINK_NETFILTER       12      /* netfilter subsystem */
 #define NETLINK_IP6_FW          13
 #define NETLINK_DNRTMSG         14      /* DECnet routing messages */
 #define NETLINK_KOBJECT_UEVENT  15      /* Kernel messages to userspace */
-#define NETLINK_TAPBASE         16      /* 16 to 31 are ethertap */
 
 #define MAX_LINKS 32            
 
@@ -90,6 +90,15 @@ struct nlmsgerr
         struct nlmsghdr msg;
 };
 
+#define NETLINK_ADD_MEMBERSHIP  1
+#define NETLINK_DROP_MEMBERSHIP 2
+#define NETLINK_PKTINFO         3
+
+struct nl_pktinfo
+{
+        __u32   group;
+};
+
 #define NET_MAJOR 36            /* Major 36 is reserved for networking                                          */
 
 enum {
@@ -106,9 +115,8 @@ struct netlink_skb_parms
 {
         struct ucred            creds;          /* Skb credentials      */
         __u32                   pid;
-        __u32                   groups;
         __u32                   dst_pid;
-        __u32                   dst_groups;
+        __u32                   dst_group;
         kernel_cap_t            eff_cap;
         __u32                   loginuid;       /* Login (audit) uid */
 };
@@ -117,11 +125,11 @@ struct netlink_skb_parms
 #define NETLINK_CREDS(skb)      (&NETLINK_CB((skb)).creds)
 
 
-extern struct sock *netlink_kernel_create(int unit, void (*input)(struct sock *sk, int len));
+extern struct sock *netlink_kernel_create(int unit, unsigned int groups, void (*input)(struct sock *sk, int len), struct module *module);
 extern void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err);
 extern int netlink_unicast(struct sock *ssk, struct sk_buff *skb, __u32 pid, int nonblock);
 extern int netlink_broadcast(struct sock *ssk, struct sk_buff *skb, __u32 pid,
-                             __u32 group, int allocation);
+                             __u32 group, unsigned int __nocast allocation);
 extern void netlink_set_err(struct sock *ssk, __u32 pid, __u32 group, int code);
 extern int netlink_register_notifier(struct notifier_block *nb);
 extern int netlink_unregister_notifier(struct notifier_block *nb);
@@ -146,7 +154,7 @@ struct netlink_callback
         int             (*dump)(struct sk_buff * skb, struct netlink_callback *cb);
         int             (*done)(struct netlink_callback *cb);
         int             family;
-        long            args[4];
+        long            args[5];
 };
 
 struct netlink_notify
@@ -156,7 +164,7 @@ struct netlink_notify
 };
 
 static __inline__ struct nlmsghdr *
-__nlmsg_put(struct sk_buff *skb, u32 pid, u32 seq, int type, int len)
+__nlmsg_put(struct sk_buff *skb, u32 pid, u32 seq, int type, int len, int flags)
 {
         struct nlmsghdr *nlh;
         int size = NLMSG_LENGTH(len);
@@ -164,15 +172,32 @@ __nlmsg_put(struct sk_buff *skb, u32 pid, u32 seq, int type, int len)
         nlh = (struct nlmsghdr*)skb_put(skb, NLMSG_ALIGN(size));
         nlh->nlmsg_type = type;
         nlh->nlmsg_len = size;
-        nlh->nlmsg_flags = 0;
+        nlh->nlmsg_flags = flags;
         nlh->nlmsg_pid = pid;
         nlh->nlmsg_seq = seq;
+        memset(NLMSG_DATA(nlh) + len, 0, NLMSG_ALIGN(size) - size);
         return nlh;
 }
 
+#define NLMSG_NEW(skb, pid, seq, type, len, flags) \
+({      if (skb_tailroom(skb) < (int)NLMSG_SPACE(len)) \
+                goto nlmsg_failure; \
+        __nlmsg_put(skb, pid, seq, type, len, flags); })
+
 #define NLMSG_PUT(skb, pid, seq, type, len) \
-({ if (skb_tailroom(skb) < (int)NLMSG_SPACE(len)) goto nlmsg_failure; \
-   __nlmsg_put(skb, pid, seq, type, len); })
+        NLMSG_NEW(skb, pid, seq, type, len, 0)
+
+#define NLMSG_NEW_ANSWER(skb, cb, type, len, flags) \
+        NLMSG_NEW(skb, NETLINK_CB((cb)->skb).pid, \
+                  (cb)->nlh->nlmsg_seq, type, len, flags)
+
+#define NLMSG_END(skb, nlh) \
+({      (nlh)->nlmsg_len = (skb)->tail - (unsigned char *) (nlh); \
+        (skb)->len; })
+
+#define NLMSG_CANCEL(skb, nlh) \
+({      skb_trim(skb, (unsigned char *) (nlh) - (skb)->data); \
+        -1; })
 
 extern int netlink_dump_start(struct sock *ssk, struct sk_buff *skb,
                               struct nlmsghdr *nlh,
diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h
index c0d8b90c5202..5ade54a78dbb 100644
--- a/include/linux/netpoll.h
+++ b/include/linux/netpoll.h
@@ -9,6 +9,7 @@
 
 #include <linux/netdevice.h>
 #include <linux/interrupt.h>
+#include <linux/rcupdate.h>
 #include <linux/list.h>
 
 struct netpoll;
@@ -16,14 +17,20 @@ struct netpoll;
 struct netpoll {
         struct net_device *dev;
         char dev_name[16], *name;
-        int rx_flags;
         void (*rx_hook)(struct netpoll *, int, char *, int);
         void (*drop)(struct sk_buff *skb);
         u32 local_ip, remote_ip;
         u16 local_port, remote_port;
         unsigned char local_mac[6], remote_mac[6];
+};
+
+struct netpoll_info {
         spinlock_t poll_lock;
         int poll_owner;
+        int tries;
+        int rx_flags;
+        spinlock_t rx_lock;
+        struct netpoll *rx_np; /* netpoll that registered an rx_hook */
 };
 
 void netpoll_poll(struct netpoll *np);
@@ -39,28 +46,47 @@ void netpoll_queue(struct sk_buff *skb);
 #ifdef CONFIG_NETPOLL
 static inline int netpoll_rx(struct sk_buff *skb)
 {
-        return skb->dev->np && skb->dev->np->rx_flags && __netpoll_rx(skb);
+        struct netpoll_info *npinfo = skb->dev->npinfo;
+        unsigned long flags;
+        int ret = 0;
+
+        if (!npinfo || (!npinfo->rx_np && !npinfo->rx_flags))
+                return 0;
+
+        spin_lock_irqsave(&npinfo->rx_lock, flags);
+        /* check rx_flags again with the lock held */
+        if (npinfo->rx_flags && __netpoll_rx(skb))
+                ret = 1;
+        spin_unlock_irqrestore(&npinfo->rx_lock, flags);
+
+        return ret;
 }
 
-static inline void netpoll_poll_lock(struct net_device *dev)
+static inline void *netpoll_poll_lock(struct net_device *dev)
 {
-        if (dev->np) {
-                spin_lock(&dev->np->poll_lock);
-                dev->np->poll_owner = smp_processor_id();
+        rcu_read_lock(); /* deal with race on ->npinfo */
+        if (dev->npinfo) {
+                spin_lock(&dev->npinfo->poll_lock);
+                dev->npinfo->poll_owner = smp_processor_id();
+                return dev->npinfo;
         }
+        return NULL;
 }
 
-static inline void netpoll_poll_unlock(struct net_device *dev)
+static inline void netpoll_poll_unlock(void *have)
 {
-        if (dev->np) {
-                spin_unlock(&dev->np->poll_lock);
-                dev->np->poll_owner = -1;
+        struct netpoll_info *npi = have;
+
+        if (npi) {
+                npi->poll_owner = -1;
+                spin_unlock(&npi->poll_lock);
         }
+        rcu_read_unlock();
 }
 
 #else
 #define netpoll_rx(a) 0
-#define netpoll_poll_lock(a)
+#define netpoll_poll_lock(a) 0
 #define netpoll_poll_unlock(a)
 #endif
 
diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h
index 5ca8a8d8ccdf..0c1c306cdaec 100644
--- a/include/linux/nfs4.h
+++ b/include/linux/nfs4.h
@@ -28,7 +28,7 @@
 #define NFS4_ACCESS_DELETE      0x0010
 #define NFS4_ACCESS_EXECUTE     0x0020
 
-#define NFS4_FH_PERISTENT               0x0000
+#define NFS4_FH_PERSISTENT              0x0000
 #define NFS4_FH_NOEXPIRE_WITH_OPEN      0x0001
 #define NFS4_FH_VOLATILE_ANY            0x0002
 #define NFS4_FH_VOL_MIGRATION           0x0004
@@ -382,6 +382,8 @@ enum {
         NFSPROC4_CLNT_READDIR,
         NFSPROC4_CLNT_SERVER_CAPS,
         NFSPROC4_CLNT_DELEGRETURN,
+        NFSPROC4_CLNT_GETACL,
+        NFSPROC4_CLNT_SETACL,
 };
 
 #endif
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index dbac7f363e5d..9a6047ff1b25 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -15,7 +15,6 @@
 #include <linux/pagemap.h>
 #include <linux/rwsem.h>
 #include <linux/wait.h>
-#include <linux/uio.h>
 
 #include <linux/nfs_fs_sb.h>
 
@@ -29,7 +28,6 @@
 #include <linux/nfs4.h>
 #include <linux/nfs_xdr.h>
 #include <linux/rwsem.h>
-#include <linux/workqueue.h>
 #include <linux/mempool.h>
 
 /*
@@ -44,13 +42,6 @@
 #define NFS_DEF_FILE_IO_BUFFER_SIZE     4096
 
 /*
- * The upper limit on timeouts for the exponential backoff algorithm.
- */
-#define NFS_WRITEBACK_DELAY             (5*HZ)
-#define NFS_WRITEBACK_LOCKDELAY         (60*HZ)
-#define NFS_COMMIT_DELAY                (5*HZ)
-
-/*
  * superblock magic number for NFS
  */
 #define NFS_SUPER_MAGIC                 0x6969
@@ -60,9 +51,6 @@
  */
 #define NFS_RPC_SWAPFLAGS               (RPC_TASK_SWAPPER|RPC_TASK_ROOTCREDS)
 
-#define NFS_RW_SYNC             0x0001  /* O_SYNC handling */
-#define NFS_RW_SWAP             0x0002  /* This is a swap request */
-
 /*
  * When flushing a cluster of dirty pages, there can be different
  * strategies:
@@ -96,7 +84,8 @@ struct nfs_open_context {
         int error;
 
         struct list_head list;
-        wait_queue_head_t waitq;
+
+        __u64 dir_cookie;
 };
 
 /*
@@ -104,6 +93,8 @@ struct nfs_open_context {
  */
 struct nfs_delegation;
 
+struct posix_acl;
+
 /*
  * nfs fs inode data in memory
  */
@@ -121,7 +112,8 @@ struct nfs_inode {
         /*
          * Various flags
          */
-        unsigned int            flags;
+        unsigned long           flags;                  /* atomic bit ops */
+        unsigned long           cache_validity;         /* bit mask */
 
         /*
          * read_cache_jiffies is when we started read-caching this inode,
@@ -140,7 +132,6 @@ struct nfs_inode {
          *
          *      mtime != read_cache_mtime
          */
-        unsigned long           readdir_timestamp;
         unsigned long           read_cache_jiffies;
         unsigned long           attrtimeo;
         unsigned long           attrtimeo_timestamp;
@@ -158,6 +149,10 @@ struct nfs_inode {
         atomic_t                data_updates;
 
         struct nfs_access_entry cache_access;
+#ifdef CONFIG_NFS_V3_ACL
+        struct posix_acl        *acl_access;
+        struct posix_acl        *acl_default;
+#endif
 
         /*
          * This is the cookie verifier used for NFSv3 readdir
@@ -180,29 +175,33 @@ struct nfs_inode {
         /* Open contexts for shared mmap writes */
         struct list_head        open_files;
 
-        wait_queue_head_t       nfs_i_wait;
-
 #ifdef CONFIG_NFS_V4
+        struct nfs4_cached_acl  *nfs4_acl;
         /* NFSv4 state */
         struct list_head        open_states;
         struct nfs_delegation   *delegation;
         int                      delegation_state;
         struct rw_semaphore     rwsem;
 #endif /* CONFIG_NFS_V4*/
-
         struct inode            vfs_inode;
 };
 
 /*
- * Legal inode flag values
+ * Cache validity bit flags
+ */
+#define NFS_INO_INVALID_ATTR    0x0001          /* cached attrs are invalid */
+#define NFS_INO_INVALID_DATA    0x0002          /* cached data is invalid */
+#define NFS_INO_INVALID_ATIME   0x0004          /* cached atime is invalid */
+#define NFS_INO_INVALID_ACCESS  0x0008          /* cached access cred invalid */
+#define NFS_INO_INVALID_ACL     0x0010          /* cached acls are invalid */
+#define NFS_INO_REVAL_PAGECACHE 0x0020          /* must revalidate pagecache */
+
+/*
+ * Bit offsets in flags field
  */
-#define NFS_INO_STALE           0x0001          /* possible stale inode */
-#define NFS_INO_ADVISE_RDPLUS   0x0002          /* advise readdirplus */
-#define NFS_INO_REVALIDATING    0x0004          /* revalidating attrs */
-#define NFS_INO_INVALID_ATTR    0x0008          /* cached attrs are invalid */
-#define NFS_INO_INVALID_DATA    0x0010          /* cached data is invalid */
-#define NFS_INO_INVALID_ATIME   0x0020          /* cached atime is invalid */
-#define NFS_INO_INVALID_ACCESS  0x0040          /* cached access cred invalid */
+#define NFS_INO_REVALIDATING    (0)             /* revalidating attrs */
+#define NFS_INO_ADVISE_RDPLUS   (1)             /* advise readdirplus */
+#define NFS_INO_STALE           (2)             /* possible stale inode */
 
 static inline struct nfs_inode *NFS_I(struct inode *inode)
 {
@@ -228,8 +227,7 @@ static inline struct nfs_inode *NFS_I(struct inode *inode)
 #define NFS_ATTRTIMEO_UPDATE(inode)     (NFS_I(inode)->attrtimeo_timestamp)
 
 #define NFS_FLAGS(inode)                (NFS_I(inode)->flags)
-#define NFS_REVALIDATING(inode)         (NFS_FLAGS(inode) & NFS_INO_REVALIDATING)
-#define NFS_STALE(inode)                (NFS_FLAGS(inode) & NFS_INO_STALE)
+#define NFS_STALE(inode)                (test_bit(NFS_INO_STALE, &NFS_FLAGS(inode)))
 
 #define NFS_FILEID(inode)               (NFS_I(inode)->fileid)
 
@@ -240,8 +238,11 @@ static inline int nfs_caches_unstable(struct inode *inode)
 
 static inline void NFS_CACHEINV(struct inode *inode)
 {
-        if (!nfs_caches_unstable(inode))
-                NFS_FLAGS(inode) |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS;
+        if (!nfs_caches_unstable(inode)) {
+                spin_lock(&inode->i_lock);
+                NFS_I(inode)->cache_validity |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS;
+                spin_unlock(&inode->i_lock);
+        }
 }
 
 static inline int nfs_server_capable(struct inode *inode, int cap)
@@ -251,7 +252,7 @@ static inline int nfs_server_capable(struct inode *inode, int cap)
 
 static inline int NFS_USE_READDIRPLUS(struct inode *inode)
 {
-        return NFS_FLAGS(inode) & NFS_INO_ADVISE_RDPLUS;
+        return test_bit(NFS_INO_ADVISE_RDPLUS, &NFS_FLAGS(inode));
 }
 
 /**
@@ -294,12 +295,13 @@ extern int nfs_release(struct inode *, struct file *);
 extern int nfs_attribute_timeout(struct inode *inode);
 extern int nfs_revalidate_inode(struct nfs_server *server, struct inode *inode);
 extern int __nfs_revalidate_inode(struct nfs_server *, struct inode *);
+extern void nfs_revalidate_mapping(struct inode *inode, struct address_space *mapping);
 extern int nfs_setattr(struct dentry *, struct iattr *);
+extern void nfs_setattr_update_inode(struct inode *inode, struct iattr *attr);
 extern void nfs_begin_attr_update(struct inode *);
 extern void nfs_end_attr_update(struct inode *);
 extern void nfs_begin_data_update(struct inode *);
 extern void nfs_end_data_update(struct inode *);
-extern void nfs_end_data_update_defer(struct inode *);
 extern struct nfs_open_context *alloc_nfs_open_context(struct dentry *dentry, struct rpc_cred *cred);
 extern struct nfs_open_context *get_nfs_open_context(struct nfs_open_context *ctx);
 extern void put_nfs_open_context(struct nfs_open_context *ctx);
@@ -314,6 +316,9 @@ extern u32 root_nfs_parse_addr(char *name); /*__init*/
  * linux/fs/nfs/file.c
  */
 extern struct inode_operations nfs_file_inode_operations;
+#ifdef CONFIG_NFS_V3
+extern struct inode_operations nfs3_file_inode_operations;
+#endif /* CONFIG_NFS_V3 */
 extern struct file_operations nfs_file_operations;
 extern struct address_space_operations nfs_file_aops;
 
@@ -329,6 +334,22 @@ static inline struct rpc_cred *nfs_file_cred(struct file *file)
 }
 
 /*
+ * linux/fs/nfs/xattr.c
+ */
+#ifdef CONFIG_NFS_V3_ACL
+extern ssize_t nfs3_listxattr(struct dentry *, char *, size_t);
+extern ssize_t nfs3_getxattr(struct dentry *, const char *, void *, size_t);
+extern int nfs3_setxattr(struct dentry *, const char *,
+                        const void *, size_t, int);
+extern int nfs3_removexattr (struct dentry *, const char *name);
+#else
+# define nfs3_listxattr NULL
+# define nfs3_getxattr NULL
+# define nfs3_setxattr NULL
+# define nfs3_removexattr NULL
+#endif
+
+/*
  * linux/fs/nfs/direct.c
  */
 extern ssize_t nfs_direct_IO(int, struct kiocb *, const struct iovec *, loff_t,
@@ -342,6 +363,9 @@ extern ssize_t nfs_file_direct_write(struct kiocb *iocb, const char __user *buf,
  * linux/fs/nfs/dir.c
  */
 extern struct inode_operations nfs_dir_inode_operations;
+#ifdef CONFIG_NFS_V3
+extern struct inode_operations nfs3_dir_inode_operations;
+#endif /* CONFIG_NFS_V3 */
 extern struct file_operations nfs_dir_operations;
 extern struct dentry_operations nfs_dentry_operations;
 
@@ -377,10 +401,10 @@ extern void nfs_commit_done(struct rpc_task *);
  */
 extern int  nfs_sync_inode(struct inode *, unsigned long, unsigned int, int);
 #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
-extern int  nfs_commit_inode(struct inode *, unsigned long, unsigned int, int);
+extern int  nfs_commit_inode(struct inode *, int);
 #else
 static inline int
-nfs_commit_inode(struct inode *inode, unsigned long idx_start, unsigned int npages, int how)
+nfs_commit_inode(struct inode *inode, int how)
 {
         return 0;
 }
@@ -434,11 +458,6 @@ static inline void nfs_writedata_free(struct nfs_write_data *p)
         mempool_free(p, nfs_wdata_mempool);
 }
 
-/* Hack for future NFS swap support */
-#ifndef IS_SWAPFILE
-# define IS_SWAPFILE(inode)     (0)
-#endif
-
 /*
  * linux/fs/nfs/read.c
  */
@@ -468,6 +487,29 @@ static inline void nfs_readdata_free(struct nfs_read_data *p)
 extern void  nfs_readdata_release(struct rpc_task *task);
 
 /*
+ * linux/fs/nfs3proc.c
+ */
+#ifdef CONFIG_NFS_V3_ACL
+extern struct posix_acl *nfs3_proc_getacl(struct inode *inode, int type);
+extern int nfs3_proc_setacl(struct inode *inode, int type,
+                            struct posix_acl *acl);
+extern int nfs3_proc_set_default_acl(struct inode *dir, struct inode *inode,
+                mode_t mode);
+extern void nfs3_forget_cached_acls(struct inode *inode);
+#else
+static inline int nfs3_proc_set_default_acl(struct inode *dir,
+                                            struct inode *inode,
+                                            mode_t mode)
+{
+        return 0;
+}
+
+static inline void nfs3_forget_cached_acls(struct inode *inode)
+{
+}
+#endif /* CONFIG_NFS_V3_ACL */
+
+/*
  * linux/fs/mount_clnt.c
  * (Used only by nfsroot module)
  */
@@ -515,230 +557,6 @@ extern void * nfs_root_data(void);
 
 #define NFS_JUKEBOX_RETRY_TIME (5 * HZ)
 
-#ifdef CONFIG_NFS_V4
-
-struct idmap;
-
-/*
- * In a seqid-mutating op, this macro controls which error return
- * values trigger incrementation of the seqid.
- *
- * from rfc 3010:
- * The client MUST monotonically increment the sequence number for the
- * CLOSE, LOCK, LOCKU, OPEN, OPEN_CONFIRM, and OPEN_DOWNGRADE
- * operations.  This is true even in the event that the previous
- * operation that used the sequence number received an error.  The only
- * exception to this rule is if the previous operation received one of
- * the following errors: NFSERR_STALE_CLIENTID, NFSERR_STALE_STATEID,
- * NFSERR_BAD_STATEID, NFSERR_BAD_SEQID, NFSERR_BADXDR,
- * NFSERR_RESOURCE, NFSERR_NOFILEHANDLE.
- *
- */
-#define seqid_mutating_err(err)       \
-(((err) != NFSERR_STALE_CLIENTID) &&  \
- ((err) != NFSERR_STALE_STATEID)  &&  \
- ((err) != NFSERR_BAD_STATEID)    &&  \
- ((err) != NFSERR_BAD_SEQID)      &&  \
- ((err) != NFSERR_BAD_XDR)        &&  \
- ((err) != NFSERR_RESOURCE)       &&  \
- ((err) != NFSERR_NOFILEHANDLE))
-
-enum nfs4_client_state {
-        NFS4CLNT_OK  = 0,
-};
-
-/*
- * The nfs4_client identifies our client state to the server.
- */
-struct nfs4_client {
-        struct list_head        cl_servers;     /* Global list of servers */
-        struct in_addr          cl_addr;        /* Server identifier */
-        u64                     cl_clientid;    /* constant */
-        nfs4_verifier           cl_confirm;
-        unsigned long           cl_state;
-
-        u32                     cl_lockowner_id;
-
-        /*
-         * The following rwsem ensures exclusive access to the server
-         * while we recover the state following a lease expiration.
-         */
-        struct rw_semaphore     cl_sem;
-
-        struct list_head        cl_delegations;
-        struct list_head        cl_state_owners;
-        struct list_head        cl_unused;
-        int                     cl_nunused;
-        spinlock_t              cl_lock;
-        atomic_t                cl_count;
-
-        struct rpc_clnt *       cl_rpcclient;
-        struct rpc_cred *       cl_cred;
-
-        struct list_head        cl_superblocks; /* List of nfs_server structs */
-
-        unsigned long           cl_lease_time;
-        unsigned long           cl_last_renewal;
-        struct work_struct      cl_renewd;
-        struct work_struct      cl_recoverd;
-
-        wait_queue_head_t       cl_waitq;
-        struct rpc_wait_queue   cl_rpcwaitq;
-
-        /* used for the setclientid verifier */
-        struct timespec         cl_boot_time;
-
-        /* idmapper */
-        struct idmap *          cl_idmap;
-
-        /* Our own IP address, as a null-terminated string.
-         * This is used to generate the clientid, and the callback address.
-         */
-        char                    cl_ipaddr[16];
-        unsigned char           cl_id_uniquifier;
-};
-
-/*
- * NFS4 state_owners and lock_owners are simply labels for ordered
- * sequences of RPC calls. Their sole purpose is to provide once-only
- * semantics by allowing the server to identify replayed requests.
- *
- * The ->so_sema is held during all state_owner seqid-mutating operations:
- * OPEN, OPEN_DOWNGRADE, and CLOSE. Its purpose is to properly serialize
- * so_seqid.
- */
-struct nfs4_state_owner {
-        struct list_head     so_list;    /* per-clientid list of state_owners */
-        struct nfs4_client   *so_client;
-        u32                  so_id;      /* 32-bit identifier, unique */
-        struct semaphore     so_sema;
-        u32                  so_seqid;   /* protected by so_sema */
-        atomic_t             so_count;
-
-        struct rpc_cred      *so_cred;   /* Associated cred */
-        struct list_head     so_states;
-        struct list_head     so_delegations;
-};
-
-/*
- * struct nfs4_state maintains the client-side state for a given
- * (state_owner,inode) tuple (OPEN) or state_owner (LOCK).
- *
- * OPEN:
- * In order to know when to OPEN_DOWNGRADE or CLOSE the state on the server,
- * we need to know how many files are open for reading or writing on a
- * given inode. This information too is stored here.
- *
- * LOCK: one nfs4_state (LOCK) to hold the lock stateid nfs4_state(OPEN)
- */
-
-struct nfs4_lock_state {
-        struct list_head        ls_locks;       /* Other lock stateids */
-        fl_owner_t              ls_owner;       /* POSIX lock owner */
-#define NFS_LOCK_INITIALIZED 1
-        int                     ls_flags;
-        u32                     ls_seqid;
-        u32                     ls_id;
-        nfs4_stateid            ls_stateid;
-        atomic_t                ls_count;
-};
-
-/* bits for nfs4_state->flags */
-enum {
-        LK_STATE_IN_USE,
-        NFS_DELEGATED_STATE,
-};
-
-struct nfs4_state {
-        struct list_head open_states;   /* List of states for the same state_owner */
-        struct list_head inode_states;  /* List of states for the same inode */
-        struct list_head lock_states;   /* List of subservient lock stateids */
-
-        struct nfs4_state_owner *owner; /* Pointer to the open owner */
-        struct inode *inode;            /* Pointer to the inode */
-
-        unsigned long flags;            /* Do we hold any locks? */
-        struct semaphore lock_sema;     /* Serializes file locking operations */
-        rwlock_t state_lock;            /* Protects the lock_states list */
-
-        nfs4_stateid stateid;
-
-        unsigned int nreaders;
-        unsigned int nwriters;
-        int state;                      /* State on the server (R,W, or RW) */
-        atomic_t count;
-};
-
-
-struct nfs4_exception {
-        long timeout;
-        int retry;
-};
-
-struct nfs4_state_recovery_ops {
-        int (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);
-        int (*recover_lock)(struct nfs4_state *, struct file_lock *);
-};
-
-extern struct dentry_operations nfs4_dentry_operations;
-extern struct inode_operations nfs4_dir_inode_operations;
-
-/* nfs4proc.c */
-extern int nfs4_map_errors(int err);
-extern int nfs4_proc_setclientid(struct nfs4_client *, u32, unsigned short);
-extern int nfs4_proc_setclientid_confirm(struct nfs4_client *);
-extern int nfs4_proc_async_renew(struct nfs4_client *);
-extern int nfs4_proc_renew(struct nfs4_client *);
-extern int nfs4_do_close(struct inode *inode, struct nfs4_state *state, mode_t mode);
-extern struct inode *nfs4_atomic_open(struct inode *, struct dentry *, struct nameidata *);
-extern int nfs4_open_revalidate(struct inode *, struct dentry *, int);
-
-extern struct nfs4_state_recovery_ops nfs4_reboot_recovery_ops;
-extern struct nfs4_state_recovery_ops nfs4_network_partition_recovery_ops;
-
-/* nfs4renewd.c */
-extern void nfs4_schedule_state_renewal(struct nfs4_client *);
-extern void nfs4_renewd_prepare_shutdown(struct nfs_server *);
-extern void nfs4_kill_renewd(struct nfs4_client *);
-
-/* nfs4state.c */
-extern void init_nfsv4_state(struct nfs_server *);
-extern void destroy_nfsv4_state(struct nfs_server *);
-extern struct nfs4_client *nfs4_get_client(struct in_addr *);
-extern void nfs4_put_client(struct nfs4_client *clp);
-extern int nfs4_init_client(struct nfs4_client *clp);
-extern struct nfs4_client *nfs4_find_client(struct in_addr *);
-extern u32 nfs4_alloc_lockowner_id(struct nfs4_client *);
-
-extern struct nfs4_state_owner * nfs4_get_state_owner(struct nfs_server *, struct rpc_cred *);
-extern void nfs4_put_state_owner(struct nfs4_state_owner *);
-extern void nfs4_drop_state_owner(struct nfs4_state_owner *);
-extern struct nfs4_state * nfs4_get_open_state(struct inode *, struct nfs4_state_owner *);
-extern void nfs4_put_open_state(struct nfs4_state *);
-extern void nfs4_close_state(struct nfs4_state *, mode_t);
-extern struct nfs4_state *nfs4_find_state(struct inode *, struct rpc_cred *, mode_t mode);
-extern void nfs4_increment_seqid(int status, struct nfs4_state_owner *sp);
-extern void nfs4_schedule_state_recovery(struct nfs4_client *);
-extern struct nfs4_lock_state *nfs4_find_lock_state(struct nfs4_state *state, fl_owner_t);
-extern struct nfs4_lock_state *nfs4_get_lock_state(struct nfs4_state *state, fl_owner_t);
-extern void nfs4_put_lock_state(struct nfs4_lock_state *state);
-extern void nfs4_increment_lock_seqid(int status, struct nfs4_lock_state *ls);
-extern void nfs4_notify_setlk(struct nfs4_state *, struct file_lock *, struct nfs4_lock_state *);
-extern void nfs4_notify_unlck(struct nfs4_state *, struct file_lock *, struct nfs4_lock_state *);
-extern void nfs4_copy_stateid(nfs4_stateid *, struct nfs4_state *, fl_owner_t);
-
-
-
-struct nfs4_mount_data;
-#else
-#define init_nfsv4_state(server)  do { } while (0)
-#define destroy_nfsv4_state(server)       do { } while (0)
-#define nfs4_put_state_owner(inode, owner) do { } while (0)
-#define nfs4_put_open_state(state) do { } while (0)
-#define nfs4_close_state(a, b) do { } while (0)
-#define nfs4_renewd_prepare_shutdown(server) do { } while (0)
-#endif
-
 #endif /* __KERNEL__ */
 
 /*
diff --git a/include/linux/nfs_fs_i.h b/include/linux/nfs_fs_i.h
index e9a749588a7b..e2c18dabff86 100644
--- a/include/linux/nfs_fs_i.h
+++ b/include/linux/nfs_fs_i.h
@@ -16,6 +16,11 @@ struct nfs_lock_info {
         struct nlm_lockowner *owner;
 };
 
+struct nfs4_lock_state;
+struct nfs4_lock_info {
+        struct nfs4_lock_state *owner;
+};
+
 /*
  * Lock flag values
  */
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index fc51645d61ee..3d3a305488cf 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -10,6 +10,7 @@
 struct nfs_server {
         struct rpc_clnt *       client;         /* RPC client handle */
         struct rpc_clnt *       client_sys;     /* 2nd handle for FSINFO */
+        struct rpc_clnt *       client_acl;     /* ACL RPC client handle */
         struct nfs_rpc_ops *    rpc_ops;        /* NFS protocol vector */
         struct backing_dev_info backing_dev_info;
         int                     flags;          /* various flags */
diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h
index 0071428231f9..659c75438454 100644
--- a/include/linux/nfs_mount.h
+++ b/include/linux/nfs_mount.h
@@ -58,6 +58,7 @@ struct nfs_mount_data {
 #define NFS_MOUNT_KERBEROS      0x0100  /* 3 */
 #define NFS_MOUNT_NONLM         0x0200  /* 3 */
 #define NFS_MOUNT_BROKEN_SUID   0x0400  /* 4 */
+#define NFS_MOUNT_NOACL         0x0800  /* 4 */
 #define NFS_MOUNT_STRICTLOCK    0x1000  /* reserved for NFSv4 */
 #define NFS_MOUNT_SECFLAVOUR    0x2000  /* 5 */
 #define NFS_MOUNT_FLAGMASK      0xFFFF
diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h
index 39e4895bcdb4..da2e077b65e2 100644
--- a/include/linux/nfs_page.h
+++ b/include/linux/nfs_page.h
@@ -20,12 +20,19 @@
 #include <asm/atomic.h>
 
 /*
+ * Valid flags for the radix tree
+ */
+#define NFS_PAGE_TAG_DIRTY      0
+#define NFS_PAGE_TAG_WRITEBACK  1
+
+/*
  * Valid flags for a dirty buffer
  */
 #define PG_BUSY                 0
 #define PG_NEED_COMMIT          1
 #define PG_NEED_RESCHED         2
 
+struct nfs_inode;
 struct nfs_page {
         struct list_head        wb_list,        /* Defines state of page: */
                                 *wb_list_head;  /*      read/write/commit */
@@ -54,14 +61,17 @@ extern	void nfs_clear_request(struct nfs_page *req);
 extern  void nfs_release_request(struct nfs_page *req);
 
 
-extern  void nfs_list_add_request(struct nfs_page *, struct list_head *);
-
+extern  int nfs_scan_lock_dirty(struct nfs_inode *nfsi, struct list_head *dst,
+                                unsigned long idx_start, unsigned int npages);
 extern  int nfs_scan_list(struct list_head *, struct list_head *,
                           unsigned long, unsigned int);
 extern  int nfs_coalesce_requests(struct list_head *, struct list_head *,
                                   unsigned int);
 extern  int nfs_wait_on_request(struct nfs_page *);
 extern  void nfs_unlock_request(struct nfs_page *req);
+extern  int nfs_set_page_writeback_locked(struct nfs_page *req);
+extern  void nfs_clear_page_writeback(struct nfs_page *req);
+
 
 /*
  * Lock the page of an asynchronous request without incrementing the wb_count
@@ -86,6 +96,18 @@ nfs_lock_request(struct nfs_page *req)
         return 1;
 }
 
+/**
+ * nfs_list_add_request - Insert a request into a list
+ * @req: request
+ * @head: head of list into which to insert the request.
+ */
+static inline void
+nfs_list_add_request(struct nfs_page *req, struct list_head *head)
+{
+        list_add_tail(&req->wb_list, head);
+        req->wb_list_head = head;
+}
+
 
 /**
  * nfs_list_remove_request - Remove a request from its wb_list
@@ -96,10 +118,6 @@ nfs_list_remove_request(struct nfs_page *req)
 {
         if (list_empty(&req->wb_list))
                 return;
-        if (!NFS_WBACK_BUSY(req)) {
-                printk(KERN_ERR "NFS: unlocked request attempted removed from list!\n");
-                BUG();
-        }
         list_del_init(&req->wb_list);
         req->wb_list_head = NULL;
 }
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 47037d9521cb..a2bf6914ff1b 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -2,6 +2,7 @@
 #define _LINUX_NFS_XDR_H
 
 #include <linux/sunrpc/xprt.h>
+#include <linux/nfsacl.h>
 
 struct nfs4_fsid {
         __u64 major;
@@ -326,6 +327,20 @@ struct nfs_setattrargs {
         const u32 *                     bitmask;
 };
 
+struct nfs_setaclargs {
+        struct nfs_fh *                 fh;
+        size_t                          acl_len;
+        unsigned int                    acl_pgbase;
+        struct page **                  acl_pages;
+};
+
+struct nfs_getaclargs {
+        struct nfs_fh *                 fh;
+        size_t                          acl_len;
+        unsigned int                    acl_pgbase;
+        struct page **                  acl_pages;
+};
+
 struct nfs_setattrres {
         struct nfs_fattr *              fattr;
         const struct nfs_server *       server;
@@ -354,6 +369,20 @@ struct nfs_readdirargs {
         struct page **          pages;
 };
 
+struct nfs3_getaclargs {
+        struct nfs_fh *         fh;
+        int                     mask;
+        struct page **          pages;
+};
+
+struct nfs3_setaclargs {
+        struct inode *          inode;
+        int                     mask;
+        struct posix_acl *      acl_access;
+        struct posix_acl *      acl_default;
+        struct page **          pages;
+};
+
 struct nfs_diropok {
         struct nfs_fh *         fh;
         struct nfs_fattr *      fattr;
@@ -477,6 +506,15 @@ struct nfs3_readdirres {
         int                     plus;
 };
 
+struct nfs3_getaclres {
+        struct nfs_fattr *      fattr;
+        int                     mask;
+        unsigned int            acl_access_count;
+        unsigned int            acl_default_count;
+        struct posix_acl *      acl_access;
+        struct posix_acl *      acl_default;
+};
+
 #ifdef CONFIG_NFS_V4
 
 typedef u64 clientid4;
@@ -667,6 +705,7 @@ struct nfs_rpc_ops {
         int     version;                /* Protocol version */
         struct dentry_operations *dentry_ops;
         struct inode_operations *dir_inode_ops;
+        struct inode_operations *file_inode_ops;
 
         int     (*getroot) (struct nfs_server *, struct nfs_fh *,
                             struct nfs_fsinfo *);
@@ -713,6 +752,7 @@ struct nfs_rpc_ops {
         int     (*file_open)   (struct inode *, struct file *);
         int     (*file_release) (struct inode *, struct file *);
         int     (*lock)(struct file *, int, struct file_lock *);
+        void    (*clear_acl_cache)(struct inode *);
 };
 
 /*
@@ -732,4 +772,7 @@ extern struct rpc_version	nfs_version2;
 extern struct rpc_version       nfs_version3;
 extern struct rpc_version       nfs_version4;
 
+extern struct rpc_version       nfsacl_version3;
+extern struct rpc_program       nfsacl_program;
+
 #endif
diff --git a/include/linux/nfsacl.h b/include/linux/nfsacl.h
new file mode 100644
index 000000000000..54487a99beb8
--- /dev/null
+++ b/include/linux/nfsacl.h
@@ -0,0 +1,58 @@
+/*
+ * File: linux/nfsacl.h
+ *
+ * (C) 2003 Andreas Gruenbacher <agruen@suse.de>
+ */
+#ifndef __LINUX_NFSACL_H
+#define __LINUX_NFSACL_H
+
+#define NFS_ACL_PROGRAM 100227
+
+#define ACLPROC2_GETACL         1
+#define ACLPROC2_SETACL         2
+#define ACLPROC2_GETATTR        3
+#define ACLPROC2_ACCESS         4
+
+#define ACLPROC3_GETACL         1
+#define ACLPROC3_SETACL         2
+
+
+/* Flags for the getacl/setacl mode */
+#define NFS_ACL                 0x0001
+#define NFS_ACLCNT              0x0002
+#define NFS_DFACL               0x0004
+#define NFS_DFACLCNT            0x0008
+
+/* Flag for Default ACL entries */
+#define NFS_ACL_DEFAULT         0x1000
+
+#ifdef __KERNEL__
+
+#include <linux/posix_acl.h>
+
+/* Maximum number of ACL entries over NFS */
+#define NFS_ACL_MAX_ENTRIES     1024
+
+#define NFSACL_MAXWORDS         (2*(2+3*NFS_ACL_MAX_ENTRIES))
+#define NFSACL_MAXPAGES         ((2*(8+12*NFS_ACL_MAX_ENTRIES) + PAGE_SIZE-1) \
+                                 >> PAGE_SHIFT)
+
+static inline unsigned int
+nfsacl_size(struct posix_acl *acl_access, struct posix_acl *acl_default)
+{
+        unsigned int w = 16;
+        w += max(acl_access ? (int)acl_access->a_count : 3, 4) * 12;
+        if (acl_default)
+                w += max((int)acl_default->a_count, 4) * 12;
+        return w;
+}
+
+extern unsigned int
+nfsacl_encode(struct xdr_buf *buf, unsigned int base, struct inode *inode,
+              struct posix_acl *acl, int encode_entries, int typeflag);
+extern unsigned int
+nfsacl_decode(struct xdr_buf *buf, unsigned int base, unsigned int *aclcnt,
+              struct posix_acl **pacl);
+
+#endif /* __KERNEL__ */
+#endif  /* __LINUX_NFSACL_H */
diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h
index 8f85d9a59607..6d5a24f3fc6d 100644
--- a/include/linux/nfsd/nfsd.h
+++ b/include/linux/nfsd/nfsd.h
@@ -15,6 +15,7 @@
 #include <linux/unistd.h>
 #include <linux/dirent.h>
 #include <linux/fs.h>
+#include <linux/posix_acl.h>
 #include <linux/mount.h>
 
 #include <linux/nfsd/debug.h>
@@ -123,21 +124,41 @@ int		nfsd_statfs(struct svc_rqst *, struct svc_fh *,
 
 int             nfsd_notify_change(struct inode *, struct iattr *);
 int             nfsd_permission(struct svc_export *, struct dentry *, int);
+void            nfsd_sync_dir(struct dentry *dp);
+
+#if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL)
+#ifdef CONFIG_NFSD_V2_ACL
+extern struct svc_version nfsd_acl_version2;
+#else
+#define nfsd_acl_version2 NULL
+#endif
+#ifdef CONFIG_NFSD_V3_ACL
+extern struct svc_version nfsd_acl_version3;
+#else
+#define nfsd_acl_version3 NULL
+#endif
+struct posix_acl *nfsd_get_posix_acl(struct svc_fh *, int);
+int nfsd_set_posix_acl(struct svc_fh *, int, struct posix_acl *);
+#endif
 
 
 /* 
  * NFSv4 State
  */
 #ifdef CONFIG_NFSD_V4
-int nfs4_state_init(void);
+void nfs4_state_init(void);
+int nfs4_state_start(void);
 void nfs4_state_shutdown(void);
 time_t nfs4_lease_time(void);
 void nfs4_reset_lease(time_t leasetime);
+int nfs4_reset_recoverydir(char *recdir);
 #else
-static inline int nfs4_state_init(void){return 0;}
+static inline void nfs4_state_init(void){};
+static inline int nfs4_state_start(void){return 0;}
 static inline void nfs4_state_shutdown(void){}
 static inline time_t nfs4_lease_time(void){return 0;}
 static inline void nfs4_reset_lease(time_t leasetime){}
+static inline int nfs4_reset_recoverydir(char *recdir) {return 0;}
 #endif
 
 /*
@@ -210,6 +231,7 @@ void		nfsd_lockd_shutdown(void);
 #define nfserr_reclaim_bad      __constant_htonl(NFSERR_RECLAIM_BAD)
 #define nfserr_badname          __constant_htonl(NFSERR_BADNAME)
 #define nfserr_cb_path_down     __constant_htonl(NFSERR_CB_PATH_DOWN)
+#define nfserr_locked           __constant_htonl(NFSERR_LOCKED)
 
 /* error codes for internal use */
 /* if a request fails due to kmalloc failure, it gets dropped.
diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h
index b6b2fe1e7c63..8bf23cf8b603 100644
--- a/include/linux/nfsd/state.h
+++ b/include/linux/nfsd/state.h
@@ -61,11 +61,6 @@ typedef struct {
 #define si_stateownerid   si_opaque.so_stateownerid
 #define si_fileid         si_opaque.so_fileid
 
-extern stateid_t zerostateid;
-extern stateid_t onestateid;
-
-#define ZERO_STATEID(stateid)       (!memcmp((stateid), &zerostateid, sizeof(stateid_t)))
-#define ONE_STATEID(stateid)        (!memcmp((stateid), &onestateid, sizeof(stateid_t)))
 
 struct nfs4_cb_recall {
         u32                     cbr_ident;
@@ -77,8 +72,8 @@ struct nfs4_cb_recall {
 };
 
 struct nfs4_delegation {
-        struct list_head        dl_del_perfile; /* nfs4_file->fi_del_perfile */
-        struct list_head        dl_del_perclnt; /* nfs4_client->cl_del_perclnt*/
+        struct list_head        dl_perfile;
+        struct list_head        dl_perclnt;
         struct list_head        dl_recall_lru;  /* delegation recalled */
         atomic_t                dl_count;       /* ref count */
         struct nfs4_client      *dl_client;
@@ -97,7 +92,6 @@ struct nfs4_delegation {
 /* client delegation callback info */
 struct nfs4_callback {
         /* SETCLIENTID info */
-        u32                     cb_parsed;  /* addr parsed */
         u32                     cb_addr;
         unsigned short          cb_port;
         u32                     cb_prog;
@@ -109,6 +103,8 @@ struct nfs4_callback {
         struct rpc_clnt *       cb_client;
 };
 
+#define HEXDIR_LEN     33 /* hex version of 16 byte md5 of cl_name plus '\0' */
+
 /*
  * struct nfs4_client - one per client.  Clientids live here.
  *      o Each nfs4_client is hashed by clientid.
@@ -122,10 +118,11 @@ struct nfs4_callback {
 struct nfs4_client {
         struct list_head        cl_idhash;      /* hash by cl_clientid.id */
         struct list_head        cl_strhash;     /* hash by cl_name */
-        struct list_head        cl_perclient;   /* list: stateowners */
-        struct list_head        cl_del_perclnt; /* list: delegations */
+        struct list_head        cl_openowners;
+        struct list_head        cl_delegations;
         struct list_head        cl_lru;         /* tail queue */
         struct xdr_netobj       cl_name;        /* id generated by client */
+        char                    cl_recdir[HEXDIR_LEN]; /* recovery dir */
         nfs4_verifier           cl_verifier;    /* generated by client */
         time_t                  cl_time;        /* time of last lease renewal */
         u32                     cl_addr;        /* client ipaddress */
@@ -134,6 +131,7 @@ struct nfs4_client {
         nfs4_verifier           cl_confirm;     /* generated by server */
         struct nfs4_callback    cl_callback;    /* callback info */
         atomic_t                cl_count;       /* ref count */
+        u32                     cl_firststate;  /* recovery dir creation */
 };
 
 /* struct nfs4_client_reset
@@ -143,7 +141,7 @@ struct nfs4_client {
  */
 struct nfs4_client_reclaim {
         struct list_head        cr_strhash;     /* hash by cr_name */
-        struct xdr_netobj       cr_name;        /* id generated by client */
+        char                    cr_recdir[HEXDIR_LEN]; /* recover dir */
 };
 
 static inline void
@@ -197,15 +195,17 @@ struct nfs4_stateowner {
         struct kref             so_ref;
         struct list_head        so_idhash;   /* hash by so_id */
         struct list_head        so_strhash;   /* hash by op_name */
-        struct list_head        so_perclient; /* nfs4_client->cl_perclient */
-        struct list_head        so_perfilestate; /* list: nfs4_stateid */
-        struct list_head        so_perlockowner; /* nfs4_stateid->st_perlockowner */
+        struct list_head        so_perclient;
+        struct list_head        so_stateids;
+        struct list_head        so_perstateid; /* for lockowners only */
         struct list_head        so_close_lru; /* tail queue */
         time_t                  so_time; /* time of placement on so_close_lru */
         int                     so_is_open_owner; /* 1=openowner,0=lockowner */
         u32                     so_id;
         struct nfs4_client *    so_client;
-        u32                     so_seqid;    
+        /* after increment in ENCODE_SEQID_OP_TAIL, represents the next
+         * sequence id expected from the client: */
+        u32                     so_seqid;
         struct xdr_netobj       so_owner;     /* open owner name */
         int                     so_confirmed; /* successful OPEN_CONFIRM? */
         struct nfs4_replay      so_replay;
@@ -217,9 +217,10 @@ struct nfs4_stateowner {
 *      share_acces, share_deny on the file.
 */
 struct nfs4_file {
+        struct kref             fi_ref;
         struct list_head        fi_hash;    /* hash by "struct inode *" */
-        struct list_head        fi_perfile; /* list: nfs4_stateid */
-        struct list_head        fi_del_perfile; /* list: nfs4_delegation */
+        struct list_head        fi_stateids;
+        struct list_head        fi_delegations;
         struct inode            *fi_inode;
         u32                     fi_id;      /* used with stateowner->so_id 
                                              * for stateid_hashtbl hash */
@@ -236,19 +237,24 @@ struct nfs4_file {
 *       st_perlockowner: (open stateid) list of lock nfs4_stateowners
 *       st_access_bmap: used only for open stateid
 *       st_deny_bmap: used only for open stateid
+*       st_openstp: open stateid lock stateid was derived from
+*
+* XXX: open stateids and lock stateids have diverged sufficiently that
+* we should consider defining separate structs for the two cases.
 */
 
 struct nfs4_stateid {
         struct list_head              st_hash; 
         struct list_head              st_perfile;
-        struct list_head              st_perfilestate; 
-        struct list_head              st_perlockowner;
+        struct list_head              st_perstateowner;
+        struct list_head              st_lockowners;
         struct nfs4_stateowner      * st_stateowner;
         struct nfs4_file            * st_file;
         stateid_t                     st_stateid;
         struct file                 * st_vfs_file;
         unsigned long                 st_access_bmap;
         unsigned long                 st_deny_bmap;
+        struct nfs4_stateid         * st_openstp;
 };
 
 /* flags for preprocess_seqid_op() */
@@ -267,12 +273,9 @@ struct nfs4_stateid {
         ((err) != nfserr_stale_stateid) &&      \
         ((err) != nfserr_bad_stateid))
 
-extern time_t nfs4_laundromat(void);
 extern int nfsd4_renew(clientid_t *clid);
 extern int nfs4_preprocess_stateid_op(struct svc_fh *current_fh, 
                 stateid_t *stateid, int flags, struct file **filp);
-extern int nfs4_share_conflict(struct svc_fh *current_fh, 
-                unsigned int deny_type);
 extern void nfs4_lock_state(void);
 extern void nfs4_unlock_state(void);
 extern int nfs4_in_grace(void);
@@ -282,6 +285,15 @@ extern void nfs4_free_stateowner(struct kref *kref);
 extern void nfsd4_probe_callback(struct nfs4_client *clp);
 extern void nfsd4_cb_recall(struct nfs4_delegation *dp);
 extern void nfs4_put_delegation(struct nfs4_delegation *dp);
+extern int nfs4_make_rec_clidname(char *clidname, struct xdr_netobj *clname);
+extern void nfsd4_init_recdir(char *recdir_name);
+extern int nfsd4_recdir_load(void);
+extern void nfsd4_shutdown_recdir(void);
+extern int nfs4_client_to_reclaim(const char *name);
+extern int nfs4_has_reclaimed_state(const char *name);
+extern void nfsd4_recdir_purge_old(void);
+extern int nfsd4_create_clid_dir(struct nfs4_client *clp);
+extern void nfsd4_remove_clid_dir(struct nfs4_client *clp);
 
 static inline void
 nfs4_put_stateowner(struct nfs4_stateowner *so)
diff --git a/include/linux/nfsd/xdr.h b/include/linux/nfsd/xdr.h
index ecccef777dae..130d4f588a37 100644
--- a/include/linux/nfsd/xdr.h
+++ b/include/linux/nfsd/xdr.h
@@ -169,4 +169,8 @@ int nfssvc_encode_entry(struct readdir_cd *, const char *name,
 
 int nfssvc_release_fhandle(struct svc_rqst *, u32 *, struct nfsd_fhandle *);
 
+/* Helper functions for NFSv2 ACL code */
+u32 *nfs2svc_encode_fattr(struct svc_rqst *rqstp, u32 *p, struct svc_fh *fhp);
+u32 *nfs2svc_decode_fh(u32 *p, struct svc_fh *fhp);
+
 #endif /* LINUX_NFSD_H */
diff --git a/include/linux/nfsd/xdr3.h b/include/linux/nfsd/xdr3.h
index 0ae9e0ef5f68..21e18ce7ca63 100644
--- a/include/linux/nfsd/xdr3.h
+++ b/include/linux/nfsd/xdr3.h
@@ -110,6 +110,19 @@ struct nfsd3_commitargs {
         __u32                   count;
 };
 
+struct nfsd3_getaclargs {
+        struct svc_fh           fh;
+        int                     mask;
+};
+
+struct posix_acl;
+struct nfsd3_setaclargs {
+        struct svc_fh           fh;
+        int                     mask;
+        struct posix_acl        *acl_access;
+        struct posix_acl        *acl_default;
+};
+
 struct nfsd3_attrstat {
         __u32                   status;
         struct svc_fh           fh;
@@ -209,6 +222,14 @@ struct nfsd3_commitres {
         struct svc_fh           fh;
 };
 
+struct nfsd3_getaclres {
+        __u32                   status;
+        struct svc_fh           fh;
+        int                     mask;
+        struct posix_acl        *acl_access;
+        struct posix_acl        *acl_default;
+};
+
 /* dummy type for release */
 struct nfsd3_fhandle_pair {
         __u32                   dummy;
@@ -241,6 +262,7 @@ union nfsd3_xdrstore {
         struct nfsd3_fsinfores          fsinfores;
         struct nfsd3_pathconfres        pathconfres;
         struct nfsd3_commitres          commitres;
+        struct nfsd3_getaclres          getaclres;
 };
 
 #define NFS3_SVC_XDRSIZE                sizeof(union nfsd3_xdrstore)
@@ -316,6 +338,10 @@ int nfs3svc_encode_entry(struct readdir_cd *, const char *name,
 int nfs3svc_encode_entry_plus(struct readdir_cd *, const char *name,
                                 int namlen, loff_t offset, ino_t ino,
                                 unsigned int);
+/* Helper functions for NFSv3 ACL code */
+u32 *nfs3svc_encode_post_op_attr(struct svc_rqst *rqstp, u32 *p,
+                                struct svc_fh *fhp);
+u32 *nfs3svc_decode_fh(u32 *p, struct svc_fh *fhp);
 
 
 #endif /* _LINUX_NFSD_XDR3_H */
diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h
index a1f5ad0be1bf..4d24d65c0e88 100644
--- a/include/linux/nfsd/xdr4.h
+++ b/include/linux/nfsd/xdr4.h
@@ -210,6 +210,7 @@ struct nfsd4_open {
         u32             op_share_access;    /* request */
         u32             op_share_deny;      /* request */
         stateid_t       op_stateid;         /* response */
+        u32             op_recall;          /* recall */
         struct nfsd4_change_info  op_cinfo; /* response */
         u32             op_rflags;          /* response */
         int             op_truncate;        /* used during processing */
diff --git a/include/linux/nfsd_idmap.h b/include/linux/nfsd_idmap.h
index 9bb7f30e923b..e82746fcad14 100644
--- a/include/linux/nfsd_idmap.h
+++ b/include/linux/nfsd_idmap.h
@@ -43,8 +43,13 @@
 /* XXX from linux/nfs_idmap.h */
 #define IDMAP_NAMESZ 128
 
+#ifdef CONFIG_NFSD_V4
 void nfsd_idmap_init(void);
 void nfsd_idmap_shutdown(void);
+#else
+static inline void nfsd_idmap_init(void) {};
+static inline void nfsd_idmap_shutdown(void) {};
+#endif
 
 int nfsd_map_name_to_uid(struct svc_rqst *, const char *, size_t, __u32 *);
 int nfsd_map_name_to_gid(struct svc_rqst *, const char *, size_t, __u32 *);
diff --git a/include/linux/node.h b/include/linux/node.h
index 6e0a697e594e..254dc3de650b 100644
--- a/include/linux/node.h
+++ b/include/linux/node.h
@@ -27,6 +27,7 @@ struct node {
 };
 
 extern int register_node(struct node *, int, struct node *);
+extern void unregister_node(struct node *node);
 
 #define to_node(sys_device) container_of(sys_device, struct node, sysdev)
 
diff --git a/include/linux/numa.h b/include/linux/numa.h
index bd0c8c4e9a95..f0c539bd3cfc 100644
--- a/include/linux/numa.h
+++ b/include/linux/numa.h
@@ -3,7 +3,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_DISCONTIGMEM
+#ifndef CONFIG_FLATMEM
 #include <asm/numnodes.h>
 #endif
 
diff --git a/include/linux/nvram.h b/include/linux/nvram.h
index b031e41b5e0d..9189829c131c 100644
--- a/include/linux/nvram.h
+++ b/include/linux/nvram.h
@@ -20,8 +20,6 @@ extern void __nvram_write_byte(unsigned char c, int i);
 extern void nvram_write_byte(unsigned char c, int i);
 extern int __nvram_check_checksum(void);
 extern int nvram_check_checksum(void);
-extern void __nvram_set_checksum(void);
-extern void nvram_set_checksum(void);
 #endif
 
 #endif  /* _LINUX_NVRAM_H */
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 39ab8c6b5652..f34767c5fc79 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -61,21 +61,20 @@
 #define PG_active                6
 #define PG_slab                  7      /* slab debug (Suparna wants this) */
 
-#define PG_highmem               8
-#define PG_checked               9      /* kill me in 2.5.<early>. */
-#define PG_arch_1               10
-#define PG_reserved             11
-
-#define PG_private              12      /* Has something at ->private */
-#define PG_writeback            13      /* Page is under writeback */
-#define PG_nosave               14      /* Used for system suspend/resume */
-#define PG_compound             15      /* Part of a compound page */
-
-#define PG_swapcache            16      /* Swap page: swp_entry_t in private */
-#define PG_mappedtodisk         17      /* Has blocks allocated on-disk */
-#define PG_reclaim              18      /* To be reclaimed asap */
-#define PG_nosave_free          19      /* Free, should not be written */
-#define PG_uncached             20      /* Page has been mapped as uncached */
+#define PG_checked               8      /* kill me in 2.5.<early>. */
+#define PG_arch_1                9
+#define PG_reserved             10
+#define PG_private              11      /* Has something at ->private */
+
+#define PG_writeback            12      /* Page is under writeback */
+#define PG_nosave               13      /* Used for system suspend/resume */
+#define PG_compound             14      /* Part of a compound page */
+#define PG_swapcache            15      /* Swap page: swp_entry_t in private */
+
+#define PG_mappedtodisk         16      /* Has blocks allocated on-disk */
+#define PG_reclaim              17      /* To be reclaimed asap */
+#define PG_nosave_free          18      /* Free, should not be written */
+#define PG_uncached             19      /* Page has been mapped as uncached */
 
 /*
  * Global page accounting.  One instance per CPU.  Only unsigned longs are
@@ -135,9 +134,10 @@ struct page_state {
 };
 
 extern void get_page_state(struct page_state *ret);
+extern void get_page_state_node(struct page_state *ret, int node);
 extern void get_full_page_state(struct page_state *ret);
-extern unsigned long __read_page_state(unsigned offset);
-extern void __mod_page_state(unsigned offset, unsigned long delta);
+extern unsigned long __read_page_state(unsigned long offset);
+extern void __mod_page_state(unsigned long offset, unsigned long delta);
 
 #define read_page_state(member) \
         __read_page_state(offsetof(struct page_state, member))
@@ -195,6 +195,7 @@ extern void __mod_page_state(unsigned offset, unsigned long delta);
 #define SetPageDirty(page)      set_bit(PG_dirty, &(page)->flags)
 #define TestSetPageDirty(page)  test_and_set_bit(PG_dirty, &(page)->flags)
 #define ClearPageDirty(page)    clear_bit(PG_dirty, &(page)->flags)
+#define __ClearPageDirty(page)  __clear_bit(PG_dirty, &(page)->flags)
 #define TestClearPageDirty(page) test_and_clear_bit(PG_dirty, &(page)->flags)
 
 #define SetPageLRU(page)        set_bit(PG_lru, &(page)->flags)
@@ -215,7 +216,7 @@ extern void __mod_page_state(unsigned offset, unsigned long delta);
 #define TestSetPageSlab(page)   test_and_set_bit(PG_slab, &(page)->flags)
 
 #ifdef CONFIG_HIGHMEM
-#define PageHighMem(page)       test_bit(PG_highmem, &(page)->flags)
+#define PageHighMem(page)       is_highmem(page_zone(page))
 #else
 #define PageHighMem(page)       0 /* needed to optimize away at compile time */
 #endif
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index 0422031161ba..d9a25647a295 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -52,12 +52,12 @@ void release_pages(struct page **pages, int nr, int cold);
 
 static inline struct page *page_cache_alloc(struct address_space *x)
 {
-        return alloc_pages(mapping_gfp_mask(x), 0);
+        return alloc_pages(mapping_gfp_mask(x)|__GFP_NORECLAIM, 0);
 }
 
 static inline struct page *page_cache_alloc_cold(struct address_space *x)
 {
-        return alloc_pages(mapping_gfp_mask(x)|__GFP_COLD, 0);
+        return alloc_pages(mapping_gfp_mask(x)|__GFP_COLD|__GFP_NORECLAIM, 0);
 }
 
 typedef int filler_t(void *, struct page *);
diff --git a/include/linux/pci-dynids.h b/include/linux/pci-dynids.h
deleted file mode 100644
index 183b6b0de81c..000000000000
--- a/include/linux/pci-dynids.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *      PCI defines and function prototypes
- *      Copyright 2003 Dell Inc.
- *        by Matt Domsch <Matt_Domsch@dell.com>
- */
-
-#ifndef LINUX_PCI_DYNIDS_H
-#define LINUX_PCI_DYNIDS_H
-
-#include <linux/list.h>
-#include <linux/mod_devicetable.h>
-
-struct dynid {
-        struct list_head        node;
-        struct pci_device_id    id;
-};
-
-#endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index b5238bd18830..bc4c40000c0d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -556,7 +556,8 @@ struct pci_dev {
         /* keep track of device state */
         unsigned int    is_enabled:1;   /* pci_enable_device has been called */
         unsigned int    is_busmaster:1; /* device is busmaster */
-        
+        unsigned int    no_msi:1;       /* device may not use msi */
+
         u32             saved_config_space[16]; /* config space saved at suspend time */
         struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
         int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
@@ -586,7 +587,7 @@ struct pci_dev {
 #define PCI_NUM_RESOURCES 11
 
 #ifndef PCI_BUS_NUM_RESOURCES
-#define PCI_BUS_NUM_RESOURCES 4
+#define PCI_BUS_NUM_RESOURCES 8
 #endif
   
 #define PCI_REGION_FLAG_MASK 0x0fU      /* These bits of resource flags tell us the PCI region flags */
@@ -734,16 +735,20 @@ void pcibios_update_irq(struct pci_dev *, int irq);
 /* Generic PCI functions used internally */
 
 extern struct pci_bus *pci_find_bus(int domain, int busnr);
+void pci_bus_add_devices(struct pci_bus *bus);
 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
 static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
 {
-        return pci_scan_bus_parented(NULL, bus, ops, sysdata);
+        struct pci_bus *root_bus;
+        root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
+        if (root_bus)
+                pci_bus_add_devices(root_bus);
+        return root_bus;
 }
 int pci_scan_slot(struct pci_bus *bus, int devfn);
 struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
 unsigned int pci_scan_child_bus(struct pci_bus *bus);
 void pci_bus_add_device(struct pci_dev *dev);
-void pci_bus_add_devices(struct pci_bus *bus);
 void pci_name_device(struct pci_dev *dev);
 char *pci_class_name(u32 class);
 void pci_read_bridge_bases(struct pci_bus *child);
@@ -856,7 +861,8 @@ int pci_register_driver(struct pci_driver *);
 void pci_unregister_driver(struct pci_driver *);
 void pci_remove_behind_bridge(struct pci_dev *);
 struct pci_driver *pci_dev_driver(const struct pci_dev *);
-const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
+const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
+const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
 
 /* kmem_cache style wrapper around pci_alloc_consistent() */
@@ -870,6 +876,15 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass
 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
 
+enum pci_dma_burst_strategy {
+        PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
+                                   strategy_parameter is N/A */
+        PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
+                                   byte boundaries */
+        PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
+                                   strategy_parameter byte boundaries */
+};
+
 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 extern struct pci_dev *isa_bridge;
 #endif
@@ -957,6 +972,8 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
 
 #define isa_bridge      ((struct pci_dev *)NULL)
 
+#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
+
 #else
 
 /*
@@ -971,7 +988,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
         return 0;
 }
 #endif
-
 #endif /* !CONFIG_PCI */
 
 /* these helpers provide future and backwards compatibility
@@ -1016,6 +1032,20 @@ static inline char *pci_name(struct pci_dev *pdev)
 #define pci_pretty_name(dev) ""
 #endif
 
+
+/* Some archs don't want to expose struct resource to userland as-is
+ * in sysfs and /proc
+ */
+#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
+static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
+                const struct resource *rsrc, u64 *start, u64 *end)
+{
+        *start = rsrc->start;
+        *end = rsrc->end;
+}
+#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
+
+
 /*
  *  The world is not perfect and supplies us with broken PCI devices.
  *  For at least a part of these bugs we need a work-around, so both
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index b8b4ebf9abf1..ee0ab7a5f91b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -62,6 +62,8 @@
 
 #define PCI_BASE_CLASS_SYSTEM           0x08
 #define PCI_CLASS_SYSTEM_PIC            0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC     0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC    0x080020
 #define PCI_CLASS_SYSTEM_DMA            0x0801
 #define PCI_CLASS_SYSTEM_TIMER          0x0802
 #define PCI_CLASS_SYSTEM_RTC            0x0803
@@ -575,6 +577,7 @@
 #define PCI_DEVICE_ID_CT_65550          0x00e0
 #define PCI_DEVICE_ID_CT_65554          0x00e4
 #define PCI_DEVICE_ID_CT_65555          0x00e5
+#define PCI_DEVICE_ID_CT_69000          0x00c0
 
 #define PCI_VENDOR_ID_MIRO              0x1031
 #define PCI_DEVICE_ID_MIRO_36050        0x5601
@@ -711,8 +714,9 @@
 #define PCI_DEVICE_ID_HP_DIVA_AUX       0x1290
 #define PCI_DEVICE_ID_HP_DIVA_RMP3      0x1301
 #define PCI_DEVICE_ID_HP_CISSA          0x3220
-#define PCI_DEVICE_ID_HP_CISSB          0x3230
+#define PCI_DEVICE_ID_HP_CISSB          0x3222
 #define PCI_DEVICE_ID_HP_ZX2_IOC        0x4031
+#define PCI_DEVICE_ID_HP_CISSC          0x3230
 
 #define PCI_VENDOR_ID_PCTECH            0x1042
 #define PCI_DEVICE_ID_PCTECH_RZ1000     0x1000
@@ -877,7 +881,7 @@
 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
 #define PCI_DEVICE_ID_APPLE_UNI_N_FW2   0x0030
 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
-#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA   0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA   0x0033
 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP2  0x0034
 #define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
 #define PCI_DEVICE_ID_APPLE_KEYLARGO_I  0x003e
@@ -907,6 +911,15 @@
 #define PCI_DEVICE_ID_QLOGIC_ISP1022    0x1022
 #define PCI_DEVICE_ID_QLOGIC_ISP2100    0x2100
 #define PCI_DEVICE_ID_QLOGIC_ISP2200    0x2200
+#define PCI_DEVICE_ID_QLOGIC_ISP2300    0x2300
+#define PCI_DEVICE_ID_QLOGIC_ISP2312    0x2312
+#define PCI_DEVICE_ID_QLOGIC_ISP2322    0x2322
+#define PCI_DEVICE_ID_QLOGIC_ISP6312    0x6312
+#define PCI_DEVICE_ID_QLOGIC_ISP6322    0x6322
+#define PCI_DEVICE_ID_QLOGIC_ISP2422    0x2422
+#define PCI_DEVICE_ID_QLOGIC_ISP2432    0x2432
+#define PCI_DEVICE_ID_QLOGIC_ISP2512    0x2512
+#define PCI_DEVICE_ID_QLOGIC_ISP2522    0x2522
 
 #define PCI_VENDOR_ID_CYRIX             0x1078
 #define PCI_DEVICE_ID_CYRIX_5510        0x0000
@@ -1007,6 +1020,7 @@
 #define PCI_DEVICE_ID_PLX_SPCOM200      0x1103
 #define PCI_DEVICE_ID_PLX_DJINN_ITOO    0x1151
 #define PCI_DEVICE_ID_PLX_R753          0x1152
+#define PCI_DEVICE_ID_PLX_OLITEC        0x1187
 #define PCI_DEVICE_ID_PLX_9030          0x9030
 #define PCI_DEVICE_ID_PLX_9050          0x9050
 #define PCI_DEVICE_ID_PLX_9060          0x9060
@@ -1234,6 +1248,8 @@
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE   0x0265
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA  0x0266
 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE   0x036E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA  0x036F
 #define PCI_DEVICE_ID_NVIDIA_NVENET_12          0x0268
 #define PCI_DEVICE_ID_NVIDIA_NVENET_13          0x0269
 #define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO        0x026B
@@ -1283,6 +1299,8 @@
 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
 #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
 #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+#define PCI_DEVICE_ID_NVIDIA_NVENET_14              0x0372
+#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
 
 #define PCI_VENDOR_ID_IMS               0x10e0
 #define PCI_DEVICE_ID_IMS_8849          0x8849
@@ -1563,10 +1581,12 @@
 #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
 #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
 #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
 #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_GCLE    0x0225
 #define PCI_DEVICE_ID_SERVERWORKS_GCLE2   0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
@@ -1592,6 +1612,7 @@
 #define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
 #define PCI_DEVICE_ID_TOSHIBA_TX4927    0x0180
 #define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC     0x0108
+#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
 
 #define PCI_VENDOR_ID_RICOH             0x1180
 #define PCI_DEVICE_ID_RICOH_RL5C465     0x0465
@@ -1810,6 +1831,8 @@
 #define PCI_VENDOR_ID_ITE               0x1283
 #define PCI_DEVICE_ID_ITE_IT8172G       0x8172
 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
+#define PCI_DEVICE_ID_ITE_8211          0x8211
+#define PCI_DEVICE_ID_ITE_8212          0x8212
 #define PCI_DEVICE_ID_ITE_8872          0x8872
 #define PCI_DEVICE_ID_ITE_IT8330G_0     0xe886
 
@@ -1862,6 +1885,7 @@
 #define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
 
 #define PCI_VENDOR_ID_SIIG              0x131f
+#define PCI_SUBVENDOR_ID_SIIG           0x131f
 #define PCI_DEVICE_ID_SIIG_1S_10x_550   0x1000
 #define PCI_DEVICE_ID_SIIG_1S_10x_650   0x1001
 #define PCI_DEVICE_ID_SIIG_1S_10x_850   0x1002
@@ -1899,6 +1923,7 @@
 #define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060
 #define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061
 #define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062
+#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL    0x2050
 
 #define PCI_VENDOR_ID_RADISYS           0x1331
 #define PCI_DEVICE_ID_RADISYS_ENP2611   0x0030
@@ -2086,6 +2111,8 @@
 #define PCI_DEVICE_ID_TIGON3_5721       0x1659
 #define PCI_DEVICE_ID_TIGON3_5705M      0x165d
 #define PCI_DEVICE_ID_TIGON3_5705M_2    0x165e
+#define PCI_DEVICE_ID_TIGON3_5780       0x166a
+#define PCI_DEVICE_ID_TIGON3_5780S      0x166b
 #define PCI_DEVICE_ID_TIGON3_5705F      0x166e
 #define PCI_DEVICE_ID_TIGON3_5750       0x1676
 #define PCI_DEVICE_ID_TIGON3_5751       0x1677
@@ -2119,6 +2146,10 @@
 #define PCI_DEVICE_ID_ENE_1225          0x1225
 #define PCI_DEVICE_ID_ENE_1410          0x1410
 #define PCI_DEVICE_ID_ENE_1420          0x1420
+#define PCI_VENDOR_ID_CHELSIO           0x1425
+
+#define PCI_VENDOR_ID_MIPS              0x153f
+#define PCI_DEVICE_ID_SOC_IT            0x0001
 
 #define PCI_VENDOR_ID_SYBA              0x1592
 #define PCI_DEVICE_ID_SYBA_2P_EPP       0x0782
@@ -2160,6 +2191,9 @@
 #define PCI_VENDOR_ID_SIBYTE            0x166d
 #define PCI_DEVICE_ID_BCM1250_HT        0x0002
 
+#define PCI_VENDOR_ID_NETCELL           0x169c
+#define PCI_DEVICE_ID_REVOLUTION        0x0044
+
 #define PCI_VENDOR_ID_LINKSYS           0x1737
 #define PCI_DEVICE_ID_LINKSYS_EG1032    0x1032
 #define PCI_DEVICE_ID_LINKSYS_EG1064    0x1064
@@ -2257,6 +2291,11 @@
 #define PCI_VENDOR_ID_INTEL             0x8086
 #define PCI_DEVICE_ID_INTEL_EESSC       0x0008
 #define PCI_DEVICE_ID_INTEL_21145       0x0039
+#define PCI_DEVICE_ID_INTEL_PXHD_0      0x0320
+#define PCI_DEVICE_ID_INTEL_PXHD_1      0x0321
+#define PCI_DEVICE_ID_INTEL_PXH_0       0x0329
+#define PCI_DEVICE_ID_INTEL_PXH_1       0x032A
+#define PCI_DEVICE_ID_INTEL_PXHV        0x032C
 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 #define PCI_DEVICE_ID_INTEL_82378       0x0484
diff --git a/include/linux/pfkeyv2.h b/include/linux/pfkeyv2.h
index e6b519220245..724066778aff 100644
--- a/include/linux/pfkeyv2.h
+++ b/include/linux/pfkeyv2.h
@@ -245,6 +245,7 @@ struct sadb_x_nat_t_port {
 
 /* Security Association flags */
 #define SADB_SAFLAGS_PFS        1
+#define SADB_SAFLAGS_NOPMTUDISC 0x20000000
 #define SADB_SAFLAGS_DECAP_DSCP 0x40000000
 #define SADB_SAFLAGS_NOECN      0x80000000
 
diff --git a/include/linux/phy.h b/include/linux/phy.h
new file mode 100644
index 000000000000..72cb67b66e0c
--- /dev/null
+++ b/include/linux/phy.h
@@ -0,0 +1,377 @@
+/*
+ * include/linux/phy.h
+ *
+ * Framework and drivers for configuring and reading different PHYs
+ * Based on code in sungem_phy.c and gianfar_phy.c
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2004 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __PHY_H
+#define __PHY_H
+
+#include <linux/spinlock.h>
+#include <linux/device.h>
+
+#define PHY_BASIC_FEATURES      (SUPPORTED_10baseT_Half | \
+                                 SUPPORTED_10baseT_Full | \
+                                 SUPPORTED_100baseT_Half | \
+                                 SUPPORTED_100baseT_Full | \
+                                 SUPPORTED_Autoneg | \
+                                 SUPPORTED_TP | \
+                                 SUPPORTED_MII)
+
+#define PHY_GBIT_FEATURES       (PHY_BASIC_FEATURES | \
+                                 SUPPORTED_1000baseT_Half | \
+                                 SUPPORTED_1000baseT_Full)
+
+/* Set phydev->irq to PHY_POLL if interrupts are not supported,
+ * or not desired for this PHY.  Set to PHY_IGNORE_INTERRUPT if
+ * the attached driver handles the interrupt
+ */
+#define PHY_POLL                -1
+#define PHY_IGNORE_INTERRUPT    -2
+
+#define PHY_HAS_INTERRUPT       0x00000001
+#define PHY_HAS_MAGICANEG       0x00000002
+
+#define MII_BUS_MAX 4
+
+
+#define PHY_INIT_TIMEOUT 100000
+#define PHY_STATE_TIME          1
+#define PHY_FORCE_TIMEOUT       10
+#define PHY_AN_TIMEOUT          10
+
+#define PHY_MAX_ADDR 32
+
+/* The Bus class for PHYs.  Devices which provide access to
+ * PHYs should register using this structure */
+struct mii_bus {
+        const char *name;
+        int id;
+        void *priv;
+        int (*read)(struct mii_bus *bus, int phy_id, int regnum);
+        int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
+        int (*reset)(struct mii_bus *bus);
+
+        /* A lock to ensure that only one thing can read/write
+         * the MDIO bus at a time */
+        spinlock_t mdio_lock;
+
+        struct device *dev;
+
+        /* list of all PHYs on bus */
+        struct phy_device *phy_map[PHY_MAX_ADDR];
+
+        /* Pointer to an array of interrupts, each PHY's
+         * interrupt at the index matching its address */
+        int *irq;
+};
+
+#define PHY_INTERRUPT_DISABLED 0x0
+#define PHY_INTERRUPT_ENABLED 0x80000000
+
+/* PHY state machine states:
+ *
+ * DOWN: PHY device and driver are not ready for anything.  probe
+ * should be called if and only if the PHY is in this state,
+ * given that the PHY device exists.
+ * - PHY driver probe function will, depending on the PHY, set
+ * the state to STARTING or READY
+ *
+ * STARTING:  PHY device is coming up, and the ethernet driver is
+ * not ready.  PHY drivers may set this in the probe function.
+ * If they do, they are responsible for making sure the state is
+ * eventually set to indicate whether the PHY is UP or READY,
+ * depending on the state when the PHY is done starting up.
+ * - PHY driver will set the state to READY
+ * - start will set the state to PENDING
+ *
+ * READY: PHY is ready to send and receive packets, but the
+ * controller is not.  By default, PHYs which do not implement
+ * probe will be set to this state by phy_probe().  If the PHY
+ * driver knows the PHY is ready, and the PHY state is STARTING,
+ * then it sets this STATE.
+ * - start will set the state to UP
+ *
+ * PENDING: PHY device is coming up, but the ethernet driver is
+ * ready.  phy_start will set this state if the PHY state is
+ * STARTING.
+ * - PHY driver will set the state to UP when the PHY is ready
+ *
+ * UP: The PHY and attached device are ready to do work.
+ * Interrupts should be started here.
+ * - timer moves to AN
+ *
+ * AN: The PHY is currently negotiating the link state.  Link is
+ * therefore down for now.  phy_timer will set this state when it
+ * detects the state is UP.  config_aneg will set this state
+ * whenever called with phydev->autoneg set to AUTONEG_ENABLE.
+ * - If autonegotiation finishes, but there's no link, it sets
+ *   the state to NOLINK.
+ * - If aneg finishes with link, it sets the state to RUNNING,
+ *   and calls adjust_link
+ * - If autonegotiation did not finish after an arbitrary amount
+ *   of time, autonegotiation should be tried again if the PHY
+ *   supports "magic" autonegotiation (back to AN)
+ * - If it didn't finish, and no magic_aneg, move to FORCING.
+ *
+ * NOLINK: PHY is up, but not currently plugged in.
+ * - If the timer notes that the link comes back, we move to RUNNING
+ * - config_aneg moves to AN
+ * - phy_stop moves to HALTED
+ *
+ * FORCING: PHY is being configured with forced settings
+ * - if link is up, move to RUNNING
+ * - If link is down, we drop to the next highest setting, and
+ *   retry (FORCING) after a timeout
+ * - phy_stop moves to HALTED
+ *
+ * RUNNING: PHY is currently up, running, and possibly sending
+ * and/or receiving packets
+ * - timer will set CHANGELINK if we're polling (this ensures the
+ *   link state is polled every other cycle of this state machine,
+ *   which makes it every other second)
+ * - irq will set CHANGELINK
+ * - config_aneg will set AN
+ * - phy_stop moves to HALTED
+ *
+ * CHANGELINK: PHY experienced a change in link state
+ * - timer moves to RUNNING if link
+ * - timer moves to NOLINK if the link is down
+ * - phy_stop moves to HALTED
+ *
+ * HALTED: PHY is up, but no polling or interrupts are done. Or
+ * PHY is in an error state.
+ *
+ * - phy_start moves to RESUMING
+ *
+ * RESUMING: PHY was halted, but now wants to run again.
+ * - If we are forcing, or aneg is done, timer moves to RUNNING
+ * - If aneg is not done, timer moves to AN
+ * - phy_stop moves to HALTED
+ */
+enum phy_state {
+        PHY_DOWN=0,
+        PHY_STARTING,
+        PHY_READY,
+        PHY_PENDING,
+        PHY_UP,
+        PHY_AN,
+        PHY_RUNNING,
+        PHY_NOLINK,
+        PHY_FORCING,
+        PHY_CHANGELINK,
+        PHY_HALTED,
+        PHY_RESUMING
+};
+
+/* phy_device: An instance of a PHY
+ *
+ * drv: Pointer to the driver for this PHY instance
+ * bus: Pointer to the bus this PHY is on
+ * dev: driver model device structure for this PHY
+ * phy_id: UID for this device found during discovery
+ * state: state of the PHY for management purposes
+ * dev_flags: Device-specific flags used by the PHY driver.
+ * addr: Bus address of PHY
+ * link_timeout: The number of timer firings to wait before the
+ * giving up on the current attempt at acquiring a link
+ * irq: IRQ number of the PHY's interrupt (-1 if none)
+ * phy_timer: The timer for handling the state machine
+ * phy_queue: A work_queue for the interrupt
+ * attached_dev: The attached enet driver's device instance ptr
+ * adjust_link: Callback for the enet controller to respond to
+ * changes in the link state.
+ * adjust_state: Callback for the enet driver to respond to
+ * changes in the state machine.
+ *
+ * speed, duplex, pause, supported, advertising, and
+ * autoneg are used like in mii_if_info
+ *
+ * interrupts currently only supports enabled or disabled,
+ * but could be changed in the future to support enabling
+ * and disabling specific interrupts
+ *
+ * Contains some infrastructure for polling and interrupt
+ * handling, as well as handling shifts in PHY hardware state
+ */
+struct phy_device {
+        /* Information about the PHY type */
+        /* And management functions */
+        struct phy_driver *drv;
+
+        struct mii_bus *bus;
+
+        struct device dev;
+
+        u32 phy_id;
+
+        enum phy_state state;
+
+        u32 dev_flags;
+
+        /* Bus address of the PHY (0-32) */
+        int addr;
+
+        /* forced speed & duplex (no autoneg)
+         * partner speed & duplex & pause (autoneg)
+         */
+        int speed;
+        int duplex;
+        int pause;
+        int asym_pause;
+
+        /* The most recently read link state */
+        int link;
+
+        /* Enabled Interrupts */
+        u32 interrupts;
+
+        /* Union of PHY and Attached devices' supported modes */
+        /* See mii.h for more info */
+        u32 supported;
+        u32 advertising;
+
+        int autoneg;
+
+        int link_timeout;
+
+        /* Interrupt number for this PHY
+         * -1 means no interrupt */
+        int irq;
+
+        /* private data pointer */
+        /* For use by PHYs to maintain extra state */
+        void *priv;
+
+        /* Interrupt and Polling infrastructure */
+        struct work_struct phy_queue;
+        struct timer_list phy_timer;
+
+        spinlock_t lock;
+
+        struct net_device *attached_dev;
+
+        void (*adjust_link)(struct net_device *dev);
+
+        void (*adjust_state)(struct net_device *dev);
+};
+#define to_phy_device(d) container_of(d, struct phy_device, dev)
+
+/* struct phy_driver: Driver structure for a particular PHY type
+ *
+ * phy_id: The result of reading the UID registers of this PHY
+ *   type, and ANDing them with the phy_id_mask.  This driver
+ *   only works for PHYs with IDs which match this field
+ * name: The friendly name of this PHY type
+ * phy_id_mask: Defines the important bits of the phy_id
+ * features: A list of features (speed, duplex, etc) supported
+ *   by this PHY
+ * flags: A bitfield defining certain other features this PHY
+ *   supports (like interrupts)
+ *
+ * The drivers must implement config_aneg and read_status.  All
+ * other functions are optional. Note that none of these
+ * functions should be called from interrupt time.  The goal is
+ * for the bus read/write functions to be able to block when the
+ * bus transaction is happening, and be freed up by an interrupt
+ * (The MPC85xx has this ability, though it is not currently
+ * supported in the driver).
+ */
+struct phy_driver {
+        u32 phy_id;
+        char *name;
+        unsigned int phy_id_mask;
+        u32 features;
+        u32 flags;
+
+        /* Called to initialize the PHY,
+         * including after a reset */
+        int (*config_init)(struct phy_device *phydev);
+
+        /* Called during discovery.  Used to set
+         * up device-specific structures, if any */
+        int (*probe)(struct phy_device *phydev);
+
+        /* PHY Power Management */
+        int (*suspend)(struct phy_device *phydev);
+        int (*resume)(struct phy_device *phydev);
+
+        /* Configures the advertisement and resets
+         * autonegotiation if phydev->autoneg is on,
+         * forces the speed to the current settings in phydev
+         * if phydev->autoneg is off */
+        int (*config_aneg)(struct phy_device *phydev);
+
+        /* Determines the negotiated speed and duplex */
+        int (*read_status)(struct phy_device *phydev);
+
+        /* Clears any pending interrupts */
+        int (*ack_interrupt)(struct phy_device *phydev);
+
+        /* Enables or disables interrupts */
+        int (*config_intr)(struct phy_device *phydev);
+
+        /* Clears up any memory if needed */
+        void (*remove)(struct phy_device *phydev);
+
+        struct device_driver driver;
+};
+#define to_phy_driver(d) container_of(d, struct phy_driver, driver)
+
+int phy_read(struct phy_device *phydev, u16 regnum);
+int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
+struct phy_device* get_phy_device(struct mii_bus *bus, int addr);
+int phy_clear_interrupt(struct phy_device *phydev);
+int phy_config_interrupt(struct phy_device *phydev, u32 interrupts);
+struct phy_device * phy_attach(struct net_device *dev,
+                const char *phy_id, u32 flags);
+struct phy_device * phy_connect(struct net_device *dev, const char *phy_id,
+                void (*handler)(struct net_device *), u32 flags);
+void phy_disconnect(struct phy_device *phydev);
+void phy_detach(struct phy_device *phydev);
+void phy_start(struct phy_device *phydev);
+void phy_stop(struct phy_device *phydev);
+int phy_start_aneg(struct phy_device *phydev);
+
+int mdiobus_register(struct mii_bus *bus);
+void mdiobus_unregister(struct mii_bus *bus);
+void phy_sanitize_settings(struct phy_device *phydev);
+int phy_stop_interrupts(struct phy_device *phydev);
+
+static inline int phy_read_status(struct phy_device *phydev) {
+        return phydev->drv->read_status(phydev);
+}
+
+int genphy_config_advert(struct phy_device *phydev);
+int genphy_setup_forced(struct phy_device *phydev);
+int genphy_restart_aneg(struct phy_device *phydev);
+int genphy_config_aneg(struct phy_device *phydev);
+int genphy_update_link(struct phy_device *phydev);
+int genphy_read_status(struct phy_device *phydev);
+void phy_driver_unregister(struct phy_driver *drv);
+int phy_driver_register(struct phy_driver *new_driver);
+void phy_prepare_link(struct phy_device *phydev,
+                void (*adjust_link)(struct net_device *));
+void phy_start_machine(struct phy_device *phydev,
+                void (*handler)(struct net_device *));
+void phy_stop_machine(struct phy_device *phydev);
+int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
+int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
+int phy_mii_ioctl(struct phy_device *phydev,
+                struct mii_ioctl_data *mii_data, int cmd);
+int phy_start_interrupts(struct phy_device *phydev);
+void phy_print_status(struct phy_device *phydev);
+
+extern struct bus_type mdio_bus_type;
+#endif /* __PHY_H */
diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h
index 36725e7c02c6..1767073df26f 100644
--- a/include/linux/pipe_fs_i.h
+++ b/include/linux/pipe_fs_i.h
@@ -39,9 +39,6 @@ struct pipe_inode_info {
 
 #define PIPE_SEM(inode)         (&(inode).i_sem)
 #define PIPE_WAIT(inode)        (&(inode).i_pipe->wait)
-#define PIPE_BASE(inode)        ((inode).i_pipe->base)
-#define PIPE_START(inode)       ((inode).i_pipe->start)
-#define PIPE_LEN(inode)         ((inode).i_pipe->len)
 #define PIPE_READERS(inode)     ((inode).i_pipe->readers)
 #define PIPE_WRITERS(inode)     ((inode).i_pipe->writers)
 #define PIPE_WAITING_WRITERS(inode)     ((inode).i_pipe->waiting_writers)
diff --git a/include/linux/pkt_cls.h b/include/linux/pkt_cls.h
index d2aa214d6803..bd2c5a2bbbf5 100644
--- a/include/linux/pkt_cls.h
+++ b/include/linux/pkt_cls.h
@@ -276,6 +276,7 @@ struct tc_rsvp_pinfo
         __u8    protocol;
         __u8    tunnelid;
         __u8    tunnelhdr;
+        __u8    pad;
 };
 
 /* ROUTE filter */
@@ -408,6 +409,7 @@ enum
         TCF_EM_NBYTE,
         TCF_EM_U32,
         TCF_EM_META,
+        TCF_EM_TEXT,
         __TCF_EM_MAX
 };
 
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index 1d9da36eb9db..60ffcb9c5791 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -221,9 +221,11 @@ struct tc_gred_qopt
 /* gred setup */
 struct tc_gred_sopt
 {
-       __u32           DPs;
-       __u32           def_DP;
-       __u8            grio;
+       __u32            DPs;
+       __u32            def_DP;
+       __u8             grio;
+       __u8             pad1;
+       __u16            pad2;
 };
 
 /* HTB section */
@@ -351,6 +353,7 @@ struct tc_cbq_ovl
 #define TC_CBQ_OVL_DROP         3
 #define TC_CBQ_OVL_RCLASSIC     4
         unsigned char   priority2;
+        __u16           pad;
         __u32           penalty;
 };
 
diff --git a/include/linux/pktcdvd.h b/include/linux/pktcdvd.h
index 4e2d2a942ecb..4b32bce9a289 100644
--- a/include/linux/pktcdvd.h
+++ b/include/linux/pktcdvd.h
@@ -159,7 +159,7 @@ struct packet_iosched
         struct bio              *read_queue_tail;
         struct bio              *write_queue;
         struct bio              *write_queue_tail;
-        int                     high_prio_read; /* An important read request has been queued */
+        sector_t                last_write;     /* The sector where the last write ended */
         int                     successive_reads;
 };
 
diff --git a/include/linux/pm.h b/include/linux/pm.h
index ed2b76e75199..5cfb07648eca 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -103,7 +103,8 @@ extern int pm_active;
 /*
  * Register a device with power management
  */
-struct pm_dev __deprecated *pm_register(pm_dev_t type, unsigned long id, pm_callback callback);
+struct pm_dev __deprecated *
+pm_register(pm_dev_t type, unsigned long id, pm_callback callback);
 
 /*
  * Unregister a device with power management
@@ -175,7 +176,7 @@ struct pm_ops {
 };
 
 extern void pm_set_ops(struct pm_ops *);
-
+extern struct pm_ops *pm_ops;
 extern int pm_suspend(suspend_state_t state);
 
 
@@ -185,29 +186,36 @@ extern int pm_suspend(suspend_state_t state);
 
 struct device;
 
-typedef u32 __bitwise pm_message_t;
+typedef struct pm_message {
+        int event;
+} pm_message_t;
 
 /*
  * There are 4 important states driver can be in:
  * ON     -- driver is working
- * FREEZE -- stop operations and apply whatever policy is applicable to a suspended driver
- *           of that class, freeze queues for block like IDE does, drop packets for
- *           ethernet, etc... stop DMA engine too etc... so a consistent image can be
- *           saved; but do not power any hardware down.
- * SUSPEND - like FREEZE, but hardware is doing as much powersaving as possible. Roughly
- *           pci D3.
+ * FREEZE -- stop operations and apply whatever policy is applicable to a
+ *           suspended driver of that class, freeze queues for block like IDE
+ *           does, drop packets for ethernet, etc... stop DMA engine too etc...
+ *           so a consistent image can be saved; but do not power any hardware
+ *           down.
+ * SUSPEND - like FREEZE, but hardware is doing as much powersaving as
+ *           possible. Roughly pci D3.
  *
- * Unfortunately, current drivers only recognize numeric values 0 (ON) and 3 (SUSPEND).
- * We'll need to fix the drivers. So yes, putting 3 to all diferent defines is intentional,
- * and will go away as soon as drivers are fixed. Also note that typedef is neccessary,
- * we'll probably want to switch to
+ * Unfortunately, current drivers only recognize numeric values 0 (ON) and 3
+ * (SUSPEND).  We'll need to fix the drivers. So yes, putting 3 to all different
+ * defines is intentional, and will go away as soon as drivers are fixed.  Also
+ * note that typedef is neccessary, we'll probably want to switch to
  *   typedef struct pm_message_t { int event; int flags; } pm_message_t
  * or something similar soon.
  */
 
-#define PMSG_FREEZE     ((__force pm_message_t) 3)
-#define PMSG_SUSPEND    ((__force pm_message_t) 3)
-#define PMSG_ON         ((__force pm_message_t) 0)
+#define PM_EVENT_ON 0
+#define PM_EVENT_FREEZE 1
+#define PM_EVENT_SUSPEND 2
+
+#define PMSG_FREEZE     ((struct pm_message){ .event = PM_EVENT_FREEZE, })
+#define PMSG_SUSPEND    ((struct pm_message){ .event = PM_EVENT_SUSPEND, })
+#define PMSG_ON         ((struct pm_message){ .event = PM_EVENT_ON, })
 
 struct dev_pm_info {
         pm_message_t            power_state;
@@ -222,11 +230,18 @@ struct dev_pm_info {
 
 extern void device_pm_set_parent(struct device * dev, struct device * parent);
 
-extern int device_suspend(pm_message_t state);
 extern int device_power_down(pm_message_t state);
 extern void device_power_up(void);
 extern void device_resume(void);
 
+#ifdef CONFIG_PM
+extern int device_suspend(pm_message_t state);
+#else
+static inline int device_suspend(pm_message_t state)
+{
+        return 0;
+}
+#endif
 
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/pmu.h b/include/linux/pmu.h
index 6d73eada277e..373bd3b9b330 100644
--- a/include/linux/pmu.h
+++ b/include/linux/pmu.h
@@ -166,7 +166,7 @@ extern int pmu_i2c_simple_read(int bus, int addr,  u8* data, int len);
 extern int pmu_i2c_simple_write(int bus, int addr,  u8* data, int len);
 
 
-#ifdef CONFIG_PMAC_PBOOK
+#ifdef CONFIG_PM
 /*
  * Stuff for putting the powerbook to sleep and waking it again.
  *
@@ -208,6 +208,8 @@ struct pmu_sleep_notifier
 int pmu_register_sleep_notifier(struct pmu_sleep_notifier* notifier);
 int pmu_unregister_sleep_notifier(struct pmu_sleep_notifier* notifier);
 
+#endif /* CONFIG_PM */
+
 #define PMU_MAX_BATTERIES       2
 
 /* values for pmu_power_flags */
@@ -235,6 +237,4 @@ extern int pmu_battery_count;
 extern struct pmu_battery_info pmu_batteries[PMU_MAX_BATTERIES];
 extern unsigned int pmu_power_flags;
 
-#endif /* CONFIG_PMAC_PBOOK */
-
 #endif  /* __KERNEL__ */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index 5ec2bd0c2848..aadbac29103c 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -443,7 +443,7 @@ static inline void pnp_unregister_driver(struct pnp_driver *drv) { ; }
 #define pnp_info(format, arg...) printk(KERN_INFO "pnp: " format "\n" , ## arg)
 #define pnp_warn(format, arg...) printk(KERN_WARNING "pnp: " format "\n" , ## arg)
 
-#ifdef DEBUG
+#ifdef CONFIG_PNP_DEBUG
 #define pnp_dbg(format, arg...) printk(KERN_DEBUG "pnp: " format "\n" , ## arg)
 #else
 #define pnp_dbg(format, arg...) do {} while (0)
diff --git a/include/linux/posix_acl_xattr.h b/include/linux/posix_acl_xattr.h
index 5efd0a6dad94..6e53c34035cd 100644
--- a/include/linux/posix_acl_xattr.h
+++ b/include/linux/posix_acl_xattr.h
@@ -23,13 +23,13 @@
 #define ACL_UNDEFINED_ID        (-1)
 
 typedef struct {
-        __u16                   e_tag;
-        __u16                   e_perm;
-        __u32                   e_id;
+        __le16                  e_tag;
+        __le16                  e_perm;
+        __le32                  e_id;
 } posix_acl_xattr_entry;
 
 typedef struct {
-        __u32                   a_version;
+        __le32                  a_version;
         posix_acl_xattr_entry   a_entries[0];
 } posix_acl_xattr_header;
 
@@ -52,4 +52,7 @@ posix_acl_xattr_count(size_t size)
         return size / sizeof(posix_acl_xattr_entry);
 }
 
+struct posix_acl *posix_acl_from_xattr(const void *value, size_t size);
+int posix_acl_to_xattr(const struct posix_acl *acl, void *buffer, size_t size);
+
 #endif  /* _POSIX_ACL_XATTR_H */
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index 59e505261fd6..0563581e3a02 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -74,6 +74,13 @@ struct kcore_list {
         size_t size;
 };
 
+struct vmcore {
+        struct list_head list;
+        unsigned long long paddr;
+        unsigned long size;
+        loff_t offset;
+};
+
 #ifdef CONFIG_PROC_FS
 
 extern struct proc_dir_entry proc_root;
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index a373fc254df2..dc6f3647bfbc 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -20,6 +20,8 @@
 #define PTRACE_DETACH           0x11
 
 #define PTRACE_SYSCALL            24
+#define PTRACE_SYSEMU             31
+#define PTRACE_SYSEMU_SINGLESTEP  32
 
 /* 0x4200-0x4300 are reserved for architecture-independent additions.  */
 #define PTRACE_SETOPTIONS       0x4200
@@ -88,6 +90,7 @@ extern void __ptrace_link(struct task_struct *child,
                           struct task_struct *new_parent);
 extern void __ptrace_unlink(struct task_struct *child);
 extern void ptrace_untrace(struct task_struct *child);
+extern int ptrace_may_attach(struct task_struct *task);
 
 static inline void ptrace_link(struct task_struct *child,
                                struct task_struct *new_parent)
diff --git a/include/linux/qnx4_fs.h b/include/linux/qnx4_fs.h
index 22ba580b0ae8..fc610bb0f733 100644
--- a/include/linux/qnx4_fs.h
+++ b/include/linux/qnx4_fs.h
@@ -46,11 +46,11 @@ struct qnx4_inode_entry {
         char            di_fname[QNX4_SHORT_NAME_MAX];
         qnx4_off_t      di_size;
         qnx4_xtnt_t     di_first_xtnt;
-        __u32           di_xblk;
-        __s32           di_ftime;
-        __s32           di_mtime;
-        __s32           di_atime;
-        __s32           di_ctime;
+        __le32          di_xblk;
+        __le32          di_ftime;
+        __le32          di_mtime;
+        __le32          di_atime;
+        __le32          di_ctime;
         qnx4_nxtnt_t    di_num_xtnts;
         qnx4_mode_t     di_mode;
         qnx4_muid_t     di_uid;
@@ -63,18 +63,18 @@ struct qnx4_inode_entry {
 
 struct qnx4_link_info {
         char            dl_fname[QNX4_NAME_MAX];
-        __u32           dl_inode_blk;
+        __le32          dl_inode_blk;
         __u8            dl_inode_ndx;
         __u8            dl_spare[10];
         __u8            dl_status;
 };
 
 struct qnx4_xblk {
-        __u32           xblk_next_xblk;
-        __u32           xblk_prev_xblk;
+        __le32          xblk_next_xblk;
+        __le32          xblk_prev_xblk;
         __u8            xblk_num_xtnts;
         __u8            xblk_spare[3];
-        __s32           xblk_num_blocks;
+        __le32          xblk_num_blocks;
         qnx4_xtnt_t     xblk_xtnts[QNX4_MAX_XTNTS_PER_XBLK];
         char            xblk_signature[8];
         qnx4_xtnt_t     xblk_first_xtnt;
diff --git a/include/linux/qnxtypes.h b/include/linux/qnxtypes.h
index fb518e318c7c..a3eb1137857b 100644
--- a/include/linux/qnxtypes.h
+++ b/include/linux/qnxtypes.h
@@ -12,18 +12,18 @@
 #ifndef _QNX4TYPES_H
 #define _QNX4TYPES_H
 
-typedef __u16 qnx4_nxtnt_t;
+typedef __le16 qnx4_nxtnt_t;
 typedef __u8  qnx4_ftype_t;
 
 typedef struct {
-        __u32 xtnt_blk;
-        __u32 xtnt_size;
+        __le32 xtnt_blk;
+        __le32 xtnt_size;
 } qnx4_xtnt_t;
 
-typedef __u16 qnx4_mode_t;
-typedef __u16 qnx4_muid_t;
-typedef __u16 qnx4_mgid_t;
-typedef __u32 qnx4_off_t;
-typedef __u16 qnx4_nlink_t;
+typedef __le16 qnx4_mode_t;
+typedef __le16 qnx4_muid_t;
+typedef __le16 qnx4_mgid_t;
+typedef __le32 qnx4_off_t;
+typedef __le16 qnx4_nlink_t;
 
 #endif
diff --git a/include/linux/quota.h b/include/linux/quota.h
index ac5b90f4f256..700ead45084f 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -138,8 +138,11 @@ struct if_dqinfo {
 #include <linux/dqblk_v2.h>
 
 /* Maximal numbers of writes for quota operation (insert/delete/update)
- * (over all formats) - info block, 4 pointer blocks, data block */
-#define DQUOT_MAX_WRITES        6
+ * (over VFS all formats) */
+#define DQUOT_INIT_ALLOC max(V1_INIT_ALLOC, V2_INIT_ALLOC)
+#define DQUOT_INIT_REWRITE max(V1_INIT_REWRITE, V2_INIT_REWRITE)
+#define DQUOT_DEL_ALLOC max(V1_DEL_ALLOC, V2_DEL_ALLOC)
+#define DQUOT_DEL_REWRITE max(V1_DEL_REWRITE, V2_DEL_REWRITE)
 
 /*
  * Data for one user/group kept in memory
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index e57baa85e744..d211507ab246 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -39,7 +39,8 @@ extern int dquot_commit_info(struct super_block *sb, int type);
 extern int dquot_mark_dquot_dirty(struct dquot *dquot);
 
 extern int vfs_quota_on(struct super_block *sb, int type, int format_id, char *path);
-extern int vfs_quota_on_mount(int type, int format_id, struct dentry *dentry);
+extern int vfs_quota_on_mount(struct super_block *sb, char *qf_name,
+                int format_id, int type);
 extern int vfs_quota_off(struct super_block *sb, int type);
 #define vfs_quota_off_mount(sb, type) vfs_quota_off(sb, type)
 extern int vfs_quota_sync(struct super_block *sb, int type);
diff --git a/include/linux/raid/bitmap.h b/include/linux/raid/bitmap.h
new file mode 100644
index 000000000000..4bf1659f8aa8
--- /dev/null
+++ b/include/linux/raid/bitmap.h
@@ -0,0 +1,274 @@
+/*
+ * bitmap.h: Copyright (C) Peter T. Breuer (ptb@ot.uc3m.es) 2003
+ *
+ * additions: Copyright (C) 2003-2004, Paul Clements, SteelEye Technology, Inc.
+ */
+#ifndef BITMAP_H
+#define BITMAP_H 1
+
+#define BITMAP_MAJOR 3
+#define BITMAP_MINOR 38
+
+/*
+ * in-memory bitmap:
+ *
+ * Use 16 bit block counters to track pending writes to each "chunk".
+ * The 2 high order bits are special-purpose, the first is a flag indicating
+ * whether a resync is needed.  The second is a flag indicating whether a
+ * resync is active.
+ * This means that the counter is actually 14 bits:
+ *
+ * +--------+--------+------------------------------------------------+
+ * | resync | resync |               counter                          |
+ * | needed | active |                                                |
+ * |  (0-1) |  (0-1) |              (0-16383)                         |
+ * +--------+--------+------------------------------------------------+
+ *
+ * The "resync needed" bit is set when:
+ *    a '1' bit is read from storage at startup.
+ *    a write request fails on some drives
+ *    a resync is aborted on a chunk with 'resync active' set
+ * It is cleared (and resync-active set) when a resync starts across all drives
+ * of the chunk.
+ *
+ *
+ * The "resync active" bit is set when:
+ *    a resync is started on all drives, and resync_needed is set.
+ *       resync_needed will be cleared (as long as resync_active wasn't already set).
+ * It is cleared when a resync completes.
+ *
+ * The counter counts pending write requests, plus the on-disk bit.
+ * When the counter is '1' and the resync bits are clear, the on-disk
+ * bit can be cleared aswell, thus setting the counter to 0.
+ * When we set a bit, or in the counter (to start a write), if the fields is
+ * 0, we first set the disk bit and set the counter to 1.
+ *
+ * If the counter is 0, the on-disk bit is clear and the stipe is clean
+ * Anything that dirties the stipe pushes the counter to 2 (at least)
+ * and sets the on-disk bit (lazily).
+ * If a periodic sweep find the counter at 2, it is decremented to 1.
+ * If the sweep find the counter at 1, the on-disk bit is cleared and the
+ * counter goes to zero.
+ *
+ * Also, we'll hijack the "map" pointer itself and use it as two 16 bit block
+ * counters as a fallback when "page" memory cannot be allocated:
+ *
+ * Normal case (page memory allocated):
+ *
+ *     page pointer (32-bit)
+ *
+ *     [ ] ------+
+ *               |
+ *               +-------> [   ][   ]..[   ] (4096 byte page == 2048 counters)
+ *                          c1   c2    c2048
+ *
+ * Hijacked case (page memory allocation failed):
+ *
+ *     hijacked page pointer (32-bit)
+ *
+ *     [                  ][              ] (no page memory allocated)
+ *      counter #1 (16-bit) counter #2 (16-bit)
+ *
+ */
+
+#ifdef __KERNEL__
+
+#define PAGE_BITS (PAGE_SIZE << 3)
+#define PAGE_BIT_SHIFT (PAGE_SHIFT + 3)
+
+typedef __u16 bitmap_counter_t;
+#define COUNTER_BITS 16
+#define COUNTER_BIT_SHIFT 4
+#define COUNTER_BYTE_RATIO (COUNTER_BITS / 8)
+#define COUNTER_BYTE_SHIFT (COUNTER_BIT_SHIFT - 3)
+
+#define NEEDED_MASK ((bitmap_counter_t) (1 << (COUNTER_BITS - 1)))
+#define RESYNC_MASK ((bitmap_counter_t) (1 << (COUNTER_BITS - 2)))
+#define COUNTER_MAX ((bitmap_counter_t) RESYNC_MASK - 1)
+#define NEEDED(x) (((bitmap_counter_t) x) & NEEDED_MASK)
+#define RESYNC(x) (((bitmap_counter_t) x) & RESYNC_MASK)
+#define COUNTER(x) (((bitmap_counter_t) x) & COUNTER_MAX)
+
+/* how many counters per page? */
+#define PAGE_COUNTER_RATIO (PAGE_BITS / COUNTER_BITS)
+/* same, except a shift value for more efficient bitops */
+#define PAGE_COUNTER_SHIFT (PAGE_BIT_SHIFT - COUNTER_BIT_SHIFT)
+/* same, except a mask value for more efficient bitops */
+#define PAGE_COUNTER_MASK  (PAGE_COUNTER_RATIO - 1)
+
+#define BITMAP_BLOCK_SIZE 512
+#define BITMAP_BLOCK_SHIFT 9
+
+/* how many blocks per chunk? (this is variable) */
+#define CHUNK_BLOCK_RATIO(bitmap) ((bitmap)->chunksize >> BITMAP_BLOCK_SHIFT)
+#define CHUNK_BLOCK_SHIFT(bitmap) ((bitmap)->chunkshift - BITMAP_BLOCK_SHIFT)
+#define CHUNK_BLOCK_MASK(bitmap) (CHUNK_BLOCK_RATIO(bitmap) - 1)
+
+/* when hijacked, the counters and bits represent even larger "chunks" */
+/* there will be 1024 chunks represented by each counter in the page pointers */
+#define PAGEPTR_BLOCK_RATIO(bitmap) \
+                        (CHUNK_BLOCK_RATIO(bitmap) << PAGE_COUNTER_SHIFT >> 1)
+#define PAGEPTR_BLOCK_SHIFT(bitmap) \
+                        (CHUNK_BLOCK_SHIFT(bitmap) + PAGE_COUNTER_SHIFT - 1)
+#define PAGEPTR_BLOCK_MASK(bitmap) (PAGEPTR_BLOCK_RATIO(bitmap) - 1)
+
+/*
+ * on-disk bitmap:
+ *
+ * Use one bit per "chunk" (block set). We do the disk I/O on the bitmap
+ * file a page at a time. There's a superblock at the start of the file.
+ */
+
+/* map chunks (bits) to file pages - offset by the size of the superblock */
+#define CHUNK_BIT_OFFSET(chunk) ((chunk) + (sizeof(bitmap_super_t) << 3))
+
+#endif
+
+/*
+ * bitmap structures:
+ */
+
+#define BITMAP_MAGIC 0x6d746962
+
+/* use these for bitmap->flags and bitmap->sb->state bit-fields */
+enum bitmap_state {
+        BITMAP_ACTIVE = 0x001, /* the bitmap is in use */
+        BITMAP_STALE  = 0x002  /* the bitmap file is out of date or had -EIO */
+};
+
+/* the superblock at the front of the bitmap file -- little endian */
+typedef struct bitmap_super_s {
+        __u32 magic;        /*  0  BITMAP_MAGIC */
+        __u32 version;      /*  4  the bitmap major for now, could change... */
+        __u8  uuid[16];     /*  8  128 bit uuid - must match md device uuid */
+        __u64 events;       /* 24  event counter for the bitmap (1)*/
+        __u64 events_cleared;/*32  event counter when last bit cleared (2) */
+        __u64 sync_size;    /* 40  the size of the md device's sync range(3) */
+        __u32 state;        /* 48  bitmap state information */
+        __u32 chunksize;    /* 52  the bitmap chunk size in bytes */
+        __u32 daemon_sleep; /* 56  seconds between disk flushes */
+
+        __u8  pad[256 - 60]; /* set to zero */
+} bitmap_super_t;
+
+/* notes:
+ * (1) This event counter is updated before the eventcounter in the md superblock
+ *    When a bitmap is loaded, it is only accepted if this event counter is equal
+ *    to, or one greater than, the event counter in the superblock.
+ * (2) This event counter is updated when the other one is *if*and*only*if* the
+ *    array is not degraded.  As bits are not cleared when the array is degraded,
+ *    this represents the last time that any bits were cleared.
+ *    If a device is being added that has an event count with this value or
+ *    higher, it is accepted as conforming to the bitmap.
+ * (3)This is the number of sectors represented by the bitmap, and is the range that
+ *    resync happens across.  For raid1 and raid5/6 it is the size of individual
+ *    devices.  For raid10 it is the size of the array.
+ */
+
+#ifdef __KERNEL__
+
+/* the in-memory bitmap is represented by bitmap_pages */
+struct bitmap_page {
+        /*
+         * map points to the actual memory page
+         */
+        char *map;
+        /*
+         * in emergencies (when map cannot be alloced), hijack the map
+         * pointer and use it as two counters itself
+         */
+        unsigned int hijacked:1;
+        /*
+         * count of dirty bits on the page
+         */
+        unsigned int  count:31;
+};
+
+/* keep track of bitmap file pages that have pending writes on them */
+struct page_list {
+        struct list_head list;
+        struct page *page;
+};
+
+/* the main bitmap structure - one per mddev */
+struct bitmap {
+        struct bitmap_page *bp;
+        unsigned long pages; /* total number of pages in the bitmap */
+        unsigned long missing_pages; /* number of pages not yet allocated */
+
+        mddev_t *mddev; /* the md device that the bitmap is for */
+
+        int counter_bits; /* how many bits per block counter */
+
+        /* bitmap chunksize -- how much data does each bit represent? */
+        unsigned long chunksize;
+        unsigned long chunkshift; /* chunksize = 2^chunkshift (for bitops) */
+        unsigned long chunks; /* total number of data chunks for the array */
+
+        /* We hold a count on the chunk currently being synced, and drop
+         * it when the last block is started.  If the resync is aborted
+         * midway, we need to be able to drop that count, so we remember
+         * the counted chunk..
+         */
+        unsigned long syncchunk;
+
+        __u64   events_cleared;
+
+        /* bitmap spinlock */
+        spinlock_t lock;
+
+        long offset; /* offset from superblock if file is NULL */
+        struct file *file; /* backing disk file */
+        struct page *sb_page; /* cached copy of the bitmap file superblock */
+        struct page **filemap; /* list of cache pages for the file */
+        unsigned long *filemap_attr; /* attributes associated w/ filemap pages */
+        unsigned long file_pages; /* number of pages in the file */
+
+        unsigned long flags;
+
+        /*
+         * the bitmap daemon - periodically wakes up and sweeps the bitmap
+         * file, cleaning up bits and flushing out pages to disk as necessary
+         */
+        unsigned long daemon_lastrun; /* jiffies of last run */
+        unsigned long daemon_sleep; /* how many seconds between updates? */
+
+        /*
+         * bitmap_writeback_daemon waits for file-pages that have been written,
+         * as there is no way to get a call-back when a page write completes.
+         */
+        mdk_thread_t *writeback_daemon;
+        spinlock_t write_lock;
+        wait_queue_head_t write_wait;
+        struct list_head complete_pages;
+        mempool_t *write_pool;
+};
+
+/* the bitmap API */
+
+/* these are used only by md/bitmap */
+int  bitmap_create(mddev_t *mddev);
+void bitmap_flush(mddev_t *mddev);
+void bitmap_destroy(mddev_t *mddev);
+int  bitmap_active(struct bitmap *bitmap);
+
+char *file_path(struct file *file, char *buf, int count);
+void bitmap_print_sb(struct bitmap *bitmap);
+int bitmap_update_sb(struct bitmap *bitmap);
+
+int  bitmap_setallbits(struct bitmap *bitmap);
+void bitmap_write_all(struct bitmap *bitmap);
+
+/* these are exported */
+int bitmap_startwrite(struct bitmap *bitmap, sector_t offset, unsigned long sectors);
+void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long sectors,
+                     int success);
+int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int degraded);
+void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted);
+void bitmap_close_sync(struct bitmap *bitmap);
+
+int bitmap_unplug(struct bitmap *bitmap);
+int bitmap_daemon_work(struct bitmap *bitmap);
+#endif
+
+#endif
diff --git a/include/linux/raid/md.h b/include/linux/raid/md.h
index a6a67d102bfa..ffa316ce4dc8 100644
--- a/include/linux/raid/md.h
+++ b/include/linux/raid/md.h
@@ -60,7 +60,14 @@
  */
 #define MD_MAJOR_VERSION                0
 #define MD_MINOR_VERSION                90
-#define MD_PATCHLEVEL_VERSION           1
+/*
+ * MD_PATCHLEVEL_VERSION indicates kernel functionality.
+ * >=1 means different superblock formats are selectable using SET_ARRAY_INFO
+ *     and major_version/minor_version accordingly
+ * >=2 means that Internal bitmaps are supported by setting MD_SB_BITMAP_PRESENT
+ *     in the super status byte
+ */
+#define MD_PATCHLEVEL_VERSION           2
 
 extern int register_md_personality (int p_num, mdk_personality_t *p);
 extern int unregister_md_personality (int p_num);
@@ -69,7 +76,7 @@ extern mdk_thread_t * md_register_thread (void (*run) (mddev_t *mddev),
 extern void md_unregister_thread (mdk_thread_t *thread);
 extern void md_wakeup_thread(mdk_thread_t *thread);
 extern void md_check_recovery(mddev_t *mddev);
-extern void md_write_start(mddev_t *mddev);
+extern void md_write_start(mddev_t *mddev, struct bio *bi);
 extern void md_write_end(mddev_t *mddev);
 extern void md_handle_safemode(mddev_t *mddev);
 extern void md_done_sync(mddev_t *mddev, int blocks, int ok);
@@ -78,6 +85,12 @@ extern void md_unplug_mddev(mddev_t *mddev);
 
 extern void md_print_devices (void);
 
+extern void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
+                           sector_t sector, int size, struct page *page);
+extern int sync_page_io(struct block_device *bdev, sector_t sector, int size,
+                        struct page *page, int rw);
+
+
 #define MD_BUG(x...) { printk("md: bug in file %s, line %d\n", __FILE__, __LINE__); md_print_devices(); }
 
 #endif 
diff --git a/include/linux/raid/md_k.h b/include/linux/raid/md_k.h
index c9a0d4013be7..8c14ba565a45 100644
--- a/include/linux/raid/md_k.h
+++ b/include/linux/raid/md_k.h
@@ -15,6 +15,9 @@
 #ifndef _MD_K_H
 #define _MD_K_H
 
+/* and dm-bio-list.h is not under include/linux because.... ??? */
+#include "../../../drivers/md/dm-bio-list.h"
+
 #define MD_RESERVED       0UL
 #define LINEAR            1UL
 #define RAID0             2UL
@@ -180,6 +183,10 @@ struct mdk_rdev_s
 
         int desc_nr;                    /* descriptor index in the superblock */
         int raid_disk;                  /* role of device in array */
+        int saved_raid_disk;            /* role that device used to have in the
+                                         * array and could again if we did a partial
+                                         * resync from the bitmap
+                                         */
 
         atomic_t        nr_pending;     /* number of pending requests.
                                          * only maintained for arrays that
@@ -252,6 +259,11 @@ struct mddev_s
         atomic_t                        recovery_active; /* blocks scheduled, but not written */
         wait_queue_head_t               recovery_wait;
         sector_t                        recovery_cp;
+
+        spinlock_t                      write_lock;
+        wait_queue_head_t               sb_wait;        /* for waiting on superblock updates */
+        atomic_t                        pending_writes; /* number of active superblock writes */
+
         unsigned int                    safemode;       /* if set, update "clean" superblock
                                                          * when no writes pending.
                                                          */ 
@@ -260,6 +272,13 @@ struct mddev_s
         atomic_t                        writes_pending; 
         request_queue_t                 *queue; /* for plugging ... */
 
+        struct bitmap                   *bitmap; /* the bitmap for the device */
+        struct file                     *bitmap_file; /* the bitmap file */
+        long                            bitmap_offset; /* offset from superblock of
+                                                        * start of bitmap. May be
+                                                        * negative, but not '0'
+                                                        */
+
         struct list_head                all_mddevs;
 };
 
@@ -291,7 +310,7 @@ struct mdk_personality_s
         int (*hot_add_disk) (mddev_t *mddev, mdk_rdev_t *rdev);
         int (*hot_remove_disk) (mddev_t *mddev, int number);
         int (*spare_active) (mddev_t *mddev);
-        int (*sync_request)(mddev_t *mddev, sector_t sector_nr, int go_faster);
+        sector_t (*sync_request)(mddev_t *mddev, sector_t sector_nr, int *skipped, int go_faster);
         int (*resize) (mddev_t *mddev, sector_t sectors);
         int (*reshape) (mddev_t *mddev, int raid_disks);
         int (*reconfig) (mddev_t *mddev, int layout, int chunk_size);
@@ -334,6 +353,7 @@ typedef struct mdk_thread_s {
         unsigned long           flags;
         struct completion       *event;
         struct task_struct      *tsk;
+        unsigned long           timeout;
         const char              *name;
 } mdk_thread_t;
 
diff --git a/include/linux/raid/md_p.h b/include/linux/raid/md_p.h
index 8ba95d67329f..dc65cd435494 100644
--- a/include/linux/raid/md_p.h
+++ b/include/linux/raid/md_p.h
@@ -96,6 +96,7 @@ typedef struct mdp_device_descriptor_s {
 #define MD_SB_CLEAN             0
 #define MD_SB_ERRORS            1
 
+#define MD_SB_BITMAP_PRESENT    8 /* bitmap may be present nearby */
 typedef struct mdp_superblock_s {
         /*
          * Constant generic information
@@ -184,7 +185,7 @@ struct mdp_superblock_1 {
         /* constant array information - 128 bytes */
         __u32   magic;          /* MD_SB_MAGIC: 0xa92b4efc - little endian */
         __u32   major_version;  /* 1 */
-        __u32   feature_map;    /* 0 for now */
+        __u32   feature_map;    /* bit 0 set if 'bitmap_offset' is meaningful */
         __u32   pad0;           /* always set to 0 when writing */
 
         __u8    set_uuid[16];   /* user-space generated. */
@@ -197,7 +198,11 @@ struct mdp_superblock_1 {
 
         __u32   chunksize;      /* in 512byte sectors */
         __u32   raid_disks;
-        __u8    pad1[128-96];   /* set to 0 when written */
+        __u32   bitmap_offset;  /* sectors after start of superblock that bitmap starts
+                                 * NOTE: signed, so bitmap can be before superblock
+                                 * only meaningful of feature_map[0] is set.
+                                 */
+        __u8    pad1[128-100];  /* set to 0 when written */
 
         /* constant this-device information - 64 bytes */
         __u64   data_offset;    /* sector start of data, often 0 */
diff --git a/include/linux/raid/md_u.h b/include/linux/raid/md_u.h
index a2df5c2a42af..81da20ccec4d 100644
--- a/include/linux/raid/md_u.h
+++ b/include/linux/raid/md_u.h
@@ -23,6 +23,7 @@
 #define GET_DISK_INFO           _IOR (MD_MAJOR, 0x12, mdu_disk_info_t)
 #define PRINT_RAID_DEBUG        _IO (MD_MAJOR, 0x13)
 #define RAID_AUTORUN            _IO (MD_MAJOR, 0x14)
+#define GET_BITMAP_FILE         _IOR (MD_MAJOR, 0x15, mdu_bitmap_file_t)
 
 /* configuration */
 #define CLEAR_ARRAY             _IO (MD_MAJOR, 0x20)
@@ -36,6 +37,7 @@
 #define HOT_ADD_DISK            _IO (MD_MAJOR, 0x28)
 #define SET_DISK_FAULTY         _IO (MD_MAJOR, 0x29)
 #define HOT_GENERATE_ERROR      _IO (MD_MAJOR, 0x2a)
+#define SET_BITMAP_FILE         _IOW (MD_MAJOR, 0x2b, int)
 
 /* usage */
 #define RUN_ARRAY               _IOW (MD_MAJOR, 0x30, mdu_param_t)
@@ -106,6 +108,11 @@ typedef struct mdu_start_info_s {
 
 } mdu_start_info_t;
 
+typedef struct mdu_bitmap_file_s
+{
+        char pathname[4096];
+} mdu_bitmap_file_t;
+
 typedef struct mdu_param_s
 {
         int                     personality;    /* 1,2,3,4 */
diff --git a/include/linux/raid/raid1.h b/include/linux/raid/raid1.h
index abbfdd9afe1e..9d93cf12e890 100644
--- a/include/linux/raid/raid1.h
+++ b/include/linux/raid/raid1.h
@@ -36,12 +36,21 @@ struct r1_private_data_s {
         spinlock_t              device_lock;
 
         struct list_head        retry_list;
+        /* queue pending writes and submit them on unplug */
+        struct bio_list         pending_bio_list;
+        /* queue of writes that have been unplugged */
+        struct bio_list         flushing_bio_list;
+
         /* for use when syncing mirrors: */
 
         spinlock_t              resync_lock;
-        int nr_pending;
-        int barrier;
+        int                     nr_pending;
+        int                     barrier;
         sector_t                next_resync;
+        int                     fullsync;  /* set to 1 if a full sync is needed,
+                                            * (fresh device added).
+                                            * Cleared when a sync completes.
+                                            */
 
         wait_queue_head_t       wait_idle;
         wait_queue_head_t       wait_resume;
@@ -85,14 +94,17 @@ struct r1bio_s {
         int                     read_disk;
 
         struct list_head        retry_list;
+        struct bitmap_update    *bitmap_update;
         /*
          * if the IO is in WRITE direction, then multiple bios are used.
          * We choose the number when they are allocated.
          */
         struct bio              *bios[0];
+        /* DO NOT PUT ANY NEW FIELDS HERE - bios array is contiguously alloced*/
 };
 
 /* bits for r1bio.state */
 #define R1BIO_Uptodate  0
 #define R1BIO_IsSync    1
+#define R1BIO_Degraded  2
 #endif
diff --git a/include/linux/raid_class.h b/include/linux/raid_class.h
new file mode 100644
index 000000000000..a71123c28272
--- /dev/null
+++ b/include/linux/raid_class.h
@@ -0,0 +1,59 @@
+/*
+ */
+#include <linux/transport_class.h>
+
+struct raid_template {
+        struct transport_container raid_attrs;
+};
+
+struct raid_function_template {
+        void *cookie;
+        int (*is_raid)(struct device *);
+        void (*get_resync)(struct device *);
+        void (*get_state)(struct device *);
+};
+
+enum raid_state {
+        RAID_ACTIVE = 1,
+        RAID_DEGRADED,
+        RAID_RESYNCING,
+        RAID_OFFLINE,
+};
+
+struct raid_data {
+        struct list_head component_list;
+        int component_count;
+        int level;
+        enum raid_state state;
+        int resync;
+};
+
+#define DEFINE_RAID_ATTRIBUTE(type, attr)                                     \
+static inline void                                                            \
+raid_set_##attr(struct raid_template *r, struct device *dev, type value) {    \
+        struct class_device *cdev =                                           \
+                attribute_container_find_class_device(&r->raid_attrs.ac, dev);\
+        struct raid_data *rd;                                                 \
+        BUG_ON(!cdev);                                                        \
+        rd = class_get_devdata(cdev);                                         \
+        rd->attr = value;                                                     \
+}                                                                             \
+static inline type                                                            \
+raid_get_##attr(struct raid_template *r, struct device *dev) {                \
+        struct class_device *cdev =                                           \
+                attribute_container_find_class_device(&r->raid_attrs.ac, dev);\
+        struct raid_data *rd;                                                 \
+        BUG_ON(!cdev);                                                        \
+        rd = class_get_devdata(cdev);                                         \
+        return rd->attr;                                                      \
+}
+
+DEFINE_RAID_ATTRIBUTE(int, level)
+DEFINE_RAID_ATTRIBUTE(int, resync)
+DEFINE_RAID_ATTRIBUTE(enum raid_state, state)
+        
+struct raid_template *raid_class_attach(struct raid_function_template *);
+void raid_class_release(struct raid_template *);
+
+void raid_component_add(struct raid_template *, struct device *,
+                        struct device *);
diff --git a/include/linux/random.h b/include/linux/random.h
index cc6703449916..7b2adb3322d5 100644
--- a/include/linux/random.h
+++ b/include/linux/random.h
@@ -59,6 +59,8 @@ extern __u32 secure_tcp_sequence_number(__u32 saddr, __u32 daddr,
                                         __u16 sport, __u16 dport);
 extern __u32 secure_tcpv6_sequence_number(__u32 *saddr, __u32 *daddr,
                                           __u16 sport, __u16 dport);
+extern u64 secure_dccp_sequence_number(__u32 saddr, __u32 daddr,
+                                       __u16 sport, __u16 dport);
 
 #ifndef MODULE
 extern struct file_operations random_fops, urandom_fops;
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index d60fafc8bdc5..3b3266ff1a95 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -51,6 +51,26 @@ extern void machine_restart(char *cmd);
 extern void machine_halt(void);
 extern void machine_power_off(void);
 
+extern void machine_shutdown(void);
+struct pt_regs;
+extern void machine_crash_shutdown(struct pt_regs *);
+
+/* 
+ * Architecture independent implemenations of sys_reboot commands.
+ */
+
+extern void kernel_restart(char *cmd);
+extern void kernel_halt(void);
+extern void kernel_power_off(void);
+extern void kernel_kexec(void);
+
+/*
+ * Emergency restart, callable from an interrupt handler.
+ */
+
+extern void emergency_restart(void);
+#include <asm/emergency-restart.h>
+
 #endif
 
 #endif /* _LINUX_REBOOT_H */
diff --git a/include/linux/reiserfs_acl.h b/include/linux/reiserfs_acl.h
index 2aef9c3f5ce8..0a3605099c44 100644
--- a/include/linux/reiserfs_acl.h
+++ b/include/linux/reiserfs_acl.h
@@ -1,33 +1,32 @@
 #include <linux/init.h>
 #include <linux/posix_acl.h>
-#include <linux/xattr_acl.h>
 
 #define REISERFS_ACL_VERSION    0x0001
 
 typedef struct {
-        __le16          e_tag;
-        __le16          e_perm;
-        __le32          e_id;
+        __le16 e_tag;
+        __le16 e_perm;
+        __le32 e_id;
 } reiserfs_acl_entry;
 
 typedef struct {
-        __le16          e_tag;
-        __le16          e_perm;
+        __le16 e_tag;
+        __le16 e_perm;
 } reiserfs_acl_entry_short;
 
 typedef struct {
-        __le32          a_version;
+        __le32 a_version;
 } reiserfs_acl_header;
 
 static inline size_t reiserfs_acl_size(int count)
 {
         if (count <= 4) {
                 return sizeof(reiserfs_acl_header) +
-                       count * sizeof(reiserfs_acl_entry_short);
+                    count * sizeof(reiserfs_acl_entry_short);
         } else {
                 return sizeof(reiserfs_acl_header) +
-                       4 * sizeof(reiserfs_acl_entry_short) +
-                       (count - 4) * sizeof(reiserfs_acl_entry);
+                    4 * sizeof(reiserfs_acl_entry_short) +
+                    (count - 4) * sizeof(reiserfs_acl_entry);
         }
 }
 
@@ -47,14 +46,14 @@ static inline int reiserfs_acl_count(size_t size)
         }
 }
 
-
 #ifdef CONFIG_REISERFS_FS_POSIX_ACL
-struct posix_acl * reiserfs_get_acl(struct inode *inode, int type);
-int reiserfs_acl_chmod (struct inode *inode);
-int reiserfs_inherit_default_acl (struct inode *dir, struct dentry *dentry, struct inode *inode);
-int reiserfs_cache_default_acl (struct inode *dir);
-extern int reiserfs_xattr_posix_acl_init (void) __init;
-extern int reiserfs_xattr_posix_acl_exit (void);
+struct posix_acl *reiserfs_get_acl(struct inode *inode, int type);
+int reiserfs_acl_chmod(struct inode *inode);
+int reiserfs_inherit_default_acl(struct inode *dir, struct dentry *dentry,
+                                 struct inode *inode);
+int reiserfs_cache_default_acl(struct inode *dir);
+extern int reiserfs_xattr_posix_acl_init(void) __init;
+extern int reiserfs_xattr_posix_acl_exit(void);
 extern struct reiserfs_xattr_handler posix_acl_default_handler;
 extern struct reiserfs_xattr_handler posix_acl_access_handler;
 #else
@@ -62,28 +61,26 @@ extern struct reiserfs_xattr_handler posix_acl_access_handler;
 #define reiserfs_get_acl NULL
 #define reiserfs_cache_default_acl(inode) 0
 
-static inline int
-reiserfs_xattr_posix_acl_init (void)
+static inline int reiserfs_xattr_posix_acl_init(void)
 {
-    return 0;
+        return 0;
 }
 
-static inline int
-reiserfs_xattr_posix_acl_exit (void)
+static inline int reiserfs_xattr_posix_acl_exit(void)
 {
-    return 0;
+        return 0;
 }
 
-static inline int
-reiserfs_acl_chmod (struct inode *inode)
+static inline int reiserfs_acl_chmod(struct inode *inode)
 {
-    return 0;
+        return 0;
 }
 
 static inline int
-reiserfs_inherit_default_acl (const struct inode *dir, struct dentry *dentry, struct inode *inode)
+reiserfs_inherit_default_acl(const struct inode *dir, struct dentry *dentry,
+                             struct inode *inode)
 {
-    return 0;
+        return 0;
 }
 
 #endif
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h
index 32148625fc2f..17e458e17e2b 100644
--- a/include/linux/reiserfs_fs.h
+++ b/include/linux/reiserfs_fs.h
@@ -3,11 +3,10 @@
  */
 
                                 /* this file has an amazingly stupid
-                                   name, yura please fix it to be
-                                   reiserfs.h, and merge all the rest
-                                   of our .h files that are in this
-                                   directory into it.  */
-
+                                   name, yura please fix it to be
+                                   reiserfs.h, and merge all the rest
+                                   of our .h files that are in this
+                                   directory into it.  */
 
 #ifndef _LINUX_REISER_FS_H
 #define _LINUX_REISER_FS_H
@@ -74,9 +73,9 @@
 /* debug levels.  Right now, CONFIG_REISERFS_CHECK means print all debug
 ** messages.
 */
-#define REISERFS_DEBUG_CODE 5 /* extra messages to help find/debug errors */ 
+#define REISERFS_DEBUG_CODE 5   /* extra messages to help find/debug errors */
 
-void reiserfs_warning (struct super_block *s, const char * fmt, ...);
+void reiserfs_warning(struct super_block *s, const char *fmt, ...);
 /* assertions handling */
 
 /** always check a condition and panic if it's false. */
@@ -105,82 +104,78 @@ if( !( cond ) ) 								\
  * Structure of super block on disk, a version of which in RAM is often accessed as REISERFS_SB(s)->s_rs
  * the version in RAM is part of a larger structure containing fields never written to disk.
  */
-#define UNSET_HASH 0 // read_super will guess about, what hash names
-                     // in directories were sorted with
+#define UNSET_HASH 0            // read_super will guess about, what hash names
+                     // in directories were sorted with
 #define TEA_HASH  1
 #define YURA_HASH 2
 #define R5_HASH   3
 #define DEFAULT_HASH R5_HASH
 
-
 struct journal_params {
-    __le32 jp_journal_1st_block;              /* where does journal start from on its
-                                       * device */
-    __le32 jp_journal_dev;            /* journal device st_rdev */
-    __le32 jp_journal_size;           /* size of the journal */
-    __le32 jp_journal_trans_max;              /* max number of blocks in a transaction. */
-    __le32 jp_journal_magic;          /* random value made on fs creation (this
-                                       * was sb_journal_block_count) */
-    __le32 jp_journal_max_batch;              /* max number of blocks to batch into a
-                                       * trans */
-    __le32 jp_journal_max_commit_age;  /* in seconds, how old can an async
-                                       * commit be */
-    __le32 jp_journal_max_trans_age;   /* in seconds, how old can a transaction
-                                       * be */
+        __le32 jp_journal_1st_block;    /* where does journal start from on its
+                                         * device */
+        __le32 jp_journal_dev;  /* journal device st_rdev */
+        __le32 jp_journal_size; /* size of the journal */
+        __le32 jp_journal_trans_max;    /* max number of blocks in a transaction. */
+        __le32 jp_journal_magic;        /* random value made on fs creation (this
+                                         * was sb_journal_block_count) */
+        __le32 jp_journal_max_batch;    /* max number of blocks to batch into a
+                                         * trans */
+        __le32 jp_journal_max_commit_age;       /* in seconds, how old can an async
+                                                 * commit be */
+        __le32 jp_journal_max_trans_age;        /* in seconds, how old can a transaction
+                                                 * be */
 };
 
 /* this is the super from 3.5.X, where X >= 10 */
-struct reiserfs_super_block_v1
-{
-    __le32 s_block_count;          /* blocks count         */
-    __le32 s_free_blocks;           /* free blocks count    */
-    __le32 s_root_block;            /* root block number    */
-    struct journal_params s_journal;
-    __le16 s_blocksize;             /* block size */
-    __le16 s_oid_maxsize;          /* max size of object id array, see
-                                    * get_objectid() commentary  */
-    __le16 s_oid_cursize;          /* current size of object id array */
-    __le16 s_umount_state;          /* this is set to 1 when filesystem was
-                                    * umounted, to 2 - when not */    
-    char s_magic[10];              /* reiserfs magic string indicates that
-                                    * file system is reiserfs:
-                                    * "ReIsErFs" or "ReIsEr2Fs" or "ReIsEr3Fs" */
-    __le16 s_fs_state;             /* it is set to used by fsck to mark which
-                                    * phase of rebuilding is done */
-    __le32 s_hash_function_code;    /* indicate, what hash function is being use
-                                    * to sort names in a directory*/
-    __le16 s_tree_height;           /* height of disk tree */
-    __le16 s_bmap_nr;               /* amount of bitmap blocks needed to address
-                                    * each block of file system */
-    __le16 s_version;               /* this field is only reliable on filesystem
-                                    * with non-standard journal */
-    __le16 s_reserved_for_journal;  /* size in blocks of journal area on main
-                                    * device, we need to keep after
-                                    * making fs with non-standard journal */    
+struct reiserfs_super_block_v1 {
+        __le32 s_block_count;   /* blocks count         */
+        __le32 s_free_blocks;   /* free blocks count    */
+        __le32 s_root_block;    /* root block number    */
+        struct journal_params s_journal;
+        __le16 s_blocksize;     /* block size */
+        __le16 s_oid_maxsize;   /* max size of object id array, see
+                                 * get_objectid() commentary  */
+        __le16 s_oid_cursize;   /* current size of object id array */
+        __le16 s_umount_state;  /* this is set to 1 when filesystem was
+                                 * umounted, to 2 - when not */
+        char s_magic[10];       /* reiserfs magic string indicates that
+                                 * file system is reiserfs:
+                                 * "ReIsErFs" or "ReIsEr2Fs" or "ReIsEr3Fs" */
+        __le16 s_fs_state;      /* it is set to used by fsck to mark which
+                                 * phase of rebuilding is done */
+        __le32 s_hash_function_code;    /* indicate, what hash function is being use
+                                         * to sort names in a directory*/
+        __le16 s_tree_height;   /* height of disk tree */
+        __le16 s_bmap_nr;       /* amount of bitmap blocks needed to address
+                                 * each block of file system */
+        __le16 s_version;       /* this field is only reliable on filesystem
+                                 * with non-standard journal */
+        __le16 s_reserved_for_journal;  /* size in blocks of journal area on main
+                                         * device, we need to keep after
+                                         * making fs with non-standard journal */
 } __attribute__ ((__packed__));
 
 #define SB_SIZE_V1 (sizeof(struct reiserfs_super_block_v1))
 
 /* this is the on disk super block */
-struct reiserfs_super_block
-{
-    struct reiserfs_super_block_v1 s_v1;
-    __le32 s_inode_generation;
-    __le32 s_flags;                  /* Right now used only by inode-attributes, if enabled */
-    unsigned char s_uuid[16];       /* filesystem unique identifier */
-    unsigned char s_label[16];      /* filesystem volume label */
-    char s_unused[88] ;             /* zero filled by mkreiserfs and
-                                     * reiserfs_convert_objectid_map_v1()
-                                     * so any additions must be updated
-                                     * there as well. */
-}  __attribute__ ((__packed__));
+struct reiserfs_super_block {
+        struct reiserfs_super_block_v1 s_v1;
+        __le32 s_inode_generation;
+        __le32 s_flags;         /* Right now used only by inode-attributes, if enabled */
+        unsigned char s_uuid[16];       /* filesystem unique identifier */
+        unsigned char s_label[16];      /* filesystem volume label */
+        char s_unused[88];      /* zero filled by mkreiserfs and
+                                 * reiserfs_convert_objectid_map_v1()
+                                 * so any additions must be updated
+                                 * there as well. */
+} __attribute__ ((__packed__));
 
 #define SB_SIZE (sizeof(struct reiserfs_super_block))
 
 #define REISERFS_VERSION_1 0
 #define REISERFS_VERSION_2 2
 
-
 // on-disk super block fields converted to cpu form
 #define SB_DISK_SUPER_BLOCK(s) (REISERFS_SB(s)->s_rs)
 #define SB_V1_DISK_SUPER_BLOCK(s) (&(SB_DISK_SUPER_BLOCK(s)->s_v1))
@@ -210,13 +205,12 @@ struct reiserfs_super_block
 #define PUT_SB_TREE_HEIGHT(s, val) \
    do { SB_V1_DISK_SUPER_BLOCK(s)->s_tree_height = cpu_to_le16(val); } while (0)
 #define PUT_SB_REISERFS_STATE(s, val) \
-   do { SB_V1_DISK_SUPER_BLOCK(s)->s_umount_state = cpu_to_le16(val); } while (0) 
+   do { SB_V1_DISK_SUPER_BLOCK(s)->s_umount_state = cpu_to_le16(val); } while (0)
 #define PUT_SB_VERSION(s, val) \
    do { SB_V1_DISK_SUPER_BLOCK(s)->s_version = cpu_to_le16(val); } while (0)
 #define PUT_SB_BMAP_NR(s, val) \
    do { SB_V1_DISK_SUPER_BLOCK(s)->s_bmap_nr = cpu_to_le16 (val); } while (0)
 
-
 #define SB_ONDISK_JP(s) (&SB_V1_DISK_SUPER_BLOCK(s)->s_journal)
 #define SB_ONDISK_JOURNAL_SIZE(s) \
          le32_to_cpu ((SB_ONDISK_JP(s)->jp_journal_size))
@@ -231,21 +225,19 @@ struct reiserfs_super_block
          block >= SB_JOURNAL_1st_RESERVED_BLOCK(s) \
          && block < SB_JOURNAL_1st_RESERVED_BLOCK(s) +  \
          ((!is_reiserfs_jr(SB_DISK_SUPER_BLOCK(s)) ? \
-         SB_ONDISK_JOURNAL_SIZE(s) + 1 : SB_ONDISK_RESERVED_FOR_JOURNAL(s))) 
-
-
+         SB_ONDISK_JOURNAL_SIZE(s) + 1 : SB_ONDISK_RESERVED_FOR_JOURNAL(s)))
 
                                 /* used by gcc */
 #define REISERFS_SUPER_MAGIC 0x52654973
                                 /* used by file system utilities that
-                                   look at the superblock, etc. */
+                                   look at the superblock, etc. */
 #define REISERFS_SUPER_MAGIC_STRING "ReIsErFs"
 #define REISER2FS_SUPER_MAGIC_STRING "ReIsEr2Fs"
 #define REISER2FS_JR_SUPER_MAGIC_STRING "ReIsEr3Fs"
 
-int is_reiserfs_3_5 (struct reiserfs_super_block * rs);
-int is_reiserfs_3_6 (struct reiserfs_super_block * rs);
-int is_reiserfs_jr (struct reiserfs_super_block * rs);
+int is_reiserfs_3_5(struct reiserfs_super_block *rs);
+int is_reiserfs_3_6(struct reiserfs_super_block *rs);
+int is_reiserfs_jr(struct reiserfs_super_block *rs);
 
 /* ReiserFS leaves the first 64k unused, so that partition labels have
    enough space.  If someone wants to write a fancy bootloader that
@@ -272,8 +264,8 @@ typedef __u32 b_blocknr_t;
 typedef __le32 unp_t;
 
 struct unfm_nodeinfo {
-    unp_t unfm_nodenum;
-    unsigned short unfm_freespace;
+        unp_t unfm_nodenum;
+        unsigned short unfm_freespace;
 };
 
 /* there are two formats of keys: 3.5 and 3.6
@@ -285,7 +277,6 @@ struct unfm_nodeinfo {
 #define STAT_DATA_V1 0
 #define STAT_DATA_V2 1
 
-
 static inline struct reiserfs_inode_info *REISERFS_I(const struct inode *inode)
 {
         return container_of(inode, struct reiserfs_inode_info, vfs_inode);
@@ -343,15 +334,13 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb)
    file would fit into one DIRECT item.
    Primary intention for this one is to increase performance by decreasing
    seeking.
-*/   
+*/
 #define STORE_TAIL_IN_UNFM_S2(n_file_size,n_tail_size,n_block_size) \
 (\
   (!(n_tail_size)) || \
   (((n_file_size) > MAX_DIRECT_ITEM_LEN(n_block_size)) ) \
 )
 
-
-
 /*
  * values for s_umount_state field
  */
@@ -364,9 +353,9 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb)
 #define TYPE_STAT_DATA 0
 #define TYPE_INDIRECT 1
 #define TYPE_DIRECT 2
-#define TYPE_DIRENTRY 3 
-#define TYPE_MAXTYPE 3 
-#define TYPE_ANY 15 // FIXME: comment is required
+#define TYPE_DIRENTRY 3
+#define TYPE_MAXTYPE 3
+#define TYPE_ANY 15             // FIXME: comment is required
 
 /***************************************************************************/
 /*                       KEY & ITEM HEAD                                   */
@@ -376,60 +365,62 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb)
 // directories use this key as well as old files
 //
 struct offset_v1 {
-    __le32 k_offset;
-    __le32 k_uniqueness;
+        __le32 k_offset;
+        __le32 k_uniqueness;
 } __attribute__ ((__packed__));
 
 struct offset_v2 {
         __le64 v;
 } __attribute__ ((__packed__));
 
-static inline __u16 offset_v2_k_type( const struct offset_v2 *v2 )
+static inline __u16 offset_v2_k_type(const struct offset_v2 *v2)
 {
         __u8 type = le64_to_cpu(v2->v) >> 60;
-        return (type <= TYPE_MAXTYPE)?type:TYPE_ANY;
+        return (type <= TYPE_MAXTYPE) ? type : TYPE_ANY;
 }
- 
-static inline void set_offset_v2_k_type( struct offset_v2 *v2, int type )
+
+static inline void set_offset_v2_k_type(struct offset_v2 *v2, int type)
 {
-        v2->v = (v2->v & cpu_to_le64(~0ULL>>4)) | cpu_to_le64((__u64)type<<60);
+        v2->v =
+            (v2->v & cpu_to_le64(~0ULL >> 4)) | cpu_to_le64((__u64) type << 60);
 }
- 
-static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 )
+
+static inline loff_t offset_v2_k_offset(const struct offset_v2 *v2)
 {
-        return le64_to_cpu(v2->v) & (~0ULL>>4);
+        return le64_to_cpu(v2->v) & (~0ULL >> 4);
 }
 
-static inline void set_offset_v2_k_offset( struct offset_v2 *v2, loff_t offset ){
-        offset &= (~0ULL>>4);
-        v2->v = (v2->v & cpu_to_le64(15ULL<<60)) | cpu_to_le64(offset);
+static inline void set_offset_v2_k_offset(struct offset_v2 *v2, loff_t offset)
+{
+        offset &= (~0ULL >> 4);
+        v2->v = (v2->v & cpu_to_le64(15ULL << 60)) | cpu_to_le64(offset);
 }
 
 /* Key of an item determines its location in the S+tree, and
    is composed of 4 components */
 struct reiserfs_key {
-    __le32 k_dir_id;    /* packing locality: by default parent
-                          directory object id */
-    __le32 k_objectid;  /* object identifier */
-    union {
-        struct offset_v1 k_offset_v1;
-        struct offset_v2 k_offset_v2;
-    } __attribute__ ((__packed__)) u;
+        __le32 k_dir_id;        /* packing locality: by default parent
+                                   directory object id */
+        __le32 k_objectid;      /* object identifier */
+        union {
+                struct offset_v1 k_offset_v1;
+                struct offset_v2 k_offset_v2;
+        } __attribute__ ((__packed__)) u;
 } __attribute__ ((__packed__));
 
 struct in_core_key {
-    __u32 k_dir_id;    /* packing locality: by default parent
-                          directory object id */
-    __u32 k_objectid;  /* object identifier */
-    __u64 k_offset;
-    __u8 k_type;
+        __u32 k_dir_id;         /* packing locality: by default parent
+                                   directory object id */
+        __u32 k_objectid;       /* object identifier */
+        __u64 k_offset;
+        __u8 k_type;
 };
 
 struct cpu_key {
-    struct in_core_key on_disk_key;
-    int version;
-    int key_length; /* 3 in all cases but direct2indirect and
-                       indirect2direct conversion */
+        struct in_core_key on_disk_key;
+        int version;
+        int key_length;         /* 3 in all cases but direct2indirect and
+                                   indirect2direct conversion */
 };
 
 /* Our function for comparing keys can compare keys of different
@@ -475,8 +466,7 @@ struct cpu_key {
     indirect items) and specifies the location of the item itself
     within the block.  */
 
-struct item_head
-{
+struct item_head {
         /* Everything in the tree is found by searching for it based on
          * its key.*/
         struct reiserfs_key ih_key;
@@ -492,13 +482,13 @@ struct item_head
                    number of directory entries in the directory item. */
                 __le16 ih_entry_count;
         } __attribute__ ((__packed__)) u;
-        __le16 ih_item_len;           /* total size of the item body */
-        __le16 ih_item_location;      /* an offset to the item body
-                                      * within the block */
-        __le16 ih_version;           /* 0 for all old items, 2 for new
-                                        ones. Highest bit is set by fsck
-                                        temporary, cleaned after all
-                                        done */
+        __le16 ih_item_len;     /* total size of the item body */
+        __le16 ih_item_location;        /* an offset to the item body
+                                         * within the block */
+        __le16 ih_version;      /* 0 for all old items, 2 for new
+                                   ones. Highest bit is set by fsck
+                                   temporary, cleaned after all
+                                   done */
 } __attribute__ ((__packed__));
 /* size of item header     */
 #define IH_SIZE (sizeof(struct item_head))
@@ -515,7 +505,6 @@ struct item_head
 #define put_ih_location(ih, val)     do { (ih)->ih_item_location = cpu_to_le16(val); } while (0)
 #define put_ih_item_len(ih, val)     do { (ih)->ih_item_len = cpu_to_le16(val); } while (0)
 
-
 #define unreachable_item(ih) (ih_version(ih) & (1 << 15))
 
 #define get_ih_free_space(ih) (ih_version (ih) == KEY_FORMAT_3_6 ? 0 : ih_free_space (ih))
@@ -537,40 +526,48 @@ struct item_head
 #define V1_INDIRECT_UNIQUENESS 0xfffffffe
 #define V1_DIRECT_UNIQUENESS 0xffffffff
 #define V1_DIRENTRY_UNIQUENESS 500
-#define V1_ANY_UNIQUENESS 555 // FIXME: comment is required
+#define V1_ANY_UNIQUENESS 555   // FIXME: comment is required
 
 //
 // here are conversion routines
 //
-static inline int uniqueness2type (__u32 uniqueness) CONSTF;
-static inline int uniqueness2type (__u32 uniqueness)
+static inline int uniqueness2type(__u32 uniqueness) CONSTF;
+static inline int uniqueness2type(__u32 uniqueness)
 {
-    switch ((int)uniqueness) {
-    case V1_SD_UNIQUENESS: return TYPE_STAT_DATA;
-    case V1_INDIRECT_UNIQUENESS: return TYPE_INDIRECT;
-    case V1_DIRECT_UNIQUENESS: return TYPE_DIRECT;
-    case V1_DIRENTRY_UNIQUENESS: return TYPE_DIRENTRY;
-    default:
-            reiserfs_warning (NULL, "vs-500: unknown uniqueness %d",
-                              uniqueness);
+        switch ((int)uniqueness) {
+        case V1_SD_UNIQUENESS:
+                return TYPE_STAT_DATA;
+        case V1_INDIRECT_UNIQUENESS:
+                return TYPE_INDIRECT;
+        case V1_DIRECT_UNIQUENESS:
+                return TYPE_DIRECT;
+        case V1_DIRENTRY_UNIQUENESS:
+                return TYPE_DIRENTRY;
+        default:
+                reiserfs_warning(NULL, "vs-500: unknown uniqueness %d",
+                                 uniqueness);
         case V1_ANY_UNIQUENESS:
-            return TYPE_ANY;
-    }
+                return TYPE_ANY;
+        }
 }
 
-static inline __u32 type2uniqueness (int type) CONSTF;
-static inline __u32 type2uniqueness (int type)
+static inline __u32 type2uniqueness(int type) CONSTF;
+static inline __u32 type2uniqueness(int type)
 {
-    switch (type) {
-    case TYPE_STAT_DATA: return V1_SD_UNIQUENESS;
-    case TYPE_INDIRECT: return V1_INDIRECT_UNIQUENESS;
-    case TYPE_DIRECT: return V1_DIRECT_UNIQUENESS;
-    case TYPE_DIRENTRY: return V1_DIRENTRY_UNIQUENESS;
-    default:
-            reiserfs_warning (NULL, "vs-501: unknown type %d", type);
+        switch (type) {
+        case TYPE_STAT_DATA:
+                return V1_SD_UNIQUENESS;
+        case TYPE_INDIRECT:
+                return V1_INDIRECT_UNIQUENESS;
+        case TYPE_DIRECT:
+                return V1_DIRECT_UNIQUENESS;
+        case TYPE_DIRENTRY:
+                return V1_DIRENTRY_UNIQUENESS;
+        default:
+                reiserfs_warning(NULL, "vs-501: unknown type %d", type);
         case TYPE_ANY:
-            return V1_ANY_UNIQUENESS;
-    }
+                return V1_ANY_UNIQUENESS;
+        }
 }
 
 //
@@ -578,57 +575,56 @@ static inline __u32 type2uniqueness (int type)
 // there is no way to get version of object from key, so, provide
 // version to these defines
 //
-static inline loff_t le_key_k_offset (int version, const struct reiserfs_key * key)
+static inline loff_t le_key_k_offset(int version,
+                                     const struct reiserfs_key *key)
 {
-    return (version == KEY_FORMAT_3_5) ?
-        le32_to_cpu( key->u.k_offset_v1.k_offset ) :
-        offset_v2_k_offset( &(key->u.k_offset_v2) );
+        return (version == KEY_FORMAT_3_5) ?
+            le32_to_cpu(key->u.k_offset_v1.k_offset) :
+            offset_v2_k_offset(&(key->u.k_offset_v2));
 }
 
-static inline loff_t le_ih_k_offset (const struct item_head * ih)
+static inline loff_t le_ih_k_offset(const struct item_head *ih)
 {
-    return le_key_k_offset (ih_version (ih), &(ih->ih_key));
+        return le_key_k_offset(ih_version(ih), &(ih->ih_key));
 }
 
-static inline loff_t le_key_k_type (int version, const struct reiserfs_key * key)
+static inline loff_t le_key_k_type(int version, const struct reiserfs_key *key)
 {
-    return (version == KEY_FORMAT_3_5) ?
-        uniqueness2type( le32_to_cpu( key->u.k_offset_v1.k_uniqueness)) :
-        offset_v2_k_type( &(key->u.k_offset_v2) );
+        return (version == KEY_FORMAT_3_5) ?
+            uniqueness2type(le32_to_cpu(key->u.k_offset_v1.k_uniqueness)) :
+            offset_v2_k_type(&(key->u.k_offset_v2));
 }
 
-static inline loff_t le_ih_k_type (const struct item_head * ih)
+static inline loff_t le_ih_k_type(const struct item_head *ih)
 {
-    return le_key_k_type (ih_version (ih), &(ih->ih_key));
+        return le_key_k_type(ih_version(ih), &(ih->ih_key));
 }
 
-
-static inline void set_le_key_k_offset (int version, struct reiserfs_key * key, loff_t offset)
+static inline void set_le_key_k_offset(int version, struct reiserfs_key *key,
+                                       loff_t offset)
 {
-    (version == KEY_FORMAT_3_5) ?
-        (void)(key->u.k_offset_v1.k_offset = cpu_to_le32 (offset)) : /* jdm check */
-        (void)(set_offset_v2_k_offset( &(key->u.k_offset_v2), offset ));
+        (version == KEY_FORMAT_3_5) ? (void)(key->u.k_offset_v1.k_offset = cpu_to_le32(offset)) :       /* jdm check */
+            (void)(set_offset_v2_k_offset(&(key->u.k_offset_v2), offset));
 }
 
-
-static inline void set_le_ih_k_offset (struct item_head * ih, loff_t offset)
+static inline void set_le_ih_k_offset(struct item_head *ih, loff_t offset)
 {
-    set_le_key_k_offset (ih_version (ih), &(ih->ih_key), offset);
+        set_le_key_k_offset(ih_version(ih), &(ih->ih_key), offset);
 }
 
-
-static inline void set_le_key_k_type (int version, struct reiserfs_key * key, int type)
+static inline void set_le_key_k_type(int version, struct reiserfs_key *key,
+                                     int type)
 {
-    (version == KEY_FORMAT_3_5) ?
-        (void)(key->u.k_offset_v1.k_uniqueness = cpu_to_le32(type2uniqueness(type))):
-        (void)(set_offset_v2_k_type( &(key->u.k_offset_v2), type ));
+        (version == KEY_FORMAT_3_5) ?
+            (void)(key->u.k_offset_v1.k_uniqueness =
+                   cpu_to_le32(type2uniqueness(type)))
+            : (void)(set_offset_v2_k_type(&(key->u.k_offset_v2), type));
 }
-static inline void set_le_ih_k_type (struct item_head * ih, int type)
+static inline void set_le_ih_k_type(struct item_head *ih, int type)
 {
-    set_le_key_k_type (ih_version (ih), &(ih->ih_key), type);
+        set_le_key_k_type(ih_version(ih), &(ih->ih_key), type);
 }
 
-
 #define is_direntry_le_key(version,key) (le_key_k_type (version, key) == TYPE_DIRENTRY)
 #define is_direct_le_key(version,key) (le_key_k_type (version, key) == TYPE_DIRECT)
 #define is_indirect_le_key(version,key) (le_key_k_type (version, key) == TYPE_INDIRECT)
@@ -642,34 +638,32 @@ static inline void set_le_ih_k_type (struct item_head * ih, int type)
 #define is_indirect_le_ih(ih) is_indirect_le_key (ih_version(ih), &((ih)->ih_key))
 #define is_statdata_le_ih(ih) is_statdata_le_key (ih_version (ih), &((ih)->ih_key))
 
-
-
 //
 // key is pointer to cpu key, result is cpu
 //
-static inline loff_t cpu_key_k_offset (const struct cpu_key * key)
+static inline loff_t cpu_key_k_offset(const struct cpu_key *key)
 {
-    return key->on_disk_key.k_offset;
+        return key->on_disk_key.k_offset;
 }
 
-static inline loff_t cpu_key_k_type (const struct cpu_key * key)
+static inline loff_t cpu_key_k_type(const struct cpu_key *key)
 {
-    return key->on_disk_key.k_type;
+        return key->on_disk_key.k_type;
 }
 
-static inline void set_cpu_key_k_offset (struct cpu_key * key, loff_t offset)
+static inline void set_cpu_key_k_offset(struct cpu_key *key, loff_t offset)
 {
         key->on_disk_key.k_offset = offset;
 }
 
-static inline void set_cpu_key_k_type (struct cpu_key * key, int type)
+static inline void set_cpu_key_k_type(struct cpu_key *key, int type)
 {
         key->on_disk_key.k_type = type;
 }
 
-static inline void cpu_key_k_offset_dec (struct cpu_key * key)
+static inline void cpu_key_k_offset_dec(struct cpu_key *key)
 {
-        key->on_disk_key.k_offset --;
+        key->on_disk_key.k_offset--;
 }
 
 #define is_direntry_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRENTRY)
@@ -677,34 +671,25 @@ static inline void cpu_key_k_offset_dec (struct cpu_key * key)
 #define is_indirect_cpu_key(key) (cpu_key_k_type (key) == TYPE_INDIRECT)
 #define is_statdata_cpu_key(key) (cpu_key_k_type (key) == TYPE_STAT_DATA)
 
-
 /* are these used ? */
 #define is_direntry_cpu_ih(ih) (is_direntry_cpu_key (&((ih)->ih_key)))
 #define is_direct_cpu_ih(ih) (is_direct_cpu_key (&((ih)->ih_key)))
 #define is_indirect_cpu_ih(ih) (is_indirect_cpu_key (&((ih)->ih_key)))
 #define is_statdata_cpu_ih(ih) (is_statdata_cpu_key (&((ih)->ih_key)))
 
-
-
-
-
 #define I_K_KEY_IN_ITEM(p_s_ih, p_s_key, n_blocksize) \
     ( ! COMP_SHORT_KEYS(p_s_ih, p_s_key) && \
           I_OFF_BYTE_IN_ITEM(p_s_ih, k_offset (p_s_key), n_blocksize) )
 
-/* maximal length of item */ 
+/* maximal length of item */
 #define MAX_ITEM_LEN(block_size) (block_size - BLKH_SIZE - IH_SIZE)
 #define MIN_ITEM_LEN 1
 
-
 /* object identifier for root dir */
 #define REISERFS_ROOT_OBJECTID 2
 #define REISERFS_ROOT_PARENT_OBJECTID 1
 extern struct reiserfs_key root_key;
 
-
-
-
 /* 
  * Picture represents a leaf of the S+tree
  *  ______________________________________________________
@@ -716,13 +701,13 @@ extern struct reiserfs_key root_key;
 
 /* Header of a disk block.  More precisely, header of a formatted leaf
    or internal node, and not the header of an unformatted node. */
-struct block_head {       
-  __le16 blk_level;        /* Level of a block in the tree. */
-  __le16 blk_nr_item;      /* Number of keys/items in a block. */
-  __le16 blk_free_space;   /* Block free space in bytes. */
-  __le16 blk_reserved;
-                                /* dump this in v4/planA */
-  struct reiserfs_key  blk_right_delim_key; /* kept only for compatibility */
+struct block_head {
+        __le16 blk_level;       /* Level of a block in the tree. */
+        __le16 blk_nr_item;     /* Number of keys/items in a block. */
+        __le16 blk_free_space;  /* Block free space in bytes. */
+        __le16 blk_reserved;
+        /* dump this in v4/planA */
+        struct reiserfs_key blk_right_delim_key;        /* kept only for compatibility */
 };
 
 #define BLKH_SIZE                     (sizeof(struct block_head))
@@ -741,12 +726,12 @@ struct block_head {
  * values for blk_level field of the struct block_head
  */
 
-#define FREE_LEVEL 0 /* when node gets removed from the tree its
-                        blk_level is set to FREE_LEVEL. It is then
-                        used to see whether the node is still in the
-                        tree */
+#define FREE_LEVEL 0            /* when node gets removed from the tree its
+                                   blk_level is set to FREE_LEVEL. It is then
+                                   used to see whether the node is still in the
+                                   tree */
 
-#define DISK_LEAF_NODE_LEVEL  1 /* Leaf node level.*/
+#define DISK_LEAF_NODE_LEVEL  1 /* Leaf node level. */
 
 /* Given the buffer head of a formatted node, resolve to the block head of that node. */
 #define B_BLK_HEAD(p_s_bh)            ((struct block_head *)((p_s_bh)->b_data))
@@ -759,7 +744,6 @@ struct block_head {
 #define PUT_B_LEVEL(p_s_bh,val)       do { set_blkh_level(B_BLK_HEAD(p_s_bh),val); } while (0)
 #define PUT_B_FREE_SPACE(p_s_bh,val)  do { set_blkh_free_space(B_BLK_HEAD(p_s_bh),val); } while (0)
 
-
 /* Get right delimiting key. -- little endian */
 #define B_PRIGHT_DELIM_KEY(p_s_bh)   (&(blk_right_delim_key(B_BLK_HEAD(p_s_bh))
 
@@ -770,41 +754,36 @@ struct block_head {
 #define B_IS_KEYS_LEVEL(p_s_bh)      (B_LEVEL(p_s_bh) > DISK_LEAF_NODE_LEVEL \
                                             && B_LEVEL(p_s_bh) <= MAX_HEIGHT)
 
-
-
-
 /***************************************************************************/
 /*                             STAT DATA                                   */
 /***************************************************************************/
 
-
 //
 // old stat data is 32 bytes long. We are going to distinguish new one by
 // different size
 //
-struct stat_data_v1
-{
-    __le16 sd_mode;     /* file type, permissions */
-    __le16 sd_nlink;    /* number of hard links */
-    __le16 sd_uid;              /* owner */
-    __le16 sd_gid;              /* group */
-    __le32 sd_size;     /* file size */
-    __le32 sd_atime;    /* time of last access */
-    __le32 sd_mtime;    /* time file was last modified  */
-    __le32 sd_ctime;    /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
-    union {
-        __le32 sd_rdev;
-        __le32 sd_blocks;       /* number of blocks file uses */
-    } __attribute__ ((__packed__)) u;
-    __le32 sd_first_direct_byte; /* first byte of file which is stored
-                                   in a direct item: except that if it
-                                   equals 1 it is a symlink and if it
-                                   equals ~(__u32)0 there is no
-                                   direct item.  The existence of this
-                                   field really grates on me. Let's
-                                   replace it with a macro based on
-                                   sd_size and our tail suppression
-                                   policy.  Someday.  -Hans */
+struct stat_data_v1 {
+        __le16 sd_mode;         /* file type, permissions */
+        __le16 sd_nlink;        /* number of hard links */
+        __le16 sd_uid;          /* owner */
+        __le16 sd_gid;          /* group */
+        __le32 sd_size;         /* file size */
+        __le32 sd_atime;        /* time of last access */
+        __le32 sd_mtime;        /* time file was last modified  */
+        __le32 sd_ctime;        /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
+        union {
+                __le32 sd_rdev;
+                __le32 sd_blocks;       /* number of blocks file uses */
+        } __attribute__ ((__packed__)) u;
+        __le32 sd_first_direct_byte;    /* first byte of file which is stored
+                                           in a direct item: except that if it
+                                           equals 1 it is a symlink and if it
+                                           equals ~(__u32)0 there is no
+                                           direct item.  The existence of this
+                                           field really grates on me. Let's
+                                           replace it with a macro based on
+                                           sd_size and our tail suppression
+                                           policy.  Someday.  -Hans */
 } __attribute__ ((__packed__));
 
 #define SD_V1_SIZE              (sizeof(struct stat_data_v1))
@@ -862,29 +841,29 @@ struct stat_data_v1
 /* Stat Data on disk (reiserfs version of UFS disk inode minus the
    address blocks) */
 struct stat_data {
-    __le16 sd_mode;     /* file type, permissions */
-    __le16 sd_attrs;     /* persistent inode flags */
-    __le32 sd_nlink;    /* number of hard links */
-    __le64 sd_size;     /* file size */
-    __le32 sd_uid;              /* owner */
-    __le32 sd_gid;              /* group */
-    __le32 sd_atime;    /* time of last access */
-    __le32 sd_mtime;    /* time file was last modified  */
-    __le32 sd_ctime;    /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
-    __le32 sd_blocks;
-    union {
-        __le32 sd_rdev;
-        __le32 sd_generation;
-      //__le32 sd_first_direct_byte;
-      /* first byte of file which is stored in a
-                                       direct item: except that if it equals 1
-                                       it is a symlink and if it equals
-                                       ~(__u32)0 there is no direct item.  The
-                                       existence of this field really grates
-                                       on me. Let's replace it with a macro
-                                       based on sd_size and our tail
-                                       suppression policy? */
-  } __attribute__ ((__packed__)) u;
+        __le16 sd_mode;         /* file type, permissions */
+        __le16 sd_attrs;        /* persistent inode flags */
+        __le32 sd_nlink;        /* number of hard links */
+        __le64 sd_size;         /* file size */
+        __le32 sd_uid;          /* owner */
+        __le32 sd_gid;          /* group */
+        __le32 sd_atime;        /* time of last access */
+        __le32 sd_mtime;        /* time file was last modified  */
+        __le32 sd_ctime;        /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */
+        __le32 sd_blocks;
+        union {
+                __le32 sd_rdev;
+                __le32 sd_generation;
+                //__le32 sd_first_direct_byte;
+                /* first byte of file which is stored in a
+                   direct item: except that if it equals 1
+                   it is a symlink and if it equals
+                   ~(__u32)0 there is no direct item.  The
+                   existence of this field really grates
+                   on me. Let's replace it with a macro
+                   based on sd_size and our tail
+                   suppression policy? */
+        } __attribute__ ((__packed__)) u;
 } __attribute__ ((__packed__));
 //
 // this is 44 bytes long
@@ -919,7 +898,6 @@ struct stat_data {
 #define sd_v2_attrs(sdp)         (le16_to_cpu((sdp)->sd_attrs))
 #define set_sd_v2_attrs(sdp,v)   ((sdp)->sd_attrs = cpu_to_le16(v))
 
-
 /***************************************************************************/
 /*                      DIRECTORY STRUCTURE                                */
 /***************************************************************************/
@@ -954,17 +932,14 @@ struct stat_data {
 /* NOT IMPLEMENTED:   
    Directory will someday contain stat data of object */
 
-
-
-struct reiserfs_de_head
-{
-  __le32 deh_offset;            /* third component of the directory entry key */
-  __le32 deh_dir_id;            /* objectid of the parent directory of the object, that is referenced
-                                           by directory entry */
-  __le32 deh_objectid;          /* objectid of the object, that is referenced by directory entry */
-  __le16 deh_location;          /* offset of name in the whole item */
-  __le16 deh_state;             /* whether 1) entry contains stat data (for future), and 2) whether
-                                           entry is hidden (unlinked) */
+struct reiserfs_de_head {
+        __le32 deh_offset;      /* third component of the directory entry key */
+        __le32 deh_dir_id;      /* objectid of the parent directory of the object, that is referenced
+                                   by directory entry */
+        __le32 deh_objectid;    /* objectid of the object, that is referenced by directory entry */
+        __le16 deh_location;    /* offset of name in the whole item */
+        __le16 deh_state;       /* whether 1) entry contains stat data (for future), and 2) whether
+                                   entry is hidden (unlinked) */
 } __attribute__ ((__packed__));
 #define DEH_SIZE                  sizeof(struct reiserfs_de_head)
 #define deh_offset(p_deh)         (le32_to_cpu((p_deh)->deh_offset))
@@ -986,7 +961,7 @@ struct reiserfs_de_head
 /* old format directories have this size when empty */
 #define EMPTY_DIR_SIZE_V1 (DEH_SIZE * 2 + 3)
 
-#define DEH_Statdata 0                  /* not used now */
+#define DEH_Statdata 0          /* not used now */
 #define DEH_Visible 2
 
 /* 64 bit systems (and the S/390) need to be aligned explicitly -jdm */
@@ -1023,10 +998,10 @@ struct reiserfs_de_head
 #define de_visible(deh)             test_bit_unaligned (DEH_Visible, &((deh)->deh_state))
 #define de_hidden(deh)              !test_bit_unaligned (DEH_Visible, &((deh)->deh_state))
 
-extern void make_empty_dir_item_v1 (char * body, __le32 dirid, __le32 objid,
-                                    __le32 par_dirid, __le32 par_objid);
-extern void make_empty_dir_item (char * body, __le32 dirid, __le32 objid,
-                                 __le32 par_dirid, __le32 par_objid);
+extern void make_empty_dir_item_v1(char *body, __le32 dirid, __le32 objid,
+                                   __le32 par_dirid, __le32 par_objid);
+extern void make_empty_dir_item(char *body, __le32 dirid, __le32 objid,
+                                __le32 par_dirid, __le32 par_objid);
 
 /* array of the entry headers */
  /* get item body */
@@ -1043,53 +1018,48 @@ extern void make_empty_dir_item (char * body, __le32 dirid, __le32 objid,
 #define I_DEH_N_ENTRY_LENGTH(ih,deh,i) \
 ((i) ? (deh_location((deh)-1) - deh_location((deh))) : (ih_item_len((ih)) - deh_location((deh))))
 */
-static inline int entry_length (const struct buffer_head * bh, 
-                                                                const struct item_head * ih, int pos_in_item)
+static inline int entry_length(const struct buffer_head *bh,
+                               const struct item_head *ih, int pos_in_item)
 {
-    struct reiserfs_de_head * deh;
+        struct reiserfs_de_head *deh;
 
-    deh = B_I_DEH (bh, ih) + pos_in_item;
-    if (pos_in_item)
-        return deh_location(deh-1) - deh_location(deh);
+        deh = B_I_DEH(bh, ih) + pos_in_item;
+        if (pos_in_item)
+                return deh_location(deh - 1) - deh_location(deh);
 
-    return ih_item_len(ih) - deh_location(deh);
+        return ih_item_len(ih) - deh_location(deh);
 }
 
-
-
 /* number of entries in the directory item, depends on ENTRY_COUNT being at the start of directory dynamic data. */
 #define I_ENTRY_COUNT(ih) (ih_entry_count((ih)))
 
-
 /* name by bh, ih and entry_num */
 #define B_I_E_NAME(bh,ih,entry_num) ((char *)(bh->b_data + ih_location(ih) + deh_location(B_I_DEH(bh,ih)+(entry_num))))
 
 // two entries per block (at least)
 #define REISERFS_MAX_NAME(block_size) 255
 
-
 /* this structure is used for operations on directory entries. It is
    not a disk structure. */
 /* When reiserfs_find_entry or search_by_entry_key find directory
    entry, they return filled reiserfs_dir_entry structure */
-struct reiserfs_dir_entry
-{
-  struct buffer_head * de_bh;
-  int de_item_num;
-  struct item_head * de_ih;
-  int de_entry_num;
-  struct reiserfs_de_head * de_deh;
-  int de_entrylen;
-  int de_namelen;
-  char * de_name;
-  char * de_gen_number_bit_string;
-
-  __u32 de_dir_id;
-  __u32 de_objectid;
-
-  struct cpu_key de_entry_key;
+struct reiserfs_dir_entry {
+        struct buffer_head *de_bh;
+        int de_item_num;
+        struct item_head *de_ih;
+        int de_entry_num;
+        struct reiserfs_de_head *de_deh;
+        int de_entrylen;
+        int de_namelen;
+        char *de_name;
+        char *de_gen_number_bit_string;
+
+        __u32 de_dir_id;
+        __u32 de_objectid;
+
+        struct cpu_key de_entry_key;
 };
-   
+
 /* these defines are useful when a particular member of a reiserfs_dir_entry is needed */
 
 /* pointer to file name, stored in entry */
@@ -1099,8 +1069,6 @@ struct reiserfs_dir_entry
 #define I_DEH_N_ENTRY_FILE_NAME_LENGTH(ih,deh,entry_num) \
 (I_DEH_N_ENTRY_LENGTH (ih, deh, entry_num) - (de_with_sd (deh) ? SD_SIZE : 0))
 
-
-
 /* hash value occupies bits from 7 up to 30 */
 #define GET_HASH_VALUE(offset) ((offset) & 0x7fffff80LL)
 /* generation number occupies 7 bits starting from 0 up to 6 */
@@ -1109,7 +1077,6 @@ struct reiserfs_dir_entry
 
 #define SET_GENERATION_NUMBER(offset,gen_number) (GET_HASH_VALUE(offset)|(gen_number))
 
-
 /*
  * Picture represents an internal node of the reiserfs tree
  *  ______________________________________________________
@@ -1125,9 +1092,9 @@ struct reiserfs_dir_entry
 /* Disk child pointer: The pointer from an internal node of the tree
    to a node that is on disk. */
 struct disk_child {
-  __le32       dc_block_number;              /* Disk child's block number. */
-  __le16       dc_size;                     /* Disk child's used space.   */
-  __le16       dc_reserved;
+        __le32 dc_block_number; /* Disk child's block number. */
+        __le16 dc_size;         /* Disk child's used space.   */
+        __le16 dc_reserved;
 };
 
 #define DC_SIZE (sizeof(struct disk_child))
@@ -1144,7 +1111,7 @@ struct disk_child {
 #define B_N_CHILD_NUM(p_s_bh,n_pos) (dc_block_number(B_N_CHILD(p_s_bh,n_pos)))
 #define PUT_B_N_CHILD_NUM(p_s_bh,n_pos, val) (put_dc_block_number(B_N_CHILD(p_s_bh,n_pos), val ))
 
- /* maximal value of field child_size in structure disk_child */ 
+ /* maximal value of field child_size in structure disk_child */
  /* child size is the combined size of all items and their headers */
 #define MAX_CHILD_SIZE(bh) ((int)( (bh)->b_size - BLKH_SIZE ))
 
@@ -1159,7 +1126,6 @@ struct disk_child {
 /*                      PATH STRUCTURES AND DEFINES                        */
 /***************************************************************************/
 
-
 /* Search_by_key fills up the path from the root to the leaf as it descends the tree looking for the
    key.  It uses reiserfs_bread to try to find buffers in the cache given their block number.  If it
    does not find them in the cache it reads them from disk.  For each node search_by_key finds using
@@ -1168,20 +1134,18 @@ struct disk_child {
    is looking through a leaf node bin_search will find the position of the item which has key either
    equal to given key, or which is the maximal key less than the given key. */
 
-struct  path_element  {
-  struct buffer_head *  pe_buffer;    /* Pointer to the buffer at the path in the tree. */
-  int                   pe_position;  /* Position in the tree node which is placed in the */
-                                      /* buffer above.                                  */
+struct path_element {
+        struct buffer_head *pe_buffer;  /* Pointer to the buffer at the path in the tree. */
+        int pe_position;        /* Position in the tree node which is placed in the */
+        /* buffer above.                                  */
 };
 
-#define MAX_HEIGHT 5 /* maximal height of a tree. don't change this without changing JOURNAL_PER_BALANCE_CNT */
-#define EXTENDED_MAX_HEIGHT         7 /* Must be equals MAX_HEIGHT + FIRST_PATH_ELEMENT_OFFSET */
-#define FIRST_PATH_ELEMENT_OFFSET   2 /* Must be equal to at least 2. */
-
-#define ILLEGAL_PATH_ELEMENT_OFFSET 1 /* Must be equal to FIRST_PATH_ELEMENT_OFFSET - 1 */
-#define MAX_FEB_SIZE 6   /* this MUST be MAX_HEIGHT + 1. See about FEB below */
-
+#define MAX_HEIGHT 5            /* maximal height of a tree. don't change this without changing JOURNAL_PER_BALANCE_CNT */
+#define EXTENDED_MAX_HEIGHT         7   /* Must be equals MAX_HEIGHT + FIRST_PATH_ELEMENT_OFFSET */
+#define FIRST_PATH_ELEMENT_OFFSET   2   /* Must be equal to at least 2. */
 
+#define ILLEGAL_PATH_ELEMENT_OFFSET 1   /* Must be equal to FIRST_PATH_ELEMENT_OFFSET - 1 */
+#define MAX_FEB_SIZE 6          /* this MUST be MAX_HEIGHT + 1. See about FEB below */
 
 /* We need to keep track of who the ancestors of nodes are.  When we
    perform a search we record which nodes were visited while
@@ -1200,14 +1164,14 @@ excessive effort to avoid disturbing the precious VFS code.:-( The
 gods only know how we are going to SMP the code that uses them.
 znodes are the way! */
 
-#define PATH_READA      0x1 /* do read ahead */
-#define PATH_READA_BACK 0x2 /* read backwards */
+#define PATH_READA      0x1     /* do read ahead */
+#define PATH_READA_BACK 0x2     /* read backwards */
 
-struct  path {
-  int                   path_length;                            /* Length of the array above.   */
-  int                   reada;
-  struct  path_element  path_elements[EXTENDED_MAX_HEIGHT];     /* Array of the path elements.  */
-  int                   pos_in_item;
+struct path {
+        int path_length;        /* Length of the array above.   */
+        int reada;
+        struct path_element path_elements[EXTENDED_MAX_HEIGHT]; /* Array of the path elements.  */
+        int pos_in_item;
 };
 
 #define pos_in_item(path) ((path)->pos_in_item)
@@ -1224,25 +1188,23 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,}
 /* Get position in the element at the path by path and path position. */
 #define PATH_OFFSET_POSITION(p_s_path,n_offset) (PATH_OFFSET_PELEMENT(p_s_path,n_offset)->pe_position)
 
-
 #define PATH_PLAST_BUFFER(p_s_path) (PATH_OFFSET_PBUFFER((p_s_path), (p_s_path)->path_length))
                                 /* you know, to the person who didn't
-                                   write this the macro name does not
-                                   at first suggest what it does.
-                                   Maybe POSITION_FROM_PATH_END? Or
-                                   maybe we should just focus on
-                                   dumping paths... -Hans */
+                                   write this the macro name does not
+                                   at first suggest what it does.
+                                   Maybe POSITION_FROM_PATH_END? Or
+                                   maybe we should just focus on
+                                   dumping paths... -Hans */
 #define PATH_LAST_POSITION(p_s_path) (PATH_OFFSET_POSITION((p_s_path), (p_s_path)->path_length))
 
-
 #define PATH_PITEM_HEAD(p_s_path)    B_N_PITEM_HEAD(PATH_PLAST_BUFFER(p_s_path),PATH_LAST_POSITION(p_s_path))
 
 /* in do_balance leaf has h == 0 in contrast with path structure,
    where root has level == 0. That is why we need these defines */
 #define PATH_H_PBUFFER(p_s_path, h) PATH_OFFSET_PBUFFER (p_s_path, p_s_path->path_length - (h)) /* tb->S[h] */
-#define PATH_H_PPARENT(path, h) PATH_H_PBUFFER (path, (h) + 1)                  /* tb->F[h] or tb->S[0]->b_parent */
-#define PATH_H_POSITION(path, h) PATH_OFFSET_POSITION (path, path->path_length - (h))   
-#define PATH_H_B_ITEM_ORDER(path, h) PATH_H_POSITION(path, h + 1)               /* tb->S[h]->b_item_order */
+#define PATH_H_PPARENT(path, h) PATH_H_PBUFFER (path, (h) + 1)  /* tb->F[h] or tb->S[0]->b_parent */
+#define PATH_H_POSITION(path, h) PATH_OFFSET_POSITION (path, path->path_length - (h))
+#define PATH_H_B_ITEM_ORDER(path, h) PATH_H_POSITION(path, h + 1)       /* tb->S[h]->b_item_order */
 
 #define PATH_H_PATH_OFFSET(p_s_path, n_h) ((p_s_path)->path_length - (n_h))
 
@@ -1253,7 +1215,6 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,}
 #define item_moved(ih,path) comp_items(ih, path)
 #define path_changed(ih,path) comp_items (ih, path)
 
-
 /***************************************************************************/
 /*                       MISC                                              */
 /***************************************************************************/
@@ -1272,30 +1233,26 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,}
 // reiserfs version 2 has max offset 60 bits. Version 1 - 32 bit offset
 #define U32_MAX (~(__u32)0)
 
-static inline loff_t max_reiserfs_offset (struct inode * inode)
+static inline loff_t max_reiserfs_offset(struct inode *inode)
 {
-    if (get_inode_item_key_version(inode) == KEY_FORMAT_3_5)
-        return (loff_t)U32_MAX;
+        if (get_inode_item_key_version(inode) == KEY_FORMAT_3_5)
+                return (loff_t) U32_MAX;
 
-    return (loff_t)((~(__u64)0) >> 4);
+        return (loff_t) ((~(__u64) 0) >> 4);
 }
 
-
 /*#define MAX_KEY_UNIQUENESS    MAX_UL_INT*/
 #define MAX_KEY_OBJECTID        MAX_UL_INT
 
-
 #define MAX_B_NUM  MAX_UL_INT
 #define MAX_FC_NUM MAX_US_INT
 
-
 /* the purpose is to detect overflow of an unsigned short */
 #define REISERFS_LINK_MAX (MAX_US_INT - 1000)
 
-
 /* The following defines are used in reiserfs_insert_item and reiserfs_append_item  */
-#define REISERFS_KERNEL_MEM             0       /* reiserfs kernel memory mode  */
-#define REISERFS_USER_MEM               1       /* reiserfs user memory mode            */
+#define REISERFS_KERNEL_MEM             0       /* reiserfs kernel memory mode  */
+#define REISERFS_USER_MEM               1       /* reiserfs user memory mode            */
 
 #define fs_generation(s) (REISERFS_SB(s)->s_generation_counter)
 #define get_generation(s) atomic_read (&fs_generation(s))
@@ -1303,7 +1260,6 @@ static inline loff_t max_reiserfs_offset (struct inode * inode)
 #define __fs_changed(gen,s) (gen != get_generation (s))
 #define fs_changed(gen,s) ({cond_resched(); __fs_changed(gen, s);})
 
-
 /***************************************************************************/
 /*                  FIXATE NODES                                           */
 /***************************************************************************/
@@ -1324,38 +1280,34 @@ static inline loff_t max_reiserfs_offset (struct inode * inode)
    calculating what we can shift to neighbors and how many nodes we
    have to have if we do not any shiftings, if we shift to left/right
    neighbor or to both. */
-struct virtual_item
-{
-    int vi_index; // index in the array of item operations
-    unsigned short vi_type;     // left/right mergeability
-    unsigned short vi_item_len;           /* length of item that it will have after balancing */
-    struct item_head * vi_ih;
-    const char * vi_item;     // body of item (old or new)
-    const void * vi_new_data; // 0 always but paste mode
-    void * vi_uarea;    // item specific area
+struct virtual_item {
+        int vi_index;           // index in the array of item operations
+        unsigned short vi_type; // left/right mergeability
+        unsigned short vi_item_len;     /* length of item that it will have after balancing */
+        struct item_head *vi_ih;
+        const char *vi_item;    // body of item (old or new)
+        const void *vi_new_data;        // 0 always but paste mode
+        void *vi_uarea;         // item specific area
 };
 
-
-struct virtual_node
-{
-  char * vn_free_ptr;           /* this is a pointer to the free space in the buffer */
-  unsigned short vn_nr_item;    /* number of items in virtual node */
-  short vn_size;                /* size of node , that node would have if it has unlimited size and no balancing is performed */
-  short vn_mode;                /* mode of balancing (paste, insert, delete, cut) */
-  short vn_affected_item_num; 
-  short vn_pos_in_item;
-  struct item_head * vn_ins_ih; /* item header of inserted item, 0 for other modes */
-  const void * vn_data;
-  struct virtual_item * vn_vi;  /* array of items (including a new one, excluding item to be deleted) */
+struct virtual_node {
+        char *vn_free_ptr;      /* this is a pointer to the free space in the buffer */
+        unsigned short vn_nr_item;      /* number of items in virtual node */
+        short vn_size;          /* size of node , that node would have if it has unlimited size and no balancing is performed */
+        short vn_mode;          /* mode of balancing (paste, insert, delete, cut) */
+        short vn_affected_item_num;
+        short vn_pos_in_item;
+        struct item_head *vn_ins_ih;    /* item header of inserted item, 0 for other modes */
+        const void *vn_data;
+        struct virtual_item *vn_vi;     /* array of items (including a new one, excluding item to be deleted) */
 };
 
 /* used by directory items when creating virtual nodes */
 struct direntry_uarea {
-    int flags;
-    __u16 entry_count;
-    __u16 entry_sizes[1];
-} __attribute__ ((__packed__)) ;
-
+        int flags;
+        __u16 entry_count;
+        __u16 entry_sizes[1];
+} __attribute__ ((__packed__));
 
 /***************************************************************************/
 /*                  TREE BALANCE                                           */
@@ -1378,73 +1330,72 @@ struct direntry_uarea {
 #define MAX_AMOUNT_NEEDED 2
 
 /* someday somebody will prefix every field in this struct with tb_ */
-struct tree_balance
-{
-  int tb_mode;
-  int need_balance_dirty;
-  struct super_block * tb_sb;
-  struct reiserfs_transaction_handle *transaction_handle ;
-  struct path * tb_path;
-  struct buffer_head * L[MAX_HEIGHT];        /* array of left neighbors of nodes in the path */
-  struct buffer_head * R[MAX_HEIGHT];        /* array of right neighbors of nodes in the path*/
-  struct buffer_head * FL[MAX_HEIGHT];       /* array of fathers of the left  neighbors      */
-  struct buffer_head * FR[MAX_HEIGHT];       /* array of fathers of the right neighbors      */
-  struct buffer_head * CFL[MAX_HEIGHT];      /* array of common parents of center node and its left neighbor  */
-  struct buffer_head * CFR[MAX_HEIGHT];      /* array of common parents of center node and its right neighbor */
-
-  struct buffer_head * FEB[MAX_FEB_SIZE]; /* array of empty buffers. Number of buffers in array equals
-                                             cur_blknum. */
-  struct buffer_head * used[MAX_FEB_SIZE];
-  struct buffer_head * thrown[MAX_FEB_SIZE];
-  int lnum[MAX_HEIGHT]; /* array of number of items which must be
-                           shifted to the left in order to balance the
-                           current node; for leaves includes item that
-                           will be partially shifted; for internal
-                           nodes, it is the number of child pointers
-                           rather than items. It includes the new item
-                           being created. The code sometimes subtracts
-                           one to get the number of wholly shifted
-                           items for other purposes. */
-  int rnum[MAX_HEIGHT]; /* substitute right for left in comment above */
-  int lkey[MAX_HEIGHT];               /* array indexed by height h mapping the key delimiting L[h] and
-                                               S[h] to its item number within the node CFL[h] */
-  int rkey[MAX_HEIGHT];               /* substitute r for l in comment above */
-  int insert_size[MAX_HEIGHT];        /* the number of bytes by we are trying to add or remove from
-                                               S[h]. A negative value means removing.  */
-  int blknum[MAX_HEIGHT];             /* number of nodes that will replace node S[h] after
-                                               balancing on the level h of the tree.  If 0 then S is
-                                               being deleted, if 1 then S is remaining and no new nodes
-                                               are being created, if 2 or 3 then 1 or 2 new nodes is
-                                               being created */
-
-  /* fields that are used only for balancing leaves of the tree */
-  int cur_blknum;       /* number of empty blocks having been already allocated                 */
-  int s0num;             /* number of items that fall into left most  node when S[0] splits     */
-  int s1num;             /* number of items that fall into first  new node when S[0] splits     */
-  int s2num;             /* number of items that fall into second new node when S[0] splits     */
-  int lbytes;            /* number of bytes which can flow to the left neighbor from the        left    */
-  /* most liquid item that cannot be shifted from S[0] entirely         */
-  /* if -1 then nothing will be partially shifted */
-  int rbytes;            /* number of bytes which will flow to the right neighbor from the right        */
-  /* most liquid item that cannot be shifted from S[0] entirely         */
-  /* if -1 then nothing will be partially shifted                           */
-  int s1bytes;          /* number of bytes which flow to the first  new node when S[0] splits   */
-                                /* note: if S[0] splits into 3 nodes, then items do not need to be cut  */
-  int s2bytes;
-  struct buffer_head * buf_to_free[MAX_FREE_BLOCK]; /* buffers which are to be freed after do_balance finishes by unfix_nodes */
-  char * vn_buf;                /* kmalloced memory. Used to create
+struct tree_balance {
+        int tb_mode;
+        int need_balance_dirty;
+        struct super_block *tb_sb;
+        struct reiserfs_transaction_handle *transaction_handle;
+        struct path *tb_path;
+        struct buffer_head *L[MAX_HEIGHT];      /* array of left neighbors of nodes in the path */
+        struct buffer_head *R[MAX_HEIGHT];      /* array of right neighbors of nodes in the path */
+        struct buffer_head *FL[MAX_HEIGHT];     /* array of fathers of the left  neighbors      */
+        struct buffer_head *FR[MAX_HEIGHT];     /* array of fathers of the right neighbors      */
+        struct buffer_head *CFL[MAX_HEIGHT];    /* array of common parents of center node and its left neighbor  */
+        struct buffer_head *CFR[MAX_HEIGHT];    /* array of common parents of center node and its right neighbor */
+
+        struct buffer_head *FEB[MAX_FEB_SIZE];  /* array of empty buffers. Number of buffers in array equals
+                                                   cur_blknum. */
+        struct buffer_head *used[MAX_FEB_SIZE];
+        struct buffer_head *thrown[MAX_FEB_SIZE];
+        int lnum[MAX_HEIGHT];   /* array of number of items which must be
+                                   shifted to the left in order to balance the
+                                   current node; for leaves includes item that
+                                   will be partially shifted; for internal
+                                   nodes, it is the number of child pointers
+                                   rather than items. It includes the new item
+                                   being created. The code sometimes subtracts
+                                   one to get the number of wholly shifted
+                                   items for other purposes. */
+        int rnum[MAX_HEIGHT];   /* substitute right for left in comment above */
+        int lkey[MAX_HEIGHT];   /* array indexed by height h mapping the key delimiting L[h] and
+                                   S[h] to its item number within the node CFL[h] */
+        int rkey[MAX_HEIGHT];   /* substitute r for l in comment above */
+        int insert_size[MAX_HEIGHT];    /* the number of bytes by we are trying to add or remove from
+                                           S[h]. A negative value means removing.  */
+        int blknum[MAX_HEIGHT]; /* number of nodes that will replace node S[h] after
+                                   balancing on the level h of the tree.  If 0 then S is
+                                   being deleted, if 1 then S is remaining and no new nodes
+                                   are being created, if 2 or 3 then 1 or 2 new nodes is
+                                   being created */
+
+        /* fields that are used only for balancing leaves of the tree */
+        int cur_blknum;         /* number of empty blocks having been already allocated                 */
+        int s0num;              /* number of items that fall into left most  node when S[0] splits     */
+        int s1num;              /* number of items that fall into first  new node when S[0] splits     */
+        int s2num;              /* number of items that fall into second new node when S[0] splits     */
+        int lbytes;             /* number of bytes which can flow to the left neighbor from the        left    */
+        /* most liquid item that cannot be shifted from S[0] entirely         */
+        /* if -1 then nothing will be partially shifted */
+        int rbytes;             /* number of bytes which will flow to the right neighbor from the right        */
+        /* most liquid item that cannot be shifted from S[0] entirely         */
+        /* if -1 then nothing will be partially shifted                           */
+        int s1bytes;            /* number of bytes which flow to the first  new node when S[0] splits   */
+        /* note: if S[0] splits into 3 nodes, then items do not need to be cut  */
+        int s2bytes;
+        struct buffer_head *buf_to_free[MAX_FREE_BLOCK];        /* buffers which are to be freed after do_balance finishes by unfix_nodes */
+        char *vn_buf;           /* kmalloced memory. Used to create
                                    virtual node and keep map of
                                    dirtied bitmap blocks */
-  int vn_buf_size;              /* size of the vn_buf */
-  struct virtual_node * tb_vn;  /* VN starts after bitmap of bitmap blocks */
+        int vn_buf_size;        /* size of the vn_buf */
+        struct virtual_node *tb_vn;     /* VN starts after bitmap of bitmap blocks */
 
-  int fs_gen;                  /* saved value of `reiserfs_generation' counter
-                                  see FILESYSTEM_CHANGED() macro in reiserfs_fs.h */
+        int fs_gen;             /* saved value of `reiserfs_generation' counter
+                                   see FILESYSTEM_CHANGED() macro in reiserfs_fs.h */
 #ifdef DISPLACE_NEW_PACKING_LOCALITIES
-  struct in_core_key  key;            /* key pointer, to pass to block allocator or
-                                 another low-level subsystem */
+        struct in_core_key key; /* key pointer, to pass to block allocator or
+                                   another low-level subsystem */
 #endif
-} ;
+};
 
 /* These are modes of balancing */
 
@@ -1479,13 +1430,12 @@ struct tree_balance
 /* used in do_balance for passing parent of node information that has
    been gotten from tb struct */
 struct buffer_info {
-    struct tree_balance * tb;
-    struct buffer_head * bi_bh;
-    struct buffer_head * bi_parent;
-    int bi_position;
+        struct tree_balance *tb;
+        struct buffer_head *bi_bh;
+        struct buffer_head *bi_parent;
+        int bi_position;
 };
 
-
 /* there are 4 types of items: stat data, directory item, indirect, direct.
 +-------------------+------------+--------------+------------+
 |                   |  k_offset  | k_uniqueness | mergeable? |
@@ -1503,24 +1453,24 @@ struct buffer_info {
 */
 
 struct item_operations {
-    int (*bytes_number) (struct item_head * ih, int block_size);
-    void (*decrement_key) (struct cpu_key *);
-    int (*is_left_mergeable) (struct reiserfs_key * ih, unsigned long bsize);
-    void (*print_item) (struct item_head *, char * item);
-    void (*check_item) (struct item_head *, char * item);
-
-    int (*create_vi) (struct virtual_node * vn, struct virtual_item * vi, 
-                      int is_affected, int insert_size);
-    int (*check_left) (struct virtual_item * vi, int free, 
-                            int start_skip, int end_skip);
-    int (*check_right) (struct virtual_item * vi, int free);
-    int (*part_size) (struct virtual_item * vi, int from, int to);
-    int (*unit_num) (struct virtual_item * vi);
-    void (*print_vi) (struct virtual_item * vi);
+        int (*bytes_number) (struct item_head * ih, int block_size);
+        void (*decrement_key) (struct cpu_key *);
+        int (*is_left_mergeable) (struct reiserfs_key * ih,
+                                  unsigned long bsize);
+        void (*print_item) (struct item_head *, char *item);
+        void (*check_item) (struct item_head *, char *item);
+
+        int (*create_vi) (struct virtual_node * vn, struct virtual_item * vi,
+                          int is_affected, int insert_size);
+        int (*check_left) (struct virtual_item * vi, int free,
+                           int start_skip, int end_skip);
+        int (*check_right) (struct virtual_item * vi, int free);
+        int (*part_size) (struct virtual_item * vi, int from, int to);
+        int (*unit_num) (struct virtual_item * vi);
+        void (*print_vi) (struct virtual_item * vi);
 };
 
-
-extern struct item_operations * item_ops [TYPE_ANY + 1];
+extern struct item_operations *item_ops[TYPE_ANY + 1];
 
 #define op_bytes_number(ih,bsize)                    item_ops[le_ih_k_type (ih)]->bytes_number (ih, bsize)
 #define op_is_left_mergeable(key,bsize)              item_ops[le_key_k_type (le_key_version (key), key)]->is_left_mergeable (key, bsize)
@@ -1533,8 +1483,6 @@ extern struct item_operations * item_ops [TYPE_ANY + 1];
 #define op_unit_num(vi)                              item_ops[(vi)->vi_index]->unit_num (vi)
 #define op_print_vi(vi)                              item_ops[(vi)->vi_index]->print_vi (vi)
 
-
-
 #define COMP_SHORT_KEYS comp_short_keys
 
 /* number of blocks pointed to by the indirect item */
@@ -1545,8 +1493,7 @@ extern struct item_operations * item_ops [TYPE_ANY + 1];
 
 /* number of bytes contained by the direct item or the unformatted nodes the indirect item points to */
 
-
-/* get the item header */ 
+/* get the item header */
 #define B_N_PITEM_HEAD(bh,item_num) ( (struct item_head * )((bh)->b_data + BLKH_SIZE) + (item_num) )
 
 /* get key */
@@ -1577,9 +1524,9 @@ extern struct item_operations * item_ops [TYPE_ANY + 1];
 #define PUT_B_I_POS_UNFM_POINTER(bh,ih,pos, val) do {*(((unp_t *)B_I_PITEM(bh,ih)) + (pos)) = cpu_to_le32(val); } while (0)
 
 struct reiserfs_iget_args {
-    __u32 objectid ;
-    __u32 dirid ;
-} ;
+        __u32 objectid;
+        __u32 dirid;
+};
 
 /***************************************************************************/
 /*                    FUNCTION DECLARATIONS                                */
@@ -1595,11 +1542,11 @@ struct reiserfs_iget_args {
 
 /* first block written in a commit.  */
 struct reiserfs_journal_desc {
-  __le32 j_trans_id ;                   /* id of commit */
-  __le32 j_len ;                        /* length of commit. len +1 is the commit block */
-  __le32 j_mount_id ;                           /* mount id of this trans*/
-  __le32 j_realblock[1] ; /* real locations for each block */
-} ;
+        __le32 j_trans_id;      /* id of commit */
+        __le32 j_len;           /* length of commit. len +1 is the commit block */
+        __le32 j_mount_id;      /* mount id of this trans */
+        __le32 j_realblock[1];  /* real locations for each block */
+};
 
 #define get_desc_trans_id(d)   le32_to_cpu((d)->j_trans_id)
 #define get_desc_trans_len(d)  le32_to_cpu((d)->j_len)
@@ -1611,10 +1558,10 @@ struct reiserfs_journal_desc {
 
 /* last block written in a commit */
 struct reiserfs_journal_commit {
-  __le32 j_trans_id ;                   /* must match j_trans_id from the desc block */
-  __le32 j_len ;                        /* ditto */
-  __le32 j_realblock[1] ; /* real locations for each block */
-} ;
+        __le32 j_trans_id;      /* must match j_trans_id from the desc block */
+        __le32 j_len;           /* ditto */
+        __le32 j_realblock[1];  /* real locations for each block */
+};
 
 #define get_commit_trans_id(c) le32_to_cpu((c)->j_trans_id)
 #define get_commit_trans_len(c)        le32_to_cpu((c)->j_len)
@@ -1628,27 +1575,34 @@ struct reiserfs_journal_commit {
 ** and this transaction does not need to be replayed.
 */
 struct reiserfs_journal_header {
-  __le32 j_last_flush_trans_id ;                /* id of last fully flushed transaction */
-  __le32 j_first_unflushed_offset ;      /* offset in the log of where to start replay after a crash */
-  __le32 j_mount_id ;
-  /* 12 */ struct journal_params jh_journal;
-} ;
+        __le32 j_last_flush_trans_id;   /* id of last fully flushed transaction */
+        __le32 j_first_unflushed_offset;        /* offset in the log of where to start replay after a crash */
+        __le32 j_mount_id;
+        /* 12 */ struct journal_params jh_journal;
+};
 
 /* biggest tunable defines are right here */
-#define JOURNAL_BLOCK_COUNT 8192 /* number of blocks in the journal */
-#define JOURNAL_TRANS_MAX_DEFAULT 1024   /* biggest possible single transaction, don't change for now (8/3/99) */
+#define JOURNAL_BLOCK_COUNT 8192        /* number of blocks in the journal */
+#define JOURNAL_TRANS_MAX_DEFAULT 1024  /* biggest possible single transaction, don't change for now (8/3/99) */
 #define JOURNAL_TRANS_MIN_DEFAULT 256
-#define JOURNAL_MAX_BATCH_DEFAULT   900 /* max blocks to batch into one transaction, don't make this any bigger than 900 */
+#define JOURNAL_MAX_BATCH_DEFAULT   900 /* max blocks to batch into one transaction, don't make this any bigger than 900 */
 #define JOURNAL_MIN_RATIO 2
-#define JOURNAL_MAX_COMMIT_AGE 30 
+#define JOURNAL_MAX_COMMIT_AGE 30
 #define JOURNAL_MAX_TRANS_AGE 30
 #define JOURNAL_PER_BALANCE_CNT (3 * (MAX_HEIGHT-2) + 9)
 #ifdef CONFIG_QUOTA
-#define REISERFS_QUOTA_TRANS_BLOCKS 2   /* We need to update data and inode (atime) */
-#define REISERFS_QUOTA_INIT_BLOCKS (DQUOT_MAX_WRITES*(JOURNAL_PER_BALANCE_CNT+2)+1)     /* 1 balancing, 1 bitmap, 1 data per write + stat data update */
+/* We need to update data and inode (atime) */
+#define REISERFS_QUOTA_TRANS_BLOCKS(s) (REISERFS_SB(s)->s_mount_opt & (1<<REISERFS_QUOTA) ? 2 : 0)
+/* 1 balancing, 1 bitmap, 1 data per write + stat data update */
+#define REISERFS_QUOTA_INIT_BLOCKS(s) (REISERFS_SB(s)->s_mount_opt & (1<<REISERFS_QUOTA) ? \
+(DQUOT_INIT_ALLOC*(JOURNAL_PER_BALANCE_CNT+2)+DQUOT_INIT_REWRITE+1) : 0)
+/* same as with INIT */
+#define REISERFS_QUOTA_DEL_BLOCKS(s) (REISERFS_SB(s)->s_mount_opt & (1<<REISERFS_QUOTA) ? \
+(DQUOT_DEL_ALLOC*(JOURNAL_PER_BALANCE_CNT+2)+DQUOT_DEL_REWRITE+1) : 0)
 #else
-#define REISERFS_QUOTA_TRANS_BLOCKS 0
-#define REISERFS_QUOTA_INIT_BLOCKS 0
+#define REISERFS_QUOTA_TRANS_BLOCKS(s) 0
+#define REISERFS_QUOTA_INIT_BLOCKS(s) 0
+#define REISERFS_QUOTA_DEL_BLOCKS(s) 0
 #endif
 
 /* both of these can be as low as 1, or as high as you want.  The min is the
@@ -1657,10 +1611,10 @@ struct reiserfs_journal_header {
 ** the current number of nodes is > max, the node is freed, otherwise, 
 ** it is put on a free list for faster use later.
 */
-#define REISERFS_MIN_BITMAP_NODES 10 
-#define REISERFS_MAX_BITMAP_NODES 100 
+#define REISERFS_MIN_BITMAP_NODES 10
+#define REISERFS_MAX_BITMAP_NODES 100
 
-#define JBH_HASH_SHIFT 13 /* these are based on journal hash size of 8192 */
+#define JBH_HASH_SHIFT 13       /* these are based on journal hash size of 8192 */
 #define JBH_HASH_MASK 8191
 
 #define _jhashfn(sb,block)      \
@@ -1674,14 +1628,14 @@ struct reiserfs_journal_header {
 #define journal_bread(s, block) __bread(SB_JOURNAL(s)->j_dev_bd, block, s->s_blocksize)
 
 enum reiserfs_bh_state_bits {
-    BH_JDirty = BH_PrivateStart, /* buffer is in current transaction */
-    BH_JDirty_wait,
-    BH_JNew,                     /* disk block was taken off free list before
-                                  * being in a finished transaction, or
-                                  * written to disk. Can be reused immed. */
-    BH_JPrepared,
-    BH_JRestore_dirty,
-    BH_JTest, // debugging only will go away
+        BH_JDirty = BH_PrivateStart,    /* buffer is in current transaction */
+        BH_JDirty_wait,
+        BH_JNew,                /* disk block was taken off free list before
+                                 * being in a finished transaction, or
+                                 * written to disk. Can be reused immed. */
+        BH_JPrepared,
+        BH_JRestore_dirty,
+        BH_JTest,               // debugging only will go away
 };
 
 BUFFER_FNS(JDirty, journaled);
@@ -1701,175 +1655,192 @@ TAS_BUFFER_FNS(JTest, journal_test);
 ** transaction handle which is passed around for all journal calls
 */
 struct reiserfs_transaction_handle {
-  struct super_block *t_super ; /* super for this FS when journal_begin was
-                                   called. saves calls to reiserfs_get_super
-                                   also used by nested transactions to make
-                                   sure they are nesting on the right FS
-                                   _must_ be first in the handle
-                                */
-  int t_refcount;
-  int t_blocks_logged ;         /* number of blocks this writer has logged */
-  int t_blocks_allocated ;      /* number of blocks this writer allocated */
-  unsigned long t_trans_id ;    /* sanity check, equals the current trans id */
-  void *t_handle_save ;         /* save existing current->journal_info */
-  unsigned displace_new_blocks:1; /* if new block allocation occurres, that block
-                                   should be displaced from others */
-  struct list_head t_list;
-} ;
+        struct super_block *t_super;    /* super for this FS when journal_begin was
+                                           called. saves calls to reiserfs_get_super
+                                           also used by nested transactions to make
+                                           sure they are nesting on the right FS
+                                           _must_ be first in the handle
+                                         */
+        int t_refcount;
+        int t_blocks_logged;    /* number of blocks this writer has logged */
+        int t_blocks_allocated; /* number of blocks this writer allocated */
+        unsigned long t_trans_id;       /* sanity check, equals the current trans id */
+        void *t_handle_save;    /* save existing current->journal_info */
+        unsigned displace_new_blocks:1; /* if new block allocation occurres, that block
+                                           should be displaced from others */
+        struct list_head t_list;
+};
 
 /* used to keep track of ordered and tail writes, attached to the buffer
  * head through b_journal_head.
  */
 struct reiserfs_jh {
-    struct reiserfs_journal_list *jl;
-    struct buffer_head *bh;
-    struct list_head list;
+        struct reiserfs_journal_list *jl;
+        struct buffer_head *bh;
+        struct list_head list;
 };
 
 void reiserfs_free_jh(struct buffer_head *bh);
 int reiserfs_add_tail_list(struct inode *inode, struct buffer_head *bh);
 int reiserfs_add_ordered_list(struct inode *inode, struct buffer_head *bh);
-int journal_mark_dirty(struct reiserfs_transaction_handle *, struct super_block *, struct buffer_head *bh) ;
-
-static inline int
-reiserfs_file_data_log(struct inode *inode) {
-    if (reiserfs_data_log(inode->i_sb) ||
-       (REISERFS_I(inode)->i_flags & i_data_log))
-        return 1 ;
-    return 0 ;
+int journal_mark_dirty(struct reiserfs_transaction_handle *,
+                       struct super_block *, struct buffer_head *bh);
+
+static inline int reiserfs_file_data_log(struct inode *inode)
+{
+        if (reiserfs_data_log(inode->i_sb) ||
+            (REISERFS_I(inode)->i_flags & i_data_log))
+                return 1;
+        return 0;
 }
 
-static inline int reiserfs_transaction_running(struct super_block *s) {
-    struct reiserfs_transaction_handle *th = current->journal_info ;
-    if (th && th->t_super == s)
-        return 1 ;
-    if (th && th->t_super == NULL)
-        BUG();
-    return 0 ;
+static inline int reiserfs_transaction_running(struct super_block *s)
+{
+        struct reiserfs_transaction_handle *th = current->journal_info;
+        if (th && th->t_super == s)
+                return 1;
+        if (th && th->t_super == NULL)
+                BUG();
+        return 0;
 }
 
 int reiserfs_async_progress_wait(struct super_block *s);
 
-struct reiserfs_transaction_handle *
-reiserfs_persistent_transaction(struct super_block *, int count);
+struct reiserfs_transaction_handle *reiserfs_persistent_transaction(struct
+                                                                    super_block
+                                                                    *,
+                                                                    int count);
 int reiserfs_end_persistent_transaction(struct reiserfs_transaction_handle *);
 int reiserfs_commit_page(struct inode *inode, struct page *page,
-                unsigned from, unsigned to);
+                         unsigned from, unsigned to);
 int reiserfs_flush_old_commits(struct super_block *);
-int reiserfs_commit_for_inode(struct inode *) ;
-int  reiserfs_inode_needs_commit(struct inode *) ;
-void reiserfs_update_inode_transaction(struct inode *) ;
-void reiserfs_wait_on_write_block(struct super_block *s) ;
-void reiserfs_block_writes(struct reiserfs_transaction_handle *th) ;
-void reiserfs_allow_writes(struct super_block *s) ;
-void reiserfs_check_lock_depth(struct super_block *s, char *caller) ;
-int reiserfs_prepare_for_journal(struct super_block *, struct buffer_head *bh, int wait) ;
-void reiserfs_restore_prepared_buffer(struct super_block *, struct buffer_head *bh) ;
-int journal_init(struct super_block *, const char * j_dev_name, int old_format, unsigned int) ;
-int journal_release(struct reiserfs_transaction_handle*, struct super_block *) ;
-int journal_release_error(struct reiserfs_transaction_handle*, struct super_block *) ;
-int journal_end(struct reiserfs_transaction_handle *, struct super_block *, unsigned long) ;
-int journal_end_sync(struct reiserfs_transaction_handle *, struct super_block *, unsigned long) ;
-int journal_mark_freed(struct reiserfs_transaction_handle *, struct super_block *, b_blocknr_t blocknr) ;
-int journal_transaction_should_end(struct reiserfs_transaction_handle *, int) ;
-int reiserfs_in_journal(struct super_block *p_s_sb, int bmap_nr, int bit_nr, int searchall, b_blocknr_t *next) ;
-int journal_begin(struct reiserfs_transaction_handle *, struct super_block *p_s_sb, unsigned long) ;
-int journal_join_abort(struct reiserfs_transaction_handle *, struct super_block *p_s_sb, unsigned long) ;
-void reiserfs_journal_abort (struct super_block *sb, int errno);
-void reiserfs_abort (struct super_block *sb, int errno, const char *fmt, ...);
-int reiserfs_allocate_list_bitmaps(struct super_block *s, struct reiserfs_list_bitmap *, int) ;
-
-void add_save_link (struct reiserfs_transaction_handle * th,
-                                        struct inode * inode, int truncate);
-int remove_save_link (struct inode * inode, int truncate);
+int reiserfs_commit_for_inode(struct inode *);
+int reiserfs_inode_needs_commit(struct inode *);
+void reiserfs_update_inode_transaction(struct inode *);
+void reiserfs_wait_on_write_block(struct super_block *s);
+void reiserfs_block_writes(struct reiserfs_transaction_handle *th);
+void reiserfs_allow_writes(struct super_block *s);
+void reiserfs_check_lock_depth(struct super_block *s, char *caller);
+int reiserfs_prepare_for_journal(struct super_block *, struct buffer_head *bh,
+                                 int wait);
+void reiserfs_restore_prepared_buffer(struct super_block *,
+                                      struct buffer_head *bh);
+int journal_init(struct super_block *, const char *j_dev_name, int old_format,
+                 unsigned int);
+int journal_release(struct reiserfs_transaction_handle *, struct super_block *);
+int journal_release_error(struct reiserfs_transaction_handle *,
+                          struct super_block *);
+int journal_end(struct reiserfs_transaction_handle *, struct super_block *,
+                unsigned long);
+int journal_end_sync(struct reiserfs_transaction_handle *, struct super_block *,
+                     unsigned long);
+int journal_mark_freed(struct reiserfs_transaction_handle *,
+                       struct super_block *, b_blocknr_t blocknr);
+int journal_transaction_should_end(struct reiserfs_transaction_handle *, int);
+int reiserfs_in_journal(struct super_block *p_s_sb, int bmap_nr, int bit_nr,
+                        int searchall, b_blocknr_t * next);
+int journal_begin(struct reiserfs_transaction_handle *,
+                  struct super_block *p_s_sb, unsigned long);
+int journal_join_abort(struct reiserfs_transaction_handle *,
+                       struct super_block *p_s_sb, unsigned long);
+void reiserfs_journal_abort(struct super_block *sb, int errno);
+void reiserfs_abort(struct super_block *sb, int errno, const char *fmt, ...);
+int reiserfs_allocate_list_bitmaps(struct super_block *s,
+                                   struct reiserfs_list_bitmap *, int);
+
+void add_save_link(struct reiserfs_transaction_handle *th,
+                   struct inode *inode, int truncate);
+int remove_save_link(struct inode *inode, int truncate);
 
 /* objectid.c */
-__u32 reiserfs_get_unused_objectid (struct reiserfs_transaction_handle *th);
-void reiserfs_release_objectid (struct reiserfs_transaction_handle *th, __u32 objectid_to_release);
-int reiserfs_convert_objectid_map_v1(struct super_block *) ;
+__u32 reiserfs_get_unused_objectid(struct reiserfs_transaction_handle *th);
+void reiserfs_release_objectid(struct reiserfs_transaction_handle *th,
+                               __u32 objectid_to_release);
+int reiserfs_convert_objectid_map_v1(struct super_block *);
 
 /* stree.c */
 int B_IS_IN_TREE(const struct buffer_head *);
-extern void copy_item_head(struct item_head * p_v_to,
-                                                                  const struct item_head * p_v_from);
+extern void copy_item_head(struct item_head *p_v_to,
+                           const struct item_head *p_v_from);
 
 // first key is in cpu form, second - le
-extern int  comp_short_keys (const struct reiserfs_key * le_key,
-                                    const struct cpu_key * cpu_key);
-extern void le_key2cpu_key (struct cpu_key * to, const struct reiserfs_key * from);
+extern int comp_short_keys(const struct reiserfs_key *le_key,
+                           const struct cpu_key *cpu_key);
+extern void le_key2cpu_key(struct cpu_key *to, const struct reiserfs_key *from);
 
 // both are in le form
-extern int comp_le_keys (const struct reiserfs_key *, const struct reiserfs_key *);
-extern int comp_short_le_keys (const struct reiserfs_key *, const struct reiserfs_key *);
+extern int comp_le_keys(const struct reiserfs_key *,
+                        const struct reiserfs_key *);
+extern int comp_short_le_keys(const struct reiserfs_key *,
+                              const struct reiserfs_key *);
 
 //
 // get key version from on disk key - kludge
 //
-static inline int le_key_version (const struct reiserfs_key * key)
+static inline int le_key_version(const struct reiserfs_key *key)
 {
-    int type;
-    
-    type = offset_v2_k_type( &(key->u.k_offset_v2));
-    if (type != TYPE_DIRECT && type != TYPE_INDIRECT && type != TYPE_DIRENTRY)
-        return KEY_FORMAT_3_5;
-
-    return KEY_FORMAT_3_6;
-        
-}
+        int type;
 
+        type = offset_v2_k_type(&(key->u.k_offset_v2));
+        if (type != TYPE_DIRECT && type != TYPE_INDIRECT
+            && type != TYPE_DIRENTRY)
+                return KEY_FORMAT_3_5;
+
+        return KEY_FORMAT_3_6;
 
-static inline void copy_key (struct reiserfs_key *to, const struct reiserfs_key *from)
-{
-    memcpy (to, from, KEY_SIZE);
 }
 
+static inline void copy_key(struct reiserfs_key *to,
+                            const struct reiserfs_key *from)
+{
+        memcpy(to, from, KEY_SIZE);
+}
 
-int comp_items (const struct item_head * stored_ih, const struct path * p_s_path);
-const struct reiserfs_key * get_rkey (const struct path * p_s_chk_path,
-                                                         const struct super_block  * p_s_sb);
-int search_by_key (struct super_block *, const struct cpu_key *, 
-                                   struct path *, int);
+int comp_items(const struct item_head *stored_ih, const struct path *p_s_path);
+const struct reiserfs_key *get_rkey(const struct path *p_s_chk_path,
+                                    const struct super_block *p_s_sb);
+int search_by_key(struct super_block *, const struct cpu_key *,
+                  struct path *, int);
 #define search_item(s,key,path) search_by_key (s, key, path, DISK_LEAF_NODE_LEVEL)
-int search_for_position_by_key (struct super_block * p_s_sb, 
-                                                                const struct cpu_key * p_s_cpu_key, 
-                                                                struct path * p_s_search_path);
-extern void decrement_bcount (struct buffer_head * p_s_bh);
-void decrement_counters_in_path (struct path * p_s_search_path);
-void pathrelse (struct path * p_s_search_path);
-int reiserfs_check_path(struct path *p) ;
-void pathrelse_and_restore (struct super_block *s, struct path * p_s_search_path);
-
-int reiserfs_insert_item (struct reiserfs_transaction_handle *th, 
-                          struct path * path, 
-                          const struct cpu_key * key,
-                          struct item_head * ih,
-                          struct inode *inode, const char * body);
-
-int reiserfs_paste_into_item (struct reiserfs_transaction_handle *th,
-                              struct path * path,
-                              const struct cpu_key * key,
-                              struct inode *inode,
-                              const char * body, int paste_size);
-
-int reiserfs_cut_from_item (struct reiserfs_transaction_handle *th,
-                            struct path * path,
-                            struct cpu_key * key,
-                            struct inode * inode,
-                            struct page *page,
-                            loff_t new_file_size);
-
-int reiserfs_delete_item (struct reiserfs_transaction_handle *th,
-                          struct path * path, 
-                          const struct cpu_key * key,
-                          struct inode * inode, 
-                          struct buffer_head  * p_s_un_bh);
-
-void reiserfs_delete_solid_item (struct reiserfs_transaction_handle *th,
-                        struct inode *inode, struct reiserfs_key * key);
-int reiserfs_delete_object (struct reiserfs_transaction_handle *th, struct inode * p_s_inode);
-int reiserfs_do_truncate (struct reiserfs_transaction_handle *th,
-                           struct  inode * p_s_inode, struct page *, 
-                           int update_timestamps);
+int search_for_position_by_key(struct super_block *p_s_sb,
+                               const struct cpu_key *p_s_cpu_key,
+                               struct path *p_s_search_path);
+extern void decrement_bcount(struct buffer_head *p_s_bh);
+void decrement_counters_in_path(struct path *p_s_search_path);
+void pathrelse(struct path *p_s_search_path);
+int reiserfs_check_path(struct path *p);
+void pathrelse_and_restore(struct super_block *s, struct path *p_s_search_path);
+
+int reiserfs_insert_item(struct reiserfs_transaction_handle *th,
+                         struct path *path,
+                         const struct cpu_key *key,
+                         struct item_head *ih,
+                         struct inode *inode, const char *body);
+
+int reiserfs_paste_into_item(struct reiserfs_transaction_handle *th,
+                             struct path *path,
+                             const struct cpu_key *key,
+                             struct inode *inode,
+                             const char *body, int paste_size);
+
+int reiserfs_cut_from_item(struct reiserfs_transaction_handle *th,
+                           struct path *path,
+                           struct cpu_key *key,
+                           struct inode *inode,
+                           struct page *page, loff_t new_file_size);
+
+int reiserfs_delete_item(struct reiserfs_transaction_handle *th,
+                         struct path *path,
+                         const struct cpu_key *key,
+                         struct inode *inode, struct buffer_head *p_s_un_bh);
+
+void reiserfs_delete_solid_item(struct reiserfs_transaction_handle *th,
+                                struct inode *inode, struct reiserfs_key *key);
+int reiserfs_delete_object(struct reiserfs_transaction_handle *th,
+                           struct inode *p_s_inode);
+int reiserfs_do_truncate(struct reiserfs_transaction_handle *th,
+                         struct inode *p_s_inode, struct page *,
+                         int update_timestamps);
 
 #define i_block_size(inode) ((inode)->i_sb->s_blocksize)
 #define file_size(inode) ((inode)->i_size)
@@ -1878,66 +1849,67 @@ int reiserfs_do_truncate (struct reiserfs_transaction_handle *th,
 #define tail_has_to_be_packed(inode) (have_large_tails ((inode)->i_sb)?\
 !STORE_TAIL_IN_UNFM_S1(file_size (inode), tail_size(inode), inode->i_sb->s_blocksize):have_small_tails ((inode)->i_sb)?!STORE_TAIL_IN_UNFM_S2(file_size (inode), tail_size(inode), inode->i_sb->s_blocksize):0 )
 
-void padd_item (char * item, int total_length, int length);
+void padd_item(char *item, int total_length, int length);
 
 /* inode.c */
 /* args for the create parameter of reiserfs_get_block */
-#define GET_BLOCK_NO_CREATE 0 /* don't create new blocks or convert tails */
-#define GET_BLOCK_CREATE 1    /* add anything you need to find block */
-#define GET_BLOCK_NO_HOLE 2   /* return -ENOENT for file holes */
-#define GET_BLOCK_READ_DIRECT 4  /* read the tail if indirect item not found */
-#define GET_BLOCK_NO_ISEM     8 /* i_sem is not held, don't preallocate */
-#define GET_BLOCK_NO_DANGLE   16 /* don't leave any transactions running */
-
-int restart_transaction(struct reiserfs_transaction_handle *th, struct inode *inode, struct path *path);
-void reiserfs_read_locked_inode(struct inode * inode, struct reiserfs_iget_args *args) ;
-int reiserfs_find_actor(struct inode * inode, void *p) ;
-int reiserfs_init_locked_inode(struct inode * inode, void *p) ;
-void reiserfs_delete_inode (struct inode * inode);
-int reiserfs_write_inode (struct inode * inode, int) ;
-int reiserfs_get_block (struct inode * inode, sector_t block, struct buffer_head * bh_result, int create);
-struct dentry *reiserfs_get_dentry(struct super_block *, void *) ;
-struct dentry *reiserfs_decode_fh(struct super_block *sb, __u32 *data,
-                                     int len, int fhtype,
-                                  int (*acceptable)(void *contect, struct dentry *de),
-                                  void *context) ;
-int reiserfs_encode_fh( struct dentry *dentry, __u32 *data, int *lenp, 
-                                                int connectable );
-
-int reiserfs_truncate_file(struct inode *, int update_timestamps) ;
-void make_cpu_key (struct cpu_key * cpu_key, struct inode * inode, loff_t offset,
-                   int type, int key_length);
-void make_le_item_head (struct item_head * ih, const struct cpu_key * key, 
-                        int version,
-                        loff_t offset, int type, int length, int entry_count);
-struct inode * reiserfs_iget (struct super_block * s, 
-                              const struct cpu_key * key);
-
-
-int reiserfs_new_inode (struct reiserfs_transaction_handle *th, 
-                                   struct inode * dir, int mode, 
-                                   const char * symname, loff_t i_size,
-                                   struct dentry *dentry, struct inode *inode);
-
-void reiserfs_update_sd_size (struct reiserfs_transaction_handle *th,
-                              struct inode * inode, loff_t size);
+#define GET_BLOCK_NO_CREATE 0   /* don't create new blocks or convert tails */
+#define GET_BLOCK_CREATE 1      /* add anything you need to find block */
+#define GET_BLOCK_NO_HOLE 2     /* return -ENOENT for file holes */
+#define GET_BLOCK_READ_DIRECT 4 /* read the tail if indirect item not found */
+#define GET_BLOCK_NO_ISEM     8 /* i_sem is not held, don't preallocate */
+#define GET_BLOCK_NO_DANGLE   16        /* don't leave any transactions running */
+
+int restart_transaction(struct reiserfs_transaction_handle *th,
+                        struct inode *inode, struct path *path);
+void reiserfs_read_locked_inode(struct inode *inode,
+                                struct reiserfs_iget_args *args);
+int reiserfs_find_actor(struct inode *inode, void *p);
+int reiserfs_init_locked_inode(struct inode *inode, void *p);
+void reiserfs_delete_inode(struct inode *inode);
+int reiserfs_write_inode(struct inode *inode, int);
+int reiserfs_get_block(struct inode *inode, sector_t block,
+                       struct buffer_head *bh_result, int create);
+struct dentry *reiserfs_get_dentry(struct super_block *, void *);
+struct dentry *reiserfs_decode_fh(struct super_block *sb, __u32 * data,
+                                  int len, int fhtype,
+                                  int (*acceptable) (void *contect,
+                                                     struct dentry * de),
+                                  void *context);
+int reiserfs_encode_fh(struct dentry *dentry, __u32 * data, int *lenp,
+                       int connectable);
+
+int reiserfs_truncate_file(struct inode *, int update_timestamps);
+void make_cpu_key(struct cpu_key *cpu_key, struct inode *inode, loff_t offset,
+                  int type, int key_length);
+void make_le_item_head(struct item_head *ih, const struct cpu_key *key,
+                       int version,
+                       loff_t offset, int type, int length, int entry_count);
+struct inode *reiserfs_iget(struct super_block *s, const struct cpu_key *key);
+
+int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
+                       struct inode *dir, int mode,
+                       const char *symname, loff_t i_size,
+                       struct dentry *dentry, struct inode *inode);
+
+void reiserfs_update_sd_size(struct reiserfs_transaction_handle *th,
+                             struct inode *inode, loff_t size);
 
 static inline void reiserfs_update_sd(struct reiserfs_transaction_handle *th,
-                                      struct inode *inode)
+                                      struct inode *inode)
 {
-    reiserfs_update_sd_size(th, inode, inode->i_size) ;
+        reiserfs_update_sd_size(th, inode, inode->i_size);
 }
 
-void sd_attrs_to_i_attrs( __u16 sd_attrs, struct inode *inode );
-void i_attrs_to_sd_attrs( struct inode *inode, __u16 *sd_attrs );
+void sd_attrs_to_i_attrs(__u16 sd_attrs, struct inode *inode);
+void i_attrs_to_sd_attrs(struct inode *inode, __u16 * sd_attrs);
 int reiserfs_setattr(struct dentry *dentry, struct iattr *attr);
 
 /* namei.c */
-void set_de_name_and_namelen (struct reiserfs_dir_entry * de);
-int search_by_entry_key (struct super_block * sb, const struct cpu_key * key, 
-                         struct path * path, 
-                         struct reiserfs_dir_entry * de);
-struct dentry *reiserfs_get_parent(struct dentry *) ;
+void set_de_name_and_namelen(struct reiserfs_dir_entry *de);
+int search_by_entry_key(struct super_block *sb, const struct cpu_key *key,
+                        struct path *path, struct reiserfs_dir_entry *de);
+struct dentry *reiserfs_get_parent(struct dentry *);
 /* procfs.c */
 
 #if defined( CONFIG_PROC_FS ) && defined( CONFIG_REISERFS_PROC_INFO )
@@ -1946,15 +1918,15 @@ struct dentry *reiserfs_get_parent(struct dentry *) ;
 #undef REISERFS_PROC_INFO
 #endif
 
-int reiserfs_proc_info_init( struct super_block *sb );
-int reiserfs_proc_info_done( struct super_block *sb );
-struct proc_dir_entry *reiserfs_proc_register_global( char *name, 
-                                                                                                          read_proc_t *func );
-void reiserfs_proc_unregister_global( const char *name );
-int reiserfs_proc_info_global_init( void );
-int reiserfs_proc_info_global_done( void );
-int reiserfs_global_version_in_proc( char *buffer, char **start, off_t offset,
-                                                                         int count, int *eof, void *data );
+int reiserfs_proc_info_init(struct super_block *sb);
+int reiserfs_proc_info_done(struct super_block *sb);
+struct proc_dir_entry *reiserfs_proc_register_global(char *name,
+                                                     read_proc_t * func);
+void reiserfs_proc_unregister_global(const char *name);
+int reiserfs_proc_info_global_init(void);
+int reiserfs_proc_info_global_done(void);
+int reiserfs_global_version_in_proc(char *buffer, char **start, off_t offset,
+                                    int count, int *eof, void *data);
 
 #if defined( REISERFS_PROC_INFO )
 
@@ -1986,123 +1958,132 @@ extern struct inode_operations reiserfs_special_inode_operations;
 extern struct file_operations reiserfs_dir_operations;
 
 /* tail_conversion.c */
-int direct2indirect (struct reiserfs_transaction_handle *, struct inode *, struct path *, struct buffer_head *, loff_t);
-int indirect2direct (struct reiserfs_transaction_handle *, struct inode *, struct page *, struct path *, const struct cpu_key *, loff_t, char *);
-void reiserfs_unmap_buffer(struct buffer_head *) ;
-
+int direct2indirect(struct reiserfs_transaction_handle *, struct inode *,
+                    struct path *, struct buffer_head *, loff_t);
+int indirect2direct(struct reiserfs_transaction_handle *, struct inode *,
+                    struct page *, struct path *, const struct cpu_key *,
+                    loff_t, char *);
+void reiserfs_unmap_buffer(struct buffer_head *);
 
 /* file.c */
 extern struct inode_operations reiserfs_file_inode_operations;
 extern struct file_operations reiserfs_file_operations;
-extern struct address_space_operations reiserfs_address_space_operations ;
+extern struct address_space_operations reiserfs_address_space_operations;
 
 /* fix_nodes.c */
 #ifdef CONFIG_REISERFS_CHECK
-void * reiserfs_kmalloc (size_t size, int flags, struct super_block * s);
-void reiserfs_kfree (const void * vp, size_t size, struct super_block * s);
+void *reiserfs_kmalloc(size_t size, int flags, struct super_block *s);
+void reiserfs_kfree(const void *vp, size_t size, struct super_block *s);
 #else
 static inline void *reiserfs_kmalloc(size_t size, int flags,
-                                        struct super_block *s)
+                                     struct super_block *s)
 {
         return kmalloc(size, flags);
 }
 
 static inline void reiserfs_kfree(const void *vp, size_t size,
-                                        struct super_block *s)
+                                  struct super_block *s)
 {
         kfree(vp);
 }
 #endif
 
-int fix_nodes (int n_op_mode, struct tree_balance * p_s_tb, 
-               struct item_head * p_s_ins_ih, const void *);
-void unfix_nodes (struct tree_balance *);
-
+int fix_nodes(int n_op_mode, struct tree_balance *p_s_tb,
+              struct item_head *p_s_ins_ih, const void *);
+void unfix_nodes(struct tree_balance *);
 
 /* prints.c */
-void reiserfs_panic (struct super_block * s, const char * fmt, ...) __attribute__ ( ( noreturn ) );
-void reiserfs_info (struct super_block *s, const char * fmt, ...);
-void reiserfs_debug (struct super_block *s, int level, const char * fmt, ...);
-void print_indirect_item (struct buffer_head * bh, int item_num);
-void store_print_tb (struct tree_balance * tb);
-void print_cur_tb (char * mes);
-void print_de (struct reiserfs_dir_entry * de);
-void print_bi (struct buffer_info * bi, char * mes);
-#define PRINT_LEAF_ITEMS 1   /* print all items */
-#define PRINT_DIRECTORY_ITEMS 2 /* print directory items */
-#define PRINT_DIRECT_ITEMS 4 /* print contents of direct items */
-void print_block (struct buffer_head * bh, ...);
-void print_bmap (struct super_block * s, int silent);
-void print_bmap_block (int i, char * data, int size, int silent);
+void reiserfs_panic(struct super_block *s, const char *fmt, ...)
+    __attribute__ ((noreturn));
+void reiserfs_info(struct super_block *s, const char *fmt, ...);
+void reiserfs_debug(struct super_block *s, int level, const char *fmt, ...);
+void print_indirect_item(struct buffer_head *bh, int item_num);
+void store_print_tb(struct tree_balance *tb);
+void print_cur_tb(char *mes);
+void print_de(struct reiserfs_dir_entry *de);
+void print_bi(struct buffer_info *bi, char *mes);
+#define PRINT_LEAF_ITEMS 1      /* print all items */
+#define PRINT_DIRECTORY_ITEMS 2 /* print directory items */
+#define PRINT_DIRECT_ITEMS 4    /* print contents of direct items */
+void print_block(struct buffer_head *bh, ...);
+void print_bmap(struct super_block *s, int silent);
+void print_bmap_block(int i, char *data, int size, int silent);
 /*void print_super_block (struct super_block * s, char * mes);*/
-void print_objectid_map (struct super_block * s);
-void print_block_head (struct buffer_head * bh, char * mes);
-void check_leaf (struct buffer_head * bh);
-void check_internal (struct buffer_head * bh);
-void print_statistics (struct super_block * s);
-char * reiserfs_hashname(int code);
+void print_objectid_map(struct super_block *s);
+void print_block_head(struct buffer_head *bh, char *mes);
+void check_leaf(struct buffer_head *bh);
+void check_internal(struct buffer_head *bh);
+void print_statistics(struct super_block *s);
+char *reiserfs_hashname(int code);
 
 /* lbalance.c */
-int leaf_move_items (int shift_mode, struct tree_balance * tb, int mov_num, int mov_bytes, struct buffer_head * Snew);
-int leaf_shift_left (struct tree_balance * tb, int shift_num, int shift_bytes);
-int leaf_shift_right (struct tree_balance * tb, int shift_num, int shift_bytes);
-void leaf_delete_items (struct buffer_info * cur_bi, int last_first, int first, int del_num, int del_bytes);
-void leaf_insert_into_buf (struct buffer_info * bi, int before, 
-                           struct item_head * inserted_item_ih, const char * inserted_item_body, int zeros_number);
-void leaf_paste_in_buffer (struct buffer_info * bi, int pasted_item_num, 
-                           int pos_in_item, int paste_size, const char * body, int zeros_number);
-void leaf_cut_from_buffer (struct buffer_info * bi, int cut_item_num, int pos_in_item, 
-                           int cut_size);
-void leaf_paste_entries (struct buffer_head * bh, int item_num, int before, 
-                         int new_entry_count, struct reiserfs_de_head * new_dehs, const char * records, int paste_size);
+int leaf_move_items(int shift_mode, struct tree_balance *tb, int mov_num,
+                    int mov_bytes, struct buffer_head *Snew);
+int leaf_shift_left(struct tree_balance *tb, int shift_num, int shift_bytes);
+int leaf_shift_right(struct tree_balance *tb, int shift_num, int shift_bytes);
+void leaf_delete_items(struct buffer_info *cur_bi, int last_first, int first,
+                       int del_num, int del_bytes);
+void leaf_insert_into_buf(struct buffer_info *bi, int before,
+                          struct item_head *inserted_item_ih,
+                          const char *inserted_item_body, int zeros_number);
+void leaf_paste_in_buffer(struct buffer_info *bi, int pasted_item_num,
+                          int pos_in_item, int paste_size, const char *body,
+                          int zeros_number);
+void leaf_cut_from_buffer(struct buffer_info *bi, int cut_item_num,
+                          int pos_in_item, int cut_size);
+void leaf_paste_entries(struct buffer_head *bh, int item_num, int before,
+                        int new_entry_count, struct reiserfs_de_head *new_dehs,
+                        const char *records, int paste_size);
 /* ibalance.c */
-int balance_internal (struct tree_balance * , int, int, struct item_head * , 
-                      struct buffer_head **);
+int balance_internal(struct tree_balance *, int, int, struct item_head *,
+                     struct buffer_head **);
 
 /* do_balance.c */
-void do_balance_mark_leaf_dirty (struct tree_balance * tb,
-                                        struct buffer_head * bh, int flag);
+void do_balance_mark_leaf_dirty(struct tree_balance *tb,
+                                struct buffer_head *bh, int flag);
 #define do_balance_mark_internal_dirty do_balance_mark_leaf_dirty
 #define do_balance_mark_sb_dirty do_balance_mark_leaf_dirty
 
-void do_balance (struct tree_balance * tb, struct item_head * ih, 
-                 const char * body, int flag);
-void reiserfs_invalidate_buffer (struct tree_balance * tb, struct buffer_head * bh);
+void do_balance(struct tree_balance *tb, struct item_head *ih,
+                const char *body, int flag);
+void reiserfs_invalidate_buffer(struct tree_balance *tb,
+                                struct buffer_head *bh);
 
-int get_left_neighbor_position (struct tree_balance * tb, int h);
-int get_right_neighbor_position (struct tree_balance * tb, int h);
-void replace_key (struct tree_balance * tb, struct buffer_head *, int, struct buffer_head *, int);
-void make_empty_node (struct buffer_info *);
-struct buffer_head * get_FEB (struct tree_balance *);
+int get_left_neighbor_position(struct tree_balance *tb, int h);
+int get_right_neighbor_position(struct tree_balance *tb, int h);
+void replace_key(struct tree_balance *tb, struct buffer_head *, int,
+                 struct buffer_head *, int);
+void make_empty_node(struct buffer_info *);
+struct buffer_head *get_FEB(struct tree_balance *);
 
 /* bitmap.c */
 
 /* structure contains hints for block allocator, and it is a container for
  * arguments, such as node, search path, transaction_handle, etc. */
- struct __reiserfs_blocknr_hint {
-     struct inode * inode;              /* inode passed to allocator, if we allocate unf. nodes */
-     long block;                        /* file offset, in blocks */
-     struct in_core_key key;
-     struct path * path;                /* search path, used by allocator to deternine search_start by
-                                         * various ways */
-     struct reiserfs_transaction_handle * th; /* transaction handle is needed to log super blocks and
-                                               * bitmap blocks changes  */
-     b_blocknr_t beg, end;
-     b_blocknr_t search_start;          /* a field used to transfer search start value (block number)
+struct __reiserfs_blocknr_hint {
+        struct inode *inode;    /* inode passed to allocator, if we allocate unf. nodes */
+        long block;             /* file offset, in blocks */
+        struct in_core_key key;
+        struct path *path;      /* search path, used by allocator to deternine search_start by
+                                 * various ways */
+        struct reiserfs_transaction_handle *th; /* transaction handle is needed to log super blocks and
+                                                 * bitmap blocks changes  */
+        b_blocknr_t beg, end;
+        b_blocknr_t search_start;       /* a field used to transfer search start value (block number)
                                          * between different block allocator procedures
                                          * (determine_search_start() and others) */
-    int prealloc_size;                  /* is set in determine_prealloc_size() function, used by underlayed
-                                         * function that do actual allocation */
+        int prealloc_size;      /* is set in determine_prealloc_size() function, used by underlayed
+                                 * function that do actual allocation */
 
-    unsigned formatted_node:1;          /* the allocator uses different polices for getting disk space for
+        unsigned formatted_node:1;      /* the allocator uses different polices for getting disk space for
                                          * formatted/unformatted blocks with/without preallocation */
-    unsigned preallocate:1;
+        unsigned preallocate:1;
 };
 
 typedef struct __reiserfs_blocknr_hint reiserfs_blocknr_hint_t;
 
-int reiserfs_parse_alloc_options (struct super_block *, char *);
-void reiserfs_init_alloc_options (struct super_block *s);
+int reiserfs_parse_alloc_options(struct super_block *, char *);
+void reiserfs_init_alloc_options(struct super_block *s);
 
 /*
  * given a directory, this will tell you what packing locality
@@ -2111,68 +2092,72 @@ void reiserfs_init_alloc_options (struct super_block *s);
  */
 __le32 reiserfs_choose_packing(struct inode *dir);
 
-int is_reusable (struct super_block * s, b_blocknr_t block, int bit_value);
-void reiserfs_free_block (struct reiserfs_transaction_handle *th, struct inode *, b_blocknr_t, int for_unformatted);
-int reiserfs_allocate_blocknrs(reiserfs_blocknr_hint_t *, b_blocknr_t * , int, int);
-extern inline int reiserfs_new_form_blocknrs (struct tree_balance * tb,
-                                              b_blocknr_t *new_blocknrs, int amount_needed)
+int is_reusable(struct super_block *s, b_blocknr_t block, int bit_value);
+void reiserfs_free_block(struct reiserfs_transaction_handle *th, struct inode *,
+                         b_blocknr_t, int for_unformatted);
+int reiserfs_allocate_blocknrs(reiserfs_blocknr_hint_t *, b_blocknr_t *, int,
+                               int);
+extern inline int reiserfs_new_form_blocknrs(struct tree_balance *tb,
+                                             b_blocknr_t * new_blocknrs,
+                                             int amount_needed)
 {
-    reiserfs_blocknr_hint_t hint = {
-        .th = tb->transaction_handle,
-        .path = tb->tb_path,
-        .inode = NULL,
-        .key = tb->key,
-        .block = 0,
-        .formatted_node = 1
-    };
-    return reiserfs_allocate_blocknrs(&hint, new_blocknrs, amount_needed, 0);
+        reiserfs_blocknr_hint_t hint = {
+                .th = tb->transaction_handle,
+                .path = tb->tb_path,
+                .inode = NULL,
+                .key = tb->key,
+                .block = 0,
+                .formatted_node = 1
+        };
+        return reiserfs_allocate_blocknrs(&hint, new_blocknrs, amount_needed,
+                                          0);
 }
 
-extern inline int reiserfs_new_unf_blocknrs (struct reiserfs_transaction_handle *th,
-                                             struct inode *inode,
-                                             b_blocknr_t *new_blocknrs,
-                                             struct path * path, long block)
+extern inline int reiserfs_new_unf_blocknrs(struct reiserfs_transaction_handle
+                                            *th, struct inode *inode,
+                                            b_blocknr_t * new_blocknrs,
+                                            struct path *path, long block)
 {
-    reiserfs_blocknr_hint_t hint = {
-        .th = th,
-        .path = path,
-        .inode = inode,
-        .block = block,
-        .formatted_node = 0,
-        .preallocate = 0
-    };
-    return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0);
+        reiserfs_blocknr_hint_t hint = {
+                .th = th,
+                .path = path,
+                .inode = inode,
+                .block = block,
+                .formatted_node = 0,
+                .preallocate = 0
+        };
+        return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0);
 }
 
 #ifdef REISERFS_PREALLOCATE
-extern inline int reiserfs_new_unf_blocknrs2(struct reiserfs_transaction_handle *th,
-                                             struct inode * inode,
-                                             b_blocknr_t *new_blocknrs,
-                                             struct path * path, long block)
+extern inline int reiserfs_new_unf_blocknrs2(struct reiserfs_transaction_handle
+                                             *th, struct inode *inode,
+                                             b_blocknr_t * new_blocknrs,
+                                             struct path *path, long block)
 {
-    reiserfs_blocknr_hint_t hint = {
-        .th = th,
-        .path = path,
-        .inode = inode,
-        .block = block,
-        .formatted_node = 0,
-        .preallocate = 1
-    };
-    return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0);
+        reiserfs_blocknr_hint_t hint = {
+                .th = th,
+                .path = path,
+                .inode = inode,
+                .block = block,
+                .formatted_node = 0,
+                .preallocate = 1
+        };
+        return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0);
 }
 
-void reiserfs_discard_prealloc (struct reiserfs_transaction_handle *th, 
-                                struct inode * inode);
-void reiserfs_discard_all_prealloc (struct reiserfs_transaction_handle *th);
+void reiserfs_discard_prealloc(struct reiserfs_transaction_handle *th,
+                               struct inode *inode);
+void reiserfs_discard_all_prealloc(struct reiserfs_transaction_handle *th);
 #endif
-void reiserfs_claim_blocks_to_be_allocated( struct super_block *sb, int blocks);
-void reiserfs_release_claimed_blocks( struct super_block *sb, int blocks);
+void reiserfs_claim_blocks_to_be_allocated(struct super_block *sb, int blocks);
+void reiserfs_release_claimed_blocks(struct super_block *sb, int blocks);
 int reiserfs_can_fit_pages(struct super_block *sb);
 
 /* hashes.c */
-__u32 keyed_hash (const signed char *msg, int len);
-__u32 yura_hash (const signed char *msg, int len);
-__u32 r5_hash (const signed char *msg, int len);
+__u32 keyed_hash(const signed char *msg, int len);
+__u32 yura_hash(const signed char *msg, int len);
+__u32 r5_hash(const signed char *msg, int len);
 
 /* the ext2 bit routines adjust for big or little endian as
 ** appropriate for the arch, so in our laziness we use them rather
@@ -2192,11 +2177,10 @@ __u32 r5_hash (const signed char *msg, int len);
    absolutely safe */
 #define SPARE_SPACE 500
 
-
 /* prototypes from ioctl.c */
-int reiserfs_ioctl (struct inode * inode, struct file * filp, 
-                    unsigned int cmd, unsigned long arg);
- 
+int reiserfs_ioctl(struct inode *inode, struct file *filp,
+                   unsigned int cmd, unsigned long arg);
+
 /* ioctl's command */
 #define REISERFS_IOC_UNPACK             _IOW(0xCD,1,long)
 /* define following flags to be the same as in ext2, so that chattr(1),
@@ -2211,10 +2195,8 @@ int reiserfs_ioctl (struct inode * inode, struct file * filp,
    would evolve into real per-fs locks */
 #define reiserfs_write_lock( sb ) lock_kernel()
 #define reiserfs_write_unlock( sb ) unlock_kernel()
-                                 
+
 /* xattr stuff */
 #define REISERFS_XATTR_DIR_SEM(s) (REISERFS_SB(s)->xattr_dir_sem)
 
-#endif /* _LINUX_REISER_FS_H */
-
-
+#endif                          /* _LINUX_REISER_FS_H */
diff --git a/include/linux/reiserfs_fs_i.h b/include/linux/reiserfs_fs_i.h
index e321eb050d65..149be8d9a0c9 100644
--- a/include/linux/reiserfs_fs_i.h
+++ b/include/linux/reiserfs_fs_i.h
@@ -10,54 +10,53 @@ typedef enum {
     /** this says what format of key do all items (but stat data) of
       an object have.  If this is set, that format is 3.6 otherwise
       - 3.5 */
-    i_item_key_version_mask    =  0x0001,
+        i_item_key_version_mask = 0x0001,
     /** If this is unset, object has 3.5 stat data, otherwise, it has
       3.6 stat data with 64bit size, 32bit nlink etc. */
-    i_stat_data_version_mask   =  0x0002,
+        i_stat_data_version_mask = 0x0002,
     /** file might need tail packing on close */
-    i_pack_on_close_mask       =  0x0004,
+        i_pack_on_close_mask = 0x0004,
     /** don't pack tail of file */
-    i_nopack_mask              =  0x0008,
+        i_nopack_mask = 0x0008,
     /** If those is set, "safe link" was created for this file during
       truncate or unlink. Safe link is used to avoid leakage of disk
       space on crash with some files open, but unlinked. */
-    i_link_saved_unlink_mask   =  0x0010,
-    i_link_saved_truncate_mask =  0x0020,
-    i_has_xattr_dir            =  0x0040,
-    i_data_log                 =  0x0080,
+        i_link_saved_unlink_mask = 0x0010,
+        i_link_saved_truncate_mask = 0x0020,
+        i_has_xattr_dir = 0x0040,
+        i_data_log = 0x0080,
 } reiserfs_inode_flags;
 
-
 struct reiserfs_inode_info {
-    __u32 i_key [4];/* key is still 4 32 bit integers */
+        __u32 i_key[4];         /* key is still 4 32 bit integers */
     /** transient inode flags that are never stored on disk. Bitmasks
       for this field are defined above. */
-    __u32 i_flags;
+        __u32 i_flags;
 
-    __u32 i_first_direct_byte; // offset of first byte stored in direct item.
+        __u32 i_first_direct_byte;      // offset of first byte stored in direct item.
 
-    /* copy of persistent inode flags read from sd_attrs. */
-    __u32 i_attrs;
+        /* copy of persistent inode flags read from sd_attrs. */
+        __u32 i_attrs;
 
-    int i_prealloc_block; /* first unused block of a sequence of unused blocks */
-    int i_prealloc_count; /* length of that sequence */
-    struct list_head i_prealloc_list; /* per-transaction list of inodes which
-                                       * have preallocated blocks */
+        int i_prealloc_block;   /* first unused block of a sequence of unused blocks */
+        int i_prealloc_count;   /* length of that sequence */
+        struct list_head i_prealloc_list;       /* per-transaction list of inodes which
+                                                 * have preallocated blocks */
 
-    unsigned new_packing_locality:1;  /* new_packig_locality is created; new blocks
-                                       * for the contents of this directory should be
-                                       * displaced */
+        unsigned new_packing_locality:1;        /* new_packig_locality is created; new blocks
+                                                 * for the contents of this directory should be
+                                                 * displaced */
 
-    /* we use these for fsync or O_SYNC to decide which transaction
-    ** needs to be committed in order for this inode to be properly
-    ** flushed */
-    unsigned long i_trans_id ;
-    struct reiserfs_journal_list *i_jl;
+        /* we use these for fsync or O_SYNC to decide which transaction
+         ** needs to be committed in order for this inode to be properly
+         ** flushed */
+        unsigned long i_trans_id;
+        struct reiserfs_journal_list *i_jl;
 
-    struct posix_acl *i_acl_access;
-    struct posix_acl *i_acl_default;
-    struct rw_semaphore xattr_sem;
-    struct inode vfs_inode;
+        struct posix_acl *i_acl_access;
+        struct posix_acl *i_acl_default;
+        struct rw_semaphore xattr_sem;
+        struct inode vfs_inode;
 };
 
 #endif
diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h
index 37a3a7afbec7..3e68592e52e9 100644
--- a/include/linux/reiserfs_fs_sb.h
+++ b/include/linux/reiserfs_fs_sb.h
@@ -10,7 +10,7 @@
 #endif
 
 typedef enum {
-  reiserfs_attrs_cleared        = 0x00000001,
+        reiserfs_attrs_cleared = 0x00000001,
 } reiserfs_super_block_flags;
 
 /* struct reiserfs_super_block accessors/mutators
@@ -61,7 +61,7 @@ typedef enum {
 #define sb_umount_state(sbp)       (le16_to_cpu((sbp)->s_v1.s_umount_state))
 #define set_sb_umount_state(sbp,v) ((sbp)->s_v1.s_umount_state = cpu_to_le16(v))
 #define sb_fs_state(sbp)           (le16_to_cpu((sbp)->s_v1.s_fs_state))
-#define set_sb_fs_state(sbp,v)     ((sbp)->s_v1.s_fs_state = cpu_to_le16(v)) 
+#define set_sb_fs_state(sbp,v)     ((sbp)->s_v1.s_fs_state = cpu_to_le16(v))
 #define sb_hash_function_code(sbp) \
               (le32_to_cpu((sbp)->s_v1.s_hash_function_code))
 #define set_sb_hash_function_code(sbp,v) \
@@ -103,10 +103,10 @@ typedef enum {
 
 /* don't mess with these for a while */
                                 /* we have a node size define somewhere in reiserfs_fs.h. -Hans */
-#define JOURNAL_BLOCK_SIZE  4096 /* BUG gotta get rid of this */
-#define JOURNAL_MAX_CNODE   1500 /* max cnodes to allocate. */
-#define JOURNAL_HASH_SIZE 8192   
-#define JOURNAL_NUM_BITMAPS 5 /* number of copies of the bitmaps to have floating.  Must be >= 2 */
+#define JOURNAL_BLOCK_SIZE  4096        /* BUG gotta get rid of this */
+#define JOURNAL_MAX_CNODE   1500        /* max cnodes to allocate. */
+#define JOURNAL_HASH_SIZE 8192
+#define JOURNAL_NUM_BITMAPS 5   /* number of copies of the bitmaps to have floating.  Must be >= 2 */
 
 /* One of these for every block in every transaction
 ** Each one is in two hash tables.  First, a hash of the current transaction, and after journal_end, a
@@ -117,27 +117,27 @@ typedef enum {
 ** to a given transaction.
 */
 struct reiserfs_journal_cnode {
-  struct buffer_head *bh ;               /* real buffer head */
-  struct super_block *sb ;               /* dev of real buffer head */
-  __u32 blocknr ;                /* block number of real buffer head, == 0 when buffer on disk */
-  long state ;
-  struct reiserfs_journal_list *jlist ;  /* journal list this cnode lives in */
-  struct reiserfs_journal_cnode *next ;  /* next in transaction list */
-  struct reiserfs_journal_cnode *prev ;  /* prev in transaction list */
-  struct reiserfs_journal_cnode *hprev ; /* prev in hash list */
-  struct reiserfs_journal_cnode *hnext ; /* next in hash list */
+        struct buffer_head *bh; /* real buffer head */
+        struct super_block *sb; /* dev of real buffer head */
+        __u32 blocknr;          /* block number of real buffer head, == 0 when buffer on disk */
+        long state;
+        struct reiserfs_journal_list *jlist;    /* journal list this cnode lives in */
+        struct reiserfs_journal_cnode *next;    /* next in transaction list */
+        struct reiserfs_journal_cnode *prev;    /* prev in transaction list */
+        struct reiserfs_journal_cnode *hprev;   /* prev in hash list */
+        struct reiserfs_journal_cnode *hnext;   /* next in hash list */
 };
 
 struct reiserfs_bitmap_node {
-  int id ;
-  char *data ;
-  struct list_head list ;
-} ;
+        int id;
+        char *data;
+        struct list_head list;
+};
 
 struct reiserfs_list_bitmap {
-  struct reiserfs_journal_list *journal_list ;
-  struct reiserfs_bitmap_node **bitmaps ;
-} ;
+        struct reiserfs_journal_list *journal_list;
+        struct reiserfs_bitmap_node **bitmaps;
+};
 
 /*
 ** one of these for each transaction.  The most important part here is the j_realblock.
@@ -146,273 +146,269 @@ struct reiserfs_list_bitmap {
 ** and to make sure every real block in a transaction is on disk before allowing the log area
 ** to be overwritten */
 struct reiserfs_journal_list {
-  unsigned long j_start ;
-  unsigned long j_state;
-  unsigned long j_len ;
-  atomic_t j_nonzerolen ;
-  atomic_t j_commit_left ;
-  atomic_t j_older_commits_done ;      /* all commits older than this on disk*/
-  struct semaphore j_commit_lock;
-  unsigned long j_trans_id ;
-  time_t j_timestamp ;
-  struct reiserfs_list_bitmap *j_list_bitmap ;
-  struct buffer_head *j_commit_bh ; /* commit buffer head */
-  struct reiserfs_journal_cnode *j_realblock  ;
-  struct reiserfs_journal_cnode *j_freedlist ; /* list of buffers that were freed during this trans.  free each of these on flush */
-  /* time ordered list of all active transactions */
-  struct list_head j_list;
-
-  /* time ordered list of all transactions we haven't tried to flush yet */
-  struct list_head j_working_list;
-
-  /* list of tail conversion targets in need of flush before commit */
-  struct list_head j_tail_bh_list;
-  /* list of data=ordered buffers in need of flush before commit */
-  struct list_head j_bh_list;
-  int j_refcount;
-} ;
+        unsigned long j_start;
+        unsigned long j_state;
+        unsigned long j_len;
+        atomic_t j_nonzerolen;
+        atomic_t j_commit_left;
+        atomic_t j_older_commits_done;  /* all commits older than this on disk */
+        struct semaphore j_commit_lock;
+        unsigned long j_trans_id;
+        time_t j_timestamp;
+        struct reiserfs_list_bitmap *j_list_bitmap;
+        struct buffer_head *j_commit_bh;        /* commit buffer head */
+        struct reiserfs_journal_cnode *j_realblock;
+        struct reiserfs_journal_cnode *j_freedlist;     /* list of buffers that were freed during this trans.  free each of these on flush */
+        /* time ordered list of all active transactions */
+        struct list_head j_list;
+
+        /* time ordered list of all transactions we haven't tried to flush yet */
+        struct list_head j_working_list;
+
+        /* list of tail conversion targets in need of flush before commit */
+        struct list_head j_tail_bh_list;
+        /* list of data=ordered buffers in need of flush before commit */
+        struct list_head j_bh_list;
+        int j_refcount;
+};
 
 struct reiserfs_journal {
-  struct buffer_head ** j_ap_blocks ; /* journal blocks on disk */
-  struct reiserfs_journal_cnode *j_last ; /* newest journal block */
-  struct reiserfs_journal_cnode *j_first ; /*  oldest journal block.  start here for traverse */
-
-  struct file         *j_dev_file;
-  struct block_device *j_dev_bd;  
-  int j_1st_reserved_block;     /* first block on s_dev of reserved area journal */        
-        
-  long j_state ;                        
-  unsigned long j_trans_id ;
-  unsigned long j_mount_id ;
-  unsigned long j_start ;             /* start of current waiting commit (index into j_ap_blocks) */
-  unsigned long j_len ;               /* lenght of current waiting commit */
-  unsigned long j_len_alloc ;         /* number of buffers requested by journal_begin() */
-  atomic_t j_wcount ;            /* count of writers for current commit */
-  unsigned long j_bcount ;            /* batch count. allows turning X transactions into 1 */
-  unsigned long j_first_unflushed_offset ;  /* first unflushed transactions offset */
-  unsigned long j_last_flush_trans_id ;    /* last fully flushed journal timestamp */
-  struct buffer_head *j_header_bh ;   
-
-  time_t j_trans_start_time ;         /* time this transaction started */
-  struct semaphore j_lock;
-  struct semaphore j_flush_sem;
-  wait_queue_head_t j_join_wait ;    /* wait for current transaction to finish before starting new one */
-  atomic_t j_jlock ;                       /* lock for j_join_wait */
-  int j_list_bitmap_index ;           /* number of next list bitmap to use */
-  int j_must_wait ;                    /* no more journal begins allowed. MUST sleep on j_join_wait */
-  int j_next_full_flush ;             /* next journal_end will flush all journal list */
-  int j_next_async_flush ;             /* next journal_end will flush all async commits */
-
-  int j_cnode_used ;          /* number of cnodes on the used list */
-  int j_cnode_free ;          /* number of cnodes on the free list */
-
-  unsigned int j_trans_max ;           /* max number of blocks in a transaction.  */
-  unsigned int j_max_batch ;           /* max number of blocks to batch into a trans */
-  unsigned int j_max_commit_age ;      /* in seconds, how old can an async commit be */
-  unsigned int j_max_trans_age ;       /* in seconds, how old can a transaction be */
-  unsigned int j_default_max_commit_age ; /* the default for the max commit age */
-
-  struct reiserfs_journal_cnode *j_cnode_free_list ;
-  struct reiserfs_journal_cnode *j_cnode_free_orig ; /* orig pointer returned from vmalloc */
-
-  struct reiserfs_journal_list *j_current_jl;
-  int j_free_bitmap_nodes ;
-  int j_used_bitmap_nodes ;
-
-  int j_num_lists;      /* total number of active transactions */
-  int j_num_work_lists; /* number that need attention from kreiserfsd */
-
-  /* debugging to make sure things are flushed in order */
-  int j_last_flush_id;
-
-  /* debugging to make sure things are committed in order */
-  int j_last_commit_id;
-
-  struct list_head j_bitmap_nodes ;
-  struct list_head j_dirty_buffers ;
-  spinlock_t j_dirty_buffers_lock ; /* protects j_dirty_buffers */
-
-  /* list of all active transactions */
-  struct list_head j_journal_list;
-  /* lists that haven't been touched by writeback attempts */
-  struct list_head j_working_list;
-
-  struct reiserfs_list_bitmap j_list_bitmap[JOURNAL_NUM_BITMAPS] ;      /* array of bitmaps to record the deleted blocks */
-  struct reiserfs_journal_cnode *j_hash_table[JOURNAL_HASH_SIZE] ;          /* hash table for real buffer heads in current trans */ 
-  struct reiserfs_journal_cnode *j_list_hash_table[JOURNAL_HASH_SIZE] ; /* hash table for all the real buffer heads in all 
-                                                                                the transactions */
-  struct list_head j_prealloc_list;     /* list of inodes which have preallocated blocks */
-  int j_persistent_trans;
-  unsigned long j_max_trans_size ;
-  unsigned long j_max_batch_size ;
-
-  int j_errno;
-
-  /* when flushing ordered buffers, throttle new ordered writers */
-  struct work_struct j_work;
-  atomic_t j_async_throttle;
+        struct buffer_head **j_ap_blocks;       /* journal blocks on disk */
+        struct reiserfs_journal_cnode *j_last;  /* newest journal block */
+        struct reiserfs_journal_cnode *j_first; /*  oldest journal block.  start here for traverse */
+
+        struct file *j_dev_file;
+        struct block_device *j_dev_bd;
+        int j_1st_reserved_block;       /* first block on s_dev of reserved area journal */
+
+        long j_state;
+        unsigned long j_trans_id;
+        unsigned long j_mount_id;
+        unsigned long j_start;  /* start of current waiting commit (index into j_ap_blocks) */
+        unsigned long j_len;    /* lenght of current waiting commit */
+        unsigned long j_len_alloc;      /* number of buffers requested by journal_begin() */
+        atomic_t j_wcount;      /* count of writers for current commit */
+        unsigned long j_bcount; /* batch count. allows turning X transactions into 1 */
+        unsigned long j_first_unflushed_offset; /* first unflushed transactions offset */
+        unsigned long j_last_flush_trans_id;    /* last fully flushed journal timestamp */
+        struct buffer_head *j_header_bh;
+
+        time_t j_trans_start_time;      /* time this transaction started */
+        struct semaphore j_lock;
+        struct semaphore j_flush_sem;
+        wait_queue_head_t j_join_wait;  /* wait for current transaction to finish before starting new one */
+        atomic_t j_jlock;       /* lock for j_join_wait */
+        int j_list_bitmap_index;        /* number of next list bitmap to use */
+        int j_must_wait;        /* no more journal begins allowed. MUST sleep on j_join_wait */
+        int j_next_full_flush;  /* next journal_end will flush all journal list */
+        int j_next_async_flush; /* next journal_end will flush all async commits */
+
+        int j_cnode_used;       /* number of cnodes on the used list */
+        int j_cnode_free;       /* number of cnodes on the free list */
+
+        unsigned int j_trans_max;       /* max number of blocks in a transaction.  */
+        unsigned int j_max_batch;       /* max number of blocks to batch into a trans */
+        unsigned int j_max_commit_age;  /* in seconds, how old can an async commit be */
+        unsigned int j_max_trans_age;   /* in seconds, how old can a transaction be */
+        unsigned int j_default_max_commit_age;  /* the default for the max commit age */
+
+        struct reiserfs_journal_cnode *j_cnode_free_list;
+        struct reiserfs_journal_cnode *j_cnode_free_orig;       /* orig pointer returned from vmalloc */
+
+        struct reiserfs_journal_list *j_current_jl;
+        int j_free_bitmap_nodes;
+        int j_used_bitmap_nodes;
+
+        int j_num_lists;        /* total number of active transactions */
+        int j_num_work_lists;   /* number that need attention from kreiserfsd */
+
+        /* debugging to make sure things are flushed in order */
+        int j_last_flush_id;
+
+        /* debugging to make sure things are committed in order */
+        int j_last_commit_id;
+
+        struct list_head j_bitmap_nodes;
+        struct list_head j_dirty_buffers;
+        spinlock_t j_dirty_buffers_lock;        /* protects j_dirty_buffers */
+
+        /* list of all active transactions */
+        struct list_head j_journal_list;
+        /* lists that haven't been touched by writeback attempts */
+        struct list_head j_working_list;
+
+        struct reiserfs_list_bitmap j_list_bitmap[JOURNAL_NUM_BITMAPS]; /* array of bitmaps to record the deleted blocks */
+        struct reiserfs_journal_cnode *j_hash_table[JOURNAL_HASH_SIZE]; /* hash table for real buffer heads in current trans */
+        struct reiserfs_journal_cnode *j_list_hash_table[JOURNAL_HASH_SIZE];    /* hash table for all the real buffer heads in all 
+                                                                                   the transactions */
+        struct list_head j_prealloc_list;       /* list of inodes which have preallocated blocks */
+        int j_persistent_trans;
+        unsigned long j_max_trans_size;
+        unsigned long j_max_batch_size;
+
+        int j_errno;
+
+        /* when flushing ordered buffers, throttle new ordered writers */
+        struct work_struct j_work;
+        atomic_t j_async_throttle;
 };
 
 enum journal_state_bits {
-    J_WRITERS_BLOCKED = 1,   /* set when new writers not allowed */
-    J_WRITERS_QUEUED,        /* set when log is full due to too many writers */
-    J_ABORTED,               /* set when log is aborted */
+        J_WRITERS_BLOCKED = 1,  /* set when new writers not allowed */
+        J_WRITERS_QUEUED,       /* set when log is full due to too many writers */
+        J_ABORTED,              /* set when log is aborted */
 };
 
+#define JOURNAL_DESC_MAGIC "ReIsErLB"   /* ick.  magic string to find desc blocks in the journal */
 
-#define JOURNAL_DESC_MAGIC "ReIsErLB" /* ick.  magic string to find desc blocks in the journal */
+typedef __u32(*hashf_t) (const signed char *, int);
 
-typedef __u32 (*hashf_t) (const signed char *, int);
-
-struct reiserfs_bitmap_info
-{
-    // FIXME: Won't work with block sizes > 8K
-    __u16  first_zero_hint;
-    __u16  free_count;
-    struct buffer_head *bh; /* the actual bitmap */
+struct reiserfs_bitmap_info {
+        // FIXME: Won't work with block sizes > 8K
+        __u16 first_zero_hint;
+        __u16 free_count;
+        struct buffer_head *bh; /* the actual bitmap */
 };
 
 struct proc_dir_entry;
 
 #if defined( CONFIG_PROC_FS ) && defined( CONFIG_REISERFS_PROC_INFO )
 typedef unsigned long int stat_cnt_t;
-typedef struct reiserfs_proc_info_data
-{
-  spinlock_t lock;
-  int exiting;
-  int max_hash_collisions;
-
-  stat_cnt_t breads;
-  stat_cnt_t bread_miss;
-  stat_cnt_t search_by_key;
-  stat_cnt_t search_by_key_fs_changed;
-  stat_cnt_t search_by_key_restarted;
-
-  stat_cnt_t insert_item_restarted;
-  stat_cnt_t paste_into_item_restarted;
-  stat_cnt_t cut_from_item_restarted;
-  stat_cnt_t delete_solid_item_restarted;
-  stat_cnt_t delete_item_restarted;
-
-  stat_cnt_t leaked_oid;
-  stat_cnt_t leaves_removable;
-
-  /* balances per level. Use explicit 5 as MAX_HEIGHT is not visible yet. */
-  stat_cnt_t balance_at[ 5 ]; /* XXX */
-  /* sbk == search_by_key */
-  stat_cnt_t sbk_read_at[ 5 ]; /* XXX */
-  stat_cnt_t sbk_fs_changed[ 5 ];
-  stat_cnt_t sbk_restarted[ 5 ];
-  stat_cnt_t items_at[ 5 ]; /* XXX */
-  stat_cnt_t free_at[ 5 ]; /* XXX */
-  stat_cnt_t can_node_be_removed[ 5 ]; /* XXX */
-  long int lnum[ 5 ]; /* XXX */
-  long int rnum[ 5 ]; /* XXX */
-  long int lbytes[ 5 ]; /* XXX */
-  long int rbytes[ 5 ]; /* XXX */
-  stat_cnt_t get_neighbors[ 5 ];
-  stat_cnt_t get_neighbors_restart[ 5 ];
-  stat_cnt_t need_l_neighbor[ 5 ];
-  stat_cnt_t need_r_neighbor[ 5 ];
-
-  stat_cnt_t free_block;
-  struct __scan_bitmap_stats {
-        stat_cnt_t call;
-        stat_cnt_t wait;
-        stat_cnt_t bmap;
-        stat_cnt_t retry;
-        stat_cnt_t in_journal_hint;
-        stat_cnt_t in_journal_nohint;
-        stat_cnt_t stolen;
-  } scan_bitmap;
-  struct __journal_stats {
-        stat_cnt_t in_journal;
-        stat_cnt_t in_journal_bitmap;
-        stat_cnt_t in_journal_reusable;
-        stat_cnt_t lock_journal;
-        stat_cnt_t lock_journal_wait;
-        stat_cnt_t journal_being;
-        stat_cnt_t journal_relock_writers;
-        stat_cnt_t journal_relock_wcount;
-        stat_cnt_t mark_dirty;
-        stat_cnt_t mark_dirty_already;
-        stat_cnt_t mark_dirty_notjournal;
-        stat_cnt_t restore_prepared;
-        stat_cnt_t prepare;
-        stat_cnt_t prepare_retry;
-  } journal;
+typedef struct reiserfs_proc_info_data {
+        spinlock_t lock;
+        int exiting;
+        int max_hash_collisions;
+
+        stat_cnt_t breads;
+        stat_cnt_t bread_miss;
+        stat_cnt_t search_by_key;
+        stat_cnt_t search_by_key_fs_changed;
+        stat_cnt_t search_by_key_restarted;
+
+        stat_cnt_t insert_item_restarted;
+        stat_cnt_t paste_into_item_restarted;
+        stat_cnt_t cut_from_item_restarted;
+        stat_cnt_t delete_solid_item_restarted;
+        stat_cnt_t delete_item_restarted;
+
+        stat_cnt_t leaked_oid;
+        stat_cnt_t leaves_removable;
+
+        /* balances per level. Use explicit 5 as MAX_HEIGHT is not visible yet. */
+        stat_cnt_t balance_at[5];       /* XXX */
+        /* sbk == search_by_key */
+        stat_cnt_t sbk_read_at[5];      /* XXX */
+        stat_cnt_t sbk_fs_changed[5];
+        stat_cnt_t sbk_restarted[5];
+        stat_cnt_t items_at[5]; /* XXX */
+        stat_cnt_t free_at[5];  /* XXX */
+        stat_cnt_t can_node_be_removed[5];      /* XXX */
+        long int lnum[5];       /* XXX */
+        long int rnum[5];       /* XXX */
+        long int lbytes[5];     /* XXX */
+        long int rbytes[5];     /* XXX */
+        stat_cnt_t get_neighbors[5];
+        stat_cnt_t get_neighbors_restart[5];
+        stat_cnt_t need_l_neighbor[5];
+        stat_cnt_t need_r_neighbor[5];
+
+        stat_cnt_t free_block;
+        struct __scan_bitmap_stats {
+                stat_cnt_t call;
+                stat_cnt_t wait;
+                stat_cnt_t bmap;
+                stat_cnt_t retry;
+                stat_cnt_t in_journal_hint;
+                stat_cnt_t in_journal_nohint;
+                stat_cnt_t stolen;
+        } scan_bitmap;
+        struct __journal_stats {
+                stat_cnt_t in_journal;
+                stat_cnt_t in_journal_bitmap;
+                stat_cnt_t in_journal_reusable;
+                stat_cnt_t lock_journal;
+                stat_cnt_t lock_journal_wait;
+                stat_cnt_t journal_being;
+                stat_cnt_t journal_relock_writers;
+                stat_cnt_t journal_relock_wcount;
+                stat_cnt_t mark_dirty;
+                stat_cnt_t mark_dirty_already;
+                stat_cnt_t mark_dirty_notjournal;
+                stat_cnt_t restore_prepared;
+                stat_cnt_t prepare;
+                stat_cnt_t prepare_retry;
+        } journal;
 } reiserfs_proc_info_data_t;
 #else
-typedef struct reiserfs_proc_info_data
-{} reiserfs_proc_info_data_t;
+typedef struct reiserfs_proc_info_data {
+} reiserfs_proc_info_data_t;
 #endif
 
 /* reiserfs union of in-core super block data */
-struct reiserfs_sb_info
-{
-    struct buffer_head * s_sbh;                   /* Buffer containing the super block */
-                                /* both the comment and the choice of
-                                   name are unclear for s_rs -Hans */
-    struct reiserfs_super_block * s_rs;           /* Pointer to the super block in the buffer */
-    struct reiserfs_bitmap_info * s_ap_bitmap;
-    struct reiserfs_journal *s_journal ;                /* pointer to journal information */
-    unsigned short s_mount_state;                 /* reiserfs state (valid, invalid) */
-  
-                                /* Comment? -Hans */
-    void (*end_io_handler)(struct buffer_head *, int);
-    hashf_t s_hash_function;    /* pointer to function which is used
-                                   to sort names in directory. Set on
-                                   mount */
-    unsigned long s_mount_opt;  /* reiserfs's mount options are set
-                                   here (currently - NOTAIL, NOLOG,
-                                   REPLAYONLY) */
-
-    struct {                    /* This is a structure that describes block allocator options */
-        unsigned long bits;     /* Bitfield for enable/disable kind of options */
-        unsigned long large_file_size; /* size started from which we consider file to be a large one(in blocks) */
-        int border;             /* percentage of disk, border takes */
-        int preallocmin;        /* Minimal file size (in blocks) starting from which we do preallocations */
-        int preallocsize;       /* Number of blocks we try to prealloc when file
-                                   reaches preallocmin size (in blocks) or
-                                   prealloc_list is empty. */
-    } s_alloc_options;
-
-                                /* Comment? -Hans */
-    wait_queue_head_t s_wait;
-                                /* To be obsoleted soon by per buffer seals.. -Hans */
-    atomic_t s_generation_counter; // increased by one every time the
-    // tree gets re-balanced
-    unsigned long s_properties;    /* File system properties. Currently holds
-                                     on-disk FS format */
-    
-    /* session statistics */
-    int s_kmallocs;
-    int s_disk_reads;
-    int s_disk_writes;
-    int s_fix_nodes;
-    int s_do_balance;
-    int s_unneeded_left_neighbor;
-    int s_good_search_by_key_reada;
-    int s_bmaps;
-    int s_bmaps_without_search;
-    int s_direct2indirect;
-    int s_indirect2direct;
+struct reiserfs_sb_info {
+        struct buffer_head *s_sbh;      /* Buffer containing the super block */
+        /* both the comment and the choice of
+           name are unclear for s_rs -Hans */
+        struct reiserfs_super_block *s_rs;      /* Pointer to the super block in the buffer */
+        struct reiserfs_bitmap_info *s_ap_bitmap;
+        struct reiserfs_journal *s_journal;     /* pointer to journal information */
+        unsigned short s_mount_state;   /* reiserfs state (valid, invalid) */
+
+        /* Comment? -Hans */
+        void (*end_io_handler) (struct buffer_head *, int);
+        hashf_t s_hash_function;        /* pointer to function which is used
+                                           to sort names in directory. Set on
+                                           mount */
+        unsigned long s_mount_opt;      /* reiserfs's mount options are set
+                                           here (currently - NOTAIL, NOLOG,
+                                           REPLAYONLY) */
+
+        struct {                /* This is a structure that describes block allocator options */
+                unsigned long bits;     /* Bitfield for enable/disable kind of options */
+                unsigned long large_file_size;  /* size started from which we consider file to be a large one(in blocks) */
+                int border;     /* percentage of disk, border takes */
+                int preallocmin;        /* Minimal file size (in blocks) starting from which we do preallocations */
+                int preallocsize;       /* Number of blocks we try to prealloc when file
+                                           reaches preallocmin size (in blocks) or
+                                           prealloc_list is empty. */
+        } s_alloc_options;
+
+        /* Comment? -Hans */
+        wait_queue_head_t s_wait;
+        /* To be obsoleted soon by per buffer seals.. -Hans */
+        atomic_t s_generation_counter;  // increased by one every time the
+        // tree gets re-balanced
+        unsigned long s_properties;     /* File system properties. Currently holds
+                                           on-disk FS format */
+
+        /* session statistics */
+        int s_kmallocs;
+        int s_disk_reads;
+        int s_disk_writes;
+        int s_fix_nodes;
+        int s_do_balance;
+        int s_unneeded_left_neighbor;
+        int s_good_search_by_key_reada;
+        int s_bmaps;
+        int s_bmaps_without_search;
+        int s_direct2indirect;
+        int s_indirect2direct;
         /* set up when it's ok for reiserfs_read_inode2() to read from
            disk inode with nlink==0. Currently this is only used during
            finish_unfinished() processing at mount time */
-    int s_is_unlinked_ok;
-    reiserfs_proc_info_data_t s_proc_info_data;
-    struct proc_dir_entry *procdir;
-    int reserved_blocks; /* amount of blocks reserved for further allocations */
-    spinlock_t bitmap_lock; /* this lock on now only used to protect reserved_blocks variable */
-    struct dentry *priv_root; /* root of /.reiserfs_priv */
-    struct dentry *xattr_root; /* root of /.reiserfs_priv/.xa */
-    struct rw_semaphore xattr_dir_sem;
-
-    int j_errno;
+        int s_is_unlinked_ok;
+        reiserfs_proc_info_data_t s_proc_info_data;
+        struct proc_dir_entry *procdir;
+        int reserved_blocks;    /* amount of blocks reserved for further allocations */
+        spinlock_t bitmap_lock; /* this lock on now only used to protect reserved_blocks variable */
+        struct dentry *priv_root;       /* root of /.reiserfs_priv */
+        struct dentry *xattr_root;      /* root of /.reiserfs_priv/.xa */
+        struct rw_semaphore xattr_dir_sem;
+
+        int j_errno;
 #ifdef CONFIG_QUOTA
-    char *s_qf_names[MAXQUOTAS];
-    int s_jquota_fmt;
+        char *s_qf_names[MAXQUOTAS];
+        int s_jquota_fmt;
 #endif
 };
 
@@ -422,14 +418,14 @@ struct reiserfs_sb_info
 
 enum reiserfs_mount_options {
 /* Mount options */
-    REISERFS_LARGETAIL,  /* large tails will be created in a session */
-    REISERFS_SMALLTAIL,  /* small (for files less than block size) tails will be created in a session */
-    REPLAYONLY, /* replay journal and return 0. Use by fsck */
-    REISERFS_CONVERT,    /* -o conv: causes conversion of old
-                                 format super block to the new
-                                 format. If not specified - old
-                                 partition will be dealt with in a
-                                 manner of 3.5.x */
+        REISERFS_LARGETAIL,     /* large tails will be created in a session */
+        REISERFS_SMALLTAIL,     /* small (for files less than block size) tails will be created in a session */
+        REPLAYONLY,             /* replay journal and return 0. Use by fsck */
+        REISERFS_CONVERT,       /* -o conv: causes conversion of old
+                                   format super block to the new
+                                   format. If not specified - old
+                                   partition will be dealt with in a
+                                   manner of 3.5.x */
 
 /* -o hash={tea, rupasov, r5, detect} is meant for properly mounting 
 ** reiserfs disks from 3.5.19 or earlier.  99% of the time, this option
@@ -439,39 +435,41 @@ enum reiserfs_mount_options {
 ** the existing hash on the FS, so if you have a tea hash disk, and mount
 ** with -o hash=rupasov, the mount will fail.
 */
-    FORCE_TEA_HASH,      /* try to force tea hash on mount */
-    FORCE_RUPASOV_HASH,  /* try to force rupasov hash on mount */
-    FORCE_R5_HASH,       /* try to force rupasov hash on mount */
-    FORCE_HASH_DETECT,   /* try to detect hash function on mount */
+        FORCE_TEA_HASH,         /* try to force tea hash on mount */
+        FORCE_RUPASOV_HASH,     /* try to force rupasov hash on mount */
+        FORCE_R5_HASH,          /* try to force rupasov hash on mount */
+        FORCE_HASH_DETECT,      /* try to detect hash function on mount */
 
-    REISERFS_DATA_LOG,
-    REISERFS_DATA_ORDERED,
-    REISERFS_DATA_WRITEBACK,
+        REISERFS_DATA_LOG,
+        REISERFS_DATA_ORDERED,
+        REISERFS_DATA_WRITEBACK,
 
 /* used for testing experimental features, makes benchmarking new
    features with and without more convenient, should never be used by
    users in any code shipped to users (ideally) */
 
-    REISERFS_NO_BORDER,
-    REISERFS_NO_UNHASHED_RELOCATION,
-    REISERFS_HASHED_RELOCATION,
-    REISERFS_ATTRS,
-    REISERFS_XATTRS,
-    REISERFS_XATTRS_USER,
-    REISERFS_POSIXACL,
-    REISERFS_BARRIER_NONE,
-    REISERFS_BARRIER_FLUSH,
-
-    /* Actions on error */
-    REISERFS_ERROR_PANIC,
-    REISERFS_ERROR_RO,
-    REISERFS_ERROR_CONTINUE,
-
-    REISERFS_TEST1,
-    REISERFS_TEST2,
-    REISERFS_TEST3,
-    REISERFS_TEST4,
-    REISERFS_UNSUPPORTED_OPT,
+        REISERFS_NO_BORDER,
+        REISERFS_NO_UNHASHED_RELOCATION,
+        REISERFS_HASHED_RELOCATION,
+        REISERFS_ATTRS,
+        REISERFS_XATTRS,
+        REISERFS_XATTRS_USER,
+        REISERFS_POSIXACL,
+        REISERFS_BARRIER_NONE,
+        REISERFS_BARRIER_FLUSH,
+
+        /* Actions on error */
+        REISERFS_ERROR_PANIC,
+        REISERFS_ERROR_RO,
+        REISERFS_ERROR_CONTINUE,
+
+        REISERFS_QUOTA,         /* Some quota option specified */
+
+        REISERFS_TEST1,
+        REISERFS_TEST2,
+        REISERFS_TEST3,
+        REISERFS_TEST4,
+        REISERFS_UNSUPPORTED_OPT,
 };
 
 #define reiserfs_r5_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_R5_HASH))
@@ -502,18 +500,17 @@ enum reiserfs_mount_options {
 #define reiserfs_error_panic(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_ERROR_PANIC))
 #define reiserfs_error_ro(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_ERROR_RO))
 
-void reiserfs_file_buffer (struct buffer_head * bh, int list);
+void reiserfs_file_buffer(struct buffer_head *bh, int list);
 extern struct file_system_type reiserfs_fs_type;
-int reiserfs_resize(struct super_block *, unsigned long) ;
+int reiserfs_resize(struct super_block *, unsigned long);
 
 #define CARRY_ON                0
 #define SCHEDULE_OCCURRED       1
 
-
 #define SB_BUFFER_WITH_SB(s) (REISERFS_SB(s)->s_sbh)
 #define SB_JOURNAL(s) (REISERFS_SB(s)->s_journal)
 #define SB_JOURNAL_1st_RESERVED_BLOCK(s) (SB_JOURNAL(s)->j_1st_reserved_block)
-#define SB_JOURNAL_LEN_FREE(s) (SB_JOURNAL(s)->j_journal_len_free) 
+#define SB_JOURNAL_LEN_FREE(s) (SB_JOURNAL(s)->j_journal_len_free)
 #define SB_AP_BITMAP(s) (REISERFS_SB(s)->s_ap_bitmap)
 
 #define SB_DISK_JOURNAL_HEAD(s) (SB_JOURNAL(s)->j_header_bh->)
@@ -523,13 +520,14 @@ int reiserfs_resize(struct super_block *, unsigned long) ;
  */
 static inline char *reiserfs_bdevname(struct super_block *s)
 {
-        return (s == NULL) ? "Null superblock" : s -> s_id;
+        return (s == NULL) ? "Null superblock" : s->s_id;
 }
 
 #define reiserfs_is_journal_aborted(journal) (unlikely (__reiserfs_is_journal_aborted (journal)))
-static inline int __reiserfs_is_journal_aborted (struct reiserfs_journal *journal)
+static inline int __reiserfs_is_journal_aborted(struct reiserfs_journal
+                                                *journal)
 {
-    return test_bit (J_ABORTED, &journal->j_state);
+        return test_bit(J_ABORTED, &journal->j_state);
 }
 
-#endif  /* _LINUX_REISER_FS_SB */
+#endif                          /* _LINUX_REISER_FS_SB */
diff --git a/include/linux/reiserfs_xattr.h b/include/linux/reiserfs_xattr.h
index 9244c5748820..c84354e8374c 100644
--- a/include/linux/reiserfs_xattr.h
+++ b/include/linux/reiserfs_xattr.h
@@ -7,48 +7,48 @@
 #include <linux/xattr.h>
 
 /* Magic value in header */
-#define REISERFS_XATTR_MAGIC 0x52465841 /* "RFXA" */
+#define REISERFS_XATTR_MAGIC 0x52465841 /* "RFXA" */
 
 struct reiserfs_xattr_header {
-    __le32 h_magic;              /* magic number for identification */
-    __le32 h_hash;               /* hash of the value */
+        __le32 h_magic;         /* magic number for identification */
+        __le32 h_hash;          /* hash of the value */
 };
 
 #ifdef __KERNEL__
 
 struct reiserfs_xattr_handler {
         char *prefix;
-        int (*init)(void);
-        void (*exit)(void);
-        int (*get)(struct inode *inode, const char *name, void *buffer,
-                   size_t size);
-        int (*set)(struct inode *inode, const char *name, const void *buffer,
-                   size_t size, int flags);
-        int (*del)(struct inode *inode, const char *name);
-        int (*list)(struct inode *inode, const char *name, int namelen, char *out);
-        struct list_head handlers;
+        int (*init) (void);
+        void (*exit) (void);
+        int (*get) (struct inode * inode, const char *name, void *buffer,
+                    size_t size);
+        int (*set) (struct inode * inode, const char *name, const void *buffer,
+                    size_t size, int flags);
+        int (*del) (struct inode * inode, const char *name);
+        int (*list) (struct inode * inode, const char *name, int namelen,
+                     char *out);
+        struct list_head handlers;
 };
 
-
 #ifdef CONFIG_REISERFS_FS_XATTR
 #define is_reiserfs_priv_object(inode) IS_PRIVATE(inode)
 #define has_xattr_dir(inode) (REISERFS_I(inode)->i_flags & i_has_xattr_dir)
-ssize_t reiserfs_getxattr (struct dentry *dentry, const char *name,
-                           void *buffer, size_t size);
-int reiserfs_setxattr (struct dentry *dentry, const char *name,
-                       const void *value, size_t size, int flags);
-ssize_t reiserfs_listxattr (struct dentry *dentry, char *buffer, size_t size);
-int reiserfs_removexattr (struct dentry *dentry, const char *name);
-int reiserfs_delete_xattrs (struct inode *inode);
-int reiserfs_chown_xattrs (struct inode *inode, struct iattr *attrs);
-int reiserfs_xattr_init (struct super_block *sb, int mount_flags);
-int reiserfs_permission (struct inode *inode, int mask, struct nameidata *nd);
-int reiserfs_permission_locked (struct inode *inode, int mask, struct nameidata *nd);
-
-int reiserfs_xattr_del (struct inode *, const char *);
-int reiserfs_xattr_get (const struct inode *, const char *, void *, size_t);
-int reiserfs_xattr_set (struct inode *, const char *, const void *,
-                               size_t, int);
+ssize_t reiserfs_getxattr(struct dentry *dentry, const char *name,
+                          void *buffer, size_t size);
+int reiserfs_setxattr(struct dentry *dentry, const char *name,
+                      const void *value, size_t size, int flags);
+ssize_t reiserfs_listxattr(struct dentry *dentry, char *buffer, size_t size);
+int reiserfs_removexattr(struct dentry *dentry, const char *name);
+int reiserfs_delete_xattrs(struct inode *inode);
+int reiserfs_chown_xattrs(struct inode *inode, struct iattr *attrs);
+int reiserfs_xattr_init(struct super_block *sb, int mount_flags);
+int reiserfs_permission(struct inode *inode, int mask, struct nameidata *nd);
+int reiserfs_permission_locked(struct inode *inode, int mask,
+                               struct nameidata *nd);
+
+int reiserfs_xattr_del(struct inode *, const char *);
+int reiserfs_xattr_get(const struct inode *, const char *, void *, size_t);
+int reiserfs_xattr_set(struct inode *, const char *, const void *, size_t, int);
 
 extern struct reiserfs_xattr_handler user_handler;
 extern struct reiserfs_xattr_handler trusted_handler;
@@ -56,57 +56,48 @@ extern struct reiserfs_xattr_handler trusted_handler;
 extern struct reiserfs_xattr_handler security_handler;
 #endif
 
-int reiserfs_xattr_register_handlers (void) __init;
-void reiserfs_xattr_unregister_handlers (void);
+int reiserfs_xattr_register_handlers(void) __init;
+void reiserfs_xattr_unregister_handlers(void);
 
-static inline void
-reiserfs_write_lock_xattrs(struct super_block *sb)
+static inline void reiserfs_write_lock_xattrs(struct super_block *sb)
 {
-    down_write (&REISERFS_XATTR_DIR_SEM(sb));
+        down_write(&REISERFS_XATTR_DIR_SEM(sb));
 }
-static inline void
-reiserfs_write_unlock_xattrs(struct super_block *sb)
+static inline void reiserfs_write_unlock_xattrs(struct super_block *sb)
 {
-    up_write (&REISERFS_XATTR_DIR_SEM(sb));
+        up_write(&REISERFS_XATTR_DIR_SEM(sb));
 }
-static inline void
-reiserfs_read_lock_xattrs(struct super_block *sb)
+static inline void reiserfs_read_lock_xattrs(struct super_block *sb)
 {
-    down_read (&REISERFS_XATTR_DIR_SEM(sb));
+        down_read(&REISERFS_XATTR_DIR_SEM(sb));
 }
 
-static inline void
-reiserfs_read_unlock_xattrs(struct super_block *sb)
+static inline void reiserfs_read_unlock_xattrs(struct super_block *sb)
 {
-    up_read (&REISERFS_XATTR_DIR_SEM(sb));
+        up_read(&REISERFS_XATTR_DIR_SEM(sb));
 }
 
-static inline void
-reiserfs_write_lock_xattr_i(struct inode *inode)
+static inline void reiserfs_write_lock_xattr_i(struct inode *inode)
 {
-    down_write (&REISERFS_I(inode)->xattr_sem);
+        down_write(&REISERFS_I(inode)->xattr_sem);
 }
-static inline void
-reiserfs_write_unlock_xattr_i(struct inode *inode)
+static inline void reiserfs_write_unlock_xattr_i(struct inode *inode)
 {
-    up_write (&REISERFS_I(inode)->xattr_sem);
+        up_write(&REISERFS_I(inode)->xattr_sem);
 }
-static inline void
-reiserfs_read_lock_xattr_i(struct inode *inode)
+static inline void reiserfs_read_lock_xattr_i(struct inode *inode)
 {
-    down_read (&REISERFS_I(inode)->xattr_sem);
+        down_read(&REISERFS_I(inode)->xattr_sem);
 }
 
-static inline void
-reiserfs_read_unlock_xattr_i(struct inode *inode)
+static inline void reiserfs_read_unlock_xattr_i(struct inode *inode)
 {
-    up_read (&REISERFS_I(inode)->xattr_sem);
+        up_read(&REISERFS_I(inode)->xattr_sem);
 }
 
-static inline void
-reiserfs_mark_inode_private(struct inode *inode)
+static inline void reiserfs_mark_inode_private(struct inode *inode)
 {
-    inode->i_flags |= S_PRIVATE;
+        inode->i_flags |= S_PRIVATE;
 }
 
 #else
@@ -127,13 +118,20 @@ reiserfs_mark_inode_private(struct inode *inode)
 #define reiserfs_xattr_register_handlers() 0
 #define reiserfs_xattr_unregister_handlers()
 
-static inline int reiserfs_delete_xattrs (struct inode *inode) { return 0; };
-static inline int reiserfs_chown_xattrs (struct inode *inode, struct iattr *attrs) { return 0; };
-static inline int reiserfs_xattr_init (struct super_block *sb, int mount_flags)
+static inline int reiserfs_delete_xattrs(struct inode *inode)
+{
+        return 0;
+};
+static inline int reiserfs_chown_xattrs(struct inode *inode,
+                                        struct iattr *attrs)
+{
+        return 0;
+};
+static inline int reiserfs_xattr_init(struct super_block *sb, int mount_flags)
 {
-    sb->s_flags = (sb->s_flags & ~MS_POSIXACL); /* to be sure */
-    return 0;
+        sb->s_flags = (sb->s_flags & ~MS_POSIXACL);     /* to be sure */
+        return 0;
 };
 #endif
 
-#endif  /* __KERNEL__ */
+#endif                          /* __KERNEL__ */
diff --git a/include/linux/relayfs_fs.h b/include/linux/relayfs_fs.h
new file mode 100644
index 000000000000..cfafc3e76bc2
--- /dev/null
+++ b/include/linux/relayfs_fs.h
@@ -0,0 +1,255 @@
+/*
+ * linux/include/linux/relayfs_fs.h
+ *
+ * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
+ * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
+ *
+ * RelayFS definitions and declarations
+ */
+
+#ifndef _LINUX_RELAYFS_FS_H
+#define _LINUX_RELAYFS_FS_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/fs.h>
+#include <linux/poll.h>
+#include <linux/kref.h>
+
+/*
+ * Tracks changes to rchan_buf struct
+ */
+#define RELAYFS_CHANNEL_VERSION         5
+
+/*
+ * Per-cpu relay channel buffer
+ */
+struct rchan_buf
+{
+        void *start;                    /* start of channel buffer */
+        void *data;                     /* start of current sub-buffer */
+        size_t offset;                  /* current offset into sub-buffer */
+        size_t subbufs_produced;        /* count of sub-buffers produced */
+        size_t subbufs_consumed;        /* count of sub-buffers consumed */
+        struct rchan *chan;             /* associated channel */
+        wait_queue_head_t read_wait;    /* reader wait queue */
+        struct work_struct wake_readers; /* reader wake-up work struct */
+        struct dentry *dentry;          /* channel file dentry */
+        struct kref kref;               /* channel buffer refcount */
+        struct page **page_array;       /* array of current buffer pages */
+        unsigned int page_count;        /* number of current buffer pages */
+        unsigned int finalized;         /* buffer has been finalized */
+        size_t *padding;                /* padding counts per sub-buffer */
+        size_t prev_padding;            /* temporary variable */
+        size_t bytes_consumed;          /* bytes consumed in cur read subbuf */
+        unsigned int cpu;               /* this buf's cpu */
+} ____cacheline_aligned;
+
+/*
+ * Relay channel data structure
+ */
+struct rchan
+{
+        u32 version;                    /* the version of this struct */
+        size_t subbuf_size;             /* sub-buffer size */
+        size_t n_subbufs;               /* number of sub-buffers per buffer */
+        size_t alloc_size;              /* total buffer size allocated */
+        struct rchan_callbacks *cb;     /* client callbacks */
+        struct kref kref;               /* channel refcount */
+        void *private_data;             /* for user-defined data */
+        struct rchan_buf *buf[NR_CPUS]; /* per-cpu channel buffers */
+};
+
+/*
+ * Relayfs inode
+ */
+struct relayfs_inode_info
+{
+        struct inode vfs_inode;
+        struct rchan_buf *buf;
+};
+
+static inline struct relayfs_inode_info *RELAYFS_I(struct inode *inode)
+{
+        return container_of(inode, struct relayfs_inode_info, vfs_inode);
+}
+
+/*
+ * Relay channel client callbacks
+ */
+struct rchan_callbacks
+{
+        /*
+         * subbuf_start - called on buffer-switch to a new sub-buffer
+         * @buf: the channel buffer containing the new sub-buffer
+         * @subbuf: the start of the new sub-buffer
+         * @prev_subbuf: the start of the previous sub-buffer
+         * @prev_padding: unused space at the end of previous sub-buffer
+         *
+         * The client should return 1 to continue logging, 0 to stop
+         * logging.
+         *
+         * NOTE: subbuf_start will also be invoked when the buffer is
+         *       created, so that the first sub-buffer can be initialized
+         *       if necessary.  In this case, prev_subbuf will be NULL.
+         *
+         * NOTE: the client can reserve bytes at the beginning of the new
+         *       sub-buffer by calling subbuf_start_reserve() in this callback.
+         */
+        int (*subbuf_start) (struct rchan_buf *buf,
+                             void *subbuf,
+                             void *prev_subbuf,
+                             size_t prev_padding);
+
+        /*
+         * buf_mapped - relayfs buffer mmap notification
+         * @buf: the channel buffer
+         * @filp: relayfs file pointer
+         *
+         * Called when a relayfs file is successfully mmapped
+         */
+        void (*buf_mapped)(struct rchan_buf *buf,
+                           struct file *filp);
+
+        /*
+         * buf_unmapped - relayfs buffer unmap notification
+         * @buf: the channel buffer
+         * @filp: relayfs file pointer
+         *
+         * Called when a relayfs file is successfully unmapped
+         */
+        void (*buf_unmapped)(struct rchan_buf *buf,
+                             struct file *filp);
+};
+
+/*
+ * relayfs kernel API, fs/relayfs/relay.c
+ */
+
+struct rchan *relay_open(const char *base_filename,
+                         struct dentry *parent,
+                         size_t subbuf_size,
+                         size_t n_subbufs,
+                         struct rchan_callbacks *cb);
+extern void relay_close(struct rchan *chan);
+extern void relay_flush(struct rchan *chan);
+extern void relay_subbufs_consumed(struct rchan *chan,
+                                   unsigned int cpu,
+                                   size_t consumed);
+extern void relay_reset(struct rchan *chan);
+extern int relay_buf_full(struct rchan_buf *buf);
+
+extern size_t relay_switch_subbuf(struct rchan_buf *buf,
+                                  size_t length);
+extern struct dentry *relayfs_create_dir(const char *name,
+                                         struct dentry *parent);
+extern int relayfs_remove_dir(struct dentry *dentry);
+
+/**
+ *      relay_write - write data into the channel
+ *      @chan: relay channel
+ *      @data: data to be written
+ *      @length: number of bytes to write
+ *
+ *      Writes data into the current cpu's channel buffer.
+ *
+ *      Protects the buffer by disabling interrupts.  Use this
+ *      if you might be logging from interrupt context.  Try
+ *      __relay_write() if you know you won't be logging from
+ *      interrupt context.
+ */
+static inline void relay_write(struct rchan *chan,
+                               const void *data,
+                               size_t length)
+{
+        unsigned long flags;
+        struct rchan_buf *buf;
+
+        local_irq_save(flags);
+        buf = chan->buf[smp_processor_id()];
+        if (unlikely(buf->offset + length > chan->subbuf_size))
+                length = relay_switch_subbuf(buf, length);
+        memcpy(buf->data + buf->offset, data, length);
+        buf->offset += length;
+        local_irq_restore(flags);
+}
+
+/**
+ *      __relay_write - write data into the channel
+ *      @chan: relay channel
+ *      @data: data to be written
+ *      @length: number of bytes to write
+ *
+ *      Writes data into the current cpu's channel buffer.
+ *
+ *      Protects the buffer by disabling preemption.  Use
+ *      relay_write() if you might be logging from interrupt
+ *      context.
+ */
+static inline void __relay_write(struct rchan *chan,
+                                 const void *data,
+                                 size_t length)
+{
+        struct rchan_buf *buf;
+
+        buf = chan->buf[get_cpu()];
+        if (unlikely(buf->offset + length > buf->chan->subbuf_size))
+                length = relay_switch_subbuf(buf, length);
+        memcpy(buf->data + buf->offset, data, length);
+        buf->offset += length;
+        put_cpu();
+}
+
+/**
+ *      relay_reserve - reserve slot in channel buffer
+ *      @chan: relay channel
+ *      @length: number of bytes to reserve
+ *
+ *      Returns pointer to reserved slot, NULL if full.
+ *
+ *      Reserves a slot in the current cpu's channel buffer.
+ *      Does not protect the buffer at all - caller must provide
+ *      appropriate synchronization.
+ */
+static inline void *relay_reserve(struct rchan *chan, size_t length)
+{
+        void *reserved;
+        struct rchan_buf *buf = chan->buf[smp_processor_id()];
+
+        if (unlikely(buf->offset + length > buf->chan->subbuf_size)) {
+                length = relay_switch_subbuf(buf, length);
+                if (!length)
+                        return NULL;
+        }
+        reserved = buf->data + buf->offset;
+        buf->offset += length;
+
+        return reserved;
+}
+
+/**
+ *      subbuf_start_reserve - reserve bytes at the start of a sub-buffer
+ *      @buf: relay channel buffer
+ *      @length: number of bytes to reserve
+ *
+ *      Helper function used to reserve bytes at the beginning of
+ *      a sub-buffer in the subbuf_start() callback.
+ */
+static inline void subbuf_start_reserve(struct rchan_buf *buf,
+                                        size_t length)
+{
+        BUG_ON(length >= buf->chan->subbuf_size - 1);
+        buf->offset = length;
+}
+
+/*
+ * exported relayfs file operations, fs/relayfs/inode.c
+ */
+
+extern struct file_operations relayfs_file_operations;
+
+#endif /* _LINUX_RELAYFS_FS_H */
+
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index 11b484e37ac9..e80fb7ee6efd 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -93,6 +93,12 @@ int page_referenced(struct page *, int is_locked, int ignore_token);
 int try_to_unmap(struct page *);
 
 /*
+ * Called from mm/filemap_xip.c to unmap empty zero page
+ */
+pte_t *page_check_address(struct page *, struct mm_struct *, unsigned long);
+
+
+/*
  * Used by swapoff to help locate where page is expected in vma.
  */
 unsigned long page_address_in_vma(struct page *, struct vm_area_struct *);
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index 91ac97c20777..c231e9a08f0b 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -89,6 +89,13 @@ enum {
         RTM_GETANYCAST  = 62,
 #define RTM_GETANYCAST  RTM_GETANYCAST
 
+        RTM_NEWNEIGHTBL = 64,
+#define RTM_NEWNEIGHTBL RTM_NEWNEIGHTBL
+        RTM_GETNEIGHTBL = 66,
+#define RTM_GETNEIGHTBL RTM_GETNEIGHTBL
+        RTM_SETNEIGHTBL,
+#define RTM_SETNEIGHTBL RTM_SETNEIGHTBL
+
         __RTM_MAX,
 #define RTM_MAX         (((__RTM_MAX + 3) & ~3) - 1)
 };
@@ -356,6 +363,8 @@ enum
 struct rta_session
 {
         __u8    proto;
+        __u8    pad1;
+        __u16   pad2;
 
         union {
                 struct {
@@ -493,6 +502,106 @@ struct nda_cacheinfo
         __u32           ndm_refcnt;
 };
 
+
+/*****************************************************************
+ *              Neighbour tables specific messages.
+ *
+ * To retrieve the neighbour tables send RTM_GETNEIGHTBL with the
+ * NLM_F_DUMP flag set. Every neighbour table configuration is
+ * spread over multiple messages to avoid running into message
+ * size limits on systems with many interfaces. The first message
+ * in the sequence transports all not device specific data such as
+ * statistics, configuration, and the default parameter set.
+ * This message is followed by 0..n messages carrying device
+ * specific parameter sets.
+ * Although the ordering should be sufficient, NDTA_NAME can be
+ * used to identify sequences. The initial message can be identified
+ * by checking for NDTA_CONFIG. The device specific messages do
+ * not contain this TLV but have NDTPA_IFINDEX set to the
+ * corresponding interface index.
+ *
+ * To change neighbour table attributes, send RTM_SETNEIGHTBL
+ * with NDTA_NAME set. Changeable attribute include NDTA_THRESH[1-3],
+ * NDTA_GC_INTERVAL, and all TLVs in NDTA_PARMS unless marked
+ * otherwise. Device specific parameter sets can be changed by
+ * setting NDTPA_IFINDEX to the interface index of the corresponding
+ * device.
+ ****/
+
+struct ndt_stats
+{
+        __u64           ndts_allocs;
+        __u64           ndts_destroys;
+        __u64           ndts_hash_grows;
+        __u64           ndts_res_failed;
+        __u64           ndts_lookups;
+        __u64           ndts_hits;
+        __u64           ndts_rcv_probes_mcast;
+        __u64           ndts_rcv_probes_ucast;
+        __u64           ndts_periodic_gc_runs;
+        __u64           ndts_forced_gc_runs;
+};
+
+enum {
+        NDTPA_UNSPEC,
+        NDTPA_IFINDEX,                  /* u32, unchangeable */
+        NDTPA_REFCNT,                   /* u32, read-only */
+        NDTPA_REACHABLE_TIME,           /* u64, read-only, msecs */
+        NDTPA_BASE_REACHABLE_TIME,      /* u64, msecs */
+        NDTPA_RETRANS_TIME,             /* u64, msecs */
+        NDTPA_GC_STALETIME,             /* u64, msecs */
+        NDTPA_DELAY_PROBE_TIME,         /* u64, msecs */
+        NDTPA_QUEUE_LEN,                /* u32 */
+        NDTPA_APP_PROBES,               /* u32 */
+        NDTPA_UCAST_PROBES,             /* u32 */
+        NDTPA_MCAST_PROBES,             /* u32 */
+        NDTPA_ANYCAST_DELAY,            /* u64, msecs */
+        NDTPA_PROXY_DELAY,              /* u64, msecs */
+        NDTPA_PROXY_QLEN,               /* u32 */
+        NDTPA_LOCKTIME,                 /* u64, msecs */
+        __NDTPA_MAX
+};
+#define NDTPA_MAX (__NDTPA_MAX - 1)
+
+struct ndtmsg
+{
+        __u8            ndtm_family;
+        __u8            ndtm_pad1;
+        __u16           ndtm_pad2;
+};
+
+struct ndt_config
+{
+        __u16           ndtc_key_len;
+        __u16           ndtc_entry_size;
+        __u32           ndtc_entries;
+        __u32           ndtc_last_flush;        /* delta to now in msecs */
+        __u32           ndtc_last_rand;         /* delta to now in msecs */
+        __u32           ndtc_hash_rnd;
+        __u32           ndtc_hash_mask;
+        __u32           ndtc_hash_chain_gc;
+        __u32           ndtc_proxy_qlen;
+};
+
+enum {
+        NDTA_UNSPEC,
+        NDTA_NAME,                      /* char *, unchangeable */
+        NDTA_THRESH1,                   /* u32 */
+        NDTA_THRESH2,                   /* u32 */
+        NDTA_THRESH3,                   /* u32 */
+        NDTA_CONFIG,                    /* struct ndt_config, read-only */
+        NDTA_PARMS,                     /* nested TLV NDTPA_* */
+        NDTA_STATS,                     /* struct ndt_stats, read-only */
+        NDTA_GC_INTERVAL,               /* u64, msecs */
+        __NDTA_MAX
+};
+#define NDTA_MAX (__NDTA_MAX - 1)
+
+#define NDTA_RTA(r) ((struct rtattr*)(((char*)(r)) + \
+                     NLMSG_ALIGN(sizeof(struct ndtmsg))))
+#define NDTA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct ndtmsg))
+
+
 /****
  *              General form of address family dependent message.
  ****/
@@ -528,10 +637,13 @@ struct ifinfomsg
 struct prefixmsg
 {
         unsigned char   prefix_family;
+        unsigned char   prefix_pad1;
+        unsigned short  prefix_pad2;
         int             prefix_ifindex;
         unsigned char   prefix_type;
         unsigned char   prefix_len;
         unsigned char   prefix_flags;
+        unsigned char   prefix_pad3;
 };
 
 enum 
@@ -714,9 +826,8 @@ enum
 #define TCA_RTA(r)  ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct tcmsg))))
 #define TCA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct tcmsg))
 
-
-/* RTnetlink multicast groups */
-
+#ifndef __KERNEL__
+/* RTnetlink multicast groups - backwards compatibility for userspace */
 #define RTMGRP_LINK             1
 #define RTMGRP_NOTIFY           2
 #define RTMGRP_NEIGH            4
@@ -735,6 +846,43 @@ enum
 #define RTMGRP_DECnet_ROUTE     0x4000
 
 #define RTMGRP_IPV6_PREFIX      0x20000
+#endif
+
+/* RTnetlink multicast groups */
+enum rtnetlink_groups {
+        RTNLGRP_NONE,
+#define RTNLGRP_NONE            RTNLGRP_NONE
+        RTNLGRP_LINK,
+#define RTNLGRP_LINK            RTNLGRP_LINK
+        RTNLGRP_NOTIFY,
+#define RTNLGRP_NOTIFY          RTNLGRP_NOTIFY
+        RTNLGRP_NEIGH,
+#define RTNLGRP_NEIGH           RTNLGRP_NEIGH
+        RTNLGRP_TC,
+#define RTNLGRP_TC              RTNLGRP_TC
+        RTNLGRP_IPV4_IFADDR,
+#define RTNLGRP_IPV4_IFADDR     RTNLGRP_IPV4_IFADDR
+        RTNLGRP_IPV4_MROUTE,
+#define RTNLGRP_IPV4_MROUTE     RTNLGRP_IPV4_MROUTE
+        RTNLGRP_IPV4_ROUTE,
+#define RTNLGRP_IPV4_ROUTE      RTNLGRP_IPV4_ROUTE
+        RTNLGRP_IPV6_IFADDR,
+#define RTNLGRP_IPV6_IFADDR     RTNLGRP_IPV6_IFADDR
+        RTNLGRP_IPV6_MROUTE,
+#define RTNLGRP_IPV6_MROUTE     RTNLGRP_IPV6_MROUTE
+        RTNLGRP_IPV6_ROUTE,
+#define RTNLGRP_IPV6_ROUTE      RTNLGRP_IPV6_ROUTE
+        RTNLGRP_IPV6_IFINFO,
+#define RTNLGRP_IPV6_IFINFO     RTNLGRP_IPV6_IFINFO
+        RTNLGRP_DECnet_IFADDR,
+#define RTNLGRP_DECnet_IFADDR   RTNLGRP_DECnet_IFADDR
+        RTNLGRP_DECnet_ROUTE,
+#define RTNLGRP_DECnet_ROUTE    RTNLGRP_DECnet_ROUTE
+        RTNLGRP_IPV6_PREFIX,
+#define RTNLGRP_IPV6_PREFIX     RTNLGRP_IPV6_PREFIX
+        __RTNLGRP_MAX
+};
+#define RTNLGRP_MAX     (__RTNLGRP_MAX - 1)
 
 /* TC action piece */
 struct tcamsg
@@ -785,10 +933,84 @@ extern void __rta_fill(struct sk_buff *skb, int attrtype, int attrlen, const voi
                  goto rtattr_failure; \
         __rta_fill(skb, attrtype, attrlen, data); }) 
 
-#define RTA_PUT_NOHDR(skb, attrlen, data) \
+#define RTA_APPEND(skb, attrlen, data) \
 ({      if (unlikely(skb_tailroom(skb) < (int)(attrlen))) \
                 goto rtattr_failure; \
-        memcpy(skb_put(skb, RTA_ALIGN(attrlen)), data, attrlen); })
+        memcpy(skb_put(skb, attrlen), data, attrlen); })
+
+#define RTA_PUT_NOHDR(skb, attrlen, data) \
+({      RTA_APPEND(skb, RTA_ALIGN(attrlen), data); \
+        memset(skb->tail - (RTA_ALIGN(attrlen) - attrlen), 0, \
+               RTA_ALIGN(attrlen) - attrlen); })
+
+#define RTA_PUT_U8(skb, attrtype, value) \
+({      u8 _tmp = (value); \
+        RTA_PUT(skb, attrtype, sizeof(u8), &_tmp); })
+
+#define RTA_PUT_U16(skb, attrtype, value) \
+({      u16 _tmp = (value); \
+        RTA_PUT(skb, attrtype, sizeof(u16), &_tmp); })
+
+#define RTA_PUT_U32(skb, attrtype, value) \
+({      u32 _tmp = (value); \
+        RTA_PUT(skb, attrtype, sizeof(u32), &_tmp); })
+
+#define RTA_PUT_U64(skb, attrtype, value) \
+({      u64 _tmp = (value); \
+        RTA_PUT(skb, attrtype, sizeof(u64), &_tmp); })
+
+#define RTA_PUT_SECS(skb, attrtype, value) \
+        RTA_PUT_U64(skb, attrtype, (value) / HZ)
+
+#define RTA_PUT_MSECS(skb, attrtype, value) \
+        RTA_PUT_U64(skb, attrtype, jiffies_to_msecs(value))
+
+#define RTA_PUT_STRING(skb, attrtype, value) \
+        RTA_PUT(skb, attrtype, strlen(value) + 1, value)
+
+#define RTA_PUT_FLAG(skb, attrtype) \
+        RTA_PUT(skb, attrtype, 0, NULL);
+
+#define RTA_NEST(skb, type) \
+({      struct rtattr *__start = (struct rtattr *) (skb)->tail; \
+        RTA_PUT(skb, type, 0, NULL); \
+        __start;  })
+
+#define RTA_NEST_END(skb, start) \
+({      (start)->rta_len = ((skb)->tail - (unsigned char *) (start)); \
+        (skb)->len; })
+
+#define RTA_NEST_CANCEL(skb, start) \
+({      if (start) \
+                skb_trim(skb, (unsigned char *) (start) - (skb)->data); \
+        -1; })
+
+#define RTA_GET_U8(rta) \
+({      if (!rta || RTA_PAYLOAD(rta) < sizeof(u8)) \
+                goto rtattr_failure; \
+        *(u8 *) RTA_DATA(rta); })
+
+#define RTA_GET_U16(rta) \
+({      if (!rta || RTA_PAYLOAD(rta) < sizeof(u16)) \
+                goto rtattr_failure; \
+        *(u16 *) RTA_DATA(rta); })
+
+#define RTA_GET_U32(rta) \
+({      if (!rta || RTA_PAYLOAD(rta) < sizeof(u32)) \
+                goto rtattr_failure; \
+        *(u32 *) RTA_DATA(rta); })
+
+#define RTA_GET_U64(rta) \
+({      u64 _tmp; \
+        if (!rta || RTA_PAYLOAD(rta) < sizeof(u64)) \
+                goto rtattr_failure; \
+        memcpy(&_tmp, RTA_DATA(rta), sizeof(_tmp)); \
+        _tmp; })
+
+#define RTA_GET_FLAG(rta) (!!(rta))
+
+#define RTA_GET_SECS(rta) ((unsigned long) RTA_GET_U64(rta) * HZ)
+#define RTA_GET_MSECS(rta) (msecs_to_jiffies((unsigned long) RTA_GET_U64(rta)))
                 
 static inline struct rtattr *
 __rta_reserve(struct sk_buff *skb, int attrtype, int attrlen)
@@ -799,6 +1021,7 @@ __rta_reserve(struct sk_buff *skb, int attrtype, int attrlen)
         rta = (struct rtattr*)skb_put(skb, RTA_ALIGN(size));
         rta->rta_type = attrtype;
         rta->rta_len = size;
+        memset(RTA_DATA(rta) + attrlen, 0, RTA_ALIGN(size) - size);
         return rta;
 }
 
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 4dbb109022f3..ea1b5f32ec5c 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -35,6 +35,8 @@
 #include <linux/topology.h>
 #include <linux/seccomp.h>
 
+#include <linux/auxvec.h>       /* For AT_VECTOR_SIZE */
+
 struct exec_domain;
 
 /*
@@ -176,6 +178,23 @@ extern void trap_init(void);
 extern void update_process_times(int user);
 extern void scheduler_tick(void);
 
+#ifdef CONFIG_DETECT_SOFTLOCKUP
+extern void softlockup_tick(struct pt_regs *regs);
+extern void spawn_softlockup_task(void);
+extern void touch_softlockup_watchdog(void);
+#else
+static inline void softlockup_tick(struct pt_regs *regs)
+{
+}
+static inline void spawn_softlockup_task(void)
+{
+}
+static inline void touch_softlockup_watchdog(void)
+{
+}
+#endif
+
+
 /* Attach to any functions which should be ignored in wchan output. */
 #define __sched         __attribute__((__section__(".sched.text")))
 /* Is this address in the __sched functions? */
@@ -201,8 +220,8 @@ extern unsigned long
 arch_get_unmapped_area_topdown(struct file *filp, unsigned long addr,
                           unsigned long len, unsigned long pgoff,
                           unsigned long flags);
-extern void arch_unmap_area(struct vm_area_struct *area);
-extern void arch_unmap_area_topdown(struct vm_area_struct *area);
+extern void arch_unmap_area(struct mm_struct *, unsigned long);
+extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 
 #define set_mm_counter(mm, member, value) (mm)->_##member = (value)
 #define get_mm_counter(mm, member) ((mm)->_##member)
@@ -218,9 +237,10 @@ struct mm_struct {
         unsigned long (*get_unmapped_area) (struct file *filp,
                                 unsigned long addr, unsigned long len,
                                 unsigned long pgoff, unsigned long flags);
-        void (*unmap_area) (struct vm_area_struct *area);
-        unsigned long mmap_base;                /* base of mmap area */
-        unsigned long free_area_cache;          /* first hole */
+        void (*unmap_area) (struct mm_struct *mm, unsigned long addr);
+        unsigned long mmap_base;                /* base of mmap area */
+        unsigned long cached_hole_size;         /* if non-zero, the largest hole below free_area_cache */
+        unsigned long free_area_cache;          /* first hole of size cached_hole_size or larger */
         pgd_t * pgd;
         atomic_t mm_users;                      /* How many users with user space? */
         atomic_t mm_count;                      /* How many references to "struct mm_struct" (users count as 1) */
@@ -243,9 +263,9 @@ struct mm_struct {
         mm_counter_t _rss;
         mm_counter_t _anon_rss;
 
-        unsigned long saved_auxv[42]; /* for /proc/PID/auxv */
+        unsigned long saved_auxv[AT_VECTOR_SIZE]; /* for /proc/PID/auxv */
 
-        unsigned dumpable:1;
+        unsigned dumpable:2;
         cpumask_t cpu_vm_mask;
 
         /* Architecture-specific MM context */
@@ -367,6 +387,11 @@ struct signal_struct {
 #endif
 };
 
+/* Context switch must be unlocked if interrupts are to be enabled */
+#ifdef __ARCH_WANT_INTERRUPTS_ON_CTXSW
+# define __ARCH_WANT_UNLOCKED_CTXSW
+#endif
+
 /*
  * Bits in flags field of signal_struct.
  */
@@ -404,6 +429,10 @@ struct user_struct {
         atomic_t processes;     /* How many processes does this user have? */
         atomic_t files;         /* How many open files does this user have? */
         atomic_t sigpending;    /* How many pending signals does this user have? */
+#ifdef CONFIG_INOTIFY
+        atomic_t inotify_watches; /* How many inotify watches does this user have? */
+        atomic_t inotify_devs;  /* How many inotify devs does this user have opened? */
+#endif
         /* protected by mq_lock */
         unsigned long mq_bytes; /* How many bytes can be allocated to mqueue? */
         unsigned long locked_shm; /* How many pages of mlocked shm ? */
@@ -459,10 +488,11 @@ enum idle_type
 #define SD_LOAD_BALANCE         1       /* Do load balancing on this domain. */
 #define SD_BALANCE_NEWIDLE      2       /* Balance when about to become idle */
 #define SD_BALANCE_EXEC         4       /* Balance on exec */
-#define SD_WAKE_IDLE            8       /* Wake to idle CPU on task wakeup */
-#define SD_WAKE_AFFINE          16      /* Wake task to waking CPU */
-#define SD_WAKE_BALANCE         32      /* Perform balancing at task wakeup */
-#define SD_SHARE_CPUPOWER       64      /* Domain members share cpu power */
+#define SD_BALANCE_FORK         8       /* Balance on fork, clone */
+#define SD_WAKE_IDLE            16      /* Wake to idle CPU on task wakeup */
+#define SD_WAKE_AFFINE          32      /* Wake task to waking CPU */
+#define SD_WAKE_BALANCE         64      /* Perform balancing at task wakeup */
+#define SD_SHARE_CPUPOWER       128     /* Domain members share cpu power */
 
 struct sched_group {
         struct sched_group *next;       /* Must be a circular list */
@@ -487,6 +517,11 @@ struct sched_domain {
         unsigned long long cache_hot_time; /* Task considered cache hot (ns) */
         unsigned int cache_nice_tries;  /* Leave cache hot tasks for # tries */
         unsigned int per_cpu_gain;      /* CPU % gained by adding domain cpus */
+        unsigned int busy_idx;
+        unsigned int idle_idx;
+        unsigned int newidle_idx;
+        unsigned int wake_idx;
+        unsigned int forkexec_idx;
         int flags;                      /* See SD_* */
 
         /* Runtime fields. */
@@ -510,10 +545,16 @@ struct sched_domain {
         unsigned long alb_failed;
         unsigned long alb_pushed;
 
-        /* sched_balance_exec() stats */
-        unsigned long sbe_attempts;
+        /* SD_BALANCE_EXEC stats */
+        unsigned long sbe_cnt;
+        unsigned long sbe_balanced;
         unsigned long sbe_pushed;
 
+        /* SD_BALANCE_FORK stats */
+        unsigned long sbf_cnt;
+        unsigned long sbf_balanced;
+        unsigned long sbf_pushed;
+
         /* try_to_wake_up() stats */
         unsigned long ttwu_wake_remote;
         unsigned long ttwu_move_affine;
@@ -521,13 +562,8 @@ struct sched_domain {
 #endif
 };
 
-#ifdef ARCH_HAS_SCHED_DOMAIN
-/* Useful helpers that arch setup code may use. Defined in kernel/sched.c */
-extern cpumask_t cpu_isolated_map;
-extern void init_sched_build_groups(struct sched_group groups[],
-                                cpumask_t span, int (*group_fn)(int cpu));
-extern void cpu_attach_domain(struct sched_domain *sd, int cpu);
-#endif /* ARCH_HAS_SCHED_DOMAIN */
+extern void partition_sched_domains(cpumask_t *partition1,
+                                    cpumask_t *partition2);
 #endif /* CONFIG_SMP */
 
 
@@ -560,9 +596,10 @@ struct group_info {
                 groups_free(group_info); \
 } while (0)
 
-struct group_info *groups_alloc(int gidsetsize);
-void groups_free(struct group_info *group_info);
-int set_current_groups(struct group_info *group_info);
+extern struct group_info *groups_alloc(int gidsetsize);
+extern void groups_free(struct group_info *group_info);
+extern int set_current_groups(struct group_info *group_info);
+extern int groups_search(struct group_info *group_info, gid_t grp);
 /* access the groups "array" with this macro */
 #define GROUP_AT(gi, i) \
     ((gi)->blocks[(i)/NGROUPS_PER_BLOCK][(i)%NGROUPS_PER_BLOCK])
@@ -580,10 +617,15 @@ struct task_struct {
 
         int lock_depth;         /* BKL lock depth */
 
+#if defined(CONFIG_SMP) && defined(__ARCH_WANT_UNLOCKED_CTXSW)
+        int oncpu;
+#endif
         int prio, static_prio;
         struct list_head run_list;
         prio_array_t *array;
 
+        unsigned short ioprio;
+
         unsigned long sleep_avg;
         unsigned long long timestamp, last_ran;
         unsigned long long sched_time; /* sched_clock time spent running */
@@ -659,6 +701,7 @@ struct task_struct {
         struct user_struct *user;
 #ifdef CONFIG_KEYS
         struct key *thread_keyring;     /* keyring private to this thread */
+        unsigned char jit_keyring;      /* default keyring to attach requested keys to */
 #endif
         int oomkilladj; /* OOM kill score adjustment (bit shift). */
         char comm[TASK_COMM_LEN]; /* executable name excluding path
@@ -701,8 +744,6 @@ struct task_struct {
         spinlock_t alloc_lock;
 /* Protection of proc_dentry: nesting proc_lock, dcache_lock, write_lock_irq(&tasklist_lock); */
         spinlock_t proc_lock;
-/* context-switch lock */
-        spinlock_t switch_lock;
 
 /* journalling filesystem info */
         void *journal_info;
@@ -740,6 +781,7 @@ struct task_struct {
         nodemask_t mems_allowed;
         int cpuset_mems_generation;
 #endif
+        atomic_t fs_excl;       /* holding fs exclusive resources */
 };
 
 static inline pid_t process_group(struct task_struct *tsk)
@@ -909,7 +951,7 @@ extern void FASTCALL(wake_up_new_task(struct task_struct * tsk,
 #else
  static inline void kick_process(struct task_struct *tsk) { }
 #endif
-extern void FASTCALL(sched_fork(task_t * p));
+extern void FASTCALL(sched_fork(task_t * p, int clone_flags));
 extern void FASTCALL(sched_exit(task_t * p));
 
 extern int in_group_p(gid_t);
@@ -1089,7 +1131,8 @@ extern void unhash_process(struct task_struct *p);
 
 /*
  * Protects ->fs, ->files, ->mm, ->ptrace, ->group_info, ->comm, keyring
- * subscriptions and synchronises with wait4().  Also used in procfs.
+ * subscriptions and synchronises with wait4().  Also used in procfs.  Also
+ * pins the final release of task.io_context.
  *
  * Nests both inside and outside of read_lock(&tasklist_lock).
  * It must not be nested with write_lock_irq(&tasklist_lock),
@@ -1242,33 +1285,78 @@ extern void normalize_rt_tasks(void);
 
 #endif
 
-/* try_to_freeze
- *
- * Checks whether we need to enter the refrigerator
- * and returns 1 if we did so.
- */
 #ifdef CONFIG_PM
-extern void refrigerator(unsigned long);
+/*
+ * Check if a process has been frozen
+ */
+static inline int frozen(struct task_struct *p)
+{
+        return p->flags & PF_FROZEN;
+}
+
+/*
+ * Check if there is a request to freeze a process
+ */
+static inline int freezing(struct task_struct *p)
+{
+        return p->flags & PF_FREEZE;
+}
+
+/*
+ * Request that a process be frozen
+ * FIXME: SMP problem. We may not modify other process' flags!
+ */
+static inline void freeze(struct task_struct *p)
+{
+        p->flags |= PF_FREEZE;
+}
+
+/*
+ * Wake up a frozen process
+ */
+static inline int thaw_process(struct task_struct *p)
+{
+        if (frozen(p)) {
+                p->flags &= ~PF_FROZEN;
+                wake_up_process(p);
+                return 1;
+        }
+        return 0;
+}
+
+/*
+ * freezing is complete, mark process as frozen
+ */
+static inline void frozen_process(struct task_struct *p)
+{
+        p->flags = (p->flags & ~PF_FREEZE) | PF_FROZEN;
+}
+
+extern void refrigerator(void);
 extern int freeze_processes(void);
 extern void thaw_processes(void);
 
-static inline int try_to_freeze(unsigned long refrigerator_flags)
+static inline int try_to_freeze(void)
 {
-        if (unlikely(current->flags & PF_FREEZE)) {
-                refrigerator(refrigerator_flags);
+        if (freezing(current)) {
+                refrigerator();
                 return 1;
         } else
                 return 0;
 }
 #else
-static inline void refrigerator(unsigned long flag) {}
+static inline int frozen(struct task_struct *p) { return 0; }
+static inline int freezing(struct task_struct *p) { return 0; }
+static inline void freeze(struct task_struct *p) { BUG(); }
+static inline int thaw_process(struct task_struct *p) { return 1; }
+static inline void frozen_process(struct task_struct *p) { BUG(); }
+
+static inline void refrigerator(void) {}
 static inline int freeze_processes(void) { BUG(); return 0; }
 static inline void thaw_processes(void) {}
 
-static inline int try_to_freeze(unsigned long refrigerator_flags)
-{
-        return 0;
-}
+static inline int try_to_freeze(void) { return 0; }
+
 #endif /* CONFIG_PM */
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/seccomp.h b/include/linux/seccomp.h
index 3a2702bbb1d6..dc89116bb1ca 100644
--- a/include/linux/seccomp.h
+++ b/include/linux/seccomp.h
@@ -19,6 +19,11 @@ static inline void secure_computing(int this_syscall)
                 __secure_computing(this_syscall);
 }
 
+static inline int has_secure_computing(struct thread_info *ti)
+{
+        return unlikely(test_ti_thread_flag(ti, TIF_SECCOMP));
+}
+
 #else /* CONFIG_SECCOMP */
 
 #if (__GNUC__ > 2)
@@ -28,6 +33,11 @@ static inline void secure_computing(int this_syscall)
 #endif
 
 #define secure_computing(x) do { } while (0)
+/* static inline to preserve typechecking */
+static inline int has_secure_computing(struct thread_info *ti)
+{
+        return 0;
+}
 
 #endif /* CONFIG_SECCOMP */
 
diff --git a/include/linux/security.h b/include/linux/security.h
index b42095a68b1c..7aab6ab7c57f 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -2727,7 +2727,8 @@ static inline int security_socket_getpeersec(struct socket *sock, char __user *o
         return security_ops->socket_getpeersec(sock, optval, optlen, len);
 }
 
-static inline int security_sk_alloc(struct sock *sk, int family, int priority)
+static inline int security_sk_alloc(struct sock *sk, int family,
+                                    unsigned int __nocast priority)
 {
         return security_ops->sk_alloc_security(sk, family, priority);
 }
@@ -2844,7 +2845,8 @@ static inline int security_socket_getpeersec(struct socket *sock, char __user *o
         return -ENOPROTOOPT;
 }
 
-static inline int security_sk_alloc(struct sock *sk, int family, int priority)
+static inline int security_sk_alloc(struct sock *sk, int family,
+                                    unsigned int __nocast priority)
 {
         return 0;
 }
diff --git a/include/linux/selinux_netlink.h b/include/linux/selinux_netlink.h
index 957e6ebca4e6..bbf489decd84 100644
--- a/include/linux/selinux_netlink.h
+++ b/include/linux/selinux_netlink.h
@@ -20,10 +20,21 @@ enum {
         SELNL_MSG_MAX
 };
 
-/* Multicast groups */
+#ifndef __KERNEL__
+/* Multicast groups - backwards compatiblility for userspace */
 #define SELNL_GRP_NONE          0x00000000
 #define SELNL_GRP_AVC           0x00000001      /* AVC notifications */
 #define SELNL_GRP_ALL           0xffffffff
+#endif
+
+enum selinux_nlgroups {
+        SELNLGRP_NONE,
+#define SELNLGRP_NONE   SELNLGRP_NONE
+        SELNLGRP_AVC,
+#define SELNLGRP_AVC    SELNLGRP_AVC
+        __SELNLGRP_MAX
+};
+#define SELNLGRP_MAX    (__SELNLGRP_MAX - 1)
 
 /* Message structures */
 struct selnl_msg_setenforce {
diff --git a/include/linux/sem.h b/include/linux/sem.h
index 2d8516be9fd7..106f9757339a 100644
--- a/include/linux/sem.h
+++ b/include/linux/sem.h
@@ -88,6 +88,7 @@ struct sem {
 /* One sem_array data structure for each set of semaphores in the system. */
 struct sem_array {
         struct kern_ipc_perm    sem_perm;       /* permissions .. see ipc.h */
+        int                     sem_id;
         time_t                  sem_otime;      /* last semop time */
         time_t                  sem_ctime;      /* last change time */
         struct sem              *sem_base;      /* ptr to first semaphore in array */
diff --git a/include/linux/serial.h b/include/linux/serial.h
index 00145822fb74..12cd9cf65e8f 100644
--- a/include/linux/serial.h
+++ b/include/linux/serial.h
@@ -174,9 +174,7 @@ struct serial_icounter_struct {
 
 
 #ifdef __KERNEL__
-/* Export to allow PCMCIA to use this - Dave Hinds */
-extern int register_serial(struct serial_struct *req);
-extern void unregister_serial(int line);
+#include <linux/compiler.h>
 
 /* Allow architectures to override entries in serial8250_ports[] at run time: */
 struct uart_port;       /* forward declaration */
diff --git a/include/linux/serialP.h b/include/linux/serialP.h
index 2307f11d8a6b..2b9e6b9554d5 100644
--- a/include/linux/serialP.h
+++ b/include/linux/serialP.h
@@ -19,7 +19,6 @@
  * For definitions of the flags field, see tty.h
  */
 
-#include <linux/version.h>
 #include <linux/config.h>
 #include <linux/termios.h>
 #include <linux/workqueue.h>
@@ -141,44 +140,4 @@ struct rs_multiport_struct {
 #define ALPHA_KLUDGE_MCR 0
 #endif
 
-/*
- * Definitions for PCI support.
- */
-#define SPCI_FL_BASE_MASK       0x0007
-#define SPCI_FL_BASE0   0x0000
-#define SPCI_FL_BASE1   0x0001
-#define SPCI_FL_BASE2   0x0002
-#define SPCI_FL_BASE3   0x0003
-#define SPCI_FL_BASE4   0x0004
-#define SPCI_FL_GET_BASE(x)     (x & SPCI_FL_BASE_MASK)
-
-#define SPCI_FL_IRQ_MASK       (0x0007 << 4)
-#define SPCI_FL_IRQBASE0       (0x0000 << 4)
-#define SPCI_FL_IRQBASE1       (0x0001 << 4)
-#define SPCI_FL_IRQBASE2       (0x0002 << 4)
-#define SPCI_FL_IRQBASE3       (0x0003 << 4)
-#define SPCI_FL_IRQBASE4       (0x0004 << 4)
-#define SPCI_FL_GET_IRQBASE(x)        ((x & SPCI_FL_IRQ_MASK) >> 4)
-
-/* Use successive BARs (PCI base address registers), 
-   else use offset into some specified BAR */
-#define SPCI_FL_BASE_TABLE      0x0100
-
-/* Use successive entries in the irq resource table */
-#define SPCI_FL_IRQ_TABLE       0x0200
-
-/* Use the irq resource table instead of dev->irq */
-#define SPCI_FL_IRQRESOURCE     0x0400
-
-/* Use the Base address register size to cap number of ports */
-#define SPCI_FL_REGION_SZ_CAP   0x0800
-
-/* Do not use irq sharing for this device */
-#define SPCI_FL_NO_SHIRQ        0x1000
-
-/* This is a PNP device */
-#define SPCI_FL_ISPNP           0x2000
-
-#define SPCI_FL_PNPDEFAULT      (SPCI_FL_IRQRESOURCE|SPCI_FL_ISPNP)
-
 #endif /* _LINUX_SERIAL_H */
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index 823181af6ddf..317a979b24de 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -14,6 +14,9 @@
 #include <linux/serial_core.h>
 #include <linux/device.h>
 
+/*
+ * This is the platform device platform_data structure
+ */
 struct plat_serial8250_port {
         unsigned long   iobase;         /* io base address */
         void __iomem    *membase;       /* ioremap cookie or NULL */
@@ -22,7 +25,36 @@ struct plat_serial8250_port {
         unsigned int    uartclk;        /* UART clock rate */
         unsigned char   regshift;       /* register shift */
         unsigned char   iotype;         /* UPIO_* */
+        unsigned char   hub6;
         unsigned int    flags;          /* UPF_* flags */
 };
 
+/*
+ * Allocate 8250 platform device IDs.  Nothing is implied by
+ * the numbering here, except for the legacy entry being -1.
+ */
+enum {
+        PLAT8250_DEV_LEGACY = -1,
+        PLAT8250_DEV_PLATFORM,
+        PLAT8250_DEV_PLATFORM1,
+        PLAT8250_DEV_FOURPORT,
+        PLAT8250_DEV_ACCENT,
+        PLAT8250_DEV_BOCA,
+        PLAT8250_DEV_HUB6,
+        PLAT8250_DEV_MCA,
+};
+
+/*
+ * This should be used by drivers which want to register
+ * their own 8250 ports without registering their own
+ * platform device.  Using these will make your driver
+ * dependent on the 8250 driver.
+ */
+struct uart_port;
+
+int serial8250_register_port(struct uart_port *);
+void serial8250_unregister_port(int line);
+void serial8250_suspend_port(int line);
+void serial8250_resume_port(int line);
+
 #endif
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index d6025af7efac..27db8da43aa4 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -104,7 +104,7 @@
 #define PORT_MPSC       63
 
 /* TXX9 type number */
-#define PORT_TXX9       64
+#define PORT_TXX9       64
 
 /* NEC VR4100 series SIU/DSIU */
 #define PORT_VR41XX_SIU         65
@@ -122,6 +122,7 @@
 #ifdef __KERNEL__
 
 #include <linux/config.h>
+#include <linux/compiler.h>
 #include <linux/interrupt.h>
 #include <linux/circ_buf.h>
 #include <linux/spinlock.h>
@@ -141,8 +142,8 @@ struct uart_ops {
         unsigned int    (*tx_empty)(struct uart_port *);
         void            (*set_mctrl)(struct uart_port *, unsigned int mctrl);
         unsigned int    (*get_mctrl)(struct uart_port *);
-        void            (*stop_tx)(struct uart_port *, unsigned int tty_stop);
-        void            (*start_tx)(struct uart_port *, unsigned int tty_start);
+        void            (*stop_tx)(struct uart_port *);
+        void            (*start_tx)(struct uart_port *);
         void            (*send_xchar)(struct uart_port *, char ch);
         void            (*stop_rx)(struct uart_port *);
         void            (*enable_ms)(struct uart_port *);
@@ -359,8 +360,6 @@ struct tty_driver *uart_console_device(struct console *co, int *index);
  */
 int uart_register_driver(struct uart_driver *uart);
 void uart_unregister_driver(struct uart_driver *uart);
-void uart_unregister_port(struct uart_driver *reg, int line);
-int uart_register_port(struct uart_driver *reg, struct uart_port *port);
 int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
 int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
 int uart_match_port(struct uart_port *port1, struct uart_port *port2);
@@ -386,11 +385,11 @@ int uart_resume_port(struct uart_driver *reg, struct uart_port *port);
 /*
  * The following are helper functions for the low level drivers.
  */
-#ifdef SUPPORT_SYSRQ
 static inline int
 uart_handle_sysrq_char(struct uart_port *port, unsigned int ch,
                        struct pt_regs *regs)
 {
+#ifdef SUPPORT_SYSRQ
         if (port->sysrq) {
                 if (ch && time_before(jiffies, port->sysrq)) {
                         handle_sysrq(ch, regs, NULL);
@@ -399,10 +398,11 @@ uart_handle_sysrq_char(struct uart_port *port, unsigned int ch,
                 }
                 port->sysrq = 0;
         }
+#endif
         return 0;
 }
-#else
-#define uart_handle_sysrq_char(port,ch,regs)    (0)
+#ifndef SUPPORT_SYSRQ
+#define uart_handle_sysrq_char(port,ch,regs) uart_handle_sysrq_char(port, 0, NULL)
 #endif
 
 /*
@@ -467,13 +467,13 @@ uart_handle_cts_change(struct uart_port *port, unsigned int status)
                 if (tty->hw_stopped) {
                         if (status) {
                                 tty->hw_stopped = 0;
-                                port->ops->start_tx(port, 0);
+                                port->ops->start_tx(port);
                                 uart_write_wakeup(port);
                         }
                 } else {
                         if (!status) {
                                 tty->hw_stopped = 1;
-                                port->ops->stop_tx(port, 0);
+                                port->ops->stop_tx(port);
                         }
                 }
         }
diff --git a/include/linux/serio.h b/include/linux/serio.h
index a2d3b9ae06f4..aa4d6493a034 100644
--- a/include/linux/serio.h
+++ b/include/linux/serio.h
@@ -83,6 +83,7 @@ static inline void serio_register_port(struct serio *serio)
 }
 
 void serio_unregister_port(struct serio *serio);
+void serio_unregister_child_port(struct serio *serio);
 void __serio_unregister_port_delayed(struct serio *serio, struct module *owner);
 static inline void serio_unregister_port_delayed(struct serio *serio)
 {
@@ -153,6 +154,11 @@ static inline int serio_pin_driver(struct serio *serio)
         return down_interruptible(&serio->drv_sem);
 }
 
+static inline void serio_pin_driver_uninterruptible(struct serio *serio)
+{
+        down(&serio->drv_sem);
+}
+
 static inline void serio_unpin_driver(struct serio *serio)
 {
         up(&serio->drv_sem);
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index cc04f5cd2286..da7da9c0ed1b 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -27,6 +27,7 @@
 #include <linux/highmem.h>
 #include <linux/poll.h>
 #include <linux/net.h>
+#include <linux/textsearch.h>
 #include <net/checksum.h>
 
 #define HAVE_ALLOC_SKB          /* For the drivers to know */
@@ -154,16 +155,29 @@ struct skb_shared_info {
 #define SKB_DATAREF_SHIFT 16
 #define SKB_DATAREF_MASK ((1 << SKB_DATAREF_SHIFT) - 1)
 
+extern struct timeval skb_tv_base;
+
+struct skb_timeval {
+        u32     off_sec;
+        u32     off_usec;
+};
+
+
+enum {
+        SKB_FCLONE_UNAVAILABLE,
+        SKB_FCLONE_ORIG,
+        SKB_FCLONE_CLONE,
+};
+
 /** 
  *      struct sk_buff - socket buffer
  *      @next: Next buffer in list
  *      @prev: Previous buffer in list
  *      @list: List we are on
  *      @sk: Socket we are owned by
- *      @stamp: Time we arrived
+ *      @tstamp: Time we arrived stored as offset to skb_tv_base
  *      @dev: Device we arrived on/are leaving by
  *      @input_dev: Device we arrived on
- *      @real_dev: The real device we are using
  *      @h: Transport layer header
  *      @nh: Network layer header
  *      @mac: Link layer header
@@ -182,7 +196,6 @@ struct skb_shared_info {
  *      @priority: Packet queueing priority
  *      @users: User count - see {datagram,tcp}.c
  *      @protocol: Packet protocol from driver
- *      @security: Security level of packet
  *      @truesize: Buffer size 
  *      @head: Head of buffer
  *      @data: Data head pointer
@@ -190,15 +203,11 @@ struct skb_shared_info {
  *      @end: End pointer
  *      @destructor: Destruct function
  *      @nfmark: Can be used for communication between hooks
- *      @nfcache: Cache info
  *      @nfct: Associated connection, if any
  *      @nfctinfo: Relationship of this skb to the connection
- *      @nf_debug: Netfilter debugging
  *      @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
- *      @private: Data which is private to the HIPPI implementation
  *      @tc_index: Traffic control index
  *      @tc_verd: traffic control verdict
- *      @tc_classid: traffic control classid
  */
 
 struct sk_buff {
@@ -206,12 +215,10 @@ struct sk_buff {
         struct sk_buff          *next;
         struct sk_buff          *prev;
 
-        struct sk_buff_head     *list;
         struct sock             *sk;
-        struct timeval          stamp;
+        struct skb_timeval      tstamp;
         struct net_device       *dev;
         struct net_device       *input_dev;
-        struct net_device       *real_dev;
 
         union {
                 struct tcphdr   *th;
@@ -249,40 +256,32 @@ struct sk_buff {
                                 data_len,
                                 mac_len,
                                 csum;
-        unsigned char           local_df,
+        __u32                   priority;
+        __u8                    local_df:1,
                                 cloned:1,
+                                ip_summed:2,
                                 nohdr:1,
-                                pkt_type,
-                                ip_summed;
-        __u32                   priority;
-        unsigned short          protocol,
-                                security;
+                                nfctinfo:3;
+        __u8                    pkt_type:3,
+                                fclone:2;
+        __be16                  protocol;
 
         void                    (*destructor)(struct sk_buff *skb);
 #ifdef CONFIG_NETFILTER
-        unsigned long           nfmark;
-        __u32                   nfcache;
-        __u32                   nfctinfo;
+        __u32                   nfmark;
         struct nf_conntrack     *nfct;
-#ifdef CONFIG_NETFILTER_DEBUG
-        unsigned int            nf_debug;
+#if defined(CONFIG_IP_VS) || defined(CONFIG_IP_VS_MODULE)
+        __u8                    ipvs_property:1;
 #endif
 #ifdef CONFIG_BRIDGE_NETFILTER
         struct nf_bridge_info   *nf_bridge;
 #endif
 #endif /* CONFIG_NETFILTER */
-#if defined(CONFIG_HIPPI)
-        union {
-                __u32           ifield;
-        } private;
-#endif
 #ifdef CONFIG_NET_SCHED
-       __u32                    tc_index;        /* traffic control index */
+        __u16                   tc_index;       /* traffic control index */
 #ifdef CONFIG_NET_CLS_ACT
-        __u32           tc_verd;               /* traffic control verdict */
-        __u32           tc_classid;            /* traffic control classid */
+        __u16                   tc_verd;        /* traffic control verdict */
 #endif
-
 #endif
 
 
@@ -304,20 +303,38 @@ struct sk_buff {
 #include <asm/system.h>
 
 extern void            __kfree_skb(struct sk_buff *skb);
-extern struct sk_buff *alloc_skb(unsigned int size, int priority);
+extern struct sk_buff *__alloc_skb(unsigned int size,
+                                   unsigned int __nocast priority, int fclone);
+static inline struct sk_buff *alloc_skb(unsigned int size,
+                                        unsigned int __nocast priority)
+{
+        return __alloc_skb(size, priority, 0);
+}
+
+static inline struct sk_buff *alloc_skb_fclone(unsigned int size,
+                                               unsigned int __nocast priority)
+{
+        return __alloc_skb(size, priority, 1);
+}
+
 extern struct sk_buff *alloc_skb_from_cache(kmem_cache_t *cp,
-                                            unsigned int size, int priority);
+                                            unsigned int size,
+                                            unsigned int __nocast priority);
 extern void            kfree_skbmem(struct sk_buff *skb);
-extern struct sk_buff *skb_clone(struct sk_buff *skb, int priority);
-extern struct sk_buff *skb_copy(const struct sk_buff *skb, int priority);
-extern struct sk_buff *pskb_copy(struct sk_buff *skb, int gfp_mask);
+extern struct sk_buff *skb_clone(struct sk_buff *skb,
+                                 unsigned int __nocast priority);
+extern struct sk_buff *skb_copy(const struct sk_buff *skb,
+                                unsigned int __nocast priority);
+extern struct sk_buff *pskb_copy(struct sk_buff *skb,
+                                 unsigned int __nocast gfp_mask);
 extern int             pskb_expand_head(struct sk_buff *skb,
-                                        int nhead, int ntail, int gfp_mask);
+                                        int nhead, int ntail,
+                                        unsigned int __nocast gfp_mask);
 extern struct sk_buff *skb_realloc_headroom(struct sk_buff *skb,
                                             unsigned int headroom);
 extern struct sk_buff *skb_copy_expand(const struct sk_buff *skb,
                                        int newheadroom, int newtailroom,
-                                       int priority);
+                                       unsigned int __nocast priority);
 extern struct sk_buff *         skb_pad(struct sk_buff *skb, int pad);
 #define dev_kfree_skb(a)        kfree_skb(a)
 extern void           skb_over_panic(struct sk_buff *skb, int len,
@@ -325,6 +342,28 @@ extern void	      skb_over_panic(struct sk_buff *skb, int len,
 extern void           skb_under_panic(struct sk_buff *skb, int len,
                                       void *here);
 
+struct skb_seq_state
+{
+        __u32           lower_offset;
+        __u32           upper_offset;
+        __u32           frag_idx;
+        __u32           stepped_offset;
+        struct sk_buff  *root_skb;
+        struct sk_buff  *cur_skb;
+        __u8            *frag_data;
+};
+
+extern void           skb_prepare_seq_read(struct sk_buff *skb,
+                                           unsigned int from, unsigned int to,
+                                           struct skb_seq_state *st);
+extern unsigned int   skb_seq_read(unsigned int consumed, const u8 **data,
+                                   struct skb_seq_state *st);
+extern void           skb_abort_seq_read(struct skb_seq_state *st);
+
+extern unsigned int   skb_find_text(struct sk_buff *skb, unsigned int from,
+                                    unsigned int to, struct ts_config *config,
+                                    struct ts_state *state);
+
 /* Internal */
 #define skb_shinfo(SKB)         ((struct skb_shared_info *)((SKB)->end))
 
@@ -446,7 +485,8 @@ static inline int skb_shared(const struct sk_buff *skb)
  *
  *      NULL is returned on a memory allocation failure.
  */
-static inline struct sk_buff *skb_share_check(struct sk_buff *skb, int pri)
+static inline struct sk_buff *skb_share_check(struct sk_buff *skb,
+                                              unsigned int __nocast pri)
 {
         might_sleep_if(pri & __GFP_WAIT);
         if (skb_shared(skb)) {
@@ -477,7 +517,8 @@ static inline struct sk_buff *skb_share_check(struct sk_buff *skb, int pri)
  *
  *      %NULL is returned on a memory allocation failure.
  */
-static inline struct sk_buff *skb_unshare(struct sk_buff *skb, int pri)
+static inline struct sk_buff *skb_unshare(struct sk_buff *skb,
+                                          unsigned int __nocast pri)
 {
         might_sleep_if(pri & __GFP_WAIT);
         if (skb_cloned(skb)) {
@@ -571,7 +612,6 @@ static inline void __skb_queue_head(struct sk_buff_head *list,
 {
         struct sk_buff *prev, *next;
 
-        newsk->list = list;
         list->qlen++;
         prev = (struct sk_buff *)list;
         next = prev->next;
@@ -596,7 +636,6 @@ static inline void __skb_queue_tail(struct sk_buff_head *list,
 {
         struct sk_buff *prev, *next;
 
-        newsk->list = list;
         list->qlen++;
         next = (struct sk_buff *)list;
         prev = next->prev;
@@ -629,7 +668,6 @@ static inline struct sk_buff *__skb_dequeue(struct sk_buff_head *list)
                 next->prev   = prev;
                 prev->next   = next;
                 result->next = result->prev = NULL;
-                result->list = NULL;
         }
         return result;
 }
@@ -638,7 +676,7 @@ static inline struct sk_buff *__skb_dequeue(struct sk_buff_head *list)
 /*
  *      Insert a packet on a list.
  */
-extern void        skb_insert(struct sk_buff *old, struct sk_buff *newsk);
+extern void        skb_insert(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list);
 static inline void __skb_insert(struct sk_buff *newsk,
                                 struct sk_buff *prev, struct sk_buff *next,
                                 struct sk_buff_head *list)
@@ -646,24 +684,23 @@ static inline void __skb_insert(struct sk_buff *newsk,
         newsk->next = next;
         newsk->prev = prev;
         next->prev  = prev->next = newsk;
-        newsk->list = list;
         list->qlen++;
 }
 
 /*
  *      Place a packet after a given packet in a list.
  */
-extern void        skb_append(struct sk_buff *old, struct sk_buff *newsk);
-static inline void __skb_append(struct sk_buff *old, struct sk_buff *newsk)
+extern void        skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list);
+static inline void __skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list)
 {
-        __skb_insert(newsk, old, old->next, old->list);
+        __skb_insert(newsk, old, old->next, list);
 }
 
 /*
  * remove sk_buff from list. _Must_ be called atomically, and with
  * the list known..
  */
-extern void        skb_unlink(struct sk_buff *skb);
+extern void        skb_unlink(struct sk_buff *skb, struct sk_buff_head *list);
 static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
 {
         struct sk_buff *next, *prev;
@@ -672,7 +709,6 @@ static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
         next       = skb->next;
         prev       = skb->prev;
         skb->next  = skb->prev = NULL;
-        skb->list  = NULL;
         next->prev = prev;
         prev->next = next;
 }
@@ -983,7 +1019,7 @@ static inline void __skb_queue_purge(struct sk_buff_head *list)
  *      %NULL is returned in there is no free memory.
  */
 static inline struct sk_buff *__dev_alloc_skb(unsigned int length,
-                                              int gfp_mask)
+                                              unsigned int __nocast gfp_mask)
 {
         struct sk_buff *skb = alloc_skb(length + 16, gfp_mask);
         if (likely(skb))
@@ -1096,8 +1132,8 @@ static inline int skb_can_coalesce(struct sk_buff *skb, int i,
  *      If there is no free memory -ENOMEM is returned, otherwise zero
  *      is returned and the old skb data released.
  */
-extern int __skb_linearize(struct sk_buff *skb, int gfp);
-static inline int skb_linearize(struct sk_buff *skb, int gfp)
+extern int __skb_linearize(struct sk_buff *skb, unsigned int __nocast gfp);
+static inline int skb_linearize(struct sk_buff *skb, unsigned int __nocast gfp)
 {
         return __skb_linearize(skb, gfp);
 }
@@ -1187,12 +1223,14 @@ extern void	       skb_copy_and_csum_dev(const struct sk_buff *skb, u8 *to);
 extern void            skb_split(struct sk_buff *skb,
                                  struct sk_buff *skb1, const u32 len);
 
+extern void            skb_release_data(struct sk_buff *skb);
+
 static inline void *skb_header_pointer(const struct sk_buff *skb, int offset,
                                        int len, void *buffer)
 {
         int hlen = skb_headlen(skb);
 
-        if (offset + len <= hlen)
+        if (hlen - offset >= len)
                 return skb->data + offset;
 
         if (skb_copy_bits(skb, offset, buffer, len) < 0)
@@ -1204,6 +1242,42 @@ static inline void *skb_header_pointer(const struct sk_buff *skb, int offset,
 extern void skb_init(void);
 extern void skb_add_mtu(int mtu);
 
+/**
+ *      skb_get_timestamp - get timestamp from a skb
+ *      @skb: skb to get stamp from
+ *      @stamp: pointer to struct timeval to store stamp in
+ *
+ *      Timestamps are stored in the skb as offsets to a base timestamp.
+ *      This function converts the offset back to a struct timeval and stores
+ *      it in stamp.
+ */
+static inline void skb_get_timestamp(const struct sk_buff *skb, struct timeval *stamp)
+{
+        stamp->tv_sec  = skb->tstamp.off_sec;
+        stamp->tv_usec = skb->tstamp.off_usec;
+        if (skb->tstamp.off_sec) {
+                stamp->tv_sec  += skb_tv_base.tv_sec;
+                stamp->tv_usec += skb_tv_base.tv_usec;
+        }
+}
+
+/**
+ *      skb_set_timestamp - set timestamp of a skb
+ *      @skb: skb to set stamp of
+ *      @stamp: pointer to struct timeval to get stamp from
+ *
+ *      Timestamps are stored in the skb as offsets to a base timestamp.
+ *      This function converts a struct timeval to an offset and stores
+ *      it in the skb.
+ */
+static inline void skb_set_timestamp(struct sk_buff *skb, const struct timeval *stamp)
+{
+        skb->tstamp.off_sec  = stamp->tv_sec - skb_tv_base.tv_sec;
+        skb->tstamp.off_usec = stamp->tv_usec - skb_tv_base.tv_usec;
+}
+
+extern void __net_timestamp(struct sk_buff *skb);
+
 #ifdef CONFIG_NETFILTER
 static inline void nf_conntrack_put(struct nf_conntrack *nfct)
 {
@@ -1219,15 +1293,6 @@ static inline void nf_reset(struct sk_buff *skb)
 {
         nf_conntrack_put(skb->nfct);
         skb->nfct = NULL;
-#ifdef CONFIG_NETFILTER_DEBUG
-        skb->nf_debug = 0;
-#endif
-}
-static inline void nf_reset_debug(struct sk_buff *skb)
-{
-#ifdef CONFIG_NETFILTER_DEBUG
-        skb->nf_debug = 0;
-#endif
 }
 
 #ifdef CONFIG_BRIDGE_NETFILTER
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 7d66385ae750..42a6bea58af3 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -64,7 +64,8 @@ extern int kmem_cache_shrink(kmem_cache_t *);
 extern void *kmem_cache_alloc(kmem_cache_t *, unsigned int __nocast);
 extern void kmem_cache_free(kmem_cache_t *, void *);
 extern unsigned int kmem_cache_size(kmem_cache_t *);
-extern kmem_cache_t *kmem_find_general_cachep(size_t size, int gfpflags);
+extern const char *kmem_cache_name(kmem_cache_t *);
+extern kmem_cache_t *kmem_find_general_cachep(size_t size, unsigned int __nocast gfpflags);
 
 /* Size description struct for general caches. */
 struct cache_sizes {
@@ -98,19 +99,33 @@ found:
         return __kmalloc(size, flags);
 }
 
-extern void *kcalloc(size_t, size_t, unsigned int __nocast);
+extern void *kzalloc(size_t, unsigned int __nocast);
+
+/**
+ * kcalloc - allocate memory for an array. The memory is set to zero.
+ * @n: number of elements.
+ * @size: element size.
+ * @flags: the type of memory to allocate.
+ */
+static inline void *kcalloc(size_t n, size_t size, unsigned int __nocast flags)
+{
+        if (n != 0 && size > INT_MAX / n)
+                return NULL;
+        return kzalloc(n * size, flags);
+}
+
 extern void kfree(const void *);
 extern unsigned int ksize(const void *);
 
 #ifdef CONFIG_NUMA
 extern void *kmem_cache_alloc_node(kmem_cache_t *, int flags, int node);
-extern void *kmalloc_node(size_t size, int flags, int node);
+extern void *kmalloc_node(size_t size, unsigned int __nocast flags, int node);
 #else
 static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int node)
 {
         return kmem_cache_alloc(cachep, flags);
 }
-static inline void *kmalloc_node(size_t size, int flags, int node)
+static inline void *kmalloc_node(size_t size, unsigned int __nocast flags, int node)
 {
         return kmalloc(size, flags);
 }
diff --git a/include/linux/smp.h b/include/linux/smp.h
index dcf1db3b35d3..9dfa3ee769ae 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -92,10 +92,7 @@ void smp_prepare_boot_cpu(void);
 /*
  *      These macros fold the SMP functionality into a single CPU system
  */
-
-#if !defined(__smp_processor_id) || !defined(CONFIG_PREEMPT)
-# define smp_processor_id()                     0
-#endif
+#define raw_smp_processor_id()                  0
 #define hard_smp_processor_id()                 0
 #define smp_call_function(func,info,retry,wait) ({ 0; })
 #define on_each_cpu(func,info,retry,wait)       ({ func(info); 0; })
@@ -106,30 +103,25 @@ static inline void smp_send_reschedule(int cpu) { }
 #endif /* !SMP */
 
 /*
- * DEBUG_PREEMPT support: check whether smp_processor_id() is being
- * used in a preemption-safe way.
+ * smp_processor_id(): get the current CPU ID.
  *
- * An architecture has to enable this debugging code explicitly.
- * It can do so by renaming the smp_processor_id() macro to
- * __smp_processor_id().  This should only be done after some minimal
- * testing, because usually there are a number of false positives
- * that an architecture will trigger.
+ * if DEBUG_PREEMPT is enabled the we check whether it is
+ * used in a preemption-safe way. (smp_processor_id() is safe
+ * if it's used in a preemption-off critical section, or in
+ * a thread that is bound to the current CPU.)
  *
- * To fix a false positive (i.e. smp_processor_id() use that the
- * debugging code reports but which use for some reason is legal),
- * change the smp_processor_id() reference to _smp_processor_id(),
- * which is the nondebug variant.  NOTE: don't use this to hack around
- * real bugs.
+ * NOTE: raw_smp_processor_id() is for internal use only
+ * (smp_processor_id() is the preferred variant), but in rare
+ * instances it might also be used to turn off false positives
+ * (i.e. smp_processor_id() use that the debugging code reports but
+ * which use for some reason is legal). Don't use this to hack around
+ * the warning message, as your code might not work under PREEMPT.
  */
-#ifdef __smp_processor_id
-# if defined(CONFIG_PREEMPT) && defined(CONFIG_DEBUG_PREEMPT)
-   extern unsigned int smp_processor_id(void);
-# else
-#  define smp_processor_id() __smp_processor_id()
-# endif
-# define _smp_processor_id() __smp_processor_id()
+#ifdef CONFIG_DEBUG_PREEMPT
+  extern unsigned int debug_smp_processor_id(void);
+# define smp_processor_id() debug_smp_processor_id()
 #else
-# define _smp_processor_id() smp_processor_id()
+# define smp_processor_id() raw_smp_processor_id()
 #endif
 
 #define get_cpu()               ({ preempt_disable(); smp_processor_id(); })
diff --git a/include/linux/socket.h b/include/linux/socket.h
index a5c7d96e4d2e..1739c2d5b95b 100644
--- a/include/linux/socket.h
+++ b/include/linux/socket.h
@@ -26,6 +26,13 @@ struct __kernel_sockaddr_storage {
 #include <linux/types.h>                /* pid_t                        */
 #include <linux/compiler.h>             /* __user                       */
 
+extern int sysctl_somaxconn;
+extern void sock_init(void);
+#ifdef CONFIG_PROC_FS
+struct seq_file;
+extern void socket_seq_show(struct seq_file *seq);
+#endif
+
 typedef unsigned short  sa_family_t;
 
 /*
@@ -271,6 +278,8 @@ struct ucred {
 #define SOL_IRDA        266
 #define SOL_NETBEUI     267
 #define SOL_LLC         268
+#define SOL_DCCP        269
+#define SOL_NETLINK     270
 
 /* IPX options */
 #define IPX_TYPE        1
diff --git a/include/linux/sonypi.h b/include/linux/sonypi.h
index 768cbba617d0..f56d24734950 100644
--- a/include/linux/sonypi.h
+++ b/include/linux/sonypi.h
@@ -99,6 +99,8 @@
 #define SONYPI_EVENT_BATTERY_INSERT             57
 #define SONYPI_EVENT_BATTERY_REMOVE             58
 #define SONYPI_EVENT_FNKEY_RELEASED             59
+#define SONYPI_EVENT_WIRELESS_ON                60
+#define SONYPI_EVENT_WIRELESS_OFF               61
 
 /* get/set brightness */
 #define SONYPI_IOCGBRT          _IOR('v', 0, __u8)
diff --git a/include/linux/sound.h b/include/linux/sound.h
index 428f59794f48..72b9af4c3fd4 100644
--- a/include/linux/sound.h
+++ b/include/linux/sound.h
@@ -29,7 +29,9 @@
  *      Sound core interface functions
  */
  
+struct device;
 extern int register_sound_special(struct file_operations *fops, int unit);
+extern int register_sound_special_device(struct file_operations *fops, int unit, struct device *dev);
 extern int register_sound_mixer(struct file_operations *fops, int dev);
 extern int register_sound_midi(struct file_operations *fops, int dev);
 extern int register_sound_dsp(struct file_operations *fops, int dev);
diff --git a/include/linux/string.h b/include/linux/string.h
index b9fc59469956..dab2652acbd8 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -88,6 +88,8 @@ extern int memcmp(const void *,const void *,__kernel_size_t);
 extern void * memchr(const void *,int,__kernel_size_t);
 #endif
 
+extern char *kstrdup(const char *s, unsigned int __nocast gfp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/linux/sunrpc/cache.h b/include/linux/sunrpc/cache.h
index 6864063d1b9f..c4e3ea7cf154 100644
--- a/include/linux/sunrpc/cache.h
+++ b/include/linux/sunrpc/cache.h
@@ -60,6 +60,7 @@ struct cache_head {
 #define CACHE_NEW_EXPIRY 120    /* keep new things pending confirmation for 120 seconds */
 
 struct cache_detail {
+        struct module *         owner;
         int                     hash_size;
         struct cache_head **    hash_table;
         rwlock_t                hash_lock;
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index 2709caf4d128..ab151bbb66df 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -111,6 +111,11 @@ struct rpc_procinfo {
 struct rpc_clnt *rpc_create_client(struct rpc_xprt *xprt, char *servname,
                                 struct rpc_program *info,
                                 u32 version, rpc_authflavor_t authflavor);
+struct rpc_clnt *rpc_new_client(struct rpc_xprt *xprt, char *servname,
+                                struct rpc_program *info,
+                                u32 version, rpc_authflavor_t authflavor);
+struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *,
+                                struct rpc_program *, int);
 struct rpc_clnt *rpc_clone_client(struct rpc_clnt *);
 int             rpc_shutdown_client(struct rpc_clnt *);
 int             rpc_destroy_client(struct rpc_clnt *);
@@ -129,6 +134,7 @@ void		rpc_clnt_sigmask(struct rpc_clnt *clnt, sigset_t *oldset);
 void            rpc_clnt_sigunmask(struct rpc_clnt *clnt, sigset_t *oldset);
 void            rpc_setbufsize(struct rpc_clnt *, unsigned int, unsigned int);
 size_t          rpc_max_payload(struct rpc_clnt *);
+int             rpc_ping(struct rpc_clnt *clnt, int flags);
 
 static __inline__
 int rpc_call(struct rpc_clnt *clnt, u32 proc, void *argp, void *resp, int flags)
diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h
index 99d17ed7cebb..4d77e90d0b30 100644
--- a/include/linux/sunrpc/sched.h
+++ b/include/linux/sunrpc/sched.h
@@ -31,7 +31,6 @@ struct rpc_wait_queue;
 struct rpc_wait {
         struct list_head        list;           /* wait queue links */
         struct list_head        links;          /* Links to related tasks */
-        wait_queue_head_t       waitq;          /* sync: sleep on this q */
         struct rpc_wait_queue * rpc_waitq;      /* RPC wait queue we're on */
 };
 
diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
index 37003970cf2e..5af8800e0ce3 100644
--- a/include/linux/sunrpc/svc.h
+++ b/include/linux/sunrpc/svc.h
@@ -185,6 +185,17 @@ xdr_ressize_check(struct svc_rqst *rqstp, u32 *p)
         return vec->iov_len <= PAGE_SIZE;
 }
 
+static inline struct page *
+svc_take_res_page(struct svc_rqst *rqstp)
+{
+        if (rqstp->rq_arghi <= rqstp->rq_argused)
+                return NULL;
+        rqstp->rq_arghi--;
+        rqstp->rq_respages[rqstp->rq_resused] =
+                rqstp->rq_argpages[rqstp->rq_arghi];
+        return rqstp->rq_respages[rqstp->rq_resused++];
+}
+
 static inline int svc_take_page(struct svc_rqst *rqstp)
 {
         if (rqstp->rq_arghi <= rqstp->rq_argused)
@@ -240,9 +251,10 @@ struct svc_deferred_req {
 };
 
 /*
- * RPC program
+ * List of RPC programs on the same transport endpoint
  */
 struct svc_program {
+        struct svc_program *    pg_next;        /* other programs (same xprt) */
         u32                     pg_prog;        /* program number */
         unsigned int            pg_lovers;      /* lowest version */
         unsigned int            pg_hivers;      /* lowest version */
diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h
index 541dcf838abf..23448d0fb5bc 100644
--- a/include/linux/sunrpc/xdr.h
+++ b/include/linux/sunrpc/xdr.h
@@ -146,7 +146,8 @@ extern void xdr_shift_buf(struct xdr_buf *, size_t);
 extern void xdr_buf_from_iov(struct kvec *, struct xdr_buf *);
 extern int xdr_buf_subsegment(struct xdr_buf *, struct xdr_buf *, int, int);
 extern int xdr_buf_read_netobj(struct xdr_buf *, struct xdr_netobj *, int);
-extern int read_bytes_from_xdr_buf(struct xdr_buf *buf, int base, void *obj, int len);
+extern int read_bytes_from_xdr_buf(struct xdr_buf *, int, void *, int);
+extern int write_bytes_to_xdr_buf(struct xdr_buf *, int, void *, int);
 
 /*
  * Helper structure for copying from an sk_buff.
@@ -160,7 +161,7 @@ typedef struct {
 
 typedef size_t (*skb_read_actor_t)(skb_reader_t *desc, void *to, size_t len);
 
-extern void xdr_partial_copy_from_skb(struct xdr_buf *, unsigned int,
+extern ssize_t xdr_partial_copy_from_skb(struct xdr_buf *, unsigned int,
                 skb_reader_t *, skb_read_actor_t);
 
 struct socket;
@@ -168,6 +169,23 @@ struct sockaddr;
 extern int xdr_sendpages(struct socket *, struct sockaddr *, int,
                 struct xdr_buf *, unsigned int, int);
 
+extern int xdr_encode_word(struct xdr_buf *, int, u32);
+extern int xdr_decode_word(struct xdr_buf *, int, u32 *);
+
+struct xdr_array2_desc;
+typedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *desc, void *elem);
+struct xdr_array2_desc {
+        unsigned int elem_size;
+        unsigned int array_len;
+        unsigned int array_maxlen;
+        xdr_xcode_elem_t xcode;
+};
+
+extern int xdr_decode_array2(struct xdr_buf *buf, unsigned int base,
+                             struct xdr_array2_desc *desc);
+extern int xdr_encode_array2(struct xdr_buf *buf, unsigned int base,
+                             struct xdr_array2_desc *desc);
+
 /*
  * Provide some simple tools for XDR buffer overflow-checking etc.
  */
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 2bf0d5fabcdb..f2e96fdfaae0 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -58,7 +58,7 @@ static inline int software_suspend(void)
 }
 #endif
 
-#ifdef CONFIG_SMP
+#ifdef CONFIG_SUSPEND_SMP
 extern void disable_nonboot_cpus(void);
 extern void enable_nonboot_cpus(void);
 #else
diff --git a/include/linux/swap.h b/include/linux/swap.h
index 3bbc41be9bd0..3c9ff0048153 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -7,6 +7,7 @@
 #include <linux/mmzone.h>
 #include <linux/list.h>
 #include <linux/sched.h>
+
 #include <asm/atomic.h>
 #include <asm/page.h>
 
@@ -106,6 +107,8 @@ enum {
         SWP_USED        = (1 << 0),     /* is slot in swap_info[] used? */
         SWP_WRITEOK     = (1 << 1),     /* ok to write to this swap?    */
         SWP_ACTIVE      = (SWP_USED | SWP_WRITEOK),
+                                        /* add others here before... */
+        SWP_SCANNING    = (1 << 8),     /* refcount in scan_swap_map */
 };
 
 #define SWAP_CLUSTER_MAX 32
@@ -115,16 +118,13 @@ enum {
 
 /*
  * The in-memory structure used to track swap areas.
- * extent_list.prev points at the lowest-index extent.  That list is
- * sorted.
  */
 struct swap_info_struct {
         unsigned int flags;
-        spinlock_t sdev_lock;
+        int prio;                       /* swap priority */
         struct file *swap_file;
         struct block_device *bdev;
         struct list_head extent_list;
-        int nr_extents;
         struct swap_extent *curr_swap_extent;
         unsigned old_block_size;
         unsigned short * swap_map;
@@ -132,10 +132,9 @@ struct swap_info_struct {
         unsigned int highest_bit;
         unsigned int cluster_next;
         unsigned int cluster_nr;
-        int prio;                       /* swap priority */
-        int pages;
-        unsigned long max;
-        unsigned long inuse_pages;
+        unsigned int pages;
+        unsigned int max;
+        unsigned int inuse_pages;
         int next;                       /* next entry on swap list */
 };
 
@@ -148,7 +147,7 @@ struct swap_list_t {
 #define vm_swap_full() (nr_swap_pages*2 < total_swap_pages)
 
 /* linux/mm/oom_kill.c */
-extern void out_of_memory(unsigned int __nocast gfp_mask);
+extern void out_of_memory(unsigned int __nocast gfp_mask, int order);
 
 /* linux/mm/memory.c */
 extern void swapin_readahead(swp_entry_t, unsigned long, struct vm_area_struct *);
@@ -172,7 +171,8 @@ extern int rotate_reclaimable_page(struct page *page);
 extern void swap_setup(void);
 
 /* linux/mm/vmscan.c */
-extern int try_to_free_pages(struct zone **, unsigned int, unsigned int);
+extern int try_to_free_pages(struct zone **, unsigned int);
+extern int zone_reclaim(struct zone *, unsigned int, unsigned int);
 extern int shrink_all_memory(int);
 extern int vm_swappiness;
 
@@ -220,13 +220,7 @@ extern int can_share_swap_page(struct page *);
 extern int remove_exclusive_swap_page(struct page *);
 struct backing_dev_info;
 
-extern struct swap_list_t swap_list;
-extern spinlock_t swaplock;
-
-#define swap_list_lock()        spin_lock(&swaplock)
-#define swap_list_unlock()      spin_unlock(&swaplock)
-#define swap_device_lock(p)     spin_lock(&p->sdev_lock)
-#define swap_device_unlock(p)   spin_unlock(&p->sdev_lock)
+extern spinlock_t swap_lock;
 
 /* linux/mm/thrash.c */
 extern struct mm_struct * swap_token_mm;
@@ -252,6 +246,8 @@ static inline void put_swap_token(struct mm_struct *mm)
 
 #define si_swapinfo(val) \
         do { (val)->freeswap = (val)->totalswap = 0; } while (0)
+/* only sparc can not include linux/pagemap.h in this file
+ * so leave page_cache_release and release_pages undeclared... */
 #define free_page_and_swap_cache(page) \
         page_cache_release(page)
 #define free_pages_and_swap_cache(pages, nr) \
diff --git a/include/linux/swapops.h b/include/linux/swapops.h
index d4c7db35e708..87b9d14c710d 100644
--- a/include/linux/swapops.h
+++ b/include/linux/swapops.h
@@ -4,7 +4,7 @@
  * the low-order bits.
  *
  * We arrange the `type' and `offset' fields so that `type' is at the five
- * high-order bits of the smp_entry_t and `offset' is right-aligned in the
+ * high-order bits of the swp_entry_t and `offset' is right-aligned in the
  * remaining bits.
  *
  * swp_entry_t's are *never* stored anywhere in their arch-dependent format.
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index c39f6f72cbbc..425f58c8ea4a 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -159,8 +159,9 @@ asmlinkage long sys_shutdown(int, int);
 asmlinkage long sys_reboot(int magic1, int magic2, unsigned int cmd,
                                 void __user *arg);
 asmlinkage long sys_restart_syscall(void);
-asmlinkage long sys_kexec_load(void *entry, unsigned long nr_segments,
-                        struct kexec_segment *segments, unsigned long flags);
+asmlinkage long sys_kexec_load(unsigned long entry, unsigned long nr_segments,
+                                struct kexec_segment __user *segments,
+                                unsigned long flags);
 
 asmlinkage long sys_exit(int error_code);
 asmlinkage void sys_exit_group(int error_code);
@@ -505,4 +506,7 @@ asmlinkage long sys_request_key(const char __user *_type,
 asmlinkage long sys_keyctl(int cmd, unsigned long arg2, unsigned long arg3,
                            unsigned long arg4, unsigned long arg5);
 
+asmlinkage long sys_ioprio_set(int which, int who, int ioprio);
+asmlinkage long sys_ioprio_get(int which, int who);
+
 #endif
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index 23032d9d6071..532a6c5c24e9 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -70,6 +70,14 @@ enum
         CTL_BUS_ISA=1           /* ISA */
 };
 
+/* /proc/sys/fs/inotify/ */
+enum
+{
+        INOTIFY_MAX_USER_INSTANCES=1,   /* max instances per user */
+        INOTIFY_MAX_USER_WATCHES=2,     /* max watches per user */
+        INOTIFY_MAX_QUEUED_EVENTS=3     /* max queued events per instance */
+};
+
 /* CTL_KERN names: */
 enum
 {
@@ -136,6 +144,8 @@ enum
         KERN_UNKNOWN_NMI_PANIC=66, /* int: unknown nmi panic flag */
         KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */
         KERN_RANDOMIZE=68, /* int: randomize virtual address space */
+        KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */
+        KERN_SPIN_RETRY=70,     /* int: number of spinlock retries */
 };
 
 
@@ -242,6 +252,7 @@ enum
         NET_CORE_MOD_CONG=16,
         NET_CORE_DEV_WEIGHT=17,
         NET_CORE_SOMAXCONN=18,
+        NET_CORE_BUDGET=19,
 };
 
 /* /proc/sys/net/ethernet */
@@ -332,20 +343,14 @@ enum
         NET_TCP_FRTO=92,
         NET_TCP_LOW_LATENCY=93,
         NET_IPV4_IPFRAG_SECRET_INTERVAL=94,
-        NET_TCP_WESTWOOD=95,
         NET_IPV4_IGMP_MAX_MSF=96,
         NET_TCP_NO_METRICS_SAVE=97,
-        NET_TCP_VEGAS=98,
-        NET_TCP_VEGAS_ALPHA=99,
-        NET_TCP_VEGAS_BETA=100,
-        NET_TCP_VEGAS_GAMMA=101,
-        NET_TCP_BIC=102,
-        NET_TCP_BIC_FAST_CONVERGENCE=103,
-        NET_TCP_BIC_LOW_WINDOW=104,
         NET_TCP_DEFAULT_WIN_SCALE=105,
         NET_TCP_MODERATE_RCVBUF=106,
         NET_TCP_TSO_WIN_DIVISOR=107,
         NET_TCP_BIC_BETA=108,
+        NET_IPV4_ICMP_ERRORS_USE_INBOUND_IFADDR=109,
+        NET_TCP_CONG_CONTROL=110,
 };
 
 enum {
@@ -645,6 +650,7 @@ enum {
         NET_SCTP_ADDIP_ENABLE            = 13,
         NET_SCTP_PRSCTP_ENABLE           = 14,
         NET_SCTP_SNDBUF_POLICY           = 15,
+        NET_SCTP_SACK_TIMEOUT            = 16,
 };
 
 /* /proc/sys/net/bridge */
@@ -679,6 +685,7 @@ enum
         FS_XFS=17,      /* struct: control xfs parameters */
         FS_AIO_NR=18,   /* current system-wide number of aio requests */
         FS_AIO_MAX_NR=19,       /* system-wide maximum number of aio requests */
+        FS_INOTIFY=20,  /* inotify submenu */
 };
 
 /* /proc/sys/fs/quota/ */
@@ -704,6 +711,7 @@ enum {
         DEV_RAID=4,
         DEV_MAC_HID=5,
         DEV_SCSI=6,
+        DEV_IPMI=7,
 };
 
 /* /proc/sys/dev/cdrom */
@@ -769,6 +777,11 @@ enum {
         DEV_SCSI_LOGGING_LEVEL=1,
 };
 
+/* /proc/sys/dev/ipmi */
+enum {
+        DEV_IPMI_POWEROFF_POWERCYCLE=1,
+};
+
 /* /proc/sys/abi */
 enum
 {
diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
index 38b58b30814a..392da5a6dacb 100644
--- a/include/linux/sysfs.h
+++ b/include/linux/sysfs.h
@@ -16,13 +16,13 @@ struct kobject;
 struct module;
 
 struct attribute {
-        char                    * name;
+        const char              * name;
         struct module           * owner;
         mode_t                  mode;
 };
 
 struct attribute_group {
-        char                    * name;
+        const char              * name;
         struct attribute        ** attrs;
 };
 
@@ -73,6 +73,7 @@ struct sysfs_dirent {
         int                     s_type;
         umode_t                 s_mode;
         struct dentry           * s_dentry;
+        struct iattr            * s_iattr;
 };
 
 #define SYSFS_ROOT              0x0001
@@ -105,11 +106,11 @@ sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, mode_t mode);
 extern void
 sysfs_remove_file(struct kobject *, const struct attribute *);
 
-extern int 
-sysfs_create_link(struct kobject * kobj, struct kobject * target, char * name);
+extern int
+sysfs_create_link(struct kobject * kobj, struct kobject * target, const char * name);
 
 extern void
-sysfs_remove_link(struct kobject *, char * name);
+sysfs_remove_link(struct kobject *, const char * name);
 
 int sysfs_create_bin_file(struct kobject * kobj, struct bin_attribute * attr);
 int sysfs_remove_bin_file(struct kobject * kobj, struct bin_attribute * attr);
@@ -153,12 +154,12 @@ static inline void sysfs_remove_file(struct kobject * k, const struct attribute
         ;
 }
 
-static inline int sysfs_create_link(struct kobject * k, struct kobject * t, char * n)
+static inline int sysfs_create_link(struct kobject * k, struct kobject * t, const char * n)
 {
         return 0;
 }
 
-static inline void sysfs_remove_link(struct kobject * k, char * name)
+static inline void sysfs_remove_link(struct kobject * k, const char * name)
 {
         ;
 }
diff --git a/include/linux/tc_ematch/tc_em_meta.h b/include/linux/tc_ematch/tc_em_meta.h
index a6b2cc530af5..081b1ee8516e 100644
--- a/include/linux/tc_ematch/tc_em_meta.h
+++ b/include/linux/tc_ematch/tc_em_meta.h
@@ -41,19 +41,14 @@ enum
         TCF_META_ID_LOADAVG_1,
         TCF_META_ID_LOADAVG_2,
         TCF_META_ID_DEV,
-        TCF_META_ID_INDEV,
-        TCF_META_ID_REALDEV,
         TCF_META_ID_PRIORITY,
         TCF_META_ID_PROTOCOL,
-        TCF_META_ID_SECURITY,
         TCF_META_ID_PKTTYPE,
         TCF_META_ID_PKTLEN,
         TCF_META_ID_DATALEN,
         TCF_META_ID_MACLEN,
         TCF_META_ID_NFMARK,
         TCF_META_ID_TCINDEX,
-        TCF_META_ID_TCVERDICT,
-        TCF_META_ID_TCCLASSID,
         TCF_META_ID_RTCLASSID,
         TCF_META_ID_RTIIF,
         TCF_META_ID_SK_FAMILY,
diff --git a/include/linux/tc_ematch/tc_em_text.h b/include/linux/tc_ematch/tc_em_text.h
new file mode 100644
index 000000000000..7cd43e99c7f5
--- /dev/null
+++ b/include/linux/tc_ematch/tc_em_text.h
@@ -0,0 +1,19 @@
+#ifndef __LINUX_TC_EM_TEXT_H
+#define __LINUX_TC_EM_TEXT_H
+
+#include <linux/pkt_cls.h>
+
+#define TC_EM_TEXT_ALGOSIZ      16
+
+struct tcf_em_text
+{
+        char            algo[TC_EM_TEXT_ALGOSIZ];
+        __u16           from_offset;
+        __u16           to_offset;
+        __u16           pattern_len;
+        __u8            from_layer:4;
+        __u8            to_layer:4;
+        __u8            pad;
+};
+
+#endif
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index 14a55e3e3a50..ac4ca44c75ca 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -55,24 +55,6 @@ struct tcphdr {
         __u16   urg_ptr;
 };
 
-
-enum {
-  TCP_ESTABLISHED = 1,
-  TCP_SYN_SENT,
-  TCP_SYN_RECV,
-  TCP_FIN_WAIT1,
-  TCP_FIN_WAIT2,
-  TCP_TIME_WAIT,
-  TCP_CLOSE,
-  TCP_CLOSE_WAIT,
-  TCP_LAST_ACK,
-  TCP_LISTEN,
-  TCP_CLOSING,   /* now a valid state */
-
-  TCP_MAX_STATES /* Leave at the end! */
-};
-
-#define TCP_STATE_MASK  0xF
 #define TCP_ACTION_FIN  (1 << 7)
 
 enum {
@@ -127,6 +109,7 @@ enum {
 #define TCP_WINDOW_CLAMP        10      /* Bound advertised window */
 #define TCP_INFO                11      /* Information about this connection. */
 #define TCP_QUICKACK            12      /* Block/reenable quick acks */
+#define TCP_CONGESTION          13      /* Congestion control algorithm */
 
 #define TCPI_OPT_TIMESTAMPS     1
 #define TCPI_OPT_SACK           2
@@ -194,8 +177,9 @@ struct tcp_info
 
 #include <linux/config.h>
 #include <linux/skbuff.h>
-#include <linux/ip.h>
 #include <net/sock.h>
+#include <net/inet_connection_sock.h>
+#include <net/inet_timewait_sock.h>
 
 /* This defines a selective acknowledgement block. */
 struct tcp_sack_block {
@@ -203,13 +187,6 @@ struct tcp_sack_block {
         __u32   end_seq;
 };
 
-enum tcp_congestion_algo {
-        TCP_RENO=0,
-        TCP_VEGAS,
-        TCP_WESTWOOD,
-        TCP_BIC,
-};
-
 struct tcp_options_received {
 /*      PAWS/RTTM data  */
         long    ts_recent_stamp;/* Time we stored ts_recent (for aging) */
@@ -230,9 +207,20 @@ struct tcp_options_received {
         __u16   mss_clamp;      /* Maximal mss, negotiated at connection setup */
 };
 
+struct tcp_request_sock {
+        struct inet_request_sock req;
+        __u32                    rcv_isn;
+        __u32                    snt_isn;
+};
+
+static inline struct tcp_request_sock *tcp_rsk(const struct request_sock *req)
+{
+        return (struct tcp_request_sock *)req;
+}
+
 struct tcp_sock {
-        /* inet_sock has to be the first member of tcp_sock */
-        struct inet_sock        inet;
+        /* inet_connection_sock has to be the first member of tcp_sock */
+        struct inet_connection_sock     inet_conn;
         int     tcp_header_len; /* Bytes of tcp header to send          */
 
 /*
@@ -253,19 +241,6 @@ struct tcp_sock {
         __u32   snd_sml;        /* Last byte of the most recently transmitted small packet */
         __u32   rcv_tstamp;     /* timestamp of last received ACK (for keepalives) */
         __u32   lsndtime;       /* timestamp of last sent data packet (for restart window) */
-        struct tcp_bind_bucket *bind_hash;
-        /* Delayed ACK control data */
-        struct {
-                __u8    pending;        /* ACK is pending */
-                __u8    quick;          /* Scheduled number of quick acks       */
-                __u8    pingpong;       /* The session is interactive           */
-                __u8    blocked;        /* Delayed ACK was blocked by socket lock*/
-                __u32   ato;            /* Predicted tick of soft clock         */
-                unsigned long timeout;  /* Currently scheduled timeout          */
-                __u32   lrcvtime;       /* timestamp of last received data packet*/
-                __u16   last_seg_size;  /* Size of last incoming segment        */
-                __u16   rcv_mss;        /* MSS used for delayed ACK decisions   */ 
-        } ack;
 
         /* Data for direct copy to user */
         struct {
@@ -281,21 +256,17 @@ struct tcp_sock {
         __u32   max_window;     /* Maximal window ever seen from peer   */
         __u32   pmtu_cookie;    /* Last pmtu seen by socket             */
         __u32   mss_cache;      /* Cached effective mss, not including SACKS */
-        __u16   mss_cache_std;  /* Like mss_cache, but without TSO */
+        __u16   xmit_size_goal; /* Goal for segmenting output packets   */
         __u16   ext_header_len; /* Network protocol overhead (IP/IPv6 options) */
-        __u8    ca_state;       /* State of fast-retransmit machine     */
-        __u8    retransmits;    /* Number of unrecovered RTO timeouts.  */
 
-        __u16   advmss;         /* Advertised MSS                       */
         __u32   window_clamp;   /* Maximal window to advertise          */
         __u32   rcv_ssthresh;   /* Current window clamp                 */
 
         __u32   frto_highmark;  /* snd_nxt when RTO occurred */
         __u8    reordering;     /* Packet reordering metric.            */
         __u8    frto_counter;   /* Number of new acks after RTO */
-
-        __u8    adv_cong;       /* Using Vegas, Westwood, or BIC */
-        __u8    defer_accept;   /* User waits for some data after accept() */
+        __u8    nonagle;        /* Disable Nagle algorithm?             */
+        __u8    keepalive_probes; /* num of allowed keep alive probes   */
 
 /* RTT measurement */
         __u32   srtt;           /* smoothed round trip time << 3        */
@@ -303,19 +274,13 @@ struct tcp_sock {
         __u32   mdev_max;       /* maximal mdev for the last rtt period */
         __u32   rttvar;         /* smoothed mdev_max                    */
         __u32   rtt_seq;        /* sequence number to update rttvar     */
-        __u32   rto;            /* retransmit timeout                   */
 
         __u32   packets_out;    /* Packets which are "in flight"        */
         __u32   left_out;       /* Packets which leaved network */
         __u32   retrans_out;    /* Retransmitted packets out            */
-        __u8    backoff;        /* backoff                              */
 /*
  *      Options received (usually on last packet, some only on SYN packets).
  */
-        __u8    nonagle;        /* Disable Nagle algorithm?             */
-        __u8    keepalive_probes; /* num of allowed keep alive probes   */
-
-        __u8    probes_out;     /* unanswered 0 window probes           */
         struct tcp_options_received rx_opt;
 
 /*
@@ -328,11 +293,6 @@ struct tcp_sock {
         __u32   snd_cwnd_used;
         __u32   snd_cwnd_stamp;
 
-        /* Two commonly used timers in both sender and receiver paths. */
-        unsigned long           timeout;
-        struct timer_list       retransmit_timer;       /* Resend (no ack)      */
-        struct timer_list       delack_timer;           /* Ack delay            */
-
         struct sk_buff_head     out_of_order_queue; /* Out of order segments go here */
 
         struct tcp_func         *af_specific;   /* Operations which are AF_INET{4,6} specific   */
@@ -347,8 +307,7 @@ struct tcp_sock {
         struct tcp_sack_block duplicate_sack[1]; /* D-SACK block */
         struct tcp_sack_block selective_acks[4]; /* The SACKS themselves*/
 
-        __u8    syn_retries;    /* num of allowed syn retries */
-        __u8    ecn_flags;      /* ECN status bits.                     */
+        __u16   advmss;         /* Advertised MSS                       */
         __u16   prior_ssthresh; /* ssthresh saved at recovery start     */
         __u32   lost_out;       /* Lost packets                 */
         __u32   sacked_out;     /* SACK'd packets                       */
@@ -362,29 +321,12 @@ struct tcp_sock {
         int     undo_retrans;   /* number of undoable retransmissions. */
         __u32   urg_seq;        /* Seq of received urgent pointer */
         __u16   urg_data;       /* Saved octet of OOB data and control flags */
-        __u8    pending;        /* Scheduled timer event        */
         __u8    urg_mode;       /* In urgent mode               */
+        __u8    ecn_flags;      /* ECN status bits.                     */
         __u32   snd_up;         /* Urgent pointer               */
 
         __u32   total_retrans;  /* Total retransmits for entire connection */
 
-        /* The syn_wait_lock is necessary only to avoid proc interface having
-         * to grab the main lock sock while browsing the listening hash
-         * (otherwise it's deadlock prone).
-         * This lock is acquired in read mode only from listening_get_next()
-         * and it's acquired in write mode _only_ from code that is actively
-         * changing the syn_wait_queue. All readers that are holding
-         * the master sock lock don't need to grab this lock in read mode
-         * too as the syn_wait_queue writes are always protected from
-         * the main sock lock.
-         */
-        rwlock_t                syn_wait_lock;
-        struct tcp_listen_opt   *listen_opt;
-
-        /* FIFO of established children */
-        struct open_request     *accept_queue;
-        struct open_request     *accept_queue_tail;
-
         unsigned int            keepalive_time;   /* time before keep alive takes place */
         unsigned int            keepalive_intvl;  /* time interval between keep alive probes */
         int                     linger2;
@@ -404,38 +346,6 @@ struct tcp_sock {
                 __u32   seq;
                 __u32   time;
         } rcvq_space;
-
-/* TCP Westwood structure */
-        struct {
-                __u32    bw_ns_est;        /* first bandwidth estimation..not too smoothed 8) */
-                __u32    bw_est;           /* bandwidth estimate */
-                __u32    rtt_win_sx;       /* here starts a new evaluation... */
-                __u32    bk;
-                __u32    snd_una;          /* used for evaluating the number of acked bytes */
-                __u32    cumul_ack;
-                __u32    accounted;
-                __u32    rtt;
-                __u32    rtt_min;          /* minimum observed RTT */
-        } westwood;
-
-/* Vegas variables */
-        struct {
-                __u32   beg_snd_nxt;    /* right edge during last RTT */
-                __u32   beg_snd_una;    /* left edge  during last RTT */
-                __u32   beg_snd_cwnd;   /* saves the size of the cwnd */
-                __u8    doing_vegas_now;/* if true, do vegas for this RTT */
-                __u16   cntRTT;         /* # of RTTs measured within last RTT */
-                __u32   minRTT;         /* min of RTTs measured within last RTT (in usec) */
-                __u32   baseRTT;        /* the min of all Vegas RTT measurements seen (in usec) */
-        } vegas;
-
-        /* BI TCP Parameters */
-        struct {
-                __u32   cnt;            /* increase cwnd by 1 after this number of ACKs */
-                __u32   last_max_cwnd;  /* last maximium snd_cwnd */
-                __u32   last_cwnd;      /* the last snd_cwnd */
-                __u32   last_stamp;     /* time when updated last_cwnd */
-        } bictcp;
 };
 
 static inline struct tcp_sock *tcp_sk(const struct sock *sk)
@@ -443,6 +353,20 @@ static inline struct tcp_sock *tcp_sk(const struct sock *sk)
         return (struct tcp_sock *)sk;
 }
 
+struct tcp_timewait_sock {
+        struct inet_timewait_sock tw_sk;
+        __u32                     tw_rcv_nxt;
+        __u32                     tw_snd_nxt;
+        __u32                     tw_rcv_wnd;
+        __u32                     tw_ts_recent;
+        long                      tw_ts_recent_stamp;
+};
+
+static inline struct tcp_timewait_sock *tcp_twsk(const struct sock *sk)
+{
+        return (struct tcp_timewait_sock *)sk;
+}
+
 #endif
 
 #endif  /* _LINUX_TCP_H */
diff --git a/include/linux/tcp_diag.h b/include/linux/tcp_diag.h
deleted file mode 100644
index ceee962e1d15..000000000000
--- a/include/linux/tcp_diag.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _TCP_DIAG_H_
-#define _TCP_DIAG_H_ 1
-
-/* Just some random number */
-#define TCPDIAG_GETSOCK 18
-
-/* Socket identity */
-struct tcpdiag_sockid
-{
-        __u16   tcpdiag_sport;
-        __u16   tcpdiag_dport;
-        __u32   tcpdiag_src[4];
-        __u32   tcpdiag_dst[4];
-        __u32   tcpdiag_if;
-        __u32   tcpdiag_cookie[2];
-#define TCPDIAG_NOCOOKIE (~0U)
-};
-
-/* Request structure */
-
-struct tcpdiagreq
-{
-        __u8    tcpdiag_family;         /* Family of addresses. */
-        __u8    tcpdiag_src_len;
-        __u8    tcpdiag_dst_len;
-        __u8    tcpdiag_ext;            /* Query extended information */
-
-        struct tcpdiag_sockid id;
-
-        __u32   tcpdiag_states;         /* States to dump */
-        __u32   tcpdiag_dbs;            /* Tables to dump (NI) */
-};
-
-enum
-{
-        TCPDIAG_REQ_NONE,
-        TCPDIAG_REQ_BYTECODE,
-};
-
-#define TCPDIAG_REQ_MAX TCPDIAG_REQ_BYTECODE
-
-/* Bytecode is sequence of 4 byte commands followed by variable arguments.
- * All the commands identified by "code" are conditional jumps forward:
- * to offset cc+"yes" or to offset cc+"no". "yes" is supposed to be
- * length of the command and its arguments.
- */
- 
-struct tcpdiag_bc_op
-{
-        unsigned char   code;
-        unsigned char   yes;
-        unsigned short  no;
-};
-
-enum
-{
-        TCPDIAG_BC_NOP,
-        TCPDIAG_BC_JMP,
-        TCPDIAG_BC_S_GE,
-        TCPDIAG_BC_S_LE,
-        TCPDIAG_BC_D_GE,
-        TCPDIAG_BC_D_LE,
-        TCPDIAG_BC_AUTO,
-        TCPDIAG_BC_S_COND,
-        TCPDIAG_BC_D_COND,
-};
-
-struct tcpdiag_hostcond
-{
-        __u8    family;
-        __u8    prefix_len;
-        int     port;
-        __u32   addr[0];
-};
-
-/* Base info structure. It contains socket identity (addrs/ports/cookie)
- * and, alas, the information shown by netstat. */
-struct tcpdiagmsg
-{
-        __u8    tcpdiag_family;
-        __u8    tcpdiag_state;
-        __u8    tcpdiag_timer;
-        __u8    tcpdiag_retrans;
-
-        struct tcpdiag_sockid id;
-
-        __u32   tcpdiag_expires;
-        __u32   tcpdiag_rqueue;
-        __u32   tcpdiag_wqueue;
-        __u32   tcpdiag_uid;
-        __u32   tcpdiag_inode;
-};
-
-/* Extensions */
-
-enum
-{
-        TCPDIAG_NONE,
-        TCPDIAG_MEMINFO,
-        TCPDIAG_INFO,
-        TCPDIAG_VEGASINFO,
-};
-
-#define TCPDIAG_MAX TCPDIAG_VEGASINFO
-
-
-/* TCPDIAG_MEM */
-
-struct tcpdiag_meminfo
-{
-        __u32   tcpdiag_rmem;
-        __u32   tcpdiag_wmem;
-        __u32   tcpdiag_fmem;
-        __u32   tcpdiag_tmem;
-};
-
-/* TCPDIAG_VEGASINFO */
-
-struct tcpvegas_info {
-        __u32   tcpv_enabled;
-        __u32   tcpv_rttcnt;
-        __u32   tcpv_rtt;
-        __u32   tcpv_minrtt;
-};
-
-
-#endif /* _TCP_DIAG_H_ */
diff --git a/include/linux/textsearch.h b/include/linux/textsearch.h
new file mode 100644
index 000000000000..941f45ac117a
--- /dev/null
+++ b/include/linux/textsearch.h
@@ -0,0 +1,180 @@
+#ifndef __LINUX_TEXTSEARCH_H
+#define __LINUX_TEXTSEARCH_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+
+struct ts_config;
+
+/**
+ * TS_AUTOLOAD - Automatically load textsearch modules when needed
+ */
+#define TS_AUTOLOAD     1
+
+/**
+ * struct ts_state - search state
+ * @offset: offset for next match
+ * @cb: control buffer, for persistant variables of get_next_block()
+ */
+struct ts_state
+{
+        unsigned int            offset;
+        char                    cb[40];
+};
+
+/**
+ * struct ts_ops - search module operations
+ * @name: name of search algorithm
+ * @init: initialization function to prepare a search
+ * @find: find the next occurrence of the pattern
+ * @destroy: destroy algorithm specific parts of a search configuration
+ * @get_pattern: return head of pattern
+ * @get_pattern_len: return length of pattern
+ * @owner: module reference to algorithm
+ */
+struct ts_ops
+{
+        const char              *name;
+        struct ts_config *      (*init)(const void *, unsigned int, int);
+        unsigned int            (*find)(struct ts_config *,
+                                        struct ts_state *);
+        void                    (*destroy)(struct ts_config *);
+        void *                  (*get_pattern)(struct ts_config *);
+        unsigned int            (*get_pattern_len)(struct ts_config *);
+        struct module           *owner;
+        struct list_head        list;
+};
+
+/**
+ * struct ts_config - search configuration
+ * @ops: operations of chosen algorithm
+ * @get_next_block: callback to fetch the next block to search in
+ * @finish: callback to finalize a search
+ */
+struct ts_config
+{
+        struct ts_ops           *ops;
+
+        /**
+         * get_next_block - fetch next block of data
+         * @consumed: number of bytes consumed by the caller
+         * @dst: destination buffer
+         * @conf: search configuration
+         * @state: search state
+         *
+         * Called repeatedly until 0 is returned. Must assign the
+         * head of the next block of data to &*dst and return the length
+         * of the block or 0 if at the end. consumed == 0 indicates
+         * a new search. May store/read persistant values in state->cb.
+         */
+        unsigned int            (*get_next_block)(unsigned int consumed,
+                                                  const u8 **dst,
+                                                  struct ts_config *conf,
+                                                  struct ts_state *state);
+
+        /**
+         * finish - finalize/clean a series of get_next_block() calls
+         * @conf: search configuration
+         * @state: search state
+         *
+         * Called after the last use of get_next_block(), may be used
+         * to cleanup any leftovers.
+         */
+        void                    (*finish)(struct ts_config *conf,
+                                          struct ts_state *state);
+};
+
+/**
+ * textsearch_next - continue searching for a pattern
+ * @conf: search configuration
+ * @state: search state
+ *
+ * Continues a search looking for more occurrences of the pattern.
+ * textsearch_find() must be called to find the first occurrence
+ * in order to reset the state.
+ *
+ * Returns the position of the next occurrence of the pattern or
+ * UINT_MAX if not match was found.
+ */ 
+static inline unsigned int textsearch_next(struct ts_config *conf,
+                                           struct ts_state *state)
+{
+        unsigned int ret = conf->ops->find(conf, state);
+
+        if (conf->finish)
+                conf->finish(conf, state);
+
+        return ret;
+}
+
+/**
+ * textsearch_find - start searching for a pattern
+ * @conf: search configuration
+ * @state: search state
+ *
+ * Returns the position of first occurrence of the pattern or
+ * UINT_MAX if no match was found.
+ */ 
+static inline unsigned int textsearch_find(struct ts_config *conf,
+                                           struct ts_state *state)
+{
+        state->offset = 0;
+        return textsearch_next(conf, state);
+}
+
+/**
+ * textsearch_get_pattern - return head of the pattern
+ * @conf: search configuration
+ */
+static inline void *textsearch_get_pattern(struct ts_config *conf)
+{
+        return conf->ops->get_pattern(conf);
+}
+
+/**
+ * textsearch_get_pattern_len - return length of the pattern
+ * @conf: search configuration
+ */
+static inline unsigned int textsearch_get_pattern_len(struct ts_config *conf)
+{
+        return conf->ops->get_pattern_len(conf);
+}
+
+extern int textsearch_register(struct ts_ops *);
+extern int textsearch_unregister(struct ts_ops *);
+extern struct ts_config *textsearch_prepare(const char *, const void *,
+                                            unsigned int, int, int);
+extern void textsearch_destroy(struct ts_config *conf);
+extern unsigned int textsearch_find_continuous(struct ts_config *,
+                                               struct ts_state *,
+                                               const void *, unsigned int);
+
+
+#define TS_PRIV_ALIGNTO 8
+#define TS_PRIV_ALIGN(len) (((len) + TS_PRIV_ALIGNTO-1) & ~(TS_PRIV_ALIGNTO-1))
+
+static inline struct ts_config *alloc_ts_config(size_t payload, int gfp_mask)
+{
+        struct ts_config *conf;
+
+        conf = kmalloc(TS_PRIV_ALIGN(sizeof(*conf)) + payload, gfp_mask);
+        if (conf == NULL)
+                return ERR_PTR(-ENOMEM);
+
+        memset(conf, 0, TS_PRIV_ALIGN(sizeof(*conf)) + payload);
+        return conf;
+}
+
+static inline void *ts_config_priv(struct ts_config *conf)
+{
+        return ((u8 *) conf + TS_PRIV_ALIGN(sizeof(struct ts_config)));
+}
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/linux/textsearch_fsm.h b/include/linux/textsearch_fsm.h
new file mode 100644
index 000000000000..fdfa078c66e5
--- /dev/null
+++ b/include/linux/textsearch_fsm.h
@@ -0,0 +1,48 @@
+#ifndef __LINUX_TEXTSEARCH_FSM_H
+#define __LINUX_TEXTSEARCH_FSM_H
+
+#include <linux/types.h>
+
+enum {
+        TS_FSM_SPECIFIC,        /* specific character */
+        TS_FSM_WILDCARD,        /* any character */
+        TS_FSM_DIGIT,           /* isdigit() */
+        TS_FSM_XDIGIT,          /* isxdigit() */
+        TS_FSM_PRINT,           /* isprint() */
+        TS_FSM_ALPHA,           /* isalpha() */
+        TS_FSM_ALNUM,           /* isalnum() */
+        TS_FSM_ASCII,           /* isascii() */
+        TS_FSM_CNTRL,           /* iscntrl() */
+        TS_FSM_GRAPH,           /* isgraph() */
+        TS_FSM_LOWER,           /* islower() */
+        TS_FSM_UPPER,           /* isupper() */
+        TS_FSM_PUNCT,           /* ispunct() */
+        TS_FSM_SPACE,           /* isspace() */
+        __TS_FSM_TYPE_MAX,
+};
+#define TS_FSM_TYPE_MAX (__TS_FSM_TYPE_MAX - 1)
+
+enum {
+        TS_FSM_SINGLE,          /* 1 occurrence */
+        TS_FSM_PERHAPS,         /* 1 or 0 occurrence */
+        TS_FSM_ANY,             /* 0..n occurrences */
+        TS_FSM_MULTI,           /* 1..n occurrences */
+        TS_FSM_HEAD_IGNORE,     /* 0..n ignored occurrences at head */
+        __TS_FSM_RECUR_MAX,
+};
+#define TS_FSM_RECUR_MAX (__TS_FSM_RECUR_MAX - 1)
+
+/**
+ * struct ts_fsm_token - state machine token (state)
+ * @type: type of token
+ * @recur: number of recurrences
+ * @value: character value for TS_FSM_SPECIFIC
+ */
+struct ts_fsm_token
+{
+        __u16           type;
+        __u8            recur;
+        __u8            value;
+};
+
+#endif
diff --git a/include/linux/time.h b/include/linux/time.h
index 5634497ff5df..c10d4c21c183 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -97,7 +97,6 @@ extern int do_settimeofday(struct timespec *tv);
 extern int do_sys_settimeofday(struct timespec *tv, struct timezone *tz);
 extern void clock_was_set(void); // call when ever the clock is set
 extern int do_posix_clock_monotonic_gettime(struct timespec *tp);
-extern long do_nanosleep(struct timespec *t);
 extern long do_utimes(char __user * filename, struct timeval * times);
 struct itimerval;
 extern int do_setitimer(int which, struct itimerval *value, struct itimerval *ovalue);
diff --git a/include/linux/timer.h b/include/linux/timer.h
index 90db1cc62ddd..221f81ac2002 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -6,45 +6,33 @@
 #include <linux/spinlock.h>
 #include <linux/stddef.h>
 
-struct tvec_t_base_s;
+struct timer_base_s;
 
 struct timer_list {
         struct list_head entry;
         unsigned long expires;
 
-        spinlock_t lock;
         unsigned long magic;
 
         void (*function)(unsigned long);
         unsigned long data;
 
-        struct tvec_t_base_s *base;
+        struct timer_base_s *base;
 };
 
 #define TIMER_MAGIC     0x4b87ad6e
 
+extern struct timer_base_s __init_timer_base;
+
 #define TIMER_INITIALIZER(_function, _expires, _data) {         \
                 .function = (_function),                        \
                 .expires = (_expires),                          \
                 .data = (_data),                                \
-                .base = NULL,                                   \
+                .base = &__init_timer_base,                     \
                 .magic = TIMER_MAGIC,                           \
-                .lock = SPIN_LOCK_UNLOCKED,                     \
         }
 
-/***
- * init_timer - initialize a timer.
- * @timer: the timer to be initialized
- *
- * init_timer() must be done to a timer prior calling *any* of the
- * other timer functions.
- */
-static inline void init_timer(struct timer_list * timer)
-{
-        timer->base = NULL;
-        timer->magic = TIMER_MAGIC;
-        spin_lock_init(&timer->lock);
-}
+void fastcall init_timer(struct timer_list * timer);
 
 /***
  * timer_pending - is a timer pending?
@@ -58,7 +46,7 @@ static inline void init_timer(struct timer_list * timer)
  */
 static inline int timer_pending(const struct timer_list * timer)
 {
-        return timer->base != NULL;
+        return timer->entry.next != NULL;
 }
 
 extern void add_timer_on(struct timer_list *timer, int cpu);
@@ -88,13 +76,15 @@ static inline void add_timer(struct timer_list * timer)
 }
 
 #ifdef CONFIG_SMP
+  extern int try_to_del_timer_sync(struct timer_list *timer);
   extern int del_timer_sync(struct timer_list *timer);
-  extern int del_singleshot_timer_sync(struct timer_list *timer);
 #else
-# define del_timer_sync(t) del_timer(t)
-# define del_singleshot_timer_sync(t) del_timer(t)
+# define try_to_del_timer_sync(t)       del_timer(t)
+# define del_timer_sync(t)              del_timer(t)
 #endif
 
+#define del_singleshot_timer_sync(t) del_timer_sync(t)
+
 extern void init_timers(void);
 extern void run_local_timers(void);
 extern void it_real_fn(unsigned long);
diff --git a/include/linux/timex.h b/include/linux/timex.h
index 74fdd07d3792..7e050a2cc35b 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -260,6 +260,29 @@ extern long pps_calcnt;		/* calibration intervals */
 extern long pps_errcnt;         /* calibration errors */
 extern long pps_stbcnt;         /* stability limit exceeded */
 
+/**
+ * ntp_clear - Clears the NTP state variables
+ *
+ * Must be called while holding a write on the xtime_lock
+ */
+static inline void ntp_clear(void)
+{
+        time_adjust = 0;                /* stop active adjtime() */
+        time_status |= STA_UNSYNC;
+        time_maxerror = NTP_PHASE_LIMIT;
+        time_esterror = NTP_PHASE_LIMIT;
+}
+
+/**
+ * ntp_synced - Returns 1 if the NTP status is not UNSYNC
+ *
+ */
+static inline int ntp_synced(void)
+{
+        return !(time_status & STA_UNSYNC);
+}
+
+
 #ifdef CONFIG_TIME_INTERPOLATION
 
 #define TIME_SOURCE_CPU 0
diff --git a/include/linux/topology.h b/include/linux/topology.h
index d70e8972c67f..3df1d474e5c5 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -89,6 +89,11 @@
         .cache_hot_time         = 0,                    \
         .cache_nice_tries       = 0,                    \
         .per_cpu_gain           = 25,                   \
+        .busy_idx               = 0,                    \
+        .idle_idx               = 0,                    \
+        .newidle_idx            = 1,                    \
+        .wake_idx               = 0,                    \
+        .forkexec_idx           = 0,                    \
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_NEWIDLE    \
                                 | SD_BALANCE_EXEC       \
@@ -115,18 +120,44 @@
         .cache_hot_time         = (5*1000000/2),        \
         .cache_nice_tries       = 1,                    \
         .per_cpu_gain           = 100,                  \
+        .busy_idx               = 2,                    \
+        .idle_idx               = 1,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
         .flags                  = SD_LOAD_BALANCE       \
                                 | SD_BALANCE_NEWIDLE    \
                                 | SD_BALANCE_EXEC       \
-                                | SD_WAKE_AFFINE        \
-                                | SD_WAKE_IDLE          \
-                                | SD_WAKE_BALANCE,      \
+                                | SD_WAKE_AFFINE,       \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
         .nr_balance_failed      = 0,                    \
 }
 #endif
 
+/* sched_domains SD_ALLNODES_INIT for NUMA machines */
+#define SD_ALLNODES_INIT (struct sched_domain) {        \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 64,                   \
+        .max_interval           = 64*num_online_cpus(), \
+        .busy_factor            = 128,                  \
+        .imbalance_pct          = 133,                  \
+        .cache_hot_time         = (10*1000000),         \
+        .cache_nice_tries       = 1,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 3,                    \
+        .newidle_idx            = 0, /* unused */       \
+        .wake_idx               = 0, /* unused */       \
+        .forkexec_idx           = 0, /* unused */       \
+        .per_cpu_gain           = 100,                  \
+        .flags                  = SD_LOAD_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 64,                   \
+        .nr_balance_failed      = 0,                    \
+}
+
 #ifdef CONFIG_NUMA
 #ifndef SD_NODE_INIT
 #error Please define an appropriate SD_NODE_INIT in include/asm/topology.h!!!
diff --git a/include/linux/transport_class.h b/include/linux/transport_class.h
index 87d98d1faefb..1d6cc22e5f42 100644
--- a/include/linux/transport_class.h
+++ b/include/linux/transport_class.h
@@ -12,11 +12,16 @@
 #include <linux/device.h>
 #include <linux/attribute_container.h>
 
+struct transport_container;
+
 struct transport_class {
         struct class class;
-        int (*setup)(struct device *);
-        int (*configure)(struct device *);
-        int (*remove)(struct device *);
+        int (*setup)(struct transport_container *, struct device *,
+                     struct class_device *);
+        int (*configure)(struct transport_container *, struct device *,
+                         struct class_device *);
+        int (*remove)(struct transport_container *, struct device *,
+                      struct class_device *);
 };
 
 #define DECLARE_TRANSPORT_CLASS(cls, nm, su, rm, cfg)                   \
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 1b76106272d3..59ff42c629ec 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -345,6 +345,7 @@ extern int tty_check_change(struct tty_struct * tty);
 extern void stop_tty(struct tty_struct * tty);
 extern void start_tty(struct tty_struct * tty);
 extern int tty_register_ldisc(int disc, struct tty_ldisc *new_ldisc);
+extern int tty_unregister_ldisc(int disc);
 extern int tty_register_driver(struct tty_driver *driver);
 extern int tty_unregister_driver(struct tty_driver *driver);
 extern void tty_register_device(struct tty_driver *driver, unsigned index, struct device *dev);
diff --git a/include/linux/types.h b/include/linux/types.h
index dcb13f865df9..2b678c22ca4a 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -123,6 +123,9 @@ typedef		__u64		u_int64_t;
 typedef         __s64           int64_t;
 #endif
 
+/* this is a special 64bit data type that is 8-byte aligned */
+#define aligned_u64 unsigned long long __attribute__((aligned(8)))
+
 /*
  * The type used for indexing onto a disc or disc partition.
  * If required, asm/types.h can override it and define
diff --git a/include/linux/uinput.h b/include/linux/uinput.h
index 4c2c82336d10..84876077027f 100644
--- a/include/linux/uinput.h
+++ b/include/linux/uinput.h
@@ -42,8 +42,7 @@ struct uinput_request {
         int                     code;   /* UI_FF_UPLOAD, UI_FF_ERASE */
 
         int                     retval;
-        wait_queue_head_t       waitq;
-        int                     completed;
+        struct completion       done;
 
         union {
                 int             effect_id;
@@ -62,7 +61,7 @@ struct uinput_device {
 
         struct uinput_request   *requests[UINPUT_NUM_REQUESTS];
         wait_queue_head_t       requests_waitq;
-        struct semaphore        requests_sem;
+        spinlock_t              requests_lock;
 };
 #endif  /* __KERNEL__ */
 
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 2d1ac5058534..724637792996 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -287,15 +287,14 @@ struct usb_bus {
 
         struct dentry *usbfs_dentry;    /* usbfs dentry entry for the bus */
 
-        struct class_device class_dev;  /* class device for this bus */
+        struct class_device *class_dev; /* class device for this bus */
+        struct kref kref;               /* handles reference counting this bus */
         void (*release)(struct usb_bus *bus);   /* function to destroy this bus's memory */
-#if defined(CONFIG_USB_MON) || defined(CONFIG_USB_MON_MODULE)
+#if defined(CONFIG_USB_MON)
         struct mon_bus *mon_bus;        /* non-null when associated */
         int monitored;                  /* non-zero when monitored */
 #endif
 };
-#define to_usb_bus(d) container_of(d, struct usb_bus, class_dev)
-
 
 /* -------------------------------------------------------------------------- */
 
@@ -939,17 +938,17 @@ static inline void usb_fill_int_urb (struct urb *urb,
 }
 
 extern void usb_init_urb(struct urb *urb);
-extern struct urb *usb_alloc_urb(int iso_packets, int mem_flags);
+extern struct urb *usb_alloc_urb(int iso_packets, unsigned mem_flags);
 extern void usb_free_urb(struct urb *urb);
 #define usb_put_urb usb_free_urb
 extern struct urb *usb_get_urb(struct urb *urb);
-extern int usb_submit_urb(struct urb *urb, int mem_flags);
+extern int usb_submit_urb(struct urb *urb, unsigned mem_flags);
 extern int usb_unlink_urb(struct urb *urb);
 extern void usb_kill_urb(struct urb *urb);
 
 #define HAVE_USB_BUFFERS
 void *usb_buffer_alloc (struct usb_device *dev, size_t size,
-        int mem_flags, dma_addr_t *dma);
+        unsigned mem_flags, dma_addr_t *dma);
 void usb_buffer_free (struct usb_device *dev, size_t size,
         void *addr, dma_addr_t dma);
 
@@ -1056,7 +1055,7 @@ int usb_sg_init (
         struct scatterlist      *sg,
         int                     nents,
         size_t                  length,
-        int                     mem_flags
+        unsigned                mem_flags
 );
 void usb_sg_cancel (struct usb_sg_request *io);
 void usb_sg_wait (struct usb_sg_request *io);
diff --git a/include/linux/usb_cdc.h b/include/linux/usb_cdc.h
index f22d6beecc73..ba617c372455 100644
--- a/include/linux/usb_cdc.h
+++ b/include/linux/usb_cdc.h
@@ -34,6 +34,7 @@
 #define USB_CDC_ACM_TYPE                0x02            /* acm_descriptor */
 #define USB_CDC_UNION_TYPE              0x06            /* union_desc */
 #define USB_CDC_COUNTRY_TYPE            0x07
+#define USB_CDC_NETWORK_TERMINAL_TYPE   0x0a            /* network_terminal_desc */
 #define USB_CDC_ETHERNET_TYPE           0x0f            /* ether_desc */
 #define USB_CDC_WHCM_TYPE               0x11
 #define USB_CDC_MDLM_TYPE               0x12            /* mdlm_desc */
@@ -83,6 +84,18 @@ struct usb_cdc_union_desc {
         /* ... and there could be other slave interfaces */
 } __attribute__ ((packed));
 
+/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
+struct usb_cdc_network_terminal_desc {
+        __u8    bLength;
+        __u8    bDescriptorType;
+        __u8    bDescriptorSubType;
+
+        __u8    bEntityId;
+        __u8    iName;
+        __u8    bChannelIndex;
+        __u8    bPhysicalInterface;
+} __attribute__ ((packed));
+
 /* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
 struct usb_cdc_ether_desc {
         __u8    bLength;
diff --git a/include/linux/usb_ch9.h b/include/linux/usb_ch9.h
index f5fe94e09a03..ee21e6bf3867 100644
--- a/include/linux/usb_ch9.h
+++ b/include/linux/usb_ch9.h
@@ -6,17 +6,20 @@
  *
  * - the master/host side Linux-USB kernel driver API;
  * - the "usbfs" user space API; and
- * - (eventually) a Linux "gadget" slave/device side driver API.
+ * - the Linux "gadget" slave/device/peripheral side driver API.
  *
  * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems
  * act either as a USB master/host or as a USB slave/device.  That means
- * the master and slave side APIs will benefit from working well together.
+ * the master and slave side APIs benefit from working well together.
+ *
+ * There's also "Wireless USB", using low power short range radios for
+ * peripheral interconnection but otherwise building on the USB framework.
  */
 
 #ifndef __LINUX_USB_CH9_H
 #define __LINUX_USB_CH9_H
 
-#include <asm/types.h>          /* __u8 etc */
+#include <linux/types.h>        /* __u8 etc */
 
 /*-------------------------------------------------------------------------*/
 
@@ -68,6 +71,18 @@
 #define USB_REQ_SET_INTERFACE           0x0B
 #define USB_REQ_SYNCH_FRAME             0x0C
 
+#define USB_REQ_SET_ENCRYPTION          0x0D    /* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION          0x0E
+#define USB_REQ_SET_HANDSHAKE           0x0F
+#define USB_REQ_GET_HANDSHAKE           0x10
+#define USB_REQ_SET_CONNECTION          0x11
+#define USB_REQ_SET_SECURITY_DATA       0x12
+#define USB_REQ_GET_SECURITY_DATA       0x13
+#define USB_REQ_SET_WUSB_DATA           0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE     0x15
+#define USB_REQ_LOOPBACK_DATA_READ      0x16
+#define USB_REQ_SET_INTERFACE_DS        0x17
+
 /*
  * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
  * are read as a bit array returned by USB_REQ_GET_STATUS.  (So there
@@ -75,10 +90,12 @@
  */
 #define USB_DEVICE_SELF_POWERED         0       /* (read only) */
 #define USB_DEVICE_REMOTE_WAKEUP        1       /* dev may initiate wakeup */
-#define USB_DEVICE_TEST_MODE            2       /* (high speed only) */
-#define USB_DEVICE_B_HNP_ENABLE         3       /* dev may initiate HNP */
-#define USB_DEVICE_A_HNP_SUPPORT        4       /* RH port supports HNP */
-#define USB_DEVICE_A_ALT_HNP_SUPPORT    5       /* other RH port does */
+#define USB_DEVICE_TEST_MODE            2       /* (wired high speed only) */
+#define USB_DEVICE_BATTERY              2       /* (wireless) */
+#define USB_DEVICE_B_HNP_ENABLE         3       /* (otg) dev may initiate HNP */
+#define USB_DEVICE_WUSB_DEVICE          3       /* (wireless)*/
+#define USB_DEVICE_A_HNP_SUPPORT        4       /* (otg) RH port supports HNP */
+#define USB_DEVICE_A_ALT_HNP_SUPPORT    5       /* (otg) other RH port does */
 #define USB_DEVICE_DEBUG_MODE           6       /* (special devices only) */
 
 #define USB_ENDPOINT_HALT               0       /* IN/OUT will STALL */
@@ -135,6 +152,13 @@ struct usb_ctrlrequest {
 #define USB_DT_OTG                      0x09
 #define USB_DT_DEBUG                    0x0a
 #define USB_DT_INTERFACE_ASSOCIATION    0x0b
+/* these are from the Wireless USB spec */
+#define USB_DT_SECURITY                 0x0c
+#define USB_DT_KEY                      0x0d
+#define USB_DT_ENCRYPTION_TYPE          0x0e
+#define USB_DT_BOS                      0x0f
+#define USB_DT_DEVICE_CAPABILITY        0x10
+#define USB_DT_WIRELESS_ENDPOINT_COMP   0x11
 
 /* conventional codes for class-specific descriptors */
 #define USB_DT_CS_DEVICE                0x21
@@ -192,6 +216,7 @@ struct usb_device_descriptor {
 #define USB_CLASS_CSCID                 0x0b    /* chip+ smart card */
 #define USB_CLASS_CONTENT_SEC           0x0d    /* content security */
 #define USB_CLASS_VIDEO                 0x0e
+#define USB_CLASS_WIRELESS_CONTROLLER   0xe0
 #define USB_CLASS_APP_SPEC              0xfe
 #define USB_CLASS_VENDOR_SPEC           0xff
 
@@ -223,6 +248,7 @@ struct usb_config_descriptor {
 #define USB_CONFIG_ATT_ONE              (1 << 7)        /* must be set */
 #define USB_CONFIG_ATT_SELFPOWER        (1 << 6)        /* self powered */
 #define USB_CONFIG_ATT_WAKEUP           (1 << 5)        /* can wakeup */
+#define USB_CONFIG_ATT_BATTERY          (1 << 4)        /* battery powered */
 
 /*-------------------------------------------------------------------------*/
 
@@ -268,8 +294,8 @@ struct usb_endpoint_descriptor {
         __le16 wMaxPacketSize;
         __u8  bInterval;
 
-        // NOTE:  these two are _only_ in audio endpoints.
-        // use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof.
+        /* NOTE:  these two are _only_ in audio endpoints. */
+        /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */
         __u8  bRefresh;
         __u8  bSynchAddress;
 } __attribute__ ((packed));
@@ -289,6 +315,7 @@ struct usb_endpoint_descriptor {
 #define USB_ENDPOINT_XFER_ISOC          1
 #define USB_ENDPOINT_XFER_BULK          2
 #define USB_ENDPOINT_XFER_INT           3
+#define USB_ENDPOINT_MAX_ADJUSTABLE     0x80
 
 
 /*-------------------------------------------------------------------------*/
@@ -352,12 +379,154 @@ struct usb_interface_assoc_descriptor {
 
 /*-------------------------------------------------------------------------*/
 
+/* USB_DT_SECURITY:  group of wireless security descriptors, including
+ * encryption types available for setting up a CC/association.
+ */
+struct usb_security_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+
+        __le16 wTotalLength;
+        __u8  bNumEncryptionTypes;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_KEY:  used with {GET,SET}_SECURITY_DATA; only public keys
+ * may be retrieved.
+ */
+struct usb_key_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+
+        __u8  tTKID[3];
+        __u8  bReserved;
+        __u8  bKeyData[0];
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_ENCRYPTION_TYPE:  bundled in DT_SECURITY groups */
+struct usb_encryption_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+
+        __u8  bEncryptionType;
+#define USB_ENC_TYPE_UNSECURE           0
+#define USB_ENC_TYPE_WIRED              1       /* non-wireless mode */
+#define USB_ENC_TYPE_CCM_1              2       /* aes128/cbc session */
+#define USB_ENC_TYPE_RSA_1              3       /* rsa3072/sha1 auth */
+        __u8  bEncryptionValue;         /* use in SET_ENCRYPTION */
+        __u8  bAuthKeyIndex;
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_BOS:  group of wireless capabilities */
+struct usb_bos_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+
+        __le16 wTotalLength;
+        __u8  bNumDeviceCaps;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE_CAPABILITY:  grouped with BOS */
+struct usb_dev_cap_header {
+        __u8  bLength;
+        __u8  bDescriptorType;
+        __u8  bDevCapabilityType;
+};
+
+#define USB_CAP_TYPE_WIRELESS_USB       1
+
+struct usb_wireless_cap_descriptor {    /* Ultra Wide Band */
+        __u8  bLength;
+        __u8  bDescriptorType;
+        __u8  bDevCapabilityType;
+
+        __u8  bmAttributes;
+#define USB_WIRELESS_P2P_DRD            (1 << 1)
+#define USB_WIRELESS_BEACON_MASK        (3 << 2)
+#define USB_WIRELESS_BEACON_SELF        (1 << 2)
+#define USB_WIRELESS_BEACON_DIRECTED    (2 << 2)
+#define USB_WIRELESS_BEACON_NONE        (3 << 2)
+        __le16 wPHYRates;       /* bit rates, Mbps */
+#define USB_WIRELESS_PHY_53             (1 << 0)        /* always set */
+#define USB_WIRELESS_PHY_80             (1 << 1)
+#define USB_WIRELESS_PHY_107            (1 << 2)        /* always set */
+#define USB_WIRELESS_PHY_160            (1 << 3)
+#define USB_WIRELESS_PHY_200            (1 << 4)        /* always set */
+#define USB_WIRELESS_PHY_320            (1 << 5)
+#define USB_WIRELESS_PHY_400            (1 << 6)
+#define USB_WIRELESS_PHY_480            (1 << 7)
+        __u8  bmTFITXPowerInfo; /* TFI power levels */
+        __u8  bmFFITXPowerInfo; /* FFI power levels */
+        __le16 bmBandGroup;
+        __u8  bReserved;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_WIRELESS_ENDPOINT_COMP:  companion descriptor associated with
+ * each endpoint descriptor for a wireless device
+ */
+struct usb_wireless_ep_comp_descriptor {
+        __u8  bLength;
+        __u8  bDescriptorType;
+
+        __u8  bMaxBurst;
+        __u8  bMaxSequence;
+        __le16 wMaxStreamDelay;
+        __le16 wOverTheAirPacketSize;
+        __u8  bOverTheAirInterval;
+        __u8  bmCompAttributes;
+#define USB_ENDPOINT_SWITCH_MASK        0x03    /* in bmCompAttributes */
+#define USB_ENDPOINT_SWITCH_NO          0
+#define USB_ENDPOINT_SWITCH_SWITCH      1
+#define USB_ENDPOINT_SWITCH_SCALE       2
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless
+ * host and a device for connection set up, mutual authentication, and
+ * exchanging short lived session keys.  The handshake depends on a CC.
+ */
+struct usb_handshake {
+        __u8 bMessageNumber;
+        __u8 bStatus;
+        __u8 tTKID[3];
+        __u8 bReserved;
+        __u8 CDID[16];
+        __u8 nonce[16];
+        __u8 MIC[8];
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC).
+ * A CC may also be set up using non-wireless secure channels (including
+ * wired USB!), and some devices may support CCs with multiple hosts.
+ */
+struct usb_connection_context {
+        __u8 CHID[16];          /* persistent host id */
+        __u8 CDID[16];          /* device id (unique w/in host context) */
+        __u8 CK[16];            /* connection key */
+};
+
+/*-------------------------------------------------------------------------*/
+
 /* USB 2.0 defines three speeds, here's how Linux identifies them */
 
 enum usb_device_speed {
         USB_SPEED_UNKNOWN = 0,                  /* enumerating */
         USB_SPEED_LOW, USB_SPEED_FULL,          /* usb 1.1 */
-        USB_SPEED_HIGH                          /* usb 2.0 */
+        USB_SPEED_HIGH,                         /* usb 2.0 */
+        USB_SPEED_VARIABLE,                     /* wireless (usb 2.5) */
 };
 
 enum usb_device_state {
diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h
index 9bba9997947b..71e608607324 100644
--- a/include/linux/usb_gadget.h
+++ b/include/linux/usb_gadget.h
@@ -107,18 +107,18 @@ struct usb_ep_ops {
         int (*disable) (struct usb_ep *ep);
 
         struct usb_request *(*alloc_request) (struct usb_ep *ep,
-                int gfp_flags);
+                unsigned gfp_flags);
         void (*free_request) (struct usb_ep *ep, struct usb_request *req);
 
         void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes,
-                dma_addr_t *dma, int gfp_flags);
+                dma_addr_t *dma, unsigned gfp_flags);
         void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma,
                 unsigned bytes);
         // NOTE:  on 2.6, drivers may also use dma_map() and
         // dma_sync_single_*() to directly manage dma overhead. 
 
         int (*queue) (struct usb_ep *ep, struct usb_request *req,
-                int gfp_flags);
+                unsigned gfp_flags);
         int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
 
         int (*set_halt) (struct usb_ep *ep, int value);
@@ -214,7 +214,7 @@ usb_ep_disable (struct usb_ep *ep)
  * Returns the request, or null if one could not be allocated.
  */
 static inline struct usb_request *
-usb_ep_alloc_request (struct usb_ep *ep, int gfp_flags)
+usb_ep_alloc_request (struct usb_ep *ep, unsigned gfp_flags)
 {
         return ep->ops->alloc_request (ep, gfp_flags);
 }
@@ -254,7 +254,7 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req)
  */
 static inline void *
 usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma,
-        int gfp_flags)
+        unsigned gfp_flags)
 {
         return ep->ops->alloc_buffer (ep, len, dma, gfp_flags);
 }
@@ -330,7 +330,7 @@ usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len)
  * reported when the usb peripheral is disconnected.
  */
 static inline int
-usb_ep_queue (struct usb_ep *ep, struct usb_request *req, int gfp_flags)
+usb_ep_queue (struct usb_ep *ep, struct usb_request *req, unsigned gfp_flags)
 {
         return ep->ops->queue (ep, req, gfp_flags);
 }
@@ -711,7 +711,7 @@ usb_gadget_disconnect (struct usb_gadget *gadget)
  *      the hardware level driver. Most calls must be handled by
  *      the gadget driver, including descriptor and configuration
  *      management.  The 16 bit members of the setup data are in
- *      cpu order. Called in_interrupt; this may not sleep.  Driver
+ *      USB byte order. Called in_interrupt; this may not sleep.  Driver
  *      queues a response to ep0, or returns negative to stall.
  * @disconnect: Invoked after all transfers have been stopped,
  *      when the host is disconnected.  May be called in_interrupt; this
diff --git a/include/linux/usb_input.h b/include/linux/usb_input.h
new file mode 100644
index 000000000000..716e0cc16043
--- /dev/null
+++ b/include/linux/usb_input.h
@@ -0,0 +1,25 @@
+#ifndef __USB_INPUT_H
+#define __USB_INPUT_H
+
+/*
+ * Copyright (C) 2005 Dmitry Torokhov
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/usb.h>
+#include <linux/input.h>
+#include <asm/byteorder.h>
+
+static inline void
+usb_to_input_id(const struct usb_device *dev, struct input_id *id)
+{
+        id->bustype = BUS_USB;
+        id->vendor = le16_to_cpu(dev->descriptor.idVendor);
+        id->product = le16_to_cpu(dev->descriptor.idProduct);
+        id->version = le16_to_cpu(dev->descriptor.bcdDevice);
+}
+
+#endif
diff --git a/include/linux/usb_isp116x.h b/include/linux/usb_isp116x.h
new file mode 100644
index 000000000000..5f5a9d9bd6c2
--- /dev/null
+++ b/include/linux/usb_isp116x.h
@@ -0,0 +1,47 @@
+
+/*
+ * Board initialization code should put one of these into dev->platform_data
+ * and place the isp116x onto platform_bus.
+ */
+
+struct isp116x_platform_data {
+        /* Enable internal resistors on downstream ports */
+        unsigned sel15Kres:1;
+        /* Chip's internal clock won't be stopped in suspended state.
+           Setting/unsetting this bit takes effect only if
+           'remote_wakeup_enable' below is not set. */
+        unsigned clknotstop:1;
+        /* On-chip overcurrent protection */
+        unsigned oc_enable:1;
+        /* INT output polarity */
+        unsigned int_act_high:1;
+        /* INT edge or level triggered */
+        unsigned int_edge_triggered:1;
+        /* WAKEUP pin connected - NOT SUPPORTED  */
+        /* unsigned remote_wakeup_connected:1; */
+        /* Wakeup by devices on usb bus enabled */
+        unsigned remote_wakeup_enable:1;
+        /* Switch or not to switch (keep always powered) */
+        unsigned no_power_switching:1;
+        /* Ganged port power switching (0) or individual port
+           power switching (1) */
+        unsigned power_switching_mode:1;
+        /* Given port_power, msec/2 after power on till power good */
+        u8 potpg;
+        /* Hardware reset set/clear. If implemented, this function must:
+           if set == 0,   deassert chip's HW reset pin
+           otherwise,     assert chip's HW reset pin       */
+        void (*reset) (struct device * dev, int set);
+        /* Hardware clock start/stop. If implemented, this function must:
+           if start == 0,    stop the external clock
+           otherwise,        start the external clock
+         */
+        void (*clock) (struct device * dev, int start);
+        /* Inter-io delay (ns). The chip is picky about access timings; it
+           expects at least:
+           150ns delay between consecutive accesses to DATA_REG,
+           300ns delay between access to ADDR_REG and DATA_REG
+           OE, WE MUST NOT be changed during these intervals
+         */
+        void (*delay) (struct device * dev, int delay);
+};
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 4e0edce53760..acbfc525576d 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -221,6 +221,8 @@ struct v4l2_pix_format
 /*  Vendor-specific formats   */
 #define V4L2_PIX_FMT_WNVA     v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
 #define V4L2_PIX_FMT_SN9C10X  v4l2_fourcc('S','9','1','0') /* SN9C10x compression */
+#define V4L2_PIX_FMT_PWC1     v4l2_fourcc('P','W','C','1') /* pwc older webcam */
+#define V4L2_PIX_FMT_PWC2     v4l2_fourcc('P','W','C','2') /* pwc newer webcam */
 
 /*
  *      F O R M A T   E N U M E R A T I O N
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 6409d9cf5965..b244f69ef682 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -10,6 +10,14 @@
 #define VM_MAP          0x00000004      /* vmap()ed pages */
 /* bits [20..32] reserved for arch specific ioremap internals */
 
+/*
+ * Maximum alignment for ioremap() regions.
+ * Can be overriden by arch-specific value.
+ */
+#ifndef IOREMAP_MAX_ORDER
+#define IOREMAP_MAX_ORDER       (7 + PAGE_SHIFT)        /* 128 pages */
+#endif
+
 struct vm_struct {
         void                    *addr;
         unsigned long           size;
diff --git a/include/linux/wait.h b/include/linux/wait.h
index c9486c3efb4a..d38c9fecdc36 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -33,7 +33,7 @@ int default_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key
 struct __wait_queue {
         unsigned int flags;
 #define WQ_FLAG_EXCLUSIVE       0x01
-        struct task_struct * task;
+        void *private;
         wait_queue_func_t func;
         struct list_head task_list;
 };
@@ -60,7 +60,7 @@ typedef struct __wait_queue_head wait_queue_head_t;
  */
 
 #define __WAITQUEUE_INITIALIZER(name, tsk) {                            \
-        .task           = tsk,                                          \
+        .private        = tsk,                                          \
         .func           = default_wake_function,                        \
         .task_list      = { NULL, NULL } }
 
@@ -86,7 +86,7 @@ static inline void init_waitqueue_head(wait_queue_head_t *q)
 static inline void init_waitqueue_entry(wait_queue_t *q, struct task_struct *p)
 {
         q->flags = 0;
-        q->task = p;
+        q->private = p;
         q->func = default_wake_function;
 }
 
@@ -94,7 +94,7 @@ static inline void init_waitqueue_func_entry(wait_queue_t *q,
                                         wait_queue_func_t func)
 {
         q->flags = 0;
-        q->task = NULL;
+        q->private = NULL;
         q->func = func;
 }
 
@@ -110,7 +110,7 @@ static inline int waitqueue_active(wait_queue_head_t *q)
  * aio specifies a wait queue entry with an async notification
  * callback routine, not associated with any task.
  */
-#define is_sync_wait(wait)      (!(wait) || ((wait)->task))
+#define is_sync_wait(wait)      (!(wait) || ((wait)->private))
 
 extern void FASTCALL(add_wait_queue(wait_queue_head_t *q, wait_queue_t * wait));
 extern void FASTCALL(add_wait_queue_exclusive(wait_queue_head_t *q, wait_queue_t * wait));
@@ -384,7 +384,7 @@ int wake_bit_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
 
 #define DEFINE_WAIT(name)                                               \
         wait_queue_t name = {                                           \
-                .task           = current,                              \
+                .private        = current,                              \
                 .func           = autoremove_wake_function,             \
                 .task_list      = LIST_HEAD_INIT((name).task_list),     \
         }
@@ -393,7 +393,7 @@ int wake_bit_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
         struct wait_bit_queue name = {                                  \
                 .key = __WAIT_BIT_KEY_INITIALIZER(word, bit),           \
                 .wait   = {                                             \
-                        .task           = current,                      \
+                        .private        = current,                      \
                         .func           = wake_bit_function,            \
                         .task_list      =                               \
                                 LIST_HEAD_INIT((name).wait.task_list),  \
@@ -402,7 +402,7 @@ int wake_bit_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
 
 #define init_wait(wait)                                                 \
         do {                                                            \
-                (wait)->task = current;                                 \
+                (wait)->private = current;                              \
                 (wait)->func = autoremove_wake_function;                \
                 INIT_LIST_HEAD(&(wait)->task_list);                     \
         } while (0)
diff --git a/include/linux/wanrouter.h b/include/linux/wanrouter.h
index 3e89f0f15f49..1b6b76a4eb54 100644
--- a/include/linux/wanrouter.h
+++ b/include/linux/wanrouter.h
@@ -516,8 +516,7 @@ struct wan_device {
 /* Public functions available for device drivers */
 extern int register_wan_device(struct wan_device *wandev);
 extern int unregister_wan_device(char *name);
-unsigned short wanrouter_type_trans(struct sk_buff *skb,
-                                    struct net_device *dev);
+__be16 wanrouter_type_trans(struct sk_buff *skb, struct net_device *dev);
 int wanrouter_encapsulate(struct sk_buff *skb, struct net_device *dev,
                           unsigned short type);
 
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 88ba0d29f8c8..1192ed8f4fe8 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -47,4 +47,14 @@ struct watchdog_info {
 #define WDIOS_ENABLECARD        0x0002  /* Turn on the watchdog timer */
 #define WDIOS_TEMPPANIC         0x0004  /* Kernel panic on temperature trip */
 
+#ifdef __KERNEL__
+
+#ifdef CONFIG_WATCHDOG_NOWAYOUT
+#define WATCHDOG_NOWAYOUT       1
+#else
+#define WATCHDOG_NOWAYOUT       0
+#endif
+
+#endif  /* __KERNEL__ */
+
 #endif  /* ifndef _LINUX_WATCHDOG_H */
diff --git a/include/linux/wireless.h b/include/linux/wireless.h
index 2f51f2b6562e..a555a0f7a7b4 100644
--- a/include/linux/wireless.h
+++ b/include/linux/wireless.h
@@ -1,10 +1,10 @@
 /*
  * This file define a set of standard wireless extensions
  *
- * Version :    17      21.6.04
+ * Version :    19      18.3.05
  *
  * Authors :    Jean Tourrilhes - HPL - <jt@hpl.hp.com>
- * Copyright (c) 1997-2004 Jean Tourrilhes, All Rights Reserved.
+ * Copyright (c) 1997-2005 Jean Tourrilhes, All Rights Reserved.
  */
 
 #ifndef _LINUX_WIRELESS_H
@@ -69,8 +69,6 @@
 
 /***************************** INCLUDES *****************************/
 
-/* To minimise problems in user space, I might remove those headers
- * at some point. Jean II */
 #include <linux/types.h>                /* for "caddr_t" et al          */
 #include <linux/socket.h>               /* for "struct sockaddr" et al  */
 #include <linux/if.h>                   /* for IFNAMSIZ and co... */
@@ -82,7 +80,7 @@
  * (there is some stuff that will be added in the future...)
  * I just plan to increment with each new version.
  */
-#define WIRELESS_EXT    17
+#define WIRELESS_EXT    19
 
 /*
  * Changes :
@@ -182,6 +180,30 @@
  *      - Document (struct iw_quality *)->updated, add new flags (INVALID)
  *      - Wireless Event capability in struct iw_range
  *      - Add support for relative TxPower (yick !)
+ *
+ * V17 to V18 (From Jouni Malinen <jkmaline@cc.hut.fi>)
+ * ----------
+ *      - Add support for WPA/WPA2
+ *      - Add extended encoding configuration (SIOCSIWENCODEEXT and
+ *        SIOCGIWENCODEEXT)
+ *      - Add SIOCSIWGENIE/SIOCGIWGENIE
+ *      - Add SIOCSIWMLME
+ *      - Add SIOCSIWPMKSA
+ *      - Add struct iw_range bit field for supported encoding capabilities
+ *      - Add optional scan request parameters for SIOCSIWSCAN
+ *      - Add SIOCSIWAUTH/SIOCGIWAUTH for setting authentication and WPA
+ *        related parameters (extensible up to 4096 parameter values)
+ *      - Add wireless events: IWEVGENIE, IWEVMICHAELMICFAILURE,
+ *        IWEVASSOCREQIE, IWEVASSOCRESPIE, IWEVPMKIDCAND
+ *
+ * V18 to V19
+ * ----------
+ *      - Remove (struct iw_point *)->pointer from events and streams
+ *      - Remove header includes to help user space
+ *      - Increase IW_ENCODING_TOKEN_MAX from 32 to 64
+ *      - Add IW_QUAL_ALL_UPDATED and IW_QUAL_ALL_INVALID macros
+ *      - Add explicit flag to tell stats are in dBm : IW_QUAL_DBM
+ *      - Add IW_IOCTL_IDX() and IW_EVENT_IDX() macros
  */
 
 /**************************** CONSTANTS ****************************/
@@ -256,6 +278,30 @@
 #define SIOCSIWPOWER    0x8B2C          /* set Power Management settings */
 #define SIOCGIWPOWER    0x8B2D          /* get Power Management settings */
 
+/* WPA : Generic IEEE 802.11 informatiom element (e.g., for WPA/RSN/WMM).
+ * This ioctl uses struct iw_point and data buffer that includes IE id and len
+ * fields. More than one IE may be included in the request. Setting the generic
+ * IE to empty buffer (len=0) removes the generic IE from the driver. Drivers
+ * are allowed to generate their own WPA/RSN IEs, but in these cases, drivers
+ * are required to report the used IE as a wireless event, e.g., when
+ * associating with an AP. */
+#define SIOCSIWGENIE    0x8B30          /* set generic IE */
+#define SIOCGIWGENIE    0x8B31          /* get generic IE */
+
+/* WPA : IEEE 802.11 MLME requests */
+#define SIOCSIWMLME     0x8B16          /* request MLME operation; uses
+                                         * struct iw_mlme */
+/* WPA : Authentication mode parameters */
+#define SIOCSIWAUTH     0x8B32          /* set authentication mode params */
+#define SIOCGIWAUTH     0x8B33          /* get authentication mode params */
+
+/* WPA : Extended version of encoding configuration */
+#define SIOCSIWENCODEEXT 0x8B34         /* set encoding token & mode */
+#define SIOCGIWENCODEEXT 0x8B35         /* get encoding token & mode */
+
+/* WPA2 : PMKSA cache management */
+#define SIOCSIWPMKSA    0x8B36          /* PMKSA cache operation */
+
 /* -------------------- DEV PRIVATE IOCTL LIST -------------------- */
 
 /* These 32 ioctl are wireless device private, for 16 commands.
@@ -283,6 +329,7 @@
 /* The first and the last (range) */
 #define SIOCIWFIRST     0x8B00
 #define SIOCIWLAST      SIOCIWLASTPRIV          /* 0x8BFF */
+#define IW_IOCTL_IDX(cmd)       ((cmd) - SIOCIWFIRST)
 
 /* Even : get (world access), odd : set (root access) */
 #define IW_IS_SET(cmd)  (!((cmd) & 0x1))
@@ -297,8 +344,37 @@
 #define IWEVCUSTOM      0x8C02          /* Driver specific ascii string */
 #define IWEVREGISTERED  0x8C03          /* Discovered a new node (AP mode) */
 #define IWEVEXPIRED     0x8C04          /* Expired a node (AP mode) */
+#define IWEVGENIE       0x8C05          /* Generic IE (WPA, RSN, WMM, ..)
+                                         * (scan results); This includes id and
+                                         * length fields. One IWEVGENIE may
+                                         * contain more than one IE. Scan
+                                         * results may contain one or more
+                                         * IWEVGENIE events. */
+#define IWEVMICHAELMICFAILURE 0x8C06    /* Michael MIC failure
+                                         * (struct iw_michaelmicfailure)
+                                         */
+#define IWEVASSOCREQIE  0x8C07          /* IEs used in (Re)Association Request.
+                                         * The data includes id and length
+                                         * fields and may contain more than one
+                                         * IE. This event is required in
+                                         * Managed mode if the driver
+                                         * generates its own WPA/RSN IE. This
+                                         * should be sent just before
+                                         * IWEVREGISTERED event for the
+                                         * association. */
+#define IWEVASSOCRESPIE 0x8C08          /* IEs used in (Re)Association
+                                         * Response. The data includes id and
+                                         * length fields and may contain more
+                                         * than one IE. This may be sent
+                                         * between IWEVASSOCREQIE and
+                                         * IWEVREGISTERED events for the
+                                         * association. */
+#define IWEVPMKIDCAND   0x8C09          /* PMKID candidate for RSN
+                                         * pre-authentication
+                                         * (struct iw_pmkid_cand) */
 
 #define IWEVFIRST       0x8C00
+#define IW_EVENT_IDX(cmd)       ((cmd) - IWEVFIRST)
 
 /* ------------------------- PRIVATE INFO ------------------------- */
 /*
@@ -360,12 +436,15 @@
 #define IW_MODE_MONITOR 6       /* Passive monitor (listen only) */
 
 /* Statistics flags (bitmask in updated) */
-#define IW_QUAL_QUAL_UPDATED    0x1     /* Value was updated since last read */
-#define IW_QUAL_LEVEL_UPDATED   0x2
-#define IW_QUAL_NOISE_UPDATED   0x4
+#define IW_QUAL_QUAL_UPDATED    0x01    /* Value was updated since last read */
+#define IW_QUAL_LEVEL_UPDATED   0x02
+#define IW_QUAL_NOISE_UPDATED   0x04
+#define IW_QUAL_ALL_UPDATED     0x07
+#define IW_QUAL_DBM             0x08    /* Level + Noise are dBm */
 #define IW_QUAL_QUAL_INVALID    0x10    /* Driver doesn't provide value */
 #define IW_QUAL_LEVEL_INVALID   0x20
 #define IW_QUAL_NOISE_INVALID   0x40
+#define IW_QUAL_ALL_INVALID     0x70
 
 /* Frequency flags */
 #define IW_FREQ_AUTO            0x00    /* Let the driver decides */
@@ -376,7 +455,7 @@
 #define IW_MAX_ENCODING_SIZES   8
 
 /* Maximum size of the encoding token in bytes */
-#define IW_ENCODING_TOKEN_MAX   32      /* 256 bits (for now) */
+#define IW_ENCODING_TOKEN_MAX   64      /* 512 bits (for now) */
 
 /* Flags for encoding (along with the token) */
 #define IW_ENCODE_INDEX         0x00FF  /* Token index (if needed) */
@@ -432,12 +511,94 @@
 #define IW_SCAN_THIS_MODE       0x0020  /* Scan only this Mode */
 #define IW_SCAN_ALL_RATE        0x0040  /* Scan all Bit-Rates */
 #define IW_SCAN_THIS_RATE       0x0080  /* Scan only this Bit-Rate */
+/* struct iw_scan_req scan_type */
+#define IW_SCAN_TYPE_ACTIVE 0
+#define IW_SCAN_TYPE_PASSIVE 1
 /* Maximum size of returned data */
 #define IW_SCAN_MAX_DATA        4096    /* In bytes */
 
 /* Max number of char in custom event - use multiple of them if needed */
 #define IW_CUSTOM_MAX           256     /* In bytes */
 
+/* Generic information element */
+#define IW_GENERIC_IE_MAX       1024
+
+/* MLME requests (SIOCSIWMLME / struct iw_mlme) */
+#define IW_MLME_DEAUTH          0
+#define IW_MLME_DISASSOC        1
+
+/* SIOCSIWAUTH/SIOCGIWAUTH struct iw_param flags */
+#define IW_AUTH_INDEX           0x0FFF
+#define IW_AUTH_FLAGS           0xF000
+/* SIOCSIWAUTH/SIOCGIWAUTH parameters (0 .. 4095)
+ * (IW_AUTH_INDEX mask in struct iw_param flags; this is the index of the
+ * parameter that is being set/get to; value will be read/written to
+ * struct iw_param value field) */
+#define IW_AUTH_WPA_VERSION             0
+#define IW_AUTH_CIPHER_PAIRWISE         1
+#define IW_AUTH_CIPHER_GROUP            2
+#define IW_AUTH_KEY_MGMT                3
+#define IW_AUTH_TKIP_COUNTERMEASURES    4
+#define IW_AUTH_DROP_UNENCRYPTED        5
+#define IW_AUTH_80211_AUTH_ALG          6
+#define IW_AUTH_WPA_ENABLED             7
+#define IW_AUTH_RX_UNENCRYPTED_EAPOL    8
+#define IW_AUTH_ROAMING_CONTROL         9
+#define IW_AUTH_PRIVACY_INVOKED         10
+
+/* IW_AUTH_WPA_VERSION values (bit field) */
+#define IW_AUTH_WPA_VERSION_DISABLED    0x00000001
+#define IW_AUTH_WPA_VERSION_WPA         0x00000002
+#define IW_AUTH_WPA_VERSION_WPA2        0x00000004
+
+/* IW_AUTH_PAIRWISE_CIPHER and IW_AUTH_GROUP_CIPHER values (bit field) */
+#define IW_AUTH_CIPHER_NONE     0x00000001
+#define IW_AUTH_CIPHER_WEP40    0x00000002
+#define IW_AUTH_CIPHER_TKIP     0x00000004
+#define IW_AUTH_CIPHER_CCMP     0x00000008
+#define IW_AUTH_CIPHER_WEP104   0x00000010
+
+/* IW_AUTH_KEY_MGMT values (bit field) */
+#define IW_AUTH_KEY_MGMT_802_1X 1
+#define IW_AUTH_KEY_MGMT_PSK    2
+
+/* IW_AUTH_80211_AUTH_ALG values (bit field) */
+#define IW_AUTH_ALG_OPEN_SYSTEM 0x00000001
+#define IW_AUTH_ALG_SHARED_KEY  0x00000002
+#define IW_AUTH_ALG_LEAP        0x00000004
+
+/* IW_AUTH_ROAMING_CONTROL values */
+#define IW_AUTH_ROAMING_ENABLE  0       /* driver/firmware based roaming */
+#define IW_AUTH_ROAMING_DISABLE 1       /* user space program used for roaming
+                                         * control */
+
+/* SIOCSIWENCODEEXT definitions */
+#define IW_ENCODE_SEQ_MAX_SIZE  8
+/* struct iw_encode_ext ->alg */
+#define IW_ENCODE_ALG_NONE      0
+#define IW_ENCODE_ALG_WEP       1
+#define IW_ENCODE_ALG_TKIP      2
+#define IW_ENCODE_ALG_CCMP      3
+/* struct iw_encode_ext ->ext_flags */
+#define IW_ENCODE_EXT_TX_SEQ_VALID      0x00000001
+#define IW_ENCODE_EXT_RX_SEQ_VALID      0x00000002
+#define IW_ENCODE_EXT_GROUP_KEY         0x00000004
+#define IW_ENCODE_EXT_SET_TX_KEY        0x00000008
+
+/* IWEVMICHAELMICFAILURE : struct iw_michaelmicfailure ->flags */
+#define IW_MICFAILURE_KEY_ID    0x00000003 /* Key ID 0..3 */
+#define IW_MICFAILURE_GROUP     0x00000004
+#define IW_MICFAILURE_PAIRWISE  0x00000008
+#define IW_MICFAILURE_STAKEY    0x00000010
+#define IW_MICFAILURE_COUNT     0x00000060 /* 1 or 2 (0 = count not supported)
+                                            */
+
+/* Bit field values for enc_capa in struct iw_range */
+#define IW_ENC_CAPA_WPA         0x00000001
+#define IW_ENC_CAPA_WPA2        0x00000002
+#define IW_ENC_CAPA_CIPHER_TKIP 0x00000004
+#define IW_ENC_CAPA_CIPHER_CCMP 0x00000008
+
 /* Event capability macros - in (struct iw_range *)->event_capa
  * Because we have more than 32 possible events, we use an array of
  * 32 bit bitmasks. Note : 32 bits = 0x20 = 2^5. */
@@ -546,6 +707,132 @@ struct	iw_thrspy
         struct iw_quality       high;           /* High threshold */
 };
 
+/*
+ *      Optional data for scan request
+ *
+ *      Note: these optional parameters are controlling parameters for the
+ *      scanning behavior, these do not apply to getting scan results
+ *      (SIOCGIWSCAN). Drivers are expected to keep a local BSS table and
+ *      provide a merged results with all BSSes even if the previous scan
+ *      request limited scanning to a subset, e.g., by specifying an SSID.
+ *      Especially, scan results are required to include an entry for the
+ *      current BSS if the driver is in Managed mode and associated with an AP.
+ */
+struct  iw_scan_req
+{
+        __u8            scan_type; /* IW_SCAN_TYPE_{ACTIVE,PASSIVE} */
+        __u8            essid_len;
+        __u8            num_channels; /* num entries in channel_list;
+                                       * 0 = scan all allowed channels */
+        __u8            flags; /* reserved as padding; use zero, this may
+                                * be used in the future for adding flags
+                                * to request different scan behavior */
+        struct sockaddr bssid; /* ff:ff:ff:ff:ff:ff for broadcast BSSID or
+                                * individual address of a specific BSS */
+
+        /*
+         * Use this ESSID if IW_SCAN_THIS_ESSID flag is used instead of using
+         * the current ESSID. This allows scan requests for specific ESSID
+         * without having to change the current ESSID and potentially breaking
+         * the current association.
+         */
+        __u8            essid[IW_ESSID_MAX_SIZE];
+
+        /*
+         * Optional parameters for changing the default scanning behavior.
+         * These are based on the MLME-SCAN.request from IEEE Std 802.11.
+         * TU is 1.024 ms. If these are set to 0, driver is expected to use
+         * reasonable default values. min_channel_time defines the time that
+         * will be used to wait for the first reply on each channel. If no
+         * replies are received, next channel will be scanned after this. If
+         * replies are received, total time waited on the channel is defined by
+         * max_channel_time.
+         */
+        __u32           min_channel_time; /* in TU */
+        __u32           max_channel_time; /* in TU */
+
+        struct iw_freq  channel_list[IW_MAX_FREQUENCIES];
+};
+
+/* ------------------------- WPA SUPPORT ------------------------- */
+
+/*
+ *      Extended data structure for get/set encoding (this is used with
+ *      SIOCSIWENCODEEXT/SIOCGIWENCODEEXT. struct iw_point and IW_ENCODE_*
+ *      flags are used in the same way as with SIOCSIWENCODE/SIOCGIWENCODE and
+ *      only the data contents changes (key data -> this structure, including
+ *      key data).
+ *
+ *      If the new key is the first group key, it will be set as the default
+ *      TX key. Otherwise, default TX key index is only changed if
+ *      IW_ENCODE_EXT_SET_TX_KEY flag is set.
+ *
+ *      Key will be changed with SIOCSIWENCODEEXT in all cases except for
+ *      special "change TX key index" operation which is indicated by setting
+ *      key_len = 0 and ext_flags |= IW_ENCODE_EXT_SET_TX_KEY.
+ *
+ *      tx_seq/rx_seq are only used when respective
+ *      IW_ENCODE_EXT_{TX,RX}_SEQ_VALID flag is set in ext_flags. Normal
+ *      TKIP/CCMP operation is to set RX seq with SIOCSIWENCODEEXT and start
+ *      TX seq from zero whenever key is changed. SIOCGIWENCODEEXT is normally
+ *      used only by an Authenticator (AP or an IBSS station) to get the
+ *      current TX sequence number. Using TX_SEQ_VALID for SIOCSIWENCODEEXT and
+ *      RX_SEQ_VALID for SIOCGIWENCODEEXT are optional, but can be useful for
+ *      debugging/testing.
+ */
+struct  iw_encode_ext
+{
+        __u32           ext_flags; /* IW_ENCODE_EXT_* */
+        __u8            tx_seq[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */
+        __u8            rx_seq[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */
+        struct sockaddr addr; /* ff:ff:ff:ff:ff:ff for broadcast/multicast
+                               * (group) keys or unicast address for
+                               * individual keys */
+        __u16           alg; /* IW_ENCODE_ALG_* */
+        __u16           key_len;
+        __u8            key[0];
+};
+
+/* SIOCSIWMLME data */
+struct  iw_mlme
+{
+        __u16           cmd; /* IW_MLME_* */
+        __u16           reason_code;
+        struct sockaddr addr;
+};
+
+/* SIOCSIWPMKSA data */
+#define IW_PMKSA_ADD            1
+#define IW_PMKSA_REMOVE         2
+#define IW_PMKSA_FLUSH          3
+
+#define IW_PMKID_LEN    16
+
+struct  iw_pmksa
+{
+        __u32           cmd; /* IW_PMKSA_* */
+        struct sockaddr bssid;
+        __u8            pmkid[IW_PMKID_LEN];
+};
+
+/* IWEVMICHAELMICFAILURE data */
+struct  iw_michaelmicfailure
+{
+        __u32           flags;
+        struct sockaddr src_addr;
+        __u8            tsc[IW_ENCODE_SEQ_MAX_SIZE]; /* LSB first */
+};
+
+/* IWEVPMKIDCAND data */
+#define IW_PMKID_CAND_PREAUTH   0x00000001 /* RNS pre-authentication enabled */
+struct  iw_pmkid_cand
+{
+        __u32           flags; /* IW_PMKID_CAND_* */
+        __u32           index; /* the smaller the index, the higher the
+                                * priority */
+        struct sockaddr bssid;
+};
+
 /* ------------------------ WIRELESS STATS ------------------------ */
 /*
  * Wireless statistics (used for /proc/net/wireless)
@@ -725,6 +1012,8 @@ struct	iw_range
         struct iw_freq  freq[IW_MAX_FREQUENCIES];       /* list */
         /* Note : this frequency list doesn't need to fit channel numbers,
          * because each entry contain its channel index */
+
+        __u32           enc_capa; /* IW_ENC_CAPA_* bit field */
 };
 
 /*
@@ -762,12 +1051,16 @@ struct iw_event
 #define IW_EV_CHAR_LEN  (IW_EV_LCP_LEN + IFNAMSIZ)
 #define IW_EV_UINT_LEN  (IW_EV_LCP_LEN + sizeof(__u32))
 #define IW_EV_FREQ_LEN  (IW_EV_LCP_LEN + sizeof(struct iw_freq))
-#define IW_EV_POINT_LEN (IW_EV_LCP_LEN + sizeof(struct iw_point))
 #define IW_EV_PARAM_LEN (IW_EV_LCP_LEN + sizeof(struct iw_param))
 #define IW_EV_ADDR_LEN  (IW_EV_LCP_LEN + sizeof(struct sockaddr))
 #define IW_EV_QUAL_LEN  (IW_EV_LCP_LEN + sizeof(struct iw_quality))
 
-/* Note : in the case of iw_point, the extra data will come at the
- * end of the event */
+/* iw_point events are special. First, the payload (extra data) come at
+ * the end of the event, so they are bigger than IW_EV_POINT_LEN. Second,
+ * we omit the pointer, so start at an offset. */
+#define IW_EV_POINT_OFF (((char *) &(((struct iw_point *) NULL)->length)) - \
+                          (char *) NULL)
+#define IW_EV_POINT_LEN (IW_EV_LCP_LEN + sizeof(struct iw_point) - \
+                         IW_EV_POINT_OFF)
 
 #endif  /* _LINUX_WIRELESS_H */
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index 1262cb43c3ab..542dbaee6512 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -14,11 +14,13 @@ extern struct list_head inode_unused;
  * Yes, writeback.h requires sched.h
  * No, sched.h is not included from here.
  */
-static inline int current_is_pdflush(void)
+static inline int task_is_pdflush(struct task_struct *task)
 {
-        return current->flags & PF_FLUSHER;
+        return task->flags & PF_FLUSHER;
 }
 
+#define current_is_pdflush()    task_is_pdflush(current)
+
 /*
  * fs/fs-writeback.c
  */
@@ -83,7 +85,7 @@ static inline void wait_on_inode(struct inode *inode)
 /*
  * mm/page-writeback.c
  */
-int wakeup_bdflush(long nr_pages);
+int wakeup_pdflush(long nr_pages);
 void laptop_io_completion(void);
 void laptop_sync_completion(void);
 void throttle_vm_writeout(void);
diff --git a/include/linux/x25.h b/include/linux/x25.h
index 7531cfed5885..16d44931afa0 100644
--- a/include/linux/x25.h
+++ b/include/linux/x25.h
@@ -4,6 +4,8 @@
  *      History
  *      mar/20/00       Daniela Squassoni Disabling/enabling of facilities 
  *                                        negotiation.
+ *      apr/02/05       Shaun Pereira Selective sub address matching with
+ *                                      call user data
  */
 
 #ifndef X25_KERNEL_H
@@ -16,6 +18,9 @@
 #define SIOCX25GCALLUSERDATA    (SIOCPROTOPRIVATE + 4)
 #define SIOCX25SCALLUSERDATA    (SIOCPROTOPRIVATE + 5)
 #define SIOCX25GCAUSEDIAG       (SIOCPROTOPRIVATE + 6)
+#define SIOCX25SCUDMATCHLEN     (SIOCPROTOPRIVATE + 7)
+#define SIOCX25CALLACCPTAPPRV   (SIOCPROTOPRIVATE + 8)
+#define SIOCX25SENDCALLACCPT    (SIOCPROTOPRIVATE + 9)
 
 /*
  *      Values for {get,set}sockopt.
@@ -109,4 +114,11 @@ struct x25_causediag {
         unsigned char   diagnostic;
 };
 
+/*
+ *      Further optional call user data match length selection
+ */
+struct x25_subaddr {
+        unsigned int cudmatchlength;
+};
+
 #endif
diff --git a/include/linux/xattr_acl.h b/include/linux/xattr_acl.h
deleted file mode 100644
index 7a1f9b93a45f..000000000000
--- a/include/linux/xattr_acl.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
-  File: linux/xattr_acl.h
-
-  (extended attribute representation of access control lists)
-
-  (C) 2000 Andreas Gruenbacher, <a.gruenbacher@computer.org>
-*/
-
-#ifndef _LINUX_XATTR_ACL_H
-#define _LINUX_XATTR_ACL_H
-
-#include <linux/posix_acl.h>
-
-#define XATTR_NAME_ACL_ACCESS   "system.posix_acl_access"
-#define XATTR_NAME_ACL_DEFAULT  "system.posix_acl_default"
-
-#define XATTR_ACL_VERSION       0x0002
-
-typedef struct {
-        __u16           e_tag;
-        __u16           e_perm;
-        __u32           e_id;
-} xattr_acl_entry;
-
-typedef struct {
-        __u32           a_version;
-        xattr_acl_entry a_entries[0];
-} xattr_acl_header;
-
-static inline size_t xattr_acl_size(int count)
-{
-        return sizeof(xattr_acl_header) + count * sizeof(xattr_acl_entry);
-}
-
-static inline int xattr_acl_count(size_t size)
-{
-        if (size < sizeof(xattr_acl_header))
-                return -1;
-        size -= sizeof(xattr_acl_header);
-        if (size % sizeof(xattr_acl_entry))
-                return -1;
-        return size / sizeof(xattr_acl_entry);
-}
-
-struct posix_acl * posix_acl_from_xattr(const void *value, size_t size);
-int posix_acl_to_xattr(const struct posix_acl *acl, void *buffer, size_t size);
-
-
-
-#endif /* _LINUX_XATTR_ACL_H */
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index fd2ef742a9fd..0fb077d68441 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -174,6 +174,8 @@ enum xfrm_attr_type_t {
         XFRMA_ALG_COMP,         /* struct xfrm_algo */
         XFRMA_ENCAP,            /* struct xfrm_algo + struct xfrm_encap_tmpl */
         XFRMA_TMPL,             /* 1 or more struct xfrm_user_tmpl */
+        XFRMA_SA,
+        XFRMA_POLICY,
         __XFRMA_MAX
 
 #define XFRMA_MAX (__XFRMA_MAX - 1)
@@ -194,6 +196,7 @@ struct xfrm_usersa_info {
         __u8                            flags;
 #define XFRM_STATE_NOECN        1
 #define XFRM_STATE_DECAP_DSCP   2
+#define XFRM_STATE_NOPMTUDISC   4
 };
 
 struct xfrm_usersa_id {
@@ -255,7 +258,27 @@ struct xfrm_usersa_flush {
         __u8                            proto;
 };
 
+#ifndef __KERNEL__
+/* backwards compatibility for userspace */
 #define XFRMGRP_ACQUIRE         1
 #define XFRMGRP_EXPIRE          2
+#define XFRMGRP_SA              4
+#define XFRMGRP_POLICY          8
+#endif
+
+enum xfrm_nlgroups {
+        XFRMNLGRP_NONE,
+#define XFRMNLGRP_NONE          XFRMNLGRP_NONE
+        XFRMNLGRP_ACQUIRE,
+#define XFRMNLGRP_ACQUIRE       XFRMNLGRP_ACQUIRE
+        XFRMNLGRP_EXPIRE,
+#define XFRMNLGRP_EXPIRE        XFRMNLGRP_EXPIRE
+        XFRMNLGRP_SA,
+#define XFRMNLGRP_SA            XFRMNLGRP_SA
+        XFRMNLGRP_POLICY,
+#define XFRMNLGRP_POLICY        XFRMNLGRP_POLICY
+        __XFRMNLGRP_MAX
+};
+#define XFRMNLGRP_MAX   (__XFRMNLGRP_MAX - 1)
 
 #endif /* _LINUX_XFRM_H */
diff --git a/include/linux/zlib.h b/include/linux/zlib.h
index 850076ea14d3..74f7b78c22d2 100644
--- a/include/linux/zlib.h
+++ b/include/linux/zlib.h
@@ -506,6 +506,11 @@ extern int zlib_deflateReset (z_streamp strm);
    stream state was inconsistent (such as zalloc or state being NULL).
 */
 
+static inline unsigned long deflateBound(unsigned long s)
+{
+        return s + ((s + 7) >> 3) + ((s + 63) >> 6) + 11;
+}
+
 extern int zlib_deflateParams (z_streamp strm, int level, int strategy);
 /*
      Dynamically update the compression level and compression strategy.  The
diff --git a/include/media/audiochip.h b/include/media/audiochip.h
index d3e9e30608dc..cd831168fdc1 100644
--- a/include/media/audiochip.h
+++ b/include/media/audiochip.h
@@ -1,3 +1,7 @@
+/*
+ * $Id: audiochip.h,v 1.5 2005/06/16 22:59:16 hhackmann Exp $
+ */
+
 #ifndef AUDIOCHIP_H
 #define AUDIOCHIP_H
 
@@ -31,5 +35,4 @@
 
 /* misc stuff to pass around config info to i2c chips */
 #define AUDC_CONFIG_PINNACLE  _IOW('m',32,int)
-
 #endif /* AUDIOCHIP_H */
diff --git a/include/media/id.h b/include/media/id.h
index 1b0320dc8f73..801ddef301aa 100644
--- a/include/media/id.h
+++ b/include/media/id.h
@@ -1,3 +1,7 @@
+/*
+ * $Id: id.h,v 1.4 2005/06/12 04:19:19 mchehab Exp $
+ */
+
 /* FIXME: this temporarely, until these are included in linux/i2c-id.h */
 
 /* drivers */
@@ -30,8 +34,3 @@
 #ifndef  I2C_DRIVERID_SAA6752HS
 # define I2C_DRIVERID_SAA6752HS I2C_DRIVERID_EXP0+8
 #endif
-
-/* algorithms */
-#ifndef I2C_ALGO_SAA7134
-# define I2C_ALGO_SAA7134 0x090000
-#endif
diff --git a/include/media/ir-common.h b/include/media/ir-common.h
index 62c963a52d86..698670547f16 100644
--- a/include/media/ir-common.h
+++ b/include/media/ir-common.h
@@ -1,5 +1,5 @@
 /*
- * $Id: ir-common.h,v 1.8 2005/02/22 12:28:40 kraxel Exp $
+ * $Id: ir-common.h,v 1.9 2005/05/15 19:01:26 mchehab Exp $
  *
  * some common structs and functions to handle infrared remotes via
  * input layer ...
@@ -50,6 +50,7 @@ extern IR_KEYTAB_TYPE ir_codes_rc5_tv[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_winfast[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_empty[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_hauppauge_new[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_pixelview[IR_KEYTAB_SIZE];
 
 void ir_input_init(struct input_dev *dev, struct ir_input_state *ir,
                    int ir_type, IR_KEYTAB_TYPE *ir_codes);
diff --git a/include/media/saa6752hs.h b/include/media/saa6752hs.h
index 791bad2b86e9..3b8686ead80d 100644
--- a/include/media/saa6752hs.h
+++ b/include/media/saa6752hs.h
@@ -18,55 +18,6 @@
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
-#if 0 /* ndef _SAA6752HS_H */
-#define _SAA6752HS_H
-
-enum mpeg_video_bitrate_mode {
-        MPEG_VIDEO_BITRATE_MODE_VBR = 0, /* Variable bitrate */
-        MPEG_VIDEO_BITRATE_MODE_CBR = 1, /* Constant bitrate */
-
-        MPEG_VIDEO_BITRATE_MODE_MAX
-};
-
-enum mpeg_audio_bitrate {
-        MPEG_AUDIO_BITRATE_256 = 0, /* 256 kBit/sec */
-        MPEG_AUDIO_BITRATE_384 = 1, /* 384 kBit/sec */
-
-        MPEG_AUDIO_BITRATE_MAX
-};
-
-enum mpeg_video_format {
-        MPEG_VIDEO_FORMAT_D1 = 0,
-        MPEG_VIDEO_FORMAT_2_3_D1 = 1,
-        MPEG_VIDEO_FORMAT_1_2_D1 = 2,
-        MPEG_VIDEO_FORMAT_SIF = 3,
-
-        MPEG_VIDEO_FORMAT_MAX
-};
-
-#define MPEG_VIDEO_TARGET_BITRATE_MAX 27000
-#define MPEG_VIDEO_MAX_BITRATE_MAX 27000
-#define MPEG_TOTAL_BITRATE_MAX 27000
-#define MPEG_PID_MAX ((1 << 14) - 1)
-
-struct mpeg_params {
-        enum mpeg_video_bitrate_mode video_bitrate_mode;
-        unsigned int video_target_bitrate;
-        unsigned int video_max_bitrate; // only used for VBR
-        enum mpeg_audio_bitrate audio_bitrate;
-        unsigned int total_bitrate;
-
-        unsigned int pmt_pid;
-        unsigned int video_pid;
-        unsigned int audio_pid;
-        unsigned int pcr_pid;
-
-        enum mpeg_video_format video_format;
-};
-
-#define MPEG_SETPARAMS             _IOW('6',100,struct mpeg_params)
-
-#endif // _SAA6752HS_H
 
 /*
  * Local variables:
diff --git a/include/media/tuner.h b/include/media/tuner.h
index 156a9c51ffec..eeaa15ddee85 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -1,5 +1,6 @@
 
-/*
+/* $Id: tuner.h,v 1.45 2005/07/28 18:41:21 mchehab Exp $
+ *
     tuner.h - definition for different tuners
 
     Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
@@ -23,7 +24,9 @@
 #ifndef _TUNER_H
 #define _TUNER_H
 
-#include "id.h"
+#include <linux/videodev2.h>
+
+#define ADDR_UNSET (255)
 
 #define TUNER_TEMIC_PAL     0        /* 4002 FH5 (3X 7756, 9483) */
 #define TUNER_PHILIPS_PAL_I 1
@@ -86,7 +89,7 @@
 #define TUNER_LG_NTSC_TAPE       47
 
 #define TUNER_TNF_8831BGFF       48
-#define TUNER_MICROTUNE_4042FI5  49     /* FusionHDTV 3 Gold - 4042 FI5 (3X 8147) */
+#define TUNER_MICROTUNE_4042FI5  49     /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
 #define TUNER_TCL_2002N          50
 #define TUNER_PHILIPS_FM1256_IH3   51
 
@@ -96,7 +99,17 @@
 #define TUNER_LG_PAL_TAPE        55    /* Hauppauge PVR-150 PAL */
 
 #define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
-#define TUNER_PHILIPS_FQ1236A_MK4 57   /* Hauppauge PVR-500MCE NTSC */
+#define TUNER_PHILIPS_FQ1236A_MK4   57   /* Hauppauge PVR-500MCE NTSC */
+
+#define TUNER_YMEC_TVF_8531MF 58
+#define TUNER_YMEC_TVF_5533MF 59        /* Pixelview Pro Ultra NTSC */
+#define TUNER_THOMSON_DTT7611 60        /* DViCO FusionHDTV 3 Gold-T */
+#define TUNER_TENA_9533_DI    61
+
+#define TUNER_TEA5767         62        /* Only FM Radio Tuner */
+#define TUNER_PHILIPS_FMD1216ME_MK3 63
+#define TUNER_LG_TDVS_H062F   64        /* DViCO FusionHDTV 5 */
+#define TUNER_YMEC_TVF66T5_B_DFF 65     /* Acorp Y878F */
 
 #define NOTUNER 0
 #define PAL     1       /* PAL_BG */
@@ -104,6 +117,7 @@
 #define NTSC    3
 #define SECAM   4
 #define ATSC    5
+#define RADIO   6
 
 #define NoTuner 0
 #define Philips 1
@@ -119,10 +133,9 @@
 #define TCL     11
 #define THOMSON 12
 
-#define TUNER_SET_TYPE               _IOW('t',1,int)    /* set tuner type */
-#define TUNER_SET_TVFREQ             _IOW('t',2,int)    /* set tv freq */
+#define TUNER_SET_TYPE_ADDR          _IOW('T',3,int)
+#define TDA9887_SET_CONFIG           _IOW('t',5,int)
 
-#define  TDA9887_SET_CONFIG          _IOW('t',5,int)
 /* tv card specific */
 # define TDA9887_PRESENT             (1<<0)
 # define TDA9887_PORT1_INACTIVE      (1<<1)
@@ -143,19 +156,34 @@
 #define I2C_ADDR_TDA8290        0x4b
 #define I2C_ADDR_TDA8275        0x61
 
+enum tuner_mode {
+        T_UNINITIALIZED = 0,
+        T_RADIO         = 1 << V4L2_TUNER_RADIO,
+        T_ANALOG_TV     = 1 << V4L2_TUNER_ANALOG_TV,
+        T_DIGITAL_TV    = 1 << V4L2_TUNER_DIGITAL_TV,
+        T_STANDBY       = 1 << 31
+};
+
+struct tuner_setup {
+        unsigned short          addr;
+        unsigned int            type;
+        unsigned int            mode_mask;
+};
+
 struct tuner {
         /* device */
         struct i2c_client i2c;
 
-        /* state + config */
-        unsigned int initialized;
         unsigned int type;            /* chip type */
+
+        unsigned int          mode;
+        unsigned int          mode_mask; /* Combination of allowable modes */
+
         unsigned int freq;            /* keep track of the current settings */
+        unsigned int audmode;
         v4l2_std_id  std;
-        int          using_v4l2;
 
-        enum v4l2_tuner_type mode;
-        unsigned int input;
+        int          using_v4l2;
 
         /* used by MT2032 */
         unsigned int xogc;
@@ -177,7 +205,9 @@ extern unsigned const int tuner_count;
 
 extern int microtune_init(struct i2c_client *c);
 extern int tda8290_init(struct i2c_client *c);
+extern int tea5767_tuner_init(struct i2c_client *c);
 extern int default_tuner_init(struct i2c_client *c);
+extern int tea5767_autodetection(struct i2c_client *c);
 
 #define tuner_warn(fmt, arg...) \
         dev_printk(KERN_WARNING , &t->i2c.dev , fmt , ## arg)
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h
index 627603e561a6..854a2c2f105b 100644
--- a/include/media/tveeprom.h
+++ b/include/media/tveeprom.h
@@ -1,3 +1,7 @@
+/*
+ * $Id: tveeprom.h,v 1.2 2005/06/12 04:19:19 mchehab Exp $
+ */
+
 struct tveeprom {
         u32 has_radio;
 
@@ -20,4 +24,3 @@ void tveeprom_hauppauge_analog(struct tveeprom *tvee,
                                unsigned char *eeprom_data);
 
 int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len);
-int tveeprom_dump(unsigned char *eedata, int len);
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index a76ab898f445..428d9122940b 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -1,5 +1,5 @@
 /*
- * $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $
+ * $Id: mtd-abi.h,v 1.11 2005/05/19 16:08:58 gleixner Exp $
  *
  * Portions of MTD ABI definition which are shared by kernel and user space 
  */
@@ -29,6 +29,7 @@ struct mtd_oob_buf {
 #define MTD_NORFLASH            3
 #define MTD_NANDFLASH           4
 #define MTD_PEROM               5
+#define MTD_DATAFLASH           6
 #define MTD_OTHER               14
 #define MTD_UNKNOWN             15
 
@@ -60,6 +61,12 @@ struct mtd_oob_buf {
 #define MTD_NANDECC_PLACE       1       // Use the given placement in the structure (YAFFS1 legacy mode)
 #define MTD_NANDECC_AUTOPLACE   2       // Use the default placement scheme
 #define MTD_NANDECC_PLACEONLY   3       // Use the given placement in the structure (Do not store ecc result on read)
+#define MTD_NANDECC_AUTOPL_USR  4       // Use the given autoplacement scheme rather than using the default
+
+/* OTP mode selection */
+#define MTD_OTP_OFF             0
+#define MTD_OTP_FACTORY         1
+#define MTD_OTP_USER            2
 
 struct mtd_info_user {
         uint8_t type;
@@ -80,6 +87,12 @@ struct region_info_user {
         uint32_t regionindex;
 };
 
+struct otp_info {
+        uint32_t start;
+        uint32_t length;
+        uint32_t locked;
+};
+
 #define MEMGETINFO              _IOR('M', 1, struct mtd_info_user)
 #define MEMERASE                _IOW('M', 2, struct erase_info_user)
 #define MEMWRITEOOB             _IOWR('M', 3, struct mtd_oob_buf)
@@ -92,6 +105,10 @@ struct region_info_user {
 #define MEMGETOOBSEL            _IOR('M', 10, struct nand_oobinfo)
 #define MEMGETBADBLOCK          _IOW('M', 11, loff_t)
 #define MEMSETBADBLOCK          _IOW('M', 12, loff_t)
+#define OTPSELECT               _IOR('M', 13, int)
+#define OTPGETREGIONCOUNT       _IOW('M', 14, int)
+#define OTPGETREGIONINFO        _IOW('M', 15, struct otp_info)
+#define OTPLOCK         _IOR('M', 16, struct otp_info)
 
 struct nand_oobinfo {
         uint32_t useecc;
diff --git a/include/net/act_api.h b/include/net/act_api.h
index ed00a995f576..b55eb7c7f033 100644
--- a/include/net/act_api.h
+++ b/include/net/act_api.h
@@ -63,7 +63,7 @@ struct tc_action_ops
         __u32   type; /* TBD to match kind */
         __u32   capab;  /* capabilities includes 4 bit version */
         struct module           *owner;
-        int     (*act)(struct sk_buff **, struct tc_action *);
+        int     (*act)(struct sk_buff **, struct tc_action *, struct tcf_result *);
         int     (*get_stats)(struct sk_buff *, struct tc_action *);
         int     (*dump)(struct sk_buff *, struct tc_action *,int , int);
         int     (*cleanup)(struct tc_action *, int bind);
diff --git a/include/net/addrconf.h b/include/net/addrconf.h
index a0ed93672176..750e2508dd90 100644
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -45,6 +45,7 @@ struct prefix_info {
 
 #ifdef __KERNEL__
 
+#include <linux/config.h>
 #include <linux/netdevice.h>
 #include <net/if_inet6.h>
 #include <net/ipv6.h>
@@ -238,5 +239,10 @@ static inline int ipv6_addr_is_ll_all_routers(const struct in6_addr *addr)
                 addr->s6_addr32[3] == htonl(0x00000002));
 }
 
+#ifdef CONFIG_PROC_FS
+extern int if6_proc_init(void);
+extern void if6_proc_exit(void);
+#endif
+
 #endif
 #endif
diff --git a/include/net/af_unix.h b/include/net/af_unix.h
index b60b3846b9d1..b5d785ab4a0e 100644
--- a/include/net/af_unix.h
+++ b/include/net/af_unix.h
@@ -1,5 +1,11 @@
 #ifndef __LINUX_NET_AFUNIX_H
 #define __LINUX_NET_AFUNIX_H
+
+#include <linux/config.h>
+#include <linux/socket.h>
+#include <linux/un.h>
+#include <net/sock.h>
+
 extern void unix_inflight(struct file *fp);
 extern void unix_notinflight(struct file *fp);
 extern void unix_gc(void);
@@ -74,5 +80,14 @@ struct unix_sock {
         wait_queue_head_t       peer_wait;
 };
 #define unix_sk(__sk) ((struct unix_sock *)__sk)
+
+#ifdef CONFIG_SYSCTL
+extern int sysctl_unix_max_dgram_qlen;
+extern void unix_sysctl_register(void);
+extern void unix_sysctl_unregister(void);
+#else
+static inline void unix_sysctl_register(void) {}
+static inline void unix_sysctl_unregister(void) {}
+#endif
 #endif
 #endif
diff --git a/include/net/arp.h b/include/net/arp.h
index a1f09fad6a52..a13e30c35f42 100644
--- a/include/net/arp.h
+++ b/include/net/arp.h
@@ -11,7 +11,7 @@ extern struct neigh_table arp_tbl;
 
 extern void     arp_init(void);
 extern int      arp_rcv(struct sk_buff *skb, struct net_device *dev,
-                        struct packet_type *pt);
+                        struct packet_type *pt, struct net_device *orig_dev);
 extern int      arp_find(unsigned char *haddr, struct sk_buff *skb);
 extern int      arp_ioctl(unsigned int cmd, void __user *arg);
 extern void     arp_send(int type, int ptype, u32 dest_ip, 
diff --git a/include/net/ax25.h b/include/net/ax25.h
index 9e6368a54547..364b046e9f47 100644
--- a/include/net/ax25.h
+++ b/include/net/ax25.h
@@ -139,11 +139,25 @@ enum {
 #define AX25_DEF_DS_TIMEOUT     (3 * 60 * HZ)           /* DAMA timeout 3 minutes */
 
 typedef struct ax25_uid_assoc {
-        struct ax25_uid_assoc   *next;
+        struct hlist_node       uid_node;
+        atomic_t                refcount;
         uid_t                   uid;
         ax25_address            call;
 } ax25_uid_assoc;
 
+#define ax25_uid_for_each(__ax25, node, list) \
+        hlist_for_each_entry(__ax25, node, list, uid_node)
+
+#define ax25_uid_hold(ax25) \
+        atomic_inc(&((ax25)->refcount))
+
+static inline void ax25_uid_put(ax25_uid_assoc *assoc)
+{
+        if (atomic_dec_and_test(&assoc->refcount)) {
+                kfree(assoc);
+        }
+}
+
 typedef struct {
         ax25_address            calls[AX25_MAX_DIGIS];
         unsigned char           repeated[AX25_MAX_DIGIS];
@@ -220,7 +234,7 @@ static __inline__ void ax25_cb_put(ax25_cb *ax25)
         }
 }
 
-static inline unsigned short ax25_type_trans(struct sk_buff *skb, struct net_device *dev)
+static inline __be16 ax25_type_trans(struct sk_buff *skb, struct net_device *dev)
 {
         skb->dev      = dev;
         skb->pkt_type = PACKET_HOST;
@@ -243,7 +257,7 @@ extern struct sock *ax25_make_new(struct sock *, struct ax25_dev *);
 
 /* ax25_addr.c */
 extern ax25_address null_ax25_address;
-extern char *ax2asc(ax25_address *);
+extern char *ax2asc(char *buf, ax25_address *);
 extern ax25_address *asc2ax(char *);
 extern int  ax25cmp(ax25_address *, ax25_address *);
 extern int  ax25digicmp(ax25_digi *, ax25_digi *);
@@ -302,7 +316,7 @@ extern int  ax25_protocol_is_registered(unsigned int);
 
 /* ax25_in.c */
 extern int  ax25_rx_iframe(ax25_cb *, struct sk_buff *);
-extern int  ax25_kiss_rcv(struct sk_buff *, struct net_device *, struct packet_type *);
+extern int  ax25_kiss_rcv(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);
 
 /* ax25_ip.c */
 extern int  ax25_encapsulate(struct sk_buff *, struct net_device *, unsigned short, void *, void *, unsigned int);
@@ -376,7 +390,7 @@ extern unsigned long ax25_display_timer(struct timer_list *);
 
 /* ax25_uid.c */
 extern int  ax25_uid_policy;
-extern ax25_address *ax25_findbyuid(uid_t);
+extern ax25_uid_assoc *ax25_findbyuid(uid_t);
 extern int  ax25_uid_ioctl(int, struct sockaddr_ax25 *);
 extern struct file_operations ax25_uid_fops;
 extern void ax25_uid_free(void);
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 42a84c53678b..6dfa4a61ffd0 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -57,12 +57,6 @@
 #define BT_DBG(fmt, arg...)  printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg)
 #define BT_ERR(fmt, arg...)  printk(KERN_ERR  "%s: " fmt "\n" , __FUNCTION__ , ## arg)
 
-#ifdef HCI_DATA_DUMP
-#define BT_DMP(buf, len) bt_dump(__FUNCTION__, buf, len)
-#else
-#define BT_DMP(D...)
-#endif
-
 extern struct proc_dir_entry *proc_bt;
 
 /* Connection and socket states */
@@ -137,11 +131,12 @@ struct sock *bt_accept_dequeue(struct sock *parent, struct socket *newsock);
 
 /* Skb helpers */
 struct bt_skb_cb {
-        int incoming;
+        __u8 pkt_type;
+        __u8 incoming;
 };
 #define bt_cb(skb) ((struct bt_skb_cb *)(skb->cb)) 
 
-static inline struct sk_buff *bt_skb_alloc(unsigned int len, int how)
+static inline struct sk_buff *bt_skb_alloc(unsigned int len, unsigned int __nocast how)
 {
         struct sk_buff *skb;
 
@@ -174,8 +169,6 @@ static inline int skb_frags_no(struct sk_buff *skb)
         return n;
 }
 
-void bt_dump(char *pref, __u8 *buf, int count);
-
 int bt_err(__u16 code);
 
 #endif /* __BLUETOOTH_H */
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index 6f0706f4af68..371e7d3f2e6f 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -453,6 +453,15 @@ struct inquiry_info_with_rssi {
         __u16    clock_offset;
         __s8     rssi;
 } __attribute__ ((packed));
+struct inquiry_info_with_rssi_and_pscan_mode {
+        bdaddr_t bdaddr;
+        __u8     pscan_rep_mode;
+        __u8     pscan_period_mode;
+        __u8     pscan_mode;
+        __u8     dev_class[3];
+        __u16    clock_offset;
+        __s8     rssi;
+} __attribute__ ((packed));
 
 #define HCI_EV_CONN_COMPLETE    0x03
 struct hci_ev_conn_complete {
@@ -584,6 +593,12 @@ struct hci_ev_clock_offset {
         __u16    clock_offset;
 } __attribute__ ((packed));
 
+#define HCI_EV_PSCAN_REP_MODE   0x20
+struct hci_ev_pscan_rep_mode {
+        bdaddr_t bdaddr;
+        __u8     pscan_rep_mode;
+} __attribute__ ((packed));
+
 /* Internal events generated by Bluetooth stack */
 #define HCI_EV_STACK_INTERNAL   0xFD
 struct hci_ev_stack_internal {
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 6d63a47c731b..7f933f302078 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -404,7 +404,7 @@ static inline int hci_recv_frame(struct sk_buff *skb)
         bt_cb(skb)->incoming = 1;
 
         /* Time stamp */
-        do_gettimeofday(&skb->stamp);
+        __net_timestamp(skb);
 
         /* Queue frame for rx task */
         skb_queue_tail(&hdev->rx_q, skb);
diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h
index 13669bad00b3..ffea9d54071f 100644
--- a/include/net/bluetooth/rfcomm.h
+++ b/include/net/bluetooth/rfcomm.h
@@ -80,9 +80,9 @@
 #define RFCOMM_RPN_STOP_15      1
 
 #define RFCOMM_RPN_PARITY_NONE  0x0
-#define RFCOMM_RPN_PARITY_ODD   0x4
-#define RFCOMM_RPN_PARITY_EVEN  0x5
-#define RFCOMM_RPN_PARITY_MARK  0x6
+#define RFCOMM_RPN_PARITY_ODD   0x1
+#define RFCOMM_RPN_PARITY_EVEN  0x3
+#define RFCOMM_RPN_PARITY_MARK  0x5
 #define RFCOMM_RPN_PARITY_SPACE 0x7
 
 #define RFCOMM_RPN_FLOW_NONE    0x00
@@ -223,8 +223,14 @@ struct rfcomm_dlc {
 #define RFCOMM_CFC_DISABLED 0
 #define RFCOMM_CFC_ENABLED  RFCOMM_MAX_CREDITS
 
+/* ---- RFCOMM SEND RPN ---- */
+int rfcomm_send_rpn(struct rfcomm_session *s, int cr, u8 dlci,
+                        u8 bit_rate, u8 data_bits, u8 stop_bits,
+                        u8 parity, u8 flow_ctrl_settings, 
+                        u8 xon_char, u8 xoff_char, u16 param_mask);
+
 /* ---- RFCOMM DLCs (channels) ---- */
-struct rfcomm_dlc *rfcomm_dlc_alloc(int prio);
+struct rfcomm_dlc *rfcomm_dlc_alloc(unsigned int __nocast prio);
 void rfcomm_dlc_free(struct rfcomm_dlc *d);
 int  rfcomm_dlc_open(struct rfcomm_dlc *d, bdaddr_t *src, bdaddr_t *dst, u8 channel);
 int  rfcomm_dlc_close(struct rfcomm_dlc *d, int reason);
diff --git a/include/net/compat.h b/include/net/compat.h
index 9983fd857804..482eb820f13a 100644
--- a/include/net/compat.h
+++ b/include/net/compat.h
@@ -33,7 +33,7 @@ extern asmlinkage long compat_sys_sendmsg(int,struct compat_msghdr __user *,unsi
 extern asmlinkage long compat_sys_recvmsg(int,struct compat_msghdr __user *,unsigned);
 extern asmlinkage long compat_sys_getsockopt(int, int, int, char __user *, int __user *);
 extern int put_cmsg_compat(struct msghdr*, int, int, int, void *);
-extern int cmsghdr_from_user_compat_to_kern(struct msghdr *, unsigned char *,
+extern int cmsghdr_from_user_compat_to_kern(struct msghdr *, struct sock *, unsigned char *,
                 int);
 
 #endif /* NET_COMPAT_H */
diff --git a/include/net/datalink.h b/include/net/datalink.h
index 5797ba3d2eb5..deb7ca75db48 100644
--- a/include/net/datalink.h
+++ b/include/net/datalink.h
@@ -9,7 +9,7 @@ struct datalink_proto {
         unsigned short  header_length;
 
         int     (*rcvfunc)(struct sk_buff *, struct net_device *,
-                                struct packet_type *);
+                                struct packet_type *, struct net_device *);
         int     (*request)(struct datalink_proto *, struct sk_buff *,
                                         unsigned char *);
         struct list_head node;
diff --git a/include/net/dn.h b/include/net/dn.h
index 5551c46db397..c1dbbd222793 100644
--- a/include/net/dn.h
+++ b/include/net/dn.h
@@ -3,6 +3,7 @@
 
 #include <linux/dn.h>
 #include <net/sock.h>
+#include <net/tcp.h>
 #include <asm/byteorder.h>
 
 typedef unsigned short dn_address;
diff --git a/include/net/icmp.h b/include/net/icmp.h
index e5ef0d15fb45..6cdebeee5f96 100644
--- a/include/net/icmp.h
+++ b/include/net/icmp.h
@@ -57,4 +57,11 @@ static inline struct raw_sock *raw_sk(const struct sock *sk)
         return (struct raw_sock *)sk;
 }
 
+extern int sysctl_icmp_echo_ignore_all;
+extern int sysctl_icmp_echo_ignore_broadcasts;
+extern int sysctl_icmp_ignore_bogus_error_responses;
+extern int sysctl_icmp_errors_use_inbound_ifaddr;
+extern int sysctl_icmp_ratelimit;
+extern int sysctl_icmp_ratemask;
+
 #endif  /* _ICMP_H */
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
new file mode 100644
index 000000000000..dc36b1be6745
--- /dev/null
+++ b/include/net/ieee80211.h
@@ -0,0 +1,855 @@
+/*
+ * Merged with mainline ieee80211.h in Aug 2004.  Original ieee802_11
+ * remains copyright by the original authors
+ *
+ * Portions of the merged code are based on Host AP (software wireless
+ * LAN access point) driver for Intersil Prism2/2.5/3.
+ *
+ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
+ * <jkmaline@cc.hut.fi>
+ * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
+ *
+ * Adaption to a generic IEEE 802.11 stack by James Ketrenos
+ * <jketreno@linux.intel.com>
+ * Copyright (c) 2004, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation. See README and COPYING for
+ * more details.
+ */
+#ifndef IEEE80211_H
+#define IEEE80211_H
+#include <linux/if_ether.h> /* ETH_ALEN */
+#include <linux/kernel.h>   /* ARRAY_SIZE */
+#include <linux/wireless.h>
+
+#define IEEE80211_DATA_LEN              2304
+/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
+   6.2.1.1.2.
+
+   The figure in section 7.1.2 suggests a body size of up to 2312
+   bytes is allowed, which is a bit confusing, I suspect this
+   represents the 2304 bytes of real data, plus a possible 8 bytes of
+   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
+
+
+#define IEEE80211_HLEN                  30
+#define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
+
+struct ieee80211_hdr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 addr4[ETH_ALEN];
+} __attribute__ ((packed));
+
+struct ieee80211_hdr_3addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+} __attribute__ ((packed));
+
+#define IEEE80211_1ADDR_LEN 10
+#define IEEE80211_2ADDR_LEN 16
+#define IEEE80211_3ADDR_LEN 24
+#define IEEE80211_4ADDR_LEN 30
+#define IEEE80211_FCS_LEN    4
+
+#define MIN_FRAG_THRESHOLD     256U
+#define MAX_FRAG_THRESHOLD     2346U
+
+/* Frame control field constants */
+#define IEEE80211_FCTL_VERS             0x0003
+#define IEEE80211_FCTL_FTYPE            0x000c
+#define IEEE80211_FCTL_STYPE            0x00f0
+#define IEEE80211_FCTL_TODS             0x0100
+#define IEEE80211_FCTL_FROMDS           0x0200
+#define IEEE80211_FCTL_MOREFRAGS        0x0400
+#define IEEE80211_FCTL_RETRY            0x0800
+#define IEEE80211_FCTL_PM               0x1000
+#define IEEE80211_FCTL_MOREDATA         0x2000
+#define IEEE80211_FCTL_PROTECTED        0x4000
+#define IEEE80211_FCTL_ORDER            0x8000
+
+#define IEEE80211_FTYPE_MGMT            0x0000
+#define IEEE80211_FTYPE_CTL             0x0004
+#define IEEE80211_FTYPE_DATA            0x0008
+
+/* management */
+#define IEEE80211_STYPE_ASSOC_REQ       0x0000
+#define IEEE80211_STYPE_ASSOC_RESP      0x0010
+#define IEEE80211_STYPE_REASSOC_REQ     0x0020
+#define IEEE80211_STYPE_REASSOC_RESP    0x0030
+#define IEEE80211_STYPE_PROBE_REQ       0x0040
+#define IEEE80211_STYPE_PROBE_RESP      0x0050
+#define IEEE80211_STYPE_BEACON          0x0080
+#define IEEE80211_STYPE_ATIM            0x0090
+#define IEEE80211_STYPE_DISASSOC        0x00A0
+#define IEEE80211_STYPE_AUTH            0x00B0
+#define IEEE80211_STYPE_DEAUTH          0x00C0
+#define IEEE80211_STYPE_ACTION          0x00D0
+
+/* control */
+#define IEEE80211_STYPE_PSPOLL          0x00A0
+#define IEEE80211_STYPE_RTS             0x00B0
+#define IEEE80211_STYPE_CTS             0x00C0
+#define IEEE80211_STYPE_ACK             0x00D0
+#define IEEE80211_STYPE_CFEND           0x00E0
+#define IEEE80211_STYPE_CFENDACK        0x00F0
+
+/* data */
+#define IEEE80211_STYPE_DATA            0x0000
+#define IEEE80211_STYPE_DATA_CFACK      0x0010
+#define IEEE80211_STYPE_DATA_CFPOLL     0x0020
+#define IEEE80211_STYPE_DATA_CFACKPOLL  0x0030
+#define IEEE80211_STYPE_NULLFUNC        0x0040
+#define IEEE80211_STYPE_CFACK           0x0050
+#define IEEE80211_STYPE_CFPOLL          0x0060
+#define IEEE80211_STYPE_CFACKPOLL       0x0070
+
+#define IEEE80211_SCTL_FRAG             0x000F
+#define IEEE80211_SCTL_SEQ              0xFFF0
+
+
+/* debug macros */
+
+#ifdef CONFIG_IEEE80211_DEBUG
+extern u32 ieee80211_debug_level;
+#define IEEE80211_DEBUG(level, fmt, args...) \
+do { if (ieee80211_debug_level & (level)) \
+  printk(KERN_DEBUG "ieee80211: %c %s " fmt, \
+         in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
+#else
+#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0)
+#endif  /* CONFIG_IEEE80211_DEBUG */
+
+
+/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */
+
+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
+#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
+
+/* escape_essid() is intended to be used in debug (and possibly error)
+ * messages. It should never be used for passing essid to user space. */
+const char *escape_essid(const char *essid, u8 essid_len);
+
+
+/*
+ * To use the debug system:
+ *
+ * If you are defining a new debug classification, simply add it to the #define
+ * list here in the form of:
+ *
+ * #define IEEE80211_DL_xxxx VALUE
+ *
+ * shifting value to the left one bit from the previous entry.  xxxx should be
+ * the name of the classification (for example, WEP)
+ *
+ * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your
+ * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want
+ * to send output to that classification.
+ *
+ * To add your debug level to the list of levels seen when you perform
+ *
+ * % cat /proc/net/ieee80211/debug_level
+ *
+ * you simply need to add your entry to the ieee80211_debug_level array.
+ *
+ * If you do not see debug_level in /proc/net/ieee80211 then you do not have
+ * CONFIG_IEEE80211_DEBUG defined in your kernel configuration
+ *
+ */
+
+#define IEEE80211_DL_INFO          (1<<0)
+#define IEEE80211_DL_WX            (1<<1)
+#define IEEE80211_DL_SCAN          (1<<2)
+#define IEEE80211_DL_STATE         (1<<3)
+#define IEEE80211_DL_MGMT          (1<<4)
+#define IEEE80211_DL_FRAG          (1<<5)
+#define IEEE80211_DL_DROP          (1<<7)
+
+#define IEEE80211_DL_TX            (1<<8)
+#define IEEE80211_DL_RX            (1<<9)
+
+#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a)
+#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a)
+#define IEEE80211_DEBUG_INFO(f, a...)   IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a)
+
+#define IEEE80211_DEBUG_WX(f, a...)     IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a)
+#define IEEE80211_DEBUG_SCAN(f, a...)   IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a)
+#define IEEE80211_DEBUG_STATE(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a)
+#define IEEE80211_DEBUG_MGMT(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a)
+#define IEEE80211_DEBUG_FRAG(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a)
+#define IEEE80211_DEBUG_DROP(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a)
+#define IEEE80211_DEBUG_TX(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a)
+#define IEEE80211_DEBUG_RX(f, a...)  IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a)
+#include <linux/netdevice.h>
+#include <linux/wireless.h>
+#include <linux/if_arp.h> /* ARPHRD_ETHER */
+
+#ifndef WIRELESS_SPY
+#define WIRELESS_SPY            /* enable iwspy support */
+#endif
+#include <net/iw_handler.h>     /* new driver API */
+
+#ifndef ETH_P_PAE
+#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
+#endif /* ETH_P_PAE */
+
+#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
+
+#ifndef ETH_P_80211_RAW
+#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
+#endif
+
+/* IEEE 802.11 defines */
+
+#define P80211_OUI_LEN 3
+
+struct ieee80211_snap_hdr {
+
+        u8    dsap;   /* always 0xAA */
+        u8    ssap;   /* always 0xAA */
+        u8    ctrl;   /* always 0x03 */
+        u8    oui[P80211_OUI_LEN];    /* organizational universal id */
+
+} __attribute__ ((packed));
+
+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
+
+#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
+#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
+#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
+
+#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG)
+#define WLAN_GET_SEQ_SEQ(seq)  ((seq) & IEEE80211_SCTL_SEQ)
+
+/* Authentication algorithms */
+#define WLAN_AUTH_OPEN 0
+#define WLAN_AUTH_SHARED_KEY 1
+
+#define WLAN_AUTH_CHALLENGE_LEN 128
+
+#define WLAN_CAPABILITY_ESS (1<<0)
+#define WLAN_CAPABILITY_IBSS (1<<1)
+#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
+#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
+#define WLAN_CAPABILITY_PRIVACY (1<<4)
+#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
+#define WLAN_CAPABILITY_PBCC (1<<6)
+#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
+#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
+#define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10)
+#define WLAN_CAPABILITY_OSSS_OFDM (1<<13)
+
+/* Status codes */
+enum ieee80211_statuscode {
+        WLAN_STATUS_SUCCESS = 0,
+        WLAN_STATUS_UNSPECIFIED_FAILURE = 1,
+        WLAN_STATUS_CAPS_UNSUPPORTED = 10,
+        WLAN_STATUS_REASSOC_NO_ASSOC = 11,
+        WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,
+        WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,
+        WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,
+        WLAN_STATUS_CHALLENGE_FAIL = 15,
+        WLAN_STATUS_AUTH_TIMEOUT = 16,
+        WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,
+        WLAN_STATUS_ASSOC_DENIED_RATES = 18,
+        /* 802.11b */
+        WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,
+        WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,
+        WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,
+        /* 802.11h */
+        WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,
+        WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,
+        WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,
+        /* 802.11g */
+        WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,
+        WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,
+        /* 802.11i */
+        WLAN_STATUS_INVALID_IE = 40,
+        WLAN_STATUS_INVALID_GROUP_CIPHER = 41,
+        WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,
+        WLAN_STATUS_INVALID_AKMP = 43,
+        WLAN_STATUS_UNSUPP_RSN_VERSION = 44,
+        WLAN_STATUS_INVALID_RSN_IE_CAP = 45,
+        WLAN_STATUS_CIPHER_SUITE_REJECTED = 46,
+};
+
+/* Reason codes */
+enum ieee80211_reasoncode {
+        WLAN_REASON_UNSPECIFIED = 1,
+        WLAN_REASON_PREV_AUTH_NOT_VALID = 2,
+        WLAN_REASON_DEAUTH_LEAVING = 3,
+        WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,
+        WLAN_REASON_DISASSOC_AP_BUSY = 5,
+        WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,
+        WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,
+        WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,
+        WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,
+        /* 802.11h */
+        WLAN_REASON_DISASSOC_BAD_POWER = 10,
+        WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,
+        /* 802.11i */
+        WLAN_REASON_INVALID_IE = 13,
+        WLAN_REASON_MIC_FAILURE = 14,
+        WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
+        WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,
+        WLAN_REASON_IE_DIFFERENT = 17,
+        WLAN_REASON_INVALID_GROUP_CIPHER = 18,
+        WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,
+        WLAN_REASON_INVALID_AKMP = 20,
+        WLAN_REASON_UNSUPP_RSN_VERSION = 21,
+        WLAN_REASON_INVALID_RSN_IE_CAP = 22,
+        WLAN_REASON_IEEE8021X_FAILED = 23,
+        WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
+};
+
+
+#define IEEE80211_STATMASK_SIGNAL (1<<0)
+#define IEEE80211_STATMASK_RSSI (1<<1)
+#define IEEE80211_STATMASK_NOISE (1<<2)
+#define IEEE80211_STATMASK_RATE (1<<3)
+#define IEEE80211_STATMASK_WEMASK 0x7
+
+
+#define IEEE80211_CCK_MODULATION    (1<<0)
+#define IEEE80211_OFDM_MODULATION   (1<<1)
+
+#define IEEE80211_24GHZ_BAND     (1<<0)
+#define IEEE80211_52GHZ_BAND     (1<<1)
+
+#define IEEE80211_CCK_RATE_1MB                  0x02
+#define IEEE80211_CCK_RATE_2MB                  0x04
+#define IEEE80211_CCK_RATE_5MB                  0x0B
+#define IEEE80211_CCK_RATE_11MB                 0x16
+#define IEEE80211_OFDM_RATE_6MB                 0x0C
+#define IEEE80211_OFDM_RATE_9MB                 0x12
+#define IEEE80211_OFDM_RATE_12MB                0x18
+#define IEEE80211_OFDM_RATE_18MB                0x24
+#define IEEE80211_OFDM_RATE_24MB                0x30
+#define IEEE80211_OFDM_RATE_36MB                0x48
+#define IEEE80211_OFDM_RATE_48MB                0x60
+#define IEEE80211_OFDM_RATE_54MB                0x6C
+#define IEEE80211_BASIC_RATE_MASK               0x80
+
+#define IEEE80211_CCK_RATE_1MB_MASK             (1<<0)
+#define IEEE80211_CCK_RATE_2MB_MASK             (1<<1)
+#define IEEE80211_CCK_RATE_5MB_MASK             (1<<2)
+#define IEEE80211_CCK_RATE_11MB_MASK            (1<<3)
+#define IEEE80211_OFDM_RATE_6MB_MASK            (1<<4)
+#define IEEE80211_OFDM_RATE_9MB_MASK            (1<<5)
+#define IEEE80211_OFDM_RATE_12MB_MASK           (1<<6)
+#define IEEE80211_OFDM_RATE_18MB_MASK           (1<<7)
+#define IEEE80211_OFDM_RATE_24MB_MASK           (1<<8)
+#define IEEE80211_OFDM_RATE_36MB_MASK           (1<<9)
+#define IEEE80211_OFDM_RATE_48MB_MASK           (1<<10)
+#define IEEE80211_OFDM_RATE_54MB_MASK           (1<<11)
+
+#define IEEE80211_CCK_RATES_MASK                0x0000000F
+#define IEEE80211_CCK_BASIC_RATES_MASK  (IEEE80211_CCK_RATE_1MB_MASK | \
+        IEEE80211_CCK_RATE_2MB_MASK)
+#define IEEE80211_CCK_DEFAULT_RATES_MASK        (IEEE80211_CCK_BASIC_RATES_MASK | \
+        IEEE80211_CCK_RATE_5MB_MASK | \
+        IEEE80211_CCK_RATE_11MB_MASK)
+
+#define IEEE80211_OFDM_RATES_MASK               0x00000FF0
+#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
+        IEEE80211_OFDM_RATE_12MB_MASK | \
+        IEEE80211_OFDM_RATE_24MB_MASK)
+#define IEEE80211_OFDM_DEFAULT_RATES_MASK       (IEEE80211_OFDM_BASIC_RATES_MASK | \
+        IEEE80211_OFDM_RATE_9MB_MASK  | \
+        IEEE80211_OFDM_RATE_18MB_MASK | \
+        IEEE80211_OFDM_RATE_36MB_MASK | \
+        IEEE80211_OFDM_RATE_48MB_MASK | \
+        IEEE80211_OFDM_RATE_54MB_MASK)
+#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
+                                IEEE80211_CCK_DEFAULT_RATES_MASK)
+
+#define IEEE80211_NUM_OFDM_RATES            8
+#define IEEE80211_NUM_CCK_RATES             4
+#define IEEE80211_OFDM_SHIFT_MASK_A         4
+
+
+
+
+/* NOTE: This data is for statistical purposes; not all hardware provides this
+ *       information for frames received.  Not setting these will not cause
+ *       any adverse affects. */
+struct ieee80211_rx_stats {
+        u32 mac_time;
+        s8 rssi;
+        u8 signal;
+        u8 noise;
+        u16 rate; /* in 100 kbps */
+        u8 received_channel;
+        u8 control;
+        u8 mask;
+        u8 freq;
+        u16 len;
+};
+
+/* IEEE 802.11 requires that STA supports concurrent reception of at least
+ * three fragmented frames. This define can be increased to support more
+ * concurrent frames, but it should be noted that each entry can consume about
+ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
+#define IEEE80211_FRAG_CACHE_LEN 4
+
+struct ieee80211_frag_entry {
+        unsigned long first_frag_time;
+        unsigned int seq;
+        unsigned int last_frag;
+        struct sk_buff *skb;
+        u8 src_addr[ETH_ALEN];
+        u8 dst_addr[ETH_ALEN];
+};
+
+struct ieee80211_stats {
+        unsigned int tx_unicast_frames;
+        unsigned int tx_multicast_frames;
+        unsigned int tx_fragments;
+        unsigned int tx_unicast_octets;
+        unsigned int tx_multicast_octets;
+        unsigned int tx_deferred_transmissions;
+        unsigned int tx_single_retry_frames;
+        unsigned int tx_multiple_retry_frames;
+        unsigned int tx_retry_limit_exceeded;
+        unsigned int tx_discards;
+        unsigned int rx_unicast_frames;
+        unsigned int rx_multicast_frames;
+        unsigned int rx_fragments;
+        unsigned int rx_unicast_octets;
+        unsigned int rx_multicast_octets;
+        unsigned int rx_fcs_errors;
+        unsigned int rx_discards_no_buffer;
+        unsigned int tx_discards_wrong_sa;
+        unsigned int rx_discards_undecryptable;
+        unsigned int rx_message_in_msg_fragments;
+        unsigned int rx_message_in_bad_msg_fragments;
+};
+
+struct ieee80211_device;
+
+#include "ieee80211_crypt.h"
+
+#define SEC_KEY_1         (1<<0)
+#define SEC_KEY_2         (1<<1)
+#define SEC_KEY_3         (1<<2)
+#define SEC_KEY_4         (1<<3)
+#define SEC_ACTIVE_KEY    (1<<4)
+#define SEC_AUTH_MODE     (1<<5)
+#define SEC_UNICAST_GROUP (1<<6)
+#define SEC_LEVEL         (1<<7)
+#define SEC_ENABLED       (1<<8)
+
+#define SEC_LEVEL_0      0 /* None */
+#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */
+#define SEC_LEVEL_2      2 /* Level 1 + TKIP */
+#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
+#define SEC_LEVEL_3      4 /* Level 2 + CCMP */
+
+#define WEP_KEYS 4
+#define WEP_KEY_LEN 13
+
+struct ieee80211_security {
+        u16 active_key:2,
+            enabled:1,
+            auth_mode:2,
+            auth_algo:4,
+            unicast_uses_group:1;
+        u8 key_sizes[WEP_KEYS];
+        u8 keys[WEP_KEYS][WEP_KEY_LEN];
+        u8 level;
+        u16 flags;
+} __attribute__ ((packed));
+
+
+/*
+
+ 802.11 data frame from AP
+
+      ,-------------------------------------------------------------------.
+Bytes |  2   |  2   |    6    |    6    |    6    |  2   | 0..2312 |   4  |
+      |------|------|---------|---------|---------|------|---------|------|
+Desc. | ctrl | dura |  DA/RA  |   TA    |    SA   | Sequ |  frame  |  fcs |
+      |      | tion | (BSSID) |         |         | ence |  data   |      |
+      `-------------------------------------------------------------------'
+
+Total: 28-2340 bytes
+
+*/
+
+#define BEACON_PROBE_SSID_ID_POSITION 12
+
+/* Management Frame Information Element Types */
+enum ieee80211_mfie {
+        MFIE_TYPE_SSID = 0,
+        MFIE_TYPE_RATES = 1,
+        MFIE_TYPE_FH_SET = 2,
+        MFIE_TYPE_DS_SET = 3,
+        MFIE_TYPE_CF_SET =  4,
+        MFIE_TYPE_TIM = 5,
+        MFIE_TYPE_IBSS_SET = 6,
+        MFIE_TYPE_COUNTRY = 7,
+        MFIE_TYPE_HOP_PARAMS = 8,
+        MFIE_TYPE_HOP_TABLE = 9,
+        MFIE_TYPE_REQUEST = 10,
+        MFIE_TYPE_CHALLENGE = 16,
+        MFIE_TYPE_POWER_CONSTRAINT = 32,
+        MFIE_TYPE_POWER_CAPABILITY = 33,
+        MFIE_TYPE_TPC_REQUEST = 34,
+        MFIE_TYPE_TPC_REPORT = 35,
+        MFIE_TYPE_SUPP_CHANNELS = 36,
+        MFIE_TYPE_CSA = 37,
+        MFIE_TYPE_MEASURE_REQUEST = 38,
+        MFIE_TYPE_MEASURE_REPORT = 39,
+        MFIE_TYPE_QUIET = 40,
+        MFIE_TYPE_IBSS_DFS = 41,
+        MFIE_TYPE_ERP_INFO = 42,
+        MFIE_TYPE_RSN = 48,
+        MFIE_TYPE_RATES_EX = 50,
+        MFIE_TYPE_GENERIC = 221,
+};
+
+struct ieee80211_info_element_hdr {
+        u8 id;
+        u8 len;
+} __attribute__ ((packed));
+
+struct ieee80211_info_element {
+        u8 id;
+        u8 len;
+        u8 data[0];
+} __attribute__ ((packed));
+
+/*
+ * These are the data types that can make up management packets
+ *
+        u16 auth_algorithm;
+        u16 auth_sequence;
+        u16 beacon_interval;
+        u16 capability;
+        u8 current_ap[ETH_ALEN];
+        u16 listen_interval;
+        struct {
+                u16 association_id:14, reserved:2;
+        } __attribute__ ((packed));
+        u32 time_stamp[2];
+        u16 reason;
+        u16 status;
+*/
+
+struct ieee80211_authentication {
+        struct ieee80211_hdr_3addr header;
+        __le16 algorithm;
+        __le16 transaction;
+        __le16 status;
+        struct ieee80211_info_element info_element;
+} __attribute__ ((packed));
+
+
+struct ieee80211_probe_response {
+        struct ieee80211_hdr_3addr header;
+        u32 time_stamp[2];
+        __le16 beacon_interval;
+        __le16 capability;
+        struct ieee80211_info_element info_element;
+} __attribute__ ((packed));
+
+struct ieee80211_assoc_request_frame {
+        __le16 capability;
+        __le16 listen_interval;
+        u8 current_ap[ETH_ALEN];
+        struct ieee80211_info_element info_element;
+} __attribute__ ((packed));
+
+struct ieee80211_assoc_response_frame {
+        struct ieee80211_hdr_3addr header;
+        __le16 capability;
+        __le16 status;
+        __le16 aid;
+        struct ieee80211_info_element info_element; /* supported rates */
+} __attribute__ ((packed));
+
+
+struct ieee80211_txb {
+        u8 nr_frags;
+        u8 encrypted;
+        u16 reserved;
+        u16 frag_size;
+        u16 payload_size;
+        struct sk_buff *fragments[0];
+};
+
+
+/* SWEEP TABLE ENTRIES NUMBER */
+#define MAX_SWEEP_TAB_ENTRIES             42
+#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7
+/* MAX_RATES_LENGTH needs to be 12.  The spec says 8, and many APs
+ * only use 8, and then use extended rates for the remaining supported
+ * rates.  Other APs, however, stick all of their supported rates on the
+ * main rates information element... */
+#define MAX_RATES_LENGTH                  ((u8)12)
+#define MAX_RATES_EX_LENGTH               ((u8)16)
+#define MAX_NETWORK_COUNT                  128
+
+#define CRC_LENGTH                 4U
+
+#define MAX_WPA_IE_LEN 64
+
+#define NETWORK_EMPTY_ESSID (1<<0)
+#define NETWORK_HAS_OFDM    (1<<1)
+#define NETWORK_HAS_CCK     (1<<2)
+
+struct ieee80211_network {
+        /* These entries are used to identify a unique network */
+        u8 bssid[ETH_ALEN];
+        u8 channel;
+        /* Ensure null-terminated for any debug msgs */
+        u8 ssid[IW_ESSID_MAX_SIZE + 1];
+        u8 ssid_len;
+
+        /* These are network statistics */
+        struct ieee80211_rx_stats stats;
+        u16 capability;
+        u8 rates[MAX_RATES_LENGTH];
+        u8 rates_len;
+        u8 rates_ex[MAX_RATES_EX_LENGTH];
+        u8 rates_ex_len;
+        unsigned long last_scanned;
+        u8 mode;
+        u8 flags;
+        u32 last_associate;
+        u32 time_stamp[2];
+        u16 beacon_interval;
+        u16 listen_interval;
+        u16 atim_window;
+        u8 wpa_ie[MAX_WPA_IE_LEN];
+        size_t wpa_ie_len;
+        u8 rsn_ie[MAX_WPA_IE_LEN];
+        size_t rsn_ie_len;
+        struct list_head list;
+};
+
+enum ieee80211_state {
+        IEEE80211_UNINITIALIZED = 0,
+        IEEE80211_INITIALIZED,
+        IEEE80211_ASSOCIATING,
+        IEEE80211_ASSOCIATED,
+        IEEE80211_AUTHENTICATING,
+        IEEE80211_AUTHENTICATED,
+        IEEE80211_SHUTDOWN
+};
+
+#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
+#define DEFAULT_FTS 2346
+
+
+#define CFG_IEEE80211_RESERVE_FCS (1<<0)
+#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
+
+struct ieee80211_device {
+        struct net_device *dev;
+
+        /* Bookkeeping structures */
+        struct net_device_stats stats;
+        struct ieee80211_stats ieee_stats;
+
+        /* Probe / Beacon management */
+        struct list_head network_free_list;
+        struct list_head network_list;
+        struct ieee80211_network *networks;
+        int scans;
+        int scan_age;
+
+        int iw_mode; /* operating mode (IW_MODE_*) */
+
+        spinlock_t lock;
+
+        int tx_headroom; /* Set to size of any additional room needed at front
+                          * of allocated Tx SKBs */
+        u32 config;
+
+        /* WEP and other encryption related settings at the device level */
+        int open_wep; /* Set to 1 to allow unencrypted frames */
+
+        int reset_on_keychange; /* Set to 1 if the HW needs to be reset on
+                                 * WEP key changes */
+
+        /* If the host performs {en,de}cryption, then set to 1 */
+        int host_encrypt;
+        int host_decrypt;
+        int ieee802_1x; /* is IEEE 802.1X used */
+
+        /* WPA data */
+        int wpa_enabled;
+        int drop_unencrypted;
+        int tkip_countermeasures;
+        int privacy_invoked;
+        size_t wpa_ie_len;
+        u8 *wpa_ie;
+
+        struct list_head crypt_deinit_list;
+        struct ieee80211_crypt_data *crypt[WEP_KEYS];
+        int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */
+        struct timer_list crypt_deinit_timer;
+
+        int bcrx_sta_key; /* use individual keys to override default keys even
+                           * with RX of broad/multicast frames */
+
+        /* Fragmentation structures */
+        struct ieee80211_frag_entry frag_cache[IEEE80211_FRAG_CACHE_LEN];
+        unsigned int frag_next_idx;
+        u16 fts; /* Fragmentation Threshold */
+
+        /* Association info */
+        u8 bssid[ETH_ALEN];
+
+        enum ieee80211_state state;
+
+        int mode;       /* A, B, G */
+        int modulation; /* CCK, OFDM */
+        int freq_band;  /* 2.4Ghz, 5.2Ghz, Mixed */
+        int abg_ture;   /* ABG flag              */
+
+        /* Callback functions */
+        void (*set_security)(struct net_device *dev,
+                             struct ieee80211_security *sec);
+        int (*hard_start_xmit)(struct ieee80211_txb *txb,
+                               struct net_device *dev);
+        int (*reset_port)(struct net_device *dev);
+
+        /* This must be the last item so that it points to the data
+         * allocated beyond this structure by alloc_ieee80211 */
+        u8 priv[0];
+};
+
+#define IEEE_A            (1<<0)
+#define IEEE_B            (1<<1)
+#define IEEE_G            (1<<2)
+#define IEEE_MODE_MASK    (IEEE_A|IEEE_B|IEEE_G)
+
+extern inline void *ieee80211_priv(struct net_device *dev)
+{
+        return ((struct ieee80211_device *)netdev_priv(dev))->priv;
+}
+
+extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
+{
+        /* Single white space is for Linksys APs */
+        if (essid_len == 1 && essid[0] == ' ')
+                return 1;
+
+        /* Otherwise, if the entire essid is 0, we assume it is hidden */
+        while (essid_len) {
+                essid_len--;
+                if (essid[essid_len] != '\0')
+                        return 0;
+        }
+
+        return 1;
+}
+
+extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode)
+{
+        /*
+         * It is possible for both access points and our device to support
+         * combinations of modes, so as long as there is one valid combination
+         * of ap/device supported modes, then return success
+         *
+         */
+        if ((mode & IEEE_A) &&
+            (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
+            (ieee->freq_band & IEEE80211_52GHZ_BAND))
+                return 1;
+
+        if ((mode & IEEE_G) &&
+            (ieee->modulation & IEEE80211_OFDM_MODULATION) &&
+            (ieee->freq_band & IEEE80211_24GHZ_BAND))
+                return 1;
+
+        if ((mode & IEEE_B) &&
+            (ieee->modulation & IEEE80211_CCK_MODULATION) &&
+            (ieee->freq_band & IEEE80211_24GHZ_BAND))
+                return 1;
+
+        return 0;
+}
+
+extern inline int ieee80211_get_hdrlen(u16 fc)
+{
+        int hdrlen = IEEE80211_3ADDR_LEN;
+
+        switch (WLAN_FC_GET_TYPE(fc)) {
+        case IEEE80211_FTYPE_DATA:
+                if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))
+                        hdrlen = IEEE80211_4ADDR_LEN;
+                break;
+        case IEEE80211_FTYPE_CTL:
+                switch (WLAN_FC_GET_STYPE(fc)) {
+                case IEEE80211_STYPE_CTS:
+                case IEEE80211_STYPE_ACK:
+                        hdrlen = IEEE80211_1ADDR_LEN;
+                        break;
+                default:
+                        hdrlen = IEEE80211_2ADDR_LEN;
+                        break;
+                }
+                break;
+        }
+
+        return hdrlen;
+}
+
+
+
+/* ieee80211.c */
+extern void free_ieee80211(struct net_device *dev);
+extern struct net_device *alloc_ieee80211(int sizeof_priv);
+
+extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
+
+/* ieee80211_tx.c */
+extern int ieee80211_xmit(struct sk_buff *skb,
+                          struct net_device *dev);
+extern void ieee80211_txb_free(struct ieee80211_txb *);
+
+
+/* ieee80211_rx.c */
+extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
+                        struct ieee80211_rx_stats *rx_stats);
+extern void ieee80211_rx_mgt(struct ieee80211_device *ieee,
+                             struct ieee80211_hdr *header,
+                             struct ieee80211_rx_stats *stats);
+
+/* ieee80211_wx.c */
+extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee,
+                                 struct iw_request_info *info,
+                                 union iwreq_data *wrqu, char *key);
+extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee,
+                                   struct iw_request_info *info,
+                                   union iwreq_data *wrqu, char *key);
+extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee,
+                                   struct iw_request_info *info,
+                                   union iwreq_data *wrqu, char *key);
+
+
+extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee)
+{
+        ieee->scans++;
+}
+
+extern inline int ieee80211_get_scans(struct ieee80211_device *ieee)
+{
+        return ieee->scans;
+}
+
+
+#endif /* IEEE80211_H */
diff --git a/include/net/ieee80211_crypt.h b/include/net/ieee80211_crypt.h
new file mode 100644
index 000000000000..b58a3bcc0dc0
--- /dev/null
+++ b/include/net/ieee80211_crypt.h
@@ -0,0 +1,86 @@
+/*
+ * Original code based on Host AP (software wireless LAN access point) driver
+ * for Intersil Prism2/2.5/3.
+ *
+ * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
+ * <jkmaline@cc.hut.fi>
+ * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
+ *
+ * Adaption to a generic IEEE 802.11 stack by James Ketrenos
+ * <jketreno@linux.intel.com>
+ *
+ * Copyright (c) 2004, Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation. See README and COPYING for
+ * more details.
+ */
+
+/*
+ * This file defines the interface to the ieee80211 crypto module.
+ */
+#ifndef IEEE80211_CRYPT_H
+#define IEEE80211_CRYPT_H
+
+#include <linux/skbuff.h>
+
+struct ieee80211_crypto_ops {
+        const char *name;
+
+        /* init new crypto context (e.g., allocate private data space,
+         * select IV, etc.); returns NULL on failure or pointer to allocated
+         * private data on success */
+        void * (*init)(int keyidx);
+
+        /* deinitialize crypto context and free allocated private data */
+        void (*deinit)(void *priv);
+
+        /* encrypt/decrypt return < 0 on error or >= 0 on success. The return
+         * value from decrypt_mpdu is passed as the keyidx value for
+         * decrypt_msdu. skb must have enough head and tail room for the
+         * encryption; if not, error will be returned; these functions are
+         * called for all MPDUs (i.e., fragments).
+         */
+        int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
+        int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv);
+
+        /* These functions are called for full MSDUs, i.e. full frames.
+         * These can be NULL if full MSDU operations are not needed. */
+        int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv);
+        int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len,
+                            void *priv);
+
+        int (*set_key)(void *key, int len, u8 *seq, void *priv);
+        int (*get_key)(void *key, int len, u8 *seq, void *priv);
+
+        /* procfs handler for printing out key information and possible
+         * statistics */
+        char * (*print_stats)(char *p, void *priv);
+
+        /* maximum number of bytes added by encryption; encrypt buf is
+         * allocated with extra_prefix_len bytes, copy of in_buf, and
+         * extra_postfix_len; encrypt need not use all this space, but
+         * the result must start at the beginning of the buffer and correct
+         * length must be returned */
+        int extra_prefix_len, extra_postfix_len;
+
+        struct module *owner;
+};
+
+struct ieee80211_crypt_data {
+        struct list_head list; /* delayed deletion list */
+        struct ieee80211_crypto_ops *ops;
+        void *priv;
+        atomic_t refcnt;
+};
+
+int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops);
+int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops);
+struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name);
+void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int);
+void ieee80211_crypt_deinit_handler(unsigned long);
+void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
+                                    struct ieee80211_crypt_data **crypt);
+
+#endif
diff --git a/include/net/inet6_hashtables.h b/include/net/inet6_hashtables.h
new file mode 100644
index 000000000000..03df3b157960
--- /dev/null
+++ b/include/net/inet6_hashtables.h
@@ -0,0 +1,130 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ * Authors:     Lotsa people, from code originally in tcp
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _INET6_HASHTABLES_H
+#define _INET6_HASHTABLES_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE)
+#include <linux/in6.h>
+#include <linux/ipv6.h>
+#include <linux/types.h>
+
+#include <net/ipv6.h>
+
+struct inet_hashinfo;
+
+/* I have no idea if this is a good hash for v6 or not. -DaveM */
+static inline int inet6_ehashfn(const struct in6_addr *laddr, const u16 lport,
+                                const struct in6_addr *faddr, const u16 fport,
+                                const int ehash_size)
+{
+        int hashent = (lport ^ fport);
+
+        hashent ^= (laddr->s6_addr32[3] ^ faddr->s6_addr32[3]);
+        hashent ^= hashent >> 16;
+        hashent ^= hashent >> 8;
+        return (hashent & (ehash_size - 1));
+}
+
+static inline int inet6_sk_ehashfn(const struct sock *sk, const int ehash_size)
+{
+        const struct inet_sock *inet = inet_sk(sk);
+        const struct ipv6_pinfo *np = inet6_sk(sk);
+        const struct in6_addr *laddr = &np->rcv_saddr;
+        const struct in6_addr *faddr = &np->daddr;
+        const __u16 lport = inet->num;
+        const __u16 fport = inet->dport;
+        return inet6_ehashfn(laddr, lport, faddr, fport, ehash_size);
+}
+
+/*
+ * Sockets in TCP_CLOSE state are _always_ taken out of the hash, so
+ * we need not check it for TCP lookups anymore, thanks Alexey. -DaveM
+ *
+ * The sockhash lock must be held as a reader here.
+ */
+static inline struct sock *
+                __inet6_lookup_established(struct inet_hashinfo *hashinfo,
+                                           const struct in6_addr *saddr,
+                                           const u16 sport,
+                                           const struct in6_addr *daddr,
+                                           const u16 hnum,
+                                           const int dif)
+{
+        struct sock *sk;
+        const struct hlist_node *node;
+        const __u32 ports = INET_COMBINED_PORTS(sport, hnum);
+        /* Optimize here for direct hit, only listening connections can
+         * have wildcards anyways.
+         */
+        const int hash = inet6_ehashfn(daddr, hnum, saddr, sport,
+                                       hashinfo->ehash_size);
+        struct inet_ehash_bucket *head = &hashinfo->ehash[hash];
+
+        read_lock(&head->lock);
+        sk_for_each(sk, node, &head->chain) {
+                /* For IPV6 do the cheaper port and family tests first. */
+                if (INET6_MATCH(sk, saddr, daddr, ports, dif))
+                        goto hit; /* You sunk my battleship! */
+        }
+        /* Must check for a TIME_WAIT'er before going to listener hash. */
+        sk_for_each(sk, node, &(head + hashinfo->ehash_size)->chain) {
+                const struct inet_timewait_sock *tw = inet_twsk(sk);
+
+                if(*((__u32 *)&(tw->tw_dport))  == ports        &&
+                   sk->sk_family                == PF_INET6) {
+                        const struct tcp6_timewait_sock *tcp6tw = tcp6_twsk(sk);
+
+                        if (ipv6_addr_equal(&tcp6tw->tw_v6_daddr, saddr)        &&
+                            ipv6_addr_equal(&tcp6tw->tw_v6_rcv_saddr, daddr)    &&
+                            (!sk->sk_bound_dev_if || sk->sk_bound_dev_if == dif))
+                                goto hit;
+                }
+        }
+        read_unlock(&head->lock);
+        return NULL;
+
+hit:
+        sock_hold(sk);
+        read_unlock(&head->lock);
+        return sk;
+}
+
+extern struct sock *inet6_lookup_listener(struct inet_hashinfo *hashinfo,
+                                          const struct in6_addr *daddr,
+                                          const unsigned short hnum,
+                                          const int dif);
+
+static inline struct sock *__inet6_lookup(struct inet_hashinfo *hashinfo,
+                                          const struct in6_addr *saddr,
+                                          const u16 sport,
+                                          const struct in6_addr *daddr,
+                                          const u16 hnum,
+                                          const int dif)
+{
+        struct sock *sk = __inet6_lookup_established(hashinfo, saddr, sport,
+                                                     daddr, hnum, dif);
+        if (sk)
+                return sk;
+
+        return inet6_lookup_listener(hashinfo, daddr, hnum, dif);
+}
+
+extern struct sock *inet6_lookup(struct inet_hashinfo *hashinfo,
+                                 const struct in6_addr *saddr, const u16 sport,
+                                 const struct in6_addr *daddr, const u16 dport,
+                                 const int dif);
+#endif /* defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) */
+#endif /* _INET6_HASHTABLES_H */
diff --git a/include/net/inet_common.h b/include/net/inet_common.h
index fbc1f4d140d8..f943306ce5ff 100644
--- a/include/net/inet_common.h
+++ b/include/net/inet_common.h
@@ -8,6 +8,11 @@ extern struct proto_ops		inet_dgram_ops;
  *      INET4 prototypes used by INET6
  */
 
+struct msghdr;
+struct sock;
+struct sockaddr;
+struct socket;
+
 extern void                     inet_remove_sock(struct sock *sk1);
 extern void                     inet_put_sock(unsigned short num, 
                                               struct sock *sk);
@@ -29,7 +34,6 @@ extern unsigned int		inet_poll(struct file * file, struct socket *sock, struct p
 extern int                      inet_listen(struct socket *sock, int backlog);
 
 extern void                     inet_sock_destruct(struct sock *sk);
-extern atomic_t                 inet_sock_nr;
 
 extern int                      inet_bind(struct socket *sock, 
                                           struct sockaddr *uaddr, int addr_len);
diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h
new file mode 100644
index 000000000000..651f824c1008
--- /dev/null
+++ b/include/net/inet_connection_sock.h
@@ -0,0 +1,276 @@
+/*
+ * NET          Generic infrastructure for INET connection oriented protocols.
+ *
+ *              Definitions for inet_connection_sock 
+ *
+ * Authors:     Many people, see the TCP sources
+ *
+ *              From code originally in TCP
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+#ifndef _INET_CONNECTION_SOCK_H
+#define _INET_CONNECTION_SOCK_H
+
+#include <linux/ip.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <net/request_sock.h>
+
+#define INET_CSK_DEBUG 1
+
+/* Cancel timers, when they are not required. */
+#undef INET_CSK_CLEAR_TIMERS
+
+struct inet_bind_bucket;
+struct inet_hashinfo;
+struct tcp_congestion_ops;
+
+/** inet_connection_sock - INET connection oriented sock
+ *
+ * @icsk_accept_queue:     FIFO of established children 
+ * @icsk_bind_hash:        Bind node
+ * @icsk_timeout:          Timeout
+ * @icsk_retransmit_timer: Resend (no ack)
+ * @icsk_rto:              Retransmit timeout
+ * @icsk_ca_ops            Pluggable congestion control hook
+ * @icsk_ca_state:         Congestion control state
+ * @icsk_retransmits:      Number of unrecovered [RTO] timeouts
+ * @icsk_pending:          Scheduled timer event
+ * @icsk_backoff:          Backoff
+ * @icsk_syn_retries:      Number of allowed SYN (or equivalent) retries
+ * @icsk_probes_out:       unanswered 0 window probes
+ * @icsk_ack:              Delayed ACK control data
+ */
+struct inet_connection_sock {
+        /* inet_sock has to be the first member! */
+        struct inet_sock          icsk_inet;
+        struct request_sock_queue icsk_accept_queue;
+        struct inet_bind_bucket   *icsk_bind_hash;
+        unsigned long             icsk_timeout;
+        struct timer_list         icsk_retransmit_timer;
+        struct timer_list         icsk_delack_timer;
+        __u32                     icsk_rto;
+        struct tcp_congestion_ops *icsk_ca_ops;
+        __u8                      icsk_ca_state;
+        __u8                      icsk_retransmits;
+        __u8                      icsk_pending;
+        __u8                      icsk_backoff;
+        __u8                      icsk_syn_retries;
+        __u8                      icsk_probes_out;
+        /* 2 BYTES HOLE, TRY TO PACK! */
+        struct {
+                __u8              pending;       /* ACK is pending                         */
+                __u8              quick;         /* Scheduled number of quick acks         */
+                __u8              pingpong;      /* The session is interactive             */
+                __u8              blocked;       /* Delayed ACK was blocked by socket lock */
+                __u32             ato;           /* Predicted tick of soft clock           */
+                unsigned long     timeout;       /* Currently scheduled timeout            */
+                __u32             lrcvtime;      /* timestamp of last received data packet */
+                __u16             last_seg_size; /* Size of last incoming segment          */
+                __u16             rcv_mss;       /* MSS used for delayed ACK decisions     */ 
+        } icsk_ack;
+        u32                       icsk_ca_priv[16];
+#define ICSK_CA_PRIV_SIZE       (16 * sizeof(u32))
+};
+
+#define ICSK_TIME_RETRANS       1       /* Retransmit timer */
+#define ICSK_TIME_DACK          2       /* Delayed ack timer */
+#define ICSK_TIME_PROBE0        3       /* Zero window probe timer */
+#define ICSK_TIME_KEEPOPEN      4       /* Keepalive timer */
+
+static inline struct inet_connection_sock *inet_csk(const struct sock *sk)
+{
+        return (struct inet_connection_sock *)sk;
+}
+
+static inline void *inet_csk_ca(const struct sock *sk)
+{
+        return (void *)inet_csk(sk)->icsk_ca_priv;
+}
+
+extern struct sock *inet_csk_clone(struct sock *sk,
+                                   const struct request_sock *req,
+                                   const unsigned int __nocast priority);
+
+enum inet_csk_ack_state_t {
+        ICSK_ACK_SCHED  = 1,
+        ICSK_ACK_TIMER  = 2,
+        ICSK_ACK_PUSHED = 4
+};
+
+extern void inet_csk_init_xmit_timers(struct sock *sk,
+                                      void (*retransmit_handler)(unsigned long),
+                                      void (*delack_handler)(unsigned long),
+                                      void (*keepalive_handler)(unsigned long));
+extern void inet_csk_clear_xmit_timers(struct sock *sk);
+
+static inline void inet_csk_schedule_ack(struct sock *sk)
+{
+        inet_csk(sk)->icsk_ack.pending |= ICSK_ACK_SCHED;
+}
+
+static inline int inet_csk_ack_scheduled(const struct sock *sk)
+{
+        return inet_csk(sk)->icsk_ack.pending & ICSK_ACK_SCHED;
+}
+
+static inline void inet_csk_delack_init(struct sock *sk)
+{
+        memset(&inet_csk(sk)->icsk_ack, 0, sizeof(inet_csk(sk)->icsk_ack));
+}
+
+extern void inet_csk_delete_keepalive_timer(struct sock *sk);
+extern void inet_csk_reset_keepalive_timer(struct sock *sk, unsigned long timeout);
+
+#ifdef INET_CSK_DEBUG
+extern const char inet_csk_timer_bug_msg[];
+#endif
+
+static inline void inet_csk_clear_xmit_timer(struct sock *sk, const int what)
+{
+        struct inet_connection_sock *icsk = inet_csk(sk);
+        
+        if (what == ICSK_TIME_RETRANS || what == ICSK_TIME_PROBE0) {
+                icsk->icsk_pending = 0;
+#ifdef INET_CSK_CLEAR_TIMERS
+                sk_stop_timer(sk, &icsk->icsk_retransmit_timer);
+#endif
+        } else if (what == ICSK_TIME_DACK) {
+                icsk->icsk_ack.blocked = icsk->icsk_ack.pending = 0;
+#ifdef INET_CSK_CLEAR_TIMERS
+                sk_stop_timer(sk, &icsk->icsk_delack_timer);
+#endif
+        }
+#ifdef INET_CSK_DEBUG
+        else {
+                pr_debug("%s", inet_csk_timer_bug_msg);
+        }
+#endif
+}
+
+/*
+ *      Reset the retransmission timer
+ */
+static inline void inet_csk_reset_xmit_timer(struct sock *sk, const int what,
+                                             unsigned long when,
+                                             const unsigned long max_when)
+{
+        struct inet_connection_sock *icsk = inet_csk(sk);
+
+        if (when > max_when) {
+#ifdef INET_CSK_DEBUG
+                pr_debug("reset_xmit_timer: sk=%p %d when=0x%lx, caller=%p\n",
+                         sk, what, when, current_text_addr());
+#endif
+                when = max_when;
+        }
+
+        if (what == ICSK_TIME_RETRANS || what == ICSK_TIME_PROBE0) {
+                icsk->icsk_pending = what;
+                icsk->icsk_timeout = jiffies + when;
+                sk_reset_timer(sk, &icsk->icsk_retransmit_timer, icsk->icsk_timeout);
+        } else if (what == ICSK_TIME_DACK) {
+                icsk->icsk_ack.pending |= ICSK_ACK_TIMER;
+                icsk->icsk_ack.timeout = jiffies + when;
+                sk_reset_timer(sk, &icsk->icsk_delack_timer, icsk->icsk_ack.timeout);
+        }
+#ifdef INET_CSK_DEBUG
+        else {
+                pr_debug("%s", inet_csk_timer_bug_msg);
+        }
+#endif
+}
+
+extern struct sock *inet_csk_accept(struct sock *sk, int flags, int *err);
+
+extern struct request_sock *inet_csk_search_req(const struct sock *sk,
+                                                struct request_sock ***prevp,
+                                                const __u16 rport,
+                                                const __u32 raddr,
+                                                const __u32 laddr);
+extern int inet_csk_get_port(struct inet_hashinfo *hashinfo,
+                             struct sock *sk, unsigned short snum);
+
+extern struct dst_entry* inet_csk_route_req(struct sock *sk,
+                                            const struct request_sock *req);
+
+static inline void inet_csk_reqsk_queue_add(struct sock *sk,
+                                            struct request_sock *req,
+                                            struct sock *child)
+{
+        reqsk_queue_add(&inet_csk(sk)->icsk_accept_queue, req, sk, child);
+}
+
+extern void inet_csk_reqsk_queue_hash_add(struct sock *sk,
+                                          struct request_sock *req,
+                                          const unsigned timeout);
+
+static inline void inet_csk_reqsk_queue_removed(struct sock *sk,
+                                                struct request_sock *req)
+{
+        if (reqsk_queue_removed(&inet_csk(sk)->icsk_accept_queue, req) == 0)
+                inet_csk_delete_keepalive_timer(sk);
+}
+
+static inline void inet_csk_reqsk_queue_added(struct sock *sk,
+                                              const unsigned long timeout)
+{
+        if (reqsk_queue_added(&inet_csk(sk)->icsk_accept_queue) == 0)
+                inet_csk_reset_keepalive_timer(sk, timeout);
+}
+
+static inline int inet_csk_reqsk_queue_len(const struct sock *sk)
+{
+        return reqsk_queue_len(&inet_csk(sk)->icsk_accept_queue);
+}
+
+static inline int inet_csk_reqsk_queue_young(const struct sock *sk)
+{
+        return reqsk_queue_len_young(&inet_csk(sk)->icsk_accept_queue);
+}
+
+static inline int inet_csk_reqsk_queue_is_full(const struct sock *sk)
+{
+        return reqsk_queue_is_full(&inet_csk(sk)->icsk_accept_queue);
+}
+
+static inline void inet_csk_reqsk_queue_unlink(struct sock *sk,
+                                               struct request_sock *req,
+                                               struct request_sock **prev)
+{
+        reqsk_queue_unlink(&inet_csk(sk)->icsk_accept_queue, req, prev);
+}
+
+static inline void inet_csk_reqsk_queue_drop(struct sock *sk,
+                                             struct request_sock *req,
+                                             struct request_sock **prev)
+{
+        inet_csk_reqsk_queue_unlink(sk, req, prev);
+        inet_csk_reqsk_queue_removed(sk, req);
+        reqsk_free(req);
+}
+
+extern void inet_csk_reqsk_queue_prune(struct sock *parent,
+                                       const unsigned long interval,
+                                       const unsigned long timeout,
+                                       const unsigned long max_rto);
+
+extern void inet_csk_destroy_sock(struct sock *sk);
+
+/*
+ * LISTEN is a special case for poll..
+ */
+static inline unsigned int inet_csk_listen_poll(const struct sock *sk)
+{
+        return !reqsk_queue_empty(&inet_csk(sk)->icsk_accept_queue) ?
+                        (POLLIN | POLLRDNORM) : 0;
+}
+
+extern int  inet_csk_listen_start(struct sock *sk, const int nr_table_entries);
+extern void inet_csk_listen_stop(struct sock *sk);
+
+#endif /* _INET_CONNECTION_SOCK_H */
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
new file mode 100644
index 000000000000..646b6ea7fe26
--- /dev/null
+++ b/include/net/inet_hashtables.h
@@ -0,0 +1,427 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ * Authors:     Lotsa people, from code originally in tcp
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _INET_HASHTABLES_H
+#define _INET_HASHTABLES_H
+
+#include <linux/config.h>
+
+#include <linux/interrupt.h>
+#include <linux/ipv6.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/socket.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+
+#include <net/inet_connection_sock.h>
+#include <net/route.h>
+#include <net/sock.h>
+#include <net/tcp_states.h>
+
+#include <asm/atomic.h>
+#include <asm/byteorder.h>
+
+/* This is for all connections with a full identity, no wildcards.
+ * New scheme, half the table is for TIME_WAIT, the other half is
+ * for the rest.  I'll experiment with dynamic table growth later.
+ */
+struct inet_ehash_bucket {
+        rwlock_t          lock;
+        struct hlist_head chain;
+} __attribute__((__aligned__(8)));
+
+/* There are a few simple rules, which allow for local port reuse by
+ * an application.  In essence:
+ *
+ *      1) Sockets bound to different interfaces may share a local port.
+ *         Failing that, goto test 2.
+ *      2) If all sockets have sk->sk_reuse set, and none of them are in
+ *         TCP_LISTEN state, the port may be shared.
+ *         Failing that, goto test 3.
+ *      3) If all sockets are bound to a specific inet_sk(sk)->rcv_saddr local
+ *         address, and none of them are the same, the port may be
+ *         shared.
+ *         Failing this, the port cannot be shared.
+ *
+ * The interesting point, is test #2.  This is what an FTP server does
+ * all day.  To optimize this case we use a specific flag bit defined
+ * below.  As we add sockets to a bind bucket list, we perform a
+ * check of: (newsk->sk_reuse && (newsk->sk_state != TCP_LISTEN))
+ * As long as all sockets added to a bind bucket pass this test,
+ * the flag bit will be set.
+ * The resulting situation is that tcp_v[46]_verify_bind() can just check
+ * for this flag bit, if it is set and the socket trying to bind has
+ * sk->sk_reuse set, we don't even have to walk the owners list at all,
+ * we return that it is ok to bind this socket to the requested local port.
+ *
+ * Sounds like a lot of work, but it is worth it.  In a more naive
+ * implementation (ie. current FreeBSD etc.) the entire list of ports
+ * must be walked for each data port opened by an ftp server.  Needless
+ * to say, this does not scale at all.  With a couple thousand FTP
+ * users logged onto your box, isn't it nice to know that new data
+ * ports are created in O(1) time?  I thought so. ;-)   -DaveM
+ */
+struct inet_bind_bucket {
+        unsigned short          port;
+        signed short            fastreuse;
+        struct hlist_node       node;
+        struct hlist_head       owners;
+};
+
+#define inet_bind_bucket_for_each(tb, node, head) \
+        hlist_for_each_entry(tb, node, head, node)
+
+struct inet_bind_hashbucket {
+        spinlock_t              lock;
+        struct hlist_head       chain;
+};
+
+/* This is for listening sockets, thus all sockets which possess wildcards. */
+#define INET_LHTABLE_SIZE       32      /* Yes, really, this is all you need. */
+
+struct inet_hashinfo {
+        /* This is for sockets with full identity only.  Sockets here will
+         * always be without wildcards and will have the following invariant:
+         *
+         *          TCP_ESTABLISHED <= sk->sk_state < TCP_CLOSE
+         *
+         * First half of the table is for sockets not in TIME_WAIT, second half
+         * is for TIME_WAIT sockets only.
+         */
+        struct inet_ehash_bucket        *ehash;
+
+        /* Ok, let's try this, I give up, we do need a local binding
+         * TCP hash as well as the others for fast bind/connect.
+         */
+        struct inet_bind_hashbucket     *bhash;
+
+        int                             bhash_size;
+        int                             ehash_size;
+
+        /* All sockets in TCP_LISTEN state will be in here.  This is the only
+         * table where wildcard'd TCP sockets can exist.  Hash function here
+         * is just local port number.
+         */
+        struct hlist_head               listening_hash[INET_LHTABLE_SIZE];
+
+        /* All the above members are written once at bootup and
+         * never written again _or_ are predominantly read-access.
+         *
+         * Now align to a new cache line as all the following members
+         * are often dirty.
+         */
+        rwlock_t                        lhash_lock ____cacheline_aligned;
+        atomic_t                        lhash_users;
+        wait_queue_head_t               lhash_wait;
+        spinlock_t                      portalloc_lock;
+        kmem_cache_t                    *bind_bucket_cachep;
+        int                             port_rover;
+};
+
+static inline int inet_ehashfn(const __u32 laddr, const __u16 lport,
+                               const __u32 faddr, const __u16 fport,
+                               const int ehash_size)
+{
+        int h = (laddr ^ lport) ^ (faddr ^ fport);
+        h ^= h >> 16;
+        h ^= h >> 8;
+        return h & (ehash_size - 1);
+}
+
+static inline int inet_sk_ehashfn(const struct sock *sk, const int ehash_size)
+{
+        const struct inet_sock *inet = inet_sk(sk);
+        const __u32 laddr = inet->rcv_saddr;
+        const __u16 lport = inet->num;
+        const __u32 faddr = inet->daddr;
+        const __u16 fport = inet->dport;
+
+        return inet_ehashfn(laddr, lport, faddr, fport, ehash_size);
+}
+
+extern struct inet_bind_bucket *
+                    inet_bind_bucket_create(kmem_cache_t *cachep,
+                                            struct inet_bind_hashbucket *head,
+                                            const unsigned short snum);
+extern void inet_bind_bucket_destroy(kmem_cache_t *cachep,
+                                     struct inet_bind_bucket *tb);
+
+static inline int inet_bhashfn(const __u16 lport, const int bhash_size)
+{
+        return lport & (bhash_size - 1);
+}
+
+extern void inet_bind_hash(struct sock *sk, struct inet_bind_bucket *tb,
+                           const unsigned short snum);
+
+/* These can have wildcards, don't try too hard. */
+static inline int inet_lhashfn(const unsigned short num)
+{
+        return num & (INET_LHTABLE_SIZE - 1);
+}
+
+static inline int inet_sk_listen_hashfn(const struct sock *sk)
+{
+        return inet_lhashfn(inet_sk(sk)->num);
+}
+
+/* Caller must disable local BH processing. */
+static inline void __inet_inherit_port(struct inet_hashinfo *table,
+                                       struct sock *sk, struct sock *child)
+{
+        const int bhash = inet_bhashfn(inet_sk(child)->num, table->bhash_size);
+        struct inet_bind_hashbucket *head = &table->bhash[bhash];
+        struct inet_bind_bucket *tb;
+
+        spin_lock(&head->lock);
+        tb = inet_csk(sk)->icsk_bind_hash;
+        sk_add_bind_node(child, &tb->owners);
+        inet_csk(child)->icsk_bind_hash = tb;
+        spin_unlock(&head->lock);
+}
+
+static inline void inet_inherit_port(struct inet_hashinfo *table,
+                                     struct sock *sk, struct sock *child)
+{
+        local_bh_disable();
+        __inet_inherit_port(table, sk, child);
+        local_bh_enable();
+}
+
+extern void inet_put_port(struct inet_hashinfo *table, struct sock *sk);
+
+extern void inet_listen_wlock(struct inet_hashinfo *hashinfo);
+
+/*
+ * - We may sleep inside this lock.
+ * - If sleeping is not required (or called from BH),
+ *   use plain read_(un)lock(&inet_hashinfo.lhash_lock).
+ */
+static inline void inet_listen_lock(struct inet_hashinfo *hashinfo)
+{
+        /* read_lock synchronizes to candidates to writers */
+        read_lock(&hashinfo->lhash_lock);
+        atomic_inc(&hashinfo->lhash_users);
+        read_unlock(&hashinfo->lhash_lock);
+}
+
+static inline void inet_listen_unlock(struct inet_hashinfo *hashinfo)
+{
+        if (atomic_dec_and_test(&hashinfo->lhash_users))
+                wake_up(&hashinfo->lhash_wait);
+}
+
+static inline void __inet_hash(struct inet_hashinfo *hashinfo,
+                               struct sock *sk, const int listen_possible)
+{
+        struct hlist_head *list;
+        rwlock_t *lock;
+
+        BUG_TRAP(sk_unhashed(sk));
+        if (listen_possible && sk->sk_state == TCP_LISTEN) {
+                list = &hashinfo->listening_hash[inet_sk_listen_hashfn(sk)];
+                lock = &hashinfo->lhash_lock;
+                inet_listen_wlock(hashinfo);
+        } else {
+                sk->sk_hashent = inet_sk_ehashfn(sk, hashinfo->ehash_size);
+                list = &hashinfo->ehash[sk->sk_hashent].chain;
+                lock = &hashinfo->ehash[sk->sk_hashent].lock;
+                write_lock(lock);
+        }
+        __sk_add_node(sk, list);
+        sock_prot_inc_use(sk->sk_prot);
+        write_unlock(lock);
+        if (listen_possible && sk->sk_state == TCP_LISTEN)
+                wake_up(&hashinfo->lhash_wait);
+}
+
+static inline void inet_hash(struct inet_hashinfo *hashinfo, struct sock *sk)
+{
+        if (sk->sk_state != TCP_CLOSE) {
+                local_bh_disable();
+                __inet_hash(hashinfo, sk, 1);
+                local_bh_enable();
+        }
+}
+
+static inline void inet_unhash(struct inet_hashinfo *hashinfo, struct sock *sk)
+{
+        rwlock_t *lock;
+
+        if (sk_unhashed(sk))
+                goto out;
+
+        if (sk->sk_state == TCP_LISTEN) {
+                local_bh_disable();
+                inet_listen_wlock(hashinfo);
+                lock = &hashinfo->lhash_lock;
+        } else {
+                struct inet_ehash_bucket *head = &hashinfo->ehash[sk->sk_hashent];
+                lock = &head->lock;
+                write_lock_bh(&head->lock);
+        }
+
+        if (__sk_del_node_init(sk))
+                sock_prot_dec_use(sk->sk_prot);
+        write_unlock_bh(lock);
+out:
+        if (sk->sk_state == TCP_LISTEN)
+                wake_up(&hashinfo->lhash_wait);
+}
+
+static inline int inet_iif(const struct sk_buff *skb)
+{
+        return ((struct rtable *)skb->dst)->rt_iif;
+}
+
+extern struct sock *__inet_lookup_listener(const struct hlist_head *head,
+                                           const u32 daddr,
+                                           const unsigned short hnum,
+                                           const int dif);
+
+/* Optimize the common listener case. */
+static inline struct sock *
+                inet_lookup_listener(struct inet_hashinfo *hashinfo,
+                                     const u32 daddr,
+                                     const unsigned short hnum, const int dif)
+{
+        struct sock *sk = NULL;
+        const struct hlist_head *head;
+
+        read_lock(&hashinfo->lhash_lock);
+        head = &hashinfo->listening_hash[inet_lhashfn(hnum)];
+        if (!hlist_empty(head)) {
+                const struct inet_sock *inet = inet_sk((sk = __sk_head(head)));
+
+                if (inet->num == hnum && !sk->sk_node.next &&
+                    (!inet->rcv_saddr || inet->rcv_saddr == daddr) &&
+                    (sk->sk_family == PF_INET || !ipv6_only_sock(sk)) &&
+                    !sk->sk_bound_dev_if)
+                        goto sherry_cache;
+                sk = __inet_lookup_listener(head, daddr, hnum, dif);
+        }
+        if (sk) {
+sherry_cache:
+                sock_hold(sk);
+        }
+        read_unlock(&hashinfo->lhash_lock);
+        return sk;
+}
+
+/* Socket demux engine toys. */
+#ifdef __BIG_ENDIAN
+#define INET_COMBINED_PORTS(__sport, __dport) \
+        (((__u32)(__sport) << 16) | (__u32)(__dport))
+#else /* __LITTLE_ENDIAN */
+#define INET_COMBINED_PORTS(__sport, __dport) \
+        (((__u32)(__dport) << 16) | (__u32)(__sport))
+#endif
+
+#if (BITS_PER_LONG == 64)
+#ifdef __BIG_ENDIAN
+#define INET_ADDR_COOKIE(__name, __saddr, __daddr) \
+        const __u64 __name = (((__u64)(__saddr)) << 32) | ((__u64)(__daddr));
+#else /* __LITTLE_ENDIAN */
+#define INET_ADDR_COOKIE(__name, __saddr, __daddr) \
+        const __u64 __name = (((__u64)(__daddr)) << 32) | ((__u64)(__saddr));
+#endif /* __BIG_ENDIAN */
+#define INET_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
+        (((*((__u64 *)&(inet_sk(__sk)->daddr))) == (__cookie))  &&      \
+         ((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports))   &&      \
+         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
+#define INET_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
+        (((*((__u64 *)&(inet_twsk(__sk)->tw_daddr))) == (__cookie)) &&  \
+         ((*((__u32 *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) &&   \
+         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
+#else /* 32-bit arch */
+#define INET_ADDR_COOKIE(__name, __saddr, __daddr)
+#define INET_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)    \
+        ((inet_sk(__sk)->daddr          == (__saddr))           &&      \
+         (inet_sk(__sk)->rcv_saddr      == (__daddr))           &&      \
+         ((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports))   &&      \
+         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
+#define INET_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif) \
+        ((inet_twsk(__sk)->tw_daddr     == (__saddr))           &&      \
+         (inet_twsk(__sk)->tw_rcv_saddr == (__daddr))           &&      \
+         ((*((__u32 *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) &&   \
+         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
+#endif /* 64-bit arch */
+
+/*
+ * Sockets in TCP_CLOSE state are _always_ taken out of the hash, so we need
+ * not check it for lookups anymore, thanks Alexey. -DaveM
+ *
+ * Local BH must be disabled here.
+ */
+static inline struct sock *
+        __inet_lookup_established(struct inet_hashinfo *hashinfo,
+                                  const u32 saddr, const u16 sport,
+                                  const u32 daddr, const u16 hnum,
+                                  const int dif)
+{
+        INET_ADDR_COOKIE(acookie, saddr, daddr)
+        const __u32 ports = INET_COMBINED_PORTS(sport, hnum);
+        struct sock *sk;
+        const struct hlist_node *node;
+        /* Optimize here for direct hit, only listening connections can
+         * have wildcards anyways.
+         */
+        const int hash = inet_ehashfn(daddr, hnum, saddr, sport, hashinfo->ehash_size);
+        struct inet_ehash_bucket *head = &hashinfo->ehash[hash];
+
+        read_lock(&head->lock);
+        sk_for_each(sk, node, &head->chain) {
+                if (INET_MATCH(sk, acookie, saddr, daddr, ports, dif))
+                        goto hit; /* You sunk my battleship! */
+        }
+
+        /* Must check for a TIME_WAIT'er before going to listener hash. */
+        sk_for_each(sk, node, &(head + hashinfo->ehash_size)->chain) {
+                if (INET_TW_MATCH(sk, acookie, saddr, daddr, ports, dif))
+                        goto hit;
+        }
+        sk = NULL;
+out:
+        read_unlock(&head->lock);
+        return sk;
+hit:
+        sock_hold(sk);
+        goto out;
+}
+
+static inline struct sock *__inet_lookup(struct inet_hashinfo *hashinfo,
+                                         const u32 saddr, const u16 sport,
+                                         const u32 daddr, const u16 hnum,
+                                         const int dif)
+{
+        struct sock *sk = __inet_lookup_established(hashinfo, saddr, sport, daddr,
+                                                    hnum, dif);
+        return sk ? : inet_lookup_listener(hashinfo, daddr, hnum, dif);
+}
+
+static inline struct sock *inet_lookup(struct inet_hashinfo *hashinfo,
+                                       const u32 saddr, const u16 sport,
+                                       const u32 daddr, const u16 dport,
+                                       const int dif)
+{
+        struct sock *sk;
+
+        local_bh_disable();
+        sk = __inet_lookup(hashinfo, saddr, sport, daddr, ntohs(dport), dif);
+        local_bh_enable();
+
+        return sk;
+}
+#endif /* _INET_HASHTABLES_H */
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
new file mode 100644
index 000000000000..3b070352e869
--- /dev/null
+++ b/include/net/inet_timewait_sock.h
@@ -0,0 +1,219 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the  BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ *              Definitions for a generic INET TIMEWAIT sock
+ *
+ *              From code originally in net/tcp.h
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+#ifndef _INET_TIMEWAIT_SOCK_
+#define _INET_TIMEWAIT_SOCK_
+
+#include <linux/config.h>
+
+#include <linux/ip.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include <net/sock.h>
+#include <net/tcp_states.h>
+
+#include <asm/atomic.h>
+
+struct inet_hashinfo;
+
+#define INET_TWDR_RECYCLE_SLOTS_LOG     5
+#define INET_TWDR_RECYCLE_SLOTS         (1 << INET_TWDR_RECYCLE_SLOTS_LOG)
+
+/*
+ * If time > 4sec, it is "slow" path, no recycling is required,
+ * so that we select tick to get range about 4 seconds.
+ */
+#if HZ <= 16 || HZ > 4096
+# error Unsupported: HZ <= 16 or HZ > 4096
+#elif HZ <= 32
+# define INET_TWDR_RECYCLE_TICK (5 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 64
+# define INET_TWDR_RECYCLE_TICK (6 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 128
+# define INET_TWDR_RECYCLE_TICK (7 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 256
+# define INET_TWDR_RECYCLE_TICK (8 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 512
+# define INET_TWDR_RECYCLE_TICK (9 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 1024
+# define INET_TWDR_RECYCLE_TICK (10 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#elif HZ <= 2048
+# define INET_TWDR_RECYCLE_TICK (11 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#else
+# define INET_TWDR_RECYCLE_TICK (12 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG)
+#endif
+
+/* TIME_WAIT reaping mechanism. */
+#define INET_TWDR_TWKILL_SLOTS  8 /* Please keep this a power of 2. */
+
+#define INET_TWDR_TWKILL_QUOTA 100
+
+struct inet_timewait_death_row {
+        /* Short-time timewait calendar */
+        int                     twcal_hand;
+        int                     twcal_jiffie;
+        struct timer_list       twcal_timer;
+        struct hlist_head       twcal_row[INET_TWDR_RECYCLE_SLOTS];
+
+        spinlock_t              death_lock;
+        int                     tw_count;
+        int                     period;
+        u32                     thread_slots;
+        struct work_struct      twkill_work;
+        struct timer_list       tw_timer;
+        int                     slot;
+        struct hlist_head       cells[INET_TWDR_TWKILL_SLOTS];
+        struct inet_hashinfo    *hashinfo;
+        int                     sysctl_tw_recycle;
+        int                     sysctl_max_tw_buckets;
+};
+
+extern void inet_twdr_hangman(unsigned long data);
+extern void inet_twdr_twkill_work(void *data);
+extern void inet_twdr_twcal_tick(unsigned long data);
+
+#if (BITS_PER_LONG == 64)
+#define INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES 8
+#else
+#define INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES 4
+#endif
+
+struct inet_bind_bucket;
+
+/*
+ * This is a TIME_WAIT sock. It works around the memory consumption
+ * problems of sockets in such a state on heavily loaded servers, but
+ * without violating the protocol specification.
+ */
+struct inet_timewait_sock {
+        /*
+         * Now struct sock also uses sock_common, so please just
+         * don't add nothing before this first member (__tw_common) --acme
+         */
+        struct sock_common      __tw_common;
+#define tw_family               __tw_common.skc_family
+#define tw_state                __tw_common.skc_state
+#define tw_reuse                __tw_common.skc_reuse
+#define tw_bound_dev_if         __tw_common.skc_bound_dev_if
+#define tw_node                 __tw_common.skc_node
+#define tw_bind_node            __tw_common.skc_bind_node
+#define tw_refcnt               __tw_common.skc_refcnt
+#define tw_prot                 __tw_common.skc_prot
+        volatile unsigned char  tw_substate;
+        /* 3 bits hole, try to pack */
+        unsigned char           tw_rcv_wscale;
+        /* Socket demultiplex comparisons on incoming packets. */
+        /* these five are in inet_sock */
+        __u16                   tw_sport;
+        __u32                   tw_daddr __attribute__((aligned(INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES)));
+        __u32                   tw_rcv_saddr;
+        __u16                   tw_dport;
+        __u16                   tw_num;
+        /* And these are ours. */
+        __u8                    tw_ipv6only:1;
+        /* 31 bits hole, try to pack */
+        int                     tw_hashent;
+        int                     tw_timeout;
+        unsigned long           tw_ttd;
+        struct inet_bind_bucket *tw_tb;
+        struct hlist_node       tw_death_node;
+};
+
+static inline void inet_twsk_add_node(struct inet_timewait_sock *tw,
+                                      struct hlist_head *list)
+{
+        hlist_add_head(&tw->tw_node, list);
+}
+
+static inline void inet_twsk_add_bind_node(struct inet_timewait_sock *tw,
+                                           struct hlist_head *list)
+{
+        hlist_add_head(&tw->tw_bind_node, list);
+}
+
+static inline int inet_twsk_dead_hashed(const struct inet_timewait_sock *tw)
+{
+        return tw->tw_death_node.pprev != NULL;
+}
+
+static inline void inet_twsk_dead_node_init(struct inet_timewait_sock *tw)
+{
+        tw->tw_death_node.pprev = NULL;
+}
+
+static inline void __inet_twsk_del_dead_node(struct inet_timewait_sock *tw)
+{
+        __hlist_del(&tw->tw_death_node);
+        inet_twsk_dead_node_init(tw);
+}
+
+static inline int inet_twsk_del_dead_node(struct inet_timewait_sock *tw)
+{
+        if (inet_twsk_dead_hashed(tw)) {
+                __inet_twsk_del_dead_node(tw);
+                return 1;
+        }
+        return 0;
+}
+
+#define inet_twsk_for_each(tw, node, head) \
+        hlist_for_each_entry(tw, node, head, tw_node)
+
+#define inet_twsk_for_each_inmate(tw, node, jail) \
+        hlist_for_each_entry(tw, node, jail, tw_death_node)
+
+#define inet_twsk_for_each_inmate_safe(tw, node, safe, jail) \
+        hlist_for_each_entry_safe(tw, node, safe, jail, tw_death_node)
+
+static inline struct inet_timewait_sock *inet_twsk(const struct sock *sk)
+{
+        return (struct inet_timewait_sock *)sk;
+}
+
+static inline u32 inet_rcv_saddr(const struct sock *sk)
+{
+        return likely(sk->sk_state != TCP_TIME_WAIT) ?
+                inet_sk(sk)->rcv_saddr : inet_twsk(sk)->tw_rcv_saddr;
+}
+
+static inline void inet_twsk_put(struct inet_timewait_sock *tw)
+{
+        if (atomic_dec_and_test(&tw->tw_refcnt)) {
+#ifdef SOCK_REFCNT_DEBUG
+                printk(KERN_DEBUG "%s timewait_sock %p released\n",
+                       tw->tw_prot->name, tw);
+#endif
+                kmem_cache_free(tw->tw_prot->twsk_slab, tw);
+        }
+}
+
+extern struct inet_timewait_sock *inet_twsk_alloc(const struct sock *sk,
+                                                  const int state);
+
+extern void __inet_twsk_kill(struct inet_timewait_sock *tw,
+                             struct inet_hashinfo *hashinfo);
+
+extern void __inet_twsk_hashdance(struct inet_timewait_sock *tw,
+                                  struct sock *sk,
+                                  struct inet_hashinfo *hashinfo);
+
+extern void inet_twsk_schedule(struct inet_timewait_sock *tw,
+                               struct inet_timewait_death_row *twdr,
+                               const int timeo, const int timewait_len);
+extern void inet_twsk_deschedule(struct inet_timewait_sock *tw,
+                                 struct inet_timewait_death_row *twdr);
+#endif  /* _INET_TIMEWAIT_SOCK_ */
diff --git a/include/net/ip.h b/include/net/ip.h
index 3f63992eb712..e4563bbee6ea 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -86,7 +86,7 @@ extern int		ip_build_and_send_pkt(struct sk_buff *skb, struct sock *sk,
                                               u32 saddr, u32 daddr,
                                               struct ip_options *opt);
 extern int              ip_rcv(struct sk_buff *skb, struct net_device *dev,
-                               struct packet_type *pt);
+                               struct packet_type *pt, struct net_device *orig_dev);
 extern int              ip_local_deliver(struct sk_buff *skb);
 extern int              ip_mr_input(struct sk_buff *skb);
 extern int              ip_output(struct sk_buff *skb);
@@ -140,8 +140,6 @@ struct ip_reply_arg {
 void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *arg,
                    unsigned int len); 
 
-extern int ip_finish_output(struct sk_buff *skb);
-
 struct ipv4_config
 {
         int     log_martians;
@@ -163,6 +161,25 @@ DECLARE_SNMP_STAT(struct linux_mib, net_statistics);
 
 extern int sysctl_local_port_range[2];
 extern int sysctl_ip_default_ttl;
+extern int sysctl_ip_nonlocal_bind;
+
+/* From ip_fragment.c */
+extern int sysctl_ipfrag_high_thresh; 
+extern int sysctl_ipfrag_low_thresh;
+extern int sysctl_ipfrag_time;
+extern int sysctl_ipfrag_secret_interval;
+
+/* From inetpeer.c */
+extern int inet_peer_threshold;
+extern int inet_peer_minttl;
+extern int inet_peer_maxttl;
+extern int inet_peer_gc_mintime;
+extern int inet_peer_gc_maxtime;
+
+/* From ip_output.c */
+extern int sysctl_ip_dynaddr;
+
+extern void ipfrag_init(void);
 
 #ifdef CONFIG_INET
 /* The function in 2.2 was invalid, producing wrong result for
@@ -318,7 +335,10 @@ extern void ip_options_build(struct sk_buff *skb, struct ip_options *opt, u32 da
 extern int ip_options_echo(struct ip_options *dopt, struct sk_buff *skb);
 extern void ip_options_fragment(struct sk_buff *skb);
 extern int ip_options_compile(struct ip_options *opt, struct sk_buff *skb);
-extern int ip_options_get(struct ip_options **optp, unsigned char *data, int optlen, int user);
+extern int ip_options_get(struct ip_options **optp,
+                          unsigned char *data, int optlen);
+extern int ip_options_get_from_user(struct ip_options **optp,
+                                    unsigned char __user *data, int optlen);
 extern void ip_options_undo(struct ip_options * opt);
 extern void ip_forward_options(struct sk_buff *skb);
 extern int ip_options_rcv_srr(struct sk_buff *skb);
@@ -349,5 +369,10 @@ int ipv4_doint_and_flush_strategy(ctl_table *table, int __user *name, int nlen,
                                   void __user *oldval, size_t __user *oldlenp,
                                   void __user *newval, size_t newlen, 
                                   void **context);
+#ifdef CONFIG_PROC_FS
+extern int ip_misc_proc_init(void);
+#endif
+
+extern struct ctl_table ipv4_table[];
 
 #endif  /* _IP_H */
diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h
index 319904518194..a66e9de16a6c 100644
--- a/include/net/ip6_fib.h
+++ b/include/net/ip6_fib.h
@@ -167,14 +167,17 @@ extern int			fib6_walk_continue(struct fib6_walker_t *w);
 extern int                      fib6_add(struct fib6_node *root,
                                          struct rt6_info *rt,
                                          struct nlmsghdr *nlh,
-                                         void *rtattr);
+                                         void *rtattr,
+                                         struct netlink_skb_parms *req);
 
 extern int                      fib6_del(struct rt6_info *rt,
                                          struct nlmsghdr *nlh,
-                                         void *rtattr);
+                                         void *rtattr,
+                                         struct netlink_skb_parms *req);
 
 extern void                     inet6_rt_notify(int event, struct rt6_info *rt,
-                                                struct nlmsghdr *nlh);
+                                                struct nlmsghdr *nlh,
+                                                struct netlink_skb_parms *req);
 
 extern void                     fib6_run_gc(unsigned long dummy);
 
diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h
index d5d1dd10cdb8..1f2e428ca364 100644
--- a/include/net/ip6_route.h
+++ b/include/net/ip6_route.h
@@ -12,7 +12,6 @@
 #include <net/flow.h>
 #include <net/ip6_fib.h>
 #include <net/sock.h>
-#include <linux/tcp.h>
 #include <linux/ip.h>
 #include <linux/ipv6.h>
 
@@ -41,13 +40,16 @@ extern int			ipv6_route_ioctl(unsigned int cmd, void __user *arg);
 
 extern int                      ip6_route_add(struct in6_rtmsg *rtmsg,
                                               struct nlmsghdr *,
-                                              void *rtattr);
+                                              void *rtattr,
+                                              struct netlink_skb_parms *req);
 extern int                      ip6_ins_rt(struct rt6_info *,
                                            struct nlmsghdr *,
-                                           void *rtattr);
+                                           void *rtattr,
+                                           struct netlink_skb_parms *req);
 extern int                      ip6_del_rt(struct rt6_info *,
                                            struct nlmsghdr *,
-                                           void *rtattr);
+                                           void *rtattr,
+                                           struct netlink_skb_parms *req);
 
 extern int                      ip6_rt_addr_add(struct in6_addr *addr,
                                                 struct net_device *dev,
diff --git a/include/net/ip_fib.h b/include/net/ip_fib.h
index e5a5f6b62f88..14de4ebd1211 100644
--- a/include/net/ip_fib.h
+++ b/include/net/ip_fib.h
@@ -109,6 +109,20 @@ struct fib_result {
 #endif
 };
 
+struct fib_result_nl {
+        u32             fl_addr;   /* To be looked up*/ 
+        u32             fl_fwmark; 
+        unsigned char   fl_tos;
+        unsigned char   fl_scope;
+        unsigned char   tb_id_in;
+
+        unsigned char   tb_id;      /* Results */
+        unsigned char   prefixlen;
+        unsigned char   nh_sel;
+        unsigned char   type;
+        unsigned char   scope;
+        int             err;      
+};
 
 #ifdef CONFIG_IP_ROUTE_MULTIPATH
 
@@ -281,4 +295,9 @@ static inline void fib_res_put(struct fib_result *res)
 #endif
 }
 
+#ifdef CONFIG_PROC_FS
+extern int  fib_proc_init(void);
+extern void fib_proc_exit(void);
+#endif
+
 #endif  /* _NET_FIB_H */
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 52da5d26617a..e426641c519f 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -255,7 +255,6 @@ struct ip_vs_daemon_user {
 #include <asm/atomic.h>                 /* for struct atomic_t */
 #include <linux/netdevice.h>            /* for struct neighbour */
 #include <net/dst.h>                    /* for struct dst_entry */
-#include <net/tcp.h>
 #include <net/udp.h>
 #include <linux/compiler.h>
 
@@ -959,7 +958,7 @@ static __inline__ int ip_vs_todrop(void)
  */
 #define IP_VS_FWD_METHOD(cp)  (cp->flags & IP_VS_CONN_F_FWD_MASK)
 
-extern __inline__ char ip_vs_fwd_tag(struct ip_vs_conn *cp)
+static inline char ip_vs_fwd_tag(struct ip_vs_conn *cp)
 {
         char fwd;
 
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 771b47e30f86..3203eaff4bd4 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -104,6 +104,7 @@ struct frag_hdr {
 
 #ifdef __KERNEL__
 
+#include <linux/config.h>
 #include <net/sock.h>
 
 /* sysctls */
@@ -145,7 +146,6 @@ DECLARE_SNMP_STAT(struct udp_mib, udp_stats_in6);
 #define UDP6_INC_STATS(field)           SNMP_INC_STATS(udp_stats_in6, field)
 #define UDP6_INC_STATS_BH(field)        SNMP_INC_STATS_BH(udp_stats_in6, field)
 #define UDP6_INC_STATS_USER(field)      SNMP_INC_STATS_USER(udp_stats_in6, field)
-extern atomic_t                 inet6_sock_nr;
 
 int snmp6_register_dev(struct inet6_dev *idev);
 int snmp6_unregister_dev(struct inet6_dev *idev);
@@ -183,7 +183,6 @@ struct ipv6_txoptions
         struct ipv6_opt_hdr     *hopopt;
         struct ipv6_opt_hdr     *dst0opt;
         struct ipv6_rt_hdr      *srcrt; /* Routing Header */
-        struct ipv6_opt_hdr     *auth;
         struct ipv6_opt_hdr     *dst1opt;
 
         /* Option buffer, as read by IPV6_PKTOPTIONS, starts here. */
@@ -347,7 +346,8 @@ static inline int ipv6_addr_any(const struct in6_addr *a)
 
 extern int                      ipv6_rcv(struct sk_buff *skb, 
                                          struct net_device *dev, 
-                                         struct packet_type *pt);
+                                         struct packet_type *pt,
+                                         struct net_device *orig_dev);
 
 /*
  *      upper-layer output functions
@@ -465,8 +465,38 @@ extern int sysctl_ip6frag_low_thresh;
 extern int sysctl_ip6frag_time;
 extern int sysctl_ip6frag_secret_interval;
 
-#endif /* __KERNEL__ */
-#endif /* _NET_IPV6_H */
+extern struct proto_ops inet6_stream_ops;
+extern struct proto_ops inet6_dgram_ops;
+
+extern int ip6_mc_source(int add, int omode, struct sock *sk,
+                         struct group_source_req *pgsr);
+extern int ip6_mc_msfilter(struct sock *sk, struct group_filter *gsf);
+extern int ip6_mc_msfget(struct sock *sk, struct group_filter *gsf,
+                         struct group_filter __user *optval,
+                         int __user *optlen);
+
+#ifdef CONFIG_PROC_FS
+extern int  ac6_proc_init(void);
+extern void ac6_proc_exit(void);
+extern int  raw6_proc_init(void);
+extern void raw6_proc_exit(void);
+extern int  tcp6_proc_init(void);
+extern void tcp6_proc_exit(void);
+extern int  udp6_proc_init(void);
+extern void udp6_proc_exit(void);
+extern int  ipv6_misc_proc_init(void);
+extern void ipv6_misc_proc_exit(void);
+
+extern struct rt6_statistics rt6_stats;
+#endif
 
+#ifdef CONFIG_SYSCTL
+extern ctl_table ipv6_route_table[];
+extern ctl_table ipv6_icmp_table[];
 
+extern void ipv6_sysctl_register(void);
+extern void ipv6_sysctl_unregister(void);
+#endif
 
+#endif /* __KERNEL__ */
+#endif /* _NET_IPV6_H */
diff --git a/include/net/irda/irda_device.h b/include/net/irda/irda_device.h
index 71d6af83b631..92c828029cd8 100644
--- a/include/net/irda/irda_device.h
+++ b/include/net/irda/irda_device.h
@@ -224,7 +224,7 @@ int  irda_device_is_receiving(struct net_device *dev);
 /* Interface for internal use */
 static inline int irda_device_txqueue_empty(const struct net_device *dev)
 {
-        return (skb_queue_len(&dev->qdisc->q) == 0);
+        return skb_queue_empty(&dev->qdisc->q);
 }
 int  irda_device_set_raw_mode(struct net_device* self, int status);
 struct net_device *alloc_irdadev(int sizeof_priv);
diff --git a/include/net/irda/irlan_filter.h b/include/net/irda/irlan_filter.h
index 3afeb6c94ea4..492dedaa8ac1 100644
--- a/include/net/irda/irlan_filter.h
+++ b/include/net/irda/irlan_filter.h
@@ -28,6 +28,6 @@
 void irlan_check_command_param(struct irlan_cb *self, char *param, 
                                char *value);
 void irlan_filter_request(struct irlan_cb *self, struct sk_buff *skb);
-int irlan_print_filter(struct seq_file *seq, int filter_type);
+void irlan_print_filter(struct seq_file *seq, int filter_type);
 
 #endif /* IRLAN_FILTER_H */
diff --git a/include/net/iw_handler.h b/include/net/iw_handler.h
index 44edd48f1234..d67c8393a343 100644
--- a/include/net/iw_handler.h
+++ b/include/net/iw_handler.h
@@ -1,10 +1,10 @@
 /*
  * This file define the new driver API for Wireless Extensions
  *
- * Version :    6       21.6.04
+ * Version :    7       18.3.05
  *
  * Authors :    Jean Tourrilhes - HPL - <jt@hpl.hp.com>
- * Copyright (c) 2001-2004 Jean Tourrilhes, All Rights Reserved.
+ * Copyright (c) 2001-2005 Jean Tourrilhes, All Rights Reserved.
  */
 
 #ifndef _IW_HANDLER_H
@@ -207,7 +207,7 @@
  * will be needed...
  * I just plan to increment with each new version.
  */
-#define IW_HANDLER_VERSION      6
+#define IW_HANDLER_VERSION      7
 
 /*
  * Changes :
@@ -232,6 +232,13 @@
  *      - Remove spy #ifdef, they are always on -> cleaner code
  *      - Add IW_DESCR_FLAG_NOMAX flag for very large requests
  *      - Start migrating get_wireless_stats to struct iw_handler_def
+ *
+ * V6 to V7
+ * --------
+ *      - Add struct ieee80211_device pointer in struct iw_public_data
+ *      - Remove (struct iw_point *)->pointer from events and streams
+ *      - Remove spy_offset from struct iw_handler_def
+ *      - Add "check" version of event macros for ieee802.11 stack
  */
 
 /**************************** CONSTANTS ****************************/
@@ -334,9 +341,6 @@ struct iw_handler_def
          * We will automatically export that to user space... */
         const struct iw_priv_args *     private_args;
 
-        /* This field will be *removed* in the next version of WE */
-        long                    spy_offset;     /* DO NOT USE */
-
         /* New location of get_wireless_stats, to de-bloat struct net_device.
          * The old pointer in struct net_device will be gradually phased
          * out, and drivers are encouraged to use this one... */
@@ -400,16 +404,21 @@ struct iw_spy_data
 /* --------------------- DEVICE WIRELESS DATA --------------------- */
 /*
  * This is all the wireless data specific to a device instance that
- * is managed by the core of Wireless Extensions.
+ * is managed by the core of Wireless Extensions or the 802.11 layer.
  * We only keep pointer to those structures, so that a driver is free
  * to share them between instances.
  * This structure should be initialised before registering the device.
  * Access to this data follow the same rules as any other struct net_device
  * data (i.e. valid as long as struct net_device exist, same locking rules).
  */
+/* Forward declaration */
+struct ieee80211_device;
+/* The struct */
 struct iw_public_data {
         /* Driver enhanced spy support */
-        struct iw_spy_data *    spy_data;
+        struct iw_spy_data *            spy_data;
+        /* Structure managed by the in-kernel IEEE 802.11 layer */
+        struct ieee80211_device *       ieee80211;
 };
 
 /**************************** PROTOTYPES ****************************/
@@ -424,7 +433,7 @@ struct iw_public_data {
 extern int dev_get_wireless_info(char * buffer, char **start, off_t offset,
                                  int length);
 
-/* Handle IOCTLs, called in net/code/dev.c */
+/* Handle IOCTLs, called in net/core/dev.c */
 extern int wireless_process_ioctl(struct ifreq *ifr, unsigned int cmd);
 
 /* Second : functions that may be called by driver modules */
@@ -479,7 +488,7 @@ iwe_stream_add_event(char *	stream,		/* Stream of events */
                      int        event_len)      /* Real size of payload */
 {
         /* Check if it's possible */
-        if((stream + event_len) < ends) {
+        if(likely((stream + event_len) < ends)) {
                 iwe->len = event_len;
                 memcpy(stream, (char *) iwe, event_len);
                 stream += event_len;
@@ -495,14 +504,17 @@ iwe_stream_add_event(char *	stream,		/* Stream of events */
 static inline char *
 iwe_stream_add_point(char *     stream,         /* Stream of events */
                      char *     ends,           /* End of stream */
-                     struct iw_event *iwe,      /* Payload */
-                     char *     extra)
+                     struct iw_event *iwe,      /* Payload length + flags */
+                     char *     extra)          /* More payload */
 {
         int     event_len = IW_EV_POINT_LEN + iwe->u.data.length;
         /* Check if it's possible */
-        if((stream + event_len) < ends) {
+        if(likely((stream + event_len) < ends)) {
                 iwe->len = event_len;
-                memcpy(stream, (char *) iwe, IW_EV_POINT_LEN);
+                memcpy(stream, (char *) iwe, IW_EV_LCP_LEN);
+                memcpy(stream + IW_EV_LCP_LEN,
+                       ((char *) iwe) + IW_EV_LCP_LEN + IW_EV_POINT_OFF,
+                       IW_EV_POINT_LEN - IW_EV_LCP_LEN);
                 memcpy(stream + IW_EV_POINT_LEN, extra, iwe->u.data.length);
                 stream += event_len;
         }
@@ -526,7 +538,7 @@ iwe_stream_add_value(char *	event,		/* Event in the stream */
         event_len -= IW_EV_LCP_LEN;
 
         /* Check if it's possible */
-        if((value + event_len) < ends) {
+        if(likely((value + event_len) < ends)) {
                 /* Add new value */
                 memcpy(value, (char *) iwe + IW_EV_LCP_LEN, event_len);
                 value += event_len;
@@ -537,4 +549,85 @@ iwe_stream_add_value(char *	event,		/* Event in the stream */
         return value;
 }
 
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add an Wireless Event to a stream of events.
+ * Same as above, with explicit error check...
+ */
+static inline char *
+iwe_stream_check_add_event(char *       stream,         /* Stream of events */
+                           char *       ends,           /* End of stream */
+                           struct iw_event *iwe,        /* Payload */
+                           int          event_len,      /* Size of payload */
+                           int *        perr)           /* Error report */
+{
+        /* Check if it's possible, set error if not */
+        if(likely((stream + event_len) < ends)) {
+                iwe->len = event_len;
+                memcpy(stream, (char *) iwe, event_len);
+                stream += event_len;
+        } else
+                *perr = -E2BIG;
+        return stream;
+}
+
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add an short Wireless Event containing a pointer to a
+ * stream of events.
+ * Same as above, with explicit error check...
+ */
+static inline char *
+iwe_stream_check_add_point(char *       stream,         /* Stream of events */
+                           char *       ends,           /* End of stream */
+                           struct iw_event *iwe,        /* Payload length + flags */
+                           char *       extra,          /* More payload */
+                           int *        perr)           /* Error report */
+{
+        int     event_len = IW_EV_POINT_LEN + iwe->u.data.length;
+        /* Check if it's possible */
+        if(likely((stream + event_len) < ends)) {
+                iwe->len = event_len;
+                memcpy(stream, (char *) iwe, IW_EV_LCP_LEN);
+                memcpy(stream + IW_EV_LCP_LEN,
+                       ((char *) iwe) + IW_EV_LCP_LEN + IW_EV_POINT_OFF,
+                       IW_EV_POINT_LEN - IW_EV_LCP_LEN);
+                memcpy(stream + IW_EV_POINT_LEN, extra, iwe->u.data.length);
+                stream += event_len;
+        } else
+                *perr = -E2BIG;
+        return stream;
+}
+
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add a value to a Wireless Event in a stream of events.
+ * Be careful, this one is tricky to use properly :
+ * At the first run, you need to have (value = event + IW_EV_LCP_LEN).
+ * Same as above, with explicit error check...
+ */
+static inline char *
+iwe_stream_check_add_value(char *       event,          /* Event in the stream */
+                           char *       value,          /* Value in event */
+                           char *       ends,           /* End of stream */
+                           struct iw_event *iwe,        /* Payload */
+                           int          event_len,      /* Size of payload */
+                           int *        perr)           /* Error report */
+{
+        /* Don't duplicate LCP */
+        event_len -= IW_EV_LCP_LEN;
+
+        /* Check if it's possible */
+        if(likely((value + event_len) < ends)) {
+                /* Add new value */
+                memcpy(value, (char *) iwe + IW_EV_LCP_LEN, event_len);
+                value += event_len;
+                /* Patch LCP */
+                iwe->len = value - event;
+                memcpy(event, (char *) iwe, IW_EV_LCP_LEN);
+        } else
+                *perr = -E2BIG;
+        return value;
+}
+
 #endif  /* _IW_HANDLER_H */
diff --git a/include/net/llc.h b/include/net/llc.h
index c9aed2a8b4e2..71769a5aeef3 100644
--- a/include/net/llc.h
+++ b/include/net/llc.h
@@ -46,7 +46,8 @@ struct llc_sap {
         unsigned char    f_bit;
         int              (*rcv_func)(struct sk_buff *skb,
                                      struct net_device *dev,
-                                     struct packet_type *pt);
+                                     struct packet_type *pt,
+                                     struct net_device *orig_dev);
         struct llc_addr  laddr;
         struct list_head node;
         struct {
@@ -64,7 +65,7 @@ extern rwlock_t llc_sap_list_lock;
 extern unsigned char llc_station_mac_sa[ETH_ALEN];
 
 extern int llc_rcv(struct sk_buff *skb, struct net_device *dev,
-                   struct packet_type *pt);
+                   struct packet_type *pt, struct net_device *orig_dev);
 
 extern int llc_mac_hdr_init(struct sk_buff *skb,
                             unsigned char *sa, unsigned char *da);
@@ -78,7 +79,8 @@ extern void llc_set_station_handler(void (*handler)(struct sk_buff *skb));
 extern struct llc_sap *llc_sap_open(unsigned char lsap,
                                     int (*rcv)(struct sk_buff *skb,
                                                struct net_device *dev,
-                                               struct packet_type *pt));
+                                               struct packet_type *pt,
+                                               struct net_device *orig_dev));
 extern void llc_sap_close(struct llc_sap *sap);
 
 extern struct llc_sap *llc_sap_find(unsigned char sap_value);
diff --git a/include/net/neighbour.h b/include/net/neighbour.h
index 4f33bbc21e7f..34c07731933d 100644
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -65,11 +65,10 @@ struct neighbour;
 
 struct neigh_parms
 {
+        struct net_device *dev;
         struct neigh_parms *next;
         int     (*neigh_setup)(struct neighbour *);
         struct neigh_table *tbl;
-        int     entries;
-        void    *priv;
 
         void    *sysctl_table;
 
@@ -192,7 +191,6 @@ struct neigh_table
         atomic_t                entries;
         rwlock_t                lock;
         unsigned long           last_rand;
-        struct neigh_parms      *parms_list;
         kmem_cache_t            *kmem_cachep;
         struct neigh_statistics *stats;
         struct neighbour        **hash_buckets;
@@ -252,6 +250,9 @@ extern int neigh_add(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg);
 extern int neigh_delete(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg);
 extern void neigh_app_ns(struct neighbour *n);
 
+extern int neightbl_dump_info(struct sk_buff *skb, struct netlink_callback *cb);
+extern int neightbl_set(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg);
+
 extern void neigh_for_each(struct neigh_table *tbl, void (*cb)(struct neighbour *, void *), void *cookie);
 extern void __neigh_for_each_release(struct neigh_table *tbl, int (*cb)(struct neighbour *));
 extern void pneigh_for_each(struct neigh_table *tbl, void (*cb)(struct pneigh_entry *));
@@ -362,7 +363,14 @@ __neigh_lookup_errno(struct neigh_table *tbl, const void *pkey,
         return neigh_create(tbl, pkey, dev);
 }
 
-#define LOCALLY_ENQUEUED -2
+struct neighbour_cb {
+        unsigned long sched_next;
+        unsigned int flags;
+};
+
+#define LOCALLY_ENQUEUED 0x1
+
+#define NEIGH_CB(skb)   ((struct neighbour_cb *)(skb)->cb)
 
 #endif
 #endif
diff --git a/include/net/p8022.h b/include/net/p8022.h
index 3c99a86c3581..42e9fac51b31 100644
--- a/include/net/p8022.h
+++ b/include/net/p8022.h
@@ -4,7 +4,10 @@ extern struct datalink_proto *
         register_8022_client(unsigned char type,
                              int (*func)(struct sk_buff *skb,
                                          struct net_device *dev,
-                                         struct packet_type *pt));
+                                         struct packet_type *pt,
+                                         struct net_device *orig_dev));
 extern void unregister_8022_client(struct datalink_proto *proto);
 
+extern struct datalink_proto *make_8023_client(void);
+extern void destroy_8023_client(struct datalink_proto *dl);
 #endif
diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h
index 4abda6aec05a..b902d24a3256 100644
--- a/include/net/pkt_cls.h
+++ b/include/net/pkt_cls.h
@@ -352,10 +352,10 @@ tcf_change_indev(struct tcf_proto *tp, char *indev, struct rtattr *indev_tlv)
 static inline int
 tcf_match_indev(struct sk_buff *skb, char *indev)
 {
-        if (0 != indev[0]) {
-                if  (NULL == skb->input_dev)
+        if (indev[0]) {
+                if  (!skb->input_dev)
                         return 0;
-                else if (0 != strcmp(indev, skb->input_dev->name))
+                if (strcmp(indev, skb->input_dev->name))
                         return 0;
         }
 
diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h
index fcb05a387dbe..6492e7363d84 100644
--- a/include/net/pkt_sched.h
+++ b/include/net/pkt_sched.h
@@ -13,13 +13,12 @@ struct qdisc_walker
 
 extern rwlock_t qdisc_tree_lock;
 
-#define QDISC_ALIGN             32
-#define QDISC_ALIGN_CONST       (QDISC_ALIGN - 1)
+#define QDISC_ALIGNTO           32
+#define QDISC_ALIGN(len)        (((len) + QDISC_ALIGNTO-1) & ~(QDISC_ALIGNTO-1))
 
 static inline void *qdisc_priv(struct Qdisc *q)
 {
-        return (char *)q + ((sizeof(struct Qdisc) + QDISC_ALIGN_CONST)
-                              & ~QDISC_ALIGN_CONST);
+        return (char *) q + QDISC_ALIGN(sizeof(struct Qdisc));
 }
 
 /* 
@@ -207,8 +206,6 @@ psched_tod_diff(int delta_sec, int bound)
 
 #endif /* !CONFIG_NET_SCH_CLK_GETTIMEOFDAY */
 
-extern struct Qdisc noop_qdisc;
-extern struct Qdisc_ops noop_qdisc_ops;
 extern struct Qdisc_ops pfifo_qdisc_ops;
 extern struct Qdisc_ops bfifo_qdisc_ops;
 
@@ -216,14 +213,6 @@ extern int register_qdisc(struct Qdisc_ops *qops);
 extern int unregister_qdisc(struct Qdisc_ops *qops);
 extern struct Qdisc *qdisc_lookup(struct net_device *dev, u32 handle);
 extern struct Qdisc *qdisc_lookup_class(struct net_device *dev, u32 handle);
-extern void dev_init_scheduler(struct net_device *dev);
-extern void dev_shutdown(struct net_device *dev);
-extern void dev_activate(struct net_device *dev);
-extern void dev_deactivate(struct net_device *dev);
-extern void qdisc_reset(struct Qdisc *qdisc);
-extern void qdisc_destroy(struct Qdisc *qdisc);
-extern struct Qdisc * qdisc_create_dflt(struct net_device *dev,
-        struct Qdisc_ops *ops);
 extern struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r,
                 struct rtattr *tab);
 extern void qdisc_put_rtab(struct qdisc_rate_table *tab);
diff --git a/include/net/psnap.h b/include/net/psnap.h
index 9c94e8f98b36..b2e01cc3fc8a 100644
--- a/include/net/psnap.h
+++ b/include/net/psnap.h
@@ -1,7 +1,7 @@
 #ifndef _NET_PSNAP_H
 #define _NET_PSNAP_H
 
-extern struct datalink_proto *register_snap_client(unsigned char *desc, int (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *));
+extern struct datalink_proto *register_snap_client(unsigned char *desc, int (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *orig_dev));
 extern void unregister_snap_client(struct datalink_proto *proto);
 
 #endif
diff --git a/include/net/raw.h b/include/net/raw.h
index 1c411c45587a..f47917469b12 100644
--- a/include/net/raw.h
+++ b/include/net/raw.h
@@ -17,10 +17,10 @@
 #ifndef _RAW_H
 #define _RAW_H
 
+#include <linux/config.h>
 
 extern struct proto raw_prot;
 
-
 extern void     raw_err(struct sock *, struct sk_buff *, u32 info);
 extern int      raw_rcv(struct sock *, struct sk_buff *);
 
@@ -37,6 +37,11 @@ extern struct sock *__raw_v4_lookup(struct sock *sk, unsigned short num,
                                     unsigned long raddr, unsigned long laddr,
                                     int dif);
 
-extern void raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash);
+extern int raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash);
+
+#ifdef CONFIG_PROC_FS
+extern int  raw_proc_init(void);
+extern void raw_proc_exit(void);
+#endif
 
 #endif  /* _RAW_H */
diff --git a/include/net/rawv6.h b/include/net/rawv6.h
index 23fd9a6a221a..14476a71725e 100644
--- a/include/net/rawv6.h
+++ b/include/net/rawv6.h
@@ -7,10 +7,11 @@
 extern struct hlist_head raw_v6_htable[RAWV6_HTABLE_SIZE];
 extern rwlock_t raw_v6_lock;
 
-extern void ipv6_raw_deliver(struct sk_buff *skb, int nexthdr);
+extern int ipv6_raw_deliver(struct sk_buff *skb, int nexthdr);
 
 extern struct sock *__raw_v6_lookup(struct sock *sk, unsigned short num,
-                                    struct in6_addr *loc_addr, struct in6_addr *rmt_addr);
+                                    struct in6_addr *loc_addr, struct in6_addr *rmt_addr,
+                                    int dif);
 
 extern int                      rawv6_rcv(struct sock *sk,
                                           struct sk_buff *skb);
diff --git a/include/net/request_sock.h b/include/net/request_sock.h
new file mode 100644
index 000000000000..b52cc52ffe39
--- /dev/null
+++ b/include/net/request_sock.h
@@ -0,0 +1,261 @@
+/*
+ * NET          Generic infrastructure for Network protocols.
+ *
+ *              Definitions for request_sock 
+ *
+ * Authors:     Arnaldo Carvalho de Melo <acme@conectiva.com.br>
+ *
+ *              From code originally in include/net/tcp.h
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+#ifndef _REQUEST_SOCK_H
+#define _REQUEST_SOCK_H
+
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <net/sock.h>
+
+struct request_sock;
+struct sk_buff;
+struct dst_entry;
+struct proto;
+
+struct request_sock_ops {
+        int             family;
+        kmem_cache_t    *slab;
+        int             obj_size;
+        int             (*rtx_syn_ack)(struct sock *sk,
+                                       struct request_sock *req,
+                                       struct dst_entry *dst);
+        void            (*send_ack)(struct sk_buff *skb,
+                                    struct request_sock *req);
+        void            (*send_reset)(struct sk_buff *skb);
+        void            (*destructor)(struct request_sock *req);
+};
+
+/* struct request_sock - mini sock to represent a connection request
+ */
+struct request_sock {
+        struct request_sock             *dl_next; /* Must be first member! */
+        u16                             mss;
+        u8                              retrans;
+        u8                              __pad;
+        /* The following two fields can be easily recomputed I think -AK */
+        u32                             window_clamp; /* window clamp at creation time */
+        u32                             rcv_wnd;          /* rcv_wnd offered first time */
+        u32                             ts_recent;
+        unsigned long                   expires;
+        struct request_sock_ops         *rsk_ops;
+        struct sock                     *sk;
+};
+
+static inline struct request_sock *reqsk_alloc(struct request_sock_ops *ops)
+{
+        struct request_sock *req = kmem_cache_alloc(ops->slab, SLAB_ATOMIC);
+
+        if (req != NULL)
+                req->rsk_ops = ops;
+
+        return req;
+}
+
+static inline void __reqsk_free(struct request_sock *req)
+{
+        kmem_cache_free(req->rsk_ops->slab, req);
+}
+
+static inline void reqsk_free(struct request_sock *req)
+{
+        req->rsk_ops->destructor(req);
+        __reqsk_free(req);
+}
+
+extern int sysctl_max_syn_backlog;
+
+/** struct listen_sock - listen state
+ *
+ * @max_qlen_log - log_2 of maximal queued SYNs/REQUESTs
+ */
+struct listen_sock {
+        u8                      max_qlen_log;
+        /* 3 bytes hole, try to use */
+        int                     qlen;
+        int                     qlen_young;
+        int                     clock_hand;
+        u32                     hash_rnd;
+        u32                     nr_table_entries;
+        struct request_sock     *syn_table[0];
+};
+
+/** struct request_sock_queue - queue of request_socks
+ *
+ * @rskq_accept_head - FIFO head of established children
+ * @rskq_accept_tail - FIFO tail of established children
+ * @rskq_defer_accept - User waits for some data after accept()
+ * @syn_wait_lock - serializer
+ *
+ * %syn_wait_lock is necessary only to avoid proc interface having to grab the main
+ * lock sock while browsing the listening hash (otherwise it's deadlock prone).
+ *
+ * This lock is acquired in read mode only from listening_get_next() seq_file
+ * op and it's acquired in write mode _only_ from code that is actively
+ * changing rskq_accept_head. All readers that are holding the master sock lock
+ * don't need to grab this lock in read mode too as rskq_accept_head. writes
+ * are always protected from the main sock lock.
+ */
+struct request_sock_queue {
+        struct request_sock     *rskq_accept_head;
+        struct request_sock     *rskq_accept_tail;
+        rwlock_t                syn_wait_lock;
+        u8                      rskq_defer_accept;
+        /* 3 bytes hole, try to pack */
+        struct listen_sock      *listen_opt;
+};
+
+extern int reqsk_queue_alloc(struct request_sock_queue *queue,
+                             const int nr_table_entries);
+
+static inline struct listen_sock *reqsk_queue_yank_listen_sk(struct request_sock_queue *queue)
+{
+        struct listen_sock *lopt;
+
+        write_lock_bh(&queue->syn_wait_lock);
+        lopt = queue->listen_opt;
+        queue->listen_opt = NULL;
+        write_unlock_bh(&queue->syn_wait_lock);
+
+        return lopt;
+}
+
+static inline void __reqsk_queue_destroy(struct request_sock_queue *queue)
+{
+        kfree(reqsk_queue_yank_listen_sk(queue));
+}
+
+extern void reqsk_queue_destroy(struct request_sock_queue *queue);
+
+static inline struct request_sock *
+        reqsk_queue_yank_acceptq(struct request_sock_queue *queue)
+{
+        struct request_sock *req = queue->rskq_accept_head;
+
+        queue->rskq_accept_head = queue->rskq_accept_head = NULL;
+        return req;
+}
+
+static inline int reqsk_queue_empty(struct request_sock_queue *queue)
+{
+        return queue->rskq_accept_head == NULL;
+}
+
+static inline void reqsk_queue_unlink(struct request_sock_queue *queue,
+                                      struct request_sock *req,
+                                      struct request_sock **prev_req)
+{
+        write_lock(&queue->syn_wait_lock);
+        *prev_req = req->dl_next;
+        write_unlock(&queue->syn_wait_lock);
+}
+
+static inline void reqsk_queue_add(struct request_sock_queue *queue,
+                                   struct request_sock *req,
+                                   struct sock *parent,
+                                   struct sock *child)
+{
+        req->sk = child;
+        sk_acceptq_added(parent);
+
+        if (queue->rskq_accept_head == NULL)
+                queue->rskq_accept_head = req;
+        else
+                queue->rskq_accept_tail->dl_next = req;
+
+        queue->rskq_accept_tail = req;
+        req->dl_next = NULL;
+}
+
+static inline struct request_sock *reqsk_queue_remove(struct request_sock_queue *queue)
+{
+        struct request_sock *req = queue->rskq_accept_head;
+
+        BUG_TRAP(req != NULL);
+
+        queue->rskq_accept_head = req->dl_next;
+        if (queue->rskq_accept_head == NULL)
+                queue->rskq_accept_tail = NULL;
+
+        return req;
+}
+
+static inline struct sock *reqsk_queue_get_child(struct request_sock_queue *queue,
+                                                 struct sock *parent)
+{
+        struct request_sock *req = reqsk_queue_remove(queue);
+        struct sock *child = req->sk;
+
+        BUG_TRAP(child != NULL);
+
+        sk_acceptq_removed(parent);
+        __reqsk_free(req);
+        return child;
+}
+
+static inline int reqsk_queue_removed(struct request_sock_queue *queue,
+                                      struct request_sock *req)
+{
+        struct listen_sock *lopt = queue->listen_opt;
+
+        if (req->retrans == 0)
+                --lopt->qlen_young;
+
+        return --lopt->qlen;
+}
+
+static inline int reqsk_queue_added(struct request_sock_queue *queue)
+{
+        struct listen_sock *lopt = queue->listen_opt;
+        const int prev_qlen = lopt->qlen;
+
+        lopt->qlen_young++;
+        lopt->qlen++;
+        return prev_qlen;
+}
+
+static inline int reqsk_queue_len(const struct request_sock_queue *queue)
+{
+        return queue->listen_opt != NULL ? queue->listen_opt->qlen : 0;
+}
+
+static inline int reqsk_queue_len_young(const struct request_sock_queue *queue)
+{
+        return queue->listen_opt->qlen_young;
+}
+
+static inline int reqsk_queue_is_full(const struct request_sock_queue *queue)
+{
+        return queue->listen_opt->qlen >> queue->listen_opt->max_qlen_log;
+}
+
+static inline void reqsk_queue_hash_req(struct request_sock_queue *queue,
+                                        u32 hash, struct request_sock *req,
+                                        unsigned timeout)
+{
+        struct listen_sock *lopt = queue->listen_opt;
+
+        req->expires = jiffies + timeout;
+        req->retrans = 0;
+        req->sk = NULL;
+        req->dl_next = lopt->syn_table[hash];
+
+        write_lock(&queue->syn_wait_lock);
+        lopt->syn_table[hash] = req;
+        write_unlock(&queue->syn_wait_lock);
+}
+
+#endif /* _REQUEST_SOCK_H */
diff --git a/include/net/route.h b/include/net/route.h
index d34ca8fc6756..dbe79ca67d31 100644
--- a/include/net/route.h
+++ b/include/net/route.h
@@ -105,10 +105,6 @@ struct rt_cache_stat
         unsigned int out_hlist_search;
 };
 
-extern struct rt_cache_stat *rt_cache_stat;
-#define RT_CACHE_STAT_INC(field)                                          \
-                (per_cpu_ptr(rt_cache_stat, _smp_processor_id())->field++)
-
 extern struct ip_rt_acct *ip_rt_acct;
 
 struct in_device;
@@ -199,4 +195,6 @@ static inline struct inet_peer *rt_get_peer(struct rtable *rt)
         return rt->peer;
 }
 
+extern ctl_table ipv4_route_table[];
+
 #endif  /* _ROUTE_H */
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index c57504b3b518..7b6ec9986715 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -164,6 +164,19 @@ extern void qdisc_unlock_tree(struct net_device *dev);
 #define tcf_tree_lock(tp)       qdisc_lock_tree((tp)->q->dev)
 #define tcf_tree_unlock(tp)     qdisc_unlock_tree((tp)->q->dev)
 
+extern struct Qdisc noop_qdisc;
+extern struct Qdisc_ops noop_qdisc_ops;
+
+extern void dev_init_scheduler(struct net_device *dev);
+extern void dev_shutdown(struct net_device *dev);
+extern void dev_activate(struct net_device *dev);
+extern void dev_deactivate(struct net_device *dev);
+extern void qdisc_reset(struct Qdisc *qdisc);
+extern void qdisc_destroy(struct Qdisc *qdisc);
+extern struct Qdisc *qdisc_alloc(struct net_device *dev, struct Qdisc_ops *ops);
+extern struct Qdisc *qdisc_create_dflt(struct net_device *dev,
+                                       struct Qdisc_ops *ops);
+
 static inline void
 tcf_destroy(struct tcf_proto *tp)
 {
@@ -172,4 +185,126 @@ tcf_destroy(struct tcf_proto *tp)
         kfree(tp);
 }
 
+static inline int __qdisc_enqueue_tail(struct sk_buff *skb, struct Qdisc *sch,
+                                       struct sk_buff_head *list)
+{
+        __skb_queue_tail(list, skb);
+        sch->qstats.backlog += skb->len;
+        sch->bstats.bytes += skb->len;
+        sch->bstats.packets++;
+
+        return NET_XMIT_SUCCESS;
+}
+
+static inline int qdisc_enqueue_tail(struct sk_buff *skb, struct Qdisc *sch)
+{
+        return __qdisc_enqueue_tail(skb, sch, &sch->q);
+}
+
+static inline struct sk_buff *__qdisc_dequeue_head(struct Qdisc *sch,
+                                                   struct sk_buff_head *list)
+{
+        struct sk_buff *skb = __skb_dequeue(list);
+
+        if (likely(skb != NULL))
+                sch->qstats.backlog -= skb->len;
+
+        return skb;
+}
+
+static inline struct sk_buff *qdisc_dequeue_head(struct Qdisc *sch)
+{
+        return __qdisc_dequeue_head(sch, &sch->q);
+}
+
+static inline struct sk_buff *__qdisc_dequeue_tail(struct Qdisc *sch,
+                                                   struct sk_buff_head *list)
+{
+        struct sk_buff *skb = __skb_dequeue_tail(list);
+
+        if (likely(skb != NULL))
+                sch->qstats.backlog -= skb->len;
+
+        return skb;
+}
+
+static inline struct sk_buff *qdisc_dequeue_tail(struct Qdisc *sch)
+{
+        return __qdisc_dequeue_tail(sch, &sch->q);
+}
+
+static inline int __qdisc_requeue(struct sk_buff *skb, struct Qdisc *sch,
+                                  struct sk_buff_head *list)
+{
+        __skb_queue_head(list, skb);
+        sch->qstats.backlog += skb->len;
+        sch->qstats.requeues++;
+
+        return NET_XMIT_SUCCESS;
+}
+
+static inline int qdisc_requeue(struct sk_buff *skb, struct Qdisc *sch)
+{
+        return __qdisc_requeue(skb, sch, &sch->q);
+}
+
+static inline void __qdisc_reset_queue(struct Qdisc *sch,
+                                       struct sk_buff_head *list)
+{
+        /*
+         * We do not know the backlog in bytes of this list, it
+         * is up to the caller to correct it
+         */
+        skb_queue_purge(list);
+}
+
+static inline void qdisc_reset_queue(struct Qdisc *sch)
+{
+        __qdisc_reset_queue(sch, &sch->q);
+        sch->qstats.backlog = 0;
+}
+
+static inline unsigned int __qdisc_queue_drop(struct Qdisc *sch,
+                                              struct sk_buff_head *list)
+{
+        struct sk_buff *skb = __qdisc_dequeue_tail(sch, list);
+
+        if (likely(skb != NULL)) {
+                unsigned int len = skb->len;
+                kfree_skb(skb);
+                return len;
+        }
+
+        return 0;
+}
+
+static inline unsigned int qdisc_queue_drop(struct Qdisc *sch)
+{
+        return __qdisc_queue_drop(sch, &sch->q);
+}
+
+static inline int qdisc_drop(struct sk_buff *skb, struct Qdisc *sch)
+{
+        kfree_skb(skb);
+        sch->qstats.drops++;
+
+        return NET_XMIT_DROP;
+}
+
+static inline int qdisc_reshape_fail(struct sk_buff *skb, struct Qdisc *sch)
+{
+        sch->qstats.drops++;
+
+#ifdef CONFIG_NET_CLS_POLICE
+        if (sch->reshape_fail == NULL || sch->reshape_fail(skb, sch))
+                goto drop;
+
+        return NET_XMIT_SUCCESS;
+
+drop:
+#endif
+        kfree_skb(skb);
+        return NET_XMIT_DROP;
+}
+
 #endif
diff --git a/include/net/sctp/command.h b/include/net/sctp/command.h
index ebc5282e6d58..dc107ffad483 100644
--- a/include/net/sctp/command.h
+++ b/include/net/sctp/command.h
@@ -65,9 +65,11 @@ typedef enum {
         SCTP_CMD_TIMER_START,   /* Start a timer.  */
         SCTP_CMD_TIMER_RESTART, /* Restart a timer. */
         SCTP_CMD_TIMER_STOP,    /* Stop a timer. */
-        SCTP_CMD_COUNTER_RESET, /* Reset a counter. */
-        SCTP_CMD_COUNTER_INC,   /* Increment a counter. */
+        SCTP_CMD_INIT_CHOOSE_TRANSPORT, /* Choose transport for an INIT. */
+        SCTP_CMD_INIT_COUNTER_RESET, /* Reset init counter. */
+        SCTP_CMD_INIT_COUNTER_INC,   /* Increment init counter. */
         SCTP_CMD_INIT_RESTART,  /* High level, do init timer work. */
+        SCTP_CMD_COOKIEECHO_RESTART,  /* High level, do cookie-echo timer work. */
         SCTP_CMD_INIT_FAILED,   /* High level, do init failure work. */
         SCTP_CMD_REPORT_DUP,    /* Report a duplicate TSN.  */
         SCTP_CMD_STRIKE,        /* Mark a strike against a transport.  */
@@ -118,7 +120,6 @@ typedef union {
         int error;
         sctp_state_t state;
         sctp_event_timeout_t to;
-        sctp_counter_t counter;
         void *ptr;
         struct sctp_chunk *chunk;
         struct sctp_association *asoc;
@@ -165,7 +166,6 @@ SCTP_ARG_CONSTRUCTOR(U16,	__u16, u16)
 SCTP_ARG_CONSTRUCTOR(U8,        __u8, u8)
 SCTP_ARG_CONSTRUCTOR(ERROR,     int, error)
 SCTP_ARG_CONSTRUCTOR(STATE,     sctp_state_t, state)
-SCTP_ARG_CONSTRUCTOR(COUNTER,   sctp_counter_t, counter)
 SCTP_ARG_CONSTRUCTOR(TO,        sctp_event_timeout_t, to)
 SCTP_ARG_CONSTRUCTOR(PTR,       void *, ptr)
 SCTP_ARG_CONSTRUCTOR(CHUNK,     struct sctp_chunk *, chunk)
diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h
index 2b76c0f4babc..c51541ee0247 100644
--- a/include/net/sctp/constants.h
+++ b/include/net/sctp/constants.h
@@ -47,10 +47,10 @@
 #ifndef __sctp_constants_h__
 #define __sctp_constants_h__
 
-#include <linux/tcp.h>  /* For TCP states used in sctp_sock_state_t */
 #include <linux/sctp.h>
 #include <linux/ipv6.h> /* For ipv6hdr. */
 #include <net/sctp/user.h>
+#include <net/tcp_states.h>  /* For TCP states used in sctp_sock_state_t */
 
 /* Value used for stream negotiation. */
 enum { SCTP_MAX_STREAM = 0xffff };
@@ -263,30 +263,11 @@ enum { SCTP_MIN_PMTU = 576 };
 enum { SCTP_MAX_DUP_TSNS = 16 };
 enum { SCTP_MAX_GABS = 16 };
 
-typedef enum {
-        SCTP_COUNTER_INIT_ERROR,
-} sctp_counter_t;
-
-/* How many counters does an association need? */
-#define SCTP_NUMBER_COUNTERS    5
-
-/* Here we define the default timers.  */
-
-/* cookie timer def = ? seconds */
-#define SCTP_DEFAULT_TIMEOUT_T1_COOKIE  (3 * HZ)
-
-/* init timer def = 3 seconds  */
-#define SCTP_DEFAULT_TIMEOUT_T1_INIT    (3 * HZ)
-
-/* shutdown timer def = 300 ms */
-#define SCTP_DEFAULT_TIMEOUT_T2_SHUTDOWN ((300 * HZ) / 1000)
-
-/* 0 seconds + RTO */
-#define SCTP_DEFAULT_TIMEOUT_HEARTBEAT  (10 * HZ)
+/* Heartbeat interval - 30 secs */
+#define SCTP_DEFAULT_TIMEOUT_HEARTBEAT  (30 * HZ)
 
-/* recv timer def = 200ms (in usec) */
+/* Delayed sack timer - 200ms */
 #define SCTP_DEFAULT_TIMEOUT_SACK       ((200 * HZ) / 1000)
-#define SCTP_DEFAULT_TIMEOUT_SACK_MAX   ((500 * HZ) / 1000) /* 500 ms */
 
 /* RTO.Initial              - 3  seconds
  * RTO.Min                  - 1  second
diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h
index 960abfa48d68..e1d5ec1c23c0 100644
--- a/include/net/sctp/sctp.h
+++ b/include/net/sctp/sctp.h
@@ -125,7 +125,8 @@
  */
 extern struct sock *sctp_get_ctl_sock(void);
 extern int sctp_copy_local_addr_list(struct sctp_bind_addr *,
-                                     sctp_scope_t, int gfp, int flags);
+                                     sctp_scope_t, unsigned int __nocast gfp,
+                                     int flags);
 extern struct sctp_pf *sctp_get_pf_specific(sa_family_t family);
 extern int sctp_register_pf(struct sctp_pf *, sa_family_t);
 
@@ -166,15 +167,12 @@ void sctp_unhash_established(struct sctp_association *);
 void sctp_hash_endpoint(struct sctp_endpoint *);
 void sctp_unhash_endpoint(struct sctp_endpoint *);
 struct sock *sctp_err_lookup(int family, struct sk_buff *,
-                             struct sctphdr *, struct sctp_endpoint **,
-                             struct sctp_association **,
+                             struct sctphdr *, struct sctp_association **,
                              struct sctp_transport **);
-void sctp_err_finish(struct sock *, struct sctp_endpoint *,
-                            struct sctp_association *);
+void sctp_err_finish(struct sock *, struct sctp_association *);
 void sctp_icmp_frag_needed(struct sock *, struct sctp_association *,
                            struct sctp_transport *t, __u32 pmtu);
 void sctp_icmp_proto_unreachable(struct sock *sk,
-                                 struct sctp_endpoint *ep,
                                  struct sctp_association *asoc,
                                  struct sctp_transport *t);
 
@@ -223,6 +221,22 @@ DECLARE_SNMP_STAT(struct sctp_mib, sctp_statistics);
 extern int sctp_debug_flag;
 #define SCTP_DEBUG_PRINTK(whatever...) \
         ((void) (sctp_debug_flag && printk(KERN_DEBUG whatever)))
+#define SCTP_DEBUG_PRINTK_IPADDR(lead, trail, leadparm, saddr, otherparms...) \
+        if (sctp_debug_flag) { \
+                if (saddr->sa.sa_family == AF_INET6) { \
+                        printk(KERN_DEBUG \
+                               lead "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x" trail, \
+                               leadparm, \
+                               NIP6(saddr->v6.sin6_addr), \
+                               otherparms); \
+                } else { \
+                        printk(KERN_DEBUG \
+                               lead "%u.%u.%u.%u" trail, \
+                               leadparm, \
+                               NIPQUAD(saddr->v4.sin_addr.s_addr), \
+                               otherparms); \
+                } \
+        }
 #define SCTP_ENABLE_DEBUG { sctp_debug_flag = 1; }
 #define SCTP_DISABLE_DEBUG { sctp_debug_flag = 0; }
 
@@ -236,6 +250,7 @@ extern int sctp_debug_flag;
 #else   /* SCTP_DEBUG */
 
 #define SCTP_DEBUG_PRINTK(whatever...)
+#define SCTP_DEBUG_PRINTK_IPADDR(whatever...)
 #define SCTP_ENABLE_DEBUG
 #define SCTP_DISABLE_DEBUG
 #define SCTP_ASSERT(expr, str, func)
diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h
index f4fcee104707..58462164d960 100644
--- a/include/net/sctp/sm.h
+++ b/include/net/sctp/sm.h
@@ -116,7 +116,8 @@ sctp_state_fn_t sctp_sf_eat_data_fast_4_4;
 sctp_state_fn_t sctp_sf_eat_sack_6_2;
 sctp_state_fn_t sctp_sf_tabort_8_4_8;
 sctp_state_fn_t sctp_sf_operr_notify;
-sctp_state_fn_t sctp_sf_t1_timer_expire;
+sctp_state_fn_t sctp_sf_t1_init_timer_expire;
+sctp_state_fn_t sctp_sf_t1_cookie_timer_expire;
 sctp_state_fn_t sctp_sf_t2_timer_expire;
 sctp_state_fn_t sctp_sf_t4_timer_expire;
 sctp_state_fn_t sctp_sf_t5_timer_expire;
@@ -130,7 +131,6 @@ sctp_state_fn_t sctp_sf_do_ecne;
 sctp_state_fn_t sctp_sf_ootb;
 sctp_state_fn_t sctp_sf_pdiscard;
 sctp_state_fn_t sctp_sf_violation;
-sctp_state_fn_t sctp_sf_violation_chunklen;
 sctp_state_fn_t sctp_sf_discard_chunk;
 sctp_state_fn_t sctp_sf_do_5_2_1_siminit;
 sctp_state_fn_t sctp_sf_do_5_2_2_dupinit;
@@ -181,17 +181,17 @@ const sctp_sm_table_entry_t *sctp_sm_lookup_event(sctp_event_t,
 int sctp_chunk_iif(const struct sctp_chunk *);
 struct sctp_association *sctp_make_temp_asoc(const struct sctp_endpoint *,
                                              struct sctp_chunk *,
-                                             int gfp);
+                                             unsigned int __nocast gfp);
 __u32 sctp_generate_verification_tag(void);
 void sctp_populate_tie_tags(__u8 *cookie, __u32 curTag, __u32 hisTag);
 
 /* Prototypes for chunk-building functions.  */
 struct sctp_chunk *sctp_make_init(const struct sctp_association *,
                              const struct sctp_bind_addr *,
-                             int gfp, int vparam_len);
+                             unsigned int __nocast gfp, int vparam_len);
 struct sctp_chunk *sctp_make_init_ack(const struct sctp_association *,
                                  const struct sctp_chunk *,
-                                 const int gfp,
+                                 const unsigned int __nocast gfp,
                                  const int unkparam_len);
 struct sctp_chunk *sctp_make_cookie_echo(const struct sctp_association *,
                                     const struct sctp_chunk *);
@@ -258,8 +258,6 @@ struct sctp_chunk *sctp_make_fwdtsn(const struct sctp_association *asoc,
 void sctp_chunk_assign_tsn(struct sctp_chunk *);
 void sctp_chunk_assign_ssn(struct sctp_chunk *);
 
-void sctp_stop_t1_and_abort(sctp_cmd_seq_t *commands, __u16 error);
-
 /* Prototypes for statetable processing. */
 
 int sctp_do_sm(sctp_event_t event_type, sctp_subtype_t subtype,
@@ -267,7 +265,7 @@ int sctp_do_sm(sctp_event_t event_type, sctp_subtype_t subtype,
                struct sctp_endpoint *,
                struct sctp_association *asoc,
                void *event_arg,
-               int gfp);
+               unsigned int __nocast gfp);
 
 /* 2nd level prototypes */
 void sctp_generate_t3_rtx_event(unsigned long peer);
@@ -277,7 +275,8 @@ void sctp_ootb_pkt_free(struct sctp_packet *);
 
 struct sctp_association *sctp_unpack_cookie(const struct sctp_endpoint *,
                                        const struct sctp_association *,
-                                       struct sctp_chunk *, int gfp, int *err,
+                                       struct sctp_chunk *,
+                                       unsigned int __nocast gfp, int *err,
                                        struct sctp_chunk **err_chk_p);
 int sctp_addip_addr_config(struct sctp_association *, sctp_param_t,
                            struct sockaddr_storage*, int);
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index 6c24d9cd3d66..994009bbe3b4 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -161,6 +161,9 @@ extern struct sctp_globals {
          */
         int sndbuf_policy;
 
+        /* Delayed SACK timeout  200ms default*/
+        int sack_timeout;
+
         /* HB.interval              - 30 seconds  */
         int hb_interval;
 
@@ -217,6 +220,7 @@ extern struct sctp_globals {
 #define sctp_sndbuf_policy              (sctp_globals.sndbuf_policy)
 #define sctp_max_retrans_path           (sctp_globals.max_retrans_path)
 #define sctp_max_retrans_init           (sctp_globals.max_retrans_init)
+#define sctp_sack_timeout               (sctp_globals.sack_timeout)
 #define sctp_hb_interval                (sctp_globals.hb_interval)
 #define sctp_max_instreams              (sctp_globals.max_instreams)
 #define sctp_max_outstreams             (sctp_globals.max_outstreams)
@@ -441,7 +445,8 @@ struct sctp_ssnmap {
         int malloced;
 };
 
-struct sctp_ssnmap *sctp_ssnmap_new(__u16 in, __u16 out, int gfp);
+struct sctp_ssnmap *sctp_ssnmap_new(__u16 in, __u16 out,
+                                    unsigned int __nocast gfp);
 void sctp_ssnmap_free(struct sctp_ssnmap *map);
 void sctp_ssnmap_clear(struct sctp_ssnmap *map);
 
@@ -578,7 +583,6 @@ void sctp_datamsg_track(struct sctp_chunk *);
 void sctp_chunk_fail(struct sctp_chunk *, int error);
 int sctp_chunk_abandoned(struct sctp_chunk *);
 
-
 /* RFC2960 1.4 Key Terms
  *
  * o Chunk: A unit of information within an SCTP packet, consisting of
@@ -588,13 +592,8 @@ int sctp_chunk_abandoned(struct sctp_chunk *);
  * each chunk as well as a few other header pointers...
  */
 struct sctp_chunk {
-        /* These first three elements MUST PRECISELY match the first
-         * three elements of struct sk_buff.  This allows us to reuse
-         * all the skb_* queue management functions.
-         */
-        struct sctp_chunk *next;
-        struct sctp_chunk *prev;
-        struct sk_buff_head *list;
+        struct list_head list;
+
         atomic_t refcnt;
 
         /* This is our link to the per-transport transmitted list.  */
@@ -713,7 +712,7 @@ struct sctp_packet {
         __u32 vtag;
 
         /* This contains the payload chunks.  */
-        struct sk_buff_head chunks;
+        struct list_head chunk_list;
 
         /* This is the overhead of the sctp and ip headers. */
         size_t overhead;
@@ -867,10 +866,13 @@ struct sctp_transport {
          */
         unsigned long last_time_ecne_reduced;
 
-        /* active      : The current active state of this destination,
-         *             :  i.e. DOWN, UP, etc.
+        /* The number of times INIT has been sent on this transport. */
+        int init_sent_count;
+
+        /* state       : The current state of this destination,
+         *             : i.e. SCTP_ACTIVE, SCTP_INACTIVE, SCTP_UNKOWN.
          */
-        int active;
+        int state;
 
         /* hb_allowed  : The current heartbeat state of this destination,
          *             :  i.e. ALLOW-HB, NO-HEARTBEAT, etc.
@@ -944,7 +946,8 @@ struct sctp_transport {
         } cacc;
 };
 
-struct sctp_transport *sctp_transport_new(const union sctp_addr *, int);
+struct sctp_transport *sctp_transport_new(const union sctp_addr *,
+                                          unsigned int __nocast);
 void sctp_transport_set_owner(struct sctp_transport *,
                               struct sctp_association *);
 void sctp_transport_route(struct sctp_transport *, union sctp_addr *,
@@ -967,7 +970,7 @@ struct sctp_inq {
         /* This is actually a queue of sctp_chunk each
          * containing a partially decoded packet.
          */
-        struct sk_buff_head in;
+        struct list_head in_chunk_list;
         /* This is the packet which is currently off the in queue and is
          * being worked on through the inbound chunk processing.
          */
@@ -1010,7 +1013,7 @@ struct sctp_outq {
         struct sctp_association *asoc;
 
         /* Data pending that has never been transmitted.  */
-        struct sk_buff_head out;
+        struct list_head out_chunk_list;
 
         unsigned out_qlen;      /* Total length of queued data chunks. */
 
@@ -1018,7 +1021,7 @@ struct sctp_outq {
         unsigned error;
 
         /* These are control chunks we want to send.  */
-        struct sk_buff_head control;
+        struct list_head control_chunk_list;
 
         /* These are chunks that have been sacked but are above the
          * CTSN, or cumulative tsn ack point.
@@ -1092,9 +1095,10 @@ void sctp_bind_addr_init(struct sctp_bind_addr *, __u16 port);
 void sctp_bind_addr_free(struct sctp_bind_addr *);
 int sctp_bind_addr_copy(struct sctp_bind_addr *dest,
                         const struct sctp_bind_addr *src,
-                        sctp_scope_t scope, int gfp,int flags);
+                        sctp_scope_t scope, unsigned int __nocast gfp,
+                        int flags);
 int sctp_add_bind_addr(struct sctp_bind_addr *, union sctp_addr *,
-                       int gfp);
+                       unsigned int __nocast gfp);
 int sctp_del_bind_addr(struct sctp_bind_addr *, union sctp_addr *);
 int sctp_bind_addr_match(struct sctp_bind_addr *, const union sctp_addr *,
                          struct sctp_sock *);
@@ -1103,9 +1107,10 @@ union sctp_addr *sctp_find_unmatch_addr(struct sctp_bind_addr	*bp,
                                         int                     addrcnt,
                                         struct sctp_sock        *opt);
 union sctp_params sctp_bind_addrs_to_raw(const struct sctp_bind_addr *bp,
-                                         int *addrs_len, int gfp);
+                                         int *addrs_len,
+                                         unsigned int __nocast gfp);
 int sctp_raw_to_bind_addrs(struct sctp_bind_addr *bp, __u8 *raw, int len,
-                           __u16 port, int gfp);
+                           __u16 port, unsigned int __nocast gfp);
 
 sctp_scope_t sctp_scope(const union sctp_addr *);
 int sctp_in_scope(const union sctp_addr *addr, const sctp_scope_t scope);
@@ -1222,9 +1227,6 @@ struct sctp_endpoint {
 
         /* sendbuf acct. policy.        */
         __u32 sndbuf_policy;
-
-        /* Name for debugging output... */
-        char *debug_name;
 };
 
 /* Recover the outter endpoint structure. */
@@ -1237,7 +1239,7 @@ static inline struct sctp_endpoint *sctp_ep(struct sctp_ep_common *base)
 }
 
 /* These are function signatures for manipulating endpoints.  */
-struct sctp_endpoint *sctp_endpoint_new(struct sock *, int);
+struct sctp_endpoint *sctp_endpoint_new(struct sock *, unsigned int __nocast);
 void sctp_endpoint_free(struct sctp_endpoint *);
 void sctp_endpoint_put(struct sctp_endpoint *);
 void sctp_endpoint_hold(struct sctp_endpoint *);
@@ -1258,7 +1260,7 @@ int sctp_verify_init(const struct sctp_association *asoc, sctp_cid_t,
                      struct sctp_chunk **err_chunk);
 int sctp_process_init(struct sctp_association *, sctp_cid_t cid,
                       const union sctp_addr *peer,
-                      sctp_init_chunk_t *init, int gfp);
+                      sctp_init_chunk_t *init, unsigned int __nocast gfp);
 __u32 sctp_generate_tag(const struct sctp_endpoint *);
 __u32 sctp_generate_tsn(const struct sctp_endpoint *);
 
@@ -1314,11 +1316,23 @@ struct sctp_association {
                  *             : association. Normally this information is
                  *             : hashed or keyed for quick lookup and access
                  *             : of the TCB.
+                 *             : The list is also initialized with the list
+                 *             : of addresses passed with the sctp_connectx()
+                 *             : call.
                  *
                  * It is a list of SCTP_transport's.
                  */
                 struct list_head transport_addr_list;
 
+                /* transport_count
+                 *
+                 * Peer        : A count of the number of peer addresses
+                 * Transport   : in the Peer Transport Address List.
+                 * Address     :
+                 * Count       :
+                 */
+                __u16 transport_count;
+
                 /* port
                  *   The transport layer port number.
                  */
@@ -1486,6 +1500,9 @@ struct sctp_association {
         /* Transport to which SHUTDOWN chunk was last sent.  */
         struct sctp_transport *shutdown_last_sent_to;
 
+        /* Transport to which INIT chunk was last sent.  */
+        struct sctp_transport *init_last_sent_to;
+
         /* Next TSN    : The next TSN number to be assigned to a new
          *             : DATA chunk.  This is sent in the INIT or INIT
          *             : ACK chunk to the peer and incremented each
@@ -1549,8 +1566,11 @@ struct sctp_association {
         /* The message size at which SCTP fragmentation will occur. */
         __u32 frag_point;
 
-        /* Currently only one counter is used to count INIT errors. */
-        int counters[SCTP_NUMBER_COUNTERS];
+        /* Counter used to count INIT errors. */
+        int init_err_counter;
+
+        /* Count the number of INIT cycles (for doubling timeout). */
+        int init_cycle;
 
         /* Default send parameters. */
         __u16 default_stream;
@@ -1650,7 +1670,7 @@ struct sctp_association {
          *  which already resides in sctp_outq.  Please move this
          *  queue and its supporting logic down there.  --piggy]
          */
-        struct sk_buff_head addip_chunks;
+        struct list_head addip_chunk_list;
 
         /* ADDIP Section 4.1 ASCONF Chunk Procedures
          *
@@ -1703,11 +1723,13 @@ static inline struct sctp_association *sctp_assoc(struct sctp_ep_common *base)
 
 struct sctp_association *
 sctp_association_new(const struct sctp_endpoint *, const struct sock *,
-                     sctp_scope_t scope, int gfp);
+                     sctp_scope_t scope, unsigned int __nocast gfp);
 void sctp_association_free(struct sctp_association *);
 void sctp_association_put(struct sctp_association *);
 void sctp_association_hold(struct sctp_association *);
 
+struct sctp_transport *sctp_assoc_choose_init_transport(
+        struct sctp_association *);
 struct sctp_transport *sctp_assoc_choose_shutdown_transport(
         struct sctp_association *);
 void sctp_assoc_update_retran_path(struct sctp_association *);
@@ -1717,9 +1739,12 @@ int sctp_assoc_lookup_laddr(struct sctp_association *asoc,
                             const union sctp_addr *laddr);
 struct sctp_transport *sctp_assoc_add_peer(struct sctp_association *,
                                      const union sctp_addr *address,
-                                     const int gfp);
+                                     const unsigned int __nocast gfp,
+                                     const int peer_state);
 void sctp_assoc_del_peer(struct sctp_association *asoc,
                          const union sctp_addr *addr);
+void sctp_assoc_rm_peer(struct sctp_association *asoc,
+                         struct sctp_transport *peer);
 void sctp_assoc_control_transport(struct sctp_association *,
                                   struct sctp_transport *,
                                   sctp_transport_cmd_t, sctp_sn_error_t);
@@ -1738,9 +1763,11 @@ void sctp_assoc_rwnd_increase(struct sctp_association *, unsigned);
 void sctp_assoc_rwnd_decrease(struct sctp_association *, unsigned);
 void sctp_assoc_set_primary(struct sctp_association *,
                             struct sctp_transport *);
-int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *, int);
+int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *,
+                                     unsigned int __nocast);
 int sctp_assoc_set_bind_addr_from_cookie(struct sctp_association *,
-                                         struct sctp_cookie*, int gfp);
+                                         struct sctp_cookie*,
+                                         unsigned int __nocast gfp);
 
 int sctp_cmp_addr_exact(const union sctp_addr *ss1,
                         const union sctp_addr *ss2);
diff --git a/include/net/sctp/ulpevent.h b/include/net/sctp/ulpevent.h
index 1019d83a580a..90fe4bf6754f 100644
--- a/include/net/sctp/ulpevent.h
+++ b/include/net/sctp/ulpevent.h
@@ -88,7 +88,7 @@ struct sctp_ulpevent *sctp_ulpevent_make_assoc_change(
         __u16 error,
         __u16 outbound,
         __u16 inbound,
-        int gfp);
+        unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_peer_addr_change(
         const struct sctp_association *asoc,
@@ -96,35 +96,35 @@ struct sctp_ulpevent *sctp_ulpevent_make_peer_addr_change(
         int flags,
         int state,
         int error,
-        int gfp);
+        unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_remote_error(
         const struct sctp_association *asoc,
         struct sctp_chunk *chunk,
         __u16 flags,
-        int gfp);
+        unsigned int __nocast gfp);
 struct sctp_ulpevent *sctp_ulpevent_make_send_failed(
         const struct sctp_association *asoc,
         struct sctp_chunk *chunk,
         __u16 flags,
         __u32 error,
-        int gfp);
+        unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_shutdown_event(
         const struct sctp_association *asoc,
         __u16 flags,
-        int gfp);
+        unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_pdapi(
         const struct sctp_association *asoc,
-        __u32 indication, int gfp);
+        __u32 indication, unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_adaption_indication(
-        const struct sctp_association *asoc, int gfp);
+        const struct sctp_association *asoc, unsigned int __nocast gfp);
 
 struct sctp_ulpevent *sctp_ulpevent_make_rcvmsg(struct sctp_association *asoc,
         struct sctp_chunk *chunk,
-        int gfp);
+        unsigned int __nocast gfp);
 
 void sctp_ulpevent_read_sndrcvinfo(const struct sctp_ulpevent *event,
         struct msghdr *);
diff --git a/include/net/sctp/ulpqueue.h b/include/net/sctp/ulpqueue.h
index 961736d29d21..1a60c6d943c1 100644
--- a/include/net/sctp/ulpqueue.h
+++ b/include/net/sctp/ulpqueue.h
@@ -62,19 +62,22 @@ struct sctp_ulpq *sctp_ulpq_init(struct sctp_ulpq *,
 void sctp_ulpq_free(struct sctp_ulpq *);
 
 /* Add a new DATA chunk for processing. */
-int sctp_ulpq_tail_data(struct sctp_ulpq *, struct sctp_chunk *, int);
+int sctp_ulpq_tail_data(struct sctp_ulpq *, struct sctp_chunk *,
+                        unsigned int __nocast);
 
 /* Add a new event for propagation to the ULP. */
 int sctp_ulpq_tail_event(struct sctp_ulpq *, struct sctp_ulpevent *ev);
 
 /* Renege previously received chunks.  */
-void sctp_ulpq_renege(struct sctp_ulpq *, struct sctp_chunk *, int);
+void sctp_ulpq_renege(struct sctp_ulpq *, struct sctp_chunk *,
+                      unsigned int __nocast);
 
 /* Perform partial delivery. */
-void sctp_ulpq_partial_delivery(struct sctp_ulpq *, struct sctp_chunk *, int);
+void sctp_ulpq_partial_delivery(struct sctp_ulpq *, struct sctp_chunk *,
+                                unsigned int __nocast);
 
 /* Abort the partial delivery. */
-void sctp_ulpq_abort_pd(struct sctp_ulpq *, int);
+void sctp_ulpq_abort_pd(struct sctp_ulpq *, unsigned int __nocast);
 
 /* Clear the partial data delivery condition on this socket. */
 int sctp_clear_pd(struct sock *sk);
diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h
index 2758e8ce4f25..f6328aeddcce 100644
--- a/include/net/sctp/user.h
+++ b/include/net/sctp/user.h
@@ -111,6 +111,8 @@ enum sctp_optname {
 #define SCTP_GET_LOCAL_ADDRS_NUM        SCTP_GET_LOCAL_ADDRS_NUM
         SCTP_GET_LOCAL_ADDRS,   /* Get all local addresss. */
 #define SCTP_GET_LOCAL_ADDRS    SCTP_GET_LOCAL_ADDRS
+        SCTP_SOCKOPT_CONNECTX, /* CONNECTX requests. */
+#define SCTP_SOCKOPT_CONNECTX   SCTP_SOCKOPT_CONNECTX
 };
 
 /*
@@ -527,6 +529,7 @@ struct sctp_paddrinfo {
 enum sctp_spinfo_state {
         SCTP_INACTIVE,
         SCTP_ACTIVE,
+        SCTP_UNKNOWN = 0xffff  /* Value used for transport state unknown */
 };
 
 /*
diff --git a/include/net/slhc_vj.h b/include/net/slhc_vj.h
index 0b2c2784f333..8716d5942b65 100644
--- a/include/net/slhc_vj.h
+++ b/include/net/slhc_vj.h
@@ -170,19 +170,14 @@ struct slcompress {
 };
 #define NULLSLCOMPR     (struct slcompress *)0
 
-#define __ARGS(x) x
-
 /* In slhc.c: */
-struct slcompress *slhc_init __ARGS((int rslots, int tslots));
-void slhc_free __ARGS((struct slcompress *comp));
-
-int slhc_compress __ARGS((struct slcompress *comp, unsigned char *icp,
-                          int isize, unsigned char *ocp, unsigned char **cpp,
-                          int compress_cid));
-int slhc_uncompress __ARGS((struct slcompress *comp, unsigned char *icp,
-                            int isize));
-int slhc_remember __ARGS((struct slcompress *comp, unsigned char *icp,
-                          int isize));
-int slhc_toss __ARGS((struct slcompress *comp));
+struct slcompress *slhc_init(int rslots, int tslots);
+void slhc_free(struct slcompress *comp);
+
+int slhc_compress(struct slcompress *comp, unsigned char *icp, int isize,
+                  unsigned char *ocp, unsigned char **cpp, int compress_cid);
+int slhc_uncompress(struct slcompress *comp, unsigned char *icp, int isize);
+int slhc_remember(struct slcompress *comp, unsigned char *icp, int isize);
+int slhc_toss(struct slcompress *comp);
 
 #endif  /* _SLHC_H */
diff --git a/include/net/snmp.h b/include/net/snmp.h
index a15ab256276e..a36bed8ea210 100644
--- a/include/net/snmp.h
+++ b/include/net/snmp.h
@@ -128,18 +128,18 @@ struct linux_mib {
 #define SNMP_STAT_USRPTR(name)  (name[1])
 
 #define SNMP_INC_STATS_BH(mib, field)   \
-        (per_cpu_ptr(mib[0], _smp_processor_id())->mibs[field]++)
+        (per_cpu_ptr(mib[0], raw_smp_processor_id())->mibs[field]++)
 #define SNMP_INC_STATS_OFFSET_BH(mib, field, offset)    \
-        (per_cpu_ptr(mib[0], _smp_processor_id())->mibs[field + (offset)]++)
+        (per_cpu_ptr(mib[0], raw_smp_processor_id())->mibs[field + (offset)]++)
 #define SNMP_INC_STATS_USER(mib, field) \
-        (per_cpu_ptr(mib[1], _smp_processor_id())->mibs[field]++)
+        (per_cpu_ptr(mib[1], raw_smp_processor_id())->mibs[field]++)
 #define SNMP_INC_STATS(mib, field)      \
-        (per_cpu_ptr(mib[!in_softirq()], _smp_processor_id())->mibs[field]++)
+        (per_cpu_ptr(mib[!in_softirq()], raw_smp_processor_id())->mibs[field]++)
 #define SNMP_DEC_STATS(mib, field)      \
-        (per_cpu_ptr(mib[!in_softirq()], _smp_processor_id())->mibs[field]--)
+        (per_cpu_ptr(mib[!in_softirq()], raw_smp_processor_id())->mibs[field]--)
 #define SNMP_ADD_STATS_BH(mib, field, addend)   \
-        (per_cpu_ptr(mib[0], _smp_processor_id())->mibs[field] += addend)
+        (per_cpu_ptr(mib[0], raw_smp_processor_id())->mibs[field] += addend)
 #define SNMP_ADD_STATS_USER(mib, field, addend)         \
-        (per_cpu_ptr(mib[1], _smp_processor_id())->mibs[field] += addend)
+        (per_cpu_ptr(mib[1], raw_smp_processor_id())->mibs[field] += addend)
 
 #endif
diff --git a/include/net/sock.h b/include/net/sock.h
index a9ef3a6a13f3..8c48fbecb7cf 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -88,6 +88,7 @@ do {	spin_lock_init(&((__sk)->sk_lock.slock)); \
 } while(0)
 
 struct sock;
+struct proto;
 
 /**
  *      struct sock_common - minimal network layer representation of sockets
@@ -98,10 +99,11 @@ struct sock;
  *      @skc_node: main hash linkage for various protocol lookup tables
  *      @skc_bind_node: bind hash linkage for various protocol lookup tables
  *      @skc_refcnt: reference count
+ *      @skc_prot: protocol handlers inside a network family
  *
  *      This is the minimal network layer representation of sockets, the header
- *      for struct sock and struct tcp_tw_bucket.
-  */
+ *      for struct sock and struct inet_timewait_sock.
+ */
 struct sock_common {
         unsigned short          skc_family;
         volatile unsigned char  skc_state;
@@ -110,11 +112,12 @@ struct sock_common {
         struct hlist_node       skc_node;
         struct hlist_node       skc_bind_node;
         atomic_t                skc_refcnt;
+        struct proto            *skc_prot;
 };
 
 /**
   *     struct sock - network layer representation of sockets
-  *     @__sk_common: shared layout with tcp_tw_bucket
+  *     @__sk_common: shared layout with inet_timewait_sock
   *     @sk_shutdown: mask of %SEND_SHUTDOWN and/or %RCV_SHUTDOWN
   *     @sk_userlocks: %SO_SNDBUF and %SO_RCVBUF settings
   *     @sk_lock:       synchronizer
@@ -136,11 +139,10 @@ struct sock_common {
   *     @sk_no_check: %SO_NO_CHECK setting, wether or not checkup packets
   *     @sk_route_caps: route capabilities (e.g. %NETIF_F_TSO)
   *     @sk_lingertime: %SO_LINGER l_linger setting
-  *     @sk_hashent: hash entry in several tables (e.g. tcp_ehash)
+  *     @sk_hashent: hash entry in several tables (e.g. inet_hashinfo.ehash)
   *     @sk_backlog: always used with the per-socket spinlock held
   *     @sk_callback_lock: used with the callbacks in the end of this struct
   *     @sk_error_queue: rarely used
-  *     @sk_prot: protocol handlers inside a network family
   *     @sk_prot_creator: sk_prot of original sock creator (see ipv6_setsockopt, IPV6_ADDRFORM for instance)
   *     @sk_err: last error
   *     @sk_err_soft: errors that don't cause failure but are the cause of a persistent failure not just 'timed out'
@@ -173,7 +175,7 @@ struct sock_common {
  */
 struct sock {
         /*
-         * Now struct tcp_tw_bucket also uses sock_common, so please just
+         * Now struct inet_timewait_sock also uses sock_common, so please just
          * don't add nothing before this first member (__sk_common) --acme
          */
         struct sock_common      __sk_common;
@@ -184,6 +186,7 @@ struct sock {
 #define sk_node                 __sk_common.skc_node
 #define sk_bind_node            __sk_common.skc_bind_node
 #define sk_refcnt               __sk_common.skc_refcnt
+#define sk_prot                 __sk_common.skc_prot
         unsigned char           sk_shutdown : 2,
                                 sk_no_check : 2,
                                 sk_userlocks : 4;
@@ -218,7 +221,6 @@ struct sock {
                 struct sk_buff *tail;
         } sk_backlog;
         struct sk_buff_head     sk_error_queue;
-        struct proto            *sk_prot;
         struct proto            *sk_prot_creator;
         rwlock_t                sk_callback_lock;
         int                     sk_err,
@@ -253,28 +255,28 @@ struct sock {
 /*
  * Hashed lists helper routines
  */
-static inline struct sock *__sk_head(struct hlist_head *head)
+static inline struct sock *__sk_head(const struct hlist_head *head)
 {
         return hlist_entry(head->first, struct sock, sk_node);
 }
 
-static inline struct sock *sk_head(struct hlist_head *head)
+static inline struct sock *sk_head(const struct hlist_head *head)
 {
         return hlist_empty(head) ? NULL : __sk_head(head);
 }
 
-static inline struct sock *sk_next(struct sock *sk)
+static inline struct sock *sk_next(const struct sock *sk)
 {
         return sk->sk_node.next ?
                 hlist_entry(sk->sk_node.next, struct sock, sk_node) : NULL;
 }
 
-static inline int sk_unhashed(struct sock *sk)
+static inline int sk_unhashed(const struct sock *sk)
 {
         return hlist_unhashed(&sk->sk_node);
 }
 
-static inline int sk_hashed(struct sock *sk)
+static inline int sk_hashed(const struct sock *sk)
 {
         return sk->sk_node.pprev != NULL;
 }
@@ -384,6 +386,11 @@ enum sock_flags {
         SOCK_QUEUE_SHRUNK, /* write queue has been shrunk recently */
 };
 
+static inline void sock_copy_flags(struct sock *nsk, struct sock *osk)
+{
+        nsk->sk_flags = osk->sk_flags;
+}
+
 static inline void sock_set_flag(struct sock *sk, enum sock_flags flag)
 {
         __set_bit(flag, &sk->sk_flags);
@@ -484,6 +491,8 @@ extern void sk_stream_kill_queues(struct sock *sk);
 
 extern int sk_wait_data(struct sock *sk, long *timeo);
 
+struct request_sock_ops;
+
 /* Networking protocol blocks we attach to sockets.
  * socket layer -> transport layer interface
  * transport -> network interface is defined by struct inet_proto
@@ -547,12 +556,20 @@ struct proto {
         kmem_cache_t            *slab;
         unsigned int            obj_size;
 
+        kmem_cache_t            *twsk_slab;
+        unsigned int            twsk_obj_size;
+        atomic_t                *orphan_count;
+
+        struct request_sock_ops *rsk_prot;
+
         struct module           *owner;
 
         char                    name[32];
 
         struct list_head        node;
-
+#ifdef SOCK_REFCNT_DEBUG
+        atomic_t                socks;
+#endif
         struct {
                 int inuse;
                 u8  __pad[SMP_CACHE_BYTES - sizeof(int)];
@@ -562,6 +579,31 @@ struct proto {
 extern int proto_register(struct proto *prot, int alloc_slab);
 extern void proto_unregister(struct proto *prot);
 
+#ifdef SOCK_REFCNT_DEBUG
+static inline void sk_refcnt_debug_inc(struct sock *sk)
+{
+        atomic_inc(&sk->sk_prot->socks);
+}
+
+static inline void sk_refcnt_debug_dec(struct sock *sk)
+{
+        atomic_dec(&sk->sk_prot->socks);
+        printk(KERN_DEBUG "%s socket %p released, %d are still alive\n",
+               sk->sk_prot->name, sk, atomic_read(&sk->sk_prot->socks));
+}
+
+static inline void sk_refcnt_debug_release(const struct sock *sk)
+{
+        if (atomic_read(&sk->sk_refcnt) != 1)
+                printk(KERN_DEBUG "Destruction of the %s socket %p delayed, refcnt=%d\n",
+                       sk->sk_prot->name, sk, atomic_read(&sk->sk_refcnt));
+}
+#else /* SOCK_REFCNT_DEBUG */
+#define sk_refcnt_debug_inc(sk) do { } while (0)
+#define sk_refcnt_debug_dec(sk) do { } while (0)
+#define sk_refcnt_debug_release(sk) do { } while (0)
+#endif /* SOCK_REFCNT_DEBUG */
+
 /* Called with local bh disabled */
 static __inline__ void sock_prot_inc_use(struct proto *prot)
 {
@@ -573,6 +615,15 @@ static __inline__ void sock_prot_dec_use(struct proto *prot)
         prot->stats[smp_processor_id()].inuse--;
 }
 
+/* With per-bucket locks this operation is not-atomic, so that
+ * this version is not worse.
+ */
+static inline void __sk_prot_rehash(struct sock *sk)
+{
+        sk->sk_prot->unhash(sk);
+        sk->sk_prot->hash(sk);
+}
+
 /* About 10 seconds */
 #define SOCK_DESTROY_TIME (10*HZ)
 
@@ -658,6 +709,12 @@ static inline int sk_stream_rmem_schedule(struct sock *sk, struct sk_buff *skb)
                 sk_stream_mem_schedule(sk, skb->truesize, 1);
 }
 
+static inline int sk_stream_wmem_schedule(struct sock *sk, int size)
+{
+        return size <= sk->sk_forward_alloc ||
+               sk_stream_mem_schedule(sk, size, 0);
+}
+
 /* Used by processes to "lock" a socket state, so that
  * interrupts and bottom half handlers won't change it
  * from under us. It essentially blocks any incoming
@@ -680,16 +737,19 @@ extern void FASTCALL(release_sock(struct sock *sk));
 #define bh_lock_sock(__sk)      spin_lock(&((__sk)->sk_lock.slock))
 #define bh_unlock_sock(__sk)    spin_unlock(&((__sk)->sk_lock.slock))
 
-extern struct sock              *sk_alloc(int family, int priority,
+extern struct sock              *sk_alloc(int family,
+                                          unsigned int __nocast priority,
                                           struct proto *prot, int zero_it);
 extern void                     sk_free(struct sock *sk);
+extern struct sock              *sk_clone(const struct sock *sk,
+                                          const unsigned int __nocast priority);
 
 extern struct sk_buff           *sock_wmalloc(struct sock *sk,
                                               unsigned long size, int force,
-                                              int priority);
+                                              unsigned int __nocast priority);
 extern struct sk_buff           *sock_rmalloc(struct sock *sk,
                                               unsigned long size, int force,
-                                              int priority);
+                                              unsigned int __nocast priority);
 extern void                     sock_wfree(struct sk_buff *skb);
 extern void                     sock_rfree(struct sk_buff *skb);
 
@@ -704,7 +764,8 @@ extern struct sk_buff 		*sock_alloc_send_skb(struct sock *sk,
                                                      unsigned long size,
                                                      int noblock,
                                                      int *errcode);
-extern void *sock_kmalloc(struct sock *sk, int size, int priority);
+extern void *sock_kmalloc(struct sock *sk, int size,
+                          unsigned int __nocast priority);
 extern void sock_kfree_s(struct sock *sk, void *mem, int size);
 extern void sk_send_sigurg(struct sock *sk);
 
@@ -975,6 +1036,16 @@ sk_dst_check(struct sock *sk, u32 cookie)
         return dst;
 }
 
+static inline void sk_setup_caps(struct sock *sk, struct dst_entry *dst)
+{
+        __sk_dst_set(sk, dst);
+        sk->sk_route_caps = dst->dev->features;
+        if (sk->sk_route_caps & NETIF_F_TSO) {
+                if (sock_flag(sk, SOCK_NO_LARGESEND) || dst->header_len)
+                        sk->sk_route_caps &= ~NETIF_F_TSO;
+        }
+}
+
 static inline void sk_charge_skb(struct sock *sk, struct sk_buff *skb)
 {
         sk->sk_wmem_queued   += skb->truesize;
@@ -1128,15 +1199,18 @@ static inline void sk_stream_moderate_sndbuf(struct sock *sk)
 }
 
 static inline struct sk_buff *sk_stream_alloc_pskb(struct sock *sk,
-                                                   int size, int mem, int gfp)
+                                                   int size, int mem,
+                                                   unsigned int __nocast gfp)
 {
-        struct sk_buff *skb = alloc_skb(size + sk->sk_prot->max_header, gfp);
+        struct sk_buff *skb;
+        int hdr_len;
 
+        hdr_len = SKB_DATA_ALIGN(sk->sk_prot->max_header);
+        skb = alloc_skb_fclone(size + hdr_len, gfp);
         if (skb) {
                 skb->truesize += mem;
-                if (sk->sk_forward_alloc >= (int)skb->truesize ||
-                    sk_stream_mem_schedule(sk, skb->truesize, 0)) {
-                        skb_reserve(skb, sk->sk_prot->max_header);
+                if (sk_stream_wmem_schedule(sk, skb->truesize)) {
+                        skb_reserve(skb, hdr_len);
                         return skb;
                 }
                 __kfree_skb(skb);
@@ -1148,7 +1222,8 @@ static inline struct sk_buff *sk_stream_alloc_pskb(struct sock *sk,
 }
 
 static inline struct sk_buff *sk_stream_alloc_skb(struct sock *sk,
-                                                  int size, int gfp)
+                                                  int size,
+                                                  unsigned int __nocast gfp)
 {
         return sk_stream_alloc_pskb(sk, size, 0, gfp);
 }
@@ -1157,10 +1232,8 @@ static inline struct page *sk_stream_alloc_page(struct sock *sk)
 {
         struct page *page = NULL;
 
-        if (sk->sk_forward_alloc >= (int)PAGE_SIZE ||
-            sk_stream_mem_schedule(sk, PAGE_SIZE, 0))
-                page = alloc_pages(sk->sk_allocation, 0);
-        else {
+        page = alloc_pages(sk->sk_allocation, 0);
+        if (!page) {
                 sk->sk_prot->enter_memory_pressure();
                 sk_stream_moderate_sndbuf(sk);
         }
@@ -1181,7 +1254,7 @@ static inline int sock_writeable(const struct sock *sk)
         return atomic_read(&sk->sk_wmem_alloc) < (sk->sk_sndbuf / 2);
 }
 
-static inline int gfp_any(void)
+static inline unsigned int __nocast gfp_any(void)
 {
         return in_softirq() ? GFP_ATOMIC : GFP_KERNEL;
 }
@@ -1212,16 +1285,19 @@ static inline int sock_intr_errno(long timeo)
 static __inline__ void
 sock_recv_timestamp(struct msghdr *msg, struct sock *sk, struct sk_buff *skb)
 {
-        struct timeval *stamp = &skb->stamp;
+        struct timeval stamp;
+
+        skb_get_timestamp(skb, &stamp);
         if (sock_flag(sk, SOCK_RCVTSTAMP)) {
                 /* Race occurred between timestamp enabling and packet
                    receiving.  Fill in the current time for now. */
-                if (stamp->tv_sec == 0)
-                        do_gettimeofday(stamp);
+                if (stamp.tv_sec == 0)
+                        do_gettimeofday(&stamp);
+                skb_set_timestamp(skb, &stamp);
                 put_cmsg(msg, SOL_SOCKET, SO_TIMESTAMP, sizeof(struct timeval),
-                         stamp);
+                         &stamp);
         } else
-                sk->sk_stamp = *stamp;
+                sk->sk_stamp = stamp;
 }
 
 /**
@@ -1246,11 +1322,11 @@ extern int sock_get_timestamp(struct sock *, struct timeval __user *);
  */
 
 #if 0
-#define NETDEBUG(x)     do { } while (0)
-#define LIMIT_NETDEBUG(x) do {} while(0)
+#define NETDEBUG(fmt, args...)  do { } while (0)
+#define LIMIT_NETDEBUG(fmt, args...) do { } while(0)
 #else
-#define NETDEBUG(x)     do { x; } while (0)
-#define LIMIT_NETDEBUG(x) do { if (net_ratelimit()) { x; } } while(0)
+#define NETDEBUG(fmt, args...)  printk(fmt,##args)
+#define LIMIT_NETDEBUG(fmt, args...) do { if (net_ratelimit()) printk(fmt,##args); } while(0)
 #endif
 
 /*
@@ -1297,4 +1373,15 @@ static inline int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsign
 }
 #endif
 
+extern void sk_init(void);
+
+#ifdef CONFIG_SYSCTL
+extern struct ctl_table core_table[];
+#endif
+
+extern int sysctl_optmem_max;
+
+extern __u32 sysctl_wmem_default;
+extern __u32 sysctl_rmem_default;
+
 #endif  /* _SOCK_H */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index e71f8ba3e101..97af77c4d096 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -21,359 +21,29 @@
 #define TCP_DEBUG 1
 #define FASTRETRANS_DEBUG 1
 
-/* Cancel timers, when they are not required. */
-#undef TCP_CLEAR_TIMERS
-
 #include <linux/config.h>
 #include <linux/list.h>
 #include <linux/tcp.h>
 #include <linux/slab.h>
 #include <linux/cache.h>
 #include <linux/percpu.h>
+
+#include <net/inet_connection_sock.h>
+#include <net/inet_timewait_sock.h>
+#include <net/inet_hashtables.h>
 #include <net/checksum.h>
+#include <net/request_sock.h>
 #include <net/sock.h>
 #include <net/snmp.h>
 #include <net/ip.h>
-#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE)
-#include <linux/ipv6.h>
-#endif
-#include <linux/seq_file.h>
-
-/* This is for all connections with a full identity, no wildcards.
- * New scheme, half the table is for TIME_WAIT, the other half is
- * for the rest.  I'll experiment with dynamic table growth later.
- */
-struct tcp_ehash_bucket {
-        rwlock_t          lock;
-        struct hlist_head chain;
-} __attribute__((__aligned__(8)));
-
-/* This is for listening sockets, thus all sockets which possess wildcards. */
-#define TCP_LHTABLE_SIZE        32      /* Yes, really, this is all you need. */
-
-/* There are a few simple rules, which allow for local port reuse by
- * an application.  In essence:
- *
- *      1) Sockets bound to different interfaces may share a local port.
- *         Failing that, goto test 2.
- *      2) If all sockets have sk->sk_reuse set, and none of them are in
- *         TCP_LISTEN state, the port may be shared.
- *         Failing that, goto test 3.
- *      3) If all sockets are bound to a specific inet_sk(sk)->rcv_saddr local
- *         address, and none of them are the same, the port may be
- *         shared.
- *         Failing this, the port cannot be shared.
- *
- * The interesting point, is test #2.  This is what an FTP server does
- * all day.  To optimize this case we use a specific flag bit defined
- * below.  As we add sockets to a bind bucket list, we perform a
- * check of: (newsk->sk_reuse && (newsk->sk_state != TCP_LISTEN))
- * As long as all sockets added to a bind bucket pass this test,
- * the flag bit will be set.
- * The resulting situation is that tcp_v[46]_verify_bind() can just check
- * for this flag bit, if it is set and the socket trying to bind has
- * sk->sk_reuse set, we don't even have to walk the owners list at all,
- * we return that it is ok to bind this socket to the requested local port.
- *
- * Sounds like a lot of work, but it is worth it.  In a more naive
- * implementation (ie. current FreeBSD etc.) the entire list of ports
- * must be walked for each data port opened by an ftp server.  Needless
- * to say, this does not scale at all.  With a couple thousand FTP
- * users logged onto your box, isn't it nice to know that new data
- * ports are created in O(1) time?  I thought so. ;-)   -DaveM
- */
-struct tcp_bind_bucket {
-        unsigned short          port;
-        signed short            fastreuse;
-        struct hlist_node       node;
-        struct hlist_head       owners;
-};
-
-#define tb_for_each(tb, node, head) hlist_for_each_entry(tb, node, head, node)
-
-struct tcp_bind_hashbucket {
-        spinlock_t              lock;
-        struct hlist_head       chain;
-};
-
-static inline struct tcp_bind_bucket *__tb_head(struct tcp_bind_hashbucket *head)
-{
-        return hlist_entry(head->chain.first, struct tcp_bind_bucket, node);
-}
-
-static inline struct tcp_bind_bucket *tb_head(struct tcp_bind_hashbucket *head)
-{
-        return hlist_empty(&head->chain) ? NULL : __tb_head(head);
-}
-
-extern struct tcp_hashinfo {
-        /* This is for sockets with full identity only.  Sockets here will
-         * always be without wildcards and will have the following invariant:
-         *
-         *          TCP_ESTABLISHED <= sk->sk_state < TCP_CLOSE
-         *
-         * First half of the table is for sockets not in TIME_WAIT, second half
-         * is for TIME_WAIT sockets only.
-         */
-        struct tcp_ehash_bucket *__tcp_ehash;
-
-        /* Ok, let's try this, I give up, we do need a local binding
-         * TCP hash as well as the others for fast bind/connect.
-         */
-        struct tcp_bind_hashbucket *__tcp_bhash;
-
-        int __tcp_bhash_size;
-        int __tcp_ehash_size;
-
-        /* All sockets in TCP_LISTEN state will be in here.  This is the only
-         * table where wildcard'd TCP sockets can exist.  Hash function here
-         * is just local port number.
-         */
-        struct hlist_head __tcp_listening_hash[TCP_LHTABLE_SIZE];
-
-        /* All the above members are written once at bootup and
-         * never written again _or_ are predominantly read-access.
-         *
-         * Now align to a new cache line as all the following members
-         * are often dirty.
-         */
-        rwlock_t __tcp_lhash_lock ____cacheline_aligned;
-        atomic_t __tcp_lhash_users;
-        wait_queue_head_t __tcp_lhash_wait;
-        spinlock_t __tcp_portalloc_lock;
-} tcp_hashinfo;
-
-#define tcp_ehash       (tcp_hashinfo.__tcp_ehash)
-#define tcp_bhash       (tcp_hashinfo.__tcp_bhash)
-#define tcp_ehash_size  (tcp_hashinfo.__tcp_ehash_size)
-#define tcp_bhash_size  (tcp_hashinfo.__tcp_bhash_size)
-#define tcp_listening_hash (tcp_hashinfo.__tcp_listening_hash)
-#define tcp_lhash_lock  (tcp_hashinfo.__tcp_lhash_lock)
-#define tcp_lhash_users (tcp_hashinfo.__tcp_lhash_users)
-#define tcp_lhash_wait  (tcp_hashinfo.__tcp_lhash_wait)
-#define tcp_portalloc_lock (tcp_hashinfo.__tcp_portalloc_lock)
-
-extern kmem_cache_t *tcp_bucket_cachep;
-extern struct tcp_bind_bucket *tcp_bucket_create(struct tcp_bind_hashbucket *head,
-                                                 unsigned short snum);
-extern void tcp_bucket_destroy(struct tcp_bind_bucket *tb);
-extern void tcp_bucket_unlock(struct sock *sk);
-extern int tcp_port_rover;
-
-/* These are AF independent. */
-static __inline__ int tcp_bhashfn(__u16 lport)
-{
-        return (lport & (tcp_bhash_size - 1));
-}
-
-extern void tcp_bind_hash(struct sock *sk, struct tcp_bind_bucket *tb,
-                          unsigned short snum);
-
-#if (BITS_PER_LONG == 64)
-#define TCP_ADDRCMP_ALIGN_BYTES 8
-#else
-#define TCP_ADDRCMP_ALIGN_BYTES 4
-#endif
-
-/* This is a TIME_WAIT bucket.  It works around the memory consumption
- * problems of sockets in such a state on heavily loaded servers, but
- * without violating the protocol specification.
- */
-struct tcp_tw_bucket {
-        /*
-         * Now struct sock also uses sock_common, so please just
-         * don't add nothing before this first member (__tw_common) --acme
-         */
-        struct sock_common      __tw_common;
-#define tw_family               __tw_common.skc_family
-#define tw_state                __tw_common.skc_state
-#define tw_reuse                __tw_common.skc_reuse
-#define tw_bound_dev_if         __tw_common.skc_bound_dev_if
-#define tw_node                 __tw_common.skc_node
-#define tw_bind_node            __tw_common.skc_bind_node
-#define tw_refcnt               __tw_common.skc_refcnt
-        volatile unsigned char  tw_substate;
-        unsigned char           tw_rcv_wscale;
-        __u16                   tw_sport;
-        /* Socket demultiplex comparisons on incoming packets. */
-        /* these five are in inet_sock */
-        __u32                   tw_daddr
-                __attribute__((aligned(TCP_ADDRCMP_ALIGN_BYTES)));
-        __u32                   tw_rcv_saddr;
-        __u16                   tw_dport;
-        __u16                   tw_num;
-        /* And these are ours. */
-        int                     tw_hashent;
-        int                     tw_timeout;
-        __u32                   tw_rcv_nxt;
-        __u32                   tw_snd_nxt;
-        __u32                   tw_rcv_wnd;
-        __u32                   tw_ts_recent;
-        long                    tw_ts_recent_stamp;
-        unsigned long           tw_ttd;
-        struct tcp_bind_bucket  *tw_tb;
-        struct hlist_node       tw_death_node;
-#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-        struct in6_addr         tw_v6_daddr;
-        struct in6_addr         tw_v6_rcv_saddr;
-        int                     tw_v6_ipv6only;
-#endif
-};
+#include <net/tcp_states.h>
 
-static __inline__ void tw_add_node(struct tcp_tw_bucket *tw,
-                                   struct hlist_head *list)
-{
-        hlist_add_head(&tw->tw_node, list);
-}
-
-static __inline__ void tw_add_bind_node(struct tcp_tw_bucket *tw,
-                                        struct hlist_head *list)
-{
-        hlist_add_head(&tw->tw_bind_node, list);
-}
-
-static inline int tw_dead_hashed(struct tcp_tw_bucket *tw)
-{
-        return tw->tw_death_node.pprev != NULL;
-}
-
-static __inline__ void tw_dead_node_init(struct tcp_tw_bucket *tw)
-{
-        tw->tw_death_node.pprev = NULL;
-}
-
-static __inline__ void __tw_del_dead_node(struct tcp_tw_bucket *tw)
-{
-        __hlist_del(&tw->tw_death_node);
-        tw_dead_node_init(tw);
-}
-
-static __inline__ int tw_del_dead_node(struct tcp_tw_bucket *tw)
-{
-        if (tw_dead_hashed(tw)) {
-                __tw_del_dead_node(tw);
-                return 1;
-        }
-        return 0;
-}
-
-#define tw_for_each(tw, node, head) \
-        hlist_for_each_entry(tw, node, head, tw_node)
-
-#define tw_for_each_inmate(tw, node, jail) \
-        hlist_for_each_entry(tw, node, jail, tw_death_node)
-
-#define tw_for_each_inmate_safe(tw, node, safe, jail) \
-        hlist_for_each_entry_safe(tw, node, safe, jail, tw_death_node)
-
-#define tcptw_sk(__sk)  ((struct tcp_tw_bucket *)(__sk))
-
-static inline u32 tcp_v4_rcv_saddr(const struct sock *sk)
-{
-        return likely(sk->sk_state != TCP_TIME_WAIT) ?
-                inet_sk(sk)->rcv_saddr : tcptw_sk(sk)->tw_rcv_saddr;
-}
-
-#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-static inline struct in6_addr *__tcp_v6_rcv_saddr(const struct sock *sk)
-{
-        return likely(sk->sk_state != TCP_TIME_WAIT) ?
-                &inet6_sk(sk)->rcv_saddr : &tcptw_sk(sk)->tw_v6_rcv_saddr;
-}
-
-static inline struct in6_addr *tcp_v6_rcv_saddr(const struct sock *sk)
-{
-        return sk->sk_family == AF_INET6 ? __tcp_v6_rcv_saddr(sk) : NULL;
-}
-
-#define tcptw_sk_ipv6only(__sk) (tcptw_sk(__sk)->tw_v6_ipv6only)
-
-static inline int tcp_v6_ipv6only(const struct sock *sk)
-{
-        return likely(sk->sk_state != TCP_TIME_WAIT) ?
-                ipv6_only_sock(sk) : tcptw_sk_ipv6only(sk);
-}
-#else
-# define __tcp_v6_rcv_saddr(__sk)       NULL
-# define tcp_v6_rcv_saddr(__sk)         NULL
-# define tcptw_sk_ipv6only(__sk)        0
-# define tcp_v6_ipv6only(__sk)          0
-#endif
+#include <linux/seq_file.h>
 
-extern kmem_cache_t *tcp_timewait_cachep;
-
-static inline void tcp_tw_put(struct tcp_tw_bucket *tw)
-{
-        if (atomic_dec_and_test(&tw->tw_refcnt)) {
-#ifdef INET_REFCNT_DEBUG
-                printk(KERN_DEBUG "tw_bucket %p released\n", tw);
-#endif
-                kmem_cache_free(tcp_timewait_cachep, tw);
-        }
-}
+extern struct inet_hashinfo tcp_hashinfo;
 
 extern atomic_t tcp_orphan_count;
-extern int tcp_tw_count;
 extern void tcp_time_wait(struct sock *sk, int state, int timeo);
-extern void tcp_tw_deschedule(struct tcp_tw_bucket *tw);
-
-
-/* Socket demux engine toys. */
-#ifdef __BIG_ENDIAN
-#define TCP_COMBINED_PORTS(__sport, __dport) \
-        (((__u32)(__sport)<<16) | (__u32)(__dport))
-#else /* __LITTLE_ENDIAN */
-#define TCP_COMBINED_PORTS(__sport, __dport) \
-        (((__u32)(__dport)<<16) | (__u32)(__sport))
-#endif
-
-#if (BITS_PER_LONG == 64)
-#ifdef __BIG_ENDIAN
-#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr) \
-        __u64 __name = (((__u64)(__saddr))<<32)|((__u64)(__daddr));
-#else /* __LITTLE_ENDIAN */
-#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr) \
-        __u64 __name = (((__u64)(__daddr))<<32)|((__u64)(__saddr));
-#endif /* __BIG_ENDIAN */
-#define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-        (((*((__u64 *)&(inet_sk(__sk)->daddr)))== (__cookie))   &&      \
-         ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))    &&      \
-         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
-#define TCP_IPV4_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-        (((*((__u64 *)&(tcptw_sk(__sk)->tw_daddr))) == (__cookie)) &&   \
-         ((*((__u32 *)&(tcptw_sk(__sk)->tw_dport))) == (__ports)) &&    \
-         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
-#else /* 32-bit arch */
-#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr)
-#define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-        ((inet_sk(__sk)->daddr                  == (__saddr))   &&      \
-         (inet_sk(__sk)->rcv_saddr              == (__daddr))   &&      \
-         ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))    &&      \
-         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
-#define TCP_IPV4_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-        ((tcptw_sk(__sk)->tw_daddr              == (__saddr))   &&      \
-         (tcptw_sk(__sk)->tw_rcv_saddr          == (__daddr))   &&      \
-         ((*((__u32 *)&(tcptw_sk(__sk)->tw_dport))) == (__ports)) &&    \
-         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
-#endif /* 64-bit arch */
-
-#define TCP_IPV6_MATCH(__sk, __saddr, __daddr, __ports, __dif)     \
-        (((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))    && \
-         ((__sk)->sk_family             == AF_INET6)            && \
-         ipv6_addr_equal(&inet6_sk(__sk)->daddr, (__saddr))     && \
-         ipv6_addr_equal(&inet6_sk(__sk)->rcv_saddr, (__daddr)) && \
-         (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
-
-/* These can have wildcards, don't try too hard. */
-static __inline__ int tcp_lhashfn(unsigned short num)
-{
-        return num & (TCP_LHTABLE_SIZE - 1);
-}
-
-static __inline__ int tcp_sk_listen_hashfn(struct sock *sk)
-{
-        return tcp_lhashfn(inet_sk(sk)->num);
-}
 
 #define MAX_TCP_HEADER  (128 + MAX_HEADER)
 
@@ -477,52 +147,6 @@ static __inline__ int tcp_sk_listen_hashfn(struct sock *sk)
                                          * timestamps. It must be less than
                                          * minimal timewait lifetime.
                                          */
-
-#define TCP_TW_RECYCLE_SLOTS_LOG        5
-#define TCP_TW_RECYCLE_SLOTS            (1<<TCP_TW_RECYCLE_SLOTS_LOG)
-
-/* If time > 4sec, it is "slow" path, no recycling is required,
-   so that we select tick to get range about 4 seconds.
- */
-
-#if HZ <= 16 || HZ > 4096
-# error Unsupported: HZ <= 16 or HZ > 4096
-#elif HZ <= 32
-# define TCP_TW_RECYCLE_TICK (5+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 64
-# define TCP_TW_RECYCLE_TICK (6+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 128
-# define TCP_TW_RECYCLE_TICK (7+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 256
-# define TCP_TW_RECYCLE_TICK (8+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 512
-# define TCP_TW_RECYCLE_TICK (9+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 1024
-# define TCP_TW_RECYCLE_TICK (10+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#elif HZ <= 2048
-# define TCP_TW_RECYCLE_TICK (11+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#else
-# define TCP_TW_RECYCLE_TICK (12+2-TCP_TW_RECYCLE_SLOTS_LOG)
-#endif
-
-#define BICTCP_BETA_SCALE    1024       /* Scale factor beta calculation
-                                         * max_cwnd = snd_cwnd * beta
-                                         */
-#define BICTCP_MAX_INCREMENT 32         /*
-                                         * Limit on the amount of
-                                         * increment allowed during
-                                         * binary search.
-                                         */
-#define BICTCP_FUNC_OF_MIN_INCR 11      /*
-                                         * log(B/Smin)/log(B/(B-1))+1,
-                                         * Smin:min increment
-                                         * B:log factor
-                                         */
-#define BICTCP_B                4        /*
-                                          * In binary search,
-                                          * go to point (max+min)/N
-                                          */
-
 /*
  *      TCP option
  */
@@ -552,23 +176,18 @@ static __inline__ int tcp_sk_listen_hashfn(struct sock *sk)
 #define TCPOLEN_SACK_BASE_ALIGNED       4
 #define TCPOLEN_SACK_PERBLOCK           8
 
-#define TCP_TIME_RETRANS        1       /* Retransmit timer */
-#define TCP_TIME_DACK           2       /* Delayed ack timer */
-#define TCP_TIME_PROBE0         3       /* Zero window probe timer */
-#define TCP_TIME_KEEPOPEN       4       /* Keepalive timer */
-
 /* Flags in tp->nonagle */
 #define TCP_NAGLE_OFF           1       /* Nagle's algo is disabled */
 #define TCP_NAGLE_CORK          2       /* Socket is corked         */
 #define TCP_NAGLE_PUSH          4       /* Cork is overriden for already queued data */
 
+extern struct inet_timewait_death_row tcp_death_row;
+
 /* sysctl variables for tcp */
-extern int sysctl_max_syn_backlog;
 extern int sysctl_tcp_timestamps;
 extern int sysctl_tcp_window_scaling;
 extern int sysctl_tcp_sack;
 extern int sysctl_tcp_fin_timeout;
-extern int sysctl_tcp_tw_recycle;
 extern int sysctl_tcp_keepalive_time;
 extern int sysctl_tcp_keepalive_probes;
 extern int sysctl_tcp_keepalive_intvl;
@@ -583,7 +202,6 @@ extern int sysctl_tcp_stdurg;
 extern int sysctl_tcp_rfc1337;
 extern int sysctl_tcp_abort_on_overflow;
 extern int sysctl_tcp_max_orphans;
-extern int sysctl_tcp_max_tw_buckets;
 extern int sysctl_tcp_fack;
 extern int sysctl_tcp_reordering;
 extern int sysctl_tcp_ecn;
@@ -596,16 +214,7 @@ extern int sysctl_tcp_adv_win_scale;
 extern int sysctl_tcp_tw_reuse;
 extern int sysctl_tcp_frto;
 extern int sysctl_tcp_low_latency;
-extern int sysctl_tcp_westwood;
-extern int sysctl_tcp_vegas_cong_avoid;
-extern int sysctl_tcp_vegas_alpha;
-extern int sysctl_tcp_vegas_beta;
-extern int sysctl_tcp_vegas_gamma;
 extern int sysctl_tcp_nometrics_save;
-extern int sysctl_tcp_bic;
-extern int sysctl_tcp_bic_fast_convergence;
-extern int sysctl_tcp_bic_low_window;
-extern int sysctl_tcp_bic_beta;
 extern int sysctl_tcp_moderate_rcvbuf;
 extern int sysctl_tcp_tso_win_divisor;
 
@@ -613,80 +222,6 @@ extern atomic_t tcp_memory_allocated;
 extern atomic_t tcp_sockets_allocated;
 extern int tcp_memory_pressure;
 
-struct open_request;
-
-struct or_calltable {
-        int  family;
-        int  (*rtx_syn_ack)     (struct sock *sk, struct open_request *req, struct dst_entry*);
-        void (*send_ack)        (struct sk_buff *skb, struct open_request *req);
-        void (*destructor)      (struct open_request *req);
-        void (*send_reset)      (struct sk_buff *skb);
-};
-
-struct tcp_v4_open_req {
-        __u32                   loc_addr;
-        __u32                   rmt_addr;
-        struct ip_options       *opt;
-};
-
-#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE)
-struct tcp_v6_open_req {
-        struct in6_addr         loc_addr;
-        struct in6_addr         rmt_addr;
-        struct sk_buff          *pktopts;
-        int                     iif;
-};
-#endif
-
-/* this structure is too big */
-struct open_request {
-        struct open_request     *dl_next; /* Must be first member! */
-        __u32                   rcv_isn;
-        __u32                   snt_isn;
-        __u16                   rmt_port;
-        __u16                   mss;
-        __u8                    retrans;
-        __u8                    __pad;
-        __u16   snd_wscale : 4, 
-                rcv_wscale : 4, 
-                tstamp_ok : 1,
-                sack_ok : 1,
-                wscale_ok : 1,
-                ecn_ok : 1,
-                acked : 1;
-        /* The following two fields can be easily recomputed I think -AK */
-        __u32                   window_clamp;   /* window clamp at creation time */
-        __u32                   rcv_wnd;        /* rcv_wnd offered first time */
-        __u32                   ts_recent;
-        unsigned long           expires;
-        struct or_calltable     *class;
-        struct sock             *sk;
-        union {
-                struct tcp_v4_open_req v4_req;
-#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE)
-                struct tcp_v6_open_req v6_req;
-#endif
-        } af;
-};
-
-/* SLAB cache for open requests. */
-extern kmem_cache_t *tcp_openreq_cachep;
-
-#define tcp_openreq_alloc()             kmem_cache_alloc(tcp_openreq_cachep, SLAB_ATOMIC)
-#define tcp_openreq_fastfree(req)       kmem_cache_free(tcp_openreq_cachep, req)
-
-static inline void tcp_openreq_free(struct open_request *req)
-{
-        req->class->destructor(req);
-        tcp_openreq_fastfree(req);
-}
-
-#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-#define TCP_INET_FAMILY(fam) ((fam) == AF_INET)
-#else
-#define TCP_INET_FAMILY(fam) 1
-#endif
-
 /*
  *      Pointers to address related TCP functions
  *      (i.e. things that depend on the address family)
@@ -708,7 +243,7 @@ struct tcp_func {
 
         struct sock *           (*syn_recv_sock)        (struct sock *sk,
                                                          struct sk_buff *skb,
-                                                         struct open_request *req,
+                                                         struct request_sock *req,
                                                          struct dst_entry *dst);
     
         int                     (*remember_stamp)       (struct sock *sk);
@@ -767,9 +302,6 @@ DECLARE_SNMP_STAT(struct tcp_mib, tcp_statistics);
 #define TCP_ADD_STATS_BH(field, val)    SNMP_ADD_STATS_BH(tcp_statistics, field, val)
 #define TCP_ADD_STATS_USER(field, val)  SNMP_ADD_STATS_USER(tcp_statistics, field, val)
 
-extern void                     tcp_put_port(struct sock *sk);
-extern void                     tcp_inherit_port(struct sock *sk, struct sock *child);
-
 extern void                     tcp_v4_err(struct sk_buff *skb, u32);
 
 extern void                     tcp_shutdown (struct sock *sk, int how);
@@ -778,7 +310,7 @@ extern int			tcp_v4_rcv(struct sk_buff *skb);
 
 extern int                      tcp_v4_remember_stamp(struct sock *sk);
 
-extern int                      tcp_v4_tw_remember_stamp(struct tcp_tw_bucket *tw);
+extern int                      tcp_v4_tw_remember_stamp(struct inet_timewait_sock *tw);
 
 extern int                      tcp_sendmsg(struct kiocb *iocb, struct sock *sk,
                                             struct msghdr *msg, size_t size);
@@ -800,37 +332,22 @@ extern int			tcp_rcv_established(struct sock *sk,
 
 extern void                     tcp_rcv_space_adjust(struct sock *sk);
 
-enum tcp_ack_state_t
+static inline void tcp_dec_quickack_mode(struct sock *sk,
+                                         const unsigned int pkts)
 {
-        TCP_ACK_SCHED = 1,
-        TCP_ACK_TIMER = 2,
-        TCP_ACK_PUSHED= 4
-};
+        struct inet_connection_sock *icsk = inet_csk(sk);
 
-static inline void tcp_schedule_ack(struct tcp_sock *tp)
-{
-        tp->ack.pending |= TCP_ACK_SCHED;
-}
-
-static inline int tcp_ack_scheduled(struct tcp_sock *tp)
-{
-        return tp->ack.pending&TCP_ACK_SCHED;
-}
-
-static __inline__ void tcp_dec_quickack_mode(struct tcp_sock *tp)
-{
-        if (tp->ack.quick && --tp->ack.quick == 0) {
-                /* Leaving quickack mode we deflate ATO. */
-                tp->ack.ato = TCP_ATO_MIN;
+        if (icsk->icsk_ack.quick) {
+                if (pkts >= icsk->icsk_ack.quick) {
+                        icsk->icsk_ack.quick = 0;
+                        /* Leaving quickack mode we deflate ATO. */
+                        icsk->icsk_ack.ato   = TCP_ATO_MIN;
+                } else
+                        icsk->icsk_ack.quick -= pkts;
         }
 }
 
-extern void tcp_enter_quickack_mode(struct tcp_sock *tp);
-
-static __inline__ void tcp_delack_init(struct tcp_sock *tp)
-{
-        memset(&tp->ack, 0, sizeof(tp->ack));
-}
+extern void tcp_enter_quickack_mode(struct sock *sk);
 
 static inline void tcp_clear_options(struct tcp_options_received *rx_opt)
 {
@@ -846,14 +363,13 @@ enum tcp_tw_status
 };
 
 
-extern enum tcp_tw_status       tcp_timewait_state_process(struct tcp_tw_bucket *tw,
+extern enum tcp_tw_status       tcp_timewait_state_process(struct inet_timewait_sock *tw,
                                                            struct sk_buff *skb,
-                                                           struct tcphdr *th,
-                                                           unsigned len);
+                                                           const struct tcphdr *th);
 
 extern struct sock *            tcp_check_req(struct sock *sk,struct sk_buff *skb,
-                                              struct open_request *req,
-                                              struct open_request **prev);
+                                              struct request_sock *req,
+                                              struct request_sock **prev);
 extern int                      tcp_child_process(struct sock *parent,
                                                   struct sock *child,
                                                   struct sk_buff *skb);
@@ -864,7 +380,6 @@ extern void			tcp_update_metrics(struct sock *sk);
 
 extern void                     tcp_close(struct sock *sk, 
                                           long timeout);
-extern struct sock *            tcp_accept(struct sock *sk, int flags, int *err);
 extern unsigned int             tcp_poll(struct file * file, struct socket *sock, struct poll_table_struct *wait);
 
 extern int                      tcp_getsockopt(struct sock *sk, int level, 
@@ -880,8 +395,6 @@ extern int			tcp_recvmsg(struct kiocb *iocb, struct sock *sk,
                                             size_t len, int nonblock, 
                                             int flags, int *addr_len);
 
-extern int                      tcp_listen_start(struct sock *sk);
-
 extern void                     tcp_parse_options(struct sk_buff *skb,
                                                   struct tcp_options_received *opt_rx,
                                                   int estab);
@@ -890,11 +403,6 @@ extern void			tcp_parse_options(struct sk_buff *skb,
  *      TCP v4 functions exported for the inet6 API
  */
 
-extern int                      tcp_v4_rebuild_header(struct sock *sk);
-
-extern int                      tcp_v4_build_header(struct sock *sk, 
-                                                    struct sk_buff *skb);
-
 extern void                     tcp_v4_send_check(struct sock *sk, 
                                                   struct tcphdr *th, int len, 
                                                   struct sk_buff *skb);
@@ -903,12 +411,12 @@ extern int			tcp_v4_conn_request(struct sock *sk,
                                                     struct sk_buff *skb);
 
 extern struct sock *            tcp_create_openreq_child(struct sock *sk,
-                                                         struct open_request *req,
+                                                         struct request_sock *req,
                                                          struct sk_buff *skb);
 
 extern struct sock *            tcp_v4_syn_recv_sock(struct sock *sk,
                                                      struct sk_buff *skb,
-                                                     struct open_request *req,
+                                                     struct request_sock *req,
                                                         struct dst_entry *dst);
 
 extern int                      tcp_v4_do_rcv(struct sock *sk,
@@ -922,7 +430,7 @@ extern int			tcp_connect(struct sock *sk);
 
 extern struct sk_buff *         tcp_make_synack(struct sock *sk,
                                                 struct dst_entry *dst,
-                                                struct open_request *req);
+                                                struct request_sock *req);
 
 extern int                      tcp_disconnect(struct sock *sk, int flags);
 
@@ -939,36 +447,40 @@ extern __u32 cookie_v4_init_sequence(struct sock *sk, struct sk_buff *skb,
 
 /* tcp_output.c */
 
-extern int tcp_write_xmit(struct sock *, int nonagle);
+extern void __tcp_push_pending_frames(struct sock *sk, struct tcp_sock *tp,
+                                      unsigned int cur_mss, int nonagle);
+extern int tcp_may_send_now(struct sock *sk, struct tcp_sock *tp);
 extern int tcp_retransmit_skb(struct sock *, struct sk_buff *);
 extern void tcp_xmit_retransmit_queue(struct sock *);
 extern void tcp_simple_retransmit(struct sock *);
 extern int tcp_trim_head(struct sock *, struct sk_buff *, u32);
+extern int tcp_fragment(struct sock *, struct sk_buff *, u32, unsigned int);
 
 extern void tcp_send_probe0(struct sock *);
 extern void tcp_send_partial(struct sock *);
 extern int  tcp_write_wakeup(struct sock *);
 extern void tcp_send_fin(struct sock *sk);
-extern void tcp_send_active_reset(struct sock *sk, int priority);
+extern void tcp_send_active_reset(struct sock *sk,
+                                  unsigned int __nocast priority);
 extern int  tcp_send_synack(struct sock *);
-extern void tcp_push_one(struct sock *, unsigned mss_now);
+extern void tcp_push_one(struct sock *, unsigned int mss_now);
 extern void tcp_send_ack(struct sock *sk);
 extern void tcp_send_delayed_ack(struct sock *sk);
 
+/* tcp_input.c */
+extern void tcp_cwnd_application_limited(struct sock *sk);
+
 /* tcp_timer.c */
 extern void tcp_init_xmit_timers(struct sock *);
-extern void tcp_clear_xmit_timers(struct sock *);
+static inline void tcp_clear_xmit_timers(struct sock *sk)
+{
+        inet_csk_clear_xmit_timers(sk);
+}
 
-extern void tcp_delete_keepalive_timer(struct sock *);
-extern void tcp_reset_keepalive_timer(struct sock *, unsigned long);
 extern unsigned int tcp_sync_mss(struct sock *sk, u32 pmtu);
 extern unsigned int tcp_current_mss(struct sock *sk, int large);
 
-#ifdef TCP_DEBUG
-extern const char tcp_timer_bug_msg[];
-#endif
-
-/* tcp_diag.c */
+/* tcp.c */
 extern void tcp_get_info(struct sock *, struct tcp_info *);
 
 /* Read 'sendfile()'-style from a TCP socket */
@@ -977,72 +489,6 @@ typedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *,
 extern int tcp_read_sock(struct sock *sk, read_descriptor_t *desc,
                          sk_read_actor_t recv_actor);
 
-static inline void tcp_clear_xmit_timer(struct sock *sk, int what)
-{
-        struct tcp_sock *tp = tcp_sk(sk);
-        
-        switch (what) {
-        case TCP_TIME_RETRANS:
-        case TCP_TIME_PROBE0:
-                tp->pending = 0;
-
-#ifdef TCP_CLEAR_TIMERS
-                sk_stop_timer(sk, &tp->retransmit_timer);
-#endif
-                break;
-        case TCP_TIME_DACK:
-                tp->ack.blocked = 0;
-                tp->ack.pending = 0;
-
-#ifdef TCP_CLEAR_TIMERS
-                sk_stop_timer(sk, &tp->delack_timer);
-#endif
-                break;
-        default:
-#ifdef TCP_DEBUG
-                printk(tcp_timer_bug_msg);
-#endif
-                return;
-        };
-
-}
-
-/*
- *      Reset the retransmission timer
- */
-static inline void tcp_reset_xmit_timer(struct sock *sk, int what, unsigned long when)
-{
-        struct tcp_sock *tp = tcp_sk(sk);
-
-        if (when > TCP_RTO_MAX) {
-#ifdef TCP_DEBUG
-                printk(KERN_DEBUG "reset_xmit_timer sk=%p %d when=0x%lx, caller=%p\n", sk, what, when, current_text_addr());
-#endif
-                when = TCP_RTO_MAX;
-        }
-
-        switch (what) {
-        case TCP_TIME_RETRANS:
-        case TCP_TIME_PROBE0:
-                tp->pending = what;
-                tp->timeout = jiffies+when;
-                sk_reset_timer(sk, &tp->retransmit_timer, tp->timeout);
-                break;
-
-        case TCP_TIME_DACK:
-                tp->ack.pending |= TCP_ACK_TIMER;
-                tp->ack.timeout = jiffies+when;
-                sk_reset_timer(sk, &tp->delack_timer, tp->ack.timeout);
-                break;
-
-        default:
-#ifdef TCP_DEBUG
-                printk(tcp_timer_bug_msg);
-#endif
-                return;
-        };
-}
-
 /* Initialize RCV_MSS value.
  * RCV_MSS is an our guess about MSS used by the peer.
  * We haven't any direct information about the MSS.
@@ -1054,13 +500,13 @@ static inline void tcp_reset_xmit_timer(struct sock *sk, int what, unsigned long
 static inline void tcp_initialize_rcv_mss(struct sock *sk)
 {
         struct tcp_sock *tp = tcp_sk(sk);
-        unsigned int hint = min(tp->advmss, tp->mss_cache_std);
+        unsigned int hint = min_t(unsigned int, tp->advmss, tp->mss_cache);
 
         hint = min(hint, tp->rcv_wnd/2);
         hint = min(hint, TCP_MIN_RCVMSS);
         hint = max(hint, TCP_MIN_MSS);
 
-        tp->ack.rcv_mss = hint;
+        inet_csk(sk)->icsk_ack.rcv_mss = hint;
 }
 
 static __inline__ void __tcp_fast_path_on(struct tcp_sock *tp, u32 snd_wnd)
@@ -1077,7 +523,7 @@ static __inline__ void tcp_fast_path_on(struct tcp_sock *tp)
 
 static inline void tcp_fast_path_check(struct sock *sk, struct tcp_sock *tp)
 {
-        if (skb_queue_len(&tp->out_of_order_queue) == 0 &&
+        if (skb_queue_empty(&tp->out_of_order_queue) &&
             tp->rcv_wnd &&
             atomic_read(&sk->sk_rmem_alloc) < sk->sk_rcvbuf &&
             !tp->urg_data)
@@ -1195,7 +641,8 @@ static inline void tcp_packets_out_inc(struct sock *sk,
 
         tp->packets_out += tcp_skb_pcount(skb);
         if (!orig)
-                tcp_reset_xmit_timer(sk, TCP_TIME_RETRANS, tp->rto);
+                inet_csk_reset_xmit_timer(sk, ICSK_TIME_RETRANS,
+                                          inet_csk(sk)->icsk_rto, TCP_RTO_MAX);
 }
 
 static inline void tcp_packets_out_dec(struct tcp_sock *tp, 
@@ -1204,6 +651,86 @@ static inline void tcp_packets_out_dec(struct tcp_sock *tp,
         tp->packets_out -= tcp_skb_pcount(skb);
 }
 
+/* Events passed to congestion control interface */
+enum tcp_ca_event {
+        CA_EVENT_TX_START,      /* first transmit when no packets in flight */
+        CA_EVENT_CWND_RESTART,  /* congestion window restart */
+        CA_EVENT_COMPLETE_CWR,  /* end of congestion recovery */
+        CA_EVENT_FRTO,          /* fast recovery timeout */
+        CA_EVENT_LOSS,          /* loss timeout */
+        CA_EVENT_FAST_ACK,      /* in sequence ack */
+        CA_EVENT_SLOW_ACK,      /* other ack */
+};
+
+/*
+ * Interface for adding new TCP congestion control handlers
+ */
+#define TCP_CA_NAME_MAX 16
+struct tcp_congestion_ops {
+        struct list_head        list;
+
+        /* initialize private data (optional) */
+        void (*init)(struct sock *sk);
+        /* cleanup private data  (optional) */
+        void (*release)(struct sock *sk);
+
+        /* return slow start threshold (required) */
+        u32 (*ssthresh)(struct sock *sk);
+        /* lower bound for congestion window (optional) */
+        u32 (*min_cwnd)(struct sock *sk);
+        /* do new cwnd calculation (required) */
+        void (*cong_avoid)(struct sock *sk, u32 ack,
+                           u32 rtt, u32 in_flight, int good_ack);
+        /* round trip time sample per acked packet (optional) */
+        void (*rtt_sample)(struct sock *sk, u32 usrtt);
+        /* call before changing ca_state (optional) */
+        void (*set_state)(struct sock *sk, u8 new_state);
+        /* call when cwnd event occurs (optional) */
+        void (*cwnd_event)(struct sock *sk, enum tcp_ca_event ev);
+        /* new value of cwnd after loss (optional) */
+        u32  (*undo_cwnd)(struct sock *sk);
+        /* hook for packet ack accounting (optional) */
+        void (*pkts_acked)(struct sock *sk, u32 num_acked);
+        /* get info for inet_diag (optional) */
+        void (*get_info)(struct sock *sk, u32 ext, struct sk_buff *skb);
+
+        char            name[TCP_CA_NAME_MAX];
+        struct module   *owner;
+};
+
+extern int tcp_register_congestion_control(struct tcp_congestion_ops *type);
+extern void tcp_unregister_congestion_control(struct tcp_congestion_ops *type);
+
+extern void tcp_init_congestion_control(struct sock *sk);
+extern void tcp_cleanup_congestion_control(struct sock *sk);
+extern int tcp_set_default_congestion_control(const char *name);
+extern void tcp_get_default_congestion_control(char *name);
+extern int tcp_set_congestion_control(struct sock *sk, const char *name);
+
+extern struct tcp_congestion_ops tcp_init_congestion_ops;
+extern u32 tcp_reno_ssthresh(struct sock *sk);
+extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack,
+                                u32 rtt, u32 in_flight, int flag);
+extern u32 tcp_reno_min_cwnd(struct sock *sk);
+extern struct tcp_congestion_ops tcp_reno;
+
+static inline void tcp_set_ca_state(struct sock *sk, const u8 ca_state)
+{
+        struct inet_connection_sock *icsk = inet_csk(sk);
+
+        if (icsk->icsk_ca_ops->set_state)
+                icsk->icsk_ca_ops->set_state(sk, ca_state);
+        icsk->icsk_ca_state = ca_state;
+}
+
+static inline void tcp_ca_event(struct sock *sk, const enum tcp_ca_event event)
+{
+        const struct inet_connection_sock *icsk = inet_csk(sk);
+
+        if (icsk->icsk_ca_ops->cwnd_event)
+                icsk->icsk_ca_ops->cwnd_event(sk, event);
+}
+
 /* This determines how many packets are "in the network" to the best
  * of our knowledge.  In many cases it is conservative, but where
  * detailed information is available from the receiver (via SACK
@@ -1223,98 +750,14 @@ static __inline__ unsigned int tcp_packets_in_flight(const struct tcp_sock *tp)
         return (tp->packets_out - tp->left_out + tp->retrans_out);
 }
 
-/*
- * Which congestion algorithim is in use on the connection.
- */
-#define tcp_is_vegas(__tp)      ((__tp)->adv_cong == TCP_VEGAS)
-#define tcp_is_westwood(__tp)   ((__tp)->adv_cong == TCP_WESTWOOD)
-#define tcp_is_bic(__tp)        ((__tp)->adv_cong == TCP_BIC)
-
-/* Recalculate snd_ssthresh, we want to set it to:
- *
- * Reno:
- *      one half the current congestion window, but no
- *      less than two segments
- *
- * BIC:
- *      behave like Reno until low_window is reached,
- *      then increase congestion window slowly
- */
-static inline __u32 tcp_recalc_ssthresh(struct tcp_sock *tp)
-{
-        if (tcp_is_bic(tp)) {
-                if (sysctl_tcp_bic_fast_convergence &&
-                    tp->snd_cwnd < tp->bictcp.last_max_cwnd)
-                        tp->bictcp.last_max_cwnd = (tp->snd_cwnd * 
-                                                    (BICTCP_BETA_SCALE
-                                                     + sysctl_tcp_bic_beta))
-                                / (2 * BICTCP_BETA_SCALE);
-                else
-                        tp->bictcp.last_max_cwnd = tp->snd_cwnd;
-
-                if (tp->snd_cwnd > sysctl_tcp_bic_low_window)
-                        return max((tp->snd_cwnd * sysctl_tcp_bic_beta)
-                                   / BICTCP_BETA_SCALE, 2U);
-        }
-
-        return max(tp->snd_cwnd >> 1U, 2U);
-}
-
-/* Stop taking Vegas samples for now. */
-#define tcp_vegas_disable(__tp) ((__tp)->vegas.doing_vegas_now = 0)
-    
-static inline void tcp_vegas_enable(struct tcp_sock *tp)
-{
-        /* There are several situations when we must "re-start" Vegas:
-         *
-         *  o when a connection is established
-         *  o after an RTO
-         *  o after fast recovery
-         *  o when we send a packet and there is no outstanding
-         *    unacknowledged data (restarting an idle connection)
-         *
-         * In these circumstances we cannot do a Vegas calculation at the
-         * end of the first RTT, because any calculation we do is using
-         * stale info -- both the saved cwnd and congestion feedback are
-         * stale.
-         *
-         * Instead we must wait until the completion of an RTT during
-         * which we actually receive ACKs.
-         */
-    
-        /* Begin taking Vegas samples next time we send something. */
-        tp->vegas.doing_vegas_now = 1;
-     
-        /* Set the beginning of the next send window. */
-        tp->vegas.beg_snd_nxt = tp->snd_nxt;
-
-        tp->vegas.cntRTT = 0;
-        tp->vegas.minRTT = 0x7fffffff;
-}
-
-/* Should we be taking Vegas samples right now? */
-#define tcp_vegas_enabled(__tp) ((__tp)->vegas.doing_vegas_now)
-
-extern void tcp_ca_init(struct tcp_sock *tp);
-
-static inline void tcp_set_ca_state(struct tcp_sock *tp, u8 ca_state)
-{
-        if (tcp_is_vegas(tp)) {
-                if (ca_state == TCP_CA_Open) 
-                        tcp_vegas_enable(tp);
-                else
-                        tcp_vegas_disable(tp);
-        }
-        tp->ca_state = ca_state;
-}
-
 /* If cwnd > ssthresh, we may raise ssthresh to be half-way to cwnd.
  * The exception is rate halving phase, when cwnd is decreasing towards
  * ssthresh.
  */
-static inline __u32 tcp_current_ssthresh(struct tcp_sock *tp)
+static inline __u32 tcp_current_ssthresh(const struct sock *sk)
 {
-        if ((1<<tp->ca_state)&(TCPF_CA_CWR|TCPF_CA_Recovery))
+        const struct tcp_sock *tp = tcp_sk(sk);
+        if ((1 << inet_csk(sk)->icsk_ca_state) & (TCPF_CA_CWR | TCPF_CA_Recovery))
                 return tp->snd_ssthresh;
         else
                 return max(tp->snd_ssthresh,
@@ -1330,33 +773,14 @@ static inline void tcp_sync_left_out(struct tcp_sock *tp)
         tp->left_out = tp->sacked_out + tp->lost_out;
 }
 
-extern void tcp_cwnd_application_limited(struct sock *sk);
-
-/* Congestion window validation. (RFC2861) */
-
-static inline void tcp_cwnd_validate(struct sock *sk, struct tcp_sock *tp)
+/* Set slow start threshold and cwnd not falling to slow start */
+static inline void __tcp_enter_cwr(struct sock *sk)
 {
-        __u32 packets_out = tp->packets_out;
-
-        if (packets_out >= tp->snd_cwnd) {
-                /* Network is feed fully. */
-                tp->snd_cwnd_used = 0;
-                tp->snd_cwnd_stamp = tcp_time_stamp;
-        } else {
-                /* Network starves. */
-                if (tp->packets_out > tp->snd_cwnd_used)
-                        tp->snd_cwnd_used = tp->packets_out;
-
-                if ((s32)(tcp_time_stamp - tp->snd_cwnd_stamp) >= tp->rto)
-                        tcp_cwnd_application_limited(sk);
-        }
-}
+        const struct inet_connection_sock *icsk = inet_csk(sk);
+        struct tcp_sock *tp = tcp_sk(sk);
 
-/* Set slow start threshould and cwnd not falling to slow start */
-static inline void __tcp_enter_cwr(struct tcp_sock *tp)
-{
         tp->undo_marker = 0;
-        tp->snd_ssthresh = tcp_recalc_ssthresh(tp);
+        tp->snd_ssthresh = icsk->icsk_ca_ops->ssthresh(sk);
         tp->snd_cwnd = min(tp->snd_cwnd,
                            tcp_packets_in_flight(tp) + 1U);
         tp->snd_cwnd_cnt = 0;
@@ -1365,12 +789,14 @@ static inline void __tcp_enter_cwr(struct tcp_sock *tp)
         TCP_ECN_queue_cwr(tp);
 }
 
-static inline void tcp_enter_cwr(struct tcp_sock *tp)
+static inline void tcp_enter_cwr(struct sock *sk)
 {
+        struct tcp_sock *tp = tcp_sk(sk);
+
         tp->prior_ssthresh = 0;
-        if (tp->ca_state < TCP_CA_CWR) {
-                __tcp_enter_cwr(tp);
-                tcp_set_ca_state(tp, TCP_CA_CWR);
+        if (inet_csk(sk)->icsk_ca_state < TCP_CA_CWR) {
+                __tcp_enter_cwr(sk);
+                tcp_set_ca_state(sk, TCP_CA_CWR);
         }
 }
 
@@ -1384,12 +810,6 @@ static __inline__ __u32 tcp_max_burst(const struct tcp_sock *tp)
         return 3;
 }
 
-static __inline__ int tcp_minshall_check(const struct tcp_sock *tp)
-{
-        return after(tp->snd_sml,tp->snd_una) &&
-                !after(tp->snd_sml, tp->snd_nxt);
-}
-
 static __inline__ void tcp_minshall_update(struct tcp_sock *tp, int mss, 
                                            const struct sk_buff *skb)
 {
@@ -1397,105 +817,12 @@ static __inline__ void tcp_minshall_update(struct tcp_sock *tp, int mss,
                 tp->snd_sml = TCP_SKB_CB(skb)->end_seq;
 }
 
-/* Return 0, if packet can be sent now without violation Nagle's rules:
-   1. It is full sized.
-   2. Or it contains FIN.
-   3. Or TCP_NODELAY was set.
-   4. Or TCP_CORK is not set, and all sent packets are ACKed.
-      With Minshall's modification: all sent small packets are ACKed.
- */
-
-static __inline__ int
-tcp_nagle_check(const struct tcp_sock *tp, const struct sk_buff *skb, 
-                unsigned mss_now, int nonagle)
-{
-        return (skb->len < mss_now &&
-                !(TCP_SKB_CB(skb)->flags & TCPCB_FLAG_FIN) &&
-                ((nonagle&TCP_NAGLE_CORK) ||
-                 (!nonagle &&
-                  tp->packets_out &&
-                  tcp_minshall_check(tp))));
-}
-
-extern void tcp_set_skb_tso_segs(struct sock *, struct sk_buff *);
-
-/* This checks if the data bearing packet SKB (usually sk->sk_send_head)
- * should be put on the wire right now.
- */
-static __inline__ int tcp_snd_test(struct sock *sk,
-                                   struct sk_buff *skb,
-                                   unsigned cur_mss, int nonagle)
-{
-        struct tcp_sock *tp = tcp_sk(sk);
-        int pkts = tcp_skb_pcount(skb);
-
-        if (!pkts) {
-                tcp_set_skb_tso_segs(sk, skb);
-                pkts = tcp_skb_pcount(skb);
-        }
-
-        /*      RFC 1122 - section 4.2.3.4
-         *
-         *      We must queue if
-         *
-         *      a) The right edge of this frame exceeds the window
-         *      b) There are packets in flight and we have a small segment
-         *         [SWS avoidance and Nagle algorithm]
-         *         (part of SWS is done on packetization)
-         *         Minshall version sounds: there are no _small_
-         *         segments in flight. (tcp_nagle_check)
-         *      c) We have too many packets 'in flight'
-         *
-         *      Don't use the nagle rule for urgent data (or
-         *      for the final FIN -DaveM).
-         *
-         *      Also, Nagle rule does not apply to frames, which
-         *      sit in the middle of queue (they have no chances
-         *      to get new data) and if room at tail of skb is
-         *      not enough to save something seriously (<32 for now).
-         */
-
-        /* Don't be strict about the congestion window for the
-         * final FIN frame.  -DaveM
-         */
-        return (((nonagle&TCP_NAGLE_PUSH) || tp->urg_mode
-                 || !tcp_nagle_check(tp, skb, cur_mss, nonagle)) &&
-                (((tcp_packets_in_flight(tp) + (pkts-1)) < tp->snd_cwnd) ||
-                 (TCP_SKB_CB(skb)->flags & TCPCB_FLAG_FIN)) &&
-                !after(TCP_SKB_CB(skb)->end_seq, tp->snd_una + tp->snd_wnd));
-}
-
 static __inline__ void tcp_check_probe_timer(struct sock *sk, struct tcp_sock *tp)
 {
-        if (!tp->packets_out && !tp->pending)
-                tcp_reset_xmit_timer(sk, TCP_TIME_PROBE0, tp->rto);
-}
-
-static __inline__ int tcp_skb_is_last(const struct sock *sk, 
-                                      const struct sk_buff *skb)
-{
-        return skb->next == (struct sk_buff *)&sk->sk_write_queue;
-}
-
-/* Push out any pending frames which were held back due to
- * TCP_CORK or attempt at coalescing tiny packets.
- * The socket must be locked by the caller.
- */
-static __inline__ void __tcp_push_pending_frames(struct sock *sk,
-                                                 struct tcp_sock *tp,
-                                                 unsigned cur_mss,
-                                                 int nonagle)
-{
-        struct sk_buff *skb = sk->sk_send_head;
-
-        if (skb) {
-                if (!tcp_skb_is_last(sk, skb))
-                        nonagle = TCP_NAGLE_PUSH;
-                if (!tcp_snd_test(sk, skb, cur_mss, nonagle) ||
-                    tcp_write_xmit(sk, nonagle))
-                        tcp_check_probe_timer(sk, tp);
-        }
-        tcp_cwnd_validate(sk, tp);
+        const struct inet_connection_sock *icsk = inet_csk(sk);
+        if (!tp->packets_out && !icsk->icsk_pending)
+                inet_csk_reset_xmit_timer(sk, ICSK_TIME_PROBE0,
+                                          icsk->icsk_rto, TCP_RTO_MAX);
 }
 
 static __inline__ void tcp_push_pending_frames(struct sock *sk,
@@ -1504,15 +831,6 @@ static __inline__ void tcp_push_pending_frames(struct sock *sk,
         __tcp_push_pending_frames(sk, tp, tcp_current_mss(sk, 1), tp->nonagle);
 }
 
-static __inline__ int tcp_may_send_now(struct sock *sk, struct tcp_sock *tp)
-{
-        struct sk_buff *skb = sk->sk_send_head;
-
-        return (skb &&
-                tcp_snd_test(sk, skb, tcp_current_mss(sk, 1),
-                             tcp_skb_is_last(sk, skb) ? TCP_NAGLE_PUSH : tp->nonagle));
-}
-
 static __inline__ void tcp_init_wl(struct tcp_sock *tp, u32 ack, u32 seq)
 {
         tp->snd_wl1 = seq;
@@ -1523,9 +841,6 @@ static __inline__ void tcp_update_wl(struct tcp_sock *tp, u32 ack, u32 seq)
         tp->snd_wl1 = seq;
 }
 
-extern void tcp_destroy_sock(struct sock *sk);
-
-
 /*
  * Calculate(/check) TCP checksum
  */
@@ -1585,8 +900,10 @@ static __inline__ int tcp_prequeue(struct sock *sk, struct sk_buff *skb)
                         tp->ucopy.memory = 0;
                 } else if (skb_queue_len(&tp->ucopy.prequeue) == 1) {
                         wake_up_interruptible(sk->sk_sleep);
-                        if (!tcp_ack_scheduled(tp))
-                                tcp_reset_xmit_timer(sk, TCP_TIME_DACK, (3*TCP_RTO_MIN)/4);
+                        if (!inet_csk_ack_scheduled(sk))
+                                inet_csk_reset_xmit_timer(sk, ICSK_TIME_DACK,
+                                                          (3 * TCP_RTO_MIN) / 4,
+                                                          TCP_RTO_MAX);
                 }
                 return 1;
         }
@@ -1619,9 +936,9 @@ static __inline__ void tcp_set_state(struct sock *sk, int state)
                         TCP_INC_STATS(TCP_MIB_ESTABRESETS);
 
                 sk->sk_prot->unhash(sk);
-                if (tcp_sk(sk)->bind_hash &&
+                if (inet_csk(sk)->icsk_bind_hash &&
                     !(sk->sk_userlocks & SOCK_BINDPORT_LOCK))
-                        tcp_put_port(sk);
+                        inet_put_port(&tcp_hashinfo, sk);
                 /* fall through */
         default:
                 if (oldstate==TCP_ESTABLISHED)
@@ -1648,7 +965,7 @@ static __inline__ void tcp_done(struct sock *sk)
         if (!sock_flag(sk, SOCK_DEAD))
                 sk->sk_state_change(sk);
         else
-                tcp_destroy_sock(sk);
+                inet_csk_destroy_sock(sk);
 }
 
 static __inline__ void tcp_sack_reset(struct tcp_options_received *rx_opt)
@@ -1750,124 +1067,27 @@ static inline int tcp_full_space(const struct sock *sk)
         return tcp_win_from_space(sk->sk_rcvbuf); 
 }
 
-static inline void tcp_acceptq_queue(struct sock *sk, struct open_request *req,
-                                         struct sock *child)
-{
-        struct tcp_sock *tp = tcp_sk(sk);
-
-        req->sk = child;
-        sk_acceptq_added(sk);
-
-        if (!tp->accept_queue_tail) {
-                tp->accept_queue = req;
-        } else {
-                tp->accept_queue_tail->dl_next = req;
-        }
-        tp->accept_queue_tail = req;
-        req->dl_next = NULL;
-}
-
-struct tcp_listen_opt
-{
-        u8                      max_qlen_log;   /* log_2 of maximal queued SYNs */
-        int                     qlen;
-        int                     qlen_young;
-        int                     clock_hand;
-        u32                     hash_rnd;
-        struct open_request     *syn_table[TCP_SYNQ_HSIZE];
-};
-
-static inline void
-tcp_synq_removed(struct sock *sk, struct open_request *req)
-{
-        struct tcp_listen_opt *lopt = tcp_sk(sk)->listen_opt;
-
-        if (--lopt->qlen == 0)
-                tcp_delete_keepalive_timer(sk);
-        if (req->retrans == 0)
-                lopt->qlen_young--;
-}
-
-static inline void tcp_synq_added(struct sock *sk)
-{
-        struct tcp_listen_opt *lopt = tcp_sk(sk)->listen_opt;
-
-        if (lopt->qlen++ == 0)
-                tcp_reset_keepalive_timer(sk, TCP_TIMEOUT_INIT);
-        lopt->qlen_young++;
-}
-
-static inline int tcp_synq_len(struct sock *sk)
-{
-        return tcp_sk(sk)->listen_opt->qlen;
-}
-
-static inline int tcp_synq_young(struct sock *sk)
-{
-        return tcp_sk(sk)->listen_opt->qlen_young;
-}
-
-static inline int tcp_synq_is_full(struct sock *sk)
-{
-        return tcp_synq_len(sk) >> tcp_sk(sk)->listen_opt->max_qlen_log;
-}
-
-static inline void tcp_synq_unlink(struct tcp_sock *tp, struct open_request *req,
-                                       struct open_request **prev)
-{
-        write_lock(&tp->syn_wait_lock);
-        *prev = req->dl_next;
-        write_unlock(&tp->syn_wait_lock);
-}
-
-static inline void tcp_synq_drop(struct sock *sk, struct open_request *req,
-                                     struct open_request **prev)
-{
-        tcp_synq_unlink(tcp_sk(sk), req, prev);
-        tcp_synq_removed(sk, req);
-        tcp_openreq_free(req);
-}
-
-static __inline__ void tcp_openreq_init(struct open_request *req,
+static __inline__ void tcp_openreq_init(struct request_sock *req,
                                         struct tcp_options_received *rx_opt,
                                         struct sk_buff *skb)
 {
+        struct inet_request_sock *ireq = inet_rsk(req);
+
         req->rcv_wnd = 0;               /* So that tcp_send_synack() knows! */
-        req->rcv_isn = TCP_SKB_CB(skb)->seq;
+        tcp_rsk(req)->rcv_isn = TCP_SKB_CB(skb)->seq;
         req->mss = rx_opt->mss_clamp;
         req->ts_recent = rx_opt->saw_tstamp ? rx_opt->rcv_tsval : 0;
-        req->tstamp_ok = rx_opt->tstamp_ok;
-        req->sack_ok = rx_opt->sack_ok;
-        req->snd_wscale = rx_opt->snd_wscale;
-        req->wscale_ok = rx_opt->wscale_ok;
-        req->acked = 0;
-        req->ecn_ok = 0;
-        req->rmt_port = skb->h.th->source;
+        ireq->tstamp_ok = rx_opt->tstamp_ok;
+        ireq->sack_ok = rx_opt->sack_ok;
+        ireq->snd_wscale = rx_opt->snd_wscale;
+        ireq->wscale_ok = rx_opt->wscale_ok;
+        ireq->acked = 0;
+        ireq->ecn_ok = 0;
+        ireq->rmt_port = skb->h.th->source;
 }
 
 extern void tcp_enter_memory_pressure(void);
 
-extern void tcp_listen_wlock(void);
-
-/* - We may sleep inside this lock.
- * - If sleeping is not required (or called from BH),
- *   use plain read_(un)lock(&tcp_lhash_lock).
- */
-
-static inline void tcp_listen_lock(void)
-{
-        /* read_lock synchronizes to candidates to writers */
-        read_lock(&tcp_lhash_lock);
-        atomic_inc(&tcp_lhash_users);
-        read_unlock(&tcp_lhash_lock);
-}
-
-static inline void tcp_listen_unlock(void)
-{
-        if (atomic_dec_and_test(&tcp_lhash_users))
-                wake_up(&tcp_lhash_wait);
-}
-
 static inline int keepalive_intvl_when(const struct tcp_sock *tp)
 {
         return tp->keepalive_intvl ? : sysctl_tcp_keepalive_intvl;
@@ -1878,12 +1098,13 @@ static inline int keepalive_time_when(const struct tcp_sock *tp)
         return tp->keepalive_time ? : sysctl_tcp_keepalive_time;
 }
 
-static inline int tcp_fin_time(const struct tcp_sock *tp)
+static inline int tcp_fin_time(const struct sock *sk)
 {
-        int fin_timeout = tp->linger2 ? : sysctl_tcp_fin_timeout;
+        int fin_timeout = tcp_sk(sk)->linger2 ? : sysctl_tcp_fin_timeout;
+        const int rto = inet_csk(sk)->icsk_rto;
 
-        if (fin_timeout < (tp->rto<<2) - (tp->rto>>1))
-                fin_timeout = (tp->rto<<2) - (tp->rto>>1);
+        if (fin_timeout < (rto << 2) - (rto >> 1))
+                fin_timeout = (rto << 2) - (rto >> 1);
 
         return fin_timeout;
 }
@@ -1912,15 +1133,6 @@ static inline int tcp_paws_check(const struct tcp_options_received *rx_opt, int
         return 1;
 }
 
-static inline void tcp_v4_setup_caps(struct sock *sk, struct dst_entry *dst)
-{
-        sk->sk_route_caps = dst->dev->features;
-        if (sk->sk_route_caps & NETIF_F_TSO) {
-                if (sock_flag(sk, SOCK_NO_LARGESEND) || dst->header_len)
-                        sk->sk_route_caps &= ~NETIF_F_TSO;
-        }
-}
-
 #define TCP_CHECK_TIMER(sk) do { } while (0)
 
 static inline int tcp_use_frto(const struct sock *sk)
@@ -1972,52 +1184,16 @@ struct tcp_iter_state {
 extern int tcp_proc_register(struct tcp_seq_afinfo *afinfo);
 extern void tcp_proc_unregister(struct tcp_seq_afinfo *afinfo);
 
-/* TCP Westwood functions and constants */
-
-#define TCP_WESTWOOD_INIT_RTT  (20*HZ)           /* maybe too conservative?! */
-#define TCP_WESTWOOD_RTT_MIN   (HZ/20)           /* 50ms */
-
-static inline void tcp_westwood_update_rtt(struct tcp_sock *tp, __u32 rtt_seq)
-{
-        if (tcp_is_westwood(tp))
-                tp->westwood.rtt = rtt_seq;
-}
+extern struct request_sock_ops tcp_request_sock_ops;
 
-static inline __u32 __tcp_westwood_bw_rttmin(const struct tcp_sock *tp)
-{
-        return max((tp->westwood.bw_est) * (tp->westwood.rtt_min) /
-                   (__u32) (tp->mss_cache_std),
-                   2U);
-}
-
-static inline __u32 tcp_westwood_bw_rttmin(const struct tcp_sock *tp)
-{
-        return tcp_is_westwood(tp) ? __tcp_westwood_bw_rttmin(tp) : 0;
-}
+extern int tcp_v4_destroy_sock(struct sock *sk);
 
-static inline int tcp_westwood_ssthresh(struct tcp_sock *tp)
-{
-        __u32 ssthresh = 0;
-
-        if (tcp_is_westwood(tp)) {
-                ssthresh = __tcp_westwood_bw_rttmin(tp);
-                if (ssthresh)
-                        tp->snd_ssthresh = ssthresh;  
-        }
-
-        return (ssthresh != 0);
-}
+#ifdef CONFIG_PROC_FS
+extern int  tcp4_proc_init(void);
+extern void tcp4_proc_exit(void);
+#endif
 
-static inline int tcp_westwood_cwnd(struct tcp_sock *tp)
-{
-        __u32 cwnd = 0;
+extern void tcp_v4_init(struct net_proto_family *ops);
+extern void tcp_init(void);
 
-        if (tcp_is_westwood(tp)) {
-                cwnd = __tcp_westwood_bw_rttmin(tp);
-                if (cwnd)
-                        tp->snd_cwnd = cwnd;
-        }
-
-        return (cwnd != 0);
-}
 #endif  /* _TCP_H */
diff --git a/include/net/tcp_ecn.h b/include/net/tcp_ecn.h
index dc1456389a97..c6b84397448d 100644
--- a/include/net/tcp_ecn.h
+++ b/include/net/tcp_ecn.h
@@ -2,6 +2,7 @@
 #define _NET_TCP_ECN_H_ 1
 
 #include <net/inet_ecn.h>
+#include <net/request_sock.h>
 
 #define TCP_HP_BITS (~(TCP_RESERVED_BITS|TCP_FLAG_PSH))
 
@@ -38,9 +39,9 @@ static inline void TCP_ECN_send_syn(struct sock *sk, struct tcp_sock *tp,
 }
 
 static __inline__ void
-TCP_ECN_make_synack(struct open_request *req, struct tcphdr *th)
+TCP_ECN_make_synack(struct request_sock *req, struct tcphdr *th)
 {
-        if (req->ecn_ok)
+        if (inet_rsk(req)->ecn_ok)
                 th->ece = 1;
 }
 
@@ -87,7 +88,7 @@ static inline void TCP_ECN_check_ce(struct tcp_sock *tp, struct sk_buff *skb)
                  * it is surely retransmit. It is not in ECN RFC,
                  * but Linux follows this rule. */
                 else if (INET_ECN_is_not_ect((TCP_SKB_CB(skb)->flags)))
-                        tcp_enter_quickack_mode(tp);
+                        tcp_enter_quickack_mode((struct sock *)tp);
         }
 }
 
@@ -111,16 +112,16 @@ static inline int TCP_ECN_rcv_ecn_echo(struct tcp_sock *tp, struct tcphdr *th)
 }
 
 static inline void TCP_ECN_openreq_child(struct tcp_sock *tp,
-                                         struct open_request *req)
+                                         struct request_sock *req)
 {
-        tp->ecn_flags = req->ecn_ok ? TCP_ECN_OK : 0;
+        tp->ecn_flags = inet_rsk(req)->ecn_ok ? TCP_ECN_OK : 0;
 }
 
 static __inline__ void
-TCP_ECN_create_request(struct open_request *req, struct tcphdr *th)
+TCP_ECN_create_request(struct request_sock *req, struct tcphdr *th)
 {
         if (sysctl_tcp_ecn && th->ece && th->cwr)
-                req->ecn_ok = 1;
+                inet_rsk(req)->ecn_ok = 1;
 }
 
 #endif
diff --git a/include/net/tcp_states.h b/include/net/tcp_states.h
new file mode 100644
index 000000000000..b9d4176b2d15
--- /dev/null
+++ b/include/net/tcp_states.h
@@ -0,0 +1,34 @@
+/*
+ * INET         An implementation of the TCP/IP protocol suite for the LINUX
+ *              operating system.  INET is implemented using the  BSD Socket
+ *              interface as the means of communication with the user level.
+ *
+ *              Definitions for the TCP protocol sk_state field.
+ *
+ *              This program is free software; you can redistribute it and/or
+ *              modify it under the terms of the GNU General Public License
+ *              as published by the Free Software Foundation; either version
+ *              2 of the License, or (at your option) any later version.
+ */
+#ifndef _LINUX_TCP_STATES_H
+#define _LINUX_TCP_STATES_H
+
+enum {
+        TCP_ESTABLISHED = 1,
+        TCP_SYN_SENT,
+        TCP_SYN_RECV,
+        TCP_FIN_WAIT1,
+        TCP_FIN_WAIT2,
+        TCP_TIME_WAIT,
+        TCP_CLOSE,
+        TCP_CLOSE_WAIT,
+        TCP_LAST_ACK,
+        TCP_LISTEN,
+        TCP_CLOSING,    /* Now a valid state */
+
+        TCP_MAX_STATES  /* Leave at the end! */
+};
+
+#define TCP_STATE_MASK  0xF
+
+#endif  /* _LINUX_TCP_STATES_H */
diff --git a/include/net/udp.h b/include/net/udp.h
index ac229b761dbc..107b9d791a1f 100644
--- a/include/net/udp.h
+++ b/include/net/udp.h
@@ -94,6 +94,11 @@ struct udp_iter_state {
         struct seq_operations   seq_ops;
 };
 
+#ifdef CONFIG_PROC_FS
 extern int udp_proc_register(struct udp_seq_afinfo *afinfo);
 extern void udp_proc_unregister(struct udp_seq_afinfo *afinfo);
+
+extern int  udp4_proc_init(void);
+extern void udp4_proc_exit(void);
+#endif
 #endif  /* _UDP_H */
diff --git a/include/net/x25.h b/include/net/x25.h
index 7a1ba5bbb868..fee62ff8c194 100644
--- a/include/net/x25.h
+++ b/include/net/x25.h
@@ -79,6 +79,8 @@ enum {
 #define X25_DEFAULT_PACKET_SIZE X25_PS128               /* Default Packet Size */
 #define X25_DEFAULT_THROUGHPUT  0x0A                    /* Deafult Throughput */
 #define X25_DEFAULT_REVERSE     0x00                    /* Default Reverse Charging */
+#define X25_DENY_ACCPT_APPRV   0x01                     /* Default value */
+#define X25_ALLOW_ACCPT_APPRV  0x00                     /* Control enabled */
 
 #define X25_SMODULUS            8
 #define X25_EMODULUS            128
@@ -94,7 +96,7 @@ enum {
 #define X25_FAC_CLASS_C         0x80
 #define X25_FAC_CLASS_D         0xC0
 
-#define X25_FAC_REVERSE         0x01
+#define X25_FAC_REVERSE         0x01                    /* also fast select */
 #define X25_FAC_THROUGHPUT      0x02
 #define X25_FAC_PACKET_SIZE     0x42
 #define X25_FAC_WINDOW_SIZE     0x43
@@ -134,8 +136,8 @@ struct x25_sock {
         struct sock             sk;
         struct x25_address      source_addr, dest_addr;
         struct x25_neigh        *neighbour;
-        unsigned int            lci;
-        unsigned char           state, condition, qbitincl, intflag;
+        unsigned int            lci, cudmatchlength;
+        unsigned char           state, condition, qbitincl, intflag, accptapprv;
         unsigned short          vs, vr, va, vl;
         unsigned long           t2, t21, t22, t23;
         unsigned short          fraglen;
@@ -173,7 +175,7 @@ extern void x25_kill_by_neigh(struct x25_neigh *);
 
 /* x25_dev.c */
 extern void x25_send_frame(struct sk_buff *, struct x25_neigh *);
-extern int  x25_lapb_receive_frame(struct sk_buff *, struct net_device *, struct packet_type *);
+extern int  x25_lapb_receive_frame(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);
 extern void x25_establish_link(struct x25_neigh *);
 extern void x25_terminate_link(struct x25_neigh *);
 
@@ -242,7 +244,6 @@ extern int  x25_validate_nr(struct sock *, unsigned short);
 extern void x25_write_internal(struct sock *, int);
 extern int  x25_decode(struct sock *, struct sk_buff *, int *, int *, int *, int *, int *);
 extern void x25_disconnect(struct sock *, int, unsigned char, unsigned char);
-extern int x25_check_calluserdata(struct x25_calluserdata *,struct x25_calluserdata *);
 
 /* x25_timer.c */
 extern void x25_start_heartbeat(struct sock *);
diff --git a/include/net/x25device.h b/include/net/x25device.h
index cf36a20ea3c5..1a318374faef 100644
--- a/include/net/x25device.h
+++ b/include/net/x25device.h
@@ -5,11 +5,9 @@
 #include <linux/if_packet.h>
 #include <linux/skbuff.h>
 
-static inline unsigned short x25_type_trans(struct sk_buff *skb,
-                                            struct net_device *dev)
+static inline __be16 x25_type_trans(struct sk_buff *skb, struct net_device *dev)
 {
         skb->mac.raw = skb->data;
-        skb->input_dev = skb->dev = dev;
         skb->pkt_type = PACKET_HOST;
         
         return htons(ETH_P_X25);
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index d675836ba6c3..a9d0d8c5dfbf 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -158,6 +158,20 @@ enum {
         XFRM_STATE_DEAD
 };
 
+/* callback structure passed from either netlink or pfkey */
+struct km_event
+{
+        union {
+                u32 hard;
+                u32 proto;
+                u32 byid;
+        } data;
+
+        u32     seq;
+        u32     pid;
+        u32     event;
+};
+
 struct xfrm_type;
 struct xfrm_dst;
 struct xfrm_policy_afinfo {
@@ -179,6 +193,8 @@ struct xfrm_policy_afinfo {
 
 extern int xfrm_policy_register_afinfo(struct xfrm_policy_afinfo *afinfo);
 extern int xfrm_policy_unregister_afinfo(struct xfrm_policy_afinfo *afinfo);
+extern void km_policy_notify(struct xfrm_policy *xp, int dir, struct km_event *c);
+extern void km_state_notify(struct xfrm_state *x, struct km_event *c);
 
 #define XFRM_ACQ_EXPIRES        30
 
@@ -188,6 +204,7 @@ struct xfrm_state_afinfo {
         rwlock_t                lock;
         struct list_head        *state_bydst;
         struct list_head        *state_byspi;
+        int                     (*init_flags)(struct xfrm_state *x);
         void                    (*init_tempsel)(struct xfrm_state *x, struct flowi *fl,
                                                 struct xfrm_tmpl *tmpl,
                                                 xfrm_address_t *daddr, xfrm_address_t *saddr);
@@ -209,7 +226,7 @@ struct xfrm_type
         struct module           *owner;
         __u8                    proto;
 
-        int                     (*init_state)(struct xfrm_state *x, void *args);
+        int                     (*init_state)(struct xfrm_state *x);
         void                    (*destructor)(struct xfrm_state *);
         int                     (*input)(struct xfrm_state *, struct xfrm_decap_state *, struct sk_buff *skb);
         int                     (*post_input)(struct xfrm_state *, struct xfrm_decap_state *, struct sk_buff *skb);
@@ -290,11 +307,11 @@ struct xfrm_mgr
 {
         struct list_head        list;
         char                    *id;
-        int                     (*notify)(struct xfrm_state *x, int event);
+        int                     (*notify)(struct xfrm_state *x, struct km_event *c);
         int                     (*acquire)(struct xfrm_state *x, struct xfrm_tmpl *, struct xfrm_policy *xp, int dir);
         struct xfrm_policy      *(*compile_policy)(u16 family, int opt, u8 *data, int len, int *dir);
         int                     (*new_mapping)(struct xfrm_state *x, xfrm_address_t *ipaddr, u16 sport);
-        int                     (*notify_policy)(struct xfrm_policy *x, int dir, int event);
+        int                     (*notify_policy)(struct xfrm_policy *x, int dir, struct km_event *c);
 };
 
 extern int xfrm_register_km(struct xfrm_mgr *km);
@@ -656,7 +673,7 @@ static inline int xfrm_sk_clone_policy(struct sock *sk)
         return 0;
 }
 
-extern void xfrm_policy_delete(struct xfrm_policy *pol, int dir);
+extern int xfrm_policy_delete(struct xfrm_policy *pol, int dir);
 
 static inline void xfrm_sk_free_policy(struct sock *sk)
 {
@@ -786,7 +803,7 @@ struct xfrm_algo_desc {
 /* XFRM tunnel handlers.  */
 struct xfrm_tunnel {
         int (*handler)(struct sk_buff *skb);
-        void (*err_handler)(struct sk_buff *skb, void *info);
+        void (*err_handler)(struct sk_buff *skb, __u32 info);
 };
 
 struct xfrm6_tunnel {
@@ -801,7 +818,6 @@ extern void xfrm6_init(void);
 extern void xfrm6_fini(void);
 extern void xfrm_state_init(void);
 extern void xfrm4_state_init(void);
-extern void xfrm4_state_fini(void);
 extern void xfrm6_state_init(void);
 extern void xfrm6_state_fini(void);
 
@@ -817,12 +833,13 @@ extern int xfrm_state_add(struct xfrm_state *x);
 extern int xfrm_state_update(struct xfrm_state *x);
 extern struct xfrm_state *xfrm_state_lookup(xfrm_address_t *daddr, u32 spi, u8 proto, unsigned short family);
 extern struct xfrm_state *xfrm_find_acq_byseq(u32 seq);
-extern void xfrm_state_delete(struct xfrm_state *x);
+extern int xfrm_state_delete(struct xfrm_state *x);
 extern void xfrm_state_flush(u8 proto);
 extern int xfrm_replay_check(struct xfrm_state *x, u32 seq);
 extern void xfrm_replay_advance(struct xfrm_state *x, u32 seq);
 extern int xfrm_state_check(struct xfrm_state *x, struct sk_buff *skb);
 extern int xfrm_state_mtu(struct xfrm_state *x, int mtu);
+extern int xfrm_init_state(struct xfrm_state *x);
 extern int xfrm4_rcv(struct sk_buff *skb);
 extern int xfrm4_output(struct sk_buff *skb);
 extern int xfrm4_tunnel_register(struct xfrm_tunnel *handler);
diff --git a/include/pcmcia/ciscode.h b/include/pcmcia/ciscode.h
index 2000b43ece91..da19c297dd65 100644
--- a/include/pcmcia/ciscode.h
+++ b/include/pcmcia/ciscode.h
@@ -112,6 +112,8 @@
 
 #define MANFID_TDK                      0x0105
 #define PRODID_TDK_CF010                0x0900
+#define PRODID_TDK_NP9610               0x0d0a
+#define PRODID_TDK_MN3200               0x0e0a
 #define PRODID_TDK_GN3410               0x4815
 
 #define MANFID_TOSHIBA                  0x0098
diff --git a/include/pcmcia/cs.h b/include/pcmcia/cs.h
index 8d8643adc786..2cab39f49eb2 100644
--- a/include/pcmcia/cs.h
+++ b/include/pcmcia/cs.h
@@ -68,21 +68,9 @@ typedef struct adjust_t {
 #define RES_ALLOCATED                   0x20
 #define RES_REMOVED                     0x40
 
-typedef struct servinfo_t {
-    char        Signature[2];
-    u_int       Count;
-    u_int       Revision;
-    u_int       CSLevel;
-    char        *VendorString;
-} servinfo_t;
-
 typedef struct event_callback_args_t {
-    client_handle_t client_handle;
-    void        *info;
-    void        *mtdrequest;
-    void        *buffer;
-    void        *misc;
-    void        *client_data;
+        struct pcmcia_device    *client_handle;
+        void                    *client_data;
 } event_callback_args_t;
 
 /* for GetConfigurationInfo */
@@ -393,31 +381,29 @@ enum service {
 
 struct pcmcia_socket;
 
-int pcmcia_access_configuration_register(client_handle_t handle, conf_reg_t *reg);
-int pcmcia_deregister_client(client_handle_t handle);
-int pcmcia_get_configuration_info(client_handle_t handle, config_info_t *config);
-int pcmcia_get_card_services_info(servinfo_t *info);
+int pcmcia_access_configuration_register(struct pcmcia_device *p_dev, conf_reg_t *reg);
+int pcmcia_deregister_client(struct pcmcia_device *p_dev);
+int pcmcia_get_configuration_info(struct pcmcia_device *p_dev, config_info_t *config);
 int pcmcia_get_first_window(window_handle_t *win, win_req_t *req);
 int pcmcia_get_next_window(window_handle_t *win, win_req_t *req);
-int pcmcia_get_status(client_handle_t handle, cs_status_t *status);
+int pcmcia_get_status(struct pcmcia_device *p_dev, cs_status_t *status);
 int pcmcia_get_mem_page(window_handle_t win, memreq_t *req);
 int pcmcia_map_mem_page(window_handle_t win, memreq_t *req);
-int pcmcia_modify_configuration(client_handle_t handle, modconf_t *mod);
+int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod);
 int pcmcia_register_client(client_handle_t *handle, client_reg_t *req);
-int pcmcia_release_configuration(client_handle_t handle);
-int pcmcia_release_io(client_handle_t handle, io_req_t *req);
-int pcmcia_release_irq(client_handle_t handle, irq_req_t *req);
+int pcmcia_release_configuration(struct pcmcia_device *p_dev);
+int pcmcia_release_io(struct pcmcia_device *p_dev, io_req_t *req);
+int pcmcia_release_irq(struct pcmcia_device *p_dev, irq_req_t *req);
 int pcmcia_release_window(window_handle_t win);
-int pcmcia_request_configuration(client_handle_t handle, config_req_t *req);
-int pcmcia_request_io(client_handle_t handle, io_req_t *req);
-int pcmcia_request_irq(client_handle_t handle, irq_req_t *req);
-int pcmcia_request_window(client_handle_t *handle, win_req_t *req, window_handle_t *wh);
-int pcmcia_reset_card(client_handle_t handle, client_req_t *req);
+int pcmcia_request_configuration(struct pcmcia_device *p_dev, config_req_t *req);
+int pcmcia_request_io(struct pcmcia_device *p_dev, io_req_t *req);
+int pcmcia_request_irq(struct pcmcia_device *p_dev, irq_req_t *req);
+int pcmcia_request_window(struct pcmcia_device **p_dev, win_req_t *req, window_handle_t *wh);
+int pcmcia_reset_card(struct pcmcia_device *p_dev, client_req_t *req);
 int pcmcia_suspend_card(struct pcmcia_socket *skt);
 int pcmcia_resume_card(struct pcmcia_socket *skt);
 int pcmcia_eject_card(struct pcmcia_socket *skt);
 int pcmcia_insert_card(struct pcmcia_socket *skt);
-int pcmcia_report_error(client_handle_t handle, error_info_t *err);
 
 struct pcmcia_socket * pcmcia_get_socket(struct pcmcia_socket *skt);
 void pcmcia_put_socket(struct pcmcia_socket *skt);
diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h
index 7881d40aac8d..c1d1629fcd27 100644
--- a/include/pcmcia/cs_types.h
+++ b/include/pcmcia/cs_types.h
@@ -34,8 +34,8 @@ typedef u_int	event_t;
 typedef u_char  cisdata_t;
 typedef u_short page_t;
 
-struct client_t;
-typedef struct client_t *client_handle_t;
+struct pcmcia_device;
+typedef struct pcmcia_device *client_handle_t;
 
 struct window_t;
 typedef struct window_t *window_handle_t;
diff --git a/include/pcmcia/device_id.h b/include/pcmcia/device_id.h
new file mode 100644
index 000000000000..346d81ece287
--- /dev/null
+++ b/include/pcmcia/device_id.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (2003-2004)        Dominik Brodowski <linux@brodo.de>
+ *                              David Woodhouse
+ *
+ * License: GPL v2
+ */
+
+#define PCMCIA_DEVICE_MANF_CARD(manf, card) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_MANF_ID| \
+                        PCMCIA_DEV_ID_MATCH_CARD_ID, \
+        .manf_id = (manf), \
+        .card_id = (card), }
+
+#define PCMCIA_DEVICE_FUNC_ID(func) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_FUNC_ID, \
+        .func_id = (func), }
+
+#define PCMCIA_DEVICE_PROD_ID1(v1, vh1) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1, \
+        .prod_id = { (v1), NULL, NULL, NULL }, \
+        .prod_id_hash = { (vh1), 0, 0, 0 }, }
+
+#define PCMCIA_DEVICE_PROD_ID2(v2, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID2, \
+        .prod_id = { NULL, (v2), NULL, NULL },  \
+        .prod_id_hash = { 0, (vh2), 0, 0 }, }
+
+#define PCMCIA_DEVICE_PROD_ID12(v1, v2, vh1, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 }, }
+
+#define PCMCIA_DEVICE_PROD_ID13(v1, v3, vh1, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3, \
+        .prod_id = { (v1), NULL, (v3), NULL }, \
+        .prod_id_hash = { (vh1), 0, (vh3), 0 }, }
+
+#define PCMCIA_DEVICE_PROD_ID14(v1, v4, vh1, vh4) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID4, \
+        .prod_id = { (v1), NULL, NULL, (v4) }, \
+        .prod_id_hash = { (vh1), 0, 0, (vh4) }, }
+
+#define PCMCIA_DEVICE_PROD_ID123(v1, v2, v3, vh1, vh2, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3, \
+        .prod_id = { (v1), (v2), (v3), NULL },\
+        .prod_id_hash = { (vh1), (vh2), (vh3), 0 }, }
+
+#define PCMCIA_DEVICE_PROD_ID124(v1, v2, v4, vh1, vh2, vh4) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID4, \
+        .prod_id = { (v1), (v2), NULL, (v4) }, \
+        .prod_id_hash = { (vh1), (vh2), 0, (vh4) }, }
+
+#define PCMCIA_DEVICE_PROD_ID134(v1, v3, v4, vh1, vh3, vh4) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID4, \
+        .prod_id = { (v1), NULL, (v3), (v4) }, \
+        .prod_id_hash = { (vh1), 0, (vh3), (vh4) }, }
+
+#define PCMCIA_DEVICE_PROD_ID1234(v1, v2, v3, v4, vh1, vh2, vh3, vh4) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID4, \
+        .prod_id = { (v1), (v2), (v3), (v4) }, \
+        .prod_id_hash = { (vh1), (vh2), (vh3), (vh4) }, }
+
+
+/* multi-function devices */
+
+#define PCMCIA_MFC_DEVICE_MANF_CARD(mfc, manf, card) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_MANF_ID| \
+                        PCMCIA_DEV_ID_MATCH_CARD_ID| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .manf_id = (manf), \
+        .card_id = (card), \
+        .function = (mfc), }
+
+#define PCMCIA_MFC_DEVICE_PROD_ID1(mfc, v1, vh1) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { (v1), NULL, NULL, NULL }, \
+        .prod_id_hash = { (vh1), 0, 0, 0 }, \
+        .function = (mfc), }
+
+#define PCMCIA_MFC_DEVICE_PROD_ID2(mfc, v2, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { NULL, (v2), NULL, NULL },  \
+        .prod_id_hash = { 0, (vh2), 0, 0 }, \
+        .function = (mfc), }
+
+#define PCMCIA_MFC_DEVICE_PROD_ID12(mfc, v1, v2, vh1, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 }, \
+        .function = (mfc), }
+
+#define PCMCIA_MFC_DEVICE_PROD_ID13(mfc, v1, v3, vh1, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { (v1), NULL, (v3), NULL }, \
+        .prod_id_hash = { (vh1), 0, (vh3), 0 }, \
+        .function = (mfc), }
+
+#define PCMCIA_MFC_DEVICE_PROD_ID123(mfc, v1, v2, v3, vh1, vh2, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { (v1), (v2), (v3), NULL },\
+        .prod_id_hash = { (vh1), (vh2), (vh3), 0 }, \
+        .function = (mfc), }
+
+/* pseudo multi-function devices */
+
+#define PCMCIA_PFC_DEVICE_MANF_CARD(mfc, manf, card) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_MANF_ID| \
+                        PCMCIA_DEV_ID_MATCH_CARD_ID| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .manf_id = (manf), \
+        .card_id = (card), \
+        .device_no = (mfc), }
+
+#define PCMCIA_PFC_DEVICE_PROD_ID1(mfc, v1, vh1) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { (v1), NULL, NULL, NULL }, \
+        .prod_id_hash = { (vh1), 0, 0, 0 }, \
+        .device_no = (mfc), }
+
+#define PCMCIA_PFC_DEVICE_PROD_ID2(mfc, v2, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { NULL, (v2), NULL, NULL },  \
+        .prod_id_hash = { 0, (vh2), 0, 0 }, \
+        .device_no = (mfc), }
+
+#define PCMCIA_PFC_DEVICE_PROD_ID12(mfc, v1, v2, vh1, vh2) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 }, \
+        .device_no = (mfc), }
+
+#define PCMCIA_PFC_DEVICE_PROD_ID13(mfc, v1, v3, vh1, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { (v1), NULL, (v3), NULL }, \
+        .prod_id_hash = { (vh1), 0, (vh3), 0 }, \
+        .device_no = (mfc), }
+
+#define PCMCIA_PFC_DEVICE_PROD_ID123(mfc, v1, v2, v3, vh1, vh2, vh3) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { (v1), (v2), (v3), NULL },\
+        .prod_id_hash = { (vh1), (vh2), (vh3), 0 }, \
+        .device_no = (mfc), }
+
+/* cards needing a CIS override */
+
+#define PCMCIA_DEVICE_CIS_MANF_CARD(manf, card, _cisfile) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_MANF_ID| \
+                        PCMCIA_DEV_ID_MATCH_CARD_ID, \
+        .manf_id = (manf), \
+        .card_id = (card), \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_DEVICE_CIS_PROD_ID12(v1, v2, vh1, vh2, _cisfile) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 }, \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_DEVICE_CIS_PROD_ID123(v1, v2, v3, vh1, vh2, vh3, _cisfile) { \
+        .match_flags = PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID3, \
+        .prod_id = { (v1), (v2), (v3), NULL },\
+        .prod_id_hash = { (vh1), (vh2), (vh3), 0 }, \
+        .cisfile = (_cisfile)}
+
+
+#define PCMCIA_DEVICE_CIS_PROD_ID2(v2, vh2, _cisfile) { \
+        .match_flags =  PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2, \
+        .prod_id = { NULL, (v2), NULL, NULL },  \
+        .prod_id_hash = { 0, (vh2), 0, 0 }, \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_PFC_DEVICE_CIS_PROD_ID12(mfc, v1, v2, vh1, vh2, _cisfile) { \
+        .match_flags =  PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_DEVICE_NO, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 },\
+        .device_no = (mfc), \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_MFC_DEVICE_CIS_MANF_CARD(mfc, manf, card, _cisfile) { \
+        .match_flags =  PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_MANF_ID| \
+                        PCMCIA_DEV_ID_MATCH_CARD_ID| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .manf_id = (manf), \
+        .card_id = (card), \
+        .function = (mfc), \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_MFC_DEVICE_CIS_PROD_ID12(mfc, v1, v2, vh1, vh2, _cisfile) { \
+        .match_flags =  PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID1| \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID2| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { (v1), (v2), NULL, NULL }, \
+        .prod_id_hash = { (vh1), (vh2), 0, 0 }, \
+        .function = (mfc), \
+        .cisfile = (_cisfile)}
+
+#define PCMCIA_MFC_DEVICE_CIS_PROD_ID4(mfc, v4, vh4, _cisfile) { \
+        .match_flags =  PCMCIA_DEV_ID_MATCH_FAKE_CIS | \
+                        PCMCIA_DEV_ID_MATCH_PROD_ID4| \
+                        PCMCIA_DEV_ID_MATCH_FUNCTION, \
+        .prod_id = { NULL, NULL, NULL, (v4) }, \
+        .prod_id_hash = { 0, 0, 0, (vh4) }, \
+        .function = (mfc), \
+        .cisfile = (_cisfile)}
+
+
+#define PCMCIA_DEVICE_NULL { .match_flags = 0, }
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index 312fd958c901..b707a603351b 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -16,8 +16,13 @@
 #ifndef _LINUX_DS_H
 #define _LINUX_DS_H
 
+#ifdef __KERNEL__
+#include <linux/mod_devicetable.h>
+#endif
+
 #include <pcmcia/bulkmem.h>
 #include <pcmcia/cs_types.h>
+#include <pcmcia/device_id.h>
 
 typedef struct tuple_parse_t {
     tuple_t             tuple;
@@ -47,7 +52,6 @@ typedef struct mtd_info_t {
 } mtd_info_t;
 
 typedef union ds_ioctl_arg_t {
-    servinfo_t          servinfo;
     adjust_t            adjust;
     config_info_t       config;
     tuple_t             tuple;
@@ -63,7 +67,6 @@ typedef union ds_ioctl_arg_t {
     cisdump_t           cisdump;
 } ds_ioctl_arg_t;
 
-#define DS_GET_CARD_SERVICES_INFO       _IOR ('d', 1, servinfo_t)
 #define DS_ADJUST_RESOURCE_INFO         _IOWR('d', 2, adjust_t)
 #define DS_GET_CONFIGURATION_INFO       _IOWR('d', 3, config_info_t)
 #define DS_GET_FIRST_TUPLE              _IOWR('d', 4, tuple_t)
@@ -129,12 +132,13 @@ typedef struct dev_link_t {
 
 struct pcmcia_socket;
 
-extern struct bus_type pcmcia_bus_type;
-
 struct pcmcia_driver {
         dev_link_t              *(*attach)(void);
+        int (*event)            (event_t event, int priority,
+                                 event_callback_args_t *);
         void                    (*detach)(dev_link_t *);
         struct module           *owner;
+        struct pcmcia_device_id *id_table;
         struct device_driver    drv;
 };
 
@@ -158,22 +162,16 @@ struct pcmcia_device {
         /* deprecated, a cleaned up version will be moved into this
            struct soon */
         dev_link_t              *instance;
-        struct client_t {
-                u_short                 client_magic;
-                struct pcmcia_socket    *Socket;
-                u_char                  Function;
-                u_int                   state;
-                event_t                 EventMask;
-                int (*event_handler)    (event_t event, int priority,
-                                         event_callback_args_t *);
-                event_callback_args_t   event_callback_args;
-        }                       client;
+        event_callback_args_t   event_callback_args;
+        u_int                   state;
 
         /* information about this device */
         u8                      has_manf_id:1;
         u8                      has_card_id:1;
         u8                      has_func_id:1;
-        u8                      reserved:5;
+
+        u8                      allow_func_id_match:1;
+        u8                      reserved:4;
 
         u8                      func_id;
         u16                     manf_id;
@@ -190,8 +188,8 @@ struct pcmcia_device {
 #define to_pcmcia_dev(n) container_of(n, struct pcmcia_device, dev)
 #define to_pcmcia_drv(n) container_of(n, struct pcmcia_driver, drv)
 
-#define handle_to_pdev(handle) container_of(handle, struct pcmcia_device, client);
-#define handle_to_dev(handle) ((container_of(handle, struct pcmcia_device, client))->dev)
+#define handle_to_pdev(handle) (handle)
+#define handle_to_dev(handle) (handle->dev)
 
 /* error reporting */
 void cs_error(client_handle_t handle, int func, int ret);
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index 6d3413a56708..0f7aacc33fe9 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -15,10 +15,12 @@
 #ifndef _LINUX_SS_H
 #define _LINUX_SS_H
 
+#include <linux/config.h>
+#include <linux/device.h>
+
 #include <pcmcia/cs_types.h>
 #include <pcmcia/cs.h>
 #include <pcmcia/bulkmem.h>
-#include <linux/device.h>
 
 /* Definitions for card status flags for GetStatus */
 #define SS_WRPROT       0x0001
@@ -77,6 +79,11 @@ extern socket_state_t dead_socket;
 /* Use this just for bridge windows */
 #define MAP_IOSPACE     0x20
 
+/* power hook operations */
+#define HOOK_POWER_PRE  0x01
+#define HOOK_POWER_POST 0x02
+
+
 typedef struct pccard_io_map {
     u_char      map;
     u_char      flags;
@@ -166,7 +173,7 @@ typedef struct window_t {
 
 struct config_t;
 struct pcmcia_callback;
-
+struct user_info_t;
 
 struct pcmcia_socket {
         struct module                   *owner;
@@ -211,8 +218,9 @@ struct pcmcia_socket {
 
         /* is set to one if resource setup is done using adjust_resource_info() */
         u8                              resource_setup_old:1;
+        u8                              resource_setup_new:1;
 
-        u8                              reserved:6;
+        u8                              reserved:5;
 
         /* socket operations */
         struct pccard_operations *      ops;
@@ -222,6 +230,9 @@ struct pcmcia_socket {
         /* Zoom video behaviour is so chip specific its not worth adding
            this to _ops */
         void                            (*zoom_video)(struct pcmcia_socket *, int);
+
+        /* so is power hook */
+        int (*power_hook)(struct pcmcia_socket *sock, int operation);
                            
         /* state thread */
         struct semaphore                skt_sem;        /* protects socket h/w state */
@@ -233,9 +244,32 @@ struct pcmcia_socket {
         unsigned int                    thread_events;
 
         /* pcmcia (16-bit) */
-        struct pcmcia_bus_socket        *pcmcia;
         struct pcmcia_callback          *callback;
 
+#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
+        struct list_head                devices_list;   /*  PCMCIA devices */
+        u8                              device_count;   /* the number of devices, used
+                                                         * only internally and subject
+                                                         * to incorrectness and change */
+
+        struct {
+                u8                      present:1,      /* PCMCIA card is present in socket */
+                                        busy:1,         /* "master" ioctl is used */
+                                        dead:1,         /* pcmcia module is being unloaded */
+                                        device_add_pending:1, /* a pseudo-multifunction-device
+                                                               * add event is pending */
+                                        reserved:4;
+        }                               pcmcia_state;
+
+        struct work_struct              device_add;     /* for adding further pseudo-multifunction
+                                                         * devices */
+
+#ifdef CONFIG_PCMCIA_IOCTL
+        struct user_info_t              *user;
+        wait_queue_head_t               queue;
+#endif
+#endif
+
         /* cardbus (32-bit) */
 #ifdef CONFIG_CARDBUS
         struct resource *               cb_cis_res;
diff --git a/include/pcmcia/version.h b/include/pcmcia/version.h
index eb88263fc8d5..5ad9c5e198b6 100644
--- a/include/pcmcia/version.h
+++ b/include/pcmcia/version.h
@@ -1,4 +1,3 @@
 /* version.h 1.94 2000/10/03 17:55:48 (David Hinds) */
 
-#define CS_RELEASE "3.1.22"
-#define CS_RELEASE_CODE 0x3116
+/* This file will be removed, please don't include it */
diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h
new file mode 100644
index 000000000000..5bf9834f7dca
--- /dev/null
+++ b/include/rdma/ib_cache.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Intel Corporation. All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_cache.h 1349 2004-12-16 21:09:43Z roland $
+ */
+
+#ifndef _IB_CACHE_H
+#define _IB_CACHE_H
+
+#include <rdma/ib_verbs.h>
+
+/**
+ * ib_get_cached_gid - Returns a cached GID table entry
+ * @device: The device to query.
+ * @port_num: The port number of the device to query.
+ * @index: The index into the cached GID table to query.
+ * @gid: The GID value found at the specified index.
+ *
+ * ib_get_cached_gid() fetches the specified GID table entry stored in
+ * the local software cache.
+ */
+int ib_get_cached_gid(struct ib_device    *device,
+                      u8                   port_num,
+                      int                  index,
+                      union ib_gid        *gid);
+
+/**
+ * ib_find_cached_gid - Returns the port number and GID table index where
+ *   a specified GID value occurs.
+ * @device: The device to query.
+ * @gid: The GID value to search for.
+ * @port_num: The port number of the device where the GID value was found.
+ * @index: The index into the cached GID table where the GID was found.  This
+ *   parameter may be NULL.
+ *
+ * ib_find_cached_gid() searches for the specified GID value in
+ * the local software cache.
+ */
+int ib_find_cached_gid(struct ib_device *device,
+                       union ib_gid     *gid,
+                       u8               *port_num,
+                       u16              *index);
+
+/**
+ * ib_get_cached_pkey - Returns a cached PKey table entry
+ * @device: The device to query.
+ * @port_num: The port number of the device to query.
+ * @index: The index into the cached PKey table to query.
+ * @pkey: The PKey value found at the specified index.
+ *
+ * ib_get_cached_pkey() fetches the specified PKey table entry stored in
+ * the local software cache.
+ */
+int ib_get_cached_pkey(struct ib_device    *device_handle,
+                       u8                   port_num,
+                       int                  index,
+                       u16                 *pkey);
+
+/**
+ * ib_find_cached_pkey - Returns the PKey table index where a specified
+ *   PKey value occurs.
+ * @device: The device to query.
+ * @port_num: The port number of the device to search for the PKey.
+ * @pkey: The PKey value to search for.
+ * @index: The index into the cached PKey table where the PKey was found.
+ *
+ * ib_find_cached_pkey() searches the specified PKey table in
+ * the local software cache.
+ */
+int ib_find_cached_pkey(struct ib_device    *device,
+                        u8                   port_num,
+                        u16                  pkey,
+                        u16                 *index);
+
+#endif /* _IB_CACHE_H */
diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h
new file mode 100644
index 000000000000..77fe9039209b
--- /dev/null
+++ b/include/rdma/ib_cm.h
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $
+ */
+#if !defined(IB_CM_H)
+#define IB_CM_H
+
+#include <rdma/ib_mad.h>
+#include <rdma/ib_sa.h>
+
+enum ib_cm_state {
+        IB_CM_IDLE,
+        IB_CM_LISTEN,
+        IB_CM_REQ_SENT,
+        IB_CM_REQ_RCVD,
+        IB_CM_MRA_REQ_SENT,
+        IB_CM_MRA_REQ_RCVD,
+        IB_CM_REP_SENT,
+        IB_CM_REP_RCVD,
+        IB_CM_MRA_REP_SENT,
+        IB_CM_MRA_REP_RCVD,
+        IB_CM_ESTABLISHED,
+        IB_CM_DREQ_SENT,
+        IB_CM_DREQ_RCVD,
+        IB_CM_TIMEWAIT,
+        IB_CM_SIDR_REQ_SENT,
+        IB_CM_SIDR_REQ_RCVD
+};
+
+enum ib_cm_lap_state {
+        IB_CM_LAP_IDLE,
+        IB_CM_LAP_SENT,
+        IB_CM_LAP_RCVD,
+        IB_CM_MRA_LAP_SENT,
+        IB_CM_MRA_LAP_RCVD,
+};
+
+enum ib_cm_event_type {
+        IB_CM_REQ_ERROR,
+        IB_CM_REQ_RECEIVED,
+        IB_CM_REP_ERROR,
+        IB_CM_REP_RECEIVED,
+        IB_CM_RTU_RECEIVED,
+        IB_CM_USER_ESTABLISHED,
+        IB_CM_DREQ_ERROR,
+        IB_CM_DREQ_RECEIVED,
+        IB_CM_DREP_RECEIVED,
+        IB_CM_TIMEWAIT_EXIT,
+        IB_CM_MRA_RECEIVED,
+        IB_CM_REJ_RECEIVED,
+        IB_CM_LAP_ERROR,
+        IB_CM_LAP_RECEIVED,
+        IB_CM_APR_RECEIVED,
+        IB_CM_SIDR_REQ_ERROR,
+        IB_CM_SIDR_REQ_RECEIVED,
+        IB_CM_SIDR_REP_RECEIVED
+};
+
+enum ib_cm_data_size {
+        IB_CM_REQ_PRIVATE_DATA_SIZE      = 92,
+        IB_CM_MRA_PRIVATE_DATA_SIZE      = 222,
+        IB_CM_REJ_PRIVATE_DATA_SIZE      = 148,
+        IB_CM_REP_PRIVATE_DATA_SIZE      = 196,
+        IB_CM_RTU_PRIVATE_DATA_SIZE      = 224,
+        IB_CM_DREQ_PRIVATE_DATA_SIZE     = 220,
+        IB_CM_DREP_PRIVATE_DATA_SIZE     = 224,
+        IB_CM_REJ_ARI_LENGTH             = 72,
+        IB_CM_LAP_PRIVATE_DATA_SIZE      = 168,
+        IB_CM_APR_PRIVATE_DATA_SIZE      = 148,
+        IB_CM_APR_INFO_LENGTH            = 72,
+        IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216,
+        IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136,
+        IB_CM_SIDR_REP_INFO_LENGTH       = 72
+};
+
+struct ib_cm_id;
+
+struct ib_cm_req_event_param {
+        struct ib_cm_id         *listen_id;
+        struct ib_device        *device;
+        u8                      port;
+
+        struct ib_sa_path_rec   *primary_path;
+        struct ib_sa_path_rec   *alternate_path;
+
+        __be64                  remote_ca_guid;
+        u32                     remote_qkey;
+        u32                     remote_qpn;
+        enum ib_qp_type         qp_type;
+
+        u32                     starting_psn;
+        u8                      responder_resources;
+        u8                      initiator_depth;
+        unsigned int            local_cm_response_timeout:5;
+        unsigned int            flow_control:1;
+        unsigned int            remote_cm_response_timeout:5;
+        unsigned int            retry_count:3;
+        unsigned int            rnr_retry_count:3;
+        unsigned int            srq:1;
+};
+
+struct ib_cm_rep_event_param {
+        __be64                  remote_ca_guid;
+        u32                     remote_qkey;
+        u32                     remote_qpn;
+        u32                     starting_psn;
+        u8                      responder_resources;
+        u8                      initiator_depth;
+        unsigned int            target_ack_delay:5;
+        unsigned int            failover_accepted:2;
+        unsigned int            flow_control:1;
+        unsigned int            rnr_retry_count:3;
+        unsigned int            srq:1;
+};
+
+enum ib_cm_rej_reason {
+        IB_CM_REJ_NO_QP                         = 1,
+        IB_CM_REJ_NO_EEC                        = 2,
+        IB_CM_REJ_NO_RESOURCES                  = 3,
+        IB_CM_REJ_TIMEOUT                       = 4,
+        IB_CM_REJ_UNSUPPORTED                   = 5,
+        IB_CM_REJ_INVALID_COMM_ID               = 6,
+        IB_CM_REJ_INVALID_COMM_INSTANCE         = 7,
+        IB_CM_REJ_INVALID_SERVICE_ID            = 8,
+        IB_CM_REJ_INVALID_TRANSPORT_TYPE        = 9,
+        IB_CM_REJ_STALE_CONN                    = 10,
+        IB_CM_REJ_RDC_NOT_EXIST                 = 11,
+        IB_CM_REJ_INVALID_GID                   = 12,
+        IB_CM_REJ_INVALID_LID                   = 13,
+        IB_CM_REJ_INVALID_SL                    = 14,
+        IB_CM_REJ_INVALID_TRAFFIC_CLASS         = 15,
+        IB_CM_REJ_INVALID_HOP_LIMIT             = 16,
+        IB_CM_REJ_INVALID_PACKET_RATE           = 17,
+        IB_CM_REJ_INVALID_ALT_GID               = 18,
+        IB_CM_REJ_INVALID_ALT_LID               = 19,
+        IB_CM_REJ_INVALID_ALT_SL                = 20,
+        IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS     = 21,
+        IB_CM_REJ_INVALID_ALT_HOP_LIMIT         = 22,
+        IB_CM_REJ_INVALID_ALT_PACKET_RATE       = 23,
+        IB_CM_REJ_PORT_CM_REDIRECT              = 24,
+        IB_CM_REJ_PORT_REDIRECT                 = 25,
+        IB_CM_REJ_INVALID_MTU                   = 26,
+        IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES   = 27,
+        IB_CM_REJ_CONSUMER_DEFINED              = 28,
+        IB_CM_REJ_INVALID_RNR_RETRY             = 29,
+        IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID       = 30,
+        IB_CM_REJ_INVALID_CLASS_VERSION         = 31,
+        IB_CM_REJ_INVALID_FLOW_LABEL            = 32,
+        IB_CM_REJ_INVALID_ALT_FLOW_LABEL        = 33
+};
+
+struct ib_cm_rej_event_param {
+        enum ib_cm_rej_reason   reason;
+        void                    *ari;
+        u8                      ari_length;
+};
+
+struct ib_cm_mra_event_param {
+        u8      service_timeout;
+};
+
+struct ib_cm_lap_event_param {
+        struct ib_sa_path_rec   *alternate_path;
+};
+
+enum ib_cm_apr_status {
+        IB_CM_APR_SUCCESS,
+        IB_CM_APR_INVALID_COMM_ID,
+        IB_CM_APR_UNSUPPORTED,
+        IB_CM_APR_REJECT,
+        IB_CM_APR_REDIRECT,
+        IB_CM_APR_IS_CURRENT,
+        IB_CM_APR_INVALID_QPN_EECN,
+        IB_CM_APR_INVALID_LID,
+        IB_CM_APR_INVALID_GID,
+        IB_CM_APR_INVALID_FLOW_LABEL,
+        IB_CM_APR_INVALID_TCLASS,
+        IB_CM_APR_INVALID_HOP_LIMIT,
+        IB_CM_APR_INVALID_PACKET_RATE,
+        IB_CM_APR_INVALID_SL
+};
+
+struct ib_cm_apr_event_param {
+        enum ib_cm_apr_status   ap_status;
+        void                    *apr_info;
+        u8                      info_len;
+};
+
+struct ib_cm_sidr_req_event_param {
+        struct ib_cm_id         *listen_id;
+        struct ib_device        *device;
+        u8                      port;
+        u16                     pkey;
+};
+
+enum ib_cm_sidr_status {
+        IB_SIDR_SUCCESS,
+        IB_SIDR_UNSUPPORTED,
+        IB_SIDR_REJECT,
+        IB_SIDR_NO_QP,
+        IB_SIDR_REDIRECT,
+        IB_SIDR_UNSUPPORTED_VERSION
+};
+
+struct ib_cm_sidr_rep_event_param {
+        enum ib_cm_sidr_status  status;
+        u32                     qkey;
+        u32                     qpn;
+        void                    *info;
+        u8                      info_len;
+
+};
+
+struct ib_cm_event {
+        enum ib_cm_event_type   event;
+        union {
+                struct ib_cm_req_event_param    req_rcvd;
+                struct ib_cm_rep_event_param    rep_rcvd;
+                /* No data for RTU received events. */
+                struct ib_cm_rej_event_param    rej_rcvd;
+                struct ib_cm_mra_event_param    mra_rcvd;
+                struct ib_cm_lap_event_param    lap_rcvd;
+                struct ib_cm_apr_event_param    apr_rcvd;
+                /* No data for DREQ/DREP received events. */
+                struct ib_cm_sidr_req_event_param sidr_req_rcvd;
+                struct ib_cm_sidr_rep_event_param sidr_rep_rcvd;
+                enum ib_wc_status               send_status;
+        } param;
+
+        void                    *private_data;
+};
+
+/**
+ * ib_cm_handler - User-defined callback to process communication events.
+ * @cm_id: Communication identifier associated with the reported event.
+ * @event: Information about the communication event.
+ *
+ * IB_CM_REQ_RECEIVED and IB_CM_SIDR_REQ_RECEIVED communication events
+ * generated as a result of listen requests result in the allocation of a
+ * new @cm_id.  The new @cm_id is returned to the user through this callback.
+ * Clients are responsible for destroying the new @cm_id.  For peer-to-peer
+ * IB_CM_REQ_RECEIVED and all other events, the returned @cm_id corresponds
+ * to a user's existing communication identifier.
+ *
+ * Users may not call ib_destroy_cm_id while in the context of this callback;
+ * however, returning a non-zero value instructs the communication manager to
+ * destroy the @cm_id after the callback completes.
+ */
+typedef int (*ib_cm_handler)(struct ib_cm_id *cm_id,
+                             struct ib_cm_event *event);
+
+struct ib_cm_id {
+        ib_cm_handler           cm_handler;
+        void                    *context;
+        __be64                  service_id;
+        __be64                  service_mask;
+        enum ib_cm_state        state;          /* internal CM/debug use */
+        enum ib_cm_lap_state    lap_state;      /* internal CM/debug use */
+        __be32                  local_id;
+        __be32                  remote_id;
+};
+
+/**
+ * ib_create_cm_id - Allocate a communication identifier.
+ * @cm_handler: Callback invoked to notify the user of CM events.
+ * @context: User specified context associated with the communication
+ *   identifier.
+ *
+ * Communication identifiers are used to track connection states, service
+ * ID resolution requests, and listen requests.
+ */
+struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler,
+                                 void *context);
+
+/**
+ * ib_destroy_cm_id - Destroy a connection identifier.
+ * @cm_id: Connection identifier to destroy.
+ *
+ * This call blocks until the connection identifier is destroyed.
+ */
+void ib_destroy_cm_id(struct ib_cm_id *cm_id);
+
+#define IB_SERVICE_ID_AGN_MASK  __constant_cpu_to_be64(0xFF00000000000000ULL)
+#define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL)
+
+/**
+ * ib_cm_listen - Initiates listening on the specified service ID for
+ *   connection and service ID resolution requests.
+ * @cm_id: Connection identifier associated with the listen request.
+ * @service_id: Service identifier matched against incoming connection
+ *   and service ID resolution requests.  The service ID should be specified
+ *   network-byte order.  If set to IB_CM_ASSIGN_SERVICE_ID, the CM will
+ *   assign a service ID to the caller.
+ * @service_mask: Mask applied to service ID used to listen across a
+ *   range of service IDs.  If set to 0, the service ID is matched
+ *   exactly.  This parameter is ignored if %service_id is set to
+ *   IB_CM_ASSIGN_SERVICE_ID.
+ */
+int ib_cm_listen(struct ib_cm_id *cm_id,
+                 __be64 service_id,
+                 __be64 service_mask);
+
+struct ib_cm_req_param {
+        struct ib_sa_path_rec   *primary_path;
+        struct ib_sa_path_rec   *alternate_path;
+        __be64                  service_id;
+        u32                     qp_num;
+        enum ib_qp_type         qp_type;
+        u32                     starting_psn;
+        const void              *private_data;
+        u8                      private_data_len;
+        u8                      peer_to_peer;
+        u8                      responder_resources;
+        u8                      initiator_depth;
+        u8                      remote_cm_response_timeout;
+        u8                      flow_control;
+        u8                      local_cm_response_timeout;
+        u8                      retry_count;
+        u8                      rnr_retry_count;
+        u8                      max_cm_retries;
+        u8                      srq;
+};
+
+/**
+ * ib_send_cm_req - Sends a connection request to the remote node.
+ * @cm_id: Connection identifier that will be associated with the
+ *   connection request.
+ * @param: Connection request information needed to establish the
+ *   connection.
+ */
+int ib_send_cm_req(struct ib_cm_id *cm_id,
+                   struct ib_cm_req_param *param);
+
+struct ib_cm_rep_param {
+        u32             qp_num;
+        u32             starting_psn;
+        const void      *private_data;
+        u8              private_data_len;
+        u8              responder_resources;
+        u8              initiator_depth;
+        u8              target_ack_delay;
+        u8              failover_accepted;
+        u8              flow_control;
+        u8              rnr_retry_count;
+        u8              srq;
+};
+
+/**
+ * ib_send_cm_rep - Sends a connection reply in response to a connection
+ *   request.
+ * @cm_id: Connection identifier that will be associated with the
+ *   connection request.
+ * @param: Connection reply information needed to establish the
+ *   connection.
+ */
+int ib_send_cm_rep(struct ib_cm_id *cm_id,
+                   struct ib_cm_rep_param *param);
+
+/**
+ * ib_send_cm_rtu - Sends a connection ready to use message in response
+ *   to a connection reply message.
+ * @cm_id: Connection identifier associated with the connection request.
+ * @private_data: Optional user-defined private data sent with the
+ *   ready to use message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_rtu(struct ib_cm_id *cm_id,
+                   const void *private_data,
+                   u8 private_data_len);
+
+/**
+ * ib_send_cm_dreq - Sends a disconnection request for an existing
+ *   connection.
+ * @cm_id: Connection identifier associated with the connection being
+ *   released.
+ * @private_data: Optional user-defined private data sent with the
+ *   disconnection request message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_dreq(struct ib_cm_id *cm_id,
+                    const void *private_data,
+                    u8 private_data_len);
+
+/**
+ * ib_send_cm_drep - Sends a disconnection reply to a disconnection request.
+ * @cm_id: Connection identifier associated with the connection being
+ *   released.
+ * @private_data: Optional user-defined private data sent with the
+ *   disconnection reply message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ *
+ * If the cm_id is in the correct state, the CM will transition the connection
+ * to the timewait state, even if an error occurs sending the DREP message.
+ */
+int ib_send_cm_drep(struct ib_cm_id *cm_id,
+                    const void *private_data,
+                    u8 private_data_len);
+
+/**
+ * ib_cm_establish - Forces a connection state to established.
+ * @cm_id: Connection identifier to transition to established.
+ *
+ * This routine should be invoked by users who receive messages on a
+ * connected QP before an RTU has been received.
+ */
+int ib_cm_establish(struct ib_cm_id *cm_id);
+
+/**
+ * ib_send_cm_rej - Sends a connection rejection message to the
+ *   remote node.
+ * @cm_id: Connection identifier associated with the connection being
+ *   rejected.
+ * @reason: Reason for the connection request rejection.
+ * @ari: Optional additional rejection information.
+ * @ari_length: Size of the additional rejection information, in bytes.
+ * @private_data: Optional user-defined private data sent with the
+ *   rejection message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_rej(struct ib_cm_id *cm_id,
+                   enum ib_cm_rej_reason reason,
+                   void *ari,
+                   u8 ari_length,
+                   const void *private_data,
+                   u8 private_data_len);
+
+/**
+ * ib_send_cm_mra - Sends a message receipt acknowledgement to a connection
+ *   message.
+ * @cm_id: Connection identifier associated with the connection message.
+ * @service_timeout: The maximum time required for the sender to reply to
+ *   to the connection message.
+ * @private_data: Optional user-defined private data sent with the
+ *   message receipt acknowledgement.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_mra(struct ib_cm_id *cm_id,
+                   u8 service_timeout,
+                   const void *private_data,
+                   u8 private_data_len);
+
+/**
+ * ib_send_cm_lap - Sends a load alternate path request.
+ * @cm_id: Connection identifier associated with the load alternate path
+ *   message.
+ * @alternate_path: A path record that identifies the alternate path to
+ *   load.
+ * @private_data: Optional user-defined private data sent with the
+ *   load alternate path message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_lap(struct ib_cm_id *cm_id,
+                   struct ib_sa_path_rec *alternate_path,
+                   const void *private_data,
+                   u8 private_data_len);
+
+/**
+ * ib_cm_init_qp_attr - Initializes the QP attributes for use in transitioning
+ *   to a specified QP state.
+ * @cm_id: Communication identifier associated with the QP attributes to
+ *   initialize.
+ * @qp_attr: On input, specifies the desired QP state.  On output, the
+ *   mandatory and desired optional attributes will be set in order to
+ *   modify the QP to the specified state.
+ * @qp_attr_mask: The QP attribute mask that may be used to transition the
+ *   QP to the specified state.
+ *
+ * Users must set the @qp_attr->qp_state to the desired QP state.  This call
+ * will set all required attributes for the given transition, along with
+ * known optional attributes.  Users may override the attributes returned from
+ * this call before calling ib_modify_qp.
+ */
+int ib_cm_init_qp_attr(struct ib_cm_id *cm_id,
+                       struct ib_qp_attr *qp_attr,
+                       int *qp_attr_mask);
+
+/**
+ * ib_send_cm_apr - Sends an alternate path response message in response to
+ *   a load alternate path request.
+ * @cm_id: Connection identifier associated with the alternate path response.
+ * @status: Reply status sent with the alternate path response.
+ * @info: Optional additional information sent with the alternate path
+ *   response.
+ * @info_length: Size of the additional information, in bytes.
+ * @private_data: Optional user-defined private data sent with the
+ *   alternate path response message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_apr(struct ib_cm_id *cm_id,
+                   enum ib_cm_apr_status status,
+                   void *info,
+                   u8 info_length,
+                   const void *private_data,
+                   u8 private_data_len);
+
+struct ib_cm_sidr_req_param {
+        struct ib_sa_path_rec   *path;
+        __be64                  service_id;
+        int                     timeout_ms;
+        const void              *private_data;
+        u8                      private_data_len;
+        u8                      max_cm_retries;
+        u16                     pkey;
+};
+
+/**
+ * ib_send_cm_sidr_req - Sends a service ID resolution request to the
+ *   remote node.
+ * @cm_id: Communication identifier that will be associated with the
+ *   service ID resolution request.
+ * @param: Service ID resolution request information.
+ */
+int ib_send_cm_sidr_req(struct ib_cm_id *cm_id,
+                        struct ib_cm_sidr_req_param *param);
+
+struct ib_cm_sidr_rep_param {
+        u32                     qp_num;
+        u32                     qkey;
+        enum ib_cm_sidr_status  status;
+        const void              *info;
+        u8                      info_length;
+        const void              *private_data;
+        u8                      private_data_len;
+};
+
+/**
+ * ib_send_cm_sidr_rep - Sends a service ID resolution request to the
+ *   remote node.
+ * @cm_id: Communication identifier associated with the received service ID
+ *   resolution request.
+ * @param: Service ID resolution reply information.
+ */
+int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id,
+                        struct ib_cm_sidr_rep_param *param);
+
+#endif /* IB_CM_H */
diff --git a/include/rdma/ib_fmr_pool.h b/include/rdma/ib_fmr_pool.h
new file mode 100644
index 000000000000..86b7e93f198b
--- /dev/null
+++ b/include/rdma/ib_fmr_pool.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $
+ */
+
+#if !defined(IB_FMR_POOL_H)
+#define IB_FMR_POOL_H
+
+#include <rdma/ib_verbs.h>
+
+struct ib_fmr_pool;
+
+/**
+ * struct ib_fmr_pool_param - Parameters for creating FMR pool
+ * @max_pages_per_fmr:Maximum number of pages per map request.
+ * @access:Access flags for FMRs in pool.
+ * @pool_size:Number of FMRs to allocate for pool.
+ * @dirty_watermark:Flush is triggered when @dirty_watermark dirty
+ *     FMRs are present.
+ * @flush_function:Callback called when unmapped FMRs are flushed and
+ *     more FMRs are possibly available for mapping
+ * @flush_arg:Context passed to user's flush function.
+ * @cache:If set, FMRs may be reused after unmapping for identical map
+ *     requests.
+ */
+struct ib_fmr_pool_param {
+        int                     max_pages_per_fmr;
+        enum ib_access_flags    access;
+        int                     pool_size;
+        int                     dirty_watermark;
+        void                  (*flush_function)(struct ib_fmr_pool *pool,
+                                                void *              arg);
+        void                   *flush_arg;
+        unsigned                cache:1;
+};
+
+struct ib_pool_fmr {
+        struct ib_fmr      *fmr;
+        struct ib_fmr_pool *pool;
+        struct list_head    list;
+        struct hlist_node   cache_node;
+        int                 ref_count;
+        int                 remap_count;
+        u64                 io_virtual_address;
+        int                 page_list_len;
+        u64                 page_list[0];
+};
+
+struct ib_fmr_pool *ib_create_fmr_pool(struct ib_pd             *pd,
+                                       struct ib_fmr_pool_param *params);
+
+void ib_destroy_fmr_pool(struct ib_fmr_pool *pool);
+
+int ib_flush_fmr_pool(struct ib_fmr_pool *pool);
+
+struct ib_pool_fmr *ib_fmr_pool_map_phys(struct ib_fmr_pool *pool_handle,
+                                         u64                *page_list,
+                                         int                 list_len,
+                                         u64                *io_virtual_address);
+
+int ib_fmr_pool_unmap(struct ib_pool_fmr *fmr);
+
+#endif /* IB_FMR_POOL_H */
diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h
new file mode 100644
index 000000000000..fc6b1c18ffc6
--- /dev/null
+++ b/include/rdma/ib_mad.h
@@ -0,0 +1,579 @@
+/*
+ * Copyright (c) 2004 Mellanox Technologies Ltd.  All rights reserved.
+ * Copyright (c) 2004 Infinicon Corporation.  All rights reserved.
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_mad.h 2775 2005-07-02 13:42:12Z halr $
+ */
+
+#if !defined( IB_MAD_H )
+#define IB_MAD_H
+
+#include <linux/pci.h>
+
+#include <rdma/ib_verbs.h>
+
+/* Management base version */
+#define IB_MGMT_BASE_VERSION                    1
+
+/* Management classes */
+#define IB_MGMT_CLASS_SUBN_LID_ROUTED           0x01
+#define IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE       0x81
+#define IB_MGMT_CLASS_SUBN_ADM                  0x03
+#define IB_MGMT_CLASS_PERF_MGMT                 0x04
+#define IB_MGMT_CLASS_BM                        0x05
+#define IB_MGMT_CLASS_DEVICE_MGMT               0x06
+#define IB_MGMT_CLASS_CM                        0x07
+#define IB_MGMT_CLASS_SNMP                      0x08
+#define IB_MGMT_CLASS_VENDOR_RANGE2_START       0x30
+#define IB_MGMT_CLASS_VENDOR_RANGE2_END         0x4F
+
+#define IB_OPENIB_OUI                           (0x001405)
+
+/* Management methods */
+#define IB_MGMT_METHOD_GET                      0x01
+#define IB_MGMT_METHOD_SET                      0x02
+#define IB_MGMT_METHOD_GET_RESP                 0x81
+#define IB_MGMT_METHOD_SEND                     0x03
+#define IB_MGMT_METHOD_TRAP                     0x05
+#define IB_MGMT_METHOD_REPORT                   0x06
+#define IB_MGMT_METHOD_REPORT_RESP              0x86
+#define IB_MGMT_METHOD_TRAP_REPRESS             0x07
+
+#define IB_MGMT_METHOD_RESP                     0x80
+
+#define IB_MGMT_MAX_METHODS                     128
+
+/* RMPP information */
+#define IB_MGMT_RMPP_VERSION                    1
+
+#define IB_MGMT_RMPP_TYPE_DATA                  1
+#define IB_MGMT_RMPP_TYPE_ACK                   2
+#define IB_MGMT_RMPP_TYPE_STOP                  3
+#define IB_MGMT_RMPP_TYPE_ABORT                 4
+
+#define IB_MGMT_RMPP_FLAG_ACTIVE                1
+#define IB_MGMT_RMPP_FLAG_FIRST                 (1<<1)
+#define IB_MGMT_RMPP_FLAG_LAST                  (1<<2)
+
+#define IB_MGMT_RMPP_NO_RESPTIME                0x1F
+
+#define IB_MGMT_RMPP_STATUS_SUCCESS             0
+#define IB_MGMT_RMPP_STATUS_RESX                1
+#define IB_MGMT_RMPP_STATUS_ABORT_MIN           118
+#define IB_MGMT_RMPP_STATUS_T2L                 118
+#define IB_MGMT_RMPP_STATUS_BAD_LEN             119
+#define IB_MGMT_RMPP_STATUS_BAD_SEG             120
+#define IB_MGMT_RMPP_STATUS_BADT                121
+#define IB_MGMT_RMPP_STATUS_W2S                 122
+#define IB_MGMT_RMPP_STATUS_S2B                 123
+#define IB_MGMT_RMPP_STATUS_BAD_STATUS          124
+#define IB_MGMT_RMPP_STATUS_UNV                 125
+#define IB_MGMT_RMPP_STATUS_TMR                 126
+#define IB_MGMT_RMPP_STATUS_UNSPEC              127
+#define IB_MGMT_RMPP_STATUS_ABORT_MAX           127
+
+#define IB_QP0          0
+#define IB_QP1          __constant_htonl(1)
+#define IB_QP1_QKEY     0x80010000
+#define IB_QP_SET_QKEY  0x80000000
+
+struct ib_mad_hdr {
+        u8      base_version;
+        u8      mgmt_class;
+        u8      class_version;
+        u8      method;
+        __be16  status;
+        __be16  class_specific;
+        __be64  tid;
+        __be16  attr_id;
+        __be16  resv;
+        __be32  attr_mod;
+};
+
+struct ib_rmpp_hdr {
+        u8      rmpp_version;
+        u8      rmpp_type;
+        u8      rmpp_rtime_flags;
+        u8      rmpp_status;
+        __be32  seg_num;
+        __be32  paylen_newwin;
+};
+
+typedef u64 __bitwise ib_sa_comp_mask;
+
+#define IB_SA_COMP_MASK(n) ((__force ib_sa_comp_mask) cpu_to_be64(1ull << n))
+
+/*
+ * ib_sa_hdr and ib_sa_mad structures must be packed because they have
+ * 64-bit fields that are only 32-bit aligned. 64-bit architectures will
+ * lay them out wrong otherwise.  (And unfortunately they are sent on
+ * the wire so we can't change the layout)
+ */
+struct ib_sa_hdr {
+        __be64                  sm_key;
+        __be16                  attr_offset;
+        __be16                  reserved;
+        ib_sa_comp_mask         comp_mask;
+} __attribute__ ((packed));
+
+struct ib_mad {
+        struct ib_mad_hdr       mad_hdr;
+        u8                      data[232];
+};
+
+struct ib_rmpp_mad {
+        struct ib_mad_hdr       mad_hdr;
+        struct ib_rmpp_hdr      rmpp_hdr;
+        u8                      data[220];
+};
+
+struct ib_sa_mad {
+        struct ib_mad_hdr       mad_hdr;
+        struct ib_rmpp_hdr      rmpp_hdr;
+        struct ib_sa_hdr        sa_hdr;
+        u8                      data[200];
+} __attribute__ ((packed));
+
+struct ib_vendor_mad {
+        struct ib_mad_hdr       mad_hdr;
+        struct ib_rmpp_hdr      rmpp_hdr;
+        u8                      reserved;
+        u8                      oui[3];
+        u8                      data[216];
+};
+
+/**
+ * ib_mad_send_buf - MAD data buffer and work request for sends.
+ * @mad: References an allocated MAD data buffer.  The size of the data
+ *   buffer is specified in the @send_wr.length field.
+ * @mapping: DMA mapping information.
+ * @mad_agent: MAD agent that allocated the buffer.
+ * @context: User-controlled context fields.
+ * @send_wr: An initialized work request structure used when sending the MAD.
+ *   The wr_id field of the work request is initialized to reference this
+ *   data structure.
+ * @sge: A scatter-gather list referenced by the work request.
+ *
+ * Users are responsible for initializing the MAD buffer itself, with the
+ * exception of specifying the payload length field in any RMPP MAD.
+ */
+struct ib_mad_send_buf {
+        struct ib_mad           *mad;
+        DECLARE_PCI_UNMAP_ADDR(mapping)
+        struct ib_mad_agent     *mad_agent;
+        void                    *context[2];
+        struct ib_send_wr       send_wr;
+        struct ib_sge           sge;
+};
+
+/**
+ * ib_get_rmpp_resptime - Returns the RMPP response time.
+ * @rmpp_hdr: An RMPP header.
+ */
+static inline u8 ib_get_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr)
+{
+        return rmpp_hdr->rmpp_rtime_flags >> 3;
+}
+
+/**
+ * ib_get_rmpp_flags - Returns the RMPP flags.
+ * @rmpp_hdr: An RMPP header.
+ */
+static inline u8 ib_get_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr)
+{
+        return rmpp_hdr->rmpp_rtime_flags & 0x7;
+}
+
+/**
+ * ib_set_rmpp_resptime - Sets the response time in an RMPP header.
+ * @rmpp_hdr: An RMPP header.
+ * @rtime: The response time to set.
+ */
+static inline void ib_set_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr, u8 rtime)
+{
+        rmpp_hdr->rmpp_rtime_flags = ib_get_rmpp_flags(rmpp_hdr) | (rtime << 3);
+}
+
+/**
+ * ib_set_rmpp_flags - Sets the flags in an RMPP header.
+ * @rmpp_hdr: An RMPP header.
+ * @flags: The flags to set.
+ */
+static inline void ib_set_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr, u8 flags)
+{
+        rmpp_hdr->rmpp_rtime_flags = (rmpp_hdr->rmpp_rtime_flags & 0xF1) |
+                                     (flags & 0x7);
+}
+
+struct ib_mad_agent;
+struct ib_mad_send_wc;
+struct ib_mad_recv_wc;
+
+/**
+ * ib_mad_send_handler - callback handler for a sent MAD.
+ * @mad_agent: MAD agent that sent the MAD.
+ * @mad_send_wc: Send work completion information on the sent MAD.
+ */
+typedef void (*ib_mad_send_handler)(struct ib_mad_agent *mad_agent,
+                                    struct ib_mad_send_wc *mad_send_wc);
+
+/**
+ * ib_mad_snoop_handler - Callback handler for snooping sent MADs.
+ * @mad_agent: MAD agent that snooped the MAD.
+ * @send_wr: Work request information on the sent MAD.
+ * @mad_send_wc: Work completion information on the sent MAD.  Valid
+ *   only for snooping that occurs on a send completion.
+ *
+ * Clients snooping MADs should not modify data referenced by the @send_wr
+ * or @mad_send_wc.
+ */
+typedef void (*ib_mad_snoop_handler)(struct ib_mad_agent *mad_agent,
+                                     struct ib_send_wr *send_wr,
+                                     struct ib_mad_send_wc *mad_send_wc);
+
+/**
+ * ib_mad_recv_handler - callback handler for a received MAD.
+ * @mad_agent: MAD agent requesting the received MAD.
+ * @mad_recv_wc: Received work completion information on the received MAD.
+ *
+ * MADs received in response to a send request operation will be handed to
+ * the user after the send operation completes.  All data buffers given
+ * to registered agents through this routine are owned by the receiving
+ * client, except for snooping agents.  Clients snooping MADs should not
+ * modify the data referenced by @mad_recv_wc.
+ */
+typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent,
+                                    struct ib_mad_recv_wc *mad_recv_wc);
+
+/**
+ * ib_mad_agent - Used to track MAD registration with the access layer.
+ * @device: Reference to device registration is on.
+ * @qp: Reference to QP used for sending and receiving MADs.
+ * @mr: Memory region for system memory usable for DMA.
+ * @recv_handler: Callback handler for a received MAD.
+ * @send_handler: Callback handler for a sent MAD.
+ * @snoop_handler: Callback handler for snooped sent MADs.
+ * @context: User-specified context associated with this registration.
+ * @hi_tid: Access layer assigned transaction ID for this client.
+ *   Unsolicited MADs sent by this client will have the upper 32-bits
+ *   of their TID set to this value.
+ * @port_num: Port number on which QP is registered
+ * @rmpp_version: If set, indicates the RMPP version used by this agent.
+ */
+struct ib_mad_agent {
+        struct ib_device        *device;
+        struct ib_qp            *qp;
+        struct ib_mr            *mr;
+        ib_mad_recv_handler     recv_handler;
+        ib_mad_send_handler     send_handler;
+        ib_mad_snoop_handler    snoop_handler;
+        void                    *context;
+        u32                     hi_tid;
+        u8                      port_num;
+        u8                      rmpp_version;
+};
+
+/**
+ * ib_mad_send_wc - MAD send completion information.
+ * @wr_id: Work request identifier associated with the send MAD request.
+ * @status: Completion status.
+ * @vendor_err: Optional vendor error information returned with a failed
+ *   request.
+ */
+struct ib_mad_send_wc {
+        u64                     wr_id;
+        enum ib_wc_status       status;
+        u32                     vendor_err;
+};
+
+/**
+ * ib_mad_recv_buf - received MAD buffer information.
+ * @list: Reference to next data buffer for a received RMPP MAD.
+ * @grh: References a data buffer containing the global route header.
+ *   The data refereced by this buffer is only valid if the GRH is
+ *   valid.
+ * @mad: References the start of the received MAD.
+ */
+struct ib_mad_recv_buf {
+        struct list_head        list;
+        struct ib_grh           *grh;
+        struct ib_mad           *mad;
+};
+
+/**
+ * ib_mad_recv_wc - received MAD information.
+ * @wc: Completion information for the received data.
+ * @recv_buf: Specifies the location of the received data buffer(s).
+ * @rmpp_list: Specifies a list of RMPP reassembled received MAD buffers.
+ * @mad_len: The length of the received MAD, without duplicated headers.
+ *
+ * For received response, the wr_id field of the wc is set to the wr_id
+ *   for the corresponding send request.
+ */
+struct ib_mad_recv_wc {
+        struct ib_wc            *wc;
+        struct ib_mad_recv_buf  recv_buf;
+        struct list_head        rmpp_list;
+        int                     mad_len;
+};
+
+/**
+ * ib_mad_reg_req - MAD registration request
+ * @mgmt_class: Indicates which management class of MADs should be receive
+ *   by the caller.  This field is only required if the user wishes to
+ *   receive unsolicited MADs, otherwise it should be 0.
+ * @mgmt_class_version: Indicates which version of MADs for the given
+ *   management class to receive.
+ * @oui: Indicates IEEE OUI when mgmt_class is a vendor class
+ *   in the range from 0x30 to 0x4f. Otherwise not used.
+ * @method_mask: The caller will receive unsolicited MADs for any method
+ *   where @method_mask = 1.
+ */
+struct ib_mad_reg_req {
+        u8      mgmt_class;
+        u8      mgmt_class_version;
+        u8      oui[3];
+        DECLARE_BITMAP(method_mask, IB_MGMT_MAX_METHODS);
+};
+
+/**
+ * ib_register_mad_agent - Register to send/receive MADs.
+ * @device: The device to register with.
+ * @port_num: The port on the specified device to use.
+ * @qp_type: Specifies which QP to access.  Must be either
+ *   IB_QPT_SMI or IB_QPT_GSI.
+ * @mad_reg_req: Specifies which unsolicited MADs should be received
+ *   by the caller.  This parameter may be NULL if the caller only
+ *   wishes to receive solicited responses.
+ * @rmpp_version: If set, indicates that the client will send
+ *   and receive MADs that contain the RMPP header for the given version.
+ *   If set to 0, indicates that RMPP is not used by this client.
+ * @send_handler: The completion callback routine invoked after a send
+ *   request has completed.
+ * @recv_handler: The completion callback routine invoked for a received
+ *   MAD.
+ * @context: User specified context associated with the registration.
+ */
+struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
+                                           u8 port_num,
+                                           enum ib_qp_type qp_type,
+                                           struct ib_mad_reg_req *mad_reg_req,
+                                           u8 rmpp_version,
+                                           ib_mad_send_handler send_handler,
+                                           ib_mad_recv_handler recv_handler,
+                                           void *context);
+
+enum ib_mad_snoop_flags {
+        /*IB_MAD_SNOOP_POSTED_SENDS        = 1,*/
+        /*IB_MAD_SNOOP_RMPP_SENDS          = (1<<1),*/
+        IB_MAD_SNOOP_SEND_COMPLETIONS      = (1<<2),
+        /*IB_MAD_SNOOP_RMPP_SEND_COMPLETIONS = (1<<3),*/
+        IB_MAD_SNOOP_RECVS                 = (1<<4)
+        /*IB_MAD_SNOOP_RMPP_RECVS          = (1<<5),*/
+        /*IB_MAD_SNOOP_REDIRECTED_QPS      = (1<<6)*/
+};
+
+/**
+ * ib_register_mad_snoop - Register to snoop sent and received MADs.
+ * @device: The device to register with.
+ * @port_num: The port on the specified device to use.
+ * @qp_type: Specifies which QP traffic to snoop.  Must be either
+ *   IB_QPT_SMI or IB_QPT_GSI.
+ * @mad_snoop_flags: Specifies information where snooping occurs.
+ * @send_handler: The callback routine invoked for a snooped send.
+ * @recv_handler: The callback routine invoked for a snooped receive.
+ * @context: User specified context associated with the registration.
+ */
+struct ib_mad_agent *ib_register_mad_snoop(struct ib_device *device,
+                                           u8 port_num,
+                                           enum ib_qp_type qp_type,
+                                           int mad_snoop_flags,
+                                           ib_mad_snoop_handler snoop_handler,
+                                           ib_mad_recv_handler recv_handler,
+                                           void *context);
+
+/**
+ * ib_unregister_mad_agent - Unregisters a client from using MAD services.
+ * @mad_agent: Corresponding MAD registration request to deregister.
+ *
+ * After invoking this routine, MAD services are no longer usable by the
+ * client on the associated QP.
+ */
+int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent);
+
+/**
+ * ib_post_send_mad - Posts MAD(s) to the send queue of the QP associated
+ *   with the registered client.
+ * @mad_agent: Specifies the associated registration to post the send to.
+ * @send_wr: Specifies the information needed to send the MAD(s).
+ * @bad_send_wr: Specifies the MAD on which an error was encountered.
+ *
+ * Sent MADs are not guaranteed to complete in the order that they were posted.
+ *
+ * If the MAD requires RMPP, the data buffer should contain a single copy
+ * of the common MAD, RMPP, and class specific headers, followed by the class
+ * defined data.  If the class defined data would not divide evenly into
+ * RMPP segments, then space must be allocated at the end of the referenced
+ * buffer for any required padding.  To indicate the amount of class defined
+ * data being transferred, the paylen_newwin field in the RMPP header should
+ * be set to the size of the class specific header plus the amount of class
+ * defined data being transferred.  The paylen_newwin field should be
+ * specified in network-byte order.
+ */
+int ib_post_send_mad(struct ib_mad_agent *mad_agent,
+                     struct ib_send_wr *send_wr,
+                     struct ib_send_wr **bad_send_wr);
+
+/**
+ * ib_coalesce_recv_mad - Coalesces received MAD data into a single buffer.
+ * @mad_recv_wc: Work completion information for a received MAD.
+ * @buf: User-provided data buffer to receive the coalesced buffers.  The
+ *   referenced buffer should be at least the size of the mad_len specified
+ *   by @mad_recv_wc.
+ *
+ * This call copies a chain of received MAD segments into a single data buffer,
+ * removing duplicated headers.
+ */
+void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf);
+
+/**
+ * ib_free_recv_mad - Returns data buffers used to receive a MAD.
+ * @mad_recv_wc: Work completion information for a received MAD.
+ *
+ * Clients receiving MADs through their ib_mad_recv_handler must call this
+ * routine to return the work completion buffers to the access layer.
+ */
+void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc);
+
+/**
+ * ib_cancel_mad - Cancels an outstanding send MAD operation.
+ * @mad_agent: Specifies the registration associated with sent MAD.
+ * @wr_id: Indicates the work request identifier of the MAD to cancel.
+ *
+ * MADs will be returned to the user through the corresponding
+ * ib_mad_send_handler.
+ */
+void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id);
+
+/**
+ * ib_modify_mad - Modifies an outstanding send MAD operation.
+ * @mad_agent: Specifies the registration associated with sent MAD.
+ * @wr_id: Indicates the work request identifier of the MAD to modify.
+ * @timeout_ms: New timeout value for sent MAD.
+ *
+ * This call will reset the timeout value for a sent MAD to the specified
+ * value.
+ */
+int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms);
+
+/**
+ * ib_redirect_mad_qp - Registers a QP for MAD services.
+ * @qp: Reference to a QP that requires MAD services.
+ * @rmpp_version: If set, indicates that the client will send
+ *   and receive MADs that contain the RMPP header for the given version.
+ *   If set to 0, indicates that RMPP is not used by this client.
+ * @send_handler: The completion callback routine invoked after a send
+ *   request has completed.
+ * @recv_handler: The completion callback routine invoked for a received
+ *   MAD.
+ * @context: User specified context associated with the registration.
+ *
+ * Use of this call allows clients to use MAD services, such as RMPP,
+ * on user-owned QPs.  After calling this routine, users may send
+ * MADs on the specified QP by calling ib_mad_post_send.
+ */
+struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp,
+                                        u8 rmpp_version,
+                                        ib_mad_send_handler send_handler,
+                                        ib_mad_recv_handler recv_handler,
+                                        void *context);
+
+/**
+ * ib_process_mad_wc - Processes a work completion associated with a
+ *   MAD sent or received on a redirected QP.
+ * @mad_agent: Specifies the registered MAD service using the redirected QP.
+ * @wc: References a work completion associated with a sent or received
+ *   MAD segment.
+ *
+ * This routine is used to complete or continue processing on a MAD request.
+ * If the work completion is associated with a send operation, calling
+ * this routine is required to continue an RMPP transfer or to wait for a
+ * corresponding response, if it is a request.  If the work completion is
+ * associated with a receive operation, calling this routine is required to
+ * process an inbound or outbound RMPP transfer, or to match a response MAD
+ * with its corresponding request.
+ */
+int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
+                      struct ib_wc *wc);
+
+/**
+ * ib_create_send_mad - Allocate and initialize a data buffer and work request
+ *   for sending a MAD.
+ * @mad_agent: Specifies the registered MAD service to associate with the MAD.
+ * @remote_qpn: Specifies the QPN of the receiving node.
+ * @pkey_index: Specifies which PKey the MAD will be sent using.  This field
+ *   is valid only if the remote_qpn is QP 1.
+ * @ah: References the address handle used to transfer to the remote node.
+ * @rmpp_active: Indicates if the send will enable RMPP.
+ * @hdr_len: Indicates the size of the data header of the MAD.  This length
+ *   should include the common MAD header, RMPP header, plus any class
+ *   specific header.
+ * @data_len: Indicates the size of any user-transferred data.  The call will
+ *   automatically adjust the allocated buffer size to account for any
+ *   additional padding that may be necessary.
+ * @gfp_mask: GFP mask used for the memory allocation.
+ *
+ * This is a helper routine that may be used to allocate a MAD.  Users are
+ * not required to allocate outbound MADs using this call.  The returned
+ * MAD send buffer will reference a data buffer usable for sending a MAD, along
+ * with an initialized work request structure.  Users may modify the returned
+ * MAD data buffer or work request before posting the send.
+ *
+ * The returned data buffer will be cleared.  Users are responsible for
+ * initializing the common MAD and any class specific headers.  If @rmpp_active
+ * is set, the RMPP header will be initialized for sending.
+ */
+struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent,
+                                            u32 remote_qpn, u16 pkey_index,
+                                            struct ib_ah *ah, int rmpp_active,
+                                            int hdr_len, int data_len,
+                                            unsigned int __nocast gfp_mask);
+
+/**
+ * ib_free_send_mad - Returns data buffers used to send a MAD.
+ * @send_buf: Previously allocated send data buffer.
+ */
+void ib_free_send_mad(struct ib_mad_send_buf *send_buf);
+
+#endif /* IB_MAD_H */
diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h
new file mode 100644
index 000000000000..f926020d6331
--- /dev/null
+++ b/include/rdma/ib_pack.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_pack.h 1349 2004-12-16 21:09:43Z roland $
+ */
+
+#ifndef IB_PACK_H
+#define IB_PACK_H
+
+#include <rdma/ib_verbs.h>
+
+enum {
+        IB_LRH_BYTES  = 8,
+        IB_GRH_BYTES  = 40,
+        IB_BTH_BYTES  = 12,
+        IB_DETH_BYTES = 8
+};
+
+struct ib_field {
+        size_t struct_offset_bytes;
+        size_t struct_size_bytes;
+        int    offset_words;
+        int    offset_bits;
+        int    size_bits;
+        char  *field_name;
+};
+
+#define RESERVED \
+        .field_name          = "reserved"
+
+/*
+ * This macro cleans up the definitions of constants for BTH opcodes.
+ * It is used to define constants such as IB_OPCODE_UD_SEND_ONLY,
+ * which becomes IB_OPCODE_UD + IB_OPCODE_SEND_ONLY, and this gives
+ * the correct value.
+ *
+ * In short, user code should use the constants defined using the
+ * macro rather than worrying about adding together other constants.
+*/
+#define IB_OPCODE(transport, op) \
+        IB_OPCODE_ ## transport ## _ ## op = \
+                IB_OPCODE_ ## transport + IB_OPCODE_ ## op
+
+enum {
+        /* transport types -- just used to define real constants */
+        IB_OPCODE_RC                                = 0x00,
+        IB_OPCODE_UC                                = 0x20,
+        IB_OPCODE_RD                                = 0x40,
+        IB_OPCODE_UD                                = 0x60,
+
+        /* operations -- just used to define real constants */
+        IB_OPCODE_SEND_FIRST                        = 0x00,
+        IB_OPCODE_SEND_MIDDLE                       = 0x01,
+        IB_OPCODE_SEND_LAST                         = 0x02,
+        IB_OPCODE_SEND_LAST_WITH_IMMEDIATE          = 0x03,
+        IB_OPCODE_SEND_ONLY                         = 0x04,
+        IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE          = 0x05,
+        IB_OPCODE_RDMA_WRITE_FIRST                  = 0x06,
+        IB_OPCODE_RDMA_WRITE_MIDDLE                 = 0x07,
+        IB_OPCODE_RDMA_WRITE_LAST                   = 0x08,
+        IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE    = 0x09,
+        IB_OPCODE_RDMA_WRITE_ONLY                   = 0x0a,
+        IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE    = 0x0b,
+        IB_OPCODE_RDMA_READ_REQUEST                 = 0x0c,
+        IB_OPCODE_RDMA_READ_RESPONSE_FIRST          = 0x0d,
+        IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE         = 0x0e,
+        IB_OPCODE_RDMA_READ_RESPONSE_LAST           = 0x0f,
+        IB_OPCODE_RDMA_READ_RESPONSE_ONLY           = 0x10,
+        IB_OPCODE_ACKNOWLEDGE                       = 0x11,
+        IB_OPCODE_ATOMIC_ACKNOWLEDGE                = 0x12,
+        IB_OPCODE_COMPARE_SWAP                      = 0x13,
+        IB_OPCODE_FETCH_ADD                         = 0x14,
+
+        /* real constants follow -- see comment about above IB_OPCODE()
+           macro for more details */
+
+        /* RC */
+        IB_OPCODE(RC, SEND_FIRST),
+        IB_OPCODE(RC, SEND_MIDDLE),
+        IB_OPCODE(RC, SEND_LAST),
+        IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(RC, SEND_ONLY),
+        IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
+        IB_OPCODE(RC, RDMA_WRITE_FIRST),
+        IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
+        IB_OPCODE(RC, RDMA_WRITE_LAST),
+        IB_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(RC, RDMA_WRITE_ONLY),
+        IB_OPCODE(RC, RDMA_WRITE_ONLY_WITH_IMMEDIATE),
+        IB_OPCODE(RC, RDMA_READ_REQUEST),
+        IB_OPCODE(RC, RDMA_READ_RESPONSE_FIRST),
+        IB_OPCODE(RC, RDMA_READ_RESPONSE_MIDDLE),
+        IB_OPCODE(RC, RDMA_READ_RESPONSE_LAST),
+        IB_OPCODE(RC, RDMA_READ_RESPONSE_ONLY),
+        IB_OPCODE(RC, ACKNOWLEDGE),
+        IB_OPCODE(RC, ATOMIC_ACKNOWLEDGE),
+        IB_OPCODE(RC, COMPARE_SWAP),
+        IB_OPCODE(RC, FETCH_ADD),
+
+        /* UC */
+        IB_OPCODE(UC, SEND_FIRST),
+        IB_OPCODE(UC, SEND_MIDDLE),
+        IB_OPCODE(UC, SEND_LAST),
+        IB_OPCODE(UC, SEND_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(UC, SEND_ONLY),
+        IB_OPCODE(UC, SEND_ONLY_WITH_IMMEDIATE),
+        IB_OPCODE(UC, RDMA_WRITE_FIRST),
+        IB_OPCODE(UC, RDMA_WRITE_MIDDLE),
+        IB_OPCODE(UC, RDMA_WRITE_LAST),
+        IB_OPCODE(UC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(UC, RDMA_WRITE_ONLY),
+        IB_OPCODE(UC, RDMA_WRITE_ONLY_WITH_IMMEDIATE),
+
+        /* RD */
+        IB_OPCODE(RD, SEND_FIRST),
+        IB_OPCODE(RD, SEND_MIDDLE),
+        IB_OPCODE(RD, SEND_LAST),
+        IB_OPCODE(RD, SEND_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(RD, SEND_ONLY),
+        IB_OPCODE(RD, SEND_ONLY_WITH_IMMEDIATE),
+        IB_OPCODE(RD, RDMA_WRITE_FIRST),
+        IB_OPCODE(RD, RDMA_WRITE_MIDDLE),
+        IB_OPCODE(RD, RDMA_WRITE_LAST),
+        IB_OPCODE(RD, RDMA_WRITE_LAST_WITH_IMMEDIATE),
+        IB_OPCODE(RD, RDMA_WRITE_ONLY),
+        IB_OPCODE(RD, RDMA_WRITE_ONLY_WITH_IMMEDIATE),
+        IB_OPCODE(RD, RDMA_READ_REQUEST),
+        IB_OPCODE(RD, RDMA_READ_RESPONSE_FIRST),
+        IB_OPCODE(RD, RDMA_READ_RESPONSE_MIDDLE),
+        IB_OPCODE(RD, RDMA_READ_RESPONSE_LAST),
+        IB_OPCODE(RD, RDMA_READ_RESPONSE_ONLY),
+        IB_OPCODE(RD, ACKNOWLEDGE),
+        IB_OPCODE(RD, ATOMIC_ACKNOWLEDGE),
+        IB_OPCODE(RD, COMPARE_SWAP),
+        IB_OPCODE(RD, FETCH_ADD),
+
+        /* UD */
+        IB_OPCODE(UD, SEND_ONLY),
+        IB_OPCODE(UD, SEND_ONLY_WITH_IMMEDIATE)
+};
+
+enum {
+        IB_LNH_RAW        = 0,
+        IB_LNH_IP         = 1,
+        IB_LNH_IBA_LOCAL  = 2,
+        IB_LNH_IBA_GLOBAL = 3
+};
+
+struct ib_unpacked_lrh {
+        u8        virtual_lane;
+        u8        link_version;
+        u8        service_level;
+        u8        link_next_header;
+        __be16    destination_lid;
+        __be16    packet_length;
+        __be16    source_lid;
+};
+
+struct ib_unpacked_grh {
+        u8           ip_version;
+        u8           traffic_class;
+        __be32       flow_label;
+        __be16       payload_length;
+        u8           next_header;
+        u8           hop_limit;
+        union ib_gid source_gid;
+        union ib_gid destination_gid;
+};
+
+struct ib_unpacked_bth {
+        u8           opcode;
+        u8           solicited_event;
+        u8           mig_req;
+        u8           pad_count;
+        u8           transport_header_version;
+        __be16       pkey;
+        __be32       destination_qpn;
+        u8           ack_req;
+        __be32       psn;
+};
+
+struct ib_unpacked_deth {
+        __be32       qkey;
+        __be32       source_qpn;
+};
+
+struct ib_ud_header {
+        struct ib_unpacked_lrh  lrh;
+        int                     grh_present;
+        struct ib_unpacked_grh  grh;
+        struct ib_unpacked_bth  bth;
+        struct ib_unpacked_deth deth;
+        int                     immediate_present;
+        __be32                  immediate_data;
+};
+
+void ib_pack(const struct ib_field        *desc,
+             int                           desc_len,
+             void                         *structure,
+             void                         *buf);
+
+void ib_unpack(const struct ib_field        *desc,
+               int                           desc_len,
+               void                         *buf,
+               void                         *structure);
+
+void ib_ud_header_init(int                 payload_bytes,
+                       int                 grh_present,
+                       struct ib_ud_header *header);
+
+int ib_ud_header_pack(struct ib_ud_header *header,
+                      void                *buf);
+
+int ib_ud_header_unpack(void                *buf,
+                        struct ib_ud_header *header);
+
+#endif /* IB_PACK_H */
diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h
new file mode 100644
index 000000000000..c022edfc49da
--- /dev/null
+++ b/include/rdma/ib_sa.h
@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $
+ */
+
+#ifndef IB_SA_H
+#define IB_SA_H
+
+#include <linux/compiler.h>
+
+#include <rdma/ib_verbs.h>
+#include <rdma/ib_mad.h>
+
+enum {
+        IB_SA_CLASS_VERSION             = 2,    /* IB spec version 1.1/1.2 */
+
+        IB_SA_METHOD_GET_TABLE          = 0x12,
+        IB_SA_METHOD_GET_TABLE_RESP     = 0x92,
+        IB_SA_METHOD_DELETE             = 0x15
+};
+
+enum ib_sa_selector {
+        IB_SA_GTE  = 0,
+        IB_SA_LTE  = 1,
+        IB_SA_EQ   = 2,
+        /*
+         * The meaning of "best" depends on the attribute: for
+         * example, for MTU best will return the largest available
+         * MTU, while for packet life time, best will return the
+         * smallest available life time.
+         */
+        IB_SA_BEST = 3
+};
+
+enum ib_sa_rate {
+        IB_SA_RATE_2_5_GBPS = 2,
+        IB_SA_RATE_5_GBPS   = 5,
+        IB_SA_RATE_10_GBPS  = 3,
+        IB_SA_RATE_20_GBPS  = 6,
+        IB_SA_RATE_30_GBPS  = 4,
+        IB_SA_RATE_40_GBPS  = 7,
+        IB_SA_RATE_60_GBPS  = 8,
+        IB_SA_RATE_80_GBPS  = 9,
+        IB_SA_RATE_120_GBPS = 10
+};
+
+static inline int ib_sa_rate_enum_to_int(enum ib_sa_rate rate)
+{
+        switch (rate) {
+        case IB_SA_RATE_2_5_GBPS: return  1;
+        case IB_SA_RATE_5_GBPS:   return  2;
+        case IB_SA_RATE_10_GBPS:  return  4;
+        case IB_SA_RATE_20_GBPS:  return  8;
+        case IB_SA_RATE_30_GBPS:  return 12;
+        case IB_SA_RATE_40_GBPS:  return 16;
+        case IB_SA_RATE_60_GBPS:  return 24;
+        case IB_SA_RATE_80_GBPS:  return 32;
+        case IB_SA_RATE_120_GBPS: return 48;
+        default:                  return -1;
+        }
+}
+
+/*
+ * Structures for SA records are named "struct ib_sa_xxx_rec."  No
+ * attempt is made to pack structures to match the physical layout of
+ * SA records in SA MADs; all packing and unpacking is handled by the
+ * SA query code.
+ *
+ * For a record with structure ib_sa_xxx_rec, the naming convention
+ * for the component mask value for field yyy is IB_SA_XXX_REC_YYY (we
+ * never use different abbreviations or otherwise change the spelling
+ * of xxx/yyy between ib_sa_xxx_rec.yyy and IB_SA_XXX_REC_YYY).
+ *
+ * Reserved rows are indicated with comments to help maintainability.
+ */
+
+/* reserved:                                                             0 */
+/* reserved:                                                             1 */
+#define IB_SA_PATH_REC_DGID                             IB_SA_COMP_MASK( 2)
+#define IB_SA_PATH_REC_SGID                             IB_SA_COMP_MASK( 3)
+#define IB_SA_PATH_REC_DLID                             IB_SA_COMP_MASK( 4)
+#define IB_SA_PATH_REC_SLID                             IB_SA_COMP_MASK( 5)
+#define IB_SA_PATH_REC_RAW_TRAFFIC                      IB_SA_COMP_MASK( 6)
+/* reserved:                                                             7 */
+#define IB_SA_PATH_REC_FLOW_LABEL                       IB_SA_COMP_MASK( 8)
+#define IB_SA_PATH_REC_HOP_LIMIT                        IB_SA_COMP_MASK( 9)
+#define IB_SA_PATH_REC_TRAFFIC_CLASS                    IB_SA_COMP_MASK(10)
+#define IB_SA_PATH_REC_REVERSIBLE                       IB_SA_COMP_MASK(11)
+#define IB_SA_PATH_REC_NUMB_PATH                        IB_SA_COMP_MASK(12)
+#define IB_SA_PATH_REC_PKEY                             IB_SA_COMP_MASK(13)
+/* reserved:                                                            14 */
+#define IB_SA_PATH_REC_SL                               IB_SA_COMP_MASK(15)
+#define IB_SA_PATH_REC_MTU_SELECTOR                     IB_SA_COMP_MASK(16)
+#define IB_SA_PATH_REC_MTU                              IB_SA_COMP_MASK(17)
+#define IB_SA_PATH_REC_RATE_SELECTOR                    IB_SA_COMP_MASK(18)
+#define IB_SA_PATH_REC_RATE                             IB_SA_COMP_MASK(19)
+#define IB_SA_PATH_REC_PACKET_LIFE_TIME_SELECTOR        IB_SA_COMP_MASK(20)
+#define IB_SA_PATH_REC_PACKET_LIFE_TIME                 IB_SA_COMP_MASK(21)
+#define IB_SA_PATH_REC_PREFERENCE                       IB_SA_COMP_MASK(22)
+
+struct ib_sa_path_rec {
+        /* reserved */
+        /* reserved */
+        union ib_gid dgid;
+        union ib_gid sgid;
+        __be16       dlid;
+        __be16       slid;
+        int          raw_traffic;
+        /* reserved */
+        __be32       flow_label;
+        u8           hop_limit;
+        u8           traffic_class;
+        int          reversible;
+        u8           numb_path;
+        __be16       pkey;
+        /* reserved */
+        u8           sl;
+        u8           mtu_selector;
+        u8           mtu;
+        u8           rate_selector;
+        u8           rate;
+        u8           packet_life_time_selector;
+        u8           packet_life_time;
+        u8           preference;
+};
+
+#define IB_SA_MCMEMBER_REC_MGID                         IB_SA_COMP_MASK( 0)
+#define IB_SA_MCMEMBER_REC_PORT_GID                     IB_SA_COMP_MASK( 1)
+#define IB_SA_MCMEMBER_REC_QKEY                         IB_SA_COMP_MASK( 2)
+#define IB_SA_MCMEMBER_REC_MLID                         IB_SA_COMP_MASK( 3)
+#define IB_SA_MCMEMBER_REC_MTU_SELECTOR                 IB_SA_COMP_MASK( 4)
+#define IB_SA_MCMEMBER_REC_MTU                          IB_SA_COMP_MASK( 5)
+#define IB_SA_MCMEMBER_REC_TRAFFIC_CLASS                IB_SA_COMP_MASK( 6)
+#define IB_SA_MCMEMBER_REC_PKEY                         IB_SA_COMP_MASK( 7)
+#define IB_SA_MCMEMBER_REC_RATE_SELECTOR                IB_SA_COMP_MASK( 8)
+#define IB_SA_MCMEMBER_REC_RATE                         IB_SA_COMP_MASK( 9)
+#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME_SELECTOR    IB_SA_COMP_MASK(10)
+#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME             IB_SA_COMP_MASK(11)
+#define IB_SA_MCMEMBER_REC_SL                           IB_SA_COMP_MASK(12)
+#define IB_SA_MCMEMBER_REC_FLOW_LABEL                   IB_SA_COMP_MASK(13)
+#define IB_SA_MCMEMBER_REC_HOP_LIMIT                    IB_SA_COMP_MASK(14)
+#define IB_SA_MCMEMBER_REC_SCOPE                        IB_SA_COMP_MASK(15)
+#define IB_SA_MCMEMBER_REC_JOIN_STATE                   IB_SA_COMP_MASK(16)
+#define IB_SA_MCMEMBER_REC_PROXY_JOIN                   IB_SA_COMP_MASK(17)
+
+struct ib_sa_mcmember_rec {
+        union ib_gid mgid;
+        union ib_gid port_gid;
+        __be32       qkey;
+        __be16       mlid;
+        u8           mtu_selector;
+        u8           mtu;
+        u8           traffic_class;
+        __be16       pkey;
+        u8           rate_selector;
+        u8           rate;
+        u8           packet_life_time_selector;
+        u8           packet_life_time;
+        u8           sl;
+        __be32       flow_label;
+        u8           hop_limit;
+        u8           scope;
+        u8           join_state;
+        int          proxy_join;
+};
+
+/* Service Record Component Mask Sec 15.2.5.14 Ver 1.1  */
+#define IB_SA_SERVICE_REC_SERVICE_ID                    IB_SA_COMP_MASK( 0)
+#define IB_SA_SERVICE_REC_SERVICE_GID                   IB_SA_COMP_MASK( 1)
+#define IB_SA_SERVICE_REC_SERVICE_PKEY                  IB_SA_COMP_MASK( 2)
+/* reserved:                                                             3 */
+#define IB_SA_SERVICE_REC_SERVICE_LEASE                 IB_SA_COMP_MASK( 4)
+#define IB_SA_SERVICE_REC_SERVICE_KEY                   IB_SA_COMP_MASK( 5)
+#define IB_SA_SERVICE_REC_SERVICE_NAME                  IB_SA_COMP_MASK( 6)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_0               IB_SA_COMP_MASK( 7)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_1               IB_SA_COMP_MASK( 8)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_2               IB_SA_COMP_MASK( 9)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_3               IB_SA_COMP_MASK(10)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_4               IB_SA_COMP_MASK(11)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_5               IB_SA_COMP_MASK(12)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_6               IB_SA_COMP_MASK(13)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_7               IB_SA_COMP_MASK(14)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_8               IB_SA_COMP_MASK(15)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_9               IB_SA_COMP_MASK(16)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_10              IB_SA_COMP_MASK(17)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_11              IB_SA_COMP_MASK(18)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_12              IB_SA_COMP_MASK(19)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_13              IB_SA_COMP_MASK(20)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_14              IB_SA_COMP_MASK(21)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_15              IB_SA_COMP_MASK(22)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_0              IB_SA_COMP_MASK(23)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_1              IB_SA_COMP_MASK(24)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_2              IB_SA_COMP_MASK(25)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_3              IB_SA_COMP_MASK(26)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_4              IB_SA_COMP_MASK(27)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_5              IB_SA_COMP_MASK(28)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_6              IB_SA_COMP_MASK(29)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_7              IB_SA_COMP_MASK(30)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_0              IB_SA_COMP_MASK(31)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_1              IB_SA_COMP_MASK(32)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_2              IB_SA_COMP_MASK(33)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_3              IB_SA_COMP_MASK(34)
+#define IB_SA_SERVICE_REC_SERVICE_DATA64_0              IB_SA_COMP_MASK(35)
+#define IB_SA_SERVICE_REC_SERVICE_DATA64_1              IB_SA_COMP_MASK(36)
+
+#define IB_DEFAULT_SERVICE_LEASE        0xFFFFFFFF
+
+struct ib_sa_service_rec {
+        u64             id;
+        union ib_gid    gid;
+        __be16          pkey;
+        /* reserved */
+        u32             lease;
+        u8              key[16];
+        u8              name[64];
+        u8              data8[16];
+        u16             data16[8];
+        u32             data32[4];
+        u64             data64[2];
+};
+
+struct ib_sa_query;
+
+void ib_sa_cancel_query(int id, struct ib_sa_query *query);
+
+int ib_sa_path_rec_get(struct ib_device *device, u8 port_num,
+                       struct ib_sa_path_rec *rec,
+                       ib_sa_comp_mask comp_mask,
+                       int timeout_ms, unsigned int __nocast gfp_mask,
+                       void (*callback)(int status,
+                                        struct ib_sa_path_rec *resp,
+                                        void *context),
+                       void *context,
+                       struct ib_sa_query **query);
+
+int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num,
+                             u8 method,
+                             struct ib_sa_mcmember_rec *rec,
+                             ib_sa_comp_mask comp_mask,
+                             int timeout_ms, unsigned int __nocast gfp_mask,
+                             void (*callback)(int status,
+                                              struct ib_sa_mcmember_rec *resp,
+                                              void *context),
+                             void *context,
+                             struct ib_sa_query **query);
+
+int ib_sa_service_rec_query(struct ib_device *device, u8 port_num,
+                         u8 method,
+                         struct ib_sa_service_rec *rec,
+                         ib_sa_comp_mask comp_mask,
+                         int timeout_ms, unsigned int __nocast gfp_mask,
+                         void (*callback)(int status,
+                                          struct ib_sa_service_rec *resp,
+                                          void *context),
+                         void *context,
+                         struct ib_sa_query **sa_query);
+
+/**
+ * ib_sa_mcmember_rec_set - Start an MCMember set query
+ * @device:device to send query on
+ * @port_num: port number to send query on
+ * @rec:MCMember Record to send in query
+ * @comp_mask:component mask to send in query
+ * @timeout_ms:time to wait for response
+ * @gfp_mask:GFP mask to use for internal allocations
+ * @callback:function called when query completes, times out or is
+ * canceled
+ * @context:opaque user context passed to callback
+ * @sa_query:query context, used to cancel query
+ *
+ * Send an MCMember Set query to the SA (eg to join a multicast
+ * group).  The callback function will be called when the query
+ * completes (or fails); status is 0 for a successful response, -EINTR
+ * if the query is canceled, -ETIMEDOUT is the query timed out, or
+ * -EIO if an error occurred sending the query.  The resp parameter of
+ * the callback is only valid if status is 0.
+ *
+ * If the return value of ib_sa_mcmember_rec_set() is negative, it is
+ * an error code.  Otherwise it is a query ID that can be used to
+ * cancel the query.
+ */
+static inline int
+ib_sa_mcmember_rec_set(struct ib_device *device, u8 port_num,
+                       struct ib_sa_mcmember_rec *rec,
+                       ib_sa_comp_mask comp_mask,
+                       int timeout_ms, unsigned int __nocast gfp_mask,
+                       void (*callback)(int status,
+                                        struct ib_sa_mcmember_rec *resp,
+                                        void *context),
+                       void *context,
+                       struct ib_sa_query **query)
+{
+        return ib_sa_mcmember_rec_query(device, port_num,
+                                        IB_MGMT_METHOD_SET,
+                                        rec, comp_mask,
+                                        timeout_ms, gfp_mask, callback,
+                                        context, query);
+}
+
+/**
+ * ib_sa_mcmember_rec_delete - Start an MCMember delete query
+ * @device:device to send query on
+ * @port_num: port number to send query on
+ * @rec:MCMember Record to send in query
+ * @comp_mask:component mask to send in query
+ * @timeout_ms:time to wait for response
+ * @gfp_mask:GFP mask to use for internal allocations
+ * @callback:function called when query completes, times out or is
+ * canceled
+ * @context:opaque user context passed to callback
+ * @sa_query:query context, used to cancel query
+ *
+ * Send an MCMember Delete query to the SA (eg to leave a multicast
+ * group).  The callback function will be called when the query
+ * completes (or fails); status is 0 for a successful response, -EINTR
+ * if the query is canceled, -ETIMEDOUT is the query timed out, or
+ * -EIO if an error occurred sending the query.  The resp parameter of
+ * the callback is only valid if status is 0.
+ *
+ * If the return value of ib_sa_mcmember_rec_delete() is negative, it
+ * is an error code.  Otherwise it is a query ID that can be used to
+ * cancel the query.
+ */
+static inline int
+ib_sa_mcmember_rec_delete(struct ib_device *device, u8 port_num,
+                          struct ib_sa_mcmember_rec *rec,
+                          ib_sa_comp_mask comp_mask,
+                          int timeout_ms, unsigned int __nocast gfp_mask,
+                          void (*callback)(int status,
+                                           struct ib_sa_mcmember_rec *resp,
+                                           void *context),
+                          void *context,
+                          struct ib_sa_query **query)
+{
+        return ib_sa_mcmember_rec_query(device, port_num,
+                                        IB_SA_METHOD_DELETE,
+                                        rec, comp_mask,
+                                        timeout_ms, gfp_mask, callback,
+                                        context, query);
+}
+
+
+#endif /* IB_SA_H */
diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h
new file mode 100644
index 000000000000..87f60737f695
--- /dev/null
+++ b/include/rdma/ib_smi.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2004 Mellanox Technologies Ltd.  All rights reserved.
+ * Copyright (c) 2004 Infinicon Corporation.  All rights reserved.
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_smi.h 1389 2004-12-27 22:56:47Z roland $
+ */
+
+#if !defined( IB_SMI_H )
+#define IB_SMI_H
+
+#include <rdma/ib_mad.h>
+
+#define IB_SMP_DATA_SIZE                        64
+#define IB_SMP_MAX_PATH_HOPS                    64
+
+struct ib_smp {
+        u8      base_version;
+        u8      mgmt_class;
+        u8      class_version;
+        u8      method;
+        __be16  status;
+        u8      hop_ptr;
+        u8      hop_cnt;
+        __be64  tid;
+        __be16  attr_id;
+        __be16  resv;
+        __be32  attr_mod;
+        __be64  mkey;
+        __be16  dr_slid;
+        __be16  dr_dlid;
+        u8      reserved[28];
+        u8      data[IB_SMP_DATA_SIZE];
+        u8      initial_path[IB_SMP_MAX_PATH_HOPS];
+        u8      return_path[IB_SMP_MAX_PATH_HOPS];
+} __attribute__ ((packed));
+
+#define IB_SMP_DIRECTION                        __constant_htons(0x8000)
+
+/* Subnet management attributes */
+#define IB_SMP_ATTR_NOTICE                      __constant_htons(0x0002)
+#define IB_SMP_ATTR_NODE_DESC                   __constant_htons(0x0010)
+#define IB_SMP_ATTR_NODE_INFO                   __constant_htons(0x0011)
+#define IB_SMP_ATTR_SWITCH_INFO                 __constant_htons(0x0012)
+#define IB_SMP_ATTR_GUID_INFO                   __constant_htons(0x0014)
+#define IB_SMP_ATTR_PORT_INFO                   __constant_htons(0x0015)
+#define IB_SMP_ATTR_PKEY_TABLE                  __constant_htons(0x0016)
+#define IB_SMP_ATTR_SL_TO_VL_TABLE              __constant_htons(0x0017)
+#define IB_SMP_ATTR_VL_ARB_TABLE                __constant_htons(0x0018)
+#define IB_SMP_ATTR_LINEAR_FORWARD_TABLE        __constant_htons(0x0019)
+#define IB_SMP_ATTR_RANDOM_FORWARD_TABLE        __constant_htons(0x001A)
+#define IB_SMP_ATTR_MCAST_FORWARD_TABLE         __constant_htons(0x001B)
+#define IB_SMP_ATTR_SM_INFO                     __constant_htons(0x0020)
+#define IB_SMP_ATTR_VENDOR_DIAG                 __constant_htons(0x0030)
+#define IB_SMP_ATTR_LED_INFO                    __constant_htons(0x0031)
+#define IB_SMP_ATTR_VENDOR_MASK                 __constant_htons(0xFF00)
+
+static inline u8
+ib_get_smp_direction(struct ib_smp *smp)
+{
+        return ((smp->status & IB_SMP_DIRECTION) == IB_SMP_DIRECTION);
+}
+
+#endif /* IB_SMI_H */
diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h
new file mode 100644
index 000000000000..72182d16778b
--- /dev/null
+++ b/include/rdma/ib_user_cm.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_user_cm.h 2576 2005-06-09 17:00:30Z libor $
+ */
+
+#ifndef IB_USER_CM_H
+#define IB_USER_CM_H
+
+#include <linux/types.h>
+
+#define IB_USER_CM_ABI_VERSION 1
+
+enum {
+        IB_USER_CM_CMD_CREATE_ID,
+        IB_USER_CM_CMD_DESTROY_ID,
+        IB_USER_CM_CMD_ATTR_ID,
+
+        IB_USER_CM_CMD_LISTEN,
+        IB_USER_CM_CMD_ESTABLISH,
+
+        IB_USER_CM_CMD_SEND_REQ,
+        IB_USER_CM_CMD_SEND_REP,
+        IB_USER_CM_CMD_SEND_RTU,
+        IB_USER_CM_CMD_SEND_DREQ,
+        IB_USER_CM_CMD_SEND_DREP,
+        IB_USER_CM_CMD_SEND_REJ,
+        IB_USER_CM_CMD_SEND_MRA,
+        IB_USER_CM_CMD_SEND_LAP,
+        IB_USER_CM_CMD_SEND_APR,
+        IB_USER_CM_CMD_SEND_SIDR_REQ,
+        IB_USER_CM_CMD_SEND_SIDR_REP,
+
+        IB_USER_CM_CMD_EVENT,
+};
+/*
+ * command ABI structures.
+ */
+struct ib_ucm_cmd_hdr {
+        __u32 cmd;
+        __u16 in;
+        __u16 out;
+};
+
+struct ib_ucm_create_id {
+        __u64 response;
+};
+
+struct ib_ucm_create_id_resp {
+        __u32 id;
+};
+
+struct ib_ucm_destroy_id {
+        __u32 id;
+};
+
+struct ib_ucm_attr_id {
+        __u64 response;
+        __u32 id;
+};
+
+struct ib_ucm_attr_id_resp {
+        __be64 service_id;
+        __be64 service_mask;
+        __be32 local_id;
+        __be32 remote_id;
+};
+
+struct ib_ucm_listen {
+        __be64 service_id;
+        __be64 service_mask;
+        __u32 id;
+};
+
+struct ib_ucm_establish {
+        __u32 id;
+};
+
+struct ib_ucm_private_data {
+        __u64 data;
+        __u32 id;
+        __u8  len;
+        __u8  reserved[3];
+};
+
+struct ib_ucm_path_rec {
+        __u8  dgid[16];
+        __u8  sgid[16];
+        __be16 dlid;
+        __be16 slid;
+        __u32 raw_traffic;
+        __be32 flow_label;
+        __u32 reversible;
+        __u32 mtu;
+        __be16 pkey;
+        __u8  hop_limit;
+        __u8  traffic_class;
+        __u8  numb_path;
+        __u8  sl;
+        __u8  mtu_selector;
+        __u8  rate_selector;
+        __u8  rate;
+        __u8  packet_life_time_selector;
+        __u8  packet_life_time;
+        __u8  preference;
+};
+
+struct ib_ucm_req {
+        __u32 id;
+        __u32 qpn;
+        __u32 qp_type;
+        __u32 psn;
+        __be64 sid;
+        __u64 data;
+        __u64 primary_path;
+        __u64 alternate_path;
+        __u8  len;
+        __u8  peer_to_peer;
+        __u8  responder_resources;
+        __u8  initiator_depth;
+        __u8  remote_cm_response_timeout;
+        __u8  flow_control;
+        __u8  local_cm_response_timeout;
+        __u8  retry_count;
+        __u8  rnr_retry_count;
+        __u8  max_cm_retries;
+        __u8  srq;
+        __u8  reserved[1];
+};
+
+struct ib_ucm_rep {
+        __u64 data;
+        __u32 id;
+        __u32 qpn;
+        __u32 psn;
+        __u8  len;
+        __u8  responder_resources;
+        __u8  initiator_depth;
+        __u8  target_ack_delay;
+        __u8  failover_accepted;
+        __u8  flow_control;
+        __u8  rnr_retry_count;
+        __u8  srq;
+};
+
+struct ib_ucm_info {
+        __u32 id;
+        __u32 status;
+        __u64 info;
+        __u64 data;
+        __u8  info_len;
+        __u8  data_len;
+        __u8  reserved[2];
+};
+
+struct ib_ucm_mra {
+        __u64 data;
+        __u32 id;
+        __u8  len;
+        __u8  timeout;
+        __u8  reserved[2];
+};
+
+struct ib_ucm_lap {
+        __u64 path;
+        __u64 data;
+        __u32 id;
+        __u8  len;
+        __u8  reserved[3];
+};
+
+struct ib_ucm_sidr_req {
+        __u32 id;
+        __u32 timeout;
+        __be64 sid;
+        __u64 data;
+        __u64 path;
+        __u16 pkey;
+        __u8  len;
+        __u8  max_cm_retries;
+};
+
+struct ib_ucm_sidr_rep {
+        __u32 id;
+        __u32 qpn;
+        __u32 qkey;
+        __u32 status;
+        __u64 info;
+        __u64 data;
+        __u8  info_len;
+        __u8  data_len;
+        __u8  reserved[2];
+};
+/*
+ * event notification ABI structures.
+ */
+struct ib_ucm_event_get {
+        __u64 response;
+        __u64 data;
+        __u64 info;
+        __u8  data_len;
+        __u8  info_len;
+        __u8  reserved[2];
+};
+
+struct ib_ucm_req_event_resp {
+        __u32                  listen_id;
+        /* device */
+        /* port */
+        struct ib_ucm_path_rec primary_path;
+        struct ib_ucm_path_rec alternate_path;
+        __be64                 remote_ca_guid;
+        __u32                  remote_qkey;
+        __u32                  remote_qpn;
+        __u32                  qp_type;
+        __u32                  starting_psn;
+        __u8  responder_resources;
+        __u8  initiator_depth;
+        __u8  local_cm_response_timeout;
+        __u8  flow_control;
+        __u8  remote_cm_response_timeout;
+        __u8  retry_count;
+        __u8  rnr_retry_count;
+        __u8  srq;
+};
+
+struct ib_ucm_rep_event_resp {
+        __be64 remote_ca_guid;
+        __u32 remote_qkey;
+        __u32 remote_qpn;
+        __u32 starting_psn;
+        __u8  responder_resources;
+        __u8  initiator_depth;
+        __u8  target_ack_delay;
+        __u8  failover_accepted;
+        __u8  flow_control;
+        __u8  rnr_retry_count;
+        __u8  srq;
+        __u8  reserved[1];
+};
+
+struct ib_ucm_rej_event_resp {
+        __u32 reason;
+        /* ari in ib_ucm_event_get info field. */
+};
+
+struct ib_ucm_mra_event_resp {
+        __u8  timeout;
+        __u8  reserved[3];
+};
+
+struct ib_ucm_lap_event_resp {
+        struct ib_ucm_path_rec path;
+};
+
+struct ib_ucm_apr_event_resp {
+        __u32 status;
+        /* apr info in ib_ucm_event_get info field. */
+};
+
+struct ib_ucm_sidr_req_event_resp {
+        __u32 listen_id;
+        /* device */
+        /* port */
+        __u16 pkey;
+        __u8  reserved[2];
+};
+
+struct ib_ucm_sidr_rep_event_resp {
+        __u32 status;
+        __u32 qkey;
+        __u32 qpn;
+        /* info in ib_ucm_event_get info field. */
+};
+
+#define IB_UCM_PRES_DATA      0x01
+#define IB_UCM_PRES_INFO      0x02
+#define IB_UCM_PRES_PRIMARY   0x04
+#define IB_UCM_PRES_ALTERNATE 0x08
+
+struct ib_ucm_event_resp {
+        __u32 id;
+        __u32 event;
+        __u32 present;
+        union {
+                struct ib_ucm_req_event_resp req_resp;
+                struct ib_ucm_rep_event_resp rep_resp;
+                struct ib_ucm_rej_event_resp rej_resp;
+                struct ib_ucm_mra_event_resp mra_resp;
+                struct ib_ucm_lap_event_resp lap_resp;
+                struct ib_ucm_apr_event_resp apr_resp;
+
+                struct ib_ucm_sidr_req_event_resp sidr_req_resp;
+                struct ib_ucm_sidr_rep_event_resp sidr_rep_resp;
+
+                __u32                             send_status;
+        } u;
+};
+
+#endif /* IB_USER_CM_H */
diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h
new file mode 100644
index 000000000000..44537aa32e62
--- /dev/null
+++ b/include/rdma/ib_user_mad.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $
+ */
+
+#ifndef IB_USER_MAD_H
+#define IB_USER_MAD_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/*
+ * Increment this value if any changes that break userspace ABI
+ * compatibility are made.
+ */
+#define IB_USER_MAD_ABI_VERSION 5
+
+/*
+ * Make sure that all structs defined in this file remain laid out so
+ * that they pack the same way on 32-bit and 64-bit architectures (to
+ * avoid incompatibility between 32-bit userspace and 64-bit kernels).
+ */
+
+/**
+ * ib_user_mad_hdr - MAD packet header
+ * @id - ID of agent MAD received with/to be sent with
+ * @status - 0 on successful receive, ETIMEDOUT if no response
+ *   received (transaction ID in data[] will be set to TID of original
+ *   request) (ignored on send)
+ * @timeout_ms - Milliseconds to wait for response (unset on receive)
+ * @retries - Number of automatic retries to attempt
+ * @qpn - Remote QP number received from/to be sent to
+ * @qkey - Remote Q_Key to be sent with (unset on receive)
+ * @lid - Remote lid received from/to be sent to
+ * @sl - Service level received with/to be sent with
+ * @path_bits - Local path bits received with/to be sent with
+ * @grh_present - If set, GRH was received/should be sent
+ * @gid_index - Local GID index to send with (unset on receive)
+ * @hop_limit - Hop limit in GRH
+ * @traffic_class - Traffic class in GRH
+ * @gid - Remote GID in GRH
+ * @flow_label - Flow label in GRH
+ */
+struct ib_user_mad_hdr {
+        __u32   id;
+        __u32   status;
+        __u32   timeout_ms;
+        __u32   retries;
+        __u32   length;
+        __be32  qpn;
+        __be32  qkey;
+        __be16  lid;
+        __u8    sl;
+        __u8    path_bits;
+        __u8    grh_present;
+        __u8    gid_index;
+        __u8    hop_limit;
+        __u8    traffic_class;
+        __u8    gid[16];
+        __be32  flow_label;
+};
+
+/**
+ * ib_user_mad - MAD packet
+ * @hdr - MAD packet header
+ * @data - Contents of MAD
+ *
+ */
+struct ib_user_mad {
+        struct ib_user_mad_hdr hdr;
+        __u8    data[0];
+};
+
+/**
+ * ib_user_mad_reg_req - MAD registration request
+ * @id - Set by the kernel; used to identify agent in future requests.
+ * @qpn - Queue pair number; must be 0 or 1.
+ * @method_mask - The caller will receive unsolicited MADs for any method
+ *   where @method_mask = 1.
+ * @mgmt_class - Indicates which management class of MADs should be receive
+ *   by the caller.  This field is only required if the user wishes to
+ *   receive unsolicited MADs, otherwise it should be 0.
+ * @mgmt_class_version - Indicates which version of MADs for the given
+ *   management class to receive.
+ * @oui: Indicates IEEE OUI when mgmt_class is a vendor class
+ *   in the range from 0x30 to 0x4f. Otherwise not used.
+ * @rmpp_version: If set, indicates the RMPP version used.
+ *
+ */
+struct ib_user_mad_reg_req {
+        __u32   id;
+        __u32   method_mask[4];
+        __u8    qpn;
+        __u8    mgmt_class;
+        __u8    mgmt_class_version;
+        __u8    oui[3];
+        __u8    rmpp_version;
+};
+
+#define IB_IOCTL_MAGIC          0x1b
+
+#define IB_USER_MAD_REGISTER_AGENT      _IOWR(IB_IOCTL_MAGIC, 1, \
+                                              struct ib_user_mad_reg_req)
+
+#define IB_USER_MAD_UNREGISTER_AGENT    _IOW(IB_IOCTL_MAGIC, 2, __u32)
+
+#endif /* IB_USER_MAD_H */
diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h
new file mode 100644
index 000000000000..7ebb01c8f996
--- /dev/null
+++ b/include/rdma/ib_user_verbs.h
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_user_verbs.h 2708 2005-06-24 17:27:21Z roland $
+ */
+
+#ifndef IB_USER_VERBS_H
+#define IB_USER_VERBS_H
+
+#include <linux/types.h>
+
+/*
+ * Increment this value if any changes that break userspace ABI
+ * compatibility are made.
+ */
+#define IB_USER_VERBS_ABI_VERSION       1
+
+enum {
+        IB_USER_VERBS_CMD_QUERY_PARAMS,
+        IB_USER_VERBS_CMD_GET_CONTEXT,
+        IB_USER_VERBS_CMD_QUERY_DEVICE,
+        IB_USER_VERBS_CMD_QUERY_PORT,
+        IB_USER_VERBS_CMD_QUERY_GID,
+        IB_USER_VERBS_CMD_QUERY_PKEY,
+        IB_USER_VERBS_CMD_ALLOC_PD,
+        IB_USER_VERBS_CMD_DEALLOC_PD,
+        IB_USER_VERBS_CMD_CREATE_AH,
+        IB_USER_VERBS_CMD_MODIFY_AH,
+        IB_USER_VERBS_CMD_QUERY_AH,
+        IB_USER_VERBS_CMD_DESTROY_AH,
+        IB_USER_VERBS_CMD_REG_MR,
+        IB_USER_VERBS_CMD_REG_SMR,
+        IB_USER_VERBS_CMD_REREG_MR,
+        IB_USER_VERBS_CMD_QUERY_MR,
+        IB_USER_VERBS_CMD_DEREG_MR,
+        IB_USER_VERBS_CMD_ALLOC_MW,
+        IB_USER_VERBS_CMD_BIND_MW,
+        IB_USER_VERBS_CMD_DEALLOC_MW,
+        IB_USER_VERBS_CMD_CREATE_CQ,
+        IB_USER_VERBS_CMD_RESIZE_CQ,
+        IB_USER_VERBS_CMD_DESTROY_CQ,
+        IB_USER_VERBS_CMD_POLL_CQ,
+        IB_USER_VERBS_CMD_PEEK_CQ,
+        IB_USER_VERBS_CMD_REQ_NOTIFY_CQ,
+        IB_USER_VERBS_CMD_CREATE_QP,
+        IB_USER_VERBS_CMD_QUERY_QP,
+        IB_USER_VERBS_CMD_MODIFY_QP,
+        IB_USER_VERBS_CMD_DESTROY_QP,
+        IB_USER_VERBS_CMD_POST_SEND,
+        IB_USER_VERBS_CMD_POST_RECV,
+        IB_USER_VERBS_CMD_ATTACH_MCAST,
+        IB_USER_VERBS_CMD_DETACH_MCAST,
+        IB_USER_VERBS_CMD_CREATE_SRQ,
+        IB_USER_VERBS_CMD_MODIFY_SRQ,
+        IB_USER_VERBS_CMD_QUERY_SRQ,
+        IB_USER_VERBS_CMD_DESTROY_SRQ,
+        IB_USER_VERBS_CMD_POST_SRQ_RECV
+};
+
+/*
+ * Make sure that all structs defined in this file remain laid out so
+ * that they pack the same way on 32-bit and 64-bit architectures (to
+ * avoid incompatibility between 32-bit userspace and 64-bit kernels).
+ * In particular do not use pointer types -- pass pointers in __u64
+ * instead.
+ */
+
+struct ib_uverbs_async_event_desc {
+        __u64 element;
+        __u32 event_type;       /* enum ib_event_type */
+        __u32 reserved;
+};
+
+struct ib_uverbs_comp_event_desc {
+        __u64 cq_handle;
+};
+
+/*
+ * All commands from userspace should start with a __u32 command field
+ * followed by __u16 in_words and out_words fields (which give the
+ * length of the command block and response buffer if any in 32-bit
+ * words).  The kernel driver will read these fields first and read
+ * the rest of the command struct based on these value.
+ */
+
+struct ib_uverbs_cmd_hdr {
+        __u32 command;
+        __u16 in_words;
+        __u16 out_words;
+};
+
+/*
+ * No driver_data for "query params" command, since this is intended
+ * to be a core function with no possible device dependence.
+ */
+struct ib_uverbs_query_params {
+        __u64 response;
+};
+
+struct ib_uverbs_query_params_resp {
+        __u32 num_cq_events;
+};
+
+struct ib_uverbs_get_context {
+        __u64 response;
+        __u64 cq_fd_tab;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_get_context_resp {
+        __u32 async_fd;
+        __u32 reserved;
+};
+
+struct ib_uverbs_query_device {
+        __u64 response;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_query_device_resp {
+        __u64 fw_ver;
+        __be64 node_guid;
+        __be64 sys_image_guid;
+        __u64 max_mr_size;
+        __u64 page_size_cap;
+        __u32 vendor_id;
+        __u32 vendor_part_id;
+        __u32 hw_ver;
+        __u32 max_qp;
+        __u32 max_qp_wr;
+        __u32 device_cap_flags;
+        __u32 max_sge;
+        __u32 max_sge_rd;
+        __u32 max_cq;
+        __u32 max_cqe;
+        __u32 max_mr;
+        __u32 max_pd;
+        __u32 max_qp_rd_atom;
+        __u32 max_ee_rd_atom;
+        __u32 max_res_rd_atom;
+        __u32 max_qp_init_rd_atom;
+        __u32 max_ee_init_rd_atom;
+        __u32 atomic_cap;
+        __u32 max_ee;
+        __u32 max_rdd;
+        __u32 max_mw;
+        __u32 max_raw_ipv6_qp;
+        __u32 max_raw_ethy_qp;
+        __u32 max_mcast_grp;
+        __u32 max_mcast_qp_attach;
+        __u32 max_total_mcast_qp_attach;
+        __u32 max_ah;
+        __u32 max_fmr;
+        __u32 max_map_per_fmr;
+        __u32 max_srq;
+        __u32 max_srq_wr;
+        __u32 max_srq_sge;
+        __u16 max_pkeys;
+        __u8  local_ca_ack_delay;
+        __u8  phys_port_cnt;
+        __u8  reserved[4];
+};
+
+struct ib_uverbs_query_port {
+        __u64 response;
+        __u8  port_num;
+        __u8  reserved[7];
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_query_port_resp {
+        __u32 port_cap_flags;
+        __u32 max_msg_sz;
+        __u32 bad_pkey_cntr;
+        __u32 qkey_viol_cntr;
+        __u32 gid_tbl_len;
+        __u16 pkey_tbl_len;
+        __u16 lid;
+        __u16 sm_lid;
+        __u8  state;
+        __u8  max_mtu;
+        __u8  active_mtu;
+        __u8  lmc;
+        __u8  max_vl_num;
+        __u8  sm_sl;
+        __u8  subnet_timeout;
+        __u8  init_type_reply;
+        __u8  active_width;
+        __u8  active_speed;
+        __u8  phys_state;
+        __u8  reserved[3];
+};
+
+struct ib_uverbs_query_gid {
+        __u64 response;
+        __u8  port_num;
+        __u8  index;
+        __u8  reserved[6];
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_query_gid_resp {
+        __u8  gid[16];
+};
+
+struct ib_uverbs_query_pkey {
+        __u64 response;
+        __u8  port_num;
+        __u8  index;
+        __u8  reserved[6];
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_query_pkey_resp {
+        __u16 pkey;
+        __u16 reserved;
+};
+
+struct ib_uverbs_alloc_pd {
+        __u64 response;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_alloc_pd_resp {
+        __u32 pd_handle;
+};
+
+struct ib_uverbs_dealloc_pd {
+        __u32 pd_handle;
+};
+
+struct ib_uverbs_reg_mr {
+        __u64 response;
+        __u64 start;
+        __u64 length;
+        __u64 hca_va;
+        __u32 pd_handle;
+        __u32 access_flags;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_reg_mr_resp {
+        __u32 mr_handle;
+        __u32 lkey;
+        __u32 rkey;
+};
+
+struct ib_uverbs_dereg_mr {
+        __u32 mr_handle;
+};
+
+struct ib_uverbs_create_cq {
+        __u64 response;
+        __u64 user_handle;
+        __u32 cqe;
+        __u32 event_handler;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_create_cq_resp {
+        __u32 cq_handle;
+        __u32 cqe;
+};
+
+struct ib_uverbs_destroy_cq {
+        __u32 cq_handle;
+};
+
+struct ib_uverbs_create_qp {
+        __u64 response;
+        __u64 user_handle;
+        __u32 pd_handle;
+        __u32 send_cq_handle;
+        __u32 recv_cq_handle;
+        __u32 srq_handle;
+        __u32 max_send_wr;
+        __u32 max_recv_wr;
+        __u32 max_send_sge;
+        __u32 max_recv_sge;
+        __u32 max_inline_data;
+        __u8  sq_sig_all;
+        __u8  qp_type;
+        __u8  is_srq;
+        __u8  reserved;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_create_qp_resp {
+        __u32 qp_handle;
+        __u32 qpn;
+};
+
+/*
+ * This struct needs to remain a multiple of 8 bytes to keep the
+ * alignment of the modify QP parameters.
+ */
+struct ib_uverbs_qp_dest {
+        __u8  dgid[16];
+        __u32 flow_label;
+        __u16 dlid;
+        __u16 reserved;
+        __u8  sgid_index;
+        __u8  hop_limit;
+        __u8  traffic_class;
+        __u8  sl;
+        __u8  src_path_bits;
+        __u8  static_rate;
+        __u8  is_global;
+        __u8  port_num;
+};
+
+struct ib_uverbs_modify_qp {
+        struct ib_uverbs_qp_dest dest;
+        struct ib_uverbs_qp_dest alt_dest;
+        __u32 qp_handle;
+        __u32 attr_mask;
+        __u32 qkey;
+        __u32 rq_psn;
+        __u32 sq_psn;
+        __u32 dest_qp_num;
+        __u32 qp_access_flags;
+        __u16 pkey_index;
+        __u16 alt_pkey_index;
+        __u8  qp_state;
+        __u8  cur_qp_state;
+        __u8  path_mtu;
+        __u8  path_mig_state;
+        __u8  en_sqd_async_notify;
+        __u8  max_rd_atomic;
+        __u8  max_dest_rd_atomic;
+        __u8  min_rnr_timer;
+        __u8  port_num;
+        __u8  timeout;
+        __u8  retry_cnt;
+        __u8  rnr_retry;
+        __u8  alt_port_num;
+        __u8  alt_timeout;
+        __u8  reserved[2];
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_modify_qp_resp {
+};
+
+struct ib_uverbs_destroy_qp {
+        __u32 qp_handle;
+};
+
+struct ib_uverbs_attach_mcast {
+        __u8  gid[16];
+        __u32 qp_handle;
+        __u16 mlid;
+        __u16 reserved;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_detach_mcast {
+        __u8  gid[16];
+        __u32 qp_handle;
+        __u16 mlid;
+        __u16 reserved;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_create_srq {
+        __u64 response;
+        __u64 user_handle;
+        __u32 pd_handle;
+        __u32 max_wr;
+        __u32 max_sge;
+        __u32 srq_limit;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_create_srq_resp {
+        __u32 srq_handle;
+};
+
+struct ib_uverbs_modify_srq {
+        __u32 srq_handle;
+        __u32 attr_mask;
+        __u32 max_wr;
+        __u32 max_sge;
+        __u32 srq_limit;
+        __u32 reserved;
+        __u64 driver_data[0];
+};
+
+struct ib_uverbs_destroy_srq {
+        __u32 srq_handle;
+};
+
+#endif /* IB_USER_VERBS_H */
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
new file mode 100644
index 000000000000..e16cf94870f2
--- /dev/null
+++ b/include/rdma/ib_verbs.h
@@ -0,0 +1,1461 @@
+/*
+ * Copyright (c) 2004 Mellanox Technologies Ltd.  All rights reserved.
+ * Copyright (c) 2004 Infinicon Corporation.  All rights reserved.
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_verbs.h 1349 2004-12-16 21:09:43Z roland $
+ */
+
+#if !defined(IB_VERBS_H)
+#define IB_VERBS_H
+
+#include <linux/types.h>
+#include <linux/device.h>
+
+#include <asm/atomic.h>
+#include <asm/scatterlist.h>
+#include <asm/uaccess.h>
+
+union ib_gid {
+        u8      raw[16];
+        struct {
+                __be64  subnet_prefix;
+                __be64  interface_id;
+        } global;
+};
+
+enum ib_node_type {
+        IB_NODE_CA      = 1,
+        IB_NODE_SWITCH,
+        IB_NODE_ROUTER
+};
+
+enum ib_device_cap_flags {
+        IB_DEVICE_RESIZE_MAX_WR         = 1,
+        IB_DEVICE_BAD_PKEY_CNTR         = (1<<1),
+        IB_DEVICE_BAD_QKEY_CNTR         = (1<<2),
+        IB_DEVICE_RAW_MULTI             = (1<<3),
+        IB_DEVICE_AUTO_PATH_MIG         = (1<<4),
+        IB_DEVICE_CHANGE_PHY_PORT       = (1<<5),
+        IB_DEVICE_UD_AV_PORT_ENFORCE    = (1<<6),
+        IB_DEVICE_CURR_QP_STATE_MOD     = (1<<7),
+        IB_DEVICE_SHUTDOWN_PORT         = (1<<8),
+        IB_DEVICE_INIT_TYPE             = (1<<9),
+        IB_DEVICE_PORT_ACTIVE_EVENT     = (1<<10),
+        IB_DEVICE_SYS_IMAGE_GUID        = (1<<11),
+        IB_DEVICE_RC_RNR_NAK_GEN        = (1<<12),
+        IB_DEVICE_SRQ_RESIZE            = (1<<13),
+        IB_DEVICE_N_NOTIFY_CQ           = (1<<14),
+};
+
+enum ib_atomic_cap {
+        IB_ATOMIC_NONE,
+        IB_ATOMIC_HCA,
+        IB_ATOMIC_GLOB
+};
+
+struct ib_device_attr {
+        u64                     fw_ver;
+        __be64                  node_guid;
+        __be64                  sys_image_guid;
+        u64                     max_mr_size;
+        u64                     page_size_cap;
+        u32                     vendor_id;
+        u32                     vendor_part_id;
+        u32                     hw_ver;
+        int                     max_qp;
+        int                     max_qp_wr;
+        int                     device_cap_flags;
+        int                     max_sge;
+        int                     max_sge_rd;
+        int                     max_cq;
+        int                     max_cqe;
+        int                     max_mr;
+        int                     max_pd;
+        int                     max_qp_rd_atom;
+        int                     max_ee_rd_atom;
+        int                     max_res_rd_atom;
+        int                     max_qp_init_rd_atom;
+        int                     max_ee_init_rd_atom;
+        enum ib_atomic_cap      atomic_cap;
+        int                     max_ee;
+        int                     max_rdd;
+        int                     max_mw;
+        int                     max_raw_ipv6_qp;
+        int                     max_raw_ethy_qp;
+        int                     max_mcast_grp;
+        int                     max_mcast_qp_attach;
+        int                     max_total_mcast_qp_attach;
+        int                     max_ah;
+        int                     max_fmr;
+        int                     max_map_per_fmr;
+        int                     max_srq;
+        int                     max_srq_wr;
+        int                     max_srq_sge;
+        u16                     max_pkeys;
+        u8                      local_ca_ack_delay;
+};
+
+enum ib_mtu {
+        IB_MTU_256  = 1,
+        IB_MTU_512  = 2,
+        IB_MTU_1024 = 3,
+        IB_MTU_2048 = 4,
+        IB_MTU_4096 = 5
+};
+
+static inline int ib_mtu_enum_to_int(enum ib_mtu mtu)
+{
+        switch (mtu) {
+        case IB_MTU_256:  return  256;
+        case IB_MTU_512:  return  512;
+        case IB_MTU_1024: return 1024;
+        case IB_MTU_2048: return 2048;
+        case IB_MTU_4096: return 4096;
+        default:          return -1;
+        }
+}
+
+enum ib_port_state {
+        IB_PORT_NOP             = 0,
+        IB_PORT_DOWN            = 1,
+        IB_PORT_INIT            = 2,
+        IB_PORT_ARMED           = 3,
+        IB_PORT_ACTIVE          = 4,
+        IB_PORT_ACTIVE_DEFER    = 5
+};
+
+enum ib_port_cap_flags {
+        IB_PORT_SM                              = 1 <<  1,
+        IB_PORT_NOTICE_SUP                      = 1 <<  2,
+        IB_PORT_TRAP_SUP                        = 1 <<  3,
+        IB_PORT_OPT_IPD_SUP                     = 1 <<  4,
+        IB_PORT_AUTO_MIGR_SUP                   = 1 <<  5,
+        IB_PORT_SL_MAP_SUP                      = 1 <<  6,
+        IB_PORT_MKEY_NVRAM                      = 1 <<  7,
+        IB_PORT_PKEY_NVRAM                      = 1 <<  8,
+        IB_PORT_LED_INFO_SUP                    = 1 <<  9,
+        IB_PORT_SM_DISABLED                     = 1 << 10,
+        IB_PORT_SYS_IMAGE_GUID_SUP              = 1 << 11,
+        IB_PORT_PKEY_SW_EXT_PORT_TRAP_SUP       = 1 << 12,
+        IB_PORT_CM_SUP                          = 1 << 16,
+        IB_PORT_SNMP_TUNNEL_SUP                 = 1 << 17,
+        IB_PORT_REINIT_SUP                      = 1 << 18,
+        IB_PORT_DEVICE_MGMT_SUP                 = 1 << 19,
+        IB_PORT_VENDOR_CLASS_SUP                = 1 << 20,
+        IB_PORT_DR_NOTICE_SUP                   = 1 << 21,
+        IB_PORT_CAP_MASK_NOTICE_SUP             = 1 << 22,
+        IB_PORT_BOOT_MGMT_SUP                   = 1 << 23,
+        IB_PORT_LINK_LATENCY_SUP                = 1 << 24,
+        IB_PORT_CLIENT_REG_SUP                  = 1 << 25
+};
+
+enum ib_port_width {
+        IB_WIDTH_1X     = 1,
+        IB_WIDTH_4X     = 2,
+        IB_WIDTH_8X     = 4,
+        IB_WIDTH_12X    = 8
+};
+
+static inline int ib_width_enum_to_int(enum ib_port_width width)
+{
+        switch (width) {
+        case IB_WIDTH_1X:  return  1;
+        case IB_WIDTH_4X:  return  4;
+        case IB_WIDTH_8X:  return  8;
+        case IB_WIDTH_12X: return 12;
+        default:          return -1;
+        }
+}
+
+struct ib_port_attr {
+        enum ib_port_state      state;
+        enum ib_mtu             max_mtu;
+        enum ib_mtu             active_mtu;
+        int                     gid_tbl_len;
+        u32                     port_cap_flags;
+        u32                     max_msg_sz;
+        u32                     bad_pkey_cntr;
+        u32                     qkey_viol_cntr;
+        u16                     pkey_tbl_len;
+        u16                     lid;
+        u16                     sm_lid;
+        u8                      lmc;
+        u8                      max_vl_num;
+        u8                      sm_sl;
+        u8                      subnet_timeout;
+        u8                      init_type_reply;
+        u8                      active_width;
+        u8                      active_speed;
+        u8                      phys_state;
+};
+
+enum ib_device_modify_flags {
+        IB_DEVICE_MODIFY_SYS_IMAGE_GUID = 1
+};
+
+struct ib_device_modify {
+        u64     sys_image_guid;
+};
+
+enum ib_port_modify_flags {
+        IB_PORT_SHUTDOWN                = 1,
+        IB_PORT_INIT_TYPE               = (1<<2),
+        IB_PORT_RESET_QKEY_CNTR         = (1<<3)
+};
+
+struct ib_port_modify {
+        u32     set_port_cap_mask;
+        u32     clr_port_cap_mask;
+        u8      init_type;
+};
+
+enum ib_event_type {
+        IB_EVENT_CQ_ERR,
+        IB_EVENT_QP_FATAL,
+        IB_EVENT_QP_REQ_ERR,
+        IB_EVENT_QP_ACCESS_ERR,
+        IB_EVENT_COMM_EST,
+        IB_EVENT_SQ_DRAINED,
+        IB_EVENT_PATH_MIG,
+        IB_EVENT_PATH_MIG_ERR,
+        IB_EVENT_DEVICE_FATAL,
+        IB_EVENT_PORT_ACTIVE,
+        IB_EVENT_PORT_ERR,
+        IB_EVENT_LID_CHANGE,
+        IB_EVENT_PKEY_CHANGE,
+        IB_EVENT_SM_CHANGE,
+        IB_EVENT_SRQ_ERR,
+        IB_EVENT_SRQ_LIMIT_REACHED,
+        IB_EVENT_QP_LAST_WQE_REACHED
+};
+
+struct ib_event {
+        struct ib_device        *device;
+        union {
+                struct ib_cq    *cq;
+                struct ib_qp    *qp;
+                struct ib_srq   *srq;
+                u8              port_num;
+        } element;
+        enum ib_event_type      event;
+};
+
+struct ib_event_handler {
+        struct ib_device *device;
+        void            (*handler)(struct ib_event_handler *, struct ib_event *);
+        struct list_head  list;
+};
+
+#define INIT_IB_EVENT_HANDLER(_ptr, _device, _handler)          \
+        do {                                                    \
+                (_ptr)->device  = _device;                      \
+                (_ptr)->handler = _handler;                     \
+                INIT_LIST_HEAD(&(_ptr)->list);                  \
+        } while (0)
+
+struct ib_global_route {
+        union ib_gid    dgid;
+        u32             flow_label;
+        u8              sgid_index;
+        u8              hop_limit;
+        u8              traffic_class;
+};
+
+struct ib_grh {
+        __be32          version_tclass_flow;
+        __be16          paylen;
+        u8              next_hdr;
+        u8              hop_limit;
+        union ib_gid    sgid;
+        union ib_gid    dgid;
+};
+
+enum {
+        IB_MULTICAST_QPN = 0xffffff
+};
+
+#define IB_LID_PERMISSIVE       __constant_htons(0xFFFF)
+
+enum ib_ah_flags {
+        IB_AH_GRH       = 1
+};
+
+struct ib_ah_attr {
+        struct ib_global_route  grh;
+        u16                     dlid;
+        u8                      sl;
+        u8                      src_path_bits;
+        u8                      static_rate;
+        u8                      ah_flags;
+        u8                      port_num;
+};
+
+enum ib_wc_status {
+        IB_WC_SUCCESS,
+        IB_WC_LOC_LEN_ERR,
+        IB_WC_LOC_QP_OP_ERR,
+        IB_WC_LOC_EEC_OP_ERR,
+        IB_WC_LOC_PROT_ERR,
+        IB_WC_WR_FLUSH_ERR,
+        IB_WC_MW_BIND_ERR,
+        IB_WC_BAD_RESP_ERR,
+        IB_WC_LOC_ACCESS_ERR,
+        IB_WC_REM_INV_REQ_ERR,
+        IB_WC_REM_ACCESS_ERR,
+        IB_WC_REM_OP_ERR,
+        IB_WC_RETRY_EXC_ERR,
+        IB_WC_RNR_RETRY_EXC_ERR,
+        IB_WC_LOC_RDD_VIOL_ERR,
+        IB_WC_REM_INV_RD_REQ_ERR,
+        IB_WC_REM_ABORT_ERR,
+        IB_WC_INV_EECN_ERR,
+        IB_WC_INV_EEC_STATE_ERR,
+        IB_WC_FATAL_ERR,
+        IB_WC_RESP_TIMEOUT_ERR,
+        IB_WC_GENERAL_ERR
+};
+
+enum ib_wc_opcode {
+        IB_WC_SEND,
+        IB_WC_RDMA_WRITE,
+        IB_WC_RDMA_READ,
+        IB_WC_COMP_SWAP,
+        IB_WC_FETCH_ADD,
+        IB_WC_BIND_MW,
+/*
+ * Set value of IB_WC_RECV so consumers can test if a completion is a
+ * receive by testing (opcode & IB_WC_RECV).
+ */
+        IB_WC_RECV                      = 1 << 7,
+        IB_WC_RECV_RDMA_WITH_IMM
+};
+
+enum ib_wc_flags {
+        IB_WC_GRH               = 1,
+        IB_WC_WITH_IMM          = (1<<1)
+};
+
+struct ib_wc {
+        u64                     wr_id;
+        enum ib_wc_status       status;
+        enum ib_wc_opcode       opcode;
+        u32                     vendor_err;
+        u32                     byte_len;
+        __be32                  imm_data;
+        u32                     qp_num;
+        u32                     src_qp;
+        int                     wc_flags;
+        u16                     pkey_index;
+        u16                     slid;
+        u8                      sl;
+        u8                      dlid_path_bits;
+        u8                      port_num;       /* valid only for DR SMPs on switches */
+};
+
+enum ib_cq_notify {
+        IB_CQ_SOLICITED,
+        IB_CQ_NEXT_COMP
+};
+
+enum ib_srq_attr_mask {
+        IB_SRQ_MAX_WR   = 1 << 0,
+        IB_SRQ_LIMIT    = 1 << 1,
+};
+
+struct ib_srq_attr {
+        u32     max_wr;
+        u32     max_sge;
+        u32     srq_limit;
+};
+
+struct ib_srq_init_attr {
+        void                  (*event_handler)(struct ib_event *, void *);
+        void                   *srq_context;
+        struct ib_srq_attr      attr;
+};
+
+struct ib_qp_cap {
+        u32     max_send_wr;
+        u32     max_recv_wr;
+        u32     max_send_sge;
+        u32     max_recv_sge;
+        u32     max_inline_data;
+};
+
+enum ib_sig_type {
+        IB_SIGNAL_ALL_WR,
+        IB_SIGNAL_REQ_WR
+};
+
+enum ib_qp_type {
+        /*
+         * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries
+         * here (and in that order) since the MAD layer uses them as
+         * indices into a 2-entry table.
+         */
+        IB_QPT_SMI,
+        IB_QPT_GSI,
+
+        IB_QPT_RC,
+        IB_QPT_UC,
+        IB_QPT_UD,
+        IB_QPT_RAW_IPV6,
+        IB_QPT_RAW_ETY
+};
+
+struct ib_qp_init_attr {
+        void                  (*event_handler)(struct ib_event *, void *);
+        void                   *qp_context;
+        struct ib_cq           *send_cq;
+        struct ib_cq           *recv_cq;
+        struct ib_srq          *srq;
+        struct ib_qp_cap        cap;
+        enum ib_sig_type        sq_sig_type;
+        enum ib_qp_type         qp_type;
+        u8                      port_num; /* special QP types only */
+};
+
+enum ib_rnr_timeout {
+        IB_RNR_TIMER_655_36 =  0,
+        IB_RNR_TIMER_000_01 =  1,
+        IB_RNR_TIMER_000_02 =  2,
+        IB_RNR_TIMER_000_03 =  3,
+        IB_RNR_TIMER_000_04 =  4,
+        IB_RNR_TIMER_000_06 =  5,
+        IB_RNR_TIMER_000_08 =  6,
+        IB_RNR_TIMER_000_12 =  7,
+        IB_RNR_TIMER_000_16 =  8,
+        IB_RNR_TIMER_000_24 =  9,
+        IB_RNR_TIMER_000_32 = 10,
+        IB_RNR_TIMER_000_48 = 11,
+        IB_RNR_TIMER_000_64 = 12,
+        IB_RNR_TIMER_000_96 = 13,
+        IB_RNR_TIMER_001_28 = 14,
+        IB_RNR_TIMER_001_92 = 15,
+        IB_RNR_TIMER_002_56 = 16,
+        IB_RNR_TIMER_003_84 = 17,
+        IB_RNR_TIMER_005_12 = 18,
+        IB_RNR_TIMER_007_68 = 19,
+        IB_RNR_TIMER_010_24 = 20,
+        IB_RNR_TIMER_015_36 = 21,
+        IB_RNR_TIMER_020_48 = 22,
+        IB_RNR_TIMER_030_72 = 23,
+        IB_RNR_TIMER_040_96 = 24,
+        IB_RNR_TIMER_061_44 = 25,
+        IB_RNR_TIMER_081_92 = 26,
+        IB_RNR_TIMER_122_88 = 27,
+        IB_RNR_TIMER_163_84 = 28,
+        IB_RNR_TIMER_245_76 = 29,
+        IB_RNR_TIMER_327_68 = 30,
+        IB_RNR_TIMER_491_52 = 31
+};
+
+enum ib_qp_attr_mask {
+        IB_QP_STATE                     = 1,
+        IB_QP_CUR_STATE                 = (1<<1),
+        IB_QP_EN_SQD_ASYNC_NOTIFY       = (1<<2),
+        IB_QP_ACCESS_FLAGS              = (1<<3),
+        IB_QP_PKEY_INDEX                = (1<<4),
+        IB_QP_PORT                      = (1<<5),
+        IB_QP_QKEY                      = (1<<6),
+        IB_QP_AV                        = (1<<7),
+        IB_QP_PATH_MTU                  = (1<<8),
+        IB_QP_TIMEOUT                   = (1<<9),
+        IB_QP_RETRY_CNT                 = (1<<10),
+        IB_QP_RNR_RETRY                 = (1<<11),
+        IB_QP_RQ_PSN                    = (1<<12),
+        IB_QP_MAX_QP_RD_ATOMIC          = (1<<13),
+        IB_QP_ALT_PATH                  = (1<<14),
+        IB_QP_MIN_RNR_TIMER             = (1<<15),
+        IB_QP_SQ_PSN                    = (1<<16),
+        IB_QP_MAX_DEST_RD_ATOMIC        = (1<<17),
+        IB_QP_PATH_MIG_STATE            = (1<<18),
+        IB_QP_CAP                       = (1<<19),
+        IB_QP_DEST_QPN                  = (1<<20)
+};
+
+enum ib_qp_state {
+        IB_QPS_RESET,
+        IB_QPS_INIT,
+        IB_QPS_RTR,
+        IB_QPS_RTS,
+        IB_QPS_SQD,
+        IB_QPS_SQE,
+        IB_QPS_ERR
+};
+
+enum ib_mig_state {
+        IB_MIG_MIGRATED,
+        IB_MIG_REARM,
+        IB_MIG_ARMED
+};
+
+struct ib_qp_attr {
+        enum ib_qp_state        qp_state;
+        enum ib_qp_state        cur_qp_state;
+        enum ib_mtu             path_mtu;
+        enum ib_mig_state       path_mig_state;
+        u32                     qkey;
+        u32                     rq_psn;
+        u32                     sq_psn;
+        u32                     dest_qp_num;
+        int                     qp_access_flags;
+        struct ib_qp_cap        cap;
+        struct ib_ah_attr       ah_attr;
+        struct ib_ah_attr       alt_ah_attr;
+        u16                     pkey_index;
+        u16                     alt_pkey_index;
+        u8                      en_sqd_async_notify;
+        u8                      sq_draining;
+        u8                      max_rd_atomic;
+        u8                      max_dest_rd_atomic;
+        u8                      min_rnr_timer;
+        u8                      port_num;
+        u8                      timeout;
+        u8                      retry_cnt;
+        u8                      rnr_retry;
+        u8                      alt_port_num;
+        u8                      alt_timeout;
+};
+
+enum ib_wr_opcode {
+        IB_WR_RDMA_WRITE,
+        IB_WR_RDMA_WRITE_WITH_IMM,
+        IB_WR_SEND,
+        IB_WR_SEND_WITH_IMM,
+        IB_WR_RDMA_READ,
+        IB_WR_ATOMIC_CMP_AND_SWP,
+        IB_WR_ATOMIC_FETCH_AND_ADD
+};
+
+enum ib_send_flags {
+        IB_SEND_FENCE           = 1,
+        IB_SEND_SIGNALED        = (1<<1),
+        IB_SEND_SOLICITED       = (1<<2),
+        IB_SEND_INLINE          = (1<<3)
+};
+
+struct ib_sge {
+        u64     addr;
+        u32     length;
+        u32     lkey;
+};
+
+struct ib_send_wr {
+        struct ib_send_wr      *next;
+        u64                     wr_id;
+        struct ib_sge          *sg_list;
+        int                     num_sge;
+        enum ib_wr_opcode       opcode;
+        int                     send_flags;
+        __be32                  imm_data;
+        union {
+                struct {
+                        u64     remote_addr;
+                        u32     rkey;
+                } rdma;
+                struct {
+                        u64     remote_addr;
+                        u64     compare_add;
+                        u64     swap;
+                        u32     rkey;
+                } atomic;
+                struct {
+                        struct ib_ah *ah;
+                        struct ib_mad_hdr *mad_hdr;
+                        u32     remote_qpn;
+                        u32     remote_qkey;
+                        int     timeout_ms; /* valid for MADs only */
+                        int     retries;    /* valid for MADs only */
+                        u16     pkey_index; /* valid for GSI only */
+                        u8      port_num;   /* valid for DR SMPs on switch only */
+                } ud;
+        } wr;
+};
+
+struct ib_recv_wr {
+        struct ib_recv_wr      *next;
+        u64                     wr_id;
+        struct ib_sge          *sg_list;
+        int                     num_sge;
+};
+
+enum ib_access_flags {
+        IB_ACCESS_LOCAL_WRITE   = 1,
+        IB_ACCESS_REMOTE_WRITE  = (1<<1),
+        IB_ACCESS_REMOTE_READ   = (1<<2),
+        IB_ACCESS_REMOTE_ATOMIC = (1<<3),
+        IB_ACCESS_MW_BIND       = (1<<4)
+};
+
+struct ib_phys_buf {
+        u64      addr;
+        u64      size;
+};
+
+struct ib_mr_attr {
+        struct ib_pd    *pd;
+        u64             device_virt_addr;
+        u64             size;
+        int             mr_access_flags;
+        u32             lkey;
+        u32             rkey;
+};
+
+enum ib_mr_rereg_flags {
+        IB_MR_REREG_TRANS       = 1,
+        IB_MR_REREG_PD          = (1<<1),
+        IB_MR_REREG_ACCESS      = (1<<2)
+};
+
+struct ib_mw_bind {
+        struct ib_mr   *mr;
+        u64             wr_id;
+        u64             addr;
+        u32             length;
+        int             send_flags;
+        int             mw_access_flags;
+};
+
+struct ib_fmr_attr {
+        int     max_pages;
+        int     max_maps;
+        u8      page_size;
+};
+
+struct ib_ucontext {
+        struct ib_device       *device;
+        struct list_head        pd_list;
+        struct list_head        mr_list;
+        struct list_head        mw_list;
+        struct list_head        cq_list;
+        struct list_head        qp_list;
+        struct list_head        srq_list;
+        struct list_head        ah_list;
+        spinlock_t              lock;
+};
+
+struct ib_uobject {
+        u64                     user_handle;    /* handle given to us by userspace */
+        struct ib_ucontext     *context;        /* associated user context */
+        struct list_head        list;           /* link to context's list */
+        u32                     id;             /* index into kernel idr */
+};
+
+struct ib_umem {
+        unsigned long           user_base;
+        unsigned long           virt_base;
+        size_t                  length;
+        int                     offset;
+        int                     page_size;
+        int                     writable;
+        struct list_head        chunk_list;
+};
+
+struct ib_umem_chunk {
+        struct list_head        list;
+        int                     nents;
+        int                     nmap;
+        struct scatterlist      page_list[0];
+};
+
+struct ib_udata {
+        void __user *inbuf;
+        void __user *outbuf;
+        size_t       inlen;
+        size_t       outlen;
+};
+
+#define IB_UMEM_MAX_PAGE_CHUNK                                          \
+        ((PAGE_SIZE - offsetof(struct ib_umem_chunk, page_list)) /      \
+         ((void *) &((struct ib_umem_chunk *) 0)->page_list[1] -        \
+          (void *) &((struct ib_umem_chunk *) 0)->page_list[0]))
+
+struct ib_umem_object {
+        struct ib_uobject       uobject;
+        struct ib_umem          umem;
+};
+
+struct ib_pd {
+        struct ib_device       *device;
+        struct ib_uobject      *uobject;
+        atomic_t                usecnt; /* count all resources */
+};
+
+struct ib_ah {
+        struct ib_device        *device;
+        struct ib_pd            *pd;
+        struct ib_uobject       *uobject;
+};
+
+typedef void (*ib_comp_handler)(struct ib_cq *cq, void *cq_context);
+
+struct ib_cq {
+        struct ib_device       *device;
+        struct ib_uobject      *uobject;
+        ib_comp_handler         comp_handler;
+        void                  (*event_handler)(struct ib_event *, void *);
+        void *                  cq_context;
+        int                     cqe;
+        atomic_t                usecnt; /* count number of work queues */
+};
+
+struct ib_srq {
+        struct ib_device       *device;
+        struct ib_pd           *pd;
+        struct ib_uobject      *uobject;
+        void                  (*event_handler)(struct ib_event *, void *);
+        void                   *srq_context;
+        atomic_t                usecnt;
+};
+
+struct ib_qp {
+        struct ib_device       *device;
+        struct ib_pd           *pd;
+        struct ib_cq           *send_cq;
+        struct ib_cq           *recv_cq;
+        struct ib_srq          *srq;
+        struct ib_uobject      *uobject;
+        void                  (*event_handler)(struct ib_event *, void *);
+        void                   *qp_context;
+        u32                     qp_num;
+        enum ib_qp_type         qp_type;
+};
+
+struct ib_mr {
+        struct ib_device  *device;
+        struct ib_pd      *pd;
+        struct ib_uobject *uobject;
+        u32                lkey;
+        u32                rkey;
+        atomic_t           usecnt; /* count number of MWs */
+};
+
+struct ib_mw {
+        struct ib_device        *device;
+        struct ib_pd            *pd;
+        struct ib_uobject       *uobject;
+        u32                     rkey;
+};
+
+struct ib_fmr {
+        struct ib_device        *device;
+        struct ib_pd            *pd;
+        struct list_head        list;
+        u32                     lkey;
+        u32                     rkey;
+};
+
+struct ib_mad;
+struct ib_grh;
+
+enum ib_process_mad_flags {
+        IB_MAD_IGNORE_MKEY      = 1,
+        IB_MAD_IGNORE_BKEY      = 2,
+        IB_MAD_IGNORE_ALL       = IB_MAD_IGNORE_MKEY | IB_MAD_IGNORE_BKEY
+};
+
+enum ib_mad_result {
+        IB_MAD_RESULT_FAILURE  = 0,      /* (!SUCCESS is the important flag) */
+        IB_MAD_RESULT_SUCCESS  = 1 << 0, /* MAD was successfully processed   */
+        IB_MAD_RESULT_REPLY    = 1 << 1, /* Reply packet needs to be sent    */
+        IB_MAD_RESULT_CONSUMED = 1 << 2  /* Packet consumed: stop processing */
+};
+
+#define IB_DEVICE_NAME_MAX 64
+
+struct ib_cache {
+        rwlock_t                lock;
+        struct ib_event_handler event_handler;
+        struct ib_pkey_cache  **pkey_cache;
+        struct ib_gid_cache   **gid_cache;
+};
+
+struct ib_device {
+        struct device                *dma_device;
+
+        char                          name[IB_DEVICE_NAME_MAX];
+
+        struct list_head              event_handler_list;
+        spinlock_t                    event_handler_lock;
+
+        struct list_head              core_list;
+        struct list_head              client_data_list;
+        spinlock_t                    client_data_lock;
+
+        struct ib_cache               cache;
+
+        u32                           flags;
+
+        int                        (*query_device)(struct ib_device *device,
+                                                   struct ib_device_attr *device_attr);
+        int                        (*query_port)(struct ib_device *device,
+                                                 u8 port_num,
+                                                 struct ib_port_attr *port_attr);
+        int                        (*query_gid)(struct ib_device *device,
+                                                u8 port_num, int index,
+                                                union ib_gid *gid);
+        int                        (*query_pkey)(struct ib_device *device,
+                                                 u8 port_num, u16 index, u16 *pkey);
+        int                        (*modify_device)(struct ib_device *device,
+                                                    int device_modify_mask,
+                                                    struct ib_device_modify *device_modify);
+        int                        (*modify_port)(struct ib_device *device,
+                                                  u8 port_num, int port_modify_mask,
+                                                  struct ib_port_modify *port_modify);
+        struct ib_ucontext *       (*alloc_ucontext)(struct ib_device *device,
+                                                     struct ib_udata *udata);
+        int                        (*dealloc_ucontext)(struct ib_ucontext *context);
+        int                        (*mmap)(struct ib_ucontext *context,
+                                           struct vm_area_struct *vma);
+        struct ib_pd *             (*alloc_pd)(struct ib_device *device,
+                                               struct ib_ucontext *context,
+                                               struct ib_udata *udata);
+        int                        (*dealloc_pd)(struct ib_pd *pd);
+        struct ib_ah *             (*create_ah)(struct ib_pd *pd,
+                                                struct ib_ah_attr *ah_attr);
+        int                        (*modify_ah)(struct ib_ah *ah,
+                                                struct ib_ah_attr *ah_attr);
+        int                        (*query_ah)(struct ib_ah *ah,
+                                               struct ib_ah_attr *ah_attr);
+        int                        (*destroy_ah)(struct ib_ah *ah);
+        struct ib_srq *            (*create_srq)(struct ib_pd *pd,
+                                                 struct ib_srq_init_attr *srq_init_attr,
+                                                 struct ib_udata *udata);
+        int                        (*modify_srq)(struct ib_srq *srq,
+                                                 struct ib_srq_attr *srq_attr,
+                                                 enum ib_srq_attr_mask srq_attr_mask);
+        int                        (*query_srq)(struct ib_srq *srq,
+                                                struct ib_srq_attr *srq_attr);
+        int                        (*destroy_srq)(struct ib_srq *srq);
+        int                        (*post_srq_recv)(struct ib_srq *srq,
+                                                    struct ib_recv_wr *recv_wr,
+                                                    struct ib_recv_wr **bad_recv_wr);
+        struct ib_qp *             (*create_qp)(struct ib_pd *pd,
+                                                struct ib_qp_init_attr *qp_init_attr,
+                                                struct ib_udata *udata);
+        int                        (*modify_qp)(struct ib_qp *qp,
+                                                struct ib_qp_attr *qp_attr,
+                                                int qp_attr_mask);
+        int                        (*query_qp)(struct ib_qp *qp,
+                                               struct ib_qp_attr *qp_attr,
+                                               int qp_attr_mask,
+                                               struct ib_qp_init_attr *qp_init_attr);
+        int                        (*destroy_qp)(struct ib_qp *qp);
+        int                        (*post_send)(struct ib_qp *qp,
+                                                struct ib_send_wr *send_wr,
+                                                struct ib_send_wr **bad_send_wr);
+        int                        (*post_recv)(struct ib_qp *qp,
+                                                struct ib_recv_wr *recv_wr,
+                                                struct ib_recv_wr **bad_recv_wr);
+        struct ib_cq *             (*create_cq)(struct ib_device *device, int cqe,
+                                                struct ib_ucontext *context,
+                                                struct ib_udata *udata);
+        int                        (*destroy_cq)(struct ib_cq *cq);
+        int                        (*resize_cq)(struct ib_cq *cq, int *cqe);
+        int                        (*poll_cq)(struct ib_cq *cq, int num_entries,
+                                              struct ib_wc *wc);
+        int                        (*peek_cq)(struct ib_cq *cq, int wc_cnt);
+        int                        (*req_notify_cq)(struct ib_cq *cq,
+                                                    enum ib_cq_notify cq_notify);
+        int                        (*req_ncomp_notif)(struct ib_cq *cq,
+                                                      int wc_cnt);
+        struct ib_mr *             (*get_dma_mr)(struct ib_pd *pd,
+                                                 int mr_access_flags);
+        struct ib_mr *             (*reg_phys_mr)(struct ib_pd *pd,
+                                                  struct ib_phys_buf *phys_buf_array,
+                                                  int num_phys_buf,
+                                                  int mr_access_flags,
+                                                  u64 *iova_start);
+        struct ib_mr *             (*reg_user_mr)(struct ib_pd *pd,
+                                                  struct ib_umem *region,
+                                                  int mr_access_flags,
+                                                  struct ib_udata *udata);
+        int                        (*query_mr)(struct ib_mr *mr,
+                                               struct ib_mr_attr *mr_attr);
+        int                        (*dereg_mr)(struct ib_mr *mr);
+        int                        (*rereg_phys_mr)(struct ib_mr *mr,
+                                                    int mr_rereg_mask,
+                                                    struct ib_pd *pd,
+                                                    struct ib_phys_buf *phys_buf_array,
+                                                    int num_phys_buf,
+                                                    int mr_access_flags,
+                                                    u64 *iova_start);
+        struct ib_mw *             (*alloc_mw)(struct ib_pd *pd);
+        int                        (*bind_mw)(struct ib_qp *qp,
+                                              struct ib_mw *mw,
+                                              struct ib_mw_bind *mw_bind);
+        int                        (*dealloc_mw)(struct ib_mw *mw);
+        struct ib_fmr *            (*alloc_fmr)(struct ib_pd *pd,
+                                                int mr_access_flags,
+                                                struct ib_fmr_attr *fmr_attr);
+        int                        (*map_phys_fmr)(struct ib_fmr *fmr,
+                                                   u64 *page_list, int list_len,
+                                                   u64 iova);
+        int                        (*unmap_fmr)(struct list_head *fmr_list);
+        int                        (*dealloc_fmr)(struct ib_fmr *fmr);
+        int                        (*attach_mcast)(struct ib_qp *qp,
+                                                   union ib_gid *gid,
+                                                   u16 lid);
+        int                        (*detach_mcast)(struct ib_qp *qp,
+                                                   union ib_gid *gid,
+                                                   u16 lid);
+        int                        (*process_mad)(struct ib_device *device,
+                                                  int process_mad_flags,
+                                                  u8 port_num,
+                                                  struct ib_wc *in_wc,
+                                                  struct ib_grh *in_grh,
+                                                  struct ib_mad *in_mad,
+                                                  struct ib_mad *out_mad);
+
+        struct module               *owner;
+        struct class_device          class_dev;
+        struct kobject               ports_parent;
+        struct list_head             port_list;
+
+        enum {
+                IB_DEV_UNINITIALIZED,
+                IB_DEV_REGISTERED,
+                IB_DEV_UNREGISTERED
+        }                            reg_state;
+
+        u8                           node_type;
+        u8                           phys_port_cnt;
+};
+
+struct ib_client {
+        char  *name;
+        void (*add)   (struct ib_device *);
+        void (*remove)(struct ib_device *);
+
+        struct list_head list;
+};
+
+struct ib_device *ib_alloc_device(size_t size);
+void ib_dealloc_device(struct ib_device *device);
+
+int ib_register_device   (struct ib_device *device);
+void ib_unregister_device(struct ib_device *device);
+
+int ib_register_client   (struct ib_client *client);
+void ib_unregister_client(struct ib_client *client);
+
+void *ib_get_client_data(struct ib_device *device, struct ib_client *client);
+void  ib_set_client_data(struct ib_device *device, struct ib_client *client,
+                         void *data);
+
+static inline int ib_copy_from_udata(void *dest, struct ib_udata *udata, size_t len)
+{
+        return copy_from_user(dest, udata->inbuf, len) ? -EFAULT : 0;
+}
+
+static inline int ib_copy_to_udata(struct ib_udata *udata, void *src, size_t len)
+{
+        return copy_to_user(udata->outbuf, src, len) ? -EFAULT : 0;
+}
+
+int ib_register_event_handler  (struct ib_event_handler *event_handler);
+int ib_unregister_event_handler(struct ib_event_handler *event_handler);
+void ib_dispatch_event(struct ib_event *event);
+
+int ib_query_device(struct ib_device *device,
+                    struct ib_device_attr *device_attr);
+
+int ib_query_port(struct ib_device *device,
+                  u8 port_num, struct ib_port_attr *port_attr);
+
+int ib_query_gid(struct ib_device *device,
+                 u8 port_num, int index, union ib_gid *gid);
+
+int ib_query_pkey(struct ib_device *device,
+                  u8 port_num, u16 index, u16 *pkey);
+
+int ib_modify_device(struct ib_device *device,
+                     int device_modify_mask,
+                     struct ib_device_modify *device_modify);
+
+int ib_modify_port(struct ib_device *device,
+                   u8 port_num, int port_modify_mask,
+                   struct ib_port_modify *port_modify);
+
+/**
+ * ib_alloc_pd - Allocates an unused protection domain.
+ * @device: The device on which to allocate the protection domain.
+ *
+ * A protection domain object provides an association between QPs, shared
+ * receive queues, address handles, memory regions, and memory windows.
+ */
+struct ib_pd *ib_alloc_pd(struct ib_device *device);
+
+/**
+ * ib_dealloc_pd - Deallocates a protection domain.
+ * @pd: The protection domain to deallocate.
+ */
+int ib_dealloc_pd(struct ib_pd *pd);
+
+/**
+ * ib_create_ah - Creates an address handle for the given address vector.
+ * @pd: The protection domain associated with the address handle.
+ * @ah_attr: The attributes of the address vector.
+ *
+ * The address handle is used to reference a local or global destination
+ * in all UD QP post sends.
+ */
+struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
+
+/**
+ * ib_create_ah_from_wc - Creates an address handle associated with the
+ *   sender of the specified work completion.
+ * @pd: The protection domain associated with the address handle.
+ * @wc: Work completion information associated with a received message.
+ * @grh: References the received global route header.  This parameter is
+ *   ignored unless the work completion indicates that the GRH is valid.
+ * @port_num: The outbound port number to associate with the address.
+ *
+ * The address handle is used to reference a local or global destination
+ * in all UD QP post sends.
+ */
+struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc,
+                                   struct ib_grh *grh, u8 port_num);
+
+/**
+ * ib_modify_ah - Modifies the address vector associated with an address
+ *   handle.
+ * @ah: The address handle to modify.
+ * @ah_attr: The new address vector attributes to associate with the
+ *   address handle.
+ */
+int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);
+
+/**
+ * ib_query_ah - Queries the address vector associated with an address
+ *   handle.
+ * @ah: The address handle to query.
+ * @ah_attr: The address vector attributes associated with the address
+ *   handle.
+ */
+int ib_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);
+
+/**
+ * ib_destroy_ah - Destroys an address handle.
+ * @ah: The address handle to destroy.
+ */
+int ib_destroy_ah(struct ib_ah *ah);
+
+/**
+ * ib_create_srq - Creates a SRQ associated with the specified protection
+ *   domain.
+ * @pd: The protection domain associated with the SRQ.
+ * @srq_init_attr: A list of initial attributes required to create the SRQ.
+ *
+ * srq_attr->max_wr and srq_attr->max_sge are read the determine the
+ * requested size of the SRQ, and set to the actual values allocated
+ * on return.  If ib_create_srq() succeeds, then max_wr and max_sge
+ * will always be at least as large as the requested values.
+ */
+struct ib_srq *ib_create_srq(struct ib_pd *pd,
+                             struct ib_srq_init_attr *srq_init_attr);
+
+/**
+ * ib_modify_srq - Modifies the attributes for the specified SRQ.
+ * @srq: The SRQ to modify.
+ * @srq_attr: On input, specifies the SRQ attributes to modify.  On output,
+ *   the current values of selected SRQ attributes are returned.
+ * @srq_attr_mask: A bit-mask used to specify which attributes of the SRQ
+ *   are being modified.
+ *
+ * The mask may contain IB_SRQ_MAX_WR to resize the SRQ and/or
+ * IB_SRQ_LIMIT to set the SRQ's limit and request notification when
+ * the number of receives queued drops below the limit.
+ */
+int ib_modify_srq(struct ib_srq *srq,
+                  struct ib_srq_attr *srq_attr,
+                  enum ib_srq_attr_mask srq_attr_mask);
+
+/**
+ * ib_query_srq - Returns the attribute list and current values for the
+ *   specified SRQ.
+ * @srq: The SRQ to query.
+ * @srq_attr: The attributes of the specified SRQ.
+ */
+int ib_query_srq(struct ib_srq *srq,
+                 struct ib_srq_attr *srq_attr);
+
+/**
+ * ib_destroy_srq - Destroys the specified SRQ.
+ * @srq: The SRQ to destroy.
+ */
+int ib_destroy_srq(struct ib_srq *srq);
+
+/**
+ * ib_post_srq_recv - Posts a list of work requests to the specified SRQ.
+ * @srq: The SRQ to post the work request on.
+ * @recv_wr: A list of work requests to post on the receive queue.
+ * @bad_recv_wr: On an immediate failure, this parameter will reference
+ *   the work request that failed to be posted on the QP.
+ */
+static inline int ib_post_srq_recv(struct ib_srq *srq,
+                                   struct ib_recv_wr *recv_wr,
+                                   struct ib_recv_wr **bad_recv_wr)
+{
+        return srq->device->post_srq_recv(srq, recv_wr, bad_recv_wr);
+}
+
+/**
+ * ib_create_qp - Creates a QP associated with the specified protection
+ *   domain.
+ * @pd: The protection domain associated with the QP.
+ * @qp_init_attr: A list of initial attributes required to create the QP.
+ */
+struct ib_qp *ib_create_qp(struct ib_pd *pd,
+                           struct ib_qp_init_attr *qp_init_attr);
+
+/**
+ * ib_modify_qp - Modifies the attributes for the specified QP and then
+ *   transitions the QP to the given state.
+ * @qp: The QP to modify.
+ * @qp_attr: On input, specifies the QP attributes to modify.  On output,
+ *   the current values of selected QP attributes are returned.
+ * @qp_attr_mask: A bit-mask used to specify which attributes of the QP
+ *   are being modified.
+ */
+int ib_modify_qp(struct ib_qp *qp,
+                 struct ib_qp_attr *qp_attr,
+                 int qp_attr_mask);
+
+/**
+ * ib_query_qp - Returns the attribute list and current values for the
+ *   specified QP.
+ * @qp: The QP to query.
+ * @qp_attr: The attributes of the specified QP.
+ * @qp_attr_mask: A bit-mask used to select specific attributes to query.
+ * @qp_init_attr: Additional attributes of the selected QP.
+ *
+ * The qp_attr_mask may be used to limit the query to gathering only the
+ * selected attributes.
+ */
+int ib_query_qp(struct ib_qp *qp,
+                struct ib_qp_attr *qp_attr,
+                int qp_attr_mask,
+                struct ib_qp_init_attr *qp_init_attr);
+
+/**
+ * ib_destroy_qp - Destroys the specified QP.
+ * @qp: The QP to destroy.
+ */
+int ib_destroy_qp(struct ib_qp *qp);
+
+/**
+ * ib_post_send - Posts a list of work requests to the send queue of
+ *   the specified QP.
+ * @qp: The QP to post the work request on.
+ * @send_wr: A list of work requests to post on the send queue.
+ * @bad_send_wr: On an immediate failure, this parameter will reference
+ *   the work request that failed to be posted on the QP.
+ */
+static inline int ib_post_send(struct ib_qp *qp,
+                               struct ib_send_wr *send_wr,
+                               struct ib_send_wr **bad_send_wr)
+{
+        return qp->device->post_send(qp, send_wr, bad_send_wr);
+}
+
+/**
+ * ib_post_recv - Posts a list of work requests to the receive queue of
+ *   the specified QP.
+ * @qp: The QP to post the work request on.
+ * @recv_wr: A list of work requests to post on the receive queue.
+ * @bad_recv_wr: On an immediate failure, this parameter will reference
+ *   the work request that failed to be posted on the QP.
+ */
+static inline int ib_post_recv(struct ib_qp *qp,
+                               struct ib_recv_wr *recv_wr,
+                               struct ib_recv_wr **bad_recv_wr)
+{
+        return qp->device->post_recv(qp, recv_wr, bad_recv_wr);
+}
+
+/**
+ * ib_create_cq - Creates a CQ on the specified device.
+ * @device: The device on which to create the CQ.
+ * @comp_handler: A user-specified callback that is invoked when a
+ *   completion event occurs on the CQ.
+ * @event_handler: A user-specified callback that is invoked when an
+ *   asynchronous event not associated with a completion occurs on the CQ.
+ * @cq_context: Context associated with the CQ returned to the user via
+ *   the associated completion and event handlers.
+ * @cqe: The minimum size of the CQ.
+ *
+ * Users can examine the cq structure to determine the actual CQ size.
+ */
+struct ib_cq *ib_create_cq(struct ib_device *device,
+                           ib_comp_handler comp_handler,
+                           void (*event_handler)(struct ib_event *, void *),
+                           void *cq_context, int cqe);
+
+/**
+ * ib_resize_cq - Modifies the capacity of the CQ.
+ * @cq: The CQ to resize.
+ * @cqe: The minimum size of the CQ.
+ *
+ * Users can examine the cq structure to determine the actual CQ size.
+ */
+int ib_resize_cq(struct ib_cq *cq, int cqe);
+
+/**
+ * ib_destroy_cq - Destroys the specified CQ.
+ * @cq: The CQ to destroy.
+ */
+int ib_destroy_cq(struct ib_cq *cq);
+
+/**
+ * ib_poll_cq - poll a CQ for completion(s)
+ * @cq:the CQ being polled
+ * @num_entries:maximum number of completions to return
+ * @wc:array of at least @num_entries &struct ib_wc where completions
+ *   will be returned
+ *
+ * Poll a CQ for (possibly multiple) completions.  If the return value
+ * is < 0, an error occurred.  If the return value is >= 0, it is the
+ * number of completions returned.  If the return value is
+ * non-negative and < num_entries, then the CQ was emptied.
+ */
+static inline int ib_poll_cq(struct ib_cq *cq, int num_entries,
+                             struct ib_wc *wc)
+{
+        return cq->device->poll_cq(cq, num_entries, wc);
+}
+
+/**
+ * ib_peek_cq - Returns the number of unreaped completions currently
+ *   on the specified CQ.
+ * @cq: The CQ to peek.
+ * @wc_cnt: A minimum number of unreaped completions to check for.
+ *
+ * If the number of unreaped completions is greater than or equal to wc_cnt,
+ * this function returns wc_cnt, otherwise, it returns the actual number of
+ * unreaped completions.
+ */
+int ib_peek_cq(struct ib_cq *cq, int wc_cnt);
+
+/**
+ * ib_req_notify_cq - Request completion notification on a CQ.
+ * @cq: The CQ to generate an event for.
+ * @cq_notify: If set to %IB_CQ_SOLICITED, completion notification will
+ *   occur on the next solicited event. If set to %IB_CQ_NEXT_COMP,
+ *   notification will occur on the next completion.
+ */
+static inline int ib_req_notify_cq(struct ib_cq *cq,
+                                   enum ib_cq_notify cq_notify)
+{
+        return cq->device->req_notify_cq(cq, cq_notify);
+}
+
+/**
+ * ib_req_ncomp_notif - Request completion notification when there are
+ *   at least the specified number of unreaped completions on the CQ.
+ * @cq: The CQ to generate an event for.
+ * @wc_cnt: The number of unreaped completions that should be on the
+ *   CQ before an event is generated.
+ */
+static inline int ib_req_ncomp_notif(struct ib_cq *cq, int wc_cnt)
+{
+        return cq->device->req_ncomp_notif ?
+                cq->device->req_ncomp_notif(cq, wc_cnt) :
+                -ENOSYS;
+}
+
+/**
+ * ib_get_dma_mr - Returns a memory region for system memory that is
+ *   usable for DMA.
+ * @pd: The protection domain associated with the memory region.
+ * @mr_access_flags: Specifies the memory access rights.
+ */
+struct ib_mr *ib_get_dma_mr(struct ib_pd *pd, int mr_access_flags);
+
+/**
+ * ib_reg_phys_mr - Prepares a virtually addressed memory region for use
+ *   by an HCA.
+ * @pd: The protection domain associated assigned to the registered region.
+ * @phys_buf_array: Specifies a list of physical buffers to use in the
+ *   memory region.
+ * @num_phys_buf: Specifies the size of the phys_buf_array.
+ * @mr_access_flags: Specifies the memory access rights.
+ * @iova_start: The offset of the region's starting I/O virtual address.
+ */
+struct ib_mr *ib_reg_phys_mr(struct ib_pd *pd,
+                             struct ib_phys_buf *phys_buf_array,
+                             int num_phys_buf,
+                             int mr_access_flags,
+                             u64 *iova_start);
+
+/**
+ * ib_rereg_phys_mr - Modifies the attributes of an existing memory region.
+ *   Conceptually, this call performs the functions deregister memory region
+ *   followed by register physical memory region.  Where possible,
+ *   resources are reused instead of deallocated and reallocated.
+ * @mr: The memory region to modify.
+ * @mr_rereg_mask: A bit-mask used to indicate which of the following
+ *   properties of the memory region are being modified.
+ * @pd: If %IB_MR_REREG_PD is set in mr_rereg_mask, this field specifies
+ *   the new protection domain to associated with the memory region,
+ *   otherwise, this parameter is ignored.
+ * @phys_buf_array: If %IB_MR_REREG_TRANS is set in mr_rereg_mask, this
+ *   field specifies a list of physical buffers to use in the new
+ *   translation, otherwise, this parameter is ignored.
+ * @num_phys_buf: If %IB_MR_REREG_TRANS is set in mr_rereg_mask, this
+ *   field specifies the size of the phys_buf_array, otherwise, this
+ *   parameter is ignored.
+ * @mr_access_flags: If %IB_MR_REREG_ACCESS is set in mr_rereg_mask, this
+ *   field specifies the new memory access rights, otherwise, this
+ *   parameter is ignored.
+ * @iova_start: The offset of the region's starting I/O virtual address.
+ */
+int ib_rereg_phys_mr(struct ib_mr *mr,
+                     int mr_rereg_mask,
+                     struct ib_pd *pd,
+                     struct ib_phys_buf *phys_buf_array,
+                     int num_phys_buf,
+                     int mr_access_flags,
+                     u64 *iova_start);
+
+/**
+ * ib_query_mr - Retrieves information about a specific memory region.
+ * @mr: The memory region to retrieve information about.
+ * @mr_attr: The attributes of the specified memory region.
+ */
+int ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr);
+
+/**
+ * ib_dereg_mr - Deregisters a memory region and removes it from the
+ *   HCA translation table.
+ * @mr: The memory region to deregister.
+ */
+int ib_dereg_mr(struct ib_mr *mr);
+
+/**
+ * ib_alloc_mw - Allocates a memory window.
+ * @pd: The protection domain associated with the memory window.
+ */
+struct ib_mw *ib_alloc_mw(struct ib_pd *pd);
+
+/**
+ * ib_bind_mw - Posts a work request to the send queue of the specified
+ *   QP, which binds the memory window to the given address range and
+ *   remote access attributes.
+ * @qp: QP to post the bind work request on.
+ * @mw: The memory window to bind.
+ * @mw_bind: Specifies information about the memory window, including
+ *   its address range, remote access rights, and associated memory region.
+ */
+static inline int ib_bind_mw(struct ib_qp *qp,
+                             struct ib_mw *mw,
+                             struct ib_mw_bind *mw_bind)
+{
+        /* XXX reference counting in corresponding MR? */
+        return mw->device->bind_mw ?
+                mw->device->bind_mw(qp, mw, mw_bind) :
+                -ENOSYS;
+}
+
+/**
+ * ib_dealloc_mw - Deallocates a memory window.
+ * @mw: The memory window to deallocate.
+ */
+int ib_dealloc_mw(struct ib_mw *mw);
+
+/**
+ * ib_alloc_fmr - Allocates a unmapped fast memory region.
+ * @pd: The protection domain associated with the unmapped region.
+ * @mr_access_flags: Specifies the memory access rights.
+ * @fmr_attr: Attributes of the unmapped region.
+ *
+ * A fast memory region must be mapped before it can be used as part of
+ * a work request.
+ */
+struct ib_fmr *ib_alloc_fmr(struct ib_pd *pd,
+                            int mr_access_flags,
+                            struct ib_fmr_attr *fmr_attr);
+
+/**
+ * ib_map_phys_fmr - Maps a list of physical pages to a fast memory region.
+ * @fmr: The fast memory region to associate with the pages.
+ * @page_list: An array of physical pages to map to the fast memory region.
+ * @list_len: The number of pages in page_list.
+ * @iova: The I/O virtual address to use with the mapped region.
+ */
+static inline int ib_map_phys_fmr(struct ib_fmr *fmr,
+                                  u64 *page_list, int list_len,
+                                  u64 iova)
+{
+        return fmr->device->map_phys_fmr(fmr, page_list, list_len, iova);
+}
+
+/**
+ * ib_unmap_fmr - Removes the mapping from a list of fast memory regions.
+ * @fmr_list: A linked list of fast memory regions to unmap.
+ */
+int ib_unmap_fmr(struct list_head *fmr_list);
+
+/**
+ * ib_dealloc_fmr - Deallocates a fast memory region.
+ * @fmr: The fast memory region to deallocate.
+ */
+int ib_dealloc_fmr(struct ib_fmr *fmr);
+
+/**
+ * ib_attach_mcast - Attaches the specified QP to a multicast group.
+ * @qp: QP to attach to the multicast group.  The QP must be type
+ *   IB_QPT_UD.
+ * @gid: Multicast group GID.
+ * @lid: Multicast group LID in host byte order.
+ *
+ * In order to send and receive multicast packets, subnet
+ * administration must have created the multicast group and configured
+ * the fabric appropriately.  The port associated with the specified
+ * QP must also be a member of the multicast group.
+ */
+int ib_attach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid);
+
+/**
+ * ib_detach_mcast - Detaches the specified QP from a multicast group.
+ * @qp: QP to detach from the multicast group.
+ * @gid: Multicast group GID.
+ * @lid: Multicast group LID in host byte order.
+ */
+int ib_detach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid);
+
+#endif /* IB_VERBS_H */
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index 659ecf48fb4a..b361172b576c 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -28,7 +28,7 @@ extern const unsigned char scsi_command_size[8];
  *      SCSI device types
  */
 
-#define MAX_SCSI_DEVICE_CODE 14
+#define MAX_SCSI_DEVICE_CODE 15
 extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 
 /*
@@ -41,6 +41,7 @@ extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 #define FORMAT_UNIT           0x04
 #define READ_BLOCK_LIMITS     0x05
 #define REASSIGN_BLOCKS       0x07
+#define INITIALIZE_ELEMENT_STATUS 0x07
 #define READ_6                0x08
 #define WRITE_6               0x0a
 #define SEEK_6                0x0b
@@ -65,6 +66,7 @@ extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 #define READ_10               0x28
 #define WRITE_10              0x2a
 #define SEEK_10               0x2b
+#define POSITION_TO_ELEMENT   0x2b
 #define WRITE_VERIFY          0x2e
 #define VERIFY                0x2f
 #define SEARCH_HIGH           0x30
@@ -97,6 +99,7 @@ extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE];
 #define PERSISTENT_RESERVE_OUT 0x5f
 #define REPORT_LUNS           0xa0
 #define MOVE_MEDIUM           0xa5
+#define EXCHANGE_MEDIUM       0xa6
 #define READ_12               0xa8
 #define WRITE_12              0xaa
 #define WRITE_VERIFY_12       0xae
@@ -208,8 +211,9 @@ static inline int scsi_status_is_good(int status)
                                      * - treated as TYPE_DISK */
 #define TYPE_MEDIUM_CHANGER 0x08
 #define TYPE_COMM           0x09    /* Communications device */
-#define TYPE_ENCLOSURE      0x0d    /* Enclosure Services Device */
 #define TYPE_RAID           0x0c
+#define TYPE_ENCLOSURE      0x0d    /* Enclosure Services Device */
+#define TYPE_RBC            0x0e
 #define TYPE_NO_LUN         0x7f
 
 /*
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index 07f5c699eaa7..bed4b7c9be99 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -31,14 +31,11 @@ struct scsi_cmnd {
         int     sc_magic;
 
         struct scsi_device *device;
-        unsigned short state;
-        unsigned short owner;
         struct scsi_request *sc_request;
 
         struct list_head list;  /* scsi_cmnd participates in queue lists */
 
         struct list_head eh_entry; /* entry for the host eh_cmd_q */
-        int eh_state;           /* Used for state tracking in error handlr */
         int eh_eflags;          /* Used by error handlr */
         void (*done) (struct scsi_cmnd *);      /* Mid-level done function */
 
@@ -54,12 +51,16 @@ struct scsi_cmnd {
          * printk's to use ->pid, so that we can kill this field.
          */
         unsigned long serial_number;
+        /*
+         * This is set to jiffies as it was when the command was first
+         * allocated.  It is used to time how long the command has
+         * been outstanding
+         */
+        unsigned long jiffies_at_alloc;
 
         int retries;
         int allowed;
         int timeout_per_command;
-        int timeout_total;
-        int timeout;
 
         unsigned char cmd_len;
         unsigned char old_cmd_len;
@@ -80,8 +81,6 @@ struct scsi_cmnd {
                                          * sense info */
         unsigned short use_sg;  /* Number of pieces of scatter-gather */
         unsigned short sglist_len;      /* size of malloc'd scatter-gather list */
-        unsigned short abort_reason;    /* If the mid-level code requests an
-                                         * abort, this is the reason. */
         unsigned bufflen;       /* Size of data buffer */
         void *buffer;           /* Data buffer */
 
diff --git a/include/scsi/scsi_dbg.h b/include/scsi/scsi_dbg.h
index 12e90934a7a8..b090a11d7e1c 100644
--- a/include/scsi/scsi_dbg.h
+++ b/include/scsi/scsi_dbg.h
@@ -3,8 +3,10 @@
 
 struct scsi_cmnd;
 struct scsi_request;
+struct scsi_sense_hdr;
 
 extern void scsi_print_command(struct scsi_cmnd *);
+extern void scsi_print_sense_hdr(const char *, struct scsi_sense_hdr *);
 extern void __scsi_print_command(unsigned char *);
 extern void scsi_print_sense(const char *, struct scsi_cmnd *);
 extern void scsi_print_req_sense(const char *, struct scsi_request *);
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index c018020d9160..da63722c0123 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -8,8 +8,17 @@
 
 struct request_queue;
 struct scsi_cmnd;
-struct scsi_mode_data;
+struct scsi_lun;
+struct scsi_sense_hdr;
 
+struct scsi_mode_data {
+        __u32   length;
+        __u16   block_descriptor_length;
+        __u8    medium_type;
+        __u8    device_specific;
+        __u8    header_length;
+        __u8    longlba:1;
+};
 
 /*
  * sdev state: If you alter this, you also need to alter scsi_sysfs.c
@@ -154,7 +163,9 @@ struct scsi_target {
         unsigned int            id; /* target id ... replace
                                      * scsi_device.id eventually */
         unsigned long           create:1; /* signal that it needs to be added */
-        unsigned long           starget_data[0];
+        void                    *hostdata; /* available to low-level driver */
+        unsigned long           starget_data[0]; /* for the transport */
+        /* starget_data must be the last element!!!! */
 } __attribute__((aligned(sizeof(unsigned long))));
 
 #define to_scsi_target(d)       container_of(d, struct scsi_target, dev)
@@ -226,7 +237,8 @@ extern int scsi_set_medium_removal(struct scsi_device *, char);
 
 extern int scsi_mode_sense(struct scsi_device *sdev, int dbd, int modepage,
                            unsigned char *buffer, int len, int timeout,
-                           int retries, struct scsi_mode_data *data);
+                           int retries, struct scsi_mode_data *data,
+                           struct scsi_sense_hdr *);
 extern int scsi_test_unit_ready(struct scsi_device *sdev, int timeout,
                                 int retries);
 extern int scsi_device_set_state(struct scsi_device *sdev,
@@ -241,9 +253,18 @@ extern void scsi_target_reap(struct scsi_target *);
 extern void scsi_target_block(struct device *);
 extern void scsi_target_unblock(struct device *);
 extern void scsi_remove_target(struct device *);
+extern void int_to_scsilun(unsigned int, struct scsi_lun *);
 extern const char *scsi_device_state_name(enum scsi_device_state);
 extern int scsi_is_sdev_device(const struct device *);
 extern int scsi_is_target_device(const struct device *);
+extern int scsi_execute(struct scsi_device *sdev, const unsigned char *cmd,
+                        int data_direction, void *buffer, unsigned bufflen,
+                        unsigned char *sense, int timeout, int retries,
+                        int flag);
+extern int scsi_execute_req(struct scsi_device *sdev, const unsigned char *cmd,
+                            int data_direction, void *buffer, unsigned bufflen,
+                            struct scsi_sense_hdr *, int timeout, int retries);
+
 static inline int scsi_device_online(struct scsi_device *sdev)
 {
         return sdev->sdev_state != SDEV_OFFLINE;
diff --git a/include/scsi/scsi_eh.h b/include/scsi/scsi_eh.h
index 80557f879e3e..fabd879c2f2e 100644
--- a/include/scsi/scsi_eh.h
+++ b/include/scsi/scsi_eh.h
@@ -26,10 +26,15 @@ struct scsi_sense_hdr {		/* See SPC-3 section 4.5 */
         u8 additional_length;   /* always 0 for fixed sense format */
 };
 
+static inline int scsi_sense_valid(struct scsi_sense_hdr *sshdr)
+{
+        if (!sshdr)
+                return 0;
+
+        return (sshdr->response_code & 0x70) == 0x70;
+}
+
 
-extern void scsi_add_timer(struct scsi_cmnd *, int,
-                void (*)(struct scsi_cmnd *));
-extern int scsi_delete_timer(struct scsi_cmnd *);
 extern void scsi_report_bus_reset(struct Scsi_Host *, int);
 extern void scsi_report_device_reset(struct Scsi_Host *, int, int);
 extern int scsi_block_when_processing_errors(struct scsi_device *);
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index 1cee1e100943..916144be208b 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -10,6 +10,7 @@ struct block_device;
 struct module;
 struct scsi_cmnd;
 struct scsi_device;
+struct scsi_target;
 struct Scsi_Host;
 struct scsi_host_cmd_pool;
 struct scsi_transport_template;
@@ -228,6 +229,30 @@ struct scsi_host_template {
         void (* slave_destroy)(struct scsi_device *);
 
         /*
+         * Before the mid layer attempts to scan for a new device attached
+         * to a target where no target currently exists, it will call this
+         * entry in your driver.  Should your driver need to allocate any
+         * structs or perform any other init items in order to send commands
+         * to a currently unused target, then this is where you can perform
+         * those allocations.
+         *
+         * Return values: 0 on success, non-0 on failure
+         *
+         * Status: OPTIONAL
+         */
+        int (* target_alloc)(struct scsi_target *);
+
+        /*
+         * Immediately prior to deallocating the target structure, and
+         * after all activity to attached scsi devices has ceased, the
+         * midlayer calls this point so that the driver may deallocate
+         * and terminate any references to the target.
+         *
+         * Status: OPTIONAL
+         */
+        void (* target_destroy)(struct scsi_target *);
+
+        /*
          * fill in this function to allow the queue depth of this host
          * to be changeable (on a per device basis).  returns either
          * the current queue depth setting (may be different from what
@@ -404,12 +429,15 @@ struct scsi_host_template {
 };
 
 /*
- * shost states
+ * shost state: If you alter this, you also need to alter scsi_sysfs.c
+ * (for the ascii descriptions) and the state model enforcer:
+ * scsi_host_set_state()
  */
-enum {
-        SHOST_ADD,
-        SHOST_DEL,
+enum scsi_host_state {
+        SHOST_CREATED = 1,
+        SHOST_RUNNING,
         SHOST_CANCEL,
+        SHOST_DEL,
         SHOST_RECOVERY,
 };
 
@@ -439,12 +467,10 @@ struct Scsi_Host {
         struct task_struct    * ehandler;  /* Error recovery thread. */
         struct semaphore      * eh_wait;   /* The error recovery thread waits
                                               on this. */
-        struct completion     * eh_notify; /* wait for eh to begin or end */
         struct semaphore      * eh_action; /* Wait for specific actions on the
                                           host. */
         unsigned int            eh_active:1; /* Indicates the eh thread is awake and active if
                                           this is true. */
-        unsigned int            eh_kill:1; /* set when killing the eh thread */
         wait_queue_head_t       host_wait;
         struct scsi_host_template *hostt;
         struct scsi_transport_template *transportt;
@@ -550,7 +576,7 @@ struct Scsi_Host {
         unsigned int  irq;
         
 
-        unsigned long shost_state;
+        enum scsi_host_state shost_state;
 
         /* ldm bits */
         struct device           shost_gendev;
@@ -608,6 +634,7 @@ extern void scsi_remove_host(struct Scsi_Host *);
 extern struct Scsi_Host *scsi_host_get(struct Scsi_Host *);
 extern void scsi_host_put(struct Scsi_Host *t);
 extern struct Scsi_Host *scsi_host_lookup(unsigned short);
+extern const char *scsi_host_state_name(enum scsi_host_state);
 
 extern u64 scsi_calculate_bounce_limit(struct Scsi_Host *);
 
@@ -616,15 +643,18 @@ static inline void scsi_assign_lock(struct Scsi_Host *shost, spinlock_t *lock)
         shost->host_lock = lock;
 }
 
-static inline void scsi_set_device(struct Scsi_Host *shost,
-                                   struct device *dev)
+static inline struct device *scsi_get_device(struct Scsi_Host *shost)
 {
-        shost->shost_gendev.parent = dev;
+        return shost->shost_gendev.parent;
 }
 
-static inline struct device *scsi_get_device(struct Scsi_Host *shost)
+/**
+ * scsi_host_scan_allowed - Is scanning of this host allowed
+ * @shost:      Pointer to Scsi_Host.
+ **/
+static inline int scsi_host_scan_allowed(struct Scsi_Host *shost)
 {
-        return shost->shost_gendev.parent;
+        return shost->shost_state == SHOST_RUNNING;
 }
 
 extern void scsi_unblock_requests(struct Scsi_Host *);
@@ -644,5 +674,6 @@ extern struct scsi_device *scsi_get_host_dev(struct Scsi_Host *);
 /* legacy interfaces */
 extern struct Scsi_Host *scsi_register(struct scsi_host_template *, int);
 extern void scsi_unregister(struct Scsi_Host *);
+extern int scsi_host_set_state(struct Scsi_Host *, enum scsi_host_state);
 
 #endif /* _SCSI_SCSI_HOST_H */
diff --git a/include/scsi/scsi_request.h b/include/scsi/scsi_request.h
index 98719407d554..6a140020d7cb 100644
--- a/include/scsi/scsi_request.h
+++ b/include/scsi/scsi_request.h
@@ -54,20 +54,4 @@ extern void scsi_do_req(struct scsi_request *, const void *cmnd,
                         void *buffer, unsigned bufflen,
                         void (*done) (struct scsi_cmnd *),
                         int timeout, int retries);
-
-struct scsi_mode_data {
-        __u32   length;
-        __u16   block_descriptor_length;
-        __u8    medium_type;
-        __u8    device_specific;
-        __u8    header_length;
-        __u8    longlba:1;
-};
-
-extern int __scsi_mode_sense(struct scsi_request *SRpnt, int dbd,
-                             int modepage, unsigned char *buffer, int len,
-                             int timeout, int retries,
-                             struct scsi_mode_data *data);
-
-
 #endif /* _SCSI_SCSI_REQUEST_H */
diff --git a/include/scsi/scsi_transport.h b/include/scsi/scsi_transport.h
index 2dcee7a84752..f6e0bb484c63 100644
--- a/include/scsi/scsi_transport.h
+++ b/include/scsi/scsi_transport.h
@@ -21,6 +21,7 @@
 #define SCSI_TRANSPORT_H
 
 #include <linux/transport_class.h>
+#include <scsi/scsi_host.h>
 
 struct scsi_transport_template {
         /* the attribute containers */
@@ -28,12 +29,23 @@ struct scsi_transport_template {
         struct transport_container target_attrs;
         struct transport_container device_attrs;
 
+        /*
+         * If set, call target_parent prior to allocating a scsi_target,
+         * so we get the appropriate parent for the target. This function
+         * is required for transports like FC and iSCSI that do not put the
+         * scsi_target under scsi_host.
+         */
+        struct device *(*target_parent)(struct Scsi_Host *, int, uint);
+
         /* The size of the specific transport attribute structure (a
          * space of this size will be left at the end of the
          * scsi_* structure */
         int     device_size;
+        int     device_private_offset;
         int     target_size;
+        int     target_private_offset;
         int     host_size;
+        /* no private offset for the host; there's an alternative mechanism */
 
         /*
          * True if the transport wants to use a host-based work-queue
@@ -45,4 +57,38 @@ struct scsi_transport_template {
         dev_to_shost((tc)->dev)
 
 
+/* Private area maintenance. The driver requested allocations come
+ * directly after the transport class allocations (if any).  The idea
+ * is that you *must* call these only once.  The code assumes that the
+ * initial values are the ones the transport specific code requires */
+static inline void
+scsi_transport_reserve_target(struct scsi_transport_template * t, int space)
+{
+        BUG_ON(t->target_private_offset != 0);
+        t->target_private_offset = ALIGN(t->target_size, sizeof(void *));
+        t->target_size = t->target_private_offset + space;
+}
+static inline void
+scsi_transport_reserve_device(struct scsi_transport_template * t, int space)
+{
+        BUG_ON(t->device_private_offset != 0);
+        t->device_private_offset = ALIGN(t->device_size, sizeof(void *));
+        t->device_size = t->device_private_offset + space;
+}
+static inline void *
+scsi_transport_target_data(struct scsi_target *starget)
+{
+        struct Scsi_Host *shost = dev_to_shost(&starget->dev);
+        return (u8 *)starget->starget_data
+                + shost->transportt->target_private_offset;
+
+}
+static inline void *
+scsi_transport_device_data(struct scsi_device *sdev)
+{
+        struct Scsi_Host *shost = sdev->host;
+        return (u8 *)sdev->sdev_data
+                + shost->transportt->device_private_offset;
+}
+
 #endif /* SCSI_TRANSPORT_H */
diff --git a/include/scsi/scsi_transport_spi.h b/include/scsi/scsi_transport_spi.h
index a30d6cd4c0e8..6bdc4afb2483 100644
--- a/include/scsi/scsi_transport_spi.h
+++ b/include/scsi/scsi_transport_spi.h
@@ -39,6 +39,7 @@ struct spi_transport_attrs {
         unsigned int rd_strm:1; /* Read streaming enabled */
         unsigned int rti:1;     /* Retain Training Information */
         unsigned int pcomp_en:1;/* Precompensation enabled */
+        unsigned int hold_mcs:1;/* Hold Margin Control Settings */
         unsigned int initial_dv:1; /* DV done to this target yet  */
         unsigned long flags;    /* flags field for drivers to use */
         /* Device Properties fields */
@@ -78,6 +79,7 @@ struct spi_host_attrs {
 #define spi_rd_strm(x)  (((struct spi_transport_attrs *)&(x)->starget_data)->rd_strm)
 #define spi_rti(x)      (((struct spi_transport_attrs *)&(x)->starget_data)->rti)
 #define spi_pcomp_en(x) (((struct spi_transport_attrs *)&(x)->starget_data)->pcomp_en)
+#define spi_hold_mcs(x) (((struct spi_transport_attrs *)&(x)->starget_data)->hold_mcs)
 #define spi_initial_dv(x)       (((struct spi_transport_attrs *)&(x)->starget_data)->initial_dv)
 
 #define spi_support_sync(x)     (((struct spi_transport_attrs *)&(x)->starget_data)->support_sync)
@@ -114,8 +116,11 @@ struct spi_function_template {
         void    (*set_rti)(struct scsi_target *, int);
         void    (*get_pcomp_en)(struct scsi_target *);
         void    (*set_pcomp_en)(struct scsi_target *, int);
+        void    (*get_hold_mcs)(struct scsi_target *);
+        void    (*set_hold_mcs)(struct scsi_target *, int);
         void    (*get_signalling)(struct Scsi_Host *);
         void    (*set_signalling)(struct Scsi_Host *, enum spi_signal_type);
+        int     (*deny_binding)(struct scsi_target *);
         /* The driver sets these to tell the transport class it
          * wants the attributes displayed in sysfs.  If the show_ flag
          * is not set, the attribute will be private to the transport
@@ -130,6 +135,7 @@ struct spi_function_template {
         unsigned long   show_rd_strm:1;
         unsigned long   show_rti:1;
         unsigned long   show_pcomp_en:1;
+        unsigned long   show_hold_mcs:1;
 };
 
 struct scsi_transport_template *spi_attach_transport(struct spi_function_template *);
diff --git a/include/scsi/sg_request.h b/include/scsi/sg_request.h
new file mode 100644
index 000000000000..57ff525bdd3b
--- /dev/null
+++ b/include/scsi/sg_request.h
@@ -0,0 +1,26 @@
+typedef struct scsi_request Scsi_Request;
+
+static Scsi_Request *dummy_cmdp;        /* only used for sizeof */
+
+typedef struct sg_scatter_hold { /* holding area for scsi scatter gather info */
+        unsigned short k_use_sg; /* Count of kernel scatter-gather pieces */
+        unsigned short sglist_len; /* size of malloc'd scatter-gather list ++ */
+        unsigned bufflen;       /* Size of (aggregate) data buffer */
+        unsigned b_malloc_len;  /* actual len malloc'ed in buffer */
+        void *buffer;           /* Data buffer or scatter list (k_use_sg>0) */
+        char dio_in_use;        /* 0->indirect IO (or mmap), 1->dio */
+        unsigned char cmd_opcode; /* first byte of command */
+} Sg_scatter_hold;
+
+typedef struct sg_request {     /* SG_MAX_QUEUE requests outstanding per file */
+        Scsi_Request *my_cmdp;  /* != 0  when request with lower levels */
+        struct sg_request *nextrp;      /* NULL -> tail request (slist) */
+        struct sg_fd *parentfp; /* NULL -> not in use */
+        Sg_scatter_hold data;   /* hold buffer, perhaps scatter list */
+        sg_io_hdr_t header;     /* scsi command+info, see <scsi/sg.h> */
+        unsigned char sense_b[sizeof (dummy_cmdp->sr_sense_buffer)];
+        char res_used;          /* 1 -> using reserve buffer, 0 -> not ... */
+        char orphan;            /* 1 -> drop on sight, 0 -> normal */
+        char sg_io_owned;       /* 1 -> packet belongs to SG_IO */
+        volatile char done;     /* 0->before bh, 1->before read, 2->read */
+} Sg_request;
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
index 2433e279e071..2857cf0472df 100644
--- a/include/sound/ac97_codec.h
+++ b/include/sound/ac97_codec.h
@@ -26,6 +26,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/device.h>
 #include "pcm.h"
 #include "control.h"
 #include "info.h"
@@ -374,6 +375,9 @@
 #define AC97_HAS_NO_PC_BEEP     (1<<12) /* no PC Beep volume */
 #define AC97_HAS_NO_VIDEO       (1<<13) /* no Video volume */
 #define AC97_HAS_NO_CD          (1<<14) /* no CD volume */
+#define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */
+#define AC97_HAS_NO_TONE        (1<<16) /* no Tone volume */
+#define AC97_HAS_NO_STD_PCM     (1<<17) /* no standard AC97 PCM volume and mute */
 
 /* rates indexes */
 #define AC97_RATES_FRONT_DAC    0
@@ -437,6 +441,7 @@ struct snd_ac97_build_ops {
         void (*suspend) (ac97_t *ac97);
         void (*resume) (ac97_t *ac97);
 #endif
+        void (*update_jacks) (ac97_t *ac97);    /* for jack-sharing */
 };
 
 struct _snd_ac97_bus_ops {
@@ -516,6 +521,10 @@ struct _snd_ac97 {
                 } ad18xx;
                 unsigned int dev_flags;         /* device specific */
         } spec;
+        /* jack-sharing info */
+        unsigned char indep_surround;
+        unsigned char channel_mode;
+        struct device dev;
 };
 
 /* conditions */
@@ -569,8 +578,8 @@ enum {
 };
 
 struct ac97_quirk {
-        unsigned short vendor;  /* PCI vendor id */
-        unsigned short device;  /* PCI device id */
+        unsigned short subvendor; /* PCI subsystem vendor id */
+        unsigned short subdevice; /* PCI sybsystem device id */
         unsigned short mask;    /* device id bit mask, 0 = accept all */
         unsigned int codec_id;  /* codec id (if any), 0 = accept all */
         const char *name;       /* name shown as info */
@@ -595,4 +604,8 @@ struct ac97_enum {
         unsigned short mask;
         const char **texts;
 };
+
+/* ad hoc AC97 device driver access */
+extern struct bus_type ac97_bus_type;
+
 #endif /* __SOUND_AC97_CODEC_H */
diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h
index 395978e375cf..ca2e0e4fa937 100644
--- a/include/sound/ad1816a.h
+++ b/include/sound/ad1816a.h
@@ -138,6 +138,7 @@ struct _snd_ad1816a {
         spinlock_t lock;
 
         unsigned short mode;
+        unsigned int clock_freq;
 
         snd_card_t *card;
         snd_pcm_t *pcm;
diff --git a/include/sound/asound.h b/include/sound/asound.h
index a4d149f34541..8e552d627fa5 100644
--- a/include/sound/asound.h
+++ b/include/sound/asound.h
@@ -113,9 +113,10 @@ enum sndrv_hwdep_iface {
         SNDRV_HWDEP_IFACE_BLUETOOTH,    /* Bluetooth audio */
         SNDRV_HWDEP_IFACE_USX2Y_PCM,    /* Tascam US122, US224 & US428 rawusb pcm */
         SNDRV_HWDEP_IFACE_PCXHR,        /* Digigram PCXHR */
+        SNDRV_HWDEP_IFACE_SB_RC,        /* SB Extigy/Audigy2NX remote control */
 
         /* Don't forget to change the following: */
-        SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_PCXHR
+        SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_SB_RC
 };
 
 struct sndrv_hwdep_info {
@@ -344,7 +345,7 @@ enum sndrv_pcm_hw_param {
         SNDRV_PCM_HW_PARAM_LAST_INTERVAL = SNDRV_PCM_HW_PARAM_TICK_TIME
 };
 
-#define SNDRV_PCM_HW_PARAMS_RUNTIME             (1<<0)
+#define SNDRV_PCM_HW_PARAMS_NORESAMPLE          (1<<0)  /* avoid rate resampling */
 
 struct sndrv_interval {
         unsigned int min, max;
@@ -559,7 +560,7 @@ enum {
  *  Timer section - /dev/snd/timer
  */
 
-#define SNDRV_TIMER_VERSION             SNDRV_PROTOCOL_VERSION(2, 0, 2)
+#define SNDRV_TIMER_VERSION             SNDRV_PROTOCOL_VERSION(2, 0, 5)
 
 enum sndrv_timer_class {
         SNDRV_TIMER_CLASS_NONE = -1,
@@ -672,10 +673,11 @@ enum {
         SNDRV_TIMER_IOCTL_INFO = _IOR('T', 0x11, struct sndrv_timer_info),
         SNDRV_TIMER_IOCTL_PARAMS = _IOW('T', 0x12, struct sndrv_timer_params),
         SNDRV_TIMER_IOCTL_STATUS = _IOR('T', 0x14, struct sndrv_timer_status),
-        SNDRV_TIMER_IOCTL_START = _IO('T', 0x20),
-        SNDRV_TIMER_IOCTL_STOP = _IO('T', 0x21),
-        SNDRV_TIMER_IOCTL_CONTINUE = _IO('T', 0x22),
-        SNDRV_TIMER_IOCTL_PAUSE = _IO('T', 0x23),
+        /* The following four ioctls are changed since 1.0.9 due to confliction */
+        SNDRV_TIMER_IOCTL_START = _IO('T', 0xa0),
+        SNDRV_TIMER_IOCTL_STOP = _IO('T', 0xa1),
+        SNDRV_TIMER_IOCTL_CONTINUE = _IO('T', 0xa2),
+        SNDRV_TIMER_IOCTL_PAUSE = _IO('T', 0xa3),
 };
 
 struct sndrv_timer_read {
@@ -691,11 +693,15 @@ enum sndrv_timer_event {
         SNDRV_TIMER_EVENT_CONTINUE,             /* val = resolution in ns */
         SNDRV_TIMER_EVENT_PAUSE,                /* val = 0 */
         SNDRV_TIMER_EVENT_EARLY,                /* val = 0, early event */
+        SNDRV_TIMER_EVENT_SUSPEND,              /* val = 0 */
+        SNDRV_TIMER_EVENT_RESUME,               /* val = resolution in ns */
         /* master timer events for slave timer instances */
         SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
         SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
         SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
         SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
+        SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
+        SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
 };
 
 struct sndrv_timer_tread {
diff --git a/include/sound/control.h b/include/sound/control.h
index 7b9444cd02f4..ef7903c7a327 100644
--- a/include/sound/control.h
+++ b/include/sound/control.h
@@ -106,7 +106,7 @@ typedef int (*snd_kctl_ioctl_func_t) (snd_card_t * card,
 void snd_ctl_notify(snd_card_t * card, unsigned int mask, snd_ctl_elem_id_t * id);
 
 snd_kcontrol_t *snd_ctl_new(snd_kcontrol_t * kcontrol, unsigned int access);
-snd_kcontrol_t *snd_ctl_new1(snd_kcontrol_new_t * kcontrolnew, void * private_data);
+snd_kcontrol_t *snd_ctl_new1(const snd_kcontrol_new_t * kcontrolnew, void * private_data);
 void snd_ctl_free_one(snd_kcontrol_t * kcontrol);
 int snd_ctl_add(snd_card_t * card, snd_kcontrol_t * kcontrol);
 int snd_ctl_remove(snd_card_t * card, snd_kcontrol_t * kcontrol);
diff --git a/include/sound/core.h b/include/sound/core.h
index 9117c23e3a01..3dc41fd5c54d 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -126,25 +126,26 @@ struct snd_monitor_file {
         struct snd_monitor_file *next;
 };
 
-struct snd_shutdown_f_ops;      /* define it later */
+struct snd_shutdown_f_ops;      /* define it later in init.c */
 
 /* main structure for soundcard */
 
 struct _snd_card {
-        int number;                     /* number of soundcard (index to snd_cards) */
+        int number;                     /* number of soundcard (index to
+                                                                snd_cards) */
 
         char id[16];                    /* id string of this card */
         char driver[16];                /* driver name */
         char shortname[32];             /* short name of this soundcard */
         char longname[80];              /* name of this soundcard */
         char mixername[80];             /* mixer name */
-        char components[80];            /* card components delimited with space */
-
+        char components[80];            /* card components delimited with
+                                                                space */
         struct module *module;          /* top-level module */
 
         void *private_data;             /* private data for soundcard */
-        void (*private_free) (snd_card_t *card); /* callback for freeing of private data */
-
+        void (*private_free) (snd_card_t *card); /* callback for freeing of
+                                                                private data */
         struct list_head devices;       /* devices */
 
         unsigned int last_numid;        /* last used numeric ID */
@@ -160,7 +161,8 @@ struct _snd_card {
         struct proc_dir_entry *proc_root_link;  /* number link to real id */
 
         struct snd_monitor_file *files; /* all files associated to this card */
-        struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */
+        struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown
+                                                                state */
         spinlock_t files_lock;          /* lock the files for this card */
         int shutdown;                   /* this card is going down */
         wait_queue_head_t shutdown_sleep;
@@ -196,8 +198,6 @@ static inline void snd_power_unlock(snd_card_t *card)
         up(&card->power_lock);
 }
 
-int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
-
 static inline unsigned int snd_power_get_state(snd_card_t *card)
 {
         return card->power_state;
@@ -208,6 +208,10 @@ static inline void snd_power_change_state(snd_card_t *card, unsigned int state)
         card->power_state = state;
         wake_up(&card->power_sleep);
 }
+
+/* init.c */
+int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
+
 int snd_card_set_pm_callback(snd_card_t *card,
                              int (*suspend)(snd_card_t *, pm_message_t),
                              int (*resume)(snd_card_t *),
@@ -238,15 +242,14 @@ static inline int snd_power_wait(snd_card_t *card, unsigned int state, struct fi
 
 #endif /* CONFIG_PM */
 
-/* device.c */
-
 struct _snd_minor {
         struct list_head list;          /* list of all minors per card */
         int number;                     /* minor number */
         int device;                     /* device number */
         const char *comment;            /* for /proc/asound/devices */
         struct file_operations *f_ops;  /* file operations */
-        char name[0];                   /* device name (keep at the end of structure) */
+        char name[0];                   /* device name (keep at the end of
+                                                                structure) */
 };
 
 typedef struct _snd_minor snd_minor_t;
@@ -287,12 +290,15 @@ void snd_memory_init(void);
 void snd_memory_done(void);
 int snd_memory_info_init(void);
 int snd_memory_info_done(void);
-void *snd_hidden_kmalloc(size_t size, int flags);
-void *snd_hidden_kcalloc(size_t n, size_t size, int flags);
+void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags);
+void *snd_hidden_kzalloc(size_t size, unsigned int __nocast flags);
+void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags);
 void snd_hidden_kfree(const void *obj);
 void *snd_hidden_vmalloc(unsigned long size);
 void snd_hidden_vfree(void *obj);
+char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags);
 #define kmalloc(size, flags) snd_hidden_kmalloc(size, flags)
+#define kzalloc(size, flags) snd_hidden_kzalloc(size, flags)
 #define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags)
 #define kfree(obj) snd_hidden_kfree(obj)
 #define vmalloc(size) snd_hidden_vmalloc(size)
@@ -301,6 +307,7 @@ void snd_hidden_vfree(void *obj);
 #define vmalloc_nocheck(size) snd_wrapper_vmalloc(size)
 #define kfree_nocheck(obj) snd_wrapper_kfree(obj)
 #define vfree_nocheck(obj) snd_wrapper_vfree(obj)
+#define kstrdup(s, flags)  snd_hidden_kstrdup(s, flags)
 #else
 #define snd_memory_init() /*NOP*/
 #define snd_memory_done() /*NOP*/
@@ -311,7 +318,6 @@ void snd_hidden_vfree(void *obj);
 #define kfree_nocheck(obj) kfree(obj)
 #define vfree_nocheck(obj) vfree(obj)
 #endif
-char *snd_kmalloc_strdup(const char *string, int flags);
 int copy_to_user_fromio(void __user *dst, const volatile void __iomem *src, size_t count);
 int copy_from_user_toio(volatile void __iomem *dst, const void __user *src, size_t count);
 
@@ -356,11 +362,13 @@ int snd_device_free_all(snd_card_t *card, snd_device_cmd_t cmd);
 
 /* isadma.c */
 
+#ifdef CONFIG_ISA_DMA_API
 #define DMA_MODE_NO_ENABLE      0x0100
 
 void snd_dma_program(unsigned long dma, unsigned long addr, unsigned int size, unsigned short mode);
 void snd_dma_disable(unsigned long dma);
 unsigned int snd_dma_pointer(unsigned long dma, unsigned int size);
+#endif
 
 /* misc.c */
 
@@ -410,7 +418,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
         printk(fmt ,##args)
 #endif
 /**
- * snd_assert - run-time assersion macro
+ * snd_assert - run-time assertion macro
  * @expr: expression
  * @args...: the action
  *
@@ -426,7 +434,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
         }\
 } while (0)
 /**
- * snd_runtime_check - run-time assersion macro
+ * snd_runtime_check - run-time assertion macro
  * @expr: expression
  * @args...: the action
  *
diff --git a/include/sound/cs46xx.h b/include/sound/cs46xx.h
index 182dd276ee74..9b94510eda60 100644
--- a/include/sound/cs46xx.h
+++ b/include/sound/cs46xx.h
@@ -1748,7 +1748,7 @@ int snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
 int snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
 int snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
 int snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t **rpcm);
-int snd_cs46xx_mixer(cs46xx_t *chip);
+int snd_cs46xx_mixer(cs46xx_t *chip, int spdif_device);
 int snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rmidi);
 int snd_cs46xx_start_dsp(cs46xx_t *chip);
 int snd_cs46xx_gameport(cs46xx_t *chip);
diff --git a/include/sound/driver.h b/include/sound/driver.h
index 948e9a1aebef..0d12456ec3ae 100644
--- a/include/sound/driver.h
+++ b/include/sound/driver.h
@@ -51,7 +51,7 @@
 #ifdef CONFIG_SND_DEBUG_MEMORY
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
-void *snd_wrapper_kmalloc(size_t, int);
+void *snd_wrapper_kmalloc(size_t, unsigned int __nocast);
 #undef kmalloc
 void snd_wrapper_kfree(const void *);
 #undef kfree
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 43b6786abae5..4e3993dfcefe 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -83,7 +83,8 @@
 #define IPR                     0x08            /* Global interrupt pending register            */
                                                 /* Clear pending interrupts by writing a 1 to   */
                                                 /* the relevant bits and zero to the other bits */
-
+#define IPR_P16V                0x80000000      /* Bit set when the CA0151 P16V chip wishes
+                                                   to interrupt */
 #define IPR_GPIOMSG             0x20000000      /* GPIO message interrupt (RE'd, still not sure 
                                                    which INTE bits enable it)                   */
 
@@ -746,6 +747,7 @@
                                                 /* Assumes sample lock                          */
 
 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS.                 */
+#define SRCS_SPDIFVALID         0x04000000      /* SPDIF stream valid                           */
 #define SRCS_SPDIFLOCKED        0x02000000      /* SPDIF stream locked                          */
 #define SRCS_RATELOCKED         0x01000000      /* Sample rate locked                           */
 #define SRCS_ESTSAMPLERATE      0x0007ffff      /* Do not modify this field.                    */
@@ -803,10 +805,26 @@
 #define A_FXWC2                 0x75            /* Selects 0x9f-0x80 for FX recording           */
 
 #define A_SPDIF_SAMPLERATE      0x76            /* Set the sample rate of SPDIF output          */
-#define A_SPDIF_RATE_MASK       0x000000c0
+#define A_SAMPLE_RATE           0x76            /* Various sample rate settings. */
+#define A_SAMPLE_RATE_NOT_USED  0x0ffc111e      /* Bits that are not used and cannot be set.    */
+#define A_SAMPLE_RATE_UNKNOWN   0xf0030001      /* Bits that can be set, but have unknown use.  */
+#define A_SPDIF_RATE_MASK       0x000000e0      /* Any other values for rates, just use 48000   */
 #define A_SPDIF_48000           0x00000000
-#define A_SPDIF_44100           0x00000080
+#define A_SPDIF_192000          0x00000020
 #define A_SPDIF_96000           0x00000040
+#define A_SPDIF_44100           0x00000080
+
+#define A_I2S_CAPTURE_RATE_MASK 0x00000e00      /* This sets the capture PCM rate, but it is    */
+#define A_I2S_CAPTURE_48000     0x00000000      /* unclear if this sets the ADC rate as well.   */
+#define A_I2S_CAPTURE_192000    0x00000200
+#define A_I2S_CAPTURE_96000     0x00000400
+#define A_I2S_CAPTURE_44100     0x00000800
+
+#define A_PCM_RATE_MASK         0x0000e000      /* This sets the playback PCM rate on the P16V  */
+#define A_PCM_48000             0x00000000
+#define A_PCM_192000            0x00002000
+#define A_PCM_96000             0x00004000
+#define A_PCM_44100             0x00008000
 
 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell  */
 /* 0x7a, 0x7b - lookup tables */
@@ -1039,28 +1057,28 @@ typedef struct {
         u32 vendor;
         u32 device;
         u32 subsystem;
+        unsigned char revision;
         unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
         unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
         unsigned char ca0102_chip;  /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
         unsigned char ca0108_chip;  /* Audigy 2 Value */
         unsigned char ca0151_chip;  /* P16V */
         unsigned char spk71;        /* Has 7.1 speakers */
+        unsigned char sblive51;     /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
         unsigned char spdif_bug;    /* Has Spdif phasing bug */
         unsigned char ac97_chip;    /* Has an AC97 chip */
         unsigned char ecard;        /* APS EEPROM */
-        char * driver;
-        char * name;
+        const char *driver;
+        const char *name;
+        const char *id;         /* for backward compatibility - can be NULL if not needed */
 } emu_chip_details_t;
 
 struct _snd_emu10k1 {
         int irq;
 
         unsigned long port;                     /* I/O port number */
-        unsigned int APS: 1,                    /* APS flag */
-            no_ac97: 1,                         /* no AC'97 */
-            tos_link: 1,                        /* tos link detected */
-            rear_ac97: 1,                       /* rear channels are on AC'97 */
-            spk71:1;                            /* 7.1 configuration (Audigy 2 ZS) */
+        unsigned int tos_link: 1,               /* tos link detected */
+            rear_ac97: 1;                       /* rear channels are on AC'97 */
         const emu_chip_details_t *card_capabilities;    /* Contains profile of card capabilities */
         unsigned int audigy;                    /* is Audigy? */
         unsigned int revision;                  /* chip revision */
@@ -1109,7 +1127,10 @@ struct _snd_emu10k1 {
 
         emu10k1_voice_t voices[NUM_G];
         emu10k1_voice_t p16v_voices[4];
+        emu10k1_voice_t p16v_capture_voice;
         int p16v_device_offset;
+        u32 p16v_capture_source;
+        u32 p16v_capture_channel;
         emu10k1_pcm_mixer_t pcm_mixer[32];
         emu10k1_pcm_mixer_t efx_pcm_mixer[NUM_EFX_PLAYBACK];
         snd_kcontrol_t *ctl_send_routing;
@@ -1146,6 +1167,7 @@ int snd_emu10k1_create(snd_card_t * card,
                        unsigned short extout_mask,
                        long max_cache_bytes,
                        int enable_ir,
+                       uint subsystem,
                        emu10k1_t ** remu);
 
 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
@@ -1156,7 +1178,7 @@ int snd_p16v_free(emu10k1_t * emu);
 int snd_p16v_mixer(emu10k1_t * emu);
 int snd_emu10k1_pcm_multi(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
 int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
-int snd_emu10k1_mixer(emu10k1_t * emu);
+int snd_emu10k1_mixer(emu10k1_t * emu, int pcm_device, int multi_device);
 int snd_emu10k1_timer(emu10k1_t * emu, int device);
 int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
 
@@ -1453,7 +1475,6 @@ int snd_emu10k1_fx8010_unregister_irq_handler(emu10k1_t *emu,
 #endif
 
 typedef struct {
-        unsigned int card;                      /* card type */
         unsigned int internal_tram_size;        /* in samples */
         unsigned int external_tram_size;        /* in samples */
         char fxbus_names[16][32];               /* names of FXBUSes */
diff --git a/include/sound/gus.h b/include/sound/gus.h
index 8b6287a6fff5..7000d9d9199d 100644
--- a/include/sound/gus.h
+++ b/include/sound/gus.h
@@ -512,13 +512,13 @@ extern void snd_gf1_ctrl_stop(snd_gus_card_t * gus, unsigned char reg);
 
 extern void snd_gf1_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
 extern unsigned char snd_gf1_look8(snd_gus_card_t * gus, unsigned char reg);
-extern inline unsigned char snd_gf1_read8(snd_gus_card_t * gus, unsigned char reg)
+static inline unsigned char snd_gf1_read8(snd_gus_card_t * gus, unsigned char reg)
 {
         return snd_gf1_look8(gus, reg | 0x80);
 }
 extern void snd_gf1_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data);
 extern unsigned short snd_gf1_look16(snd_gus_card_t * gus, unsigned char reg);
-extern inline unsigned short snd_gf1_read16(snd_gus_card_t * gus, unsigned char reg)
+static inline unsigned short snd_gf1_read16(snd_gus_card_t * gus, unsigned char reg)
 {
         return snd_gf1_look16(gus, reg | 0x80);
 }
@@ -526,27 +526,21 @@ extern void snd_gf1_adlib_write(snd_gus_card_t * gus, unsigned char reg, unsigne
 extern void snd_gf1_dram_addr(snd_gus_card_t * gus, unsigned int addr);
 extern void snd_gf1_poke(snd_gus_card_t * gus, unsigned int addr, unsigned char data);
 extern unsigned char snd_gf1_peek(snd_gus_card_t * gus, unsigned int addr);
-extern void snd_gf1_pokew(snd_gus_card_t * gus, unsigned int addr, unsigned short data);
-extern unsigned short snd_gf1_peekw(snd_gus_card_t * gus, unsigned int addr);
-extern void snd_gf1_dram_setmem(snd_gus_card_t * gus, unsigned int addr, unsigned short value, unsigned int count);
 extern void snd_gf1_write_addr(snd_gus_card_t * gus, unsigned char reg, unsigned int addr, short w_16bit);
 extern unsigned int snd_gf1_read_addr(snd_gus_card_t * gus, unsigned char reg, short w_16bit);
 extern void snd_gf1_i_ctrl_stop(snd_gus_card_t * gus, unsigned char reg);
 extern void snd_gf1_i_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
 extern unsigned char snd_gf1_i_look8(snd_gus_card_t * gus, unsigned char reg);
 extern void snd_gf1_i_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data);
-extern inline unsigned char snd_gf1_i_read8(snd_gus_card_t * gus, unsigned char reg)
+static inline unsigned char snd_gf1_i_read8(snd_gus_card_t * gus, unsigned char reg)
 {
         return snd_gf1_i_look8(gus, reg | 0x80);
 }
 extern unsigned short snd_gf1_i_look16(snd_gus_card_t * gus, unsigned char reg);
-extern inline unsigned short snd_gf1_i_read16(snd_gus_card_t * gus, unsigned char reg)
+static inline unsigned short snd_gf1_i_read16(snd_gus_card_t * gus, unsigned char reg)
 {
         return snd_gf1_i_look16(gus, reg | 0x80);
 }
-extern void snd_gf1_i_adlib_write(snd_gus_card_t * gus, unsigned char reg, unsigned char data);
-extern void snd_gf1_i_write_addr(snd_gus_card_t * gus, unsigned char reg, unsigned int addr, short w_16bit);
-extern unsigned int snd_gf1_i_read_addr(snd_gus_card_t * gus, unsigned char reg, short w_16bit);
 
 extern void snd_gf1_select_active_voices(snd_gus_card_t * gus);
 
@@ -580,10 +574,6 @@ extern void snd_gf1_lfo_command(snd_gus_card_t * gus, int voice, unsigned char *
 
 void snd_gf1_mem_lock(snd_gf1_mem_t * alloc, int xup);
 int snd_gf1_mem_xfree(snd_gf1_mem_t * alloc, snd_gf1_mem_block_t * block);
-snd_gf1_mem_block_t *snd_gf1_mem_look(snd_gf1_mem_t * alloc,
-                                      unsigned int address);
-snd_gf1_mem_block_t *snd_gf1_mem_share(snd_gf1_mem_t * alloc,
-                                       unsigned int *share_id);
 snd_gf1_mem_block_t *snd_gf1_mem_alloc(snd_gf1_mem_t * alloc, int owner,
                                        char *name, int size, int w_16,
                                        int align, unsigned int *share_id);
@@ -608,23 +598,13 @@ int snd_gf1_dma_transfer_block(snd_gus_card_t * gus,
 /* gus_volume.c */
 
 unsigned short snd_gf1_lvol_to_gvol_raw(unsigned int vol);
-unsigned int snd_gf1_gvol_to_lvol_raw(unsigned short gf1_vol);
-unsigned int snd_gf1_calc_ramp_rate(snd_gus_card_t * gus,
-                                    unsigned short start,
-                                    unsigned short end,
-                                    unsigned int us);
 unsigned short snd_gf1_translate_freq(snd_gus_card_t * gus, unsigned int freq2);
-unsigned short snd_gf1_compute_pitchbend(unsigned short pitchbend, unsigned short sens);
-unsigned short snd_gf1_compute_freq(unsigned int freq,
-                                    unsigned int rate,
-                                    unsigned short mix_rate);
 
 /* gus_reset.c */
 
 void snd_gf1_set_default_handlers(snd_gus_card_t * gus, unsigned int what);
 void snd_gf1_smart_stop_voice(snd_gus_card_t * gus, unsigned short voice);
 void snd_gf1_stop_voice(snd_gus_card_t * gus, unsigned short voice);
-void snd_gf1_clear_voices(snd_gus_card_t * gus, unsigned short v_min, unsigned short v_max);
 void snd_gf1_stop_voices(snd_gus_card_t * gus, unsigned short v_min, unsigned short v_max);
 snd_gus_voice_t *snd_gf1_alloc_voice(snd_gus_card_t * gus, int type, int client, int port);
 void snd_gf1_free_voice(snd_gus_card_t * gus, snd_gus_voice_t *voice);
@@ -641,9 +621,6 @@ int snd_gf1_pcm_new(snd_gus_card_t * gus, int pcm_dev, int control_index, snd_pc
 
 #ifdef CONFIG_SND_DEBUG
 extern void snd_gf1_print_voice_registers(snd_gus_card_t * gus);
-extern void snd_gf1_print_global_registers(snd_gus_card_t * gus);
-extern void snd_gf1_print_setup_registers(snd_gus_card_t * gus);
-extern void snd_gf1_peek_print_block(snd_gus_card_t * gus, unsigned int addr, int count, int w_16bit);
 #endif
 
 /* gus.c */
diff --git a/include/sound/hdspm.h b/include/sound/hdspm.h
new file mode 100644
index 000000000000..c34427ccd0b3
--- /dev/null
+++ b/include/sound/hdspm.h
@@ -0,0 +1,131 @@
+#ifndef __SOUND_HDSPM_H         /* -*- linux-c -*- */
+#define __SOUND_HDSPM_H
+/*
+ *   Copyright (C) 2003 Winfried Ritsch (IEM)
+ *   based on hdsp.h from Thomas Charbonnel (thomas@undata.org)
+ *                      
+ *    
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Maximum channels is 64 even on 56Mode you have 64playbacks to matrix */
+#define HDSPM_MAX_CHANNELS      64
+
+/* -------------------- IOCTL Peak/RMS Meters -------------------- */
+
+typedef struct _snd_hdspm_peak_rms hdspm_peak_rms_t;
+
+/* peam rms level structure like we get from hardware 
+  
+   maybe in future we can memory map it so I just copy it
+   to user on ioctl call now an dont change anything
+   rms are made out of low and high values
+   where (long) ????_rms = (????_rms_l >> 8) + ((????_rms_h & 0xFFFFFF00)<<24)
+   (i asume so from the code)
+*/
+
+struct _snd_hdspm_peak_rms {
+
+        unsigned int level_offset[1024];
+
+        unsigned int input_peak[64];
+        unsigned int playback_peak[64];
+        unsigned int output_peak[64];
+        unsigned int xxx_peak[64];      /* not used */
+
+        unsigned int reserved[256];     /* not used */
+
+        unsigned int input_rms_l[64];
+        unsigned int playback_rms_l[64];
+        unsigned int output_rms_l[64];
+        unsigned int xxx_rms_l[64];     /* not used */
+
+        unsigned int input_rms_h[64];
+        unsigned int playback_rms_h[64];
+        unsigned int output_rms_h[64];
+        unsigned int xxx_rms_h[64];     /* not used */
+};
+
+struct sndrv_hdspm_peak_rms_ioctl {
+        hdspm_peak_rms_t *peak;
+};
+
+/* use indirect access due to the limit of ioctl bit size */
+#define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS _IOR('H', 0x40, struct sndrv_hdspm_peak_rms_ioctl)
+
+/* ------------ CONFIG block IOCTL ---------------------- */
+
+typedef struct _snd_hdspm_config_info hdspm_config_info_t;
+
+struct _snd_hdspm_config_info {
+        unsigned char pref_sync_ref;
+        unsigned char wordclock_sync_check;
+        unsigned char madi_sync_check;
+        unsigned int system_sample_rate;
+        unsigned int autosync_sample_rate;
+        unsigned char system_clock_mode;
+        unsigned char clock_source;
+        unsigned char autosync_ref;
+        unsigned char line_out;
+        unsigned int passthru;
+        unsigned int analog_out;
+};
+
+#define SNDRV_HDSPM_IOCTL_GET_CONFIG_INFO _IOR('H', 0x41, hdspm_config_info_t)
+
+
+/* get Soundcard Version */
+
+typedef struct _snd_hdspm_version hdspm_version_t;
+
+struct _snd_hdspm_version {
+        unsigned short firmware_rev;
+};
+
+#define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x43, hdspm_version_t)
+
+
+/* ------------- get Matrix Mixer IOCTL --------------- */
+
+/* MADI mixer: 64inputs+64playback in 64outputs = 8192 => *4Byte = 32768 Bytes */
+
+/* organisation is 64 channelfader in a continous memory block */
+/* equivalent to hardware definition, maybe for future feature of mmap of them */
+/* each of 64 outputs has 64 infader and 64 outfader: 
+   Ins to Outs mixer[out].in[in], Outstreams to Outs mixer[out].pb[pb] */
+
+#define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS
+
+typedef struct _snd_hdspm_channelfader snd_hdspm_channelfader_t;
+
+struct _snd_hdspm_channelfader {
+        unsigned int in[HDSPM_MIXER_CHANNELS];
+        unsigned int pb[HDSPM_MIXER_CHANNELS];
+};
+
+typedef struct _snd_hdspm_mixer hdspm_mixer_t;
+
+struct _snd_hdspm_mixer {
+        snd_hdspm_channelfader_t ch[HDSPM_MIXER_CHANNELS];
+};
+
+struct sndrv_hdspm_mixer_ioctl {
+        hdspm_mixer_t *mixer;
+};
+
+/* use indirect access due to the limit of ioctl bit size */
+#define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct sndrv_hdspm_mixer_ioctl)
+
+#endif                          /* __SOUND_HDSPM_H */
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 53fc04d75bad..389e8ebe9c19 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -379,7 +379,6 @@ struct _snd_pcm_substream {
         unsigned int dma_buf_id;
         size_t dma_max;
         /* -- hardware operations -- */
-        unsigned int open_flag: 1;      /* lowlevel device has been opened */
         snd_pcm_ops_t *ops;
         /* -- runtime information -- */
         snd_pcm_runtime_t *runtime;
@@ -848,23 +847,6 @@ int snd_interval_ratnum(snd_interval_t *i,
 
 void _snd_pcm_hw_params_any(snd_pcm_hw_params_t *params);
 void _snd_pcm_hw_param_setempty(snd_pcm_hw_params_t *params, snd_pcm_hw_param_t var);
-int snd_pcm_hw_param_min(snd_pcm_substream_t *substream, 
-                         snd_pcm_hw_params_t *params,
-                         snd_pcm_hw_param_t var,
-                         unsigned int val, int *dir);
-int snd_pcm_hw_param_max(snd_pcm_substream_t *substream, 
-                         snd_pcm_hw_params_t *params,
-                         snd_pcm_hw_param_t var,
-                         unsigned int val, int *dir);
-int snd_pcm_hw_param_setinteger(snd_pcm_substream_t *substream, 
-                                snd_pcm_hw_params_t *params,
-                                snd_pcm_hw_param_t var);
-int snd_pcm_hw_param_first(snd_pcm_substream_t *substream, 
-                           snd_pcm_hw_params_t *params,
-                           snd_pcm_hw_param_t var, int *dir);
-int snd_pcm_hw_param_last(snd_pcm_substream_t *substream, 
-                          snd_pcm_hw_params_t *params,
-                          snd_pcm_hw_param_t var, int *dir);
 int snd_pcm_hw_param_near(snd_pcm_substream_t *substream, 
                           snd_pcm_hw_params_t *params,
                           snd_pcm_hw_param_t var, 
@@ -876,7 +858,6 @@ int snd_pcm_hw_param_set(snd_pcm_substream_t *pcm,
 int snd_pcm_hw_params_choose(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
 
 int snd_pcm_hw_refine(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
-int snd_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *params);
 
 int snd_pcm_hw_constraints_init(snd_pcm_substream_t *substream);
 int snd_pcm_hw_constraints_complete(snd_pcm_substream_t *substream);
@@ -922,8 +903,22 @@ int snd_pcm_format_unsigned(snd_pcm_format_t format);
 int snd_pcm_format_linear(snd_pcm_format_t format);
 int snd_pcm_format_little_endian(snd_pcm_format_t format);
 int snd_pcm_format_big_endian(snd_pcm_format_t format);
+/*
+ * snd_pcm_format_cpu_endian - Check the PCM format is CPU-endian
+ * @format: the format to check
+ *
+ * Returns 1 if the given PCM format is CPU-endian, 0 if
+ * opposite, or a negative error code if endian not specified.
+ */
+/* int snd_pcm_format_cpu_endian(snd_pcm_format_t format); */
+#ifdef SNDRV_LITTLE_ENDIAN
+#define snd_pcm_format_cpu_endian       snd_pcm_format_little_endian
+#else
+#define snd_pcm_format_cpu_endian       snd_pcm_format_big_endian
+#endif
 int snd_pcm_format_width(snd_pcm_format_t format);                      /* in bits */
 int snd_pcm_format_physical_width(snd_pcm_format_t format);             /* in bits */
+ssize_t snd_pcm_format_size(snd_pcm_format_t format, size_t samples);
 const unsigned char *snd_pcm_format_silence_64(snd_pcm_format_t format);
 int snd_pcm_format_set_silence(snd_pcm_format_t format, void *buf, unsigned int frames);
 snd_pcm_format_t snd_pcm_build_linear_format(int width, int unsignd, int big_endian);
diff --git a/include/sound/seq_midi_event.h b/include/sound/seq_midi_event.h
index 4357cac07500..8857e2bd31a5 100644
--- a/include/sound/seq_midi_event.h
+++ b/include/sound/seq_midi_event.h
@@ -41,9 +41,7 @@ struct snd_midi_event_t {
 };
 
 int snd_midi_event_new(int bufsize, snd_midi_event_t **rdev);
-int snd_midi_event_resize_buffer(snd_midi_event_t *dev, int bufsize);
 void snd_midi_event_free(snd_midi_event_t *dev);
-void snd_midi_event_init(snd_midi_event_t *dev);
 void snd_midi_event_reset_encode(snd_midi_event_t *dev);
 void snd_midi_event_reset_decode(snd_midi_event_t *dev);
 void snd_midi_event_no_status(snd_midi_event_t *dev, int on);
diff --git a/include/sound/seq_virmidi.h b/include/sound/seq_virmidi.h
index cf4e2388103f..1ad27e859af3 100644
--- a/include/sound/seq_virmidi.h
+++ b/include/sound/seq_virmidi.h
@@ -79,6 +79,5 @@ struct _snd_virmidi_dev {
 #define SNDRV_VIRMIDI_SEQ_DISPATCH      2
 
 int snd_virmidi_new(snd_card_t *card, int device, snd_rawmidi_t **rrmidi);
-int snd_virmidi_receive(snd_rawmidi_t *rmidi, snd_seq_event_t *ev);
 
 #endif /* __SOUND_SEQ_VIRMIDI */
diff --git a/include/sound/timer.h b/include/sound/timer.h
index 57fde990606e..1898511a0f38 100644
--- a/include/sound/timer.h
+++ b/include/sound/timer.h
@@ -152,6 +152,4 @@ extern int snd_timer_pause(snd_timer_instance_t * timeri);
 
 extern void snd_timer_interrupt(snd_timer_t * timer, unsigned long ticks_left);
 
-extern unsigned int snd_timer_system_resolution(void);
-
 #endif /* __SOUND_TIMER_H */
diff --git a/include/sound/version.h b/include/sound/version.h
index 98b4230778ed..8d19bfabb7e0 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h.  Generated by configure.  */
-#define CONFIG_SND_VERSION "1.0.9rc2"
-#define CONFIG_SND_DATE "  (Thu Mar 24 10:33:39 2005 UTC)"
+#define CONFIG_SND_VERSION "1.0.10rc1"
+#define CONFIG_SND_DATE " (Tue Aug 30 05:31:08 2005 UTC)"
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h
index a7e29933f2d0..7a60a3888667 100644
--- a/include/sound/vx_core.h
+++ b/include/sound/vx_core.h
@@ -233,37 +233,37 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs);
 /*
  * lowlevel functions
  */
-inline static int vx_test_and_ack(vx_core_t *chip)
+static inline int vx_test_and_ack(vx_core_t *chip)
 {
         snd_assert(chip->ops->test_and_ack, return -ENXIO);
         return chip->ops->test_and_ack(chip);
 }
 
-inline static void vx_validate_irq(vx_core_t *chip, int enable)
+static inline void vx_validate_irq(vx_core_t *chip, int enable)
 {
         snd_assert(chip->ops->validate_irq, return);
         chip->ops->validate_irq(chip, enable);
 }
 
-inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg)
+static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg)
 {
         snd_assert(chip->ops->in8, return 0);
         return chip->ops->in8(chip, reg);
 }
 
-inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg)
+static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg)
 {
         snd_assert(chip->ops->in32, return 0);
         return chip->ops->in32(chip, reg);
 }
 
-inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
+static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
 {
         snd_assert(chip->ops->out8, return);
         chip->ops->out8(chip, reg, val);
 }
 
-inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
+static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
 {
         snd_assert(chip->ops->out32, return);
         chip->ops->out32(chip, reg, val);
@@ -303,14 +303,14 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time);
 /*
  * pseudo-DMA transfer
  */
-inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
+static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
                                        vx_pipe_t *pipe, int count)
 {
         snd_assert(chip->ops->dma_write, return);
         chip->ops->dma_write(chip, runtime, pipe, count);
 }
 
-inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
+static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
                                       vx_pipe_t *pipe, int count)
 {
         snd_assert(chip->ops->dma_read, return);
diff --git a/include/sound/ymfpci.h b/include/sound/ymfpci.h
index 4b570684a6aa..9a3c1e6c820a 100644
--- a/include/sound/ymfpci.h
+++ b/include/sound/ymfpci.h
@@ -295,6 +295,7 @@ struct _snd_ymfpci_pcm {
         unsigned int running: 1;
         unsigned int output_front: 1;
         unsigned int output_rear: 1;
+        unsigned int update_pcm_vol;
         u32 period_size;                /* cached from runtime->period_size */
         u32 buffer_size;                /* cached from runtime->buffer_size */
         u32 period_pos;
@@ -367,6 +368,11 @@ struct _snd_ymfpci {
         int mode_dup4ch;
         int rear_opened;
         int spdif_opened;
+        struct {
+                u16 left;
+                u16 right;
+                snd_kcontrol_t *ctl;
+        } pcm_mixer[32];
 
         spinlock_t reg_lock;
         spinlock_t voice_lock;
diff --git a/include/video/pmag-ba-fb.h b/include/video/pmag-ba-fb.h
index cebef073b9a3..fceb6c0f6583 100644
--- a/include/video/pmag-ba-fb.h
+++ b/include/video/pmag-ba-fb.h
@@ -1,24 +1,27 @@
 /*
- *      linux/drivers/video/pmag-ba-fb.h
+ *      linux/include/video/pmag-ba-fb.h
  *
- *      TurboChannel PMAG-BA framebuffer card support,
- *      Copyright (C) 1999,2000,2001 by
- *      Michael Engel <engel@unix-ag.org>,
- *      Karsten Merker <merker@linuxtag.org>
- *      This file is subject to the terms and conditions of the GNU General
- *      Public License.  See the file COPYING in the main directory of this
- *      archive for more details.
- */
-
-/*
- * Bt459 RAM DAC register base offset (rel. to TC slot base address)
+ *      TURBOchannel PMAG-BA Color Frame Buffer (CFB) card support,
+ *      Copyright (C) 1999, 2000, 2001 by
+ *      Michael Engel <engel@unix-ag.org>,
+ *      Karsten Merker <merker@linuxtag.org>
+ *      Copyright (c) 2005  Maciej W. Rozycki
+ *
+ *      This file is subject to the terms and conditions of the GNU General
+ *      Public License.  See the file COPYING in the main directory of this
+ *      archive for more details.
  */
 
-#define PMAG_BA_BT459_OFFSET                    0x00200000
-
-/*
- * Begin of PMAG-BA framebuffer memory relative to TC slot address,
- * resolution is 1024x864x8
- */
+/* IOmem resource offsets.  */
+#define PMAG_BA_FBMEM           0x000000        /* frame buffer */
+#define PMAG_BA_BT459           0x200000        /* Bt459 RAMDAC */
+#define PMAG_BA_IRQ             0x300000        /* IRQ acknowledge */
+#define PMAG_BA_ROM             0x380000        /* REX option ROM */
+#define PMAG_BA_BT438           0x380000        /* Bt438 clock chip reset */
+#define PMAG_BA_SIZE            0x400000        /* address space size */
 
-#define PMAG_BA_ONBOARD_FBMEM_OFFSET    0x00000000
+/* Bt459 register offsets, byte-wide registers.  */
+#define BT459_ADDR_LO           0x0             /* address low */
+#define BT459_ADDR_HI           0x4             /* address high */
+#define BT459_DATA              0x8             /* data window register */
+#define BT459_CMAP              0xc             /* color map window register */
diff --git a/include/video/pmagb-b-fb.h b/include/video/pmagb-b-fb.h
index 87b81a555139..7539b9087a80 100644
--- a/include/video/pmagb-b-fb.h
+++ b/include/video/pmagb-b-fb.h
@@ -1,32 +1,58 @@
 /*
- *      linux/drivers/video/pmagb-b-fb.h
+ *      linux/include/video/pmagb-b-fb.h
  *
- *      TurboChannel PMAGB-B framebuffer card support,
- *      Copyright (C) 1999, 2000, 2001 by
- *      Michael Engel <engel@unix-ag.org> and 
- *      Karsten Merker <merker@linuxtag.org>
- *      This file is subject to the terms and conditions of the GNU General
- *      Public License.  See the file COPYING in the main directory of this
- *      archive for more details.
+ *      TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support,
+ *      Copyright (C) 1999, 2000, 2001 by
+ *      Michael Engel <engel@unix-ag.org> and
+ *      Karsten Merker <merker@linuxtag.org>
+ *      Copyright (c) 2005  Maciej W. Rozycki
+ *
+ *      This file is subject to the terms and conditions of the GNU General
+ *      Public License.  See the file COPYING in the main directory of this
+ *      archive for more details.
  */
 
+/* IOmem resource offsets.  */
+#define PMAGB_B_ROM             0x000000        /* REX option ROM */
+#define PMAGB_B_SFB             0x100000        /* SFB ASIC */
+#define PMAGB_B_GP0             0x140000        /* general purpose output 0 */
+#define PMAGB_B_GP1             0x180000        /* general purpose output 1 */
+#define PMAGB_B_BT459           0x1c0000        /* Bt459 RAMDAC */
+#define PMAGB_B_FBMEM           0x200000        /* frame buffer */
+#define PMAGB_B_SIZE            0x400000        /* address space size */
 
-/*
- * Bt459 RAM DAC register base offset (rel. to TC slot base address)
- */
-#define PMAGB_B_BT459_OFFSET                    0x001C0000
+/* IOmem register offsets.  */
+#define SFB_REG_VID_HOR         0x64            /* video horizontal setup */
+#define SFB_REG_VID_VER         0x68            /* video vertical setup */
+#define SFB_REG_VID_BASE        0x6c            /* video base address */
+#define SFB_REG_TCCLK_COUNT     0x78            /* TURBOchannel clock count */
+#define SFB_REG_VIDCLK_COUNT    0x7c            /* video clock count */
 
-/*
- * Begin of PMAGB-B framebuffer memory, resolution is configurable:
- * 1024x864x8 or 1280x1024x8, settable by jumper on the card
- */
-#define PMAGB_B_ONBOARD_FBMEM_OFFSET    0x00201000
+/* Video horizontal setup register constants.  All bits are r/w.  */
+#define SFB_VID_HOR_BP_SHIFT    0x15            /* back porch */
+#define SFB_VID_HOR_BP_MASK     0x7f
+#define SFB_VID_HOR_SYN_SHIFT   0x0e            /* sync pulse */
+#define SFB_VID_HOR_SYN_MASK    0x7f
+#define SFB_VID_HOR_FP_SHIFT    0x09            /* front porch */
+#define SFB_VID_HOR_FP_MASK     0x1f
+#define SFB_VID_HOR_PIX_SHIFT   0x00            /* active video */
+#define SFB_VID_HOR_PIX_MASK    0x1ff
 
-/*
- * Bt459 register offsets, byte-wide registers
- */
+/* Video vertical setup register constants.  All bits are r/w.  */
+#define SFB_VID_VER_BP_SHIFT    0x16            /* back porch */
+#define SFB_VID_VER_BP_MASK     0x3f
+#define SFB_VID_VER_SYN_SHIFT   0x10            /* sync pulse */
+#define SFB_VID_VER_SYN_MASK    0x3f
+#define SFB_VID_VER_FP_SHIFT    0x0b            /* front porch */
+#define SFB_VID_VER_FP_MASK     0x1f
+#define SFB_VID_VER_SL_SHIFT    0x00            /* active scan lines */
+#define SFB_VID_VER_SL_MASK     0x7ff
+
+/* Video base address register constants.  All bits are r/w.  */
+#define SFB_VID_BASE_MASK       0x1ff           /* video base row address */
 
-#define BT459_ADR_LOW                   BT459_OFFSET + 0x00     /* addr. low */
-#define BT459_ADR_HIGH                  BT459_OFFSET + 0x04     /* addr. high */
-#define BT459_DATA                      BT459_OFFSET + 0x08     /* r/w data */
-#define BT459_CMAP                      BT459_OFFSET + 0x0C     /* color map */
+/* Bt459 register offsets, byte-wide registers.  */
+#define BT459_ADDR_LO           0x0             /* address low */
+#define BT459_ADDR_HI           0x4             /* address high */
+#define BT459_DATA              0x8             /* data window register */
+#define BT459_CMAP              0xc             /* color map window register */
diff --git a/include/video/w100fb.h b/include/video/w100fb.h
index bd548c2b47c4..e6da2d7ded8c 100644
--- a/include/video/w100fb.h
+++ b/include/video/w100fb.h
@@ -1,21 +1,149 @@
 /*
  *  Support for the w100 frame buffer.
  *
- *  Copyright (c) 2004 Richard Purdie
+ *  Copyright (c) 2004-2005 Richard Purdie
+ *  Copyright (c) 2005 Ian Molton
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
 
+#define W100_GPIO_PORT_A        0
+#define W100_GPIO_PORT_B        1
+
+#define CLK_SRC_XTAL  0
+#define CLK_SRC_PLL   1
+
+struct w100fb_par;
+
+unsigned long w100fb_gpio_read(int port);
+void w100fb_gpio_write(int port, unsigned long value);
+
+/* LCD Specific Routines and Config */
+struct w100_tg_info {
+        void (*change)(struct w100fb_par*);
+        void (*suspend)(struct w100fb_par*);
+        void (*resume)(struct w100fb_par*);
+};
+
+/* General Platform Specific w100 Register Values */
+struct w100_gen_regs {
+        unsigned long lcd_format;
+        unsigned long lcdd_cntl1;
+        unsigned long lcdd_cntl2;
+        unsigned long genlcd_cntl1;
+        unsigned long genlcd_cntl2;
+        unsigned long genlcd_cntl3;
+};
+
+struct w100_gpio_regs {
+        unsigned long init_data1;
+        unsigned long init_data2;
+        unsigned long gpio_dir1;
+        unsigned long gpio_oe1;
+        unsigned long gpio_dir2;
+        unsigned long gpio_oe2;
+};
+
+/* Optional External Memory Configuration */
+struct w100_mem_info {
+        unsigned long ext_cntl;
+        unsigned long sdram_mode_reg;
+        unsigned long ext_timing_cntl;
+        unsigned long io_cntl;
+        unsigned int size;
+};
+
+struct w100_bm_mem_info {
+        unsigned long ext_mem_bw;
+        unsigned long offset;
+        unsigned long ext_timing_ctl;
+        unsigned long ext_cntl;
+        unsigned long mode_reg;
+        unsigned long io_cntl;
+        unsigned long config;
+};
+
+/* LCD Mode definition */
+struct w100_mode {
+        unsigned int xres;
+        unsigned int yres;
+        unsigned short left_margin;
+        unsigned short right_margin;
+        unsigned short upper_margin;
+        unsigned short lower_margin;
+        unsigned long crtc_ss;
+        unsigned long crtc_ls;
+        unsigned long crtc_gs;
+        unsigned long crtc_vpos_gs;
+        unsigned long crtc_rev;
+        unsigned long crtc_dclk;
+        unsigned long crtc_gclk;
+        unsigned long crtc_goe;
+        unsigned long crtc_ps1_active;
+        char pll_freq;
+        char fast_pll_freq;
+        int sysclk_src;
+        int sysclk_divider;
+        int pixclk_src;
+        int pixclk_divider;
+        int pixclk_divider_rotated;
+};
+
+struct w100_pll_info {
+        uint16_t freq;  /* desired Fout for PLL (Mhz) */
+        uint8_t M;      /* input divider */
+        uint8_t N_int;  /* VCO multiplier */
+        uint8_t N_fac;  /* VCO multiplier fractional part */
+        uint8_t tfgoal;
+        uint8_t lock_time;
+};
+
+/* Initial Video mode orientation flags */
+#define INIT_MODE_ROTATED  0x1
+#define INIT_MODE_FLIPPED  0x2
+
 /*
  * This structure describes the machine which we are running on.
  * It is set by machine specific code and used in the probe routine
  * of drivers/video/w100fb.c
  */
-
 struct w100fb_mach_info {
-        void (*w100fb_ssp_send)(u8 adrs, u8 data);
-        int comadj;
-        int phadadj;
+        /* General Platform Specific Registers */
+        struct w100_gen_regs *regs;
+        /* Table of modes the LCD is capable of */
+        struct w100_mode *modelist;
+        unsigned int num_modes;
+        /* Hooks for any platform specific tg/lcd code (optional) */
+        struct w100_tg_info *tg;
+        /* External memory definition (if present) */
+        struct w100_mem_info *mem;
+        /* Additional External memory definition (if present) */
+        struct w100_bm_mem_info *bm_mem;
+        /* GPIO definitions (optional) */
+        struct w100_gpio_regs *gpio;
+        /* Initial Mode flags */
+        unsigned int init_mode;
+        /* Xtal Frequency */
+        unsigned int xtal_freq;
+        /* Enable Xtal input doubler (1 == enable) */
+        unsigned int xtal_dbl;
+};
+
+/* General frame buffer data structure */
+struct w100fb_par {
+        unsigned int chip_id;
+        unsigned int xres;
+        unsigned int yres;
+        unsigned int extmem_active;
+        unsigned int flip;
+        unsigned int blanked;
+        unsigned int fastpll_mode;
+        unsigned long hsync_len;
+        struct w100_mode *mode;
+        struct w100_pll_info *pll_table;
+        struct w100fb_mach_info *mach;
+        uint32_t *saved_intmem;
+        uint32_t *saved_extmem;
 };