21 files changed, 2558 insertions, 2 deletions
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f427c60f..0ae6f5a75d2a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
 #define EXYNOS_SCLK_I2S 7
 #define EXYNOS_PCM_BUS          8
 #define EXYNOS_SCLK_PCM 9
+#define EXYNOS_ADMA             10
-#define EXYNOS_AUDSS_MAX_CLKS   10
+#define EXYNOS_AUDSS_MAX_CLKS   11
 #endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
new file mode 100644
index 000000000000..75aff336dfb0
--- /dev/null
+++ b/include/dt-bindings/clock/exynos4.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Haja <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos4 clock controller.
+*/
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
+/* core clocks */
+#define CLK_XXTI                1
+#define CLK_XUSBXTI             2
+#define CLK_FIN_PLL             3
+#define CLK_FOUT_APLL           4
+#define CLK_FOUT_MPLL           5
+#define CLK_FOUT_EPLL           6
+#define CLK_FOUT_VPLL           7
+#define CLK_SCLK_APLL           8
+#define CLK_SCLK_MPLL           9
+#define CLK_SCLK_EPLL           10
+#define CLK_SCLK_VPLL           11
+#define CLK_ARM_CLK             12
+#define CLK_ACLK200             13
+#define CLK_ACLK100             14
+#define CLK_ACLK160             15
+#define CLK_ACLK133             16
+#define CLK_MOUT_MPLL_USER_T    17 /* Exynos4x12 only */
+#define CLK_MOUT_MPLL_USER_C    18 /* Exynos4x12 only */
+#define CLK_MOUT_CORE           19
+#define CLK_MOUT_APLL           20
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_FIMC0          128
+#define CLK_SCLK_FIMC1          129
+#define CLK_SCLK_FIMC2          130
+#define CLK_SCLK_FIMC3          131
+#define CLK_SCLK_CAM0           132
+#define CLK_SCLK_CAM1           133
+#define CLK_SCLK_CSIS0          134
+#define CLK_SCLK_CSIS1          135
+#define CLK_SCLK_HDMI           136
+#define CLK_SCLK_MIXER          137
+#define CLK_SCLK_DAC            138
+#define CLK_SCLK_PIXEL          139
+#define CLK_SCLK_FIMD0          140
+#define CLK_SCLK_MDNIE0         141 /* Exynos4412 only */
+#define CLK_SCLK_MDNIE_PWM0     142
+#define CLK_SCLK_MIPI0          143
+#define CLK_SCLK_AUDIO0         144
+#define CLK_SCLK_MMC0           145
+#define CLK_SCLK_MMC1           146
+#define CLK_SCLK_MMC2           147
+#define CLK_SCLK_MMC3           148
+#define CLK_SCLK_MMC4           149
+#define CLK_SCLK_SATA           150 /* Exynos4210 only */
+#define CLK_SCLK_UART0          151
+#define CLK_SCLK_UART1          152
+#define CLK_SCLK_UART2          153
+#define CLK_SCLK_UART3          154
+#define CLK_SCLK_UART4          155
+#define CLK_SCLK_AUDIO1         156
+#define CLK_SCLK_AUDIO2         157
+#define CLK_SCLK_SPDIF          158
+#define CLK_SCLK_SPI0           159
+#define CLK_SCLK_SPI1           160
+#define CLK_SCLK_SPI2           161
+#define CLK_SCLK_SLIMBUS        162
+#define CLK_SCLK_FIMD1          163 /* Exynos4210 only */
+#define CLK_SCLK_MIPI1          164 /* Exynos4210 only */
+#define CLK_SCLK_PCM1           165
+#define CLK_SCLK_PCM2           166
+#define CLK_SCLK_I2S1           167
+#define CLK_SCLK_I2S2           168
+#define CLK_SCLK_MIPIHSI        169 /* Exynos4412 only */
+#define CLK_SCLK_MFC            170
+#define CLK_SCLK_PCM0           171
+#define CLK_SCLK_G3D            172
+#define CLK_SCLK_PWM_ISP        173 /* Exynos4x12 only */
+#define CLK_SCLK_SPI0_ISP       174 /* Exynos4x12 only */
+#define CLK_SCLK_SPI1_ISP       175 /* Exynos4x12 only */
+#define CLK_SCLK_UART_ISP       176 /* Exynos4x12 only */
+#define CLK_SCLK_FIMG2D         177
+/* gate clocks */
+#define CLK_FIMC0               256
+#define CLK_FIMC1               257
+#define CLK_FIMC2               258
+#define CLK_FIMC3               259
+#define CLK_CSIS0               260
+#define CLK_CSIS1               261
+#define CLK_JPEG                262
+#define CLK_SMMU_FIMC0          263
+#define CLK_SMMU_FIMC1          264
+#define CLK_SMMU_FIMC2          265
+#define CLK_SMMU_FIMC3          266
+#define CLK_SMMU_JPEG           267
+#define CLK_VP                  268
+#define CLK_MIXER               269
+#define CLK_TVENC               270 /* Exynos4210 only */
+#define CLK_HDMI                271
+#define CLK_SMMU_TV             272
+#define CLK_MFC                 273
+#define CLK_SMMU_MFCL           274
+#define CLK_SMMU_MFCR           275
+#define CLK_G3D                 276
+#define CLK_G2D                 277
+#define CLK_ROTATOR             278 /* Exynos4210 only */
+#define CLK_MDMA                279 /* Exynos4210 only */
+#define CLK_SMMU_G2D            280 /* Exynos4210 only */
+#define CLK_SMMU_ROTATOR        281 /* Exynos4210 only */
+#define CLK_SMMU_MDMA           282 /* Exynos4210 only */
+#define CLK_FIMD0               283
+#define CLK_MIE0                284
+#define CLK_MDNIE0              285 /* Exynos4412 only */
+#define CLK_DSIM0               286
+#define CLK_SMMU_FIMD0          287
+#define CLK_FIMD1               288 /* Exynos4210 only */
+#define CLK_MIE1                289 /* Exynos4210 only */
+#define CLK_DSIM1               290 /* Exynos4210 only */
+#define CLK_SMMU_FIMD1          291 /* Exynos4210 only */
+#define CLK_PDMA0               292
+#define CLK_PDMA1               293
+#define CLK_PCIE_PHY            294
+#define CLK_SATA_PHY            295 /* Exynos4210 only */
+#define CLK_TSI                 296
+#define CLK_SDMMC0              297
+#define CLK_SDMMC1              298
+#define CLK_SDMMC2              299
+#define CLK_SDMMC3              300
+#define CLK_SDMMC4              301
+#define CLK_SATA                302 /* Exynos4210 only */
+#define CLK_SROMC               303
+#define CLK_USB_HOST            304
+#define CLK_USB_DEVICE          305
+#define CLK_PCIE                306
+#define CLK_ONENAND             307
+#define CLK_NFCON               308
+#define CLK_SMMU_PCIE           309
+#define CLK_GPS                 310
+#define CLK_SMMU_GPS            311
+#define CLK_UART0               312
+#define CLK_UART1               313
+#define CLK_UART2               314
+#define CLK_UART3               315
+#define CLK_UART4               316
+#define CLK_I2C0                317
+#define CLK_I2C1                318
+#define CLK_I2C2                319
+#define CLK_I2C3                320
+#define CLK_I2C4                321
+#define CLK_I2C5                322
+#define CLK_I2C6                323
+#define CLK_I2C7                324
+#define CLK_I2C_HDMI            325
+#define CLK_TSADC               326
+#define CLK_SPI0                327
+#define CLK_SPI1                328
+#define CLK_SPI2                329
+#define CLK_I2S1                330
+#define CLK_I2S2                331
+#define CLK_PCM0                332
+#define CLK_I2S0                333
+#define CLK_PCM1                334
+#define CLK_PCM2                335
+#define CLK_PWM                 336
+#define CLK_SLIMBUS             337
+#define CLK_SPDIF               338
+#define CLK_AC97                339
+#define CLK_MODEMIF             340
+#define CLK_CHIPID              341
+#define CLK_SYSREG              342
+#define CLK_HDMI_CEC            343
+#define CLK_MCT                 344
+#define CLK_WDT                 345
+#define CLK_RTC                 346
+#define CLK_KEYIF               347
+#define CLK_AUDSS               348
+#define CLK_MIPI_HSI            349 /* Exynos4210 only */
+#define CLK_MDMA2               350 /* Exynos4210 only */
+#define CLK_PIXELASYNCM0        351
+#define CLK_PIXELASYNCM1        352
+#define CLK_FIMC_LITE0          353 /* Exynos4x12 only */
+#define CLK_FIMC_LITE1          354 /* Exynos4x12 only */
+#define CLK_PPMUISPX            355 /* Exynos4x12 only */
+#define CLK_PPMUISPMX           356 /* Exynos4x12 only */
+#define CLK_FIMC_ISP            357 /* Exynos4x12 only */
+#define CLK_FIMC_DRC            358 /* Exynos4x12 only */
+#define CLK_FIMC_FD             359 /* Exynos4x12 only */
+#define CLK_MCUISP              360 /* Exynos4x12 only */
+#define CLK_GICISP              361 /* Exynos4x12 only */
+#define CLK_SMMU_ISP            362 /* Exynos4x12 only */
+#define CLK_SMMU_DRC            363 /* Exynos4x12 only */
+#define CLK_SMMU_FD             364 /* Exynos4x12 only */
+#define CLK_SMMU_LITE0          365 /* Exynos4x12 only */
+#define CLK_SMMU_LITE1          366 /* Exynos4x12 only */
+#define CLK_MCUCTL_ISP          367 /* Exynos4x12 only */
+#define CLK_MPWM_ISP            368 /* Exynos4x12 only */
+#define CLK_I2C0_ISP            369 /* Exynos4x12 only */
+#define CLK_I2C1_ISP            370 /* Exynos4x12 only */
+#define CLK_MTCADC_ISP          371 /* Exynos4x12 only */
+#define CLK_PWM_ISP             372 /* Exynos4x12 only */
+#define CLK_WDT_ISP             373 /* Exynos4x12 only */
+#define CLK_UART_ISP            374 /* Exynos4x12 only */
+#define CLK_ASYNCAXIM           375 /* Exynos4x12 only */
+#define CLK_SMMU_ISPCX          376 /* Exynos4x12 only */
+#define CLK_SPI0_ISP            377 /* Exynos4x12 only */
+#define CLK_SPI1_ISP            378 /* Exynos4x12 only */
+#define CLK_PWM_ISP_SCLK        379 /* Exynos4x12 only */
+#define CLK_SPI0_ISP_SCLK       380 /* Exynos4x12 only */
+#define CLK_SPI1_ISP_SCLK       381 /* Exynos4x12 only */
+#define CLK_UART_ISP_SCLK       382 /* Exynos4x12 only */
+#define CLK_TMU_APBIF           383
+/* mux clocks */
+#define CLK_MOUT_FIMC0          384
+#define CLK_MOUT_FIMC1          385
+#define CLK_MOUT_FIMC2          386
+#define CLK_MOUT_FIMC3          387
+#define CLK_MOUT_CAM0           388
+#define CLK_MOUT_CAM1           389
+#define CLK_MOUT_CSIS0          390
+#define CLK_MOUT_CSIS1          391
+#define CLK_MOUT_G3D0           392
+#define CLK_MOUT_G3D1           393
+#define CLK_MOUT_G3D            394
+#define CLK_ACLK400_MCUISP      395 /* Exynos4x12 only */
+/* div clocks */
+#define CLK_DIV_ISP0            450 /* Exynos4x12 only */
+#define CLK_DIV_ISP1            451 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP0         452 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP1         453 /* Exynos4x12 only */
+#define CLK_DIV_ACLK200         454 /* Exynos4x12 only */
+#define CLK_DIV_ACLK400_MCUISP  455 /* Exynos4x12 only */
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS             456
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
new file mode 100644
index 000000000000..922f2dca9bf0
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Haja <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5250 clock controller.
+*/
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+/* core clocks */
+#define CLK_FIN_PLL             1
+#define CLK_FOUT_APLL           2
+#define CLK_FOUT_MPLL           3
+#define CLK_FOUT_BPLL           4
+#define CLK_FOUT_GPLL           5
+#define CLK_FOUT_CPLL           6
+#define CLK_FOUT_EPLL           7
+#define CLK_FOUT_VPLL           8
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_CAM_BAYER      128
+#define CLK_SCLK_CAM0           129
+#define CLK_SCLK_CAM1           130
+#define CLK_SCLK_GSCL_WA        131
+#define CLK_SCLK_GSCL_WB        132
+#define CLK_SCLK_FIMD1          133
+#define CLK_SCLK_MIPI1          134
+#define CLK_SCLK_DP             135
+#define CLK_SCLK_HDMI           136
+#define CLK_SCLK_PIXEL          137
+#define CLK_SCLK_AUDIO0         138
+#define CLK_SCLK_MMC0           139
+#define CLK_SCLK_MMC1           140
+#define CLK_SCLK_MMC2           141
+#define CLK_SCLK_MMC3           142
+#define CLK_SCLK_SATA           143
+#define CLK_SCLK_USB3           144
+#define CLK_SCLK_JPEG           145
+#define CLK_SCLK_UART0          146
+#define CLK_SCLK_UART1          147
+#define CLK_SCLK_UART2          148
+#define CLK_SCLK_UART3          149
+#define CLK_SCLK_PWM            150
+#define CLK_SCLK_AUDIO1         151
+#define CLK_SCLK_AUDIO2         152
+#define CLK_SCLK_SPDIF          153
+#define CLK_SCLK_SPI0           154
+#define CLK_SCLK_SPI1           155
+#define CLK_SCLK_SPI2           156
+#define CLK_DIV_I2S1            157
+#define CLK_DIV_I2S2            158
+#define CLK_SCLK_HDMIPHY        159
+#define CLK_DIV_PCM0            160
+/* gate clocks */
+#define CLK_GSCL0               256
+#define CLK_GSCL1               257
+#define CLK_GSCL2               258
+#define CLK_GSCL3               259
+#define CLK_GSCL_WA             260
+#define CLK_GSCL_WB             261
+#define CLK_SMMU_GSCL0          262
+#define CLK_SMMU_GSCL1          263
+#define CLK_SMMU_GSCL2          264
+#define CLK_SMMU_GSCL3          265
+#define CLK_MFC                 266
+#define CLK_SMMU_MFCL           267
+#define CLK_SMMU_MFCR           268
+#define CLK_ROTATOR             269
+#define CLK_JPEG                270
+#define CLK_MDMA1               271
+#define CLK_SMMU_ROTATOR        272
+#define CLK_SMMU_JPEG           273
+#define CLK_SMMU_MDMA1          274
+#define CLK_PDMA0               275
+#define CLK_PDMA1               276
+#define CLK_SATA                277
+#define CLK_USBOTG              278
+#define CLK_MIPI_HSI            279
+#define CLK_SDMMC0              280
+#define CLK_SDMMC1              281
+#define CLK_SDMMC2              282
+#define CLK_SDMMC3              283
+#define CLK_SROMC               284
+#define CLK_USB2                285
+#define CLK_USB3                286
+#define CLK_SATA_PHYCTRL        287
+#define CLK_SATA_PHYI2C         288
+#define CLK_UART0               289
+#define CLK_UART1               290
+#define CLK_UART2               291
+#define CLK_UART3               292
+#define CLK_UART4               293
+#define CLK_I2C0                294
+#define CLK_I2C1                295
+#define CLK_I2C2                296
+#define CLK_I2C3                297
+#define CLK_I2C4                298
+#define CLK_I2C5                299
+#define CLK_I2C6                300
+#define CLK_I2C7                301
+#define CLK_I2C_HDMI            302
+#define CLK_ADC                 303
+#define CLK_SPI0                304
+#define CLK_SPI1                305
+#define CLK_SPI2                306
+#define CLK_I2S1                307
+#define CLK_I2S2                308
+#define CLK_PCM1                309
+#define CLK_PCM2                310
+#define CLK_PWM                 311
+#define CLK_SPDIF               312
+#define CLK_AC97                313
+#define CLK_HSI2C0              314
+#define CLK_HSI2C1              315
+#define CLK_HSI2C2              316
+#define CLK_HSI2C3              317
+#define CLK_CHIPID              318
+#define CLK_SYSREG              319
+#define CLK_PMU                 320
+#define CLK_CMU_TOP             321
+#define CLK_CMU_CORE            322
+#define CLK_CMU_MEM             323
+#define CLK_TZPC0               324
+#define CLK_TZPC1               325
+#define CLK_TZPC2               326
+#define CLK_TZPC3               327
+#define CLK_TZPC4               328
+#define CLK_TZPC5               329
+#define CLK_TZPC6               330
+#define CLK_TZPC7               331
+#define CLK_TZPC8               332
+#define CLK_TZPC9               333
+#define CLK_HDMI_CEC            334
+#define CLK_MCT                 335
+#define CLK_WDT                 336
+#define CLK_RTC                 337
+#define CLK_TMU                 338
+#define CLK_FIMD1               339
+#define CLK_MIE1                340
+#define CLK_DSIM0               341
+#define CLK_DP                  342
+#define CLK_MIXER               343
+#define CLK_HDMI                344
+#define CLK_G2D                 345
+#define CLK_MDMA0               346
+#define CLK_SMMU_MDMA0          347
+/* mux clocks */
+#define CLK_MOUT_HDMI           1024
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS             1025
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
new file mode 100644
index 000000000000..5eefd8813f02
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Haja <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5420 clock controller.
+*/
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+/* core clocks */
+#define CLK_FIN_PLL             1
+#define CLK_FOUT_APLL           2
+#define CLK_FOUT_CPLL           3
+#define CLK_FOUT_DPLL           4
+#define CLK_FOUT_EPLL           5
+#define CLK_FOUT_RPLL           6
+#define CLK_FOUT_IPLL           7
+#define CLK_FOUT_SPLL           8
+#define CLK_FOUT_VPLL           9
+#define CLK_FOUT_MPLL           10
+#define CLK_FOUT_BPLL           11
+#define CLK_FOUT_KPLL           12
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0          128
+#define CLK_SCLK_UART1          129
+#define CLK_SCLK_UART2          130
+#define CLK_SCLK_UART3          131
+#define CLK_SCLK_MMC0           132
+#define CLK_SCLK_MMC1           133
+#define CLK_SCLK_MMC2           134
+#define CLK_SCLK_SPI0           135
+#define CLK_SCLK_SPI1           136
+#define CLK_SCLK_SPI2           137
+#define CLK_SCLK_I2S1           138
+#define CLK_SCLK_I2S2           139
+#define CLK_SCLK_PCM1           140
+#define CLK_SCLK_PCM2           141
+#define CLK_SCLK_SPDIF          142
+#define CLK_SCLK_HDMI           143
+#define CLK_SCLK_PIXEL          144
+#define CLK_SCLK_DP1            145
+#define CLK_SCLK_MIPI1          146
+#define CLK_SCLK_FIMD1          147
+#define CLK_SCLK_MAUDIO0        148
+#define CLK_SCLK_MAUPCM0        149
+#define CLK_SCLK_USBD300        150
+#define CLK_SCLK_USBD301        151
+#define CLK_SCLK_USBPHY300      152
+#define CLK_SCLK_USBPHY301      153
+#define CLK_SCLK_UNIPRO         154
+#define CLK_SCLK_PWM            155
+#define CLK_SCLK_GSCL_WA        156
+#define CLK_SCLK_GSCL_WB        157
+#define CLK_SCLK_HDMIPHY        158
+/* gate clocks */
+#define CLK_ACLK66_PERIC        256
+#define CLK_UART0               257
+#define CLK_UART1               258
+#define CLK_UART2               259
+#define CLK_UART3               260
+#define CLK_I2C0                261
+#define CLK_I2C1                262
+#define CLK_I2C2                263
+#define CLK_I2C3                264
+#define CLK_I2C4                265
+#define CLK_I2C5                266
+#define CLK_I2C6                267
+#define CLK_I2C7                268
+#define CLK_I2C_HDMI            269
+#define CLK_TSADC               270
+#define CLK_SPI0                271
+#define CLK_SPI1                272
+#define CLK_SPI2                273
+#define CLK_KEYIF               274
+#define CLK_I2S1                275
+#define CLK_I2S2                276
+#define CLK_PCM1                277
+#define CLK_PCM2                278
+#define CLK_PWM                 279
+#define CLK_SPDIF               280
+#define CLK_I2C8                281
+#define CLK_I2C9                282
+#define CLK_I2C10               283
+#define CLK_ACLK66_PSGEN        300
+#define CLK_CHIPID              301
+#define CLK_SYSREG              302
+#define CLK_TZPC0               303
+#define CLK_TZPC1               304
+#define CLK_TZPC2               305
+#define CLK_TZPC3               306
+#define CLK_TZPC4               307
+#define CLK_TZPC5               308
+#define CLK_TZPC6               309
+#define CLK_TZPC7               310
+#define CLK_TZPC8               311
+#define CLK_TZPC9               312
+#define CLK_HDMI_CEC            313
+#define CLK_SECKEY              314
+#define CLK_MCT                 315
+#define CLK_WDT                 316
+#define CLK_RTC                 317
+#define CLK_TMU                 318
+#define CLK_TMU_GPU             319
+#define CLK_PCLK66_GPIO         330
+#define CLK_ACLK200_FSYS2       350
+#define CLK_MMC0                351
+#define CLK_MMC1                352
+#define CLK_MMC2                353
+#define CLK_SROMC               354
+#define CLK_UFS                 355
+#define CLK_ACLK200_FSYS        360
+#define CLK_TSI                 361
+#define CLK_PDMA0               362
+#define CLK_PDMA1               363
+#define CLK_RTIC                364
+#define CLK_USBH20              365
+#define CLK_USBD300             366
+#define CLK_USBD301             367
+#define CLK_ACLK400_MSCL        380
+#define CLK_MSCL0               381
+#define CLK_MSCL1               382
+#define CLK_MSCL2               383
+#define CLK_SMMU_MSCL0          384
+#define CLK_SMMU_MSCL1          385
+#define CLK_SMMU_MSCL2          386
+#define CLK_ACLK333             400
+#define CLK_MFC                 401
+#define CLK_SMMU_MFCL           402
+#define CLK_SMMU_MFCR           403
+#define CLK_ACLK200_DISP1       410
+#define CLK_DSIM1               411
+#define CLK_DP1                 412
+#define CLK_HDMI                413
+#define CLK_ACLK300_DISP1       420
+#define CLK_FIMD1               421
+#define CLK_SMMU_FIMD1          422
+#define CLK_ACLK166             430
+#define CLK_MIXER               431
+#define CLK_ACLK266             440
+#define CLK_ROTATOR             441
+#define CLK_MDMA1               442
+#define CLK_SMMU_ROTATOR        443
+#define CLK_SMMU_MDMA1          444
+#define CLK_ACLK300_JPEG        450
+#define CLK_JPEG                451
+#define CLK_JPEG2               452
+#define CLK_SMMU_JPEG           453
+#define CLK_ACLK300_GSCL        460
+#define CLK_SMMU_GSCL0          461
+#define CLK_SMMU_GSCL1          462
+#define CLK_GSCL_WA             463
+#define CLK_GSCL_WB             464
+#define CLK_GSCL0               465
+#define CLK_GSCL1               466
+#define CLK_CLK_3AA             467
+#define CLK_ACLK266_G2D         470
+#define CLK_SSS                 471
+#define CLK_SLIM_SSS            472
+#define CLK_MDMA0               473
+#define CLK_ACLK333_G2D         480
+#define CLK_G2D                 481
+#define CLK_ACLK333_432_GSCL    490
+#define CLK_SMMU_3AA            491
+#define CLK_SMMU_FIMCL0         492
+#define CLK_SMMU_FIMCL1         493
+#define CLK_SMMU_FIMCL3         494
+#define CLK_FIMC_LITE3          495
+#define CLK_ACLK_G3D            500
+#define CLK_G3D                 501
+#define CLK_SMMU_MIXER          502
+/* mux clocks */
+#define CLK_MOUT_HDMI           640
+/* divider clocks */
+#define CLK_DOUT_PIXEL          768
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS             769
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h
new file mode 100644
index 000000000000..70cd85077fa9
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5440.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5440 clock controller.
+*/
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
+#define CLK_XTAL                1
+#define CLK_ARM_CLK             2
+#define CLK_SPI_BAUD            16
+#define CLK_PB0_250             17
+#define CLK_PR0_250             18
+#define CLK_PR1_250             19
+#define CLK_B_250               20
+#define CLK_B_125               21
+#define CLK_B_200               22
+#define CLK_SATA                23
+#define CLK_USB                 24
+#define CLK_GMAC0               25
+#define CLK_CS250               26
+#define CLK_PB0_250_O           27
+#define CLK_PR0_250_O           28
+#define CLK_PR1_250_O           29
+#define CLK_B_250_O             30
+#define CLK_B_125_O             31
+#define CLK_B_200_O             32
+#define CLK_SATA_O              33
+#define CLK_USB_O               34
+#define CLK_GMAC0_O             35
+#define CLK_CS250_O             36
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS             37
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
diff --git a/include/dt-bindings/clock/hi3620-clock.h b/include/dt-bindings/clock/hi3620-clock.h
new file mode 100644
index 000000000000..6eaa6a45e110
--- /dev/null
+++ b/include/dt-bindings/clock/hi3620-clock.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *         Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef __DTS_HI3620_CLOCK_H
+#define __DTS_HI3620_CLOCK_H
+#define HI3620_NONE_CLOCK       0
+/* fixed rate & fixed factor clocks */
+#define HI3620_OSC32K           1
+#define HI3620_OSC26M           2
+#define HI3620_PCLK             3
+#define HI3620_PLL_ARM0         4
+#define HI3620_PLL_ARM1         5
+#define HI3620_PLL_PERI         6
+#define HI3620_PLL_USB          7
+#define HI3620_PLL_HDMI         8
+#define HI3620_PLL_GPU          9
+#define HI3620_RCLK_TCXO        10
+#define HI3620_RCLK_CFGAXI      11
+#define HI3620_RCLK_PICO        12
+/* mux clocks */
+#define HI3620_TIMER0_MUX       32
+#define HI3620_TIMER1_MUX       33
+#define HI3620_TIMER2_MUX       34
+#define HI3620_TIMER3_MUX       35
+#define HI3620_TIMER4_MUX       36
+#define HI3620_TIMER5_MUX       37
+#define HI3620_TIMER6_MUX       38
+#define HI3620_TIMER7_MUX       39
+#define HI3620_TIMER8_MUX       40
+#define HI3620_TIMER9_MUX       41
+#define HI3620_UART0_MUX        42
+#define HI3620_UART1_MUX        43
+#define HI3620_UART2_MUX        44
+#define HI3620_UART3_MUX        45
+#define HI3620_UART4_MUX        46
+#define HI3620_SPI0_MUX         47
+#define HI3620_SPI1_MUX         48
+#define HI3620_SPI2_MUX         49
+#define HI3620_SAXI_MUX         50
+#define HI3620_PWM0_MUX         51
+#define HI3620_PWM1_MUX         52
+#define HI3620_SD_MUX           53
+#define HI3620_MMC1_MUX         54
+#define HI3620_MMC1_MUX2        55
+#define HI3620_G2D_MUX          56
+#define HI3620_VENC_MUX         57
+#define HI3620_VDEC_MUX         58
+#define HI3620_VPP_MUX          59
+#define HI3620_EDC0_MUX         60
+#define HI3620_LDI0_MUX         61
+#define HI3620_EDC1_MUX         62
+#define HI3620_LDI1_MUX         63
+#define HI3620_RCLK_HSIC        64
+#define HI3620_MMC2_MUX         65
+#define HI3620_MMC3_MUX         66
+/* divider clocks */
+#define HI3620_SHAREAXI_DIV     128
+#define HI3620_CFGAXI_DIV       129
+#define HI3620_SD_DIV           130
+#define HI3620_MMC1_DIV         131
+#define HI3620_HSIC_DIV         132
+#define HI3620_MMC2_DIV         133
+#define HI3620_MMC3_DIV         134
+/* gate clocks */
+#define HI3620_TIMERCLK01       160
+#define HI3620_TIMER_RCLK01     161
+#define HI3620_TIMERCLK23       162
+#define HI3620_TIMER_RCLK23     163
+#define HI3620_TIMERCLK45       164
+#define HI3620_TIMERCLK67       165
+#define HI3620_TIMERCLK89       166
+#define HI3620_RTCCLK           167
+#define HI3620_KPC_CLK          168
+#define HI3620_GPIOCLK0         169
+#define HI3620_GPIOCLK1         170
+#define HI3620_GPIOCLK2         171
+#define HI3620_GPIOCLK3         172
+#define HI3620_GPIOCLK4         173
+#define HI3620_GPIOCLK5         174
+#define HI3620_GPIOCLK6         175
+#define HI3620_GPIOCLK7         176
+#define HI3620_GPIOCLK8         177
+#define HI3620_GPIOCLK9         178
+#define HI3620_GPIOCLK10        179
+#define HI3620_GPIOCLK11        180
+#define HI3620_GPIOCLK12        181
+#define HI3620_GPIOCLK13        182
+#define HI3620_GPIOCLK14        183
+#define HI3620_GPIOCLK15        184
+#define HI3620_GPIOCLK16        185
+#define HI3620_GPIOCLK17        186
+#define HI3620_GPIOCLK18        187
+#define HI3620_GPIOCLK19        188
+#define HI3620_GPIOCLK20        189
+#define HI3620_GPIOCLK21        190
+#define HI3620_DPHY0_CLK        191
+#define HI3620_DPHY1_CLK        192
+#define HI3620_DPHY2_CLK        193
+#define HI3620_USBPHY_CLK       194
+#define HI3620_ACP_CLK          195
+#define HI3620_PWMCLK0          196
+#define HI3620_PWMCLK1          197
+#define HI3620_UARTCLK0         198
+#define HI3620_UARTCLK1         199
+#define HI3620_UARTCLK2         200
+#define HI3620_UARTCLK3         201
+#define HI3620_UARTCLK4         202
+#define HI3620_SPICLK0          203
+#define HI3620_SPICLK1          204
+#define HI3620_SPICLK2          205
+#define HI3620_I2CCLK0          206
+#define HI3620_I2CCLK1          207
+#define HI3620_I2CCLK2          208
+#define HI3620_I2CCLK3          209
+#define HI3620_SCI_CLK          210
+#define HI3620_DDRC_PER_CLK     211
+#define HI3620_DMAC_CLK         212
+#define HI3620_USB2DVC_CLK      213
+#define HI3620_SD_CLK           214
+#define HI3620_MMC_CLK1         215
+#define HI3620_MMC_CLK2         216
+#define HI3620_MMC_CLK3         217
+#define HI3620_MCU_CLK          218
+#define HI3620_NR_CLKS          219
+#endif  /* __DTS_HI3620_CLOCK_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8660.h b/include/dt-bindings/clock/qcom,gcc-msm8660.h
new file mode 100644
index 000000000000..67665f6813dd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8660.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8660_H
+#define AFAB_CLK_SRC                            0
+#define AFAB_CORE_CLK                           1
+#define SCSS_A_CLK                              2
+#define SCSS_H_CLK                              3
+#define SCSS_XO_SRC_CLK                         4
+#define AFAB_EBI1_CH0_A_CLK                     5
+#define AFAB_EBI1_CH1_A_CLK                     6
+#define AFAB_AXI_S0_FCLK                        7
+#define AFAB_AXI_S1_FCLK                        8
+#define AFAB_AXI_S2_FCLK                        9
+#define AFAB_AXI_S3_FCLK                        10
+#define AFAB_AXI_S4_FCLK                        11
+#define SFAB_CORE_CLK                           12
+#define SFAB_AXI_S0_FCLK                        13
+#define SFAB_AXI_S1_FCLK                        14
+#define SFAB_AXI_S2_FCLK                        15
+#define SFAB_AXI_S3_FCLK                        16
+#define SFAB_AXI_S4_FCLK                        17
+#define SFAB_AHB_S0_FCLK                        18
+#define SFAB_AHB_S1_FCLK                        19
+#define SFAB_AHB_S2_FCLK                        20
+#define SFAB_AHB_S3_FCLK                        21
+#define SFAB_AHB_S4_FCLK                        22
+#define SFAB_AHB_S5_FCLK                        23
+#define SFAB_AHB_S6_FCLK                        24
+#define SFAB_ADM0_M0_A_CLK                      25
+#define SFAB_ADM0_M1_A_CLK                      26
+#define SFAB_ADM0_M2_A_CLK                      27
+#define ADM0_CLK                                28
+#define ADM0_PBUS_CLK                           29
+#define SFAB_ADM1_M0_A_CLK                      30
+#define SFAB_ADM1_M1_A_CLK                      31
+#define SFAB_ADM1_M2_A_CLK                      32
+#define MMFAB_ADM1_M3_A_CLK                     33
+#define ADM1_CLK                                34
+#define ADM1_PBUS_CLK                           35
+#define IMEM0_A_CLK                             36
+#define MAHB0_CLK                               37
+#define SFAB_LPASS_Q6_A_CLK                     38
+#define SFAB_AFAB_M_A_CLK                       39
+#define AFAB_SFAB_M0_A_CLK                      40
+#define AFAB_SFAB_M1_A_CLK                      41
+#define DFAB_CLK_SRC                            42
+#define DFAB_CLK                                43
+#define DFAB_CORE_CLK                           44
+#define SFAB_DFAB_M_A_CLK                       45
+#define DFAB_SFAB_M_A_CLK                       46
+#define DFAB_SWAY0_H_CLK                        47
+#define DFAB_SWAY1_H_CLK                        48
+#define DFAB_ARB0_H_CLK                         49
+#define DFAB_ARB1_H_CLK                         50
+#define PPSS_H_CLK                              51
+#define PPSS_PROC_CLK                           52
+#define PPSS_TIMER0_CLK                         53
+#define PPSS_TIMER1_CLK                         54
+#define PMEM_A_CLK                              55
+#define DMA_BAM_H_CLK                           56
+#define SIC_H_CLK                               57
+#define SPS_TIC_H_CLK                           58
+#define SLIMBUS_H_CLK                           59
+#define SLIMBUS_XO_SRC_CLK                      60
+#define CFPB_2X_CLK_SRC                         61
+#define CFPB_CLK                                62
+#define CFPB0_H_CLK                             63
+#define CFPB1_H_CLK                             64
+#define CFPB2_H_CLK                             65
+#define EBI2_2X_CLK                             66
+#define EBI2_CLK                                67
+#define SFAB_CFPB_M_H_CLK                       68
+#define CFPB_MASTER_H_CLK                       69
+#define SFAB_CFPB_S_HCLK                        70
+#define CFPB_SPLITTER_H_CLK                     71
+#define TSIF_H_CLK                              72
+#define TSIF_INACTIVITY_TIMERS_CLK              73
+#define TSIF_REF_SRC                            74
+#define TSIF_REF_CLK                            75
+#define CE1_H_CLK                               76
+#define CE2_H_CLK                               77
+#define SFPB_H_CLK_SRC                          78
+#define SFPB_H_CLK                              79
+#define SFAB_SFPB_M_H_CLK                       80
+#define SFAB_SFPB_S_H_CLK                       81
+#define RPM_PROC_CLK                            82
+#define RPM_BUS_H_CLK                           83
+#define RPM_SLEEP_CLK                           84
+#define RPM_TIMER_CLK                           85
+#define MODEM_AHB1_H_CLK                        86
+#define MODEM_AHB2_H_CLK                        87
+#define RPM_MSG_RAM_H_CLK                       88
+#define SC_H_CLK                                89
+#define SC_A_CLK                                90
+#define PMIC_ARB0_H_CLK                         91
+#define PMIC_ARB1_H_CLK                         92
+#define PMIC_SSBI2_SRC                          93
+#define PMIC_SSBI2_CLK                          94
+#define SDC1_H_CLK                              95
+#define SDC2_H_CLK                              96
+#define SDC3_H_CLK                              97
+#define SDC4_H_CLK                              98
+#define SDC5_H_CLK                              99
+#define SDC1_SRC                                100
+#define SDC2_SRC                                101
+#define SDC3_SRC                                102
+#define SDC4_SRC                                103
+#define SDC5_SRC                                104
+#define SDC1_CLK                                105
+#define SDC2_CLK                                106
+#define SDC3_CLK                                107
+#define SDC4_CLK                                108
+#define SDC5_CLK                                109
+#define USB_HS1_H_CLK                           110
+#define USB_HS1_XCVR_SRC                        111
+#define USB_HS1_XCVR_CLK                        112
+#define USB_HS2_H_CLK                           113
+#define USB_HS2_XCVR_SRC                        114
+#define USB_HS2_XCVR_CLK                        115
+#define USB_FS1_H_CLK                           116
+#define USB_FS1_XCVR_FS_SRC                     117
+#define USB_FS1_XCVR_FS_CLK                     118
+#define USB_FS1_SYSTEM_CLK                      119
+#define USB_FS2_H_CLK                           120
+#define USB_FS2_XCVR_FS_SRC                     121
+#define USB_FS2_XCVR_FS_CLK                     122
+#define USB_FS2_SYSTEM_CLK                      123
+#define GSBI_COMMON_SIM_SRC                     124
+#define GSBI1_H_CLK                             125
+#define GSBI2_H_CLK                             126
+#define GSBI3_H_CLK                             127
+#define GSBI4_H_CLK                             128
+#define GSBI5_H_CLK                             129
+#define GSBI6_H_CLK                             130
+#define GSBI7_H_CLK                             131
+#define GSBI8_H_CLK                             132
+#define GSBI9_H_CLK                             133
+#define GSBI10_H_CLK                            134
+#define GSBI11_H_CLK                            135
+#define GSBI12_H_CLK                            136
+#define GSBI1_UART_SRC                          137
+#define GSBI1_UART_CLK                          138
+#define GSBI2_UART_SRC                          139
+#define GSBI2_UART_CLK                          140
+#define GSBI3_UART_SRC                          141
+#define GSBI3_UART_CLK                          142
+#define GSBI4_UART_SRC                          143
+#define GSBI4_UART_CLK                          144
+#define GSBI5_UART_SRC                          145
+#define GSBI5_UART_CLK                          146
+#define GSBI6_UART_SRC                          147
+#define GSBI6_UART_CLK                          148
+#define GSBI7_UART_SRC                          149
+#define GSBI7_UART_CLK                          150
+#define GSBI8_UART_SRC                          151
+#define GSBI8_UART_CLK                          152
+#define GSBI9_UART_SRC                          153
+#define GSBI9_UART_CLK                          154
+#define GSBI10_UART_SRC                         155
+#define GSBI10_UART_CLK                         156
+#define GSBI11_UART_SRC                         157
+#define GSBI11_UART_CLK                         158
+#define GSBI12_UART_SRC                         159
+#define GSBI12_UART_CLK                         160
+#define GSBI1_QUP_SRC                           161
+#define GSBI1_QUP_CLK                           162
+#define GSBI2_QUP_SRC                           163
+#define GSBI2_QUP_CLK                           164
+#define GSBI3_QUP_SRC                           165
+#define GSBI3_QUP_CLK                           166
+#define GSBI4_QUP_SRC                           167
+#define GSBI4_QUP_CLK                           168
+#define GSBI5_QUP_SRC                           169
+#define GSBI5_QUP_CLK                           170
+#define GSBI6_QUP_SRC                           171
+#define GSBI6_QUP_CLK                           172
+#define GSBI7_QUP_SRC                           173
+#define GSBI7_QUP_CLK                           174
+#define GSBI8_QUP_SRC                           175
+#define GSBI8_QUP_CLK                           176
+#define GSBI9_QUP_SRC                           177
+#define GSBI9_QUP_CLK                           178
+#define GSBI10_QUP_SRC                          179
+#define GSBI10_QUP_CLK                          180
+#define GSBI11_QUP_SRC                          181
+#define GSBI11_QUP_CLK                          182
+#define GSBI12_QUP_SRC                          183
+#define GSBI12_QUP_CLK                          184
+#define GSBI1_SIM_CLK                           185
+#define GSBI2_SIM_CLK                           186
+#define GSBI3_SIM_CLK                           187
+#define GSBI4_SIM_CLK                           188
+#define GSBI5_SIM_CLK                           189
+#define GSBI6_SIM_CLK                           190
+#define GSBI7_SIM_CLK                           191
+#define GSBI8_SIM_CLK                           192
+#define GSBI9_SIM_CLK                           193
+#define GSBI10_SIM_CLK                          194
+#define GSBI11_SIM_CLK                          195
+#define GSBI12_SIM_CLK                          196
+#define SPDM_CFG_H_CLK                          197
+#define SPDM_MSTR_H_CLK                         198
+#define SPDM_FF_CLK_SRC                         199
+#define SPDM_FF_CLK                             200
+#define SEC_CTRL_CLK                            201
+#define SEC_CTRL_ACC_CLK_SRC                    202
+#define SEC_CTRL_ACC_CLK                        203
+#define TLMM_H_CLK                              204
+#define TLMM_CLK                                205
+#define MARM_CLK_SRC                            206
+#define MARM_CLK                                207
+#define MAHB1_SRC                               208
+#define MAHB1_CLK                               209
+#define SFAB_MSS_S_H_CLK                        210
+#define MAHB2_SRC                               211
+#define MAHB2_CLK                               212
+#define MSS_MODEM_CLK_SRC                       213
+#define MSS_MODEM_CXO_CLK                       214
+#define MSS_SLP_CLK                             215
+#define MSS_SYS_REF_CLK                         216
+#define TSSC_CLK_SRC                            217
+#define TSSC_CLK                                218
+#define PDM_SRC                                 219
+#define PDM_CLK                                 220
+#define GP0_SRC                                 221
+#define GP0_CLK                                 222
+#define GP1_SRC                                 223
+#define GP1_CLK                                 224
+#define GP2_SRC                                 225
+#define GP2_CLK                                 226
+#define PMEM_CLK                                227
+#define MPM_CLK                                 228
+#define EBI1_ASFAB_SRC                          229
+#define EBI1_CLK_SRC                            230
+#define EBI1_CH0_CLK                            231
+#define EBI1_CH1_CLK                            232
+#define SFAB_SMPSS_S_H_CLK                      233
+#define PRNG_SRC                                234
+#define PRNG_CLK                                235
+#define PXO_SRC                                 236
+#define LPASS_CXO_CLK                           237
+#define LPASS_PXO_CLK                           238
+#define SPDM_CY_PORT0_CLK                       239
+#define SPDM_CY_PORT1_CLK                       240
+#define SPDM_CY_PORT2_CLK                       241
+#define SPDM_CY_PORT3_CLK                       242
+#define SPDM_CY_PORT4_CLK                       243
+#define SPDM_CY_PORT5_CLK                       244
+#define SPDM_CY_PORT6_CLK                       245
+#define SPDM_CY_PORT7_CLK                       246
+#define PLL0                                    247
+#define PLL0_VOTE                               248
+#define PLL5                                    249
+#define PLL6                                    250
+#define PLL6_VOTE                               251
+#define PLL8                                    252
+#define PLL8_VOTE                               253
+#define PLL9                                    254
+#define PLL10                                   255
+#define PLL11                                   256
+#define PLL12                                   257
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
new file mode 100644
index 000000000000..03bbf49d43b7
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8960_H
+#define AFAB_CLK_SRC                            0
+#define AFAB_CORE_CLK                           1
+#define SFAB_MSS_Q6_SW_A_CLK                    2
+#define SFAB_MSS_Q6_FW_A_CLK                    3
+#define QDSS_STM_CLK                            4
+#define SCSS_A_CLK                              5
+#define SCSS_H_CLK                              6
+#define SCSS_XO_SRC_CLK                         7
+#define AFAB_EBI1_CH0_A_CLK                     8
+#define AFAB_EBI1_CH1_A_CLK                     9
+#define AFAB_AXI_S0_FCLK                        10
+#define AFAB_AXI_S1_FCLK                        11
+#define AFAB_AXI_S2_FCLK                        12
+#define AFAB_AXI_S3_FCLK                        13
+#define AFAB_AXI_S4_FCLK                        14
+#define SFAB_CORE_CLK                           15
+#define SFAB_AXI_S0_FCLK                        16
+#define SFAB_AXI_S1_FCLK                        17
+#define SFAB_AXI_S2_FCLK                        18
+#define SFAB_AXI_S3_FCLK                        19
+#define SFAB_AXI_S4_FCLK                        20
+#define SFAB_AHB_S0_FCLK                        21
+#define SFAB_AHB_S1_FCLK                        22
+#define SFAB_AHB_S2_FCLK                        23
+#define SFAB_AHB_S3_FCLK                        24
+#define SFAB_AHB_S4_FCLK                        25
+#define SFAB_AHB_S5_FCLK                        26
+#define SFAB_AHB_S6_FCLK                        27
+#define SFAB_AHB_S7_FCLK                        28
+#define QDSS_AT_CLK_SRC                         29
+#define QDSS_AT_CLK                             30
+#define QDSS_TRACECLKIN_CLK_SRC                 31
+#define QDSS_TRACECLKIN_CLK                     32
+#define QDSS_TSCTR_CLK_SRC                      33
+#define QDSS_TSCTR_CLK                          34
+#define SFAB_ADM0_M0_A_CLK                      35
+#define SFAB_ADM0_M1_A_CLK                      36
+#define SFAB_ADM0_M2_A_CLK                      37
+#define ADM0_CLK                                38
+#define ADM0_PBUS_CLK                           39
+#define MSS_XPU_CLK                             40
+#define IMEM0_A_CLK                             41
+#define QDSS_H_CLK                              42
+#define PCIE_A_CLK                              43
+#define PCIE_AUX_CLK                            44
+#define PCIE_PHY_REF_CLK                        45
+#define PCIE_H_CLK                              46
+#define SFAB_CLK_SRC                            47
+#define MAHB0_CLK                               48
+#define Q6SW_CLK_SRC                            49
+#define Q6SW_CLK                                50
+#define Q6FW_CLK_SRC                            51
+#define Q6FW_CLK                                52
+#define SFAB_MSS_M_A_CLK                        53
+#define SFAB_USB3_M_A_CLK                       54
+#define SFAB_LPASS_Q6_A_CLK                     55
+#define SFAB_AFAB_M_A_CLK                       56
+#define AFAB_SFAB_M0_A_CLK                      57
+#define AFAB_SFAB_M1_A_CLK                      58
+#define SFAB_SATA_S_H_CLK                       59
+#define DFAB_CLK_SRC                            60
+#define DFAB_CLK                                61
+#define SFAB_DFAB_M_A_CLK                       62
+#define DFAB_SFAB_M_A_CLK                       63
+#define DFAB_SWAY0_H_CLK                        64
+#define DFAB_SWAY1_H_CLK                        65
+#define DFAB_ARB0_H_CLK                         66
+#define DFAB_ARB1_H_CLK                         67
+#define PPSS_H_CLK                              68
+#define PPSS_PROC_CLK                           69
+#define PPSS_TIMER0_CLK                         70
+#define PPSS_TIMER1_CLK                         71
+#define PMEM_A_CLK                              72
+#define DMA_BAM_H_CLK                           73
+#define SIC_H_CLK                               74
+#define SPS_TIC_H_CLK                           75
+#define SLIMBUS_H_CLK                           76
+#define SLIMBUS_XO_SRC_CLK                      77
+#define CFPB_2X_CLK_SRC                         78
+#define CFPB_CLK                                79
+#define CFPB0_H_CLK                             80
+#define CFPB1_H_CLK                             81
+#define CFPB2_H_CLK                             82
+#define SFAB_CFPB_M_H_CLK                       83
+#define CFPB_MASTER_H_CLK                       84
+#define SFAB_CFPB_S_HCLK                        85
+#define CFPB_SPLITTER_H_CLK                     86
+#define TSIF_H_CLK                              87
+#define TSIF_INACTIVITY_TIMERS_CLK              88
+#define TSIF_REF_SRC                            89
+#define TSIF_REF_CLK                            90
+#define CE1_H_CLK                               91
+#define CE1_CORE_CLK                            92
+#define CE1_SLEEP_CLK                           93
+#define CE2_H_CLK                               94
+#define CE2_CORE_CLK                            95
+#define CE2_SLEEP_CLK                           96
+#define SFPB_H_CLK_SRC                          97
+#define SFPB_H_CLK                              98
+#define SFAB_SFPB_M_H_CLK                       99
+#define SFAB_SFPB_S_H_CLK                       100
+#define RPM_PROC_CLK                            101
+#define RPM_BUS_H_CLK                           102
+#define RPM_SLEEP_CLK                           103
+#define RPM_TIMER_CLK                           104
+#define RPM_MSG_RAM_H_CLK                       105
+#define PMIC_ARB0_H_CLK                         106
+#define PMIC_ARB1_H_CLK                         107
+#define PMIC_SSBI2_SRC                          108
+#define PMIC_SSBI2_CLK                          109
+#define SDC1_H_CLK                              110
+#define SDC2_H_CLK                              111
+#define SDC3_H_CLK                              112
+#define SDC4_H_CLK                              113
+#define SDC5_H_CLK                              114
+#define SDC1_SRC                                115
+#define SDC2_SRC                                116
+#define SDC3_SRC                                117
+#define SDC4_SRC                                118
+#define SDC5_SRC                                119
+#define SDC1_CLK                                120
+#define SDC2_CLK                                121
+#define SDC3_CLK                                122
+#define SDC4_CLK                                123
+#define SDC5_CLK                                124
+#define DFAB_A2_H_CLK                           125
+#define USB_HS1_H_CLK                           126
+#define USB_HS1_XCVR_SRC                        127
+#define USB_HS1_XCVR_CLK                        128
+#define USB_HSIC_H_CLK                          129
+#define USB_HSIC_XCVR_FS_SRC                    130
+#define USB_HSIC_XCVR_FS_CLK                    131
+#define USB_HSIC_SYSTEM_CLK_SRC                 132
+#define USB_HSIC_SYSTEM_CLK                     133
+#define CFPB0_C0_H_CLK                          134
+#define CFPB0_C1_H_CLK                          135
+#define CFPB0_D0_H_CLK                          136
+#define CFPB0_D1_H_CLK                          137
+#define USB_FS1_H_CLK                           138
+#define USB_FS1_XCVR_FS_SRC                     139
+#define USB_FS1_XCVR_FS_CLK                     140
+#define USB_FS1_SYSTEM_CLK                      141
+#define USB_FS2_H_CLK                           142
+#define USB_FS2_XCVR_FS_SRC                     143
+#define USB_FS2_XCVR_FS_CLK                     144
+#define USB_FS2_SYSTEM_CLK                      145
+#define GSBI_COMMON_SIM_SRC                     146
+#define GSBI1_H_CLK                             147
+#define GSBI2_H_CLK                             148
+#define GSBI3_H_CLK                             149
+#define GSBI4_H_CLK                             150
+#define GSBI5_H_CLK                             151
+#define GSBI6_H_CLK                             152
+#define GSBI7_H_CLK                             153
+#define GSBI8_H_CLK                             154
+#define GSBI9_H_CLK                             155
+#define GSBI10_H_CLK                            156
+#define GSBI11_H_CLK                            157
+#define GSBI12_H_CLK                            158
+#define GSBI1_UART_SRC                          159
+#define GSBI1_UART_CLK                          160
+#define GSBI2_UART_SRC                          161
+#define GSBI2_UART_CLK                          162
+#define GSBI3_UART_SRC                          163
+#define GSBI3_UART_CLK                          164
+#define GSBI4_UART_SRC                          165
+#define GSBI4_UART_CLK                          166
+#define GSBI5_UART_SRC                          167
+#define GSBI5_UART_CLK                          168
+#define GSBI6_UART_SRC                          169
+#define GSBI6_UART_CLK                          170
+#define GSBI7_UART_SRC                          171
+#define GSBI7_UART_CLK                          172
+#define GSBI8_UART_SRC                          173
+#define GSBI8_UART_CLK                          174
+#define GSBI9_UART_SRC                          175
+#define GSBI9_UART_CLK                          176
+#define GSBI10_UART_SRC                         177
+#define GSBI10_UART_CLK                         178
+#define GSBI11_UART_SRC                         179
+#define GSBI11_UART_CLK                         180
+#define GSBI12_UART_SRC                         181
+#define GSBI12_UART_CLK                         182
+#define GSBI1_QUP_SRC                           183
+#define GSBI1_QUP_CLK                           184
+#define GSBI2_QUP_SRC                           185
+#define GSBI2_QUP_CLK                           186
+#define GSBI3_QUP_SRC                           187
+#define GSBI3_QUP_CLK                           188
+#define GSBI4_QUP_SRC                           189
+#define GSBI4_QUP_CLK                           190
+#define GSBI5_QUP_SRC                           191
+#define GSBI5_QUP_CLK                           192
+#define GSBI6_QUP_SRC                           193
+#define GSBI6_QUP_CLK                           194
+#define GSBI7_QUP_SRC                           195
+#define GSBI7_QUP_CLK                           196
+#define GSBI8_QUP_SRC                           197
+#define GSBI8_QUP_CLK                           198
+#define GSBI9_QUP_SRC                           199
+#define GSBI9_QUP_CLK                           200
+#define GSBI10_QUP_SRC                          201
+#define GSBI10_QUP_CLK                          202
+#define GSBI11_QUP_SRC                          203
+#define GSBI11_QUP_CLK                          204
+#define GSBI12_QUP_SRC                          205
+#define GSBI12_QUP_CLK                          206
+#define GSBI1_SIM_CLK                           207
+#define GSBI2_SIM_CLK                           208
+#define GSBI3_SIM_CLK                           209
+#define GSBI4_SIM_CLK                           210
+#define GSBI5_SIM_CLK                           211
+#define GSBI6_SIM_CLK                           212
+#define GSBI7_SIM_CLK                           213
+#define GSBI8_SIM_CLK                           214
+#define GSBI9_SIM_CLK                           215
+#define GSBI10_SIM_CLK                          216
+#define GSBI11_SIM_CLK                          217
+#define GSBI12_SIM_CLK                          218
+#define USB_HSIC_HSIC_CLK_SRC                   219
+#define USB_HSIC_HSIC_CLK                       220
+#define USB_HSIC_HSIO_CAL_CLK                   221
+#define SPDM_CFG_H_CLK                          222
+#define SPDM_MSTR_H_CLK                         223
+#define SPDM_FF_CLK_SRC                         224
+#define SPDM_FF_CLK                             225
+#define SEC_CTRL_CLK                            226
+#define SEC_CTRL_ACC_CLK_SRC                    227
+#define SEC_CTRL_ACC_CLK                        228
+#define TLMM_H_CLK                              229
+#define TLMM_CLK                                230
+#define SFAB_MSS_S_H_CLK                        231
+#define MSS_SLP_CLK                             232
+#define MSS_Q6SW_JTAG_CLK                       233
+#define MSS_Q6FW_JTAG_CLK                       234
+#define MSS_S_H_CLK                             235
+#define MSS_CXO_SRC_CLK                         236
+#define SATA_H_CLK                              237
+#define SATA_SRC_CLK                            238
+#define SATA_RXOOB_CLK                          239
+#define SATA_PMALIVE_CLK                        240
+#define SATA_PHY_REF_CLK                        241
+#define TSSC_CLK_SRC                            242
+#define TSSC_CLK                                243
+#define PDM_SRC                                 244
+#define PDM_CLK                                 245
+#define GP0_SRC                                 246
+#define GP0_CLK                                 247
+#define GP1_SRC                                 248
+#define GP1_CLK                                 249
+#define GP2_SRC                                 250
+#define GP2_CLK                                 251
+#define MPM_CLK                                 252
+#define EBI1_CLK_SRC                            253
+#define EBI1_CH0_CLK                            254
+#define EBI1_CH1_CLK                            255
+#define EBI1_2X_CLK                             256
+#define EBI1_CH0_DQ_CLK                         257
+#define EBI1_CH1_DQ_CLK                         258
+#define EBI1_CH0_CA_CLK                         259
+#define EBI1_CH1_CA_CLK                         260
+#define EBI1_XO_CLK                             261
+#define SFAB_SMPSS_S_H_CLK                      262
+#define PRNG_SRC                                263
+#define PRNG_CLK                                264
+#define PXO_SRC                                 265
+#define LPASS_CXO_CLK                           266
+#define LPASS_PXO_CLK                           267
+#define SPDM_CY_PORT0_CLK                       268
+#define SPDM_CY_PORT1_CLK                       269
+#define SPDM_CY_PORT2_CLK                       270
+#define SPDM_CY_PORT3_CLK                       271
+#define SPDM_CY_PORT4_CLK                       272
+#define SPDM_CY_PORT5_CLK                       273
+#define SPDM_CY_PORT6_CLK                       274
+#define SPDM_CY_PORT7_CLK                       275
+#define PLL0                                    276
+#define PLL0_VOTE                               277
+#define PLL3                                    278
+#define PLL3_VOTE                               279
+#define PLL4_VOTE                               280
+#define PLL5                                    281
+#define PLL5_VOTE                               282
+#define PLL6                                    283
+#define PLL6_VOTE                               284
+#define PLL7_VOTE                               285
+#define PLL8                                    286
+#define PLL8_VOTE                               287
+#define PLL9                                    288
+#define PLL10                                   289
+#define PLL11                                   290
+#define PLL12                                   291
+#define PLL13                                   292
+#define PLL14                                   293
+#define PLL14_VOTE                              294
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
new file mode 100644
index 000000000000..223ca174d9d3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8974_H
+#define GPLL0                                                   0
+#define GPLL0_VOTE                                              1
+#define CONFIG_NOC_CLK_SRC                                      2
+#define GPLL2                                                   3
+#define GPLL2_VOTE                                              4
+#define GPLL3                                                   5
+#define GPLL3_VOTE                                              6
+#define PERIPH_NOC_CLK_SRC                                      7
+#define BLSP_UART_SIM_CLK_SRC                                   8
+#define QDSS_TSCTR_CLK_SRC                                      9
+#define BIMC_DDR_CLK_SRC                                        10
+#define SYSTEM_NOC_CLK_SRC                                      11
+#define GPLL1                                                   12
+#define GPLL1_VOTE                                              13
+#define RPM_CLK_SRC                                             14
+#define GCC_BIMC_CLK                                            15
+#define BIMC_DDR_CPLL0_ROOT_CLK_SRC                             16
+#define KPSS_AHB_CLK_SRC                                        17
+#define QDSS_AT_CLK_SRC                                         18
+#define USB30_MASTER_CLK_SRC                                    19
+#define BIMC_DDR_CPLL1_ROOT_CLK_SRC                             20
+#define QDSS_STM_CLK_SRC                                        21
+#define ACC_CLK_SRC                                             22
+#define SEC_CTRL_CLK_SRC                                        23
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                             24
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                             25
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                             26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                             27
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                             28
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                             29
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                             30
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                             31
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                             32
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                             33
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                             34
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                             35
+#define BLSP1_UART1_APPS_CLK_SRC                                36
+#define BLSP1_UART2_APPS_CLK_SRC                                37
+#define BLSP1_UART3_APPS_CLK_SRC                                38
+#define BLSP1_UART4_APPS_CLK_SRC                                39
+#define BLSP1_UART5_APPS_CLK_SRC                                40
+#define BLSP1_UART6_APPS_CLK_SRC                                41
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                             42
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                             43
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                             44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                             45
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                             46
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                             47
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                             48
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                             49
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                             50
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                             51
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                             52
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                             53
+#define BLSP2_UART1_APPS_CLK_SRC                                54
+#define BLSP2_UART2_APPS_CLK_SRC                                55
+#define BLSP2_UART3_APPS_CLK_SRC                                56
+#define BLSP2_UART4_APPS_CLK_SRC                                57
+#define BLSP2_UART5_APPS_CLK_SRC                                58
+#define BLSP2_UART6_APPS_CLK_SRC                                59
+#define CE1_CLK_SRC                                             60
+#define CE2_CLK_SRC                                             61
+#define GP1_CLK_SRC                                             62
+#define GP2_CLK_SRC                                             63
+#define GP3_CLK_SRC                                             64
+#define PDM2_CLK_SRC                                            65
+#define QDSS_TRACECLKIN_CLK_SRC                                 66
+#define RBCPR_CLK_SRC                                           67
+#define SDCC1_APPS_CLK_SRC                                      68
+#define SDCC2_APPS_CLK_SRC                                      69
+#define SDCC3_APPS_CLK_SRC                                      70
+#define SDCC4_APPS_CLK_SRC                                      71
+#define SPMI_AHB_CLK_SRC                                        72
+#define SPMI_SER_CLK_SRC                                        73
+#define TSIF_REF_CLK_SRC                                        74
+#define USB30_MOCK_UTMI_CLK_SRC                                 75
+#define USB_HS_SYSTEM_CLK_SRC                                   76
+#define USB_HSIC_CLK_SRC                                        77
+#define USB_HSIC_IO_CAL_CLK_SRC                                 78
+#define USB_HSIC_SYSTEM_CLK_SRC                                 79
+#define GCC_BAM_DMA_AHB_CLK                                     80
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK                       81
+#define GCC_BIMC_CFG_AHB_CLK                                    82
+#define GCC_BIMC_KPSS_AXI_CLK                                   83
+#define GCC_BIMC_SLEEP_CLK                                      84
+#define GCC_BIMC_SYSNOC_AXI_CLK                                 85
+#define GCC_BIMC_XO_CLK                                         86
+#define GCC_BLSP1_AHB_CLK                                       87
+#define GCC_BLSP1_SLEEP_CLK                                     88
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                             89
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                             90
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                             91
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                             92
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                             93
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                             94
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                             95
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                             96
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                             97
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                             98
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                             99
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                             100
+#define GCC_BLSP1_UART1_APPS_CLK                                101
+#define GCC_BLSP1_UART1_SIM_CLK                                 102
+#define GCC_BLSP1_UART2_APPS_CLK                                103
+#define GCC_BLSP1_UART2_SIM_CLK                                 104
+#define GCC_BLSP1_UART3_APPS_CLK                                105
+#define GCC_BLSP1_UART3_SIM_CLK                                 106
+#define GCC_BLSP1_UART4_APPS_CLK                                107
+#define GCC_BLSP1_UART4_SIM_CLK                                 108
+#define GCC_BLSP1_UART5_APPS_CLK                                109
+#define GCC_BLSP1_UART5_SIM_CLK                                 110
+#define GCC_BLSP1_UART6_APPS_CLK                                111
+#define GCC_BLSP1_UART6_SIM_CLK                                 112
+#define GCC_BLSP2_AHB_CLK                                       113
+#define GCC_BLSP2_SLEEP_CLK                                     114
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                             115
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                             116
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                             117
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                             118
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                             119
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                             120
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                             121
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                             122
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                             123
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                             124
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                             125
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                             126
+#define GCC_BLSP2_UART1_APPS_CLK                                127
+#define GCC_BLSP2_UART1_SIM_CLK                                 128
+#define GCC_BLSP2_UART2_APPS_CLK                                129
+#define GCC_BLSP2_UART2_SIM_CLK                                 130
+#define GCC_BLSP2_UART3_APPS_CLK                                131
+#define GCC_BLSP2_UART3_SIM_CLK                                 132
+#define GCC_BLSP2_UART4_APPS_CLK                                133
+#define GCC_BLSP2_UART4_SIM_CLK                                 134
+#define GCC_BLSP2_UART5_APPS_CLK                                135
+#define GCC_BLSP2_UART5_SIM_CLK                                 136
+#define GCC_BLSP2_UART6_APPS_CLK                                137
+#define GCC_BLSP2_UART6_SIM_CLK                                 138
+#define GCC_BOOT_ROM_AHB_CLK                                    139
+#define GCC_CE1_AHB_CLK                                         140
+#define GCC_CE1_AXI_CLK                                         141
+#define GCC_CE1_CLK                                             142
+#define GCC_CE2_AHB_CLK                                         143
+#define GCC_CE2_AXI_CLK                                         144
+#define GCC_CE2_CLK                                             145
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK                           146
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK                           147
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK                           148
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK                           149
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK                           150
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK                           151
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK                           152
+#define GCC_CFG_NOC_AHB_CLK                                     153
+#define GCC_CFG_NOC_DDR_CFG_CLK                                 154
+#define GCC_CFG_NOC_RPM_AHB_CLK                                 155
+#define GCC_BIMC_DDR_CPLL0_CLK                                  156
+#define GCC_BIMC_DDR_CPLL1_CLK                                  157
+#define GCC_DDR_DIM_CFG_CLK                                     158
+#define GCC_DDR_DIM_SLEEP_CLK                                   159
+#define GCC_DEHR_CLK                                            160
+#define GCC_AHB_CLK                                             161
+#define GCC_IM_SLEEP_CLK                                        162
+#define GCC_XO_CLK                                              163
+#define GCC_XO_DIV4_CLK                                         164
+#define GCC_GP1_CLK                                             165
+#define GCC_GP2_CLK                                             166
+#define GCC_GP3_CLK                                             167
+#define GCC_IMEM_AXI_CLK                                        168
+#define GCC_IMEM_CFG_AHB_CLK                                    169
+#define GCC_KPSS_AHB_CLK                                        170
+#define GCC_KPSS_AXI_CLK                                        171
+#define GCC_LPASS_Q6_AXI_CLK                                    172
+#define GCC_MMSS_NOC_AT_CLK                                     173
+#define GCC_MMSS_NOC_CFG_AHB_CLK                                174
+#define GCC_OCMEM_NOC_CFG_AHB_CLK                               175
+#define GCC_OCMEM_SYS_NOC_AXI_CLK                               176
+#define GCC_MPM_AHB_CLK                                         177
+#define GCC_MSG_RAM_AHB_CLK                                     178
+#define GCC_MSS_CFG_AHB_CLK                                     179
+#define GCC_MSS_Q6_BIMC_AXI_CLK                                 180
+#define GCC_NOC_CONF_XPU_AHB_CLK                                181
+#define GCC_PDM2_CLK                                            182
+#define GCC_PDM_AHB_CLK                                         183
+#define GCC_PDM_XO4_CLK                                         184
+#define GCC_PERIPH_NOC_AHB_CLK                                  185
+#define GCC_PERIPH_NOC_AT_CLK                                   186
+#define GCC_PERIPH_NOC_CFG_AHB_CLK                              187
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK                          188
+#define GCC_PERIPH_XPU_AHB_CLK                                  189
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK                           190
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK                           191
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK                           192
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK                           193
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK                           194
+#define GCC_PRNG_AHB_CLK                                        195
+#define GCC_QDSS_AT_CLK                                         196
+#define GCC_QDSS_CFG_AHB_CLK                                    197
+#define GCC_QDSS_DAP_AHB_CLK                                    198
+#define GCC_QDSS_DAP_CLK                                        199
+#define GCC_QDSS_ETR_USB_CLK                                    200
+#define GCC_QDSS_STM_CLK                                        201
+#define GCC_QDSS_TRACECLKIN_CLK                                 202
+#define GCC_QDSS_TSCTR_DIV16_CLK                                203
+#define GCC_QDSS_TSCTR_DIV2_CLK                                 204
+#define GCC_QDSS_TSCTR_DIV3_CLK                                 205
+#define GCC_QDSS_TSCTR_DIV4_CLK                                 206
+#define GCC_QDSS_TSCTR_DIV8_CLK                                 207
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK                              208
+#define GCC_RBCPR_AHB_CLK                                       209
+#define GCC_RBCPR_CLK                                           210
+#define GCC_RPM_BUS_AHB_CLK                                     211
+#define GCC_RPM_PROC_HCLK                                       212
+#define GCC_RPM_SLEEP_CLK                                       213
+#define GCC_RPM_TIMER_CLK                                       214
+#define GCC_SDCC1_AHB_CLK                                       215
+#define GCC_SDCC1_APPS_CLK                                      216
+#define GCC_SDCC1_INACTIVITY_TIMERS_CLK                         217
+#define GCC_SDCC2_AHB_CLK                                       218
+#define GCC_SDCC2_APPS_CLK                                      219
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK                         220
+#define GCC_SDCC3_AHB_CLK                                       221
+#define GCC_SDCC3_APPS_CLK                                      222
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK                         223
+#define GCC_SDCC4_AHB_CLK                                       224
+#define GCC_SDCC4_APPS_CLK                                      225
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK                         226
+#define GCC_SEC_CTRL_ACC_CLK                                    227
+#define GCC_SEC_CTRL_AHB_CLK                                    228
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK                         229
+#define GCC_SEC_CTRL_CLK                                        230
+#define GCC_SEC_CTRL_SENSE_CLK                                  231
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK                           232
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK                           233
+#define GCC_SPDM_BIMC_CY_CLK                                    234
+#define GCC_SPDM_CFG_AHB_CLK                                    235
+#define GCC_SPDM_DEBUG_CY_CLK                                   236
+#define GCC_SPDM_FF_CLK                                         237
+#define GCC_SPDM_MSTR_AHB_CLK                                   238
+#define GCC_SPDM_PNOC_CY_CLK                                    239
+#define GCC_SPDM_RPM_CY_CLK                                     240
+#define GCC_SPDM_SNOC_CY_CLK                                    241
+#define GCC_SPMI_AHB_CLK                                        242
+#define GCC_SPMI_CNOC_AHB_CLK                                   243
+#define GCC_SPMI_SER_CLK                                        244
+#define GCC_SNOC_CNOC_AHB_CLK                                   245
+#define GCC_SNOC_PNOC_AHB_CLK                                   246
+#define GCC_SYS_NOC_AT_CLK                                      247
+#define GCC_SYS_NOC_AXI_CLK                                     248
+#define GCC_SYS_NOC_KPSS_AHB_CLK                                249
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK                            250
+#define GCC_SYS_NOC_USB3_AXI_CLK                                251
+#define GCC_TCSR_AHB_CLK                                        252
+#define GCC_TLMM_AHB_CLK                                        253
+#define GCC_TLMM_CLK                                            254
+#define GCC_TSIF_AHB_CLK                                        255
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                          256
+#define GCC_TSIF_REF_CLK                                        257
+#define GCC_USB2A_PHY_SLEEP_CLK                                 258
+#define GCC_USB2B_PHY_SLEEP_CLK                                 259
+#define GCC_USB30_MASTER_CLK                                    260
+#define GCC_USB30_MOCK_UTMI_CLK                                 261
+#define GCC_USB30_SLEEP_CLK                                     262
+#define GCC_USB_HS_AHB_CLK                                      263
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK                        264
+#define GCC_USB_HS_SYSTEM_CLK                                   265
+#define GCC_USB_HSIC_AHB_CLK                                    266
+#define GCC_USB_HSIC_CLK                                        267
+#define GCC_USB_HSIC_IO_CAL_CLK                                 268
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK                           269
+#define GCC_USB_HSIC_SYSTEM_CLK                                 270
+#define GCC_WCSS_GPLL1_CLK_SRC                                  271
+#define GCC_MMSS_GPLL0_CLK_SRC                                  272
+#define GCC_LPASS_GPLL0_CLK_SRC                                 273
+#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA                        274
+#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA                        275
+#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA                       276
+#define GCC_IMEM_AXI_CLK_SLEEP_ENA                              277
+#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA                      278
+#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA                         279
+#define GCC_KPSS_AHB_CLK_SLEEP_ENA                              280
+#define GCC_KPSS_AXI_CLK_SLEEP_ENA                              281
+#define GCC_MPM_AHB_CLK_SLEEP_ENA                               282
+#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA                     283
+#define GCC_BLSP1_AHB_CLK_SLEEP_ENA                             284
+#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA                           285
+#define GCC_BLSP2_AHB_CLK_SLEEP_ENA                             286
+#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA                           287
+#define GCC_PRNG_AHB_CLK_SLEEP_ENA                              288
+#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA                           289
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA             290
+#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA                          291
+#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA                           292
+#define GCC_TLMM_AHB_CLK_SLEEP_ENA                              293
+#define GCC_TLMM_CLK_SLEEP_ENA                                  294
+#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA                         295
+#define GCC_CE1_CLK_SLEEP_ENA                                   296
+#define GCC_CE1_AXI_CLK_SLEEP_ENA                               297
+#define GCC_CE1_AHB_CLK_SLEEP_ENA                               298
+#define GCC_CE2_CLK_SLEEP_ENA                                   299
+#define GCC_CE2_AXI_CLK_SLEEP_ENA                               300
+#define GCC_CE2_AHB_CLK_SLEEP_ENA                               301
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
new file mode 100644
index 000000000000..5868ef14a777
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+#define MMSS_AHB_SRC                                    0
+#define FAB_AHB_CLK                                     1
+#define APU_AHB_CLK                                     2
+#define TV_ENC_AHB_CLK                                  3
+#define AMP_AHB_CLK                                     4
+#define DSI2_S_AHB_CLK                                  5
+#define JPEGD_AHB_CLK                                   6
+#define GFX2D0_AHB_CLK                                  7
+#define DSI_S_AHB_CLK                                   8
+#define DSI2_M_AHB_CLK                                  9
+#define VPE_AHB_CLK                                     10
+#define SMMU_AHB_CLK                                    11
+#define HDMI_M_AHB_CLK                                  12
+#define VFE_AHB_CLK                                     13
+#define ROT_AHB_CLK                                     14
+#define VCODEC_AHB_CLK                                  15
+#define MDP_AHB_CLK                                     16
+#define DSI_M_AHB_CLK                                   17
+#define CSI_AHB_CLK                                     18
+#define MMSS_IMEM_AHB_CLK                               19
+#define IJPEG_AHB_CLK                                   20
+#define HDMI_S_AHB_CLK                                  21
+#define GFX3D_AHB_CLK                                   22
+#define GFX2D1_AHB_CLK                                  23
+#define MMSS_FPB_CLK                                    24
+#define MMSS_AXI_SRC                                    25
+#define MMSS_FAB_CORE                                   26
+#define FAB_MSP_AXI_CLK                                 27
+#define JPEGD_AXI_CLK                                   28
+#define GMEM_AXI_CLK                                    29
+#define MDP_AXI_CLK                                     30
+#define MMSS_IMEM_AXI_CLK                               31
+#define IJPEG_AXI_CLK                                   32
+#define GFX3D_AXI_CLK                                   33
+#define VCODEC_AXI_CLK                                  34
+#define VFE_AXI_CLK                                     35
+#define VPE_AXI_CLK                                     36
+#define ROT_AXI_CLK                                     37
+#define VCODEC_AXI_A_CLK                                38
+#define VCODEC_AXI_B_CLK                                39
+#define MM_AXI_S3_FCLK                                  40
+#define MM_AXI_S2_FCLK                                  41
+#define MM_AXI_S1_FCLK                                  42
+#define MM_AXI_S0_FCLK                                  43
+#define MM_AXI_S2_CLK                                   44
+#define MM_AXI_S1_CLK                                   45
+#define MM_AXI_S0_CLK                                   46
+#define CSI0_SRC                                        47
+#define CSI0_CLK                                        48
+#define CSI0_PHY_CLK                                    49
+#define CSI1_SRC                                        50
+#define CSI1_CLK                                        51
+#define CSI1_PHY_CLK                                    52
+#define CSI2_SRC                                        53
+#define CSI2_CLK                                        54
+#define CSI2_PHY_CLK                                    55
+#define DSI_SRC                                         56
+#define DSI_CLK                                         57
+#define CSI_PIX_CLK                                     58
+#define CSI_RDI_CLK                                     59
+#define MDP_VSYNC_CLK                                   60
+#define HDMI_DIV_CLK                                    61
+#define HDMI_APP_CLK                                    62
+#define CSI_PIX1_CLK                                    63
+#define CSI_RDI2_CLK                                    64
+#define CSI_RDI1_CLK                                    65
+#define GFX2D0_SRC                                      66
+#define GFX2D0_CLK                                      67
+#define GFX2D1_SRC                                      68
+#define GFX2D1_CLK                                      69
+#define GFX3D_SRC                                       70
+#define GFX3D_CLK                                       71
+#define IJPEG_SRC                                       72
+#define IJPEG_CLK                                       73
+#define JPEGD_SRC                                       74
+#define JPEGD_CLK                                       75
+#define MDP_SRC                                         76
+#define MDP_CLK                                         77
+#define MDP_LUT_CLK                                     78
+#define DSI2_PIXEL_SRC                                  79
+#define DSI2_PIXEL_CLK                                  80
+#define DSI2_SRC                                        81
+#define DSI2_CLK                                        82
+#define DSI1_BYTE_SRC                                   83
+#define DSI1_BYTE_CLK                                   84
+#define DSI2_BYTE_SRC                                   85
+#define DSI2_BYTE_CLK                                   86
+#define DSI1_ESC_SRC                                    87
+#define DSI1_ESC_CLK                                    88
+#define DSI2_ESC_SRC                                    89
+#define DSI2_ESC_CLK                                    90
+#define ROT_SRC                                         91
+#define ROT_CLK                                         92
+#define TV_ENC_CLK                                      93
+#define TV_DAC_CLK                                      94
+#define HDMI_TV_CLK                                     95
+#define MDP_TV_CLK                                      96
+#define TV_SRC                                          97
+#define VCODEC_SRC                                      98
+#define VCODEC_CLK                                      99
+#define VFE_SRC                                         100
+#define VFE_CLK                                         101
+#define VFE_CSI_CLK                                     102
+#define VPE_SRC                                         103
+#define VPE_CLK                                         104
+#define DSI_PIXEL_SRC                                   105
+#define DSI_PIXEL_CLK                                   106
+#define CAMCLK0_SRC                                     107
+#define CAMCLK0_CLK                                     108
+#define CAMCLK1_SRC                                     109
+#define CAMCLK1_CLK                                     110
+#define CAMCLK2_SRC                                     111
+#define CAMCLK2_CLK                                     112
+#define CSIPHYTIMER_SRC                                 113
+#define CSIPHY2_TIMER_CLK                               114
+#define CSIPHY1_TIMER_CLK                               115
+#define CSIPHY0_TIMER_CLK                               116
+#define PLL1                                            117
+#define PLL2                                            118
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
new file mode 100644
index 000000000000..04d318d1187a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+#define MMSS_AHB_CLK_SRC                                0
+#define MMSS_AXI_CLK_SRC                                1
+#define MMPLL0                                          2
+#define MMPLL0_VOTE                                     3
+#define MMPLL1                                          4
+#define MMPLL1_VOTE                                     5
+#define MMPLL2                                          6
+#define MMPLL3                                          7
+#define CSI0_CLK_SRC                                    8
+#define CSI1_CLK_SRC                                    9
+#define CSI2_CLK_SRC                                    10
+#define CSI3_CLK_SRC                                    11
+#define VFE0_CLK_SRC                                    12
+#define VFE1_CLK_SRC                                    13
+#define MDP_CLK_SRC                                     14
+#define GFX3D_CLK_SRC                                   15
+#define JPEG0_CLK_SRC                                   16
+#define JPEG1_CLK_SRC                                   17
+#define JPEG2_CLK_SRC                                   18
+#define PCLK0_CLK_SRC                                   19
+#define PCLK1_CLK_SRC                                   20
+#define VCODEC0_CLK_SRC                                 21
+#define CCI_CLK_SRC                                     22
+#define CAMSS_GP0_CLK_SRC                               23
+#define CAMSS_GP1_CLK_SRC                               24
+#define MCLK0_CLK_SRC                                   25
+#define MCLK1_CLK_SRC                                   26
+#define MCLK2_CLK_SRC                                   27
+#define MCLK3_CLK_SRC                                   28
+#define CSI0PHYTIMER_CLK_SRC                            29
+#define CSI1PHYTIMER_CLK_SRC                            30
+#define CSI2PHYTIMER_CLK_SRC                            31
+#define CPP_CLK_SRC                                     32
+#define BYTE0_CLK_SRC                                   33
+#define BYTE1_CLK_SRC                                   34
+#define EDPAUX_CLK_SRC                                  35
+#define EDPLINK_CLK_SRC                                 36
+#define EDPPIXEL_CLK_SRC                                37
+#define ESC0_CLK_SRC                                    38
+#define ESC1_CLK_SRC                                    39
+#define EXTPCLK_CLK_SRC                                 40
+#define HDMI_CLK_SRC                                    41
+#define VSYNC_CLK_SRC                                   42
+#define RBCPR_CLK_SRC                                   43
+#define CAMSS_CCI_CCI_AHB_CLK                           44
+#define CAMSS_CCI_CCI_CLK                               45
+#define CAMSS_CSI0_AHB_CLK                              46
+#define CAMSS_CSI0_CLK                                  47
+#define CAMSS_CSI0PHY_CLK                               48
+#define CAMSS_CSI0PIX_CLK                               49
+#define CAMSS_CSI0RDI_CLK                               50
+#define CAMSS_CSI1_AHB_CLK                              51
+#define CAMSS_CSI1_CLK                                  52
+#define CAMSS_CSI1PHY_CLK                               53
+#define CAMSS_CSI1PIX_CLK                               54
+#define CAMSS_CSI1RDI_CLK                               55
+#define CAMSS_CSI2_AHB_CLK                              56
+#define CAMSS_CSI2_CLK                                  57
+#define CAMSS_CSI2PHY_CLK                               58
+#define CAMSS_CSI2PIX_CLK                               59
+#define CAMSS_CSI2RDI_CLK                               60
+#define CAMSS_CSI3_AHB_CLK                              61
+#define CAMSS_CSI3_CLK                                  62
+#define CAMSS_CSI3PHY_CLK                               63
+#define CAMSS_CSI3PIX_CLK                               64
+#define CAMSS_CSI3RDI_CLK                               65
+#define CAMSS_CSI_VFE0_CLK                              66
+#define CAMSS_CSI_VFE1_CLK                              67
+#define CAMSS_GP0_CLK                                   68
+#define CAMSS_GP1_CLK                                   69
+#define CAMSS_ISPIF_AHB_CLK                             70
+#define CAMSS_JPEG_JPEG0_CLK                            71
+#define CAMSS_JPEG_JPEG1_CLK                            72
+#define CAMSS_JPEG_JPEG2_CLK                            73
+#define CAMSS_JPEG_JPEG_AHB_CLK                         74
+#define CAMSS_JPEG_JPEG_AXI_CLK                         75
+#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK                    76
+#define CAMSS_MCLK0_CLK                                 77
+#define CAMSS_MCLK1_CLK                                 78
+#define CAMSS_MCLK2_CLK                                 79
+#define CAMSS_MCLK3_CLK                                 80
+#define CAMSS_MICRO_AHB_CLK                             81
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK                     82
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK                     83
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK                     84
+#define CAMSS_TOP_AHB_CLK                               85
+#define CAMSS_VFE_CPP_AHB_CLK                           86
+#define CAMSS_VFE_CPP_CLK                               87
+#define CAMSS_VFE_VFE0_CLK                              88
+#define CAMSS_VFE_VFE1_CLK                              89
+#define CAMSS_VFE_VFE_AHB_CLK                           90
+#define CAMSS_VFE_VFE_AXI_CLK                           91
+#define CAMSS_VFE_VFE_OCMEMNOC_CLK                      92
+#define MDSS_AHB_CLK                                    93
+#define MDSS_AXI_CLK                                    94
+#define MDSS_BYTE0_CLK                                  95
+#define MDSS_BYTE1_CLK                                  96
+#define MDSS_EDPAUX_CLK                                 97
+#define MDSS_EDPLINK_CLK                                98
+#define MDSS_EDPPIXEL_CLK                               99
+#define MDSS_ESC0_CLK                                   100
+#define MDSS_ESC1_CLK                                   101
+#define MDSS_EXTPCLK_CLK                                102
+#define MDSS_HDMI_AHB_CLK                               103
+#define MDSS_HDMI_CLK                                   104
+#define MDSS_MDP_CLK                                    105
+#define MDSS_MDP_LUT_CLK                                106
+#define MDSS_PCLK0_CLK                                  107
+#define MDSS_PCLK1_CLK                                  108
+#define MDSS_VSYNC_CLK                                  109
+#define MMSS_MISC_AHB_CLK                               110
+#define MMSS_MMSSNOC_AHB_CLK                            111
+#define MMSS_MMSSNOC_BTO_AHB_CLK                        112
+#define MMSS_MMSSNOC_AXI_CLK                            113
+#define MMSS_S0_AXI_CLK                                 114
+#define OCMEMCX_AHB_CLK                                 115
+#define OCMEMCX_OCMEMNOC_CLK                            116
+#define OXILI_OCMEMGX_CLK                               117
+#define OCMEMNOC_CLK                                    118
+#define OXILI_GFX3D_CLK                                 119
+#define OXILICX_AHB_CLK                                 120
+#define OXILICX_AXI_CLK                                 121
+#define VENUS0_AHB_CLK                                  122
+#define VENUS0_AXI_CLK                                  123
+#define VENUS0_OCMEMNOC_CLK                             124
+#define VENUS0_VCODEC0_CLK                              125
+#define OCMEMNOC_CLK_SRC                                126
+#define SPDM_JPEG0                                      127
+#define SPDM_JPEG1                                      128
+#define SPDM_MDP                                        129
+#define SPDM_AXI                                        130
+#define SPDM_VCODEC0                                    131
+#define SPDM_VFE0                                       132
+#define SPDM_VFE1                                       133
+#define SPDM_JPEG2                                      134
+#define SPDM_PCLK1                                      135
+#define SPDM_GFX3D                                      136
+#define SPDM_AHB                                        137
+#define SPDM_PCLK0                                      138
+#define SPDM_OCMEMNOC                                   139
+#define SPDM_CSI0                                       140
+#define SPDM_RM_AXI                                     141
+#define SPDM_RM_OCMEMNOC                                142
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8660.h b/include/dt-bindings/reset/qcom,gcc-msm8660.h
new file mode 100644
index 000000000000..a83282fe5465
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8660.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8660_H
+#define AFAB_CORE_RESET                                 0
+#define SCSS_SYS_RESET                                  1
+#define SCSS_SYS_POR_RESET                              2
+#define AFAB_SMPSS_S_RESET                              3
+#define AFAB_SMPSS_M1_RESET                             4
+#define AFAB_SMPSS_M0_RESET                             5
+#define AFAB_EBI1_S_RESET                               6
+#define SFAB_CORE_RESET                                 7
+#define SFAB_ADM0_M0_RESET                              8
+#define SFAB_ADM0_M1_RESET                              9
+#define SFAB_ADM0_M2_RESET                              10
+#define ADM0_C2_RESET                                   11
+#define ADM0_C1_RESET                                   12
+#define ADM0_C0_RESET                                   13
+#define ADM0_PBUS_RESET                                 14
+#define ADM0_RESET                                      15
+#define SFAB_ADM1_M0_RESET                              16
+#define SFAB_ADM1_M1_RESET                              17
+#define SFAB_ADM1_M2_RESET                              18
+#define MMFAB_ADM1_M3_RESET                             19
+#define ADM1_C3_RESET                                   20
+#define ADM1_C2_RESET                                   21
+#define ADM1_C1_RESET                                   22
+#define ADM1_C0_RESET                                   23
+#define ADM1_PBUS_RESET                                 24
+#define ADM1_RESET                                      25
+#define IMEM0_RESET                                     26
+#define SFAB_LPASS_Q6_RESET                             27
+#define SFAB_AFAB_M_RESET                               28
+#define AFAB_SFAB_M0_RESET                              29
+#define AFAB_SFAB_M1_RESET                              30
+#define DFAB_CORE_RESET                                 31
+#define SFAB_DFAB_M_RESET                               32
+#define DFAB_SFAB_M_RESET                               33
+#define DFAB_SWAY0_RESET                                34
+#define DFAB_SWAY1_RESET                                35
+#define DFAB_ARB0_RESET                                 36
+#define DFAB_ARB1_RESET                                 37
+#define PPSS_PROC_RESET                                 38
+#define PPSS_RESET                                      39
+#define PMEM_RESET                                      40
+#define DMA_BAM_RESET                                   41
+#define SIC_RESET                                       42
+#define SPS_TIC_RESET                                   43
+#define CFBP0_RESET                                     44
+#define CFBP1_RESET                                     45
+#define CFBP2_RESET                                     46
+#define EBI2_RESET                                      47
+#define SFAB_CFPB_M_RESET                               48
+#define CFPB_MASTER_RESET                               49
+#define SFAB_CFPB_S_RESET                               50
+#define CFPB_SPLITTER_RESET                             51
+#define TSIF_RESET                                      52
+#define CE1_RESET                                       53
+#define CE2_RESET                                       54
+#define SFAB_SFPB_M_RESET                               55
+#define SFAB_SFPB_S_RESET                               56
+#define RPM_PROC_RESET                                  57
+#define RPM_BUS_RESET                                   58
+#define RPM_MSG_RAM_RESET                               59
+#define PMIC_ARB0_RESET                                 60
+#define PMIC_ARB1_RESET                                 61
+#define PMIC_SSBI2_RESET                                62
+#define SDC1_RESET                                      63
+#define SDC2_RESET                                      64
+#define SDC3_RESET                                      65
+#define SDC4_RESET                                      66
+#define SDC5_RESET                                      67
+#define USB_HS1_RESET                                   68
+#define USB_HS2_XCVR_RESET                              69
+#define USB_HS2_RESET                                   70
+#define USB_FS1_XCVR_RESET                              71
+#define USB_FS1_RESET                                   72
+#define USB_FS2_XCVR_RESET                              73
+#define USB_FS2_RESET                                   74
+#define GSBI1_RESET                                     75
+#define GSBI2_RESET                                     76
+#define GSBI3_RESET                                     77
+#define GSBI4_RESET                                     78
+#define GSBI5_RESET                                     79
+#define GSBI6_RESET                                     80
+#define GSBI7_RESET                                     81
+#define GSBI8_RESET                                     82
+#define GSBI9_RESET                                     83
+#define GSBI10_RESET                                    84
+#define GSBI11_RESET                                    85
+#define GSBI12_RESET                                    86
+#define SPDM_RESET                                      87
+#define SEC_CTRL_RESET                                  88
+#define TLMM_H_RESET                                    89
+#define TLMM_RESET                                      90
+#define MARRM_PWRON_RESET                               91
+#define MARM_RESET                                      92
+#define MAHB1_RESET                                     93
+#define SFAB_MSS_S_RESET                                94
+#define MAHB2_RESET                                     95
+#define MODEM_SW_AHB_RESET                              96
+#define MODEM_RESET                                     97
+#define SFAB_MSS_MDM1_RESET                             98
+#define SFAB_MSS_MDM0_RESET                             99
+#define MSS_SLP_RESET                                   100
+#define MSS_MARM_SAW_RESET                              101
+#define MSS_WDOG_RESET                                  102
+#define TSSC_RESET                                      103
+#define PDM_RESET                                       104
+#define SCSS_CORE0_RESET                                105
+#define SCSS_CORE0_POR_RESET                            106
+#define SCSS_CORE1_RESET                                107
+#define SCSS_CORE1_POR_RESET                            108
+#define MPM_RESET                                       109
+#define EBI1_1X_DIV_RESET                               110
+#define EBI1_RESET                                      111
+#define SFAB_SMPSS_S_RESET                              112
+#define USB_PHY0_RESET                                  113
+#define USB_PHY1_RESET                                  114
+#define PRNG_RESET                                      115
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
new file mode 100644
index 000000000000..a840e680323c
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8960_H
+#define SFAB_MSS_Q6_SW_RESET                            0
+#define SFAB_MSS_Q6_FW_RESET                            1
+#define QDSS_STM_RESET                                  2
+#define AFAB_SMPSS_S_RESET                              3
+#define AFAB_SMPSS_M1_RESET                             4
+#define AFAB_SMPSS_M0_RESET                             5
+#define AFAB_EBI1_CH0_RESET                             6
+#define AFAB_EBI1_CH1_RESET                             7
+#define SFAB_ADM0_M0_RESET                              8
+#define SFAB_ADM0_M1_RESET                              9
+#define SFAB_ADM0_M2_RESET                              10
+#define ADM0_C2_RESET                                   11
+#define ADM0_C1_RESET                                   12
+#define ADM0_C0_RESET                                   13
+#define ADM0_PBUS_RESET                                 14
+#define ADM0_RESET                                      15
+#define QDSS_CLKS_SW_RESET                              16
+#define QDSS_POR_RESET                                  17
+#define QDSS_TSCTR_RESET                                18
+#define QDSS_HRESET_RESET                               19
+#define QDSS_AXI_RESET                                  20
+#define QDSS_DBG_RESET                                  21
+#define PCIE_A_RESET                                    22
+#define PCIE_AUX_RESET                                  23
+#define PCIE_H_RESET                                    24
+#define SFAB_PCIE_M_RESET                               25
+#define SFAB_PCIE_S_RESET                               26
+#define SFAB_MSS_M_RESET                                27
+#define SFAB_USB3_M_RESET                               28
+#define SFAB_RIVA_M_RESET                               29
+#define SFAB_LPASS_RESET                                30
+#define SFAB_AFAB_M_RESET                               31
+#define AFAB_SFAB_M0_RESET                              32
+#define AFAB_SFAB_M1_RESET                              33
+#define SFAB_SATA_S_RESET                               34
+#define SFAB_DFAB_M_RESET                               35
+#define DFAB_SFAB_M_RESET                               36
+#define DFAB_SWAY0_RESET                                37
+#define DFAB_SWAY1_RESET                                38
+#define DFAB_ARB0_RESET                                 39
+#define DFAB_ARB1_RESET                                 40
+#define PPSS_PROC_RESET                                 41
+#define PPSS_RESET                                      42
+#define DMA_BAM_RESET                                   43
+#define SIC_TIC_RESET                                   44
+#define SLIMBUS_H_RESET                                 45
+#define SFAB_CFPB_M_RESET                               46
+#define SFAB_CFPB_S_RESET                               47
+#define TSIF_H_RESET                                    48
+#define CE1_H_RESET                                     49
+#define CE1_CORE_RESET                                  50
+#define CE1_SLEEP_RESET                                 51
+#define CE2_H_RESET                                     52
+#define CE2_CORE_RESET                                  53
+#define SFAB_SFPB_M_RESET                               54
+#define SFAB_SFPB_S_RESET                               55
+#define RPM_PROC_RESET                                  56
+#define PMIC_SSBI2_RESET                                57
+#define SDC1_RESET                                      58
+#define SDC2_RESET                                      59
+#define SDC3_RESET                                      60
+#define SDC4_RESET                                      61
+#define SDC5_RESET                                      62
+#define DFAB_A2_RESET                                   63
+#define USB_HS1_RESET                                   64
+#define USB_HSIC_RESET                                  65
+#define USB_FS1_XCVR_RESET                              66
+#define USB_FS1_RESET                                   67
+#define USB_FS2_XCVR_RESET                              68
+#define USB_FS2_RESET                                   69
+#define GSBI1_RESET                                     70
+#define GSBI2_RESET                                     71
+#define GSBI3_RESET                                     72
+#define GSBI4_RESET                                     73
+#define GSBI5_RESET                                     74
+#define GSBI6_RESET                                     75
+#define GSBI7_RESET                                     76
+#define GSBI8_RESET                                     77
+#define GSBI9_RESET                                     78
+#define GSBI10_RESET                                    79
+#define GSBI11_RESET                                    80
+#define GSBI12_RESET                                    81
+#define SPDM_RESET                                      82
+#define TLMM_H_RESET                                    83
+#define SFAB_MSS_S_RESET                                84
+#define MSS_SLP_RESET                                   85
+#define MSS_Q6SW_JTAG_RESET                             86
+#define MSS_Q6FW_JTAG_RESET                             87
+#define MSS_RESET                                       88
+#define SATA_H_RESET                                    89
+#define SATA_RXOOB_RESE                                 90
+#define SATA_PMALIVE_RESET                              91
+#define SATA_SFAB_M_RESET                               92
+#define TSSC_RESET                                      93
+#define PDM_RESET                                       94
+#define MPM_H_RESET                                     95
+#define MPM_RESET                                       96
+#define SFAB_SMPSS_S_RESET                              97
+#define PRNG_RESET                                      98
+#define RIVA_RESET                                      99
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8974.h b/include/dt-bindings/reset/qcom,gcc-msm8974.h
new file mode 100644
index 000000000000..9bdf54322938
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8974.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8974_H
+#define GCC_SYSTEM_NOC_BCR                      0
+#define GCC_CONFIG_NOC_BCR                      1
+#define GCC_PERIPH_NOC_BCR                      2
+#define GCC_IMEM_BCR                            3
+#define GCC_MMSS_BCR                            4
+#define GCC_QDSS_BCR                            5
+#define GCC_USB_30_BCR                          6
+#define GCC_USB3_PHY_BCR                        7
+#define GCC_USB_HS_HSIC_BCR                     8
+#define GCC_USB_HS_BCR                          9
+#define GCC_USB2A_PHY_BCR                       10
+#define GCC_USB2B_PHY_BCR                       11
+#define GCC_SDCC1_BCR                           12
+#define GCC_SDCC2_BCR                           13
+#define GCC_SDCC3_BCR                           14
+#define GCC_SDCC4_BCR                           15
+#define GCC_BLSP1_BCR                           16
+#define GCC_BLSP1_QUP1_BCR                      17
+#define GCC_BLSP1_UART1_BCR                     18
+#define GCC_BLSP1_QUP2_BCR                      19
+#define GCC_BLSP1_UART2_BCR                     20
+#define GCC_BLSP1_QUP3_BCR                      21
+#define GCC_BLSP1_UART3_BCR                     22
+#define GCC_BLSP1_QUP4_BCR                      23
+#define GCC_BLSP1_UART4_BCR                     24
+#define GCC_BLSP1_QUP5_BCR                      25
+#define GCC_BLSP1_UART5_BCR                     26
+#define GCC_BLSP1_QUP6_BCR                      27
+#define GCC_BLSP1_UART6_BCR                     28
+#define GCC_BLSP2_BCR                           29
+#define GCC_BLSP2_QUP1_BCR                      30
+#define GCC_BLSP2_UART1_BCR                     31
+#define GCC_BLSP2_QUP2_BCR                      32
+#define GCC_BLSP2_UART2_BCR                     33
+#define GCC_BLSP2_QUP3_BCR                      34
+#define GCC_BLSP2_UART3_BCR                     35
+#define GCC_BLSP2_QUP4_BCR                      36
+#define GCC_BLSP2_UART4_BCR                     37
+#define GCC_BLSP2_QUP5_BCR                      38
+#define GCC_BLSP2_UART5_BCR                     39
+#define GCC_BLSP2_QUP6_BCR                      40
+#define GCC_BLSP2_UART6_BCR                     41
+#define GCC_PDM_BCR                             42
+#define GCC_BAM_DMA_BCR                         43
+#define GCC_TSIF_BCR                            44
+#define GCC_TCSR_BCR                            45
+#define GCC_BOOT_ROM_BCR                        46
+#define GCC_MSG_RAM_BCR                         47
+#define GCC_TLMM_BCR                            48
+#define GCC_MPM_BCR                             49
+#define GCC_SEC_CTRL_BCR                        50
+#define GCC_SPMI_BCR                            51
+#define GCC_SPDM_BCR                            52
+#define GCC_CE1_BCR                             53
+#define GCC_CE2_BCR                             54
+#define GCC_BIMC_BCR                            55
+#define GCC_MPM_NON_AHB_RESET                   56
+#define GCC_MPM_AHB_RESET                       57
+#define GCC_SNOC_BUS_TIMEOUT0_BCR               58
+#define GCC_SNOC_BUS_TIMEOUT2_BCR               59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR               60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR               61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR               62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR               63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR               64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR               65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR               66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR               67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR               68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR               69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR               70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR               71
+#define GCC_DEHR_BCR                            72
+#define GCC_RBCPR_BCR                           73
+#define GCC_MSS_RESTART                         74
+#define GCC_LPASS_RESTART                       75
+#define GCC_WCSS_RESTART                        76
+#define GCC_VENUS_RESTART                       77
+#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
new file mode 100644
index 000000000000..ba36ec680118
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H
+#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H
+#define VPE_AXI_RESET                                   0
+#define IJPEG_AXI_RESET                                 1
+#define MPD_AXI_RESET                                   2
+#define VFE_AXI_RESET                                   3
+#define SP_AXI_RESET                                    4
+#define VCODEC_AXI_RESET                                5
+#define ROT_AXI_RESET                                   6
+#define VCODEC_AXI_A_RESET                              7
+#define VCODEC_AXI_B_RESET                              8
+#define FAB_S3_AXI_RESET                                9
+#define FAB_S2_AXI_RESET                                10
+#define FAB_S1_AXI_RESET                                11
+#define FAB_S0_AXI_RESET                                12
+#define SMMU_GFX3D_ABH_RESET                            13
+#define SMMU_VPE_AHB_RESET                              14
+#define SMMU_VFE_AHB_RESET                              15
+#define SMMU_ROT_AHB_RESET                              16
+#define SMMU_VCODEC_B_AHB_RESET                         17
+#define SMMU_VCODEC_A_AHB_RESET                         18
+#define SMMU_MDP1_AHB_RESET                             19
+#define SMMU_MDP0_AHB_RESET                             20
+#define SMMU_JPEGD_AHB_RESET                            21
+#define SMMU_IJPEG_AHB_RESET                            22
+#define SMMU_GFX2D0_AHB_RESET                           23
+#define SMMU_GFX2D1_AHB_RESET                           24
+#define APU_AHB_RESET                                   25
+#define CSI_AHB_RESET                                   26
+#define TV_ENC_AHB_RESET                                27
+#define VPE_AHB_RESET                                   28
+#define FABRIC_AHB_RESET                                29
+#define GFX2D0_AHB_RESET                                30
+#define GFX2D1_AHB_RESET                                31
+#define GFX3D_AHB_RESET                                 32
+#define HDMI_AHB_RESET                                  33
+#define MSSS_IMEM_AHB_RESET                             34
+#define IJPEG_AHB_RESET                                 35
+#define DSI_M_AHB_RESET                                 36
+#define DSI_S_AHB_RESET                                 37
+#define JPEGD_AHB_RESET                                 38
+#define MDP_AHB_RESET                                   39
+#define ROT_AHB_RESET                                   40
+#define VCODEC_AHB_RESET                                41
+#define VFE_AHB_RESET                                   42
+#define DSI2_M_AHB_RESET                                43
+#define DSI2_S_AHB_RESET                                44
+#define CSIPHY2_RESET                                   45
+#define CSI_PIX1_RESET                                  46
+#define CSIPHY0_RESET                                   47
+#define CSIPHY1_RESET                                   48
+#define DSI2_RESET                                      49
+#define VFE_CSI_RESET                                   50
+#define MDP_RESET                                       51
+#define AMP_RESET                                       52
+#define JPEGD_RESET                                     53
+#define CSI1_RESET                                      54
+#define VPE_RESET                                       55
+#define MMSS_FABRIC_RESET                               56
+#define VFE_RESET                                       57
+#define GFX2D0_RESET                                    58
+#define GFX2D1_RESET                                    59
+#define GFX3D_RESET                                     60
+#define HDMI_RESET                                      61
+#define MMSS_IMEM_RESET                                 62
+#define IJPEG_RESET                                     63
+#define CSI0_RESET                                      64
+#define DSI_RESET                                       65
+#define VCODEC_RESET                                    66
+#define MDP_TV_RESET                                    67
+#define MDP_VSYNC_RESET                                 68
+#define ROT_RESET                                       69
+#define TV_HDMI_RESET                                   70
+#define TV_ENC_RESET                                    71
+#define CSI2_RESET                                      72
+#define CSI_RDI1_RESET                                  73
+#define CSI_RDI2_RESET                                  74
+#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/include/dt-bindings/reset/qcom,mmcc-msm8974.h
new file mode 100644
index 000000000000..da3ec37f1b1e
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8974.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H
+#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H
+#define SPDM_RESET                      0
+#define SPDM_RM_RESET                   1
+#define VENUS0_RESET                    2
+#define MDSS_RESET                      3
+#define CAMSS_PHY0_RESET                4
+#define CAMSS_PHY1_RESET                5
+#define CAMSS_PHY2_RESET                6
+#define CAMSS_CSI0_RESET                7
+#define CAMSS_CSI0PHY_RESET             8
+#define CAMSS_CSI0RDI_RESET             9
+#define CAMSS_CSI0PIX_RESET             10
+#define CAMSS_CSI1_RESET                11
+#define CAMSS_CSI1PHY_RESET             12
+#define CAMSS_CSI1RDI_RESET             13
+#define CAMSS_CSI1PIX_RESET             14
+#define CAMSS_CSI2_RESET                15
+#define CAMSS_CSI2PHY_RESET             16
+#define CAMSS_CSI2RDI_RESET             17
+#define CAMSS_CSI2PIX_RESET             18
+#define CAMSS_CSI3_RESET                19
+#define CAMSS_CSI3PHY_RESET             20
+#define CAMSS_CSI3RDI_RESET             21
+#define CAMSS_CSI3PIX_RESET             22
+#define CAMSS_ISPIF_RESET               23
+#define CAMSS_CCI_RESET                 24
+#define CAMSS_MCLK0_RESET               25
+#define CAMSS_MCLK1_RESET               26
+#define CAMSS_MCLK2_RESET               27
+#define CAMSS_MCLK3_RESET               28
+#define CAMSS_GP0_RESET                 29
+#define CAMSS_GP1_RESET                 30
+#define CAMSS_TOP_RESET                 31
+#define CAMSS_MICRO_RESET               32
+#define CAMSS_JPEG_RESET                33
+#define CAMSS_VFE_RESET                 34
+#define CAMSS_CSI_VFE0_RESET            35
+#define CAMSS_CSI_VFE1_RESET            36
+#define OXILI_RESET                     37
+#define OXILICX_RESET                   38
+#define OCMEMCX_RESET                   39
+#define MMSS_RBCRP_RESET                40
+#define MMSSNOCAHB_RESET                41
+#define MMSSNOCAXI_RESET                42
+#define OCMEMNOC_RESET                  43
+#endif
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 8138c94409f3..efbf70b9fd84 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -12,6 +12,7 @@
 #define __LINUX_CLK_PRIVATE_H
 #include <linux/clk-provider.h>
+#include <linux/kref.h>
 #include <linux/list.h>
 /*
@@ -25,10 +26,13 @@
 #ifdef CONFIG_COMMON_CLK
+struct module;
 struct clk {
        const char              *name;
        const struct clk_ops    *ops;
        struct clk_hw           *hw;
+        struct module           *owner;
        struct clk              *parent;
        const char              **parent_names;
        struct clk              **parents;
@@ -41,12 +45,14 @@ struct clk {
        unsigned long           flags;
        unsigned int            enable_count;
        unsigned int            prepare_count;
+        unsigned long           accuracy;
        struct hlist_head       children;
        struct hlist_node       child_node;
        unsigned int            notifier_count;
-#ifdef CONFIG_COMMON_CLK_DEBUG
+#ifdef CONFIG_DEBUG_FS
        struct dentry           *dentry;
 #endif
+        struct kref             ref;
 };
 /*
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253b8603..999b28ba38f7 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -29,6 +29,7 @@
 #define CLK_IS_BASIC            BIT(5) /* Basic clk, can't do a to_clk_foo() */
 #define CLK_GET_RATE_NOCACHE    BIT(6) /* do not use the cached clk rate */
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
 struct clk_hw;
@@ -108,6 +109,25 @@ struct clk_hw;
 *              which is likely helpful for most .set_rate implementation.
 *              Returns 0 on success, -EERROR otherwise.
 *
+ * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
+ *              is expressed in ppb (parts per billion). The parent accuracy is
+ *              an input parameter.
+ *              Returns the calculated accuracy.  Optional - if this op is not
+ *              set then clock accuracy will be initialized to parent accuracy
+ *              or 0 (perfect clock) if clock has no parent.
+ *
+ * @set_rate_and_parent: Change the rate and the parent of this clock. The
+ *              requested rate is specified by the second argument, which
+ *              should typically be the return of .round_rate call.  The
+ *              third argument gives the parent rate which is likely helpful
+ *              for most .set_rate_and_parent implementation. The fourth
+ *              argument gives the parent index. This callback is optional (and
+ *              unnecessary) for clocks with 0 or 1 parents as well as
+ *              for clocks that can tolerate switching the rate and the parent
+ *              separately via calls to .set_parent and .set_rate.
+ *              Returns 0 on success, -EERROR otherwise.
+ *
+ *
 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
 * implementations to split any work between atomic (enable) and sleepable
 * (prepare) contexts.  If enabling a clock requires code that might sleep,
@@ -139,6 +159,11 @@ struct clk_ops {
        u8              (*get_parent)(struct clk_hw *hw);
        int             (*set_rate)(struct clk_hw *hw, unsigned long,
                                    unsigned long);
+        int             (*set_rate_and_parent)(struct clk_hw *hw,
+                                    unsigned long rate,
+                                    unsigned long parent_rate, u8 index);
+        unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
+                                           unsigned long parent_accuracy);
        void            (*init)(struct clk_hw *hw);
 };
@@ -194,6 +219,7 @@ struct clk_hw {
 struct clk_fixed_rate {
        struct          clk_hw hw;
        unsigned long   fixed_rate;
+        unsigned long   fixed_accuracy;
        u8              flags;
 };
@@ -201,6 +227,9 @@ extern const struct clk_ops clk_fixed_rate_ops;
 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                unsigned long fixed_rate);
+struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
+                const char *name, const char *parent_name, unsigned long flags,
+                unsigned long fixed_rate, unsigned long fixed_accuracy);
 void of_fixed_clk_setup(struct device_node *np);
@@ -433,6 +462,7 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
+unsigned long __clk_get_accuracy(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
 bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 9a6d04524b1a..0dd91148165e 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -82,6 +82,23 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
+/**
+ * clk_get_accuracy - obtain the clock accuracy in ppb (parts per billion)
+ *                    for a clock source.
+ * @clk: clock source
+ *
+ * This gets the clock source accuracy expressed in ppb.
+ * A perfect clock returns 0.
+ */
+long clk_get_accuracy(struct clk *clk);
+#else
+static inline long clk_get_accuracy(struct clk *clk)
+{
+        return -ENOTSUPP;
+}
 #endif
 /**
diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index a6a6f603103b..94bad77eeb4a 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -43,4 +43,9 @@ int clk_add_alias(const char *, const char *, char *, struct device *);
 int clk_register_clkdev(struct clk *, const char *, const char *, ...);
 int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
+#ifdef CONFIG_COMMON_CLK
+int __clk_get(struct clk *clk);
+void __clk_put(struct clk *clk);
+#endif
 #endif
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index 2f61311ae3e0..41a4695fde08 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -21,6 +21,7 @@ struct reset_control_ops {
 struct module;
 struct device_node;
+struct of_phandle_args;
 /**
 * struct reset_controller_dev - reset controller entity that might