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-rw-r--r--include/asm-powerpc/hw_irq.h31
-rw-r--r--include/asm-powerpc/immap_qe.h17
-rw-r--r--include/asm-powerpc/iommu.h8
-rw-r--r--include/asm-powerpc/mmu.h15
-rw-r--r--include/asm-powerpc/mpc52xx.h287
-rw-r--r--include/asm-powerpc/mpc85xx.h8
-rw-r--r--include/asm-powerpc/paca.h3
-rw-r--r--include/asm-powerpc/pci.h2
-rw-r--r--include/asm-powerpc/processor.h4
-rw-r--r--include/asm-powerpc/prom.h15
-rw-r--r--include/asm-powerpc/spu.h19
-rw-r--r--include/asm-powerpc/spu_csa.h1
-rw-r--r--include/asm-powerpc/spu_priv1.h6
-rw-r--r--include/asm-powerpc/todc.h487
-rw-r--r--include/asm-powerpc/xmon.h2
-rw-r--r--include/asm-ppc/io.h8
-rw-r--r--include/asm-ppc/mpc52xx.h11
-rw-r--r--include/asm-ppc/mpc83xx.h8
-rw-r--r--include/asm-ppc/mpc85xx.h8
-rw-r--r--include/linux/cpu.h8
20 files changed, 355 insertions, 593 deletions
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index d40359204aba..c4a1ab608f6f 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -7,16 +7,30 @@
7#ifdef __KERNEL__ 7#ifdef __KERNEL__
8 8
9#include <linux/errno.h> 9#include <linux/errno.h>
10#include <linux/compiler.h>
10#include <asm/ptrace.h> 11#include <asm/ptrace.h>
11#include <asm/processor.h> 12#include <asm/processor.h>
12 13
13extern void timer_interrupt(struct pt_regs *); 14extern void timer_interrupt(struct pt_regs *);
14 15
15#ifdef CONFIG_PPC_ISERIES 16#ifdef CONFIG_PPC64
17#include <asm/paca.h>
18
19static inline unsigned long local_get_flags(void)
20{
21 return get_paca()->soft_enabled;
22}
23
24static inline unsigned long local_irq_disable(void)
25{
26 unsigned long flag = get_paca()->soft_enabled;
27 get_paca()->soft_enabled = 0;
28 barrier();
29 return flag;
30}
16 31
17extern unsigned long local_get_flags(void);
18extern unsigned long local_irq_disable(void);
19extern void local_irq_restore(unsigned long); 32extern void local_irq_restore(unsigned long);
33extern void iseries_handle_interrupts(void);
20 34
21#define local_irq_enable() local_irq_restore(1) 35#define local_irq_enable() local_irq_restore(1)
22#define local_save_flags(flags) ((flags) = local_get_flags()) 36#define local_save_flags(flags) ((flags) = local_get_flags())
@@ -24,17 +38,14 @@ extern void local_irq_restore(unsigned long);
24 38
25#define irqs_disabled() (local_get_flags() == 0) 39#define irqs_disabled() (local_get_flags() == 0)
26 40
41#define hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
42#define hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
43
27#else 44#else
28 45
29#if defined(CONFIG_BOOKE) 46#if defined(CONFIG_BOOKE)
30#define SET_MSR_EE(x) mtmsr(x) 47#define SET_MSR_EE(x) mtmsr(x)
31#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") 48#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
32#elif defined(__powerpc64__)
33#define SET_MSR_EE(x) __mtmsrd(x, 1)
34#define local_irq_restore(flags) do { \
35 __asm__ __volatile__("": : :"memory"); \
36 __mtmsrd((flags), 1); \
37} while(0)
38#else 49#else
39#define SET_MSR_EE(x) mtmsr(x) 50#define SET_MSR_EE(x) mtmsr(x)
40#define local_irq_restore(flags) mtmsr(flags) 51#define local_irq_restore(flags) mtmsr(flags)
@@ -81,7 +92,7 @@ static inline void local_irq_save_ptr(unsigned long *flags)
81#define local_irq_save(flags) local_irq_save_ptr(&flags) 92#define local_irq_save(flags) local_irq_save_ptr(&flags)
82#define irqs_disabled() ((mfmsr() & MSR_EE) == 0) 93#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
83 94
84#endif /* CONFIG_PPC_ISERIES */ 95#endif /* CONFIG_PPC64 */
85 96
86#define mask_irq(irq) \ 97#define mask_irq(irq) \
87 ({ \ 98 ({ \
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index ce12f85fff9b..9fdd0491f6a3 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -136,22 +136,7 @@ struct qe_timers {
136 136
137/* BRG */ 137/* BRG */
138struct qe_brg { 138struct qe_brg {
139 __be32 brgc1; /* BRG1 configuration register */ 139 __be32 brgc[16]; /* BRG configuration registers */
140 __be32 brgc2; /* BRG2 configuration register */
141 __be32 brgc3; /* BRG3 configuration register */
142 __be32 brgc4; /* BRG4 configuration register */
143 __be32 brgc5; /* BRG5 configuration register */
144 __be32 brgc6; /* BRG6 configuration register */
145 __be32 brgc7; /* BRG7 configuration register */
146 __be32 brgc8; /* BRG8 configuration register */
147 __be32 brgc9; /* BRG9 configuration register */
148 __be32 brgc10; /* BRG10 configuration register */
149 __be32 brgc11; /* BRG11 configuration register */
150 __be32 brgc12; /* BRG12 configuration register */
151 __be32 brgc13; /* BRG13 configuration register */
152 __be32 brgc14; /* BRG14 configuration register */
153 __be32 brgc15; /* BRG15 configuration register */
154 __be32 brgc16; /* BRG16 configuration register */
155 u8 res0[0x40]; 140 u8 res0[0x40];
156} __attribute__ ((packed)); 141} __attribute__ ((packed));
157 142
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 39fad685ffab..19e6f7e0a607 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -70,17 +70,9 @@ struct iommu_table {
70struct scatterlist; 70struct scatterlist;
71struct device_node; 71struct device_node;
72 72
73#ifdef CONFIG_PPC_MULTIPLATFORM
74
75/* Walks all buses and creates iommu tables */
76extern void iommu_setup_pSeries(void);
77extern void iommu_setup_dart(void);
78
79/* Frees table for an individual device node */ 73/* Frees table for an individual device node */
80extern void iommu_free_table(struct device_node *dn); 74extern void iommu_free_table(struct device_node *dn);
81 75
82#endif /* CONFIG_PPC_MULTIPLATFORM */
83
84/* Initializes an iommu_table based in values set in the passed-in 76/* Initializes an iommu_table based in values set in the passed-in
85 * structure 77 * structure
86 */ 78 */
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index c3fc7a28e3cd..41c8c9c5a254 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -248,21 +248,6 @@ extern void hpte_init_native(void);
248extern void hpte_init_lpar(void); 248extern void hpte_init_lpar(void);
249extern void hpte_init_iSeries(void); 249extern void hpte_init_iSeries(void);
250 250
251extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
252 unsigned long va, unsigned long prpn,
253 unsigned long rflags,
254 unsigned long vflags, int psize);
255
256extern long native_hpte_insert(unsigned long hpte_group,
257 unsigned long va, unsigned long prpn,
258 unsigned long rflags,
259 unsigned long vflags, int psize);
260
261extern long iSeries_hpte_insert(unsigned long hpte_group,
262 unsigned long va, unsigned long prpn,
263 unsigned long rflags,
264 unsigned long vflags, int psize);
265
266extern void stabs_alloc(void); 251extern void stabs_alloc(void);
267extern void slb_initialize(void); 252extern void slb_initialize(void);
268extern void slb_flush_and_rebolt(void); 253extern void slb_flush_and_rebolt(void);
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
new file mode 100644
index 000000000000..e9aa622f19f6
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx.h
@@ -0,0 +1,287 @@
1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21
22/* ======================================================================== */
23/* HW IRQ mapping */
24/* ======================================================================== */
25
26#define MPC52xx_IRQ_L1_CRIT (0)
27#define MPC52xx_IRQ_L1_MAIN (1)
28#define MPC52xx_IRQ_L1_PERP (2)
29#define MPC52xx_IRQ_L1_SDMA (3)
30
31#define MPC52xx_IRQ_L1_OFFSET (6)
32#define MPC52xx_IRQ_L1_MASK (0xc0)
33
34#define MPC52xx_IRQ_L2_OFFSET (0)
35#define MPC52xx_IRQ_L2_MASK (0x3f)
36
37#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
38
39
40/* ======================================================================== */
41/* Structures mapping of some unit register set */
42/* ======================================================================== */
43
44#ifndef __ASSEMBLY__
45
46/* Interrupt controller Register set */
47struct mpc52xx_intr {
48 u32 per_mask; /* INTR + 0x00 */
49 u32 per_pri1; /* INTR + 0x04 */
50 u32 per_pri2; /* INTR + 0x08 */
51 u32 per_pri3; /* INTR + 0x0c */
52 u32 ctrl; /* INTR + 0x10 */
53 u32 main_mask; /* INTR + 0x14 */
54 u32 main_pri1; /* INTR + 0x18 */
55 u32 main_pri2; /* INTR + 0x1c */
56 u32 reserved1; /* INTR + 0x20 */
57 u32 enc_status; /* INTR + 0x24 */
58 u32 crit_status; /* INTR + 0x28 */
59 u32 main_status; /* INTR + 0x2c */
60 u32 per_status; /* INTR + 0x30 */
61 u32 reserved2; /* INTR + 0x34 */
62 u32 per_error; /* INTR + 0x38 */
63};
64
65/* Memory Mapping Control */
66struct mpc52xx_mmap_ctl {
67 u32 mbar; /* MMAP_CTRL + 0x00 */
68
69 u32 cs0_start; /* MMAP_CTRL + 0x04 */
70 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
71 u32 cs1_start; /* MMAP_CTRL + 0x0c */
72 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
73 u32 cs2_start; /* MMAP_CTRL + 0x14 */
74 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
75 u32 cs3_start; /* MMAP_CTRL + 0x1c */
76 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
77 u32 cs4_start; /* MMAP_CTRL + 0x24 */
78 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
79 u32 cs5_start; /* MMAP_CTRL + 0x2c */
80 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
81
82 u32 sdram0; /* MMAP_CTRL + 0x34 */
83 u32 sdram1; /* MMAP_CTRL + 0X38 */
84
85 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
86
87 u32 boot_start; /* MMAP_CTRL + 0x4c */
88 u32 boot_stop; /* MMAP_CTRL + 0x50 */
89
90 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
91
92 u32 cs6_start; /* MMAP_CTRL + 0x58 */
93 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
94 u32 cs7_start; /* MMAP_CTRL + 0x60 */
95 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
96};
97
98/* SDRAM control */
99struct mpc52xx_sdram {
100 u32 mode; /* SDRAM + 0x00 */
101 u32 ctrl; /* SDRAM + 0x04 */
102 u32 config1; /* SDRAM + 0x08 */
103 u32 config2; /* SDRAM + 0x0c */
104};
105
106/* SDMA */
107struct mpc52xx_sdma {
108 u32 taskBar; /* SDMA + 0x00 */
109 u32 currentPointer; /* SDMA + 0x04 */
110 u32 endPointer; /* SDMA + 0x08 */
111 u32 variablePointer; /* SDMA + 0x0c */
112
113 u8 IntVect1; /* SDMA + 0x10 */
114 u8 IntVect2; /* SDMA + 0x11 */
115 u16 PtdCntrl; /* SDMA + 0x12 */
116
117 u32 IntPend; /* SDMA + 0x14 */
118 u32 IntMask; /* SDMA + 0x18 */
119
120 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
121
122 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
123
124 u32 cReqSelect; /* SDMA + 0x5c */
125 u32 task_size0; /* SDMA + 0x60 */
126 u32 task_size1; /* SDMA + 0x64 */
127 u32 MDEDebug; /* SDMA + 0x68 */
128 u32 ADSDebug; /* SDMA + 0x6c */
129 u32 Value1; /* SDMA + 0x70 */
130 u32 Value2; /* SDMA + 0x74 */
131 u32 Control; /* SDMA + 0x78 */
132 u32 Status; /* SDMA + 0x7c */
133 u32 PTDDebug; /* SDMA + 0x80 */
134};
135
136/* GPT */
137struct mpc52xx_gpt {
138 u32 mode; /* GPTx + 0x00 */
139 u32 count; /* GPTx + 0x04 */
140 u32 pwm; /* GPTx + 0x08 */
141 u32 status; /* GPTx + 0X0c */
142};
143
144/* GPIO */
145struct mpc52xx_gpio {
146 u32 port_config; /* GPIO + 0x00 */
147 u32 simple_gpioe; /* GPIO + 0x04 */
148 u32 simple_ode; /* GPIO + 0x08 */
149 u32 simple_ddr; /* GPIO + 0x0c */
150 u32 simple_dvo; /* GPIO + 0x10 */
151 u32 simple_ival; /* GPIO + 0x14 */
152 u8 outo_gpioe; /* GPIO + 0x18 */
153 u8 reserved1[3]; /* GPIO + 0x19 */
154 u8 outo_dvo; /* GPIO + 0x1c */
155 u8 reserved2[3]; /* GPIO + 0x1d */
156 u8 sint_gpioe; /* GPIO + 0x20 */
157 u8 reserved3[3]; /* GPIO + 0x21 */
158 u8 sint_ode; /* GPIO + 0x24 */
159 u8 reserved4[3]; /* GPIO + 0x25 */
160 u8 sint_ddr; /* GPIO + 0x28 */
161 u8 reserved5[3]; /* GPIO + 0x29 */
162 u8 sint_dvo; /* GPIO + 0x2c */
163 u8 reserved6[3]; /* GPIO + 0x2d */
164 u8 sint_inten; /* GPIO + 0x30 */
165 u8 reserved7[3]; /* GPIO + 0x31 */
166 u16 sint_itype; /* GPIO + 0x34 */
167 u16 reserved8; /* GPIO + 0x36 */
168 u8 gpio_control; /* GPIO + 0x38 */
169 u8 reserved9[3]; /* GPIO + 0x39 */
170 u8 sint_istat; /* GPIO + 0x3c */
171 u8 sint_ival; /* GPIO + 0x3d */
172 u8 bus_errs; /* GPIO + 0x3e */
173 u8 reserved10; /* GPIO + 0x3f */
174};
175
176#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
177#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
178#define MPC52xx_GPIO_PCI_DIS (1<<15)
179
180/* GPIO with WakeUp*/
181struct mpc52xx_gpio_wkup {
182 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
183 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
184 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
185 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
186 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
187 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
188 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
189 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
190 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
191 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
192 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
193 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
194 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
195 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
196 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
197 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
198 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
199 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
200 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
201 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
202};
203
204/* XLB Bus control */
205struct mpc52xx_xlb {
206 u8 reserved[0x40];
207 u32 config; /* XLB + 0x40 */
208 u32 version; /* XLB + 0x44 */
209 u32 status; /* XLB + 0x48 */
210 u32 int_enable; /* XLB + 0x4c */
211 u32 addr_capture; /* XLB + 0x50 */
212 u32 bus_sig_capture; /* XLB + 0x54 */
213 u32 addr_timeout; /* XLB + 0x58 */
214 u32 data_timeout; /* XLB + 0x5c */
215 u32 bus_act_timeout; /* XLB + 0x60 */
216 u32 master_pri_enable; /* XLB + 0x64 */
217 u32 master_priority; /* XLB + 0x68 */
218 u32 base_address; /* XLB + 0x6c */
219 u32 snoop_window; /* XLB + 0x70 */
220};
221
222#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
223#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
224
225/* Clock Distribution control */
226struct mpc52xx_cdm {
227 u32 jtag_id; /* CDM + 0x00 reg0 read only */
228 u32 rstcfg; /* CDM + 0x04 reg1 read only */
229 u32 breadcrumb; /* CDM + 0x08 reg2 */
230
231 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
232 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
233 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
234 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
235
236 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
237 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
238 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
239
240 u32 clk_enables; /* CDM + 0x14 reg5 */
241
242 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
243 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
244
245 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
246 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
247 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
248 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
249
250 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
251 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
252 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
253
254 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
255 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
256 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
257 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
258
259 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
260 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
261
262 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
263 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
264
265 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
266 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
267
268 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
269 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
270};
271
272#endif /* __ASSEMBLY__ */
273
274
275/* ========================================================================= */
276/* Prototypes for MPC52xx sysdev */
277/* ========================================================================= */
278
279#ifndef __ASSEMBLY__
280
281extern void mpc52xx_init_irq(void);
282extern unsigned int mpc52xx_get_irq(void);
283
284#endif /* __ASSEMBLY__ */
285
286#endif /* __ASM_POWERPC_MPC52xx_H__ */
287
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
index ccdb8a21138f..54142997a584 100644
--- a/include/asm-powerpc/mpc85xx.h
+++ b/include/asm-powerpc/mpc85xx.h
@@ -31,14 +31,6 @@
31#include <platforms/85xx/mpc85xx_cds.h> 31#include <platforms/85xx/mpc85xx_cds.h>
32#endif 32#endif
33 33
34#define _IO_BASE isa_io_base
35#define _ISA_MEM_BASE isa_mem_base
36#ifdef CONFIG_PCI
37#define PCI_DRAM_OFFSET pci_dram_offset
38#else
39#define PCI_DRAM_OFFSET 0
40#endif
41
42/* Let modules/drivers get at CCSRBAR */ 34/* Let modules/drivers get at CCSRBAR */
43extern phys_addr_t get_ccsrbar(void); 35extern phys_addr_t get_ccsrbar(void);
44 36
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 0a4e5c93e8e6..0d3adc09c847 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -93,7 +93,8 @@ struct paca_struct {
93 u64 stab_rr; /* stab/slb round-robin counter */ 93 u64 stab_rr; /* stab/slb round-robin counter */
94 u64 saved_r1; /* r1 save for RTAS calls */ 94 u64 saved_r1; /* r1 save for RTAS calls */
95 u64 saved_msr; /* MSR saved here by enter_rtas */ 95 u64 saved_msr; /* MSR saved here by enter_rtas */
96 u8 proc_enabled; /* irq soft-enable flag */ 96 u8 soft_enabled; /* irq soft-enable flag */
97 u8 hard_enabled; /* set if irqs are enabled in MSR */
97 u8 io_sync; /* writel() needs spin_unlock sync */ 98 u8 io_sync; /* writel() needs spin_unlock sync */
98 99
99 /* Stuff for accurate time accounting */ 100 /* Stuff for accurate time accounting */
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 721c97f09b20..c77286051496 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -232,12 +232,10 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
232 unsigned long size, 232 unsigned long size,
233 pgprot_t prot); 233 pgprot_t prot);
234 234
235#if defined(CONFIG_PPC_MULTIPLATFORM) || defined(CONFIG_PPC32)
236#define HAVE_ARCH_PCI_RESOURCE_TO_USER 235#define HAVE_ARCH_PCI_RESOURCE_TO_USER
237extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 236extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
238 const struct resource *rsrc, 237 const struct resource *rsrc,
239 resource_size_t *start, resource_size_t *end); 238 resource_size_t *start, resource_size_t *end);
240#endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
241 239
242#endif /* __KERNEL__ */ 240#endif /* __KERNEL__ */
243#endif /* __ASM_POWERPC_PCI_H */ 241#endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index 6cb6fb19e57f..a26c32ee5527 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -53,10 +53,6 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
53 53
54#endif /* CONFIG_PPC_PREP */ 54#endif /* CONFIG_PPC_PREP */
55 55
56#ifndef CONFIG_PPC_MULTIPLATFORM
57#define _machine 0
58#endif /* CONFIG_PPC_MULTIPLATFORM */
59
60#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 56#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
61 57
62/* 58/*
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index ec11d44eaeb5..0afee17f33b4 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -17,6 +17,7 @@
17 */ 17 */
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/proc_fs.h> 19#include <linux/proc_fs.h>
20#include <linux/platform_device.h>
20#include <asm/atomic.h> 21#include <asm/atomic.h>
21 22
22/* Definitions used by the flattened device tree */ 23/* Definitions used by the flattened device tree */
@@ -333,6 +334,20 @@ extern int of_irq_map_one(struct device_node *device, int index,
333struct pci_dev; 334struct pci_dev;
334extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq); 335extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
335 336
337static inline int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
338{
339 int irq = irq_of_parse_and_map(dev, index);
340
341 /* Only dereference the resource if both the
342 * resource and the irq are valid. */
343 if (r && irq != NO_IRQ) {
344 r->start = r->end = irq;
345 r->flags = IORESOURCE_IRQ;
346 }
347
348 return irq;
349}
350
336 351
337#endif /* __KERNEL__ */ 352#endif /* __KERNEL__ */
338#endif /* _POWERPC_PROM_H */ 353#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index e73ea00efd8b..ffa4df083609 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -115,10 +115,10 @@ struct spu {
115 struct spu_priv2 __iomem *priv2; 115 struct spu_priv2 __iomem *priv2;
116 struct list_head list; 116 struct list_head list;
117 struct list_head sched_list; 117 struct list_head sched_list;
118 struct list_head full_list;
118 int number; 119 int number;
119 int nid; 120 int nid;
120 unsigned int irqs[3]; 121 unsigned int irqs[3];
121 u32 isrc;
122 u32 node; 122 u32 node;
123 u64 flags; 123 u64 flags;
124 u64 dar; 124 u64 dar;
@@ -144,6 +144,8 @@ struct spu {
144 char irq_c1[8]; 144 char irq_c1[8];
145 char irq_c2[8]; 145 char irq_c2[8];
146 146
147 struct device_node *devnode;
148
147 struct sys_device sysdev; 149 struct sys_device sysdev;
148}; 150};
149 151
@@ -182,8 +184,10 @@ extern struct spufs_calls {
182 */ 184 */
183#define SPU_CREATE_EVENTS_ENABLED 0x0001 185#define SPU_CREATE_EVENTS_ENABLED 0x0001
184#define SPU_CREATE_GANG 0x0002 186#define SPU_CREATE_GANG 0x0002
187#define SPU_CREATE_NOSCHED 0x0004
188#define SPU_CREATE_ISOLATE 0x0008
185 189
186#define SPU_CREATE_FLAG_ALL 0x0003 /* mask of all valid flags */ 190#define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */
187 191
188 192
189#ifdef CONFIG_SPU_FS_MODULE 193#ifdef CONFIG_SPU_FS_MODULE
@@ -199,6 +203,12 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
199} 203}
200#endif /* MODULE */ 204#endif /* MODULE */
201 205
206int spu_add_sysdev_attr(struct sysdev_attribute *attr);
207void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
208
209int spu_add_sysdev_attr_group(struct attribute_group *attrs);
210void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
211
202 212
203/* 213/*
204 * Notifier blocks: 214 * Notifier blocks:
@@ -277,6 +287,7 @@ struct spu_problem {
277 u32 spu_runcntl_RW; /* 0x401c */ 287 u32 spu_runcntl_RW; /* 0x401c */
278#define SPU_RUNCNTL_STOP 0L 288#define SPU_RUNCNTL_STOP 0L
279#define SPU_RUNCNTL_RUNNABLE 1L 289#define SPU_RUNCNTL_RUNNABLE 1L
290#define SPU_RUNCNTL_ISOLATE 2L
280 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */ 291 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
281 u32 spu_status_R; /* 0x4024 */ 292 u32 spu_status_R; /* 0x4024 */
282#define SPU_STOP_STATUS_SHIFT 16 293#define SPU_STOP_STATUS_SHIFT 16
@@ -289,8 +300,8 @@ struct spu_problem {
289#define SPU_STATUS_INVALID_INSTR 0x20 300#define SPU_STATUS_INVALID_INSTR 0x20
290#define SPU_STATUS_INVALID_CH 0x40 301#define SPU_STATUS_INVALID_CH 0x40
291#define SPU_STATUS_ISOLATED_STATE 0x80 302#define SPU_STATUS_ISOLATED_STATE 0x80
292#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200 303#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
293#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400 304#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
294 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */ 305 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
295 u32 spu_spe_R; /* 0x402c */ 306 u32 spu_spe_R; /* 0x402c */
296 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */ 307 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index 964c2d38ccb7..bdbf906a767f 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -151,7 +151,6 @@ struct spu_priv1_collapsed {
151 u64 mfc_fir_chkstp_enable_RW; 151 u64 mfc_fir_chkstp_enable_RW;
152 u64 smf_sbi_signal_sel; 152 u64 smf_sbi_signal_sel;
153 u64 smf_ato_signal_sel; 153 u64 smf_ato_signal_sel;
154 u64 mfc_sdr_RW;
155 u64 tlb_index_hint_RO; 154 u64 tlb_index_hint_RO;
156 u64 tlb_index_W; 155 u64 tlb_index_W;
157 u64 tlb_vpn_RW; 156 u64 tlb_vpn_RW;
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 300c458b6d06..4f9a04db99f7 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -37,7 +37,7 @@ struct spu_priv1_ops
37 u64 (*mfc_dar_get) (struct spu *spu); 37 u64 (*mfc_dar_get) (struct spu *spu);
38 u64 (*mfc_dsisr_get) (struct spu *spu); 38 u64 (*mfc_dsisr_get) (struct spu *spu);
39 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr); 39 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
40 void (*mfc_sdr_set) (struct spu *spu, u64 sdr); 40 void (*mfc_sdr_setup) (struct spu *spu);
41 void (*mfc_sr1_set) (struct spu *spu, u64 sr1); 41 void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
42 u64 (*mfc_sr1_get) (struct spu *spu); 42 u64 (*mfc_sr1_get) (struct spu *spu);
43 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id); 43 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
@@ -112,9 +112,9 @@ spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
112} 112}
113 113
114static inline void 114static inline void
115spu_mfc_sdr_set (struct spu *spu, u64 sdr) 115spu_mfc_sdr_setup (struct spu *spu)
116{ 116{
117 spu_priv1_ops->mfc_sdr_set(spu, sdr); 117 spu_priv1_ops->mfc_sdr_setup(spu);
118} 118}
119 119
120static inline void 120static inline void
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
deleted file mode 100644
index 60a8c39b8c11..000000000000
--- a/include/asm-powerpc/todc.h
+++ /dev/null
@@ -1,487 +0,0 @@
1/*
2 * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
3 * Clock chips.
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
15 * Purpose is to make one generic file that handles all of these chips instead
16 * of every platform implementing the same code over & over again.
17 */
18
19#ifndef __PPC_KERNEL_TODC_H
20#define __PPC_KERNEL_TODC_H
21
22typedef struct {
23 uint rtc_type; /* your particular chip */
24
25 /*
26 * Following are the addresses of the AS0, AS1, and DATA registers
27 * of these chips. Note that these are board-specific.
28 */
29 unsigned int nvram_as0;
30 unsigned int nvram_as1;
31 unsigned int nvram_data;
32
33 /*
34 * Define bits to stop external set of regs from changing so
35 * the chip can be read/written reliably.
36 */
37 unsigned char enable_read;
38 unsigned char enable_write;
39
40 /*
41 * Following is the number of AS0 address bits. This is normally
42 * 8 but some bad hardware routes address lines incorrectly.
43 */
44 int as0_bits;
45
46 int nvram_size; /* Size of NVRAM on chip */
47 int sw_flags; /* Software control flags */
48
49 /* Following are the register offsets for the particular chip */
50 int year;
51 int month;
52 int day_of_month;
53 int day_of_week;
54 int hours;
55 int minutes;
56 int seconds;
57 int control_b;
58 int control_a;
59 int watchdog;
60 int interrupts;
61 int alarm_date;
62 int alarm_hour;
63 int alarm_minutes;
64 int alarm_seconds;
65 int century;
66 int flags;
67
68 /*
69 * Some RTC chips have their NVRAM buried behind a addr/data pair of
70 * regs on the first level/clock registers. The following fields
71 * are the addresses for those addr/data regs.
72 */
73 int nvram_addr_reg;
74 int nvram_data_reg;
75} todc_info_t;
76
77/*
78 * Define the types of TODC/RTC variants that are supported in
79 * arch/ppc/kernel/todc_time.c
80 * Make a new one of these for any chip somehow differs from what's already
81 * defined. That way, if you ever need to put in code to touch those
82 * bits/registers in todc_time.c, you can put it inside an
83 * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
84 * anyone else.
85 */
86#define TODC_TYPE_MK48T35 1
87#define TODC_TYPE_MK48T37 2
88#define TODC_TYPE_MK48T59 3
89#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
90#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
91#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
92#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
93#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
94#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
95#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
96#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
97#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
98#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
99#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
100
101/*
102 * Bit to clear/set to enable reads/writes to the chip
103 */
104#define TODC_MK48TXX_CNTL_A_R 0x40
105#define TODC_MK48TXX_CNTL_A_W 0x80
106#define TODC_MK48TXX_DAY_CB 0x80
107
108#define TODC_DS1501_CNTL_B_TE 0x80
109
110/*
111 * Define flag bits used by todc routines.
112 */
113#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
114
115/*
116 * Define the values for the various RTC's that should to into the todc_info
117 * table.
118 * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
119 * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
120 */
121#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
122#define TODC_TYPE_MK48T35_SW_FLAGS 0
123#define TODC_TYPE_MK48T35_YEAR 0x7fff
124#define TODC_TYPE_MK48T35_MONTH 0x7ffe
125#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
126#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
127#define TODC_TYPE_MK48T35_HOURS 0x7ffb
128#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
129#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
130#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
131#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
132#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
133#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
134#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
135#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
136#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
137#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
138#define TODC_TYPE_MK48T35_CENTURY 0x0000
139#define TODC_TYPE_MK48T35_FLAGS 0x0000
140#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
141#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
142
143#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
144#define TODC_TYPE_MK48T37_SW_FLAGS 0
145#define TODC_TYPE_MK48T37_YEAR 0x7fff
146#define TODC_TYPE_MK48T37_MONTH 0x7ffe
147#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
148#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
149#define TODC_TYPE_MK48T37_HOURS 0x7ffb
150#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
151#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
152#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
153#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
154#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
155#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
156#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
157#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
158#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
159#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
160#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
161#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
162#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
163#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
164
165#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
166#define TODC_TYPE_MK48T59_SW_FLAGS 0
167#define TODC_TYPE_MK48T59_YEAR 0x1fff
168#define TODC_TYPE_MK48T59_MONTH 0x1ffe
169#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
170#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
171#define TODC_TYPE_MK48T59_HOURS 0x1ffb
172#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
173#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
174#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
175#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
176#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
177#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
178#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
179#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
180#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
181#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
182#define TODC_TYPE_MK48T59_CENTURY 0x1fff
183#define TODC_TYPE_MK48T59_FLAGS 0x1fff
184#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
185#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
186
187#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
188#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
189#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
190#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
191#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
192#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
193#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
194#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
195#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
196#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
197#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
198#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
199#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
200#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
201#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
202#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
203#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
204#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
205#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
206#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
207#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
208
209#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
210#define TODC_TYPE_DS1553_SW_FLAGS 0
211#define TODC_TYPE_DS1553_YEAR 0x1fff
212#define TODC_TYPE_DS1553_MONTH 0x1ffe
213#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
214#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
215#define TODC_TYPE_DS1553_HOURS 0x1ffb
216#define TODC_TYPE_DS1553_MINUTES 0x1ffa
217#define TODC_TYPE_DS1553_SECONDS 0x1ff9
218#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
219#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
220#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
221#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
222#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
223#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
224#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
225#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
226#define TODC_TYPE_DS1553_CENTURY 0x1ff8
227#define TODC_TYPE_DS1553_FLAGS 0x1ff0
228#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
229#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
230
231#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
232#define TODC_TYPE_DS1557_SW_FLAGS 0
233#define TODC_TYPE_DS1557_YEAR 0x7ffff
234#define TODC_TYPE_DS1557_MONTH 0x7fffe
235#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
236#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
237#define TODC_TYPE_DS1557_HOURS 0x7fffb
238#define TODC_TYPE_DS1557_MINUTES 0x7fffa
239#define TODC_TYPE_DS1557_SECONDS 0x7fff9
240#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
241#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
242#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
243#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
244#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
245#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
246#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
247#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
248#define TODC_TYPE_DS1557_CENTURY 0x7fff8
249#define TODC_TYPE_DS1557_FLAGS 0x7fff0
250#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
251#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
252
253#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
254#define TODC_TYPE_DS1643_SW_FLAGS 0
255#define TODC_TYPE_DS1643_YEAR 0x1fff
256#define TODC_TYPE_DS1643_MONTH 0x1ffe
257#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
258#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
259#define TODC_TYPE_DS1643_HOURS 0x1ffb
260#define TODC_TYPE_DS1643_MINUTES 0x1ffa
261#define TODC_TYPE_DS1643_SECONDS 0x1ff9
262#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
263#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
264#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
265#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
266#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
267#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
268#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
269#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
270#define TODC_TYPE_DS1643_CENTURY 0x1ff8
271#define TODC_TYPE_DS1643_FLAGS 0x1fff
272#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
273#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
274
275#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
276#define TODC_TYPE_DS1693_SW_FLAGS 0
277#define TODC_TYPE_DS1693_YEAR 0x09
278#define TODC_TYPE_DS1693_MONTH 0x08
279#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
280#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
281#define TODC_TYPE_DS1693_HOURS 0x04
282#define TODC_TYPE_DS1693_MINUTES 0x02
283#define TODC_TYPE_DS1693_SECONDS 0x00
284#define TODC_TYPE_DS1693_CNTL_B 0x0b
285#define TODC_TYPE_DS1693_CNTL_A 0x0a
286#define TODC_TYPE_DS1693_WATCHDOG 0xff
287#define TODC_TYPE_DS1693_INTERRUPTS 0xff
288#define TODC_TYPE_DS1693_ALARM_DATE 0x49
289#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
290#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
291#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
292#define TODC_TYPE_DS1693_CENTURY 0x48
293#define TODC_TYPE_DS1693_FLAGS 0xff
294#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
295#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
296
297#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
298#define TODC_TYPE_DS1743_SW_FLAGS 0
299#define TODC_TYPE_DS1743_YEAR 0x1fff
300#define TODC_TYPE_DS1743_MONTH 0x1ffe
301#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
302#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
303#define TODC_TYPE_DS1743_HOURS 0x1ffb
304#define TODC_TYPE_DS1743_MINUTES 0x1ffa
305#define TODC_TYPE_DS1743_SECONDS 0x1ff9
306#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
307#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
308#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
309#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
310#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
311#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
312#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
313#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
314#define TODC_TYPE_DS1743_CENTURY 0x1ff8
315#define TODC_TYPE_DS1743_FLAGS 0x1fff
316#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
317#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
318
319#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
320#define TODC_TYPE_DS1746_SW_FLAGS 0
321#define TODC_TYPE_DS1746_YEAR 0x1ffff
322#define TODC_TYPE_DS1746_MONTH 0x1fffe
323#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
324#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
325#define TODC_TYPE_DS1746_HOURS 0x1fffb
326#define TODC_TYPE_DS1746_MINUTES 0x1fffa
327#define TODC_TYPE_DS1746_SECONDS 0x1fff9
328#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
329#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
330#define TODC_TYPE_DS1746_WATCHDOG 0x00000
331#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
332#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
333#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
334#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
335#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
336#define TODC_TYPE_DS1746_CENTURY 0x00000
337#define TODC_TYPE_DS1746_FLAGS 0x00000
338#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
339#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
340
341#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
342#define TODC_TYPE_DS1747_SW_FLAGS 0
343#define TODC_TYPE_DS1747_YEAR 0x7ffff
344#define TODC_TYPE_DS1747_MONTH 0x7fffe
345#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
346#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
347#define TODC_TYPE_DS1747_HOURS 0x7fffb
348#define TODC_TYPE_DS1747_MINUTES 0x7fffa
349#define TODC_TYPE_DS1747_SECONDS 0x7fff9
350#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
351#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
352#define TODC_TYPE_DS1747_WATCHDOG 0x00000
353#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
354#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
355#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
356#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
357#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
358#define TODC_TYPE_DS1747_CENTURY 0x00000
359#define TODC_TYPE_DS1747_FLAGS 0x00000
360#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
361#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
362
363#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
364#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
365#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
366#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
367#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
368#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
369#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
370#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
371#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
372#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
373#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
374#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
375#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
376#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
377#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
378#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
379#define TODC_TYPE_DS17285_WATCHDOG 0
380#define TODC_TYPE_DS17285_INTERRUPTS 0
381#define TODC_TYPE_DS17285_ALARM_DATE 0
382#define TODC_TYPE_DS17285_CENTURY 0
383#define TODC_TYPE_DS17285_FLAGS 0
384#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
385#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
386
387#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
388#define TODC_TYPE_MC146818_SW_FLAGS 0
389#define TODC_TYPE_MC146818_YEAR 0x09
390#define TODC_TYPE_MC146818_MONTH 0x08
391#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
392#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
393#define TODC_TYPE_MC146818_HOURS 0x04
394#define TODC_TYPE_MC146818_MINUTES 0x02
395#define TODC_TYPE_MC146818_SECONDS 0x00
396#define TODC_TYPE_MC146818_CNTL_B 0x0a
397#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
398#define TODC_TYPE_MC146818_WATCHDOG 0
399#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
400#define TODC_TYPE_MC146818_ALARM_DATE 0xff
401#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
402#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
403#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
404#define TODC_TYPE_MC146818_CENTURY 0xff
405#define TODC_TYPE_MC146818_FLAGS 0xff
406#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
407#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
408
409#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
410#define TODC_TYPE_PC97307_SW_FLAGS 0
411#define TODC_TYPE_PC97307_YEAR 0x09
412#define TODC_TYPE_PC97307_MONTH 0x08
413#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
414#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
415#define TODC_TYPE_PC97307_HOURS 0x04
416#define TODC_TYPE_PC97307_MINUTES 0x02
417#define TODC_TYPE_PC97307_SECONDS 0x00
418#define TODC_TYPE_PC97307_CNTL_B 0x0a
419#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
420#define TODC_TYPE_PC97307_WATCHDOG 0x0c
421#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
422#define TODC_TYPE_PC97307_ALARM_DATE 0xff
423#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
424#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
425#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
426#define TODC_TYPE_PC97307_CENTURY 0xff
427#define TODC_TYPE_PC97307_FLAGS 0xff
428#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
429#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
430
431/*
432 * Define macros to allocate and init the todc_info_t table that will
433 * be used by the todc_time.c routines.
434 */
435#define TODC_ALLOC() \
436 static todc_info_t todc_info_alloc; \
437 todc_info_t *todc_info = &todc_info_alloc;
438
439#define TODC_INIT(clock_type, as0, as1, data, bits) { \
440 todc_info->rtc_type = clock_type; \
441 \
442 todc_info->nvram_as0 = (unsigned int)(as0); \
443 todc_info->nvram_as1 = (unsigned int)(as1); \
444 todc_info->nvram_data = (unsigned int)(data); \
445 \
446 todc_info->as0_bits = (bits); \
447 \
448 todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
449 todc_info->sw_flags = clock_type ##_SW_FLAGS; \
450 \
451 todc_info->year = clock_type ##_YEAR; \
452 todc_info->month = clock_type ##_MONTH; \
453 todc_info->day_of_month = clock_type ##_DOM; \
454 todc_info->day_of_week = clock_type ##_DOW; \
455 todc_info->hours = clock_type ##_HOURS; \
456 todc_info->minutes = clock_type ##_MINUTES; \
457 todc_info->seconds = clock_type ##_SECONDS; \
458 todc_info->control_b = clock_type ##_CNTL_B; \
459 todc_info->control_a = clock_type ##_CNTL_A; \
460 todc_info->watchdog = clock_type ##_WATCHDOG; \
461 todc_info->interrupts = clock_type ##_INTERRUPTS; \
462 todc_info->alarm_date = clock_type ##_ALARM_DATE; \
463 todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
464 todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
465 todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
466 todc_info->century = clock_type ##_CENTURY; \
467 todc_info->flags = clock_type ##_FLAGS; \
468 \
469 todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
470 todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
471}
472
473extern todc_info_t *todc_info;
474
475unsigned char todc_direct_read_val(int addr);
476void todc_direct_write_val(int addr, unsigned char val);
477unsigned char todc_m48txx_read_val(int addr);
478void todc_m48txx_write_val(int addr, unsigned char val);
479unsigned char todc_mc146818_read_val(int addr);
480void todc_mc146818_write_val(int addr, unsigned char val);
481
482long todc_time_init(void);
483void todc_get_rtc_time(struct rtc_time *);
484int todc_set_rtc_time(struct rtc_time *);
485void todc_calibrate_decr(void);
486
487#endif /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index f1d337ed68d5..88320a05f0a8 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -14,8 +14,10 @@
14 14
15#ifdef CONFIG_XMON 15#ifdef CONFIG_XMON
16extern void xmon_setup(void); 16extern void xmon_setup(void);
17extern void xmon_register_spus(struct list_head *list);
17#else 18#else
18static inline void xmon_setup(void) { }; 19static inline void xmon_setup(void) { };
20static inline void xmon_register_spus(struct list_head *list) { };
19#endif 21#endif
20 22
21#endif /* __KERNEL __ */ 23#endif /* __KERNEL __ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index a4c411b753ef..b744baf9e206 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -26,17 +26,11 @@
26 26
27#if defined(CONFIG_4xx) 27#if defined(CONFIG_4xx)
28#include <asm/ibm4xx.h> 28#include <asm/ibm4xx.h>
29#elif defined(CONFIG_PPC_MPC52xx)
30#include <asm/mpc52xx.h>
31#elif defined(CONFIG_8xx) 29#elif defined(CONFIG_8xx)
32#include <asm/mpc8xx.h> 30#include <asm/mpc8xx.h>
33#elif defined(CONFIG_8260) 31#elif defined(CONFIG_8260)
34#include <asm/mpc8260.h> 32#include <asm/mpc8260.h>
35#elif defined(CONFIG_83xx) 33#elif defined(CONFIG_APUS) || !defined(CONFIG_PCI)
36#include <asm/mpc83xx.h>
37#elif defined(CONFIG_85xx)
38#include <asm/mpc85xx.h>
39#elif defined(CONFIG_APUS)
40#define _IO_BASE 0 34#define _IO_BASE 0
41#define _ISA_MEM_BASE 0 35#define _ISA_MEM_BASE 0
42#define PCI_DRAM_OFFSET 0 36#define PCI_DRAM_OFFSET 0
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
index 64c8874618dc..d9d21aa68ba3 100644
--- a/include/asm-ppc/mpc52xx.h
+++ b/include/asm-ppc/mpc52xx.h
@@ -29,17 +29,6 @@ struct pt_regs;
29#endif /* __ASSEMBLY__ */ 29#endif /* __ASSEMBLY__ */
30 30
31 31
32#ifdef CONFIG_PCI
33#define _IO_BASE isa_io_base
34#define _ISA_MEM_BASE isa_mem_base
35#define PCI_DRAM_OFFSET pci_dram_offset
36#else
37#define _IO_BASE 0
38#define _ISA_MEM_BASE 0
39#define PCI_DRAM_OFFSET 0
40#endif
41
42
43/* ======================================================================== */ 32/* ======================================================================== */
44/* PPC Sys devices definition */ 33/* PPC Sys devices definition */
45/* ======================================================================== */ 34/* ======================================================================== */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
index 02ed2c325714..c3061972309b 100644
--- a/include/asm-ppc/mpc83xx.h
+++ b/include/asm-ppc/mpc83xx.h
@@ -25,14 +25,6 @@
25#include <platforms/83xx/mpc834x_sys.h> 25#include <platforms/83xx/mpc834x_sys.h>
26#endif 26#endif
27 27
28#define _IO_BASE isa_io_base
29#define _ISA_MEM_BASE isa_mem_base
30#ifdef CONFIG_PCI
31#define PCI_DRAM_OFFSET pci_dram_offset
32#else
33#define PCI_DRAM_OFFSET 0
34#endif
35
36/* 28/*
37 * The "residual" board information structure the boot loader passes 29 * The "residual" board information structure the boot loader passes
38 * into the kernel. 30 * into the kernel.
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 9b4851199c76..d7e4a79d77fb 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -44,14 +44,6 @@
44#include <platforms/85xx/tqm85xx.h> 44#include <platforms/85xx/tqm85xx.h>
45#endif 45#endif
46 46
47#define _IO_BASE isa_io_base
48#define _ISA_MEM_BASE isa_mem_base
49#ifdef CONFIG_PCI
50#define PCI_DRAM_OFFSET pci_dram_offset
51#else
52#define PCI_DRAM_OFFSET 0
53#endif
54
55/* 47/*
56 * The "residual" board information structure the boot loader passes 48 * The "residual" board information structure the boot loader passes
57 * into the kernel. 49 * into the kernel.
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 3fef7d67aedc..f02d71bf6894 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -33,6 +33,14 @@ struct cpu {
33 33
34extern int register_cpu(struct cpu *cpu, int num); 34extern int register_cpu(struct cpu *cpu, int num);
35extern struct sys_device *get_cpu_sysdev(unsigned cpu); 35extern struct sys_device *get_cpu_sysdev(unsigned cpu);
36
37extern int cpu_add_sysdev_attr(struct sysdev_attribute *attr);
38extern void cpu_remove_sysdev_attr(struct sysdev_attribute *attr);
39
40extern int cpu_add_sysdev_attr_group(struct attribute_group *attrs);
41extern void cpu_remove_sysdev_attr_group(struct attribute_group *attrs);
42
43
36#ifdef CONFIG_HOTPLUG_CPU 44#ifdef CONFIG_HOTPLUG_CPU
37extern void unregister_cpu(struct cpu *cpu); 45extern void unregister_cpu(struct cpu *cpu);
38#endif 46#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 15:05:50 -0500