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-rw-r--r--include/asm-arm/arch-aaec2000/memory.h40
-rw-r--r--include/asm-arm/arch-clps711x/memory.h53
-rw-r--r--include/asm-arm/arch-imx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/debug-macro.S26
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h3
-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S39
-rw-r--r--include/asm-arm/arch-iop13xx/hardware.h28
-rw-r--r--include/asm-arm/arch-iop13xx/io.h41
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h492
-rw-r--r--include/asm-arm/arch-iop13xx/iq81340.h31
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h207
-rw-r--r--include/asm-arm/arch-iop13xx/memory.h64
-rw-r--r--include/asm-arm/arch-iop13xx/pci.h57
-rw-r--r--include/asm-arm/arch-iop13xx/system.h59
-rw-r--r--include/asm-arm/arch-iop13xx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h24
-rw-r--r--include/asm-arm/arch-iop13xx/vmalloc.h4
-rw-r--r--include/asm-arm/arch-ixp4xx/nslu2.h5
-rw-r--r--include/asm-arm/arch-ixp4xx/udc.h8
-rw-r--r--include/asm-arm/arch-l7200/io.h56
-rw-r--r--include/asm-arm/arch-lh7a40x/memory.h12
-rw-r--r--include/asm-arm/arch-pxa/memory.h36
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h13
-rw-r--r--include/asm-arm/arch-s3c2410/h1940.h21
-rw-r--r--include/asm-arm/arch-s3c2410/system.h2
-rw-r--r--include/asm-arm/arch-sa1100/jornada720.h42
-rw-r--r--include/asm-arm/arch-sa1100/memory.h34
-rw-r--r--include/asm-arm/bug.h4
-rw-r--r--include/asm-arm/cnt32_to_63.h78
-rw-r--r--include/asm-arm/div64.h180
-rw-r--r--include/asm-arm/elf.h150
-rw-r--r--include/asm-arm/io.h8
-rw-r--r--include/asm-arm/mach/irq.h12
-rw-r--r--include/asm-arm/memory.h39
-rw-r--r--include/asm-arm/pgtable-nommu.h1
-rw-r--r--include/asm-arm/pgtable.h3
-rw-r--r--include/asm-arm/processor.h1
-rw-r--r--include/asm-arm/procinfo.h21
-rw-r--r--include/asm-arm/thread_info.h14
-rw-r--r--include/linux/i2c-pxa.h31
40 files changed, 1529 insertions, 416 deletions
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
index 24b51cccde8f..9eceb4148922 100644
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ b/include/asm-arm/arch-aaec2000/memory.h
@@ -17,8 +17,6 @@
17#define __virt_to_bus(x) __virt_to_phys(x) 17#define __virt_to_bus(x) __virt_to_phys(x)
18#define __bus_to_virt(x) __phys_to_virt(x) 18#define __bus_to_virt(x) __phys_to_virt(x)
19 19
20#ifdef CONFIG_DISCONTIGMEM
21
22/* 20/*
23 * The nodes are the followings: 21 * The nodes are the followings:
24 * 22 *
@@ -27,42 +25,6 @@
27 * node 2: 0xf800.0000 - 0xfbff.ffff 25 * node 2: 0xf800.0000 - 0xfbff.ffff
28 * node 3: 0xfc00.0000 - 0xffff.ffff 26 * node 3: 0xfc00.0000 - 0xffff.ffff
29 */ 27 */
30 28#define NODE_MEM_SIZE_BITS 26
31/*
32 * Given a kernel address, find the home node of the underlying memory.
33 */
34#define KVADDR_TO_NID(addr) \
35 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
36
37/*
38 * Given a page frame number, convert it to a node id.
39 */
40#define PFN_TO_NID(pfn) \
41 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
42
43/*
44 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
45 * and return the mem_map of that node.
46 */
47#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
48
49/*
50 * Given a page frame number, find the owning node of the memory
51 * and return the mem_map of that node.
52 */
53#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
54
55/*
56 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
57 * and returns the index corresponding to the appropriate page in the
58 * node's mem_map.
59 */
60#define LOCAL_MAP_NR(addr) \
61 (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
62
63#define NODE_MAX_MEM_SHIFT 26
64#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT)
65
66#endif /* CONFIG_DISCONTIGMEM */
67 29
68#endif /* __ASM_ARCH_MEMORY_H */ 30#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
index c6e8dcf674de..42768cc8bfb4 100644
--- a/include/asm-arm/arch-clps711x/memory.h
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -62,7 +62,15 @@
62 * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. 62 * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM.
63 */ 63 */
64 64
65#ifdef CONFIG_DISCONTIGMEM 65/*
66 * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
67 * uses only one of the two banks (bank #1). However, even within
68 * bank #1, memory is discontiguous.
69 *
70 * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
71 * them, so we use 24 for the node max shift to get 16MB node sizes.
72 */
73
66/* 74/*
67 * Because of the wide memory address space between physical RAM banks on the 75 * Because of the wide memory address space between physical RAM banks on the
68 * SA1100, it's much more convenient to use Linux's NUMA support to implement 76 * SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
80 * node 2: 0xd0000000 - 0xd7ffffff 88 * node 2: 0xd0000000 - 0xd7ffffff
81 * node 3: 0xd8000000 - 0xdfffffff 89 * node 3: 0xd8000000 - 0xdfffffff
82 */ 90 */
83 91#define NODE_MEM_SIZE_BITS 24
84/*
85 * Given a kernel address, find the home node of the underlying memory.
86 */
87#define KVADDR_TO_NID(addr) \
88 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
89
90/*
91 * Given a page frame number, convert it to a node id.
92 */
93#define PFN_TO_NID(pfn) \
94 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
95
96/*
97 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
98 * and returns the mem_map of that node.
99 */
100#define ADDR_TO_MAPBASE(kaddr) \
101 NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
102
103#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
104
105/*
106 * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
107 * and returns the index corresponding to the appropriate page in the
108 * node's mem_map.
109 */
110#define LOCAL_MAP_NR(addr) \
111 (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
112
113/*
114 * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
115 * uses only one of the two banks (bank #1). However, even within
116 * bank #1, memory is discontiguous.
117 *
118 * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
119 * them, so we use 24 for the node max shift to get 16MB node sizes.
120 */
121#define NODE_MAX_MEM_SHIFT 24
122#define NODE_MAX_MEM_SIZE (1<<NODE_MAX_MEM_SHIFT)
123
124#endif /* CONFIG_DISCONTIGMEM */
125 92
126#endif 93#endif
127 94
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
index 8c91674706b1..e22ba789546c 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/include/asm-arm/arch-imx/timex.h
@@ -21,7 +21,6 @@
21#ifndef __ASM_ARCH_TIMEX_H 21#ifndef __ASM_ARCH_TIMEX_H
22#define __ASM_ARCH_TIMEX_H 22#define __ASM_ARCH_TIMEX_H
23 23
24#include <asm/hardware.h> 24#define CLOCK_TICK_RATE (16000000)
25#define CLOCK_TICK_RATE (CLK32)
26 25
27#endif 26#endif
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop13xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 orreq \rx, \rx, #0x00d80000
19 movne \rx, #0xfe000000 @ virtual
20 orrne \rx, \rx, #0x00e80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm
24
25#define UART_SHIFT 2
26#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_
3#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * iop13xx low level irq macros
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 .macro disable_fiq
20 .endm
21
22 /*
23 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros"
25 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
36
37 biceq \tmp, \tmp, #(1 << 6)
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
39 .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_ARCH_HARDWARE_H
2#define __ASM_ARCH_HARDWARE_H
3#include <asm/types.h>
4
5#define pcibios_assign_all_busses() 1
6
7#ifndef __ASSEMBLY__
8extern unsigned long iop13xx_pcibios_min_io;
9extern unsigned long iop13xx_pcibios_min_mem;
10extern u16 iop13xx_dev_id(void);
11extern void iop13xx_set_atu_mmr_bases(void);
12#endif
13
14#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
15#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
16
17/*
18 * Generic chipset bits
19 *
20 */
21#include "iop13xx.h"
22
23/*
24 * Board specific bits
25 */
26#include "iq81340.h"
27
28#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) (a)
25#define __mem_pci(a) (a)
26#define __mem_isa(a) (a)
27
28extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
29extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30 unsigned long flags);
31extern void __iop13xx_iounmap(void __iomem *addr);
32
33extern u32 iop13xx_atue_mem_base;
34extern u32 iop13xx_atux_mem_base;
35extern size_t iop13xx_atue_mem_size;
36extern size_t iop13xx_atux_mem_size;
37
38#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
39#define __arch_iounmap(a) __iop13xx_iounmap(a)
40
41#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
1#ifndef _IOP13XX_HW_H_
2#define _IOP13XX_HW_H_
3
4#ifndef __ASSEMBLY__
5/* The ATU offsets can change based on the strapping */
6extern u32 iop13xx_atux_pmmr_offset;
7extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void);
9void iop13xx_map_io(void);
10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40
41/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void)
43{
44 int id;
45 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
46 return id;
47}
48
49#endif
50
51/*
52 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
53 */
54#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
55#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
56
57/* PCI MAP
58 * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
59 * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
60*/
61#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
62#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
63#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
64#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
65#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
66 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
67#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
68 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
69#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
70 IOP13XX_PCIX_LOWER_IO_BA)
71#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
72 (IOP13XX_PCIX_LOWER_IO_PA\
73 - IOP13XX_PCIX_LOWER_IO_VA))
74
75#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
76#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
77#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
78#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
79 IOP13XX_PCIX_LOWER_MEM_BA)
80#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
81 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
83 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
84
85#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
86#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
87#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91
92/* PCI-E ranges */
93#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
94#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
95#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
96#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
97#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
98 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
99#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
100 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
101#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
102 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
103#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
104 IOP13XX_PCIE_LOWER_IO_BA)
105#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
106 (IOP13XX_PCIE_LOWER_IO_PA\
107 - IOP13XX_PCIE_LOWER_IO_VA))
108
109#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
110#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
111#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
112#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
113 IOP13XX_PCIE_LOWER_MEM_BA)
114#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
115 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
116#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118
119/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
120#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
121#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
122#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
123 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
124#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
125 IOP13XX_PCIE_LOWER_MEM_BA)
126
127/* PBI Ranges */
128#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
129#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
130#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
131#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
132#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
133 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
134
135/*
136 * IOP13XX chipset registers
137 */
138#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
139#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
140#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
141#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
142 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
143#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
144 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
145#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
146 (IOP13XX_PMMR_PHYS_MEM_BASE\
147 - IOP13XX_PMMR_VIRT_MEM_BASE))
148#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
149 (IOP13XX_PMMR_PHYS_MEM_BASE\
150 - IOP13XX_PMMR_VIRT_MEM_BASE))
151#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
152#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
153#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
154#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
155#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
156#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
157#define IOP13XX_PMMR_SIZE 0x00080000
158
159/*=================== Defines for Platform Devices =====================*/
160#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
161#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
162#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
163#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
164
165#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
166#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
167#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
168#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
169#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
170#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
171
172/* ATU selection flags */
173/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
174#define IOP13XX_INIT_ATU_DEFAULT (0)
175#define IOP13XX_INIT_ATU_ATUX (1 << 0)
176#define IOP13XX_INIT_ATU_ATUE (1 << 1)
177#define IOP13XX_INIT_ATU_NONE (1 << 2)
178
179/* UART selection flags */
180/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
181#define IOP13XX_INIT_UART_DEFAULT (0)
182#define IOP13XX_INIT_UART_0 (1 << 0)
183#define IOP13XX_INIT_UART_1 (1 << 1)
184
185/* I2C selection flags */
186/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
187#define IOP13XX_INIT_I2C_DEFAULT (0)
188#define IOP13XX_INIT_I2C_0 (1 << 0)
189#define IOP13XX_INIT_I2C_1 (1 << 1)
190#define IOP13XX_INIT_I2C_2 (1 << 2)
191
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
196 IQ81340_NUM_I2C +\
197 IQ81340_NUM_PHYS_MAP_FLASH)
198
199/*========================== PMMR offsets for key registers ============*/
200#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
201#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
202#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
203#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
204#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
205#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
206#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
207#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
208#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
209
210#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
211#define IOP13XX_CONTROLLER_ONLY (1 << 14)
212#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
213
214#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
215#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
216 IOP13XX_PMON_PMMR_OFFSET)
217#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
218 IOP13XX_PMON_PMMR_OFFSET)
219
220#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
221#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
222#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
223#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
224
225#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
226#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
227#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
228#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
229
230#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
231#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
232#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
233#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
234
235#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
236#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
237
238/*================================ATU===================================*/
239#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
240 iop13xx_atux_pmmr_offset + (ofs))
241
242#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
243 iop13xx_atux_pmmr_offset + 0x2)
244
245#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x4)
247#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
248 iop13xx_atux_pmmr_offset + 0x6)
249
250#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
251#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
252#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
253#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
254#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
255#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
256#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
257#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
258#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
259#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
260#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
261#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
262#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
263#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
264#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
265#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
266#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
267#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
268#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
269#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
270#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
271#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
272#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
273#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
274
275#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
276#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
277#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
278#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
279#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
280#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
281#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
282#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
283#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
284#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
285#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
286#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
287#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
288#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
289
290#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
291#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
292#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
293#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
294#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
295#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
296
297#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
298#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
299#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
300#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
301#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
302#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
303#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
304#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
305#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
306#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
307#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
308#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
309#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
310#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
311#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
312#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
313#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
314
315#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
316#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
317#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
318
319#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
320#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
321
322#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
323 iop13xx_atue_pmmr_offset + (ofs))
324
325#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
326 iop13xx_atue_pmmr_offset + 0x2)
327#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
328 iop13xx_atue_pmmr_offset + 0x4)
329#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
330 iop13xx_atue_pmmr_offset + 0x6)
331
332#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
333#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
334#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
335#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
336#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
337#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
338#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
339#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
340#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
341#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
342#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
343#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
344#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
345#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
346#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
347#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
348 iop13xx_atue_pmmr_offset + 0xe2)
349#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
350#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
351#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
352#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
353#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
354#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
355#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
356#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
357#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
358
359#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
360#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
361#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
362#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
363#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
364#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
365
366#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
367#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
368
369#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
370#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
371#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
372#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
373#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
374#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
375#define IOP13XX_ATUE_OCCAR_REG (2)
376
377#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
378#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
379#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
380#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
381#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
382#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
383#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
384
385#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
386#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
387#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
388
389#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
391
392#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
393#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
394#define IOP13XX_ATUE_STAT_PME (1 << 27)
395#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
396#define IOP13XX_ATUE_STAT_IVM (1 << 25)
397#define IOP13XX_ATUE_STAT_BIST (1 << 24)
398#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
399#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
400#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
401#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
402#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
403#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
404#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
405#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
406#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
407#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
408#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
409#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
410#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
411#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
412#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
413#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
414#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
415
416#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
417#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
418#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
419#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
420#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
421#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
422#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
423#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
424#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
425#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
426#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
427#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
428#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
429#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
430#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
431
432#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
433#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
434#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
435#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
436/*=======================================================================*/
437
438/*==============================ADMA UNITS===============================*/
439#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
440#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
441#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
442
443#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
444#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
445#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
446#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
447#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
448#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
449#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
450#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
451#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
452#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
453#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
454#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
455#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
456#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
457
458/*==============================XSI BRIDGE===============================*/
459#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
460#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
461#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
462#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
463 IOP13XX_PMMR_VIRT_TO_PHYS(\
464 IOP13XX_ATUE_OCCDR))\
465 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
466#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
467 IOP13XX_PMMR_VIRT_TO_PHYS(\
468 IOP13XX_ATUX_OCCDR))\
469 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
470/*=======================================================================*/
471
472#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
473 (ofs))
474
475#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
476#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
477#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
478#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
479#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481
482#define IOP13XX_TMR_TC 0x01
483#define IOP13XX_TMR_EN 0x02
484#define IOP13XX_TMR_RELOAD 0x04
485#define IOP13XX_TMR_PRIVILEGED 0x08
486
487#define IOP13XX_TMR_RATIO_1_1 0x00
488#define IOP13XX_TMR_RATIO_4_1 0x10
489#define IOP13XX_TMR_RATIO_8_1 0x20
490#define IOP13XX_TMR_RATIO_16_1 0x30
491
492#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
1#ifndef _IQ81340_H_
2#define _IQ81340_H_
3
4#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
5#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
6
7#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
8
9#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
10
11#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
12#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
13#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
14#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
15#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
16#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
17#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
18#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
19#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
20#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
21#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
22#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
23
24#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
25#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
26
27/* These are the values used in the Machine description */
28#define PHYS_IO 0xfeffff00
29#define IO_PG_OFFSET 0xffffff00
30#define BOOT_PARAM_OFFSET 0x00000100
31#endif /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8
9/* INTPND0 CP6 R0 Page 3
10 */
11static inline u32 read_intpnd_0(void)
12{
13 u32 val;
14 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
15 return val;
16}
17
18/* INTPND1 CP6 R1 Page 3
19 */
20static inline u32 read_intpnd_1(void)
21{
22 u32 val;
23 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
24 return val;
25}
26
27/* INTPND2 CP6 R2 Page 3
28 */
29static inline u32 read_intpnd_2(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
33 return val;
34}
35
36/* INTPND3 CP6 R3 Page 3
37 */
38static inline u32 read_intpnd_3(void)
39{
40 u32 val;
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val;
43}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif
60
61#define INTBASE 0
62#define INTSIZE_4 1
63
64/*
65 * iop34x chipset interrupts
66 */
67#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
68
69/*
70 * On IRQ or FIQ register
71 */
72#define IRQ_IOP13XX_ADMA0_EOT (0)
73#define IRQ_IOP13XX_ADMA0_EOC (1)
74#define IRQ_IOP13XX_ADMA1_EOT (2)
75#define IRQ_IOP13XX_ADMA1_EOC (3)
76#define IRQ_IOP13XX_ADMA2_EOT (4)
77#define IRQ_IOP13XX_ADMA2_EOC (5)
78#define IRQ_IOP134_WATCHDOG (6)
79#define IRQ_IOP13XX_RSVD_7 (7)
80#define IRQ_IOP13XX_TIMER0 (8)
81#define IRQ_IOP13XX_TIMER1 (9)
82#define IRQ_IOP13XX_I2C_0 (10)
83#define IRQ_IOP13XX_I2C_1 (11)
84#define IRQ_IOP13XX_MSG (12)
85#define IRQ_IOP13XX_MSGIBQ (13)
86#define IRQ_IOP13XX_ATU_IM (14)
87#define IRQ_IOP13XX_ATU_BIST (15)
88#define IRQ_IOP13XX_PPMU (16)
89#define IRQ_IOP13XX_COREPMU (17)
90#define IRQ_IOP13XX_CORECACHE (18)
91#define IRQ_IOP13XX_RSVD_19 (19)
92#define IRQ_IOP13XX_RSVD_20 (20)
93#define IRQ_IOP13XX_RSVD_21 (21)
94#define IRQ_IOP13XX_RSVD_22 (22)
95#define IRQ_IOP13XX_RSVD_23 (23)
96#define IRQ_IOP13XX_XINT0 (24)
97#define IRQ_IOP13XX_XINT1 (25)
98#define IRQ_IOP13XX_XINT2 (26)
99#define IRQ_IOP13XX_XINT3 (27)
100#define IRQ_IOP13XX_XINT4 (28)
101#define IRQ_IOP13XX_XINT5 (29)
102#define IRQ_IOP13XX_XINT6 (30)
103#define IRQ_IOP13XX_XINT7 (31)
104 /* IINTSRC1 bit */
105#define IRQ_IOP13XX_XINT8 (32) /* 0 */
106#define IRQ_IOP13XX_XINT9 (33) /* 1 */
107#define IRQ_IOP13XX_XINT10 (34) /* 2 */
108#define IRQ_IOP13XX_XINT11 (35) /* 3 */
109#define IRQ_IOP13XX_XINT12 (36) /* 4 */
110#define IRQ_IOP13XX_XINT13 (37) /* 5 */
111#define IRQ_IOP13XX_XINT14 (38) /* 6 */
112#define IRQ_IOP13XX_XINT15 (39) /* 7 */
113#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
114#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
115#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
116#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
117#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
118#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
119#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
120#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
121#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
122#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
123#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
124#define IRQ_IOP13XX_UART0 (51) /* 19 */
125#define IRQ_IOP13XX_UART1 (52) /* 20 */
126#define IRQ_IOP13XX_PBIE (53) /* 21 */
127#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
128#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
129#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
130#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
131#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
132#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
133#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
134#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
135#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
136#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
137 /* IINTSRC2 bit */
138#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
139#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
140#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
141#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
142#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
143#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
144#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
145#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
146#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
147#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
148#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
149#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
150#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
151#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
152#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
153#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
154#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
155#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
156#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
157#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
158#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
159#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
160#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
161#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
162#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
163#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
164#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
165#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
166#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
167#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
168#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
169#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
170 /* IINTSRC3 bit */
171#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
172#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
173#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
174#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
175#define IRQ_IOP13XX_IMU (100) /* 4 */
176#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
177#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
178#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
179#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
180#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
181#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
182#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
183#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
184#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
185#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
186#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
187#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
188#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
189#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
190#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
191#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
192#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
193#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
194#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
195#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
196#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
197#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
198#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
199#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
200#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
201#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
202#define IRQ_IOP13XX_HPI (127) /* 31 */
203
204#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
205#define NR_IRQS NR_IOP13XX_IRQS
206
207#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_ARCH_MEMORY_H
2#define __ASM_ARCH_MEMORY_H
3
4#include <asm/arch/hardware.h>
5
6/*
7 * Physical DRAM offset.
8 */
9#define PHYS_OFFSET UL(0x00000000)
10#define TASK_SIZE UL(0x3f000000)
11#define PAGE_OFFSET UL(0x40000000)
12#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
13
14#ifndef __ASSEMBLY__
15
16#if defined(CONFIG_ARCH_IOP13XX)
17#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
18#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
19#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
20#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
21
22/*
23 * Virtual view <-> PCI DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29
30/* RAM has 1:1 mapping on the PCIe/x Busses */
31#define __virt_to_bus(x) (__virt_to_phys(x))
32#define __bus_to_virt(x) (__phys_to_virt(x))
33
34#define virt_to_lbus(x) \
35(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
36((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
37((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
38((x) - PAGE_OFFSET + PHYS_OFFSET))
39
40#define lbus_to_virt(x) \
41(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
42((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
43((x) - PHYS_OFFSET + PAGE_OFFSET))
44
45/* Device is an lbus device if it is on the platform bus of the IOP13XX */
46#define is_lbus_device(dev) (dev &&\
47 (strncmp(dev->bus->name, "platform", 8) == 0))
48
49#define __arch_page_to_dma(dev, page) \
50({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
51(dma_addr_t)__virt_to_bus(page_address(page));})
52
53#define __arch_dma_to_virt(dev, addr) \
54({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
55
56#define __arch_virt_to_dma(dev, addr) \
57({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
58
59#endif /* CONFIG_ARCH_IOP13XX */
60#endif /* !ASSEMBLY */
61
62#define PFN_TO_NID(addr) (0)
63
64#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
1#ifndef _IOP13XX_PCI_H_
2#define _IOP13XX_PCI_H_
3#include <asm/arch/irqs.h>
4#include <asm/io.h>
5
6struct pci_sys_data;
7struct hw_pci;
8int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
9struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
10void iop13xx_atu_select(struct hw_pci *plat_pci);
11void iop13xx_pci_init(void);
12void iop13xx_map_pci_memory(void);
13
14#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
15 PCI_STATUS_SIG_TARGET_ABORT | \
16 PCI_STATUS_REC_TARGET_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_SIG_SYSTEM_ERROR | \
20 PCI_STATUS_DETECTED_PARITY)
21
22#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
23 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
24 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
25 IOP13XX_ATUE_STAT_ERR_COR | \
26 IOP13XX_ATUE_STAT_ERR_UNCOR | \
27 IOP13XX_ATUE_STAT_CRS | \
28 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
29 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
30 IOP13XX_ATUE_STAT_SIG_TABORT | \
31 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
32 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
33
34#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
35 IOP13XX_ATUX_STAT_REC_SCEM | \
36 IOP13XX_ATUX_STAT_TX_SERR | \
37 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
39 IOP13XX_ATUX_STAT_REC_SERR | \
40 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
41 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
42 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
43 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
44
45/* PCI interrupts
46 */
47#define ATUX_INTA IRQ_IOP13XX_XINT0
48#define ATUX_INTB IRQ_IOP13XX_XINT1
49#define ATUX_INTC IRQ_IOP13XX_XINT2
50#define ATUX_INTD IRQ_IOP13XX_XINT3
51
52#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
53#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
54#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
55#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
56
57#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
1/*
2 * linux/include/asm-arm/arch-iop13xx/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <asm/arch/iop13xx.h>
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode)
47{
48 /*
49 * Reset the internal bus (warning both cores are reset)
50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57
58 for(;;);
59}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
1#include <asm/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
1#include <asm/types.h>
2#include <linux/serial_reg.h>
3#include <asm/hardware.h>
4#include <asm/processor.h>
5
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
8
9static inline void putc(char c)
10{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 cpu_relax();
13 UART_BASE[UART_TX] = c;
14}
15
16static inline void flush(void)
17{
18}
19
20/*
21 * nothing to do
22 */
23#define arch_decomp_setup()
24#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
1#ifndef _VMALLOC_H_
2#define _VMALLOC_H_
3#define VMALLOC_END 0xfa000000UL
4#endif
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 4281838873ef..6b437f7c9955 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -76,6 +76,7 @@
76 76
77#define NSLU2_GPIO_BUZZ 4 77#define NSLU2_GPIO_BUZZ 4
78#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) 78#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
79
79/* LEDs */ 80/* LEDs */
80 81
81#define NSLU2_LED_RED NSLU2_GPIO0 82#define NSLU2_LED_RED NSLU2_GPIO0
@@ -84,8 +85,8 @@
84#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED) 85#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
85#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN) 86#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
86 87
87#define NSLU2_LED_DISK1 NSLU2_GPIO2 88#define NSLU2_LED_DISK1 NSLU2_GPIO3
88#define NSLU2_LED_DISK2 NSLU2_GPIO3 89#define NSLU2_LED_DISK2 NSLU2_GPIO2
89 90
90#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2) 91#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
91#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3) 92#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
new file mode 100644
index 000000000000..dbdec36ff0d1
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -0,0 +1,8 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/udc.h
3 *
4 */
5#include <asm/mach/udc_pxa2xx.h>
6
7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
8
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index d744d97c18a5..645dbdfb3908 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -17,59 +17,11 @@
17/* 17/*
18 * There are not real ISA nor PCI buses, so we fake it. 18 * There are not real ISA nor PCI buses, so we fake it.
19 */ 19 */
20#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a))) 20static inline void __iomem *__io(unsigned long addr)
21#define __mem_pci(a) (a)
22
23#define __ioaddr(p) __io_pci(p)
24
25/*
26 * Generic virtual read/write
27 */
28#define __arch_getb(a) (*(volatile unsigned char *)(a))
29#define __arch_getl(a) (*(volatile unsigned int *)(a))
30
31static inline unsigned int __arch_getw(unsigned long a)
32{
33 unsigned int value;
34 __asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
35 : "=&r" (value)
36 : "r" (a) : "cc");
37 return value;
38}
39
40#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
41#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
42
43static inline void __arch_putw(unsigned int value, unsigned long a)
44{ 21{
45 __asm__ __volatile__("strh %0, [%1, #0] @ putw" 22 return (void __iomem *)addr;
46 : : "r" (value), "r" (a) : "cc");
47} 23}
48 24#define __io(a) __io(a)
49/* 25#define __mem_pci(a) (a)
50 * Translated address IO functions
51 *
52 * IO address has already been translated to a virtual address
53 */
54#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v))
55#define inb_t(p) (*(volatile unsigned char *)(p))
56#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v))
57#define inw_t(p) (*(volatile unsigned int *)(p))
58#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v))
59#define inl_t(p) (*(volatile unsigned long *)(p))
60
61/*
62 * FIXME - These are to allow for linking. On all the other
63 * ARM platforms, the entire IO space is contiguous.
64 * The 7200 has three separate IO spaces. The below
65 * macros will eventually become more involved. Use
66 * with caution and don't be surprised by kernel oopses!!!
67 */
68#define inb(p) inb_t(p)
69#define inw(p) inw_t(p)
70#define inl(p) inl_t(p)
71#define outb(v,p) outb_t(v,p)
72#define outw(v,p) outw_t(v,p)
73#define outl(v,p) outl_t(v,p)
74 26
75#endif 27#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
index 9f1a58cbf407..9b0c8012e713 100644
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -58,18 +58,6 @@
58#endif 58#endif
59 59
60/* 60/*
61 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
62 * and return the mem_map of that node.
63 */
64# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
65
66/*
67 * Given a page frame number, find the owning node of the memory
68 * and return the mem_map of that node.
69 */
70# define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
71
72/*
73 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory 61 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
74 * and returns the index corresponding to the appropriate page in the 62 * and returns the index corresponding to the appropriate page in the
75 * node's mem_map. 63 * node's mem_map.
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
27#define __virt_to_bus(x) __virt_to_phys(x) 27#define __virt_to_bus(x) __virt_to_phys(x)
28#define __bus_to_virt(x) __phys_to_virt(x) 28#define __bus_to_virt(x) __phys_to_virt(x)
29 29
30#ifdef CONFIG_DISCONTIGMEM
31/* 30/*
32 * The nodes are matched with the physical SDRAM banks as follows: 31 * The nodes are matched with the physical SDRAM banks as follows:
33 * 32 *
@@ -35,38 +34,9 @@
35 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff 34 * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
36 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff 35 * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
37 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff 36 * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
37 *
38 * This needs a node mem size of 26 bits.
38 */ 39 */
39 40#define NODE_MEM_SIZE_BITS 26
40/*
41 * Given a kernel address, find the home node of the underlying memory.
42 */
43#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
44
45/*
46 * Given a page frame number, convert it to a node id.
47 */
48#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
49
50/*
51 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
52 * and returns the mem_map of that node.
53 */
54#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
55
56/*
57 * Given a page frame number, find the owning node of the memory
58 * and returns the mem_map of that node.
59 */
60#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
61
62/*
63 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
64 * and returns the index corresponding to the appropriate page in the
65 * node's mem_map.
66 */
67#define LOCAL_MAP_NR(addr) \
68 (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
69
70#endif
71 41
72#endif 42#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index cff752f35230..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
99#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ 99#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
100#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ 100#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ 101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ 102#define DCSR_EORINTR (1 << 9) /* The end of Receive */
103#endif 103#endif
104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ 104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ 105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
@@ -803,12 +803,11 @@
803#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ 803#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
804#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ 804#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
805#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) 805#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
806#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ 806#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
807#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ 807#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
808#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ 808#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
809#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ 809#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
810#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ 810#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
811
812 811
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ 812#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ 813#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h
new file mode 100644
index 000000000000..6135592e60f2
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/h1940.h
@@ -0,0 +1,21 @@
1/* linux/include/asm-arm/arch-s3c2410/h1940.h
2 *
3 * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_H1940_H
13#define __ASM_ARCH_H1940_H
14
15#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
16#define H1940_SUSPEND_RESUMEAT (0x30081000)
17#define H1940_SUSPEND_CHECK (0x30080000)
18
19extern void h1940_pm_return(void);
20
21#endif /* __ASM_ARCH_H1940_H */
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 718246d85952..4f72a853a5cf 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -71,7 +71,7 @@ arch_reset(char mode)
71 71
72 /* set the watchdog to go and reset... */ 72 /* set the watchdog to go and reset... */
73 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | 73 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
74 S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); 74 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
75 75
76 /* wait for reset to assert... */ 76 /* wait for reset to assert... */
77 mdelay(5000); 77 mdelay(5000);
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
deleted file mode 100644
index 3f37ca07806d..000000000000
--- a/include/asm-arm/arch-sa1100/jornada720.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-sa1100/jornada720.h
3 *
4 * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
5 *
6 * This file contains the hardware specific definitions for HP Jornada 720
7 *
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H
11#error "include <asm/hardware.h> instead"
12#endif
13
14#define SA1111_BASE (0x40000000)
15
16#define GPIO_JORNADA720_KEYBOARD GPIO_GPIO(0)
17#define GPIO_JORNADA720_MOUSE GPIO_GPIO(9)
18
19#define GPIO_JORNADA720_KEYBOARD_IRQ IRQ_GPIO0
20#define GPIO_JORNADA720_MOUSE_IRQ IRQ_GPIO9
21
22/* MCU COMMANDS */
23#define MCU_GetBatteryData 0xc0
24#define MCU_GetScanKeyCode 0x90
25#define MCU_GetTouchSamples 0xa0
26#define MCU_GetContrast 0xD0
27#define MCU_SetContrast 0xD1
28#define MCU_GetBrightness 0xD2
29#define MCU_SetBrightness 0xD3
30#define MCU_ContrastOff 0xD8
31#define MCU_BrightnessOff 0xD9
32#define MCU_PWMOFF 0xDF
33#define MCU_TxDummy 0x11
34#define MCU_ErrorCode 0x00
35
36#ifndef __ASSEMBLY__
37
38void jornada720_mcu_init(void);
39void jornada_contrast(int arg_contrast);
40void jornada720_battery(void);
41int jornada720_getkey(unsigned char *data, int size);
42#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
index 1ff172dc8e33..0e907fc6d42a 100644
--- a/include/asm-arm/arch-sa1100/memory.h
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
39#define __virt_to_bus(x) __virt_to_phys(x) 39#define __virt_to_bus(x) __virt_to_phys(x)
40#define __bus_to_virt(x) __phys_to_virt(x) 40#define __bus_to_virt(x) __phys_to_virt(x)
41 41
42#ifdef CONFIG_DISCONTIGMEM
43/* 42/*
44 * Because of the wide memory address space between physical RAM banks on the 43 * Because of the wide memory address space between physical RAM banks on the
45 * SA1100, it's much convenient to use Linux's NUMA support to implement our 44 * SA1100, it's much convenient to use Linux's NUMA support to implement our
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
57 * node 2: 0xd0000000 - 0xd7ffffff 56 * node 2: 0xd0000000 - 0xd7ffffff
58 * node 3: 0xd8000000 - 0xdfffffff 57 * node 3: 0xd8000000 - 0xdfffffff
59 */ 58 */
60 59#define NODE_MEM_SIZE_BITS 27
61/*
62 * Given a kernel address, find the home node of the underlying memory.
63 */
64#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
65
66/*
67 * Given a page frame number, convert it to a node id.
68 */
69#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
70
71/*
72 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
73 * and return the mem_map of that node.
74 */
75#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
76
77/*
78 * Given a page frame number, find the owning node of the memory
79 * and return the mem_map of that node.
80 */
81#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
82
83/*
84 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
85 * and returns the index corresponding to the appropriate page in the
86 * node's mem_map.
87 */
88#define LOCAL_MAP_NR(addr) \
89 (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
90
91#endif
92 60
93/* 61/*
94 * Cache flushing area - SA1100 zero bank 62 * Cache flushing area - SA1100 zero bank
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
index 0e36fd5d87df..7b62351f097d 100644
--- a/include/asm-arm/bug.h
+++ b/include/asm-arm/bug.h
@@ -4,10 +4,10 @@
4 4
5#ifdef CONFIG_BUG 5#ifdef CONFIG_BUG
6#ifdef CONFIG_DEBUG_BUGVERBOSE 6#ifdef CONFIG_DEBUG_BUGVERBOSE
7extern void __bug(const char *file, int line, void *data) __attribute__((noreturn)); 7extern void __bug(const char *file, int line) __attribute__((noreturn));
8 8
9/* give file/line information */ 9/* give file/line information */
10#define BUG() __bug(__FILE__, __LINE__, NULL) 10#define BUG() __bug(__FILE__, __LINE__)
11 11
12#else 12#else
13 13
diff --git a/include/asm-arm/cnt32_to_63.h b/include/asm-arm/cnt32_to_63.h
new file mode 100644
index 000000000000..480c873fa746
--- /dev/null
+++ b/include/asm-arm/cnt32_to_63.h
@@ -0,0 +1,78 @@
1/*
2 * include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
3 *
4 * Author: Nicolas Pitre
5 * Created: December 3, 2006
6 * Copyright: MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
11 */
12
13#ifndef __INCLUDE_CNT32_TO_63_H__
14#define __INCLUDE_CNT32_TO_63_H__
15
16#include <linux/compiler.h>
17#include <asm/types.h>
18#include <asm/byteorder.h>
19
20/*
21 * Prototype: u64 cnt32_to_63(u32 cnt)
22 * Many hardware clock counters are only 32 bits wide and therefore have
23 * a relatively short period making wrap-arounds rather frequent. This
24 * is a problem when implementing sched_clock() for example, where a 64-bit
25 * non-wrapping monotonic value is expected to be returned.
26 *
27 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
28 * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
29 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
30 * memory is used to synchronize with the hardware clock half-period. When
31 * the top bit of both counters (hardware and in memory) differ then the
32 * memory is updated with a new value, incrementing it when the hardware
33 * counter wraps around.
34 *
35 * Because a word store in memory is atomic then the incremented value will
36 * always be in synch with the top bit indicating to any potential concurrent
37 * reader if the value in memory is up to date or not with regards to the
38 * needed increment. And any race in updating the value in memory is harmless
39 * as the same value would simply be stored more than once.
40 *
41 * The only restriction for the algorithm to work properly is that this
42 * code must be executed at least once per each half period of the 32-bit
43 * counter to properly update the state bit in memory. This is usually not a
44 * problem in practice, but if it is then a kernel timer could be scheduled
45 * to manage for this code to be executed often enough.
46 *
47 * Note that the top bit (bit 63) in the returned value should be considered
48 * as garbage. It is not cleared here because callers are likely to use a
49 * multiplier on the returned value which can get rid of the top bit
50 * implicitly by making the multiplier even, therefore saving on a runtime
51 * clear-bit instruction. Otherwise caller must remember to clear the top
52 * bit explicitly.
53 */
54
55/* this is used only to give gcc a clue about good code generation */
56typedef union {
57 struct {
58#if defined(__LITTLE_ENDIAN)
59 u32 lo, hi;
60#elif defined(__BIG_ENDIAN)
61 u32 hi, lo;
62#endif
63 };
64 u64 val;
65} cnt32_to_63_t;
66
67#define cnt32_to_63(cnt_lo) \
68({ \
69 static volatile u32 __m_cnt_hi = 0; \
70 cnt32_to_63_t __x; \
71 __x.hi = __m_cnt_hi; \
72 __x.lo = (cnt_lo); \
73 if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
74 __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
75 __x.val; \
76})
77
78#endif
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h
index 3682616804ca..37e0a96e8789 100644
--- a/include/asm-arm/div64.h
+++ b/include/asm-arm/div64.h
@@ -27,7 +27,7 @@
27#define __xh "r1" 27#define __xh "r1"
28#endif 28#endif
29 29
30#define do_div(n,base) \ 30#define __do_div_asm(n, base) \
31({ \ 31({ \
32 register unsigned int __base asm("r4") = base; \ 32 register unsigned int __base asm("r4") = base; \
33 register unsigned long long __n asm("r0") = n; \ 33 register unsigned long long __n asm("r0") = n; \
@@ -45,4 +45,182 @@
45 __rem; \ 45 __rem; \
46}) 46})
47 47
48#if __GNUC__ < 4
49
50/*
51 * gcc versions earlier than 4.0 are simply too problematic for the
52 * optimized implementation below. First there is gcc PR 15089 that
53 * tend to trig on more complex constructs, spurious .global __udivsi3
54 * are inserted even if none of those symbols are referenced in the
55 * generated code, and those gcc versions are not able to do constant
56 * propagation on long long values anyway.
57 */
58#define do_div(n, base) __do_div_asm(n, base)
59
60#elif __GNUC__ >= 4
61
62#include <asm/bug.h>
63
64/*
65 * If the divisor happens to be constant, we determine the appropriate
66 * inverse at compile time to turn the division into a few inline
67 * multiplications instead which is much faster. And yet only if compiling
68 * for ARMv4 or higher (we need umull/umlal) and if the gcc version is
69 * sufficiently recent to perform proper long long constant propagation.
70 * (It is unfortunate that gcc doesn't perform all this internally.)
71 */
72#define do_div(n, base) \
73({ \
74 unsigned int __r, __b = (base); \
75 if (!__builtin_constant_p(__b) || __b == 0 || \
76 (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \
77 /* non-constant divisor (or zero): slow path */ \
78 __r = __do_div_asm(n, __b); \
79 } else if ((__b & (__b - 1)) == 0) { \
80 /* Trivial: __b is constant and a power of 2 */ \
81 /* gcc does the right thing with this code. */ \
82 __r = n; \
83 __r &= (__b - 1); \
84 n /= __b; \
85 } else { \
86 /* Multiply by inverse of __b: n/b = n*(p/b)/p */ \
87 /* We rely on the fact that most of this code gets */ \
88 /* optimized away at compile time due to constant */ \
89 /* propagation and only a couple inline assembly */ \
90 /* instructions should remain. Better avoid any */ \
91 /* code construct that might prevent that. */ \
92 unsigned long long __res, __x, __t, __m, __n = n; \
93 unsigned int __c, __p, __z = 0; \
94 /* preserve low part of n for reminder computation */ \
95 __r = __n; \
96 /* determine number of bits to represent __b */ \
97 __p = 1 << __div64_fls(__b); \
98 /* compute __m = ((__p << 64) + __b - 1) / __b */ \
99 __m = (~0ULL / __b) * __p; \
100 __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \
101 /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
102 __x = ~0ULL / __b * __b - 1; \
103 __res = (__m & 0xffffffff) * (__x & 0xffffffff); \
104 __res >>= 32; \
105 __res += (__m & 0xffffffff) * (__x >> 32); \
106 __t = __res; \
107 __res += (__x & 0xffffffff) * (__m >> 32); \
108 __t = (__res < __t) ? (1ULL << 32) : 0; \
109 __res = (__res >> 32) + __t; \
110 __res += (__m >> 32) * (__x >> 32); \
111 __res /= __p; \
112 /* Now sanitize and optimize what we've got. */ \
113 if (~0ULL % (__b / (__b & -__b)) == 0) { \
114 /* those cases can be simplified with: */ \
115 __n /= (__b & -__b); \
116 __m = ~0ULL / (__b / (__b & -__b)); \
117 __p = 1; \
118 __c = 1; \
119 } else if (__res != __x / __b) { \
120 /* We can't get away without a correction */ \
121 /* to compensate for bit truncation errors. */ \
122 /* To avoid it we'd need an additional bit */ \
123 /* to represent __m which would overflow it. */ \
124 /* Instead we do m=p/b and n/b=(n*m+m)/p. */ \
125 __c = 1; \
126 /* Compute __m = (__p << 64) / __b */ \
127 __m = (~0ULL / __b) * __p; \
128 __m += ((~0ULL % __b + 1) * __p) / __b; \
129 } else { \
130 /* Reduce __m/__p, and try to clear bit 31 */ \
131 /* of __m when possible otherwise that'll */ \
132 /* need extra overflow handling later. */ \
133 unsigned int __bits = -(__m & -__m); \
134 __bits |= __m >> 32; \
135 __bits = (~__bits) << 1; \
136 /* If __bits == 0 then setting bit 31 is */ \
137 /* unavoidable. Simply apply the maximum */ \
138 /* possible reduction in that case. */ \
139 /* Otherwise the MSB of __bits indicates the */ \
140 /* best reduction we should apply. */ \
141 if (!__bits) { \
142 __p /= (__m & -__m); \
143 __m /= (__m & -__m); \
144 } else { \
145 __p >>= __div64_fls(__bits); \
146 __m >>= __div64_fls(__bits); \
147 } \
148 /* No correction needed. */ \
149 __c = 0; \
150 } \
151 /* Now we have a combination of 2 conditions: */ \
152 /* 1) whether or not we need a correction (__c), and */ \
153 /* 2) whether or not there might be an overflow in */ \
154 /* the cross product (__m & ((1<<63) | (1<<31))) */ \
155 /* Select the best insn combination to perform the */ \
156 /* actual __m * __n / (__p << 64) operation. */ \
157 if (!__c) { \
158 asm ( "umull %Q0, %R0, %1, %Q2\n\t" \
159 "mov %Q0, #0" \
160 : "=&r" (__res) \
161 : "r" (__m), "r" (__n) \
162 : "cc" ); \
163 } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
164 __res = __m; \
165 asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \
166 "mov %Q0, #0" \
167 : "+r" (__res) \
168 : "r" (__m), "r" (__n) \
169 : "cc" ); \
170 } else { \
171 asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
172 "cmn %Q0, %Q1\n\t" \
173 "adcs %R0, %R0, %R1\n\t" \
174 "adc %Q0, %3, #0" \
175 : "=&r" (__res) \
176 : "r" (__m), "r" (__n), "r" (__z) \
177 : "cc" ); \
178 } \
179 if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
180 asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \
181 "umlal %R0, %Q0, %Q1, %R2\n\t" \
182 "mov %R0, #0\n\t" \
183 "umlal %Q0, %R0, %R1, %R2" \
184 : "+r" (__res) \
185 : "r" (__m), "r" (__n) \
186 : "cc" ); \
187 } else { \
188 asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \
189 "umlal %R0, %1, %Q2, %R3\n\t" \
190 "mov %R0, #0\n\t" \
191 "adds %Q0, %1, %Q0\n\t" \
192 "adc %R0, %R0, #0\n\t" \
193 "umlal %Q0, %R0, %R2, %R3" \
194 : "+r" (__res), "+r" (__z) \
195 : "r" (__m), "r" (__n) \
196 : "cc" ); \
197 } \
198 __res /= __p; \
199 /* The reminder can be computed with 32-bit regs */ \
200 /* only, and gcc is good at that. */ \
201 { \
202 unsigned int __res0 = __res; \
203 unsigned int __b0 = __b; \
204 __r -= __res0 * __b0; \
205 } \
206 /* BUG_ON(__r >= __b || __res * __b + __r != n); */ \
207 n = __res; \
208 } \
209 __r; \
210})
211
212/* our own fls implementation to make sure constant propagation is fine */
213#define __div64_fls(bits) \
214({ \
215 unsigned int __left = (bits), __nr = 0; \
216 if (__left & 0xffff0000) __nr += 16, __left >>= 16; \
217 if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \
218 if (__left & 0x000000f0) __nr += 4, __left >>= 4; \
219 if (__left & 0x0000000c) __nr += 2, __left >>= 2; \
220 if (__left & 0x00000002) __nr += 1; \
221 __nr; \
222})
223
224#endif
225
48#endif 226#endif
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 17f0c656d272..642382d2c9f0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,17 +1,22 @@
1#ifndef __ASMARM_ELF_H 1#ifndef __ASMARM_ELF_H
2#define __ASMARM_ELF_H 2#define __ASMARM_ELF_H
3 3
4 4#ifndef __ASSEMBLY__
5/* 5/*
6 * ELF register definitions.. 6 * ELF register definitions..
7 */ 7 */
8
9#include <asm/ptrace.h> 8#include <asm/ptrace.h>
10#include <asm/user.h> 9#include <asm/user.h>
11 10
12typedef unsigned long elf_greg_t; 11typedef unsigned long elf_greg_t;
13typedef unsigned long elf_freg_t[3]; 12typedef unsigned long elf_freg_t[3];
14 13
14#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
15typedef elf_greg_t elf_gregset_t[ELF_NGREG];
16
17typedef struct user_fp elf_fpregset_t;
18#endif
19
15#define EM_ARM 40 20#define EM_ARM 40
16#define EF_ARM_APCS26 0x08 21#define EF_ARM_APCS26 0x08
17#define EF_ARM_SOFT_FLOAT 0x200 22#define EF_ARM_SOFT_FLOAT 0x200
@@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3];
23#define R_ARM_CALL 28 28#define R_ARM_CALL 28
24#define R_ARM_JUMP24 29 29#define R_ARM_JUMP24 29
25 30
26#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
27typedef elf_greg_t elf_gregset_t[ELF_NGREG];
28
29typedef struct user_fp elf_fpregset_t;
30
31/* 31/*
32 * These are used to set parameters in the core dumps. 32 * These are used to set parameters in the core dumps.
33 */ 33 */
@@ -39,97 +39,99 @@ typedef struct user_fp elf_fpregset_t;
39#endif 39#endif
40#define ELF_ARCH EM_ARM 40#define ELF_ARCH EM_ARM
41 41
42#ifdef __KERNEL__
43#include <asm/procinfo.h>
44
45/* 42/*
46 * This is used to ensure we don't load something for the wrong architecture. 43 * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
47 */ 44 */
48#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) ) 45#define HWCAP_SWP 1
49 46#define HWCAP_HALF 2
50#define USE_ELF_CORE_DUMP 47#define HWCAP_THUMB 4
51#define ELF_EXEC_PAGESIZE 4096 48#define HWCAP_26BIT 8 /* Play it safe */
52 49#define HWCAP_FAST_MULT 16
53/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 50#define HWCAP_FPA 32
54 use of this is to invoke "./ld.so someprog" to test out a new version of 51#define HWCAP_VFP 64
55 the loader. We need to make sure that it is out of the way of the program 52#define HWCAP_EDSP 128
56 that it will "exec", and that there is sufficient room for the brk. */ 53#define HWCAP_JAVA 256
57 54#define HWCAP_IWMMXT 512
58#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
59
60/* When the program starts, a1 contains a pointer to a function to be
61 registered with atexit, as per the SVR4 ABI. A value of 0 means we
62 have no such handler. */
63#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
64
65/* This yields a mask that user programs can use to figure out what
66 instruction set this cpu supports. */
67 55
56#ifdef __KERNEL__
57#ifndef __ASSEMBLY__
58/*
59 * This yields a mask that user programs can use to figure out what
60 * instruction set this cpu supports.
61 */
68#define ELF_HWCAP (elf_hwcap) 62#define ELF_HWCAP (elf_hwcap)
63extern unsigned int elf_hwcap;
69 64
70/* This yields a string that ld.so will use to load implementation 65/*
71 specific libraries for optimization. This is more specific in 66 * This yields a string that ld.so will use to load implementation
72 intent than poking at uname or /proc/cpuinfo. */ 67 * specific libraries for optimization. This is more specific in
73 68 * intent than poking at uname or /proc/cpuinfo.
74/* For now we just provide a fairly general string that describes the 69 *
75 processor family. This could be made more specific later if someone 70 * For now we just provide a fairly general string that describes the
76 implemented optimisations that require it. 26-bit CPUs give you 71 * processor family. This could be made more specific later if someone
77 "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't 72 * implemented optimisations that require it. 26-bit CPUs give you
78 supported). 32-bit CPUs give you "v3[lb]" for anything based on an 73 * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
79 ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 74 * supported). 32-bit CPUs give you "v3[lb]" for anything based on an
80 core. */ 75 * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
81 76 * core.
77 */
82#define ELF_PLATFORM_SIZE 8 78#define ELF_PLATFORM_SIZE 8
83extern char elf_platform[];
84#define ELF_PLATFORM (elf_platform) 79#define ELF_PLATFORM (elf_platform)
85 80
81extern char elf_platform[];
82#endif
83
84/*
85 * This is used to ensure we don't load something for the wrong architecture.
86 */
87#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
88
86/* 89/*
87 * 32-bit code is always OK. Some cpus can do 26-bit, some can't. 90 * 32-bit code is always OK. Some cpus can do 26-bit, some can't.
88 */ 91 */
89#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) 92#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
90 93
91#define ELF_THUMB_OK(x) \ 94#define ELF_THUMB_OK(x) \
92 (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \ 95 ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
93 ((x)->e_entry & 3) == 0) 96 ((x)->e_entry & 3) == 0)
94 97
95#define ELF_26BIT_OK(x) \ 98#define ELF_26BIT_OK(x) \
96 (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \ 99 ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
97 ((x)->e_flags & EF_ARM_APCS26) == 0) 100 ((x)->e_flags & EF_ARM_APCS26) == 0)
98 101
99#ifndef CONFIG_IWMMXT 102#define USE_ELF_CORE_DUMP
103#define ELF_EXEC_PAGESIZE 4096
100 104
101/* Old NetWinder binaries were compiled in such a way that the iBCS 105/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
102 heuristic always trips on them. Until these binaries become uncommon 106 use of this is to invoke "./ld.so someprog" to test out a new version of
103 enough not to care, don't trust the `ibcs' flag here. In any case 107 the loader. We need to make sure that it is out of the way of the program
104 there is no other ELF system currently supported by iBCS. 108 that it will "exec", and that there is sufficient room for the brk. */
105 @@ Could print a warning message to encourage users to upgrade. */
106#define SET_PERSONALITY(ex,ibcs2) \
107 set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
108 109
109#else 110#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
111
112/* When the program starts, a1 contains a pointer to a function to be
113 registered with atexit, as per the SVR4 ABI. A value of 0 means we
114 have no such handler. */
115#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
110 116
111/* 117/*
112 * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run 118 * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
113 * legacy binaries which used to contain FPA11 floating point instructions 119 * and CP1, we only enable access to the iWMMXt coprocessor if the
114 * that have always been emulated by the kernel. PFA11 and iWMMXt overlap 120 * binary is EABI or softfloat (and thus, guaranteed not to use
115 * on coprocessor 1 space though. We therefore must decide if given task 121 * FPA instructions.)
116 * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
117 * at all times for the prefetch exception handler to catch FPA11 opcodes
118 * and emulate them. The best indication to discriminate those two cases
119 * is the SOFT_FLOAT flag in the ELF header.
120 */ 122 */
121 123#define SET_PERSONALITY(ex, ibcs2) \
122#define SET_PERSONALITY(ex,ibcs2) \ 124 do { \
123do { \ 125 if ((ex).e_flags & EF_ARM_APCS26) { \
124 set_personality(PER_LINUX_32BIT); \ 126 set_personality(PER_LINUX); \
125 if (((ex).e_flags & EF_ARM_EABI_MASK) || \ 127 } else { \
126 ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \ 128 set_personality(PER_LINUX_32BIT); \
127 set_thread_flag(TIF_USING_IWMMXT); \ 129 if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
128 else \ 130 set_thread_flag(TIF_USING_IWMMXT); \
129 clear_thread_flag(TIF_USING_IWMMXT); \ 131 else \
130} while (0) 132 clear_thread_flag(TIF_USING_IWMMXT); \
131 133 } \
132#endif 134 } while (0)
133 135
134#endif 136#endif
135 137
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index ae999fd5dc67..288f76b166d0 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn);
75 */ 75 */
76#include <asm/arch/io.h> 76#include <asm/arch/io.h>
77 77
78#ifdef __io_pci
79#warning machine class uses buggy __io_pci
80#endif
81#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
82 defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
83#warning machine class uses old __arch_putw or __arch_getw
84#endif
85
86/* 78/*
87 * IO port access primitives 79 * IO port access primitives
88 * ------------------------- 80 * -------------------------
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
index 0e017ecf2096..eb0bfba6570d 100644
--- a/include/asm-arm/mach/irq.h
+++ b/include/asm-arm/mach/irq.h
@@ -22,12 +22,6 @@ extern void init_FIQ(void);
22extern int show_fiq_list(struct seq_file *, void *); 22extern int show_fiq_list(struct seq_file *, void *);
23 23
24/* 24/*
25 * Function wrappers
26 */
27#define set_irq_chipdata(irq, d) set_irq_chip_data(irq, d)
28#define get_irq_chipdata(irq) get_irq_chip_data(irq)
29
30/*
31 * Obsolete inline function for calling irq descriptor handlers. 25 * Obsolete inline function for calling irq descriptor handlers.
32 */ 26 */
33static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) 27static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
@@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
44/* 38/*
45 * This is for easy migration, but should be changed in the source 39 * This is for easy migration, but should be changed in the source
46 */ 40 */
47#define do_level_IRQ handle_level_irq
48#define do_edge_IRQ handle_edge_irq
49#define do_simple_IRQ handle_simple_irq
50#define irqdesc irq_desc
51#define irqchip irq_chip
52
53#define do_bad_IRQ(irq,desc) \ 41#define do_bad_IRQ(irq,desc) \
54do { \ 42do { \
55 spin_lock(&desc->lock); \ 43 spin_lock(&desc->lock); \
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 91d536c215d7..d9bfb39adabf 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
215 * virt_addr_valid(k) indicates whether a virtual address is valid 215 * virt_addr_valid(k) indicates whether a virtual address is valid
216 */ 216 */
217#ifndef CONFIG_DISCONTIGMEM 217#ifndef CONFIG_DISCONTIGMEM
218
218#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET 219#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
219#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) 220#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
220 221
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
230 * around in memory. 231 * around in memory.
231 */ 232 */
232#include <linux/numa.h> 233#include <linux/numa.h>
234
233#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn) 235#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn)
234#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT) 236#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
235 237
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
256 */ 258 */
257#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) 259#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT)
258 260
261/*
262 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
263 * and returns the mem_map of that node.
264 */
265#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
266
267/*
268 * Given a page frame number, find the owning node of the memory
269 * and returns the mem_map of that node.
270 */
271#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
272
273#ifdef NODE_MEM_SIZE_BITS
274#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1)
275
276/*
277 * Given a kernel address, find the home node of the underlying memory.
278 */
279#define KVADDR_TO_NID(addr) \
280 (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
281
282/*
283 * Given a page frame number, convert it to a node id.
284 */
285#define PFN_TO_NID(pfn) \
286 (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
287
288/*
289 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
290 * and returns the index corresponding to the appropriate page in the
291 * node's mem_map.
292 */
293#define LOCAL_MAP_NR(addr) \
294 (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
295
296#endif /* NODE_MEM_SIZE_BITS */
297
259#endif /* !CONFIG_DISCONTIGMEM */ 298#endif /* !CONFIG_DISCONTIGMEM */
260 299
261/* 300/*
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index c1b264dff287..7b1c9acdf79a 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -44,7 +44,6 @@
44#define PAGE_READONLY __pgprot(0) 44#define PAGE_READONLY __pgprot(0)
45#define PAGE_KERNEL __pgprot(0) 45#define PAGE_KERNEL __pgprot(0)
46 46
47//extern void paging_init(struct meminfo *, struct machine_desc *);
48#define swapper_pg_dir ((pgd_t *) 0) 47#define swapper_pg_dir ((pgd_t *) 0)
49 48
50#define __swp_type(x) (0) 49#define __swp_type(x) (0)
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index ed8cb5963e99..88cd5c784ef0 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
169#define L_PTE_WRITE (1 << 5) 169#define L_PTE_WRITE (1 << 5)
170#define L_PTE_EXEC (1 << 6) 170#define L_PTE_EXEC (1 << 6)
171#define L_PTE_DIRTY (1 << 7) 171#define L_PTE_DIRTY (1 << 7)
172#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ 172#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
173#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */
174#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ 173#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
175 174
176#ifndef __ASSEMBLY__ 175#ifndef __ASSEMBLY__
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index 04f4d34c6317..b442e8e2a809 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -20,7 +20,6 @@
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <asm/ptrace.h> 22#include <asm/ptrace.h>
23#include <asm/procinfo.h>
24#include <asm/types.h> 23#include <asm/types.h>
25 24
26union debug_insn { 25union debug_insn {
diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
index 91a31adfa8a8..4d3c685075e0 100644
--- a/include/asm-arm/procinfo.h
+++ b/include/asm-arm/procinfo.h
@@ -10,7 +10,7 @@
10#ifndef __ASM_PROCINFO_H 10#ifndef __ASM_PROCINFO_H
11#define __ASM_PROCINFO_H 11#define __ASM_PROCINFO_H
12 12
13#ifndef __ASSEMBLY__ 13#ifdef __KERNEL__
14 14
15struct cpu_tlb_fns; 15struct cpu_tlb_fns;
16struct cpu_user_fns; 16struct cpu_user_fns;
@@ -42,19 +42,8 @@ struct proc_info_list {
42 struct cpu_cache_fns *cache; 42 struct cpu_cache_fns *cache;
43}; 43};
44 44
45extern unsigned int elf_hwcap; 45#else /* __KERNEL__ */
46 46#include <asm/elf.h>
47#endif /* __ASSEMBLY__ */ 47#warning "Please include asm/elf.h instead"
48 48#endif /* __KERNEL__ */
49#define HWCAP_SWP 1
50#define HWCAP_HALF 2
51#define HWCAP_THUMB 4
52#define HWCAP_26BIT 8 /* Play it safe */
53#define HWCAP_FAST_MULT 16
54#define HWCAP_FPA 32
55#define HWCAP_VFP 64
56#define HWCAP_EDSP 128
57#define HWCAP_JAVA 256
58#define HWCAP_IWMMXT 512
59
60#endif 49#endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index f28b236139ed..d9b8bddc8732 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void)
94 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); 94 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
95} 95}
96 96
97extern struct thread_info *alloc_thread_info(struct task_struct *task); 97/* thread information allocation */
98extern void free_thread_info(struct thread_info *); 98#ifdef CONFIG_DEBUG_STACK_USAGE
99#define alloc_thread_info(tsk) \
100 ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
101 THREAD_SIZE_ORDER))
102#else
103#define alloc_thread_info(tsk) \
104 ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
105#endif
106
107#define free_thread_info(info) \
108 free_pages((unsigned long)info, THREAD_SIZE_ORDER);
99 109
100#define thread_saved_pc(tsk) \ 110#define thread_saved_pc(tsk) \
101 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) 111 ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
index 5f3eaf802223..41dcdfe7f625 100644
--- a/include/linux/i2c-pxa.h
+++ b/include/linux/i2c-pxa.h
@@ -1,29 +1,6 @@
1#ifndef _LINUX_I2C_ALGO_PXA_H 1#ifndef _LINUX_I2C_ALGO_PXA_H
2#define _LINUX_I2C_ALGO_PXA_H 2#define _LINUX_I2C_ALGO_PXA_H
3 3
4struct i2c_eeprom_emu_watcher {
5 void (*write)(void *, unsigned int addr, unsigned char newval);
6};
7
8struct i2c_eeprom_emu_watch {
9 struct list_head node;
10 unsigned int start;
11 unsigned int end;
12 struct i2c_eeprom_emu_watcher *ops;
13 void *data;
14};
15
16#define I2C_EEPROM_EMU_SIZE (256)
17
18struct i2c_eeprom_emu {
19 unsigned int size;
20 unsigned int ptr;
21 unsigned int seen_start;
22 struct list_head watch;
23
24 unsigned char bytes[I2C_EEPROM_EMU_SIZE];
25};
26
27typedef enum i2c_slave_event_e { 4typedef enum i2c_slave_event_e {
28 I2C_SLAVE_EVENT_START_READ, 5 I2C_SLAVE_EVENT_START_READ,
29 I2C_SLAVE_EVENT_START_WRITE, 6 I2C_SLAVE_EVENT_START_WRITE,
@@ -37,12 +14,4 @@ struct i2c_slave_client {
37 void (*write)(void *ptr, unsigned int val); 14 void (*write)(void *ptr, unsigned int val);
38}; 15};
39 16
40extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
41 unsigned int addr, unsigned int size,
42 struct i2c_eeprom_emu_watcher *);
43
44extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
45
46extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
47
48#endif /* _LINUX_I2C_ALGO_PXA_H */ 17#endif /* _LINUX_I2C_ALGO_PXA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 21:10:37 -0500