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-rw-r--r--include/dt-bindings/clk/at91.h22
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h107
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h111
-rw-r--r--include/dt-bindings/clock/tegra114-car.h8
-rw-r--r--include/dt-bindings/clock/tegra124-car.h341
-rw-r--r--include/dt-bindings/clock/tegra20-car.h2
-rw-r--r--include/dt-bindings/clock/tegra30-car.h12
-rw-r--r--include/dt-bindings/gpio/tegra-gpio.h1
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra.h45
-rw-r--r--include/linux/clk/at91_pmc.h192
-rw-r--r--include/linux/clk/shmobile.h19
-rw-r--r--include/linux/clk/tegra.h7
-rw-r--r--include/linux/dmaengine.h9
-rw-r--r--include/linux/pinctrl/pinconf-generic.h6
-rw-r--r--include/linux/platform_data/clocksource-nomadik-mtu.h9
-rw-r--r--include/linux/platform_data/pinctrl-nomadik.h242
-rw-r--r--include/linux/tegra-powergate.h7
-rw-r--r--include/sound/dmaengine_pcm.h10
18 files changed, 881 insertions, 269 deletions
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h
new file mode 100644
index 000000000000..0b4cb999a3f7
--- /dev/null
+++ b/include/dt-bindings/clk/at91.h
@@ -0,0 +1,22 @@
1/*
2 * This header provides constants for AT91 pmc status.
3 *
4 * The constants defined in this header are being used in dts.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef _DT_BINDINGS_CLK_AT91_H
10#define _DT_BINDINGS_CLK_AT91_H
11
12#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
13#define AT91_PMC_LOCKA 1 /* PLLA Lock */
14#define AT91_PMC_LOCKB 2 /* PLLB Lock */
15#define AT91_PMC_MCKRDY 3 /* Master Clock */
16#define AT91_PMC_LOCKU 6 /* UPLL Lock */
17#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
18#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
19#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
20#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
21
22#endif
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000000..859e9be511d9
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,107 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
11#define __DT_BINDINGS_CLOCK_R8A7790_H__
12
13/* CPG */
14#define R8A7790_CLK_MAIN 0
15#define R8A7790_CLK_PLL0 1
16#define R8A7790_CLK_PLL1 2
17#define R8A7790_CLK_PLL3 3
18#define R8A7790_CLK_LB 4
19#define R8A7790_CLK_QSPI 5
20#define R8A7790_CLK_SDH 6
21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9
24
25/* MSTP0 */
26#define R8A7790_CLK_MSIOF0 0
27
28/* MSTP1 */
29#define R8A7790_CLK_TMU1 11
30#define R8A7790_CLK_TMU3 21
31#define R8A7790_CLK_TMU2 22
32#define R8A7790_CLK_CMT0 24
33#define R8A7790_CLK_TMU0 25
34#define R8A7790_CLK_VSP1_DU1 27
35#define R8A7790_CLK_VSP1_DU0 28
36#define R8A7790_CLK_VSP1_RT 30
37#define R8A7790_CLK_VSP1_SY 31
38
39/* MSTP2 */
40#define R8A7790_CLK_SCIFA2 2
41#define R8A7790_CLK_SCIFA1 3
42#define R8A7790_CLK_SCIFA0 4
43#define R8A7790_CLK_MSIOF2 5
44#define R8A7790_CLK_SCIFB0 6
45#define R8A7790_CLK_SCIFB1 7
46#define R8A7790_CLK_MSIOF1 8
47#define R8A7790_CLK_MSIOF3 15
48#define R8A7790_CLK_SCIFB2 16
49#define R8A7790_CLK_SYS_DMAC0 18
50#define R8A7790_CLK_SYS_DMAC1 19
51
52/* MSTP3 */
53#define R8A7790_CLK_TPU0 4
54#define R8A7790_CLK_MMCIF1 5
55#define R8A7790_CLK_SDHI3 11
56#define R8A7790_CLK_SDHI2 12
57#define R8A7790_CLK_SDHI1 13
58#define R8A7790_CLK_SDHI0 14
59#define R8A7790_CLK_MMCIF0 15
60#define R8A7790_CLK_SSUSB 28
61#define R8A7790_CLK_CMT1 29
62#define R8A7790_CLK_USBDMAC0 30
63#define R8A7790_CLK_USBDMAC1 31
64
65/* MSTP5 */
66#define R8A7790_CLK_THERMAL 22
67#define R8A7790_CLK_PWM 23
68
69/* MSTP7 */
70#define R8A7790_CLK_EHCI 3
71#define R8A7790_CLK_HSUSB 4
72#define R8A7790_CLK_HSCIF1 16
73#define R8A7790_CLK_HSCIF0 17
74#define R8A7790_CLK_SCIF1 20
75#define R8A7790_CLK_SCIF0 21
76#define R8A7790_CLK_DU2 22
77#define R8A7790_CLK_DU1 23
78#define R8A7790_CLK_DU0 24
79#define R8A7790_CLK_LVDS1 25
80#define R8A7790_CLK_LVDS0 26
81
82/* MSTP8 */
83#define R8A7790_CLK_VIN3 8
84#define R8A7790_CLK_VIN2 9
85#define R8A7790_CLK_VIN1 10
86#define R8A7790_CLK_VIN0 11
87#define R8A7790_CLK_ETHER 13
88#define R8A7790_CLK_SATA1 14
89#define R8A7790_CLK_SATA0 15
90
91/* MSTP9 */
92#define R8A7790_CLK_GPIO5 7
93#define R8A7790_CLK_GPIO4 8
94#define R8A7790_CLK_GPIO3 9
95#define R8A7790_CLK_GPIO2 10
96#define R8A7790_CLK_GPIO1 11
97#define R8A7790_CLK_GPIO0 12
98#define R8A7790_CLK_RCAN1 15
99#define R8A7790_CLK_RCAN0 16
100#define R8A7790_CLK_QSPI_MOD 17
101#define R8A7790_CLK_IICDVFS 26
102#define R8A7790_CLK_I2C3 28
103#define R8A7790_CLK_I2C2 29
104#define R8A7790_CLK_I2C1 30
105#define R8A7790_CLK_I2C0 31
106
107#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 000000000000..30f82f286e29
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
11#define __DT_BINDINGS_CLOCK_R8A7791_H__
12
13/* CPG */
14#define R8A7791_CLK_MAIN 0
15#define R8A7791_CLK_PLL0 1
16#define R8A7791_CLK_PLL1 2
17#define R8A7791_CLK_PLL3 3
18#define R8A7791_CLK_LB 4
19#define R8A7791_CLK_QSPI 5
20#define R8A7791_CLK_SDH 6
21#define R8A7791_CLK_SD0 7
22#define R8A7791_CLK_Z 8
23
24/* MSTP0 */
25#define R8A7791_CLK_MSIOF0 0
26
27/* MSTP1 */
28#define R8A7791_CLK_TMU1 11
29#define R8A7791_CLK_TMU3 21
30#define R8A7791_CLK_TMU2 22
31#define R8A7791_CLK_CMT0 24
32#define R8A7791_CLK_TMU0 25
33#define R8A7791_CLK_VSP1_DU1 27
34#define R8A7791_CLK_VSP1_DU0 28
35#define R8A7791_CLK_VSP1_SY 31
36
37/* MSTP2 */
38#define R8A7791_CLK_SCIFA2 2
39#define R8A7791_CLK_SCIFA1 3
40#define R8A7791_CLK_SCIFA0 4
41#define R8A7791_CLK_MSIOF2 5
42#define R8A7791_CLK_SCIFB0 6
43#define R8A7791_CLK_SCIFB1 7
44#define R8A7791_CLK_MSIOF1 8
45#define R8A7791_CLK_SCIFB2 16
46#define R8A7791_CLK_DMAC 18
47
48/* MSTP3 */
49#define R8A7791_CLK_TPU0 4
50#define R8A7791_CLK_SDHI2 11
51#define R8A7791_CLK_SDHI1 12
52#define R8A7791_CLK_SDHI0 14
53#define R8A7791_CLK_MMCIF0 15
54#define R8A7791_CLK_SSUSB 28
55#define R8A7791_CLK_CMT1 29
56#define R8A7791_CLK_USBDMAC0 30
57#define R8A7791_CLK_USBDMAC1 31
58
59/* MSTP5 */
60#define R8A7791_CLK_THERMAL 22
61#define R8A7791_CLK_PWM 23
62
63/* MSTP7 */
64#define R8A7791_CLK_HSUSB 4
65#define R8A7791_CLK_HSCIF2 13
66#define R8A7791_CLK_SCIF5 14
67#define R8A7791_CLK_SCIF4 15
68#define R8A7791_CLK_HSCIF1 16
69#define R8A7791_CLK_HSCIF0 17
70#define R8A7791_CLK_SCIF3 18
71#define R8A7791_CLK_SCIF2 19
72#define R8A7791_CLK_SCIF1 20
73#define R8A7791_CLK_SCIF0 21
74#define R8A7791_CLK_DU1 23
75#define R8A7791_CLK_DU0 24
76#define R8A7791_CLK_LVDS0 26
77
78/* MSTP8 */
79#define R8A7791_CLK_VIN2 9
80#define R8A7791_CLK_VIN1 10
81#define R8A7791_CLK_VIN0 11
82#define R8A7791_CLK_ETHER 13
83#define R8A7791_CLK_SATA1 14
84#define R8A7791_CLK_SATA0 15
85
86/* MSTP9 */
87#define R8A7791_CLK_GPIO7 4
88#define R8A7791_CLK_GPIO6 5
89#define R8A7791_CLK_GPIO5 7
90#define R8A7791_CLK_GPIO4 8
91#define R8A7791_CLK_GPIO3 9
92#define R8A7791_CLK_GPIO2 10
93#define R8A7791_CLK_GPIO1 11
94#define R8A7791_CLK_GPIO0 12
95#define R8A7791_CLK_RCAN1 15
96#define R8A7791_CLK_RCAN0 16
97#define R8A7791_CLK_QSPI_MOD 17
98#define R8A7791_CLK_I2C5 25
99#define R8A7791_CLK_IICDVFS 26
100#define R8A7791_CLK_I2C4 27
101#define R8A7791_CLK_I2C3 28
102#define R8A7791_CLK_I2C2 29
103#define R8A7791_CLK_I2C1 30
104#define R8A7791_CLK_I2C0 31
105
106/* MSTP11 */
107#define R8A7791_CLK_SCIFA3 6
108#define R8A7791_CLK_SCIFA4 7
109#define R8A7791_CLK_SCIFA5 8
110
111#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 614aec417902..6d0d8d8ef31e 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -37,10 +37,10 @@
37#define TEGRA114_CLK_I2S2 18 37#define TEGRA114_CLK_I2S2 18
38#define TEGRA114_CLK_EPP 19 38#define TEGRA114_CLK_EPP 19
39/* 20 (register bit affects vi and vi_sensor) */ 39/* 20 (register bit affects vi and vi_sensor) */
40#define TEGRA114_CLK_GR_2D 21 40#define TEGRA114_CLK_GR2D 21
41#define TEGRA114_CLK_USBD 22 41#define TEGRA114_CLK_USBD 22
42#define TEGRA114_CLK_ISP 23 42#define TEGRA114_CLK_ISP 23
43#define TEGRA114_CLK_GR_3D 24 43#define TEGRA114_CLK_GR3D 24
44/* 25 */ 44/* 25 */
45#define TEGRA114_CLK_DISP2 26 45#define TEGRA114_CLK_DISP2 26
46#define TEGRA114_CLK_DISP1 27 46#define TEGRA114_CLK_DISP1 27
@@ -289,8 +289,8 @@
289#define TEGRA114_CLK_PCLK 261 289#define TEGRA114_CLK_PCLK 261
290#define TEGRA114_CLK_CCLK_G 262 290#define TEGRA114_CLK_CCLK_G 262
291#define TEGRA114_CLK_CCLK_LP 263 291#define TEGRA114_CLK_CCLK_LP 263
292/* 264 */ 292#define TEGRA114_CLK_DFLL_REF 264
293/* 265 */ 293#define TEGRA114_CLK_DFLL_SOC 265
294/* 266 */ 294/* 266 */
295/* 267 */ 295/* 267 */
296/* 268 */ 296/* 268 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
new file mode 100644
index 000000000000..a1116a3b54ef
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -0,0 +1,341 @@
1/*
2 * This header provides constants for binding nvidia,tegra124-car.
3 *
4 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 185 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
13 * above.
14 */
15
16#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
18
19/* 0 */
20/* 1 */
21/* 2 */
22#define TEGRA124_CLK_ISPB 3
23#define TEGRA124_CLK_RTC 4
24#define TEGRA124_CLK_TIMER 5
25#define TEGRA124_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27/* 8 */
28#define TEGRA124_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA124_CLK_I2S1 11
31#define TEGRA124_CLK_I2C1 12
32#define TEGRA124_CLK_NDFLASH 13
33#define TEGRA124_CLK_SDMMC1 14
34#define TEGRA124_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA124_CLK_PWM 17
37#define TEGRA124_CLK_I2S2 18
38/* 20 (register bit affects vi and vi_sensor) */
39#define TEGRA124_CLK_GR_2D 21
40#define TEGRA124_CLK_USBD 22
41#define TEGRA124_CLK_ISP 23
42#define TEGRA124_CLK_GR_3D 24
43/* 25 */
44#define TEGRA124_CLK_DISP2 26
45#define TEGRA124_CLK_DISP1 27
46#define TEGRA124_CLK_HOST1X 28
47#define TEGRA124_CLK_VCP 29
48#define TEGRA124_CLK_I2S0 30
49/* 31 */
50
51/* 32 */
52/* 33 */
53#define TEGRA124_CLK_APBDMA 34
54/* 35 */
55#define TEGRA124_CLK_KBC 36
56/* 37 */
57/* 38 */
58/* 39 (register bit affects fuse and fuse_burn) */
59#define TEGRA124_CLK_KFUSE 40
60#define TEGRA124_CLK_SBC1 41
61#define TEGRA124_CLK_NOR 42
62/* 43 */
63#define TEGRA124_CLK_SBC2 44
64/* 45 */
65#define TEGRA124_CLK_SBC3 46
66#define TEGRA124_CLK_I2C5 47
67#define TEGRA124_CLK_DSIA 48
68/* 49 */
69#define TEGRA124_CLK_MIPI 50
70#define TEGRA124_CLK_HDMI 51
71#define TEGRA124_CLK_CSI 52
72/* 53 */
73#define TEGRA124_CLK_I2C2 54
74#define TEGRA124_CLK_UARTC 55
75#define TEGRA124_CLK_MIPI_CAL 56
76#define TEGRA124_CLK_EMC 57
77#define TEGRA124_CLK_USB2 58
78#define TEGRA124_CLK_USB3 59
79/* 60 */
80#define TEGRA124_CLK_VDE 61
81#define TEGRA124_CLK_BSEA 62
82#define TEGRA124_CLK_BSEV 63
83
84/* 64 */
85#define TEGRA124_CLK_UARTD 65
86#define TEGRA124_CLK_UARTE 66
87#define TEGRA124_CLK_I2C3 67
88#define TEGRA124_CLK_SBC4 68
89#define TEGRA124_CLK_SDMMC3 69
90#define TEGRA124_CLK_PCIE 70
91#define TEGRA124_CLK_OWR 71
92#define TEGRA124_CLK_AFI 72
93#define TEGRA124_CLK_CSITE 73
94/* 74 */
95/* 75 */
96#define TEGRA124_CLK_LA 76
97#define TEGRA124_CLK_TRACE 77
98#define TEGRA124_CLK_SOC_THERM 78
99#define TEGRA124_CLK_DTV 79
100#define TEGRA124_CLK_NDSPEED 80
101#define TEGRA124_CLK_I2CSLOW 81
102#define TEGRA124_CLK_DSIB 82
103#define TEGRA124_CLK_TSEC 83
104/* 84 */
105/* 85 */
106/* 86 */
107/* 87 */
108/* 88 */
109#define TEGRA124_CLK_XUSB_HOST 89
110/* 90 */
111#define TEGRA124_CLK_MSENC 91
112#define TEGRA124_CLK_CSUS 92
113/* 93 */
114/* 94 */
115/* 95 (bit affects xusb_dev and xusb_dev_src) */
116
117/* 96 */
118/* 97 */
119/* 98 */
120#define TEGRA124_CLK_MSELECT 99
121#define TEGRA124_CLK_TSENSOR 100
122#define TEGRA124_CLK_I2S3 101
123#define TEGRA124_CLK_I2S4 102
124#define TEGRA124_CLK_I2C4 103
125#define TEGRA124_CLK_SBC5 104
126#define TEGRA124_CLK_SBC6 105
127#define TEGRA124_CLK_D_AUDIO 106
128#define TEGRA124_CLK_APBIF 107
129#define TEGRA124_CLK_DAM0 108
130#define TEGRA124_CLK_DAM1 109
131#define TEGRA124_CLK_DAM2 110
132#define TEGRA124_CLK_HDA2CODEC_2X 111
133/* 112 */
134#define TEGRA124_CLK_AUDIO0_2X 113
135#define TEGRA124_CLK_AUDIO1_2X 114
136#define TEGRA124_CLK_AUDIO2_2X 115
137#define TEGRA124_CLK_AUDIO3_2X 116
138#define TEGRA124_CLK_AUDIO4_2X 117
139#define TEGRA124_CLK_SPDIF_2X 118
140#define TEGRA124_CLK_ACTMON 119
141#define TEGRA124_CLK_EXTERN1 120
142#define TEGRA124_CLK_EXTERN2 121
143#define TEGRA124_CLK_EXTERN3 122
144#define TEGRA124_CLK_SATA_OOB 123
145#define TEGRA124_CLK_SATA 124
146#define TEGRA124_CLK_HDA 125
147/* 126 */
148#define TEGRA124_CLK_SE 127
149
150#define TEGRA124_CLK_HDA2HDMI 128
151#define TEGRA124_CLK_SATA_COLD 129
152/* 130 */
153/* 131 */
154/* 132 */
155/* 133 */
156/* 134 */
157/* 135 */
158/* 136 */
159/* 137 */
160/* 138 */
161/* 139 */
162/* 140 */
163/* 141 */
164/* 142 */
165/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
166/* xusb_host_src and xusb_ss_src) */
167#define TEGRA124_CLK_CILAB 144
168#define TEGRA124_CLK_CILCD 145
169#define TEGRA124_CLK_CILE 146
170#define TEGRA124_CLK_DSIALP 147
171#define TEGRA124_CLK_DSIBLP 148
172#define TEGRA124_CLK_ENTROPY 149
173#define TEGRA124_CLK_DDS 150
174/* 151 */
175#define TEGRA124_CLK_DP2 152
176#define TEGRA124_CLK_AMX 153
177#define TEGRA124_CLK_ADX 154
178/* 155 (bit affects dfll_ref and dfll_soc) */
179#define TEGRA124_CLK_XUSB_SS 156
180/* 157 */
181/* 158 */
182/* 159 */
183
184/* 160 */
185/* 161 */
186/* 162 */
187/* 163 */
188/* 164 */
189/* 165 */
190#define TEGRA124_CLK_I2C6 166
191/* 167 */
192/* 168 */
193/* 169 */
194/* 170 */
195#define TEGRA124_CLK_VIM2_CLK 171
196/* 172 */
197/* 173 */
198/* 174 */
199/* 175 */
200#define TEGRA124_CLK_HDMI_AUDIO 176
201#define TEGRA124_CLK_CLK72MHZ 177
202#define TEGRA124_CLK_VIC03 178
203/* 179 */
204#define TEGRA124_CLK_ADX1 180
205#define TEGRA124_CLK_DPAUX 181
206#define TEGRA124_CLK_SOR0 182
207/* 183 */
208#define TEGRA124_CLK_GPU 184
209#define TEGRA124_CLK_AMX1 185
210/* 186 */
211/* 187 */
212/* 188 */
213/* 189 */
214/* 190 */
215/* 191 */
216#define TEGRA124_CLK_UARTB 192
217#define TEGRA124_CLK_VFIR 193
218#define TEGRA124_CLK_SPDIF_IN 194
219#define TEGRA124_CLK_SPDIF_OUT 195
220#define TEGRA124_CLK_VI 196
221#define TEGRA124_CLK_VI_SENSOR 197
222#define TEGRA124_CLK_FUSE 198
223#define TEGRA124_CLK_FUSE_BURN 199
224#define TEGRA124_CLK_CLK_32K 200
225#define TEGRA124_CLK_CLK_M 201
226#define TEGRA124_CLK_CLK_M_DIV2 202
227#define TEGRA124_CLK_CLK_M_DIV4 203
228#define TEGRA124_CLK_PLL_REF 204
229#define TEGRA124_CLK_PLL_C 205
230#define TEGRA124_CLK_PLL_C_OUT1 206
231#define TEGRA124_CLK_PLL_C2 207
232#define TEGRA124_CLK_PLL_C3 208
233#define TEGRA124_CLK_PLL_M 209
234#define TEGRA124_CLK_PLL_M_OUT1 210
235#define TEGRA124_CLK_PLL_P 211
236#define TEGRA124_CLK_PLL_P_OUT1 212
237#define TEGRA124_CLK_PLL_P_OUT2 213
238#define TEGRA124_CLK_PLL_P_OUT3 214
239#define TEGRA124_CLK_PLL_P_OUT4 215
240#define TEGRA124_CLK_PLL_A 216
241#define TEGRA124_CLK_PLL_A_OUT0 217
242#define TEGRA124_CLK_PLL_D 218
243#define TEGRA124_CLK_PLL_D_OUT0 219
244#define TEGRA124_CLK_PLL_D2 220
245#define TEGRA124_CLK_PLL_D2_OUT0 221
246#define TEGRA124_CLK_PLL_U 222
247#define TEGRA124_CLK_PLL_U_480M 223
248
249#define TEGRA124_CLK_PLL_U_60M 224
250#define TEGRA124_CLK_PLL_U_48M 225
251#define TEGRA124_CLK_PLL_U_12M 226
252#define TEGRA124_CLK_PLL_X 227
253#define TEGRA124_CLK_PLL_X_OUT0 228
254#define TEGRA124_CLK_PLL_RE_VCO 229
255#define TEGRA124_CLK_PLL_RE_OUT 230
256#define TEGRA124_CLK_PLL_E 231
257#define TEGRA124_CLK_SPDIF_IN_SYNC 232
258#define TEGRA124_CLK_I2S0_SYNC 233
259#define TEGRA124_CLK_I2S1_SYNC 234
260#define TEGRA124_CLK_I2S2_SYNC 235
261#define TEGRA124_CLK_I2S3_SYNC 236
262#define TEGRA124_CLK_I2S4_SYNC 237
263#define TEGRA124_CLK_VIMCLK_SYNC 238
264#define TEGRA124_CLK_AUDIO0 239
265#define TEGRA124_CLK_AUDIO1 240
266#define TEGRA124_CLK_AUDIO2 241
267#define TEGRA124_CLK_AUDIO3 242
268#define TEGRA124_CLK_AUDIO4 243
269#define TEGRA124_CLK_SPDIF 244
270#define TEGRA124_CLK_CLK_OUT_1 245
271#define TEGRA124_CLK_CLK_OUT_2 246
272#define TEGRA124_CLK_CLK_OUT_3 247
273#define TEGRA124_CLK_BLINK 248
274/* 249 */
275/* 250 */
276/* 251 */
277#define TEGRA124_CLK_XUSB_HOST_SRC 252
278#define TEGRA124_CLK_XUSB_FALCON_SRC 253
279#define TEGRA124_CLK_XUSB_FS_SRC 254
280#define TEGRA124_CLK_XUSB_SS_SRC 255
281
282#define TEGRA124_CLK_XUSB_DEV_SRC 256
283#define TEGRA124_CLK_XUSB_DEV 257
284#define TEGRA124_CLK_XUSB_HS_SRC 258
285#define TEGRA124_CLK_SCLK 259
286#define TEGRA124_CLK_HCLK 260
287#define TEGRA124_CLK_PCLK 261
288#define TEGRA124_CLK_CCLK_G 262
289#define TEGRA124_CLK_CCLK_LP 263
290#define TEGRA124_CLK_DFLL_REF 264
291#define TEGRA124_CLK_DFLL_SOC 265
292#define TEGRA124_CLK_VI_SENSOR2 266
293#define TEGRA124_CLK_PLL_P_OUT5 267
294#define TEGRA124_CLK_CML0 268
295#define TEGRA124_CLK_CML1 269
296#define TEGRA124_CLK_PLL_C4 270
297#define TEGRA124_CLK_PLL_DP 271
298#define TEGRA124_CLK_PLL_E_MUX 272
299/* 273 */
300/* 274 */
301/* 275 */
302/* 276 */
303/* 277 */
304/* 278 */
305/* 279 */
306/* 280 */
307/* 281 */
308/* 282 */
309/* 283 */
310/* 284 */
311/* 285 */
312/* 286 */
313/* 287 */
314
315/* 288 */
316/* 289 */
317/* 290 */
318/* 291 */
319/* 292 */
320/* 293 */
321/* 294 */
322/* 295 */
323/* 296 */
324/* 297 */
325/* 298 */
326/* 299 */
327#define TEGRA124_CLK_AUDIO0_MUX 300
328#define TEGRA124_CLK_AUDIO1_MUX 301
329#define TEGRA124_CLK_AUDIO2_MUX 302
330#define TEGRA124_CLK_AUDIO3_MUX 303
331#define TEGRA124_CLK_AUDIO4_MUX 304
332#define TEGRA124_CLK_SPDIF_MUX 305
333#define TEGRA124_CLK_CLK_OUT_1_MUX 306
334#define TEGRA124_CLK_CLK_OUT_2_MUX 307
335#define TEGRA124_CLK_CLK_OUT_3_MUX 308
336#define TEGRA124_CLK_DSIA_MUX 309
337#define TEGRA124_CLK_DSIB_MUX 310
338#define TEGRA124_CLK_SOR0_LVDS 311
339#define TEGRA124_CLK_CLK_MAX 312
340
341#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c..9406207cfac8 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -92,7 +92,7 @@
92#define TEGRA20_CLK_OWR 71 92#define TEGRA20_CLK_OWR 71
93#define TEGRA20_CLK_AFI 72 93#define TEGRA20_CLK_AFI 72
94#define TEGRA20_CLK_CSITE 73 94#define TEGRA20_CLK_CSITE 73
95#define TEGRA20_CLK_PCIE_XCLK 74 95/* 74 */
96#define TEGRA20_CLK_AVPUCQ 75 96#define TEGRA20_CLK_AVPUCQ 75
97#define TEGRA20_CLK_LA 76 97#define TEGRA20_CLK_LA 76
98/* 77 */ 98/* 77 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index e40fae8f9a8d..889e49ba0aa3 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -92,7 +92,7 @@
92#define TEGRA30_CLK_OWR 71 92#define TEGRA30_CLK_OWR 71
93#define TEGRA30_CLK_AFI 72 93#define TEGRA30_CLK_AFI 72
94#define TEGRA30_CLK_CSITE 73 94#define TEGRA30_CLK_CSITE 73
95#define TEGRA30_CLK_PCIEX 74 95/* 74 */
96#define TEGRA30_CLK_AVPUCQ 75 96#define TEGRA30_CLK_AVPUCQ 75
97#define TEGRA30_CLK_LA 76 97#define TEGRA30_CLK_LA 76
98/* 77 */ 98/* 77 */
@@ -260,6 +260,14 @@
260/* 298 */ 260/* 298 */
261/* 299 */ 261/* 299 */
262#define TEGRA30_CLK_CLK_OUT_1_MUX 300 262#define TEGRA30_CLK_CLK_OUT_1_MUX 300
263#define TEGRA30_CLK_CLK_MAX 301 263#define TEGRA30_CLK_CLK_OUT_2_MUX 301
264#define TEGRA30_CLK_CLK_OUT_3_MUX 302
265#define TEGRA30_CLK_AUDIO0_MUX 303
266#define TEGRA30_CLK_AUDIO1_MUX 304
267#define TEGRA30_CLK_AUDIO2_MUX 305
268#define TEGRA30_CLK_AUDIO3_MUX 306
269#define TEGRA30_CLK_AUDIO4_MUX 307
270#define TEGRA30_CLK_SPDIF_MUX 308
271#define TEGRA30_CLK_CLK_MAX 309
264 272
265#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 273#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 4d179c00f081..197dc28b676e 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -43,6 +43,7 @@
43#define TEGRA_GPIO_BANK_ID_CC 28 43#define TEGRA_GPIO_BANK_ID_CC 28
44#define TEGRA_GPIO_BANK_ID_DD 29 44#define TEGRA_GPIO_BANK_ID_DD 29
45#define TEGRA_GPIO_BANK_ID_EE 30 45#define TEGRA_GPIO_BANK_ID_EE 30
46#define TEGRA_GPIO_BANK_ID_FF 31
46 47
47#define TEGRA_GPIO(bank, offset) \ 48#define TEGRA_GPIO(bank, offset) \
48 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) 49 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 000000000000..ebafa498be0f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,45 @@
1/*
2 * This header provides constants for Tegra pinctrl bindings.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
19#define _DT_BINDINGS_PINCTRL_TEGRA_H
20
21/*
22 * Enable/disable for diffeent dt properties. This is applicable for
23 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
24 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
25 */
26#define TEGRA_PIN_DISABLE 0
27#define TEGRA_PIN_ENABLE 1
28
29#define TEGRA_PIN_PULL_NONE 0
30#define TEGRA_PIN_PULL_DOWN 1
31#define TEGRA_PIN_PULL_UP 2
32
33/* Low power mode driver */
34#define TEGRA_PIN_LP_DRIVE_DIV_8 0
35#define TEGRA_PIN_LP_DRIVE_DIV_4 1
36#define TEGRA_PIN_LP_DRIVE_DIV_2 2
37#define TEGRA_PIN_LP_DRIVE_DIV_1 3
38
39/* Rising/Falling slew rate */
40#define TEGRA_PIN_SLEW_RATE_FASTEST 0
41#define TEGRA_PIN_SLEW_RATE_FAST 1
42#define TEGRA_PIN_SLEW_RATE_SLOW 2
43#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
44
45#endif
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
new file mode 100644
index 000000000000..a6911ebbd02a
--- /dev/null
+++ b/include/linux/clk/at91_pmc.h
@@ -0,0 +1,192 @@
1/*
2 * include/linux/clk/at91_pmc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Power Management Controller (PMC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PMC_H
17#define AT91_PMC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_pmc_base;
21
22#define at91_pmc_read(field) \
23 __raw_readl(at91_pmc_base + field)
24
25#define at91_pmc_write(field, value) \
26 __raw_writel(value, at91_pmc_base + field)
27#else
28.extern at91_pmc_base
29#endif
30
31#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
32#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
33
34#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
35#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
36#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
37#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
38#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
39#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
40#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
41#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
42#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
43#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
44#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
45#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
46#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
47#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
48
49#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
50#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
51#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
52
53#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
54#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
55#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
56#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
57#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
58
59#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
60#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
61#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
62#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
63#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
64#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
65#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
66#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
67
68#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
69#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
70#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
71
72#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
73#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
74#define AT91_PMC_DIV (0xff << 0) /* Divider */
75#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
76#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
77#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
78#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
79#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
80#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f)
81#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
82#define AT91_PMC_USBDIV_1 (0 << 28)
83#define AT91_PMC_USBDIV_2 (1 << 28)
84#define AT91_PMC_USBDIV_4 (2 << 28)
85#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
86
87#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
88#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
89#define AT91_PMC_CSS_SLOW (0 << 0)
90#define AT91_PMC_CSS_MAIN (1 << 0)
91#define AT91_PMC_CSS_PLLA (2 << 0)
92#define AT91_PMC_CSS_PLLB (3 << 0)
93#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
94#define PMC_PRES_OFFSET 2
95#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
96#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
97#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
98#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
99#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
100#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
101#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
102#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
103#define PMC_ALT_PRES_OFFSET 4
104#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
105#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
106#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
107#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
108#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
109#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
110#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
111#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
112#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
113#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
114#define AT91RM9200_PMC_MDIV_2 (1 << 8)
115#define AT91RM9200_PMC_MDIV_3 (2 << 8)
116#define AT91RM9200_PMC_MDIV_4 (3 << 8)
117#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
118#define AT91SAM9_PMC_MDIV_2 (1 << 8)
119#define AT91SAM9_PMC_MDIV_4 (2 << 8)
120#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
121#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
122#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
123#define AT91_PMC_PDIV_1 (0 << 12)
124#define AT91_PMC_PDIV_2 (1 << 12)
125#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
126#define AT91_PMC_PLLADIV2_OFF (0 << 12)
127#define AT91_PMC_PLLADIV2_ON (1 << 12)
128
129#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
130#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
131#define AT91_PMC_USBS_PLLA (0 << 0)
132#define AT91_PMC_USBS_UPLL (1 << 0)
133#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
134#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
135#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
136#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
137
138#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
139#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
140#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
141#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
142
143#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
144#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
145#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
146#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
147#define AT91_PMC_CSSMCK_CSS (0 << 8)
148#define AT91_PMC_CSSMCK_MCK (1 << 8)
149
150#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
151#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
152#define AT91_PMC_SR 0x68 /* Status Register */
153#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
154#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
155#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
156#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
157#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
158#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
159#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
160#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
161#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
162#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
163#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
164#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
165#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
166
167#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
168
169#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
170#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
171#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
172#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
173
174#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
175#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
176#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
177
178#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
179#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
180#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
181
182#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
183#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
184#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
185#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
186#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
187#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
188#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */
189#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
190#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
191
192#endif
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
new file mode 100644
index 000000000000..f9bf080a1123
--- /dev/null
+++ b/include/linux/clk/shmobile.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __LINUX_CLK_SHMOBILE_H_
13#define __LINUX_CLK_SHMOBILE_H_
14
15#include <linux/types.h>
16
17void rcar_gen2_clocks_init(u32 mode);
18
19#endif
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 23a0ceee831f..3ca9fca827a2 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,13 +120,6 @@ static inline void tegra_cpu_clock_resume(void)
120} 120}
121#endif 121#endif
122 122
123#ifdef CONFIG_ARCH_TEGRA
124void tegra_periph_reset_deassert(struct clk *c);
125void tegra_periph_reset_assert(struct clk *c);
126#else
127static inline void tegra_periph_reset_deassert(struct clk *c) {}
128static inline void tegra_periph_reset_assert(struct clk *c) {}
129#endif
130void tegra_clocks_apply_init_table(void); 123void tegra_clocks_apply_init_table(void);
131 124
132#endif /* __LINUX_CLK_TEGRA_H_ */ 125#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 41cf0c399288..bae1568416f8 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -22,6 +22,7 @@
22#define LINUX_DMAENGINE_H 22#define LINUX_DMAENGINE_H
23 23
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/err.h>
25#include <linux/uio.h> 26#include <linux/uio.h>
26#include <linux/bug.h> 27#include <linux/bug.h>
27#include <linux/scatterlist.h> 28#include <linux/scatterlist.h>
@@ -1040,6 +1041,8 @@ enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1040void dma_issue_pending_all(void); 1041void dma_issue_pending_all(void);
1041struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1042struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1042 dma_filter_fn fn, void *fn_param); 1043 dma_filter_fn fn, void *fn_param);
1044struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1045 const char *name);
1043struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1046struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1044void dma_release_channel(struct dma_chan *chan); 1047void dma_release_channel(struct dma_chan *chan);
1045#else 1048#else
@@ -1063,6 +1066,11 @@ static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1063{ 1066{
1064 return NULL; 1067 return NULL;
1065} 1068}
1069static inline struct dma_chan *dma_request_slave_channel_reason(
1070 struct device *dev, const char *name)
1071{
1072 return ERR_PTR(-ENODEV);
1073}
1066static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1074static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1067 const char *name) 1075 const char *name)
1068{ 1076{
@@ -1079,6 +1087,7 @@ int dma_async_device_register(struct dma_device *device);
1079void dma_async_device_unregister(struct dma_device *device); 1087void dma_async_device_unregister(struct dma_device *device);
1080void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1088void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1081struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); 1089struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1090struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1082struct dma_chan *net_dma_find_channel(void); 1091struct dma_chan *net_dma_find_channel(void);
1083#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 1092#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1084#define dma_request_slave_channel_compat(mask, x, y, dev, name) \ 1093#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index fb90ef5eb038..282309d7c4dc 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -82,8 +82,10 @@
82 * operation, if several modes of operation are supported these can be 82 * operation, if several modes of operation are supported these can be
83 * passed in the argument on a custom form, else just use argument 1 83 * passed in the argument on a custom form, else just use argument 1
84 * to indicate low power mode, argument 0 turns low power mode off. 84 * to indicate low power mode, argument 0 turns low power mode off.
85 * @PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument 85 * @PIN_CONFIG_OUTPUT: this will configure the pin as an output. Use argument
86 * 1 to indicate high level, argument 0 to indicate low level. 86 * 1 to indicate high level, argument 0 to indicate low level. (Please
87 * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a
88 * discussion around this parameter.)
87 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if 89 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
88 * you need to pass in custom configurations to the pin controller, use 90 * you need to pass in custom configurations to the pin controller, use
89 * PIN_CONFIG_END+1 as the base offset. 91 * PIN_CONFIG_END+1 as the base offset.
diff --git a/include/linux/platform_data/clocksource-nomadik-mtu.h b/include/linux/platform_data/clocksource-nomadik-mtu.h
deleted file mode 100644
index 80088973b734..000000000000
--- a/include/linux/platform_data/clocksource-nomadik-mtu.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __PLAT_MTU_H
2#define __PLAT_MTU_H
3
4void nmdk_timer_init(void __iomem *base, int irq);
5void nmdk_clkevt_reset(void);
6void nmdk_clksrc_reset(void);
7
8#endif /* __PLAT_MTU_H */
9
diff --git a/include/linux/platform_data/pinctrl-nomadik.h b/include/linux/platform_data/pinctrl-nomadik.h
deleted file mode 100644
index abf5bed84df3..000000000000
--- a/include/linux/platform_data/pinctrl-nomadik.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * Structures and registers for GPIO access in the Nomadik SoC
3 *
4 * Copyright (C) 2008 STMicroelectronics
5 * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PLAT_NOMADIK_GPIO
14#define __PLAT_NOMADIK_GPIO
15
16/*
17 * pin configurations are represented by 32-bit integers:
18 *
19 * bit 0.. 8 - Pin Number (512 Pins Maximum)
20 * bit 9..10 - Alternate Function Selection
21 * bit 11..12 - Pull up/down state
22 * bit 13 - Sleep mode behaviour
23 * bit 14 - Direction
24 * bit 15 - Value (if output)
25 * bit 16..18 - SLPM pull up/down state
26 * bit 19..20 - SLPM direction
27 * bit 21..22 - SLPM Value (if output)
28 * bit 23..25 - PDIS value (if input)
29 * bit 26 - Gpio mode
30 * bit 27 - Sleep mode
31 *
32 * to facilitate the definition, the following macros are provided
33 *
34 * PIN_CFG_DEFAULT - default config (0):
35 * pull up/down = disabled
36 * sleep mode = input/wakeup
37 * direction = input
38 * value = low
39 * SLPM direction = same as normal
40 * SLPM pull = same as normal
41 * SLPM value = same as normal
42 *
43 * PIN_CFG - default config with alternate function
44 */
45
46typedef unsigned long pin_cfg_t;
47
48#define PIN_NUM_MASK 0x1ff
49#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
50
51#define PIN_ALT_SHIFT 9
52#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
53#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
54#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
55#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
56#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
57#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
58
59#define PIN_PULL_SHIFT 11
60#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
61#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
62#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
63#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
64#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
65
66#define PIN_SLPM_SHIFT 13
67#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
68#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
69#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
70#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
71/* These two replace the above in DB8500v2+ */
72#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
73#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
74#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
75
76#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
77#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
78
79#define PIN_DIR_SHIFT 14
80#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
81#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
82#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
83#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
84
85#define PIN_VAL_SHIFT 15
86#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
87#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
88#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
89#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
90
91#define PIN_SLPM_PULL_SHIFT 16
92#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
93#define PIN_SLPM_PULL(x) \
94 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
95#define PIN_SLPM_PULL_NONE \
96 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
97#define PIN_SLPM_PULL_UP \
98 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
99#define PIN_SLPM_PULL_DOWN \
100 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
101
102#define PIN_SLPM_DIR_SHIFT 19
103#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
104#define PIN_SLPM_DIR(x) \
105 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
106#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
107#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
108
109#define PIN_SLPM_VAL_SHIFT 21
110#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
111#define PIN_SLPM_VAL(x) \
112 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
113#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
114#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
115
116#define PIN_SLPM_PDIS_SHIFT 23
117#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
118#define PIN_SLPM_PDIS(x) \
119 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
120#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
121#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
122#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
123
124#define PIN_LOWEMI_SHIFT 25
125#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
126#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
127#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
128#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
129
130#define PIN_GPIOMODE_SHIFT 26
131#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
132#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
133#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
134#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
135
136#define PIN_SLEEPMODE_SHIFT 27
137#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
138#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
139#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
140#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
141
142
143/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
144#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
145#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
146#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
147#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
148#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
149
150#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
151#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
152#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
153#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
154#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
155
156#define PIN_CFG_DEFAULT (0)
157
158#define PIN_CFG(num, alt) \
159 (PIN_CFG_DEFAULT |\
160 (PIN_NUM(num) | PIN_##alt))
161
162#define PIN_CFG_INPUT(num, alt, pull) \
163 (PIN_CFG_DEFAULT |\
164 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
165
166#define PIN_CFG_OUTPUT(num, alt, val) \
167 (PIN_CFG_DEFAULT |\
168 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
169
170/*
171 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
172 * the "gpio" namespace for generic and cross-machine functions
173 */
174
175#define GPIO_BLOCK_SHIFT 5
176#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
177
178/* Register in the logic block */
179#define NMK_GPIO_DAT 0x00
180#define NMK_GPIO_DATS 0x04
181#define NMK_GPIO_DATC 0x08
182#define NMK_GPIO_PDIS 0x0c
183#define NMK_GPIO_DIR 0x10
184#define NMK_GPIO_DIRS 0x14
185#define NMK_GPIO_DIRC 0x18
186#define NMK_GPIO_SLPC 0x1c
187#define NMK_GPIO_AFSLA 0x20
188#define NMK_GPIO_AFSLB 0x24
189#define NMK_GPIO_LOWEMI 0x28
190
191#define NMK_GPIO_RIMSC 0x40
192#define NMK_GPIO_FIMSC 0x44
193#define NMK_GPIO_IS 0x48
194#define NMK_GPIO_IC 0x4c
195#define NMK_GPIO_RWIMSC 0x50
196#define NMK_GPIO_FWIMSC 0x54
197#define NMK_GPIO_WKS 0x58
198/* These appear in DB8540 and later ASICs */
199#define NMK_GPIO_EDGELEVEL 0x5C
200#define NMK_GPIO_LEVEL 0x60
201
202/* Alternate functions: function C is set in hw by setting both A and B */
203#define NMK_GPIO_ALT_GPIO 0
204#define NMK_GPIO_ALT_A 1
205#define NMK_GPIO_ALT_B 2
206#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
207
208#define NMK_GPIO_ALT_CX_SHIFT 2
209#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
210#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
211#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
212#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
213
214/* Pull up/down values */
215enum nmk_gpio_pull {
216 NMK_GPIO_PULL_NONE,
217 NMK_GPIO_PULL_UP,
218 NMK_GPIO_PULL_DOWN,
219};
220
221/* Sleep mode */
222enum nmk_gpio_slpm {
223 NMK_GPIO_SLPM_INPUT,
224 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
225 NMK_GPIO_SLPM_NOCHANGE,
226 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
227};
228
229/*
230 * Platform data to register a block: only the initial gpio/irq number.
231 */
232struct nmk_gpio_platform_data {
233 char *name;
234 int first_gpio;
235 int first_irq;
236 int num_gpio;
237 u32 (*get_secondary_status)(unsigned int bank);
238 void (*set_ioforce)(bool enable);
239 bool supports_sleepmode;
240};
241
242#endif /* __PLAT_NOMADIK_GPIO */
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index fd4498329c7c..afe442d2629a 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -19,6 +19,7 @@
19#define _MACH_TEGRA_POWERGATE_H_ 19#define _MACH_TEGRA_POWERGATE_H_
20 20
21struct clk; 21struct clk;
22struct reset_control;
22 23
23#define TEGRA_POWERGATE_CPU 0 24#define TEGRA_POWERGATE_CPU 0
24#define TEGRA_POWERGATE_3D 1 25#define TEGRA_POWERGATE_3D 1
@@ -52,7 +53,8 @@ int tegra_powergate_power_off(int id);
52int tegra_powergate_remove_clamping(int id); 53int tegra_powergate_remove_clamping(int id);
53 54
54/* Must be called with clk disabled, and returns with clk enabled */ 55/* Must be called with clk disabled, and returns with clk enabled */
55int tegra_powergate_sequence_power_up(int id, struct clk *clk); 56int tegra_powergate_sequence_power_up(int id, struct clk *clk,
57 struct reset_control *rst);
56#else 58#else
57static inline int tegra_powergate_is_powered(int id) 59static inline int tegra_powergate_is_powered(int id)
58{ 60{
@@ -74,7 +76,8 @@ static inline int tegra_powergate_remove_clamping(int id)
74 return -ENOSYS; 76 return -ENOSYS;
75} 77}
76 78
77static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk) 79static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
80 struct reset_control *rst);
78{ 81{
79 return -ENOSYS; 82 return -ENOSYS;
80} 83}
diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h
index 15017311f2e9..eb73a3a39ec2 100644
--- a/include/sound/dmaengine_pcm.h
+++ b/include/sound/dmaengine_pcm.h
@@ -114,6 +114,10 @@ void snd_dmaengine_pcm_set_config_from_dai_data(
114 * @compat_filter_fn: Will be used as the filter function when requesting a 114 * @compat_filter_fn: Will be used as the filter function when requesting a
115 * channel for platforms which do not use devicetree. The filter parameter 115 * channel for platforms which do not use devicetree. The filter parameter
116 * will be the DAI's DMA data. 116 * will be the DAI's DMA data.
117 * @dma_dev: If set, request DMA channel on this device rather than the DAI
118 * device.
119 * @chan_names: If set, these custom DMA channel names will be requested at
120 * registration time.
117 * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM. 121 * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM.
118 * @prealloc_buffer_size: Size of the preallocated audio buffer. 122 * @prealloc_buffer_size: Size of the preallocated audio buffer.
119 * 123 *
@@ -130,6 +134,8 @@ struct snd_dmaengine_pcm_config {
130 struct snd_soc_pcm_runtime *rtd, 134 struct snd_soc_pcm_runtime *rtd,
131 struct snd_pcm_substream *substream); 135 struct snd_pcm_substream *substream);
132 dma_filter_fn compat_filter_fn; 136 dma_filter_fn compat_filter_fn;
137 struct device *dma_dev;
138 const char *chan_names[SNDRV_PCM_STREAM_LAST + 1];
133 139
134 const struct snd_pcm_hardware *pcm_hardware; 140 const struct snd_pcm_hardware *pcm_hardware;
135 unsigned int prealloc_buffer_size; 141 unsigned int prealloc_buffer_size;
@@ -140,6 +146,10 @@ int snd_dmaengine_pcm_register(struct device *dev,
140 unsigned int flags); 146 unsigned int flags);
141void snd_dmaengine_pcm_unregister(struct device *dev); 147void snd_dmaengine_pcm_unregister(struct device *dev);
142 148
149int devm_snd_dmaengine_pcm_register(struct device *dev,
150 const struct snd_dmaengine_pcm_config *config,
151 unsigned int flags);
152
143int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream, 153int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream,
144 struct snd_pcm_hw_params *params, 154 struct snd_pcm_hw_params *params,
145 struct dma_slave_config *slave_config); 155 struct dma_slave_config *slave_config);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 08:38:59 -0500