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-rw-r--r--include/asm-i386/tsc.h68
-rw-r--r--include/asm-i386/vmi_time.h8
-rw-r--r--include/asm-mips/bitops.h56
-rw-r--r--include/asm-mips/mips_mt.h2
-rw-r--r--include/asm-mips/smtc.h3
-rw-r--r--include/asm-mips/smtc_ipi.h2
-rw-r--r--include/asm-mips/spinlock.h4
-rw-r--r--include/asm-mips/uaccess.h2
-rw-r--r--include/asm-mips/unistd.h18
-rw-r--r--include/asm-x86_64/tsc.h68
-rw-r--r--include/linux/audit.h1
-rw-r--r--include/linux/hrtimer.h4
-rw-r--r--include/linux/igmp.h2
-rw-r--r--include/linux/mmc/host.h8
-rw-r--r--include/linux/mv643xx.h1
-rw-r--r--include/linux/ncp_fs_sb.h2
-rw-r--r--include/linux/sunrpc/svc.h2
-rw-r--r--include/linux/sunrpc/svcsock.h2
-rw-r--r--include/sound/version.h4
19 files changed, 151 insertions, 106 deletions
diff --git a/include/asm-i386/tsc.h b/include/asm-i386/tsc.h
index e997891cc7cc..84016ff481b9 100644
--- a/include/asm-i386/tsc.h
+++ b/include/asm-i386/tsc.h
@@ -1 +1,67 @@
1#include <asm-x86_64/tsc.h> 1/*
2 * linux/include/asm-i386/tsc.h
3 *
4 * i386 TSC related functions
5 */
6#ifndef _ASM_i386_TSC_H
7#define _ASM_i386_TSC_H
8
9#include <asm/processor.h>
10
11/*
12 * Standard way to access the cycle counter.
13 */
14typedef unsigned long long cycles_t;
15
16extern unsigned int cpu_khz;
17extern unsigned int tsc_khz;
18
19static inline cycles_t get_cycles(void)
20{
21 unsigned long long ret = 0;
22
23#ifndef CONFIG_X86_TSC
24 if (!cpu_has_tsc)
25 return 0;
26#endif
27
28#if defined(CONFIG_X86_GENERIC) || defined(CONFIG_X86_TSC)
29 rdtscll(ret);
30#endif
31 return ret;
32}
33
34/* Like get_cycles, but make sure the CPU is synchronized. */
35static __always_inline cycles_t get_cycles_sync(void)
36{
37 unsigned long long ret;
38#ifdef X86_FEATURE_SYNC_RDTSC
39 unsigned eax;
40
41 /*
42 * Don't do an additional sync on CPUs where we know
43 * RDTSC is already synchronous:
44 */
45 alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
46 "=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
47#else
48 sync_core();
49#endif
50 rdtscll(ret);
51
52 return ret;
53}
54
55extern void tsc_init(void);
56extern void mark_tsc_unstable(void);
57extern int unsynchronized_tsc(void);
58extern void init_tsc_clocksource(void);
59
60/*
61 * Boot-time check whether the TSCs are synchronized across
62 * all CPUs/cores:
63 */
64extern void check_tsc_sync_source(int cpu);
65extern void check_tsc_sync_target(void);
66
67#endif
diff --git a/include/asm-i386/vmi_time.h b/include/asm-i386/vmi_time.h
index 1f971eb7f71e..94d0a12a4114 100644
--- a/include/asm-i386/vmi_time.h
+++ b/include/asm-i386/vmi_time.h
@@ -61,6 +61,14 @@ extern void apic_vmi_timer_interrupt(void);
61#ifdef CONFIG_NO_IDLE_HZ 61#ifdef CONFIG_NO_IDLE_HZ
62extern int vmi_stop_hz_timer(void); 62extern int vmi_stop_hz_timer(void);
63extern void vmi_account_time_restart_hz_timer(void); 63extern void vmi_account_time_restart_hz_timer(void);
64#else
65static inline int vmi_stop_hz_timer(void)
66{
67 return 0;
68}
69static inline void vmi_account_time_restart_hz_timer(void)
70{
71}
64#endif 72#endif
65 73
66/* 74/*
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 89436b96ad66..8959da245cfb 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -54,6 +54,7 @@
54static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 54static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
55{ 55{
56 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 56 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
57 unsigned short bit = nr & SZLONG_MASK;
57 unsigned long temp; 58 unsigned long temp;
58 59
59 if (cpu_has_llsc && R10000_LLSC_WAR) { 60 if (cpu_has_llsc && R10000_LLSC_WAR) {
@@ -65,9 +66,9 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
65 " beqzl %0, 1b \n" 66 " beqzl %0, 1b \n"
66 " .set mips0 \n" 67 " .set mips0 \n"
67 : "=&r" (temp), "=m" (*m) 68 : "=&r" (temp), "=m" (*m)
68 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 69 : "ir" (1UL << bit), "m" (*m));
69#ifdef CONFIG_CPU_MIPSR2 70#ifdef CONFIG_CPU_MIPSR2
70 } else if (__builtin_constant_p(nr)) { 71 } else if (__builtin_constant_p(bit)) {
71 __asm__ __volatile__( 72 __asm__ __volatile__(
72 "1: " __LL "%0, %1 # set_bit \n" 73 "1: " __LL "%0, %1 # set_bit \n"
73 " " __INS "%0, %4, %2, 1 \n" 74 " " __INS "%0, %4, %2, 1 \n"
@@ -77,7 +78,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
77 "2: b 1b \n" 78 "2: b 1b \n"
78 " .previous \n" 79 " .previous \n"
79 : "=&r" (temp), "=m" (*m) 80 : "=&r" (temp), "=m" (*m)
80 : "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0)); 81 : "ir" (bit), "m" (*m), "r" (~0));
81#endif /* CONFIG_CPU_MIPSR2 */ 82#endif /* CONFIG_CPU_MIPSR2 */
82 } else if (cpu_has_llsc) { 83 } else if (cpu_has_llsc) {
83 __asm__ __volatile__( 84 __asm__ __volatile__(
@@ -91,14 +92,14 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
91 " .previous \n" 92 " .previous \n"
92 " .set mips0 \n" 93 " .set mips0 \n"
93 : "=&r" (temp), "=m" (*m) 94 : "=&r" (temp), "=m" (*m)
94 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 95 : "ir" (1UL << bit), "m" (*m));
95 } else { 96 } else {
96 volatile unsigned long *a = addr; 97 volatile unsigned long *a = addr;
97 unsigned long mask; 98 unsigned long mask;
98 unsigned long flags; 99 unsigned long flags;
99 100
100 a += nr >> SZLONG_LOG; 101 a += nr >> SZLONG_LOG;
101 mask = 1UL << (nr & SZLONG_MASK); 102 mask = 1UL << bit;
102 local_irq_save(flags); 103 local_irq_save(flags);
103 *a |= mask; 104 *a |= mask;
104 local_irq_restore(flags); 105 local_irq_restore(flags);
@@ -118,6 +119,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
118static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 119static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
119{ 120{
120 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 121 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
122 unsigned short bit = nr & SZLONG_MASK;
121 unsigned long temp; 123 unsigned long temp;
122 124
123 if (cpu_has_llsc && R10000_LLSC_WAR) { 125 if (cpu_has_llsc && R10000_LLSC_WAR) {
@@ -129,9 +131,9 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
129 " beqzl %0, 1b \n" 131 " beqzl %0, 1b \n"
130 " .set mips0 \n" 132 " .set mips0 \n"
131 : "=&r" (temp), "=m" (*m) 133 : "=&r" (temp), "=m" (*m)
132 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); 134 : "ir" (~(1UL << bit)), "m" (*m));
133#ifdef CONFIG_CPU_MIPSR2 135#ifdef CONFIG_CPU_MIPSR2
134 } else if (__builtin_constant_p(nr)) { 136 } else if (__builtin_constant_p(bit)) {
135 __asm__ __volatile__( 137 __asm__ __volatile__(
136 "1: " __LL "%0, %1 # clear_bit \n" 138 "1: " __LL "%0, %1 # clear_bit \n"
137 " " __INS "%0, $0, %2, 1 \n" 139 " " __INS "%0, $0, %2, 1 \n"
@@ -141,7 +143,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
141 "2: b 1b \n" 143 "2: b 1b \n"
142 " .previous \n" 144 " .previous \n"
143 : "=&r" (temp), "=m" (*m) 145 : "=&r" (temp), "=m" (*m)
144 : "ir" (nr & SZLONG_MASK), "m" (*m)); 146 : "ir" (bit), "m" (*m));
145#endif /* CONFIG_CPU_MIPSR2 */ 147#endif /* CONFIG_CPU_MIPSR2 */
146 } else if (cpu_has_llsc) { 148 } else if (cpu_has_llsc) {
147 __asm__ __volatile__( 149 __asm__ __volatile__(
@@ -155,14 +157,14 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
155 " .previous \n" 157 " .previous \n"
156 " .set mips0 \n" 158 " .set mips0 \n"
157 : "=&r" (temp), "=m" (*m) 159 : "=&r" (temp), "=m" (*m)
158 : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); 160 : "ir" (~(1UL << bit)), "m" (*m));
159 } else { 161 } else {
160 volatile unsigned long *a = addr; 162 volatile unsigned long *a = addr;
161 unsigned long mask; 163 unsigned long mask;
162 unsigned long flags; 164 unsigned long flags;
163 165
164 a += nr >> SZLONG_LOG; 166 a += nr >> SZLONG_LOG;
165 mask = 1UL << (nr & SZLONG_MASK); 167 mask = 1UL << bit;
166 local_irq_save(flags); 168 local_irq_save(flags);
167 *a &= ~mask; 169 *a &= ~mask;
168 local_irq_restore(flags); 170 local_irq_restore(flags);
@@ -180,6 +182,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
180 */ 182 */
181static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 183static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
182{ 184{
185 unsigned short bit = nr & SZLONG_MASK;
186
183 if (cpu_has_llsc && R10000_LLSC_WAR) { 187 if (cpu_has_llsc && R10000_LLSC_WAR) {
184 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 188 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
185 unsigned long temp; 189 unsigned long temp;
@@ -192,7 +196,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
192 " beqzl %0, 1b \n" 196 " beqzl %0, 1b \n"
193 " .set mips0 \n" 197 " .set mips0 \n"
194 : "=&r" (temp), "=m" (*m) 198 : "=&r" (temp), "=m" (*m)
195 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 199 : "ir" (1UL << bit), "m" (*m));
196 } else if (cpu_has_llsc) { 200 } else if (cpu_has_llsc) {
197 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 201 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
198 unsigned long temp; 202 unsigned long temp;
@@ -208,14 +212,14 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
208 " .previous \n" 212 " .previous \n"
209 " .set mips0 \n" 213 " .set mips0 \n"
210 : "=&r" (temp), "=m" (*m) 214 : "=&r" (temp), "=m" (*m)
211 : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); 215 : "ir" (1UL << bit), "m" (*m));
212 } else { 216 } else {
213 volatile unsigned long *a = addr; 217 volatile unsigned long *a = addr;
214 unsigned long mask; 218 unsigned long mask;
215 unsigned long flags; 219 unsigned long flags;
216 220
217 a += nr >> SZLONG_LOG; 221 a += nr >> SZLONG_LOG;
218 mask = 1UL << (nr & SZLONG_MASK); 222 mask = 1UL << bit;
219 local_irq_save(flags); 223 local_irq_save(flags);
220 *a ^= mask; 224 *a ^= mask;
221 local_irq_restore(flags); 225 local_irq_restore(flags);
@@ -233,6 +237,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
233static inline int test_and_set_bit(unsigned long nr, 237static inline int test_and_set_bit(unsigned long nr,
234 volatile unsigned long *addr) 238 volatile unsigned long *addr)
235{ 239{
240 unsigned short bit = nr & SZLONG_MASK;
241
236 if (cpu_has_llsc && R10000_LLSC_WAR) { 242 if (cpu_has_llsc && R10000_LLSC_WAR) {
237 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 243 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
238 unsigned long temp, res; 244 unsigned long temp, res;
@@ -246,7 +252,7 @@ static inline int test_and_set_bit(unsigned long nr,
246 " and %2, %0, %3 \n" 252 " and %2, %0, %3 \n"
247 " .set mips0 \n" 253 " .set mips0 \n"
248 : "=&r" (temp), "=m" (*m), "=&r" (res) 254 : "=&r" (temp), "=m" (*m), "=&r" (res)
249 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 255 : "r" (1UL << bit), "m" (*m)
250 : "memory"); 256 : "memory");
251 257
252 return res != 0; 258 return res != 0;
@@ -269,7 +275,7 @@ static inline int test_and_set_bit(unsigned long nr,
269 " .previous \n" 275 " .previous \n"
270 " .set pop \n" 276 " .set pop \n"
271 : "=&r" (temp), "=m" (*m), "=&r" (res) 277 : "=&r" (temp), "=m" (*m), "=&r" (res)
272 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 278 : "r" (1UL << bit), "m" (*m)
273 : "memory"); 279 : "memory");
274 280
275 return res != 0; 281 return res != 0;
@@ -280,7 +286,7 @@ static inline int test_and_set_bit(unsigned long nr,
280 unsigned long flags; 286 unsigned long flags;
281 287
282 a += nr >> SZLONG_LOG; 288 a += nr >> SZLONG_LOG;
283 mask = 1UL << (nr & SZLONG_MASK); 289 mask = 1UL << bit;
284 local_irq_save(flags); 290 local_irq_save(flags);
285 retval = (mask & *a) != 0; 291 retval = (mask & *a) != 0;
286 *a |= mask; 292 *a |= mask;
@@ -303,6 +309,8 @@ static inline int test_and_set_bit(unsigned long nr,
303static inline int test_and_clear_bit(unsigned long nr, 309static inline int test_and_clear_bit(unsigned long nr,
304 volatile unsigned long *addr) 310 volatile unsigned long *addr)
305{ 311{
312 unsigned short bit = nr & SZLONG_MASK;
313
306 if (cpu_has_llsc && R10000_LLSC_WAR) { 314 if (cpu_has_llsc && R10000_LLSC_WAR) {
307 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 315 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
308 unsigned long temp, res; 316 unsigned long temp, res;
@@ -317,7 +325,7 @@ static inline int test_and_clear_bit(unsigned long nr,
317 " and %2, %0, %3 \n" 325 " and %2, %0, %3 \n"
318 " .set mips0 \n" 326 " .set mips0 \n"
319 : "=&r" (temp), "=m" (*m), "=&r" (res) 327 : "=&r" (temp), "=m" (*m), "=&r" (res)
320 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 328 : "r" (1UL << bit), "m" (*m)
321 : "memory"); 329 : "memory");
322 330
323 return res != 0; 331 return res != 0;
@@ -336,7 +344,7 @@ static inline int test_and_clear_bit(unsigned long nr,
336 "2: b 1b \n" 344 "2: b 1b \n"
337 " .previous \n" 345 " .previous \n"
338 : "=&r" (temp), "=m" (*m), "=&r" (res) 346 : "=&r" (temp), "=m" (*m), "=&r" (res)
339 : "ri" (nr & SZLONG_MASK), "m" (*m) 347 : "ri" (bit), "m" (*m)
340 : "memory"); 348 : "memory");
341 349
342 return res; 350 return res;
@@ -361,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
361 " .previous \n" 369 " .previous \n"
362 " .set pop \n" 370 " .set pop \n"
363 : "=&r" (temp), "=m" (*m), "=&r" (res) 371 : "=&r" (temp), "=m" (*m), "=&r" (res)
364 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 372 : "r" (1UL << bit), "m" (*m)
365 : "memory"); 373 : "memory");
366 374
367 return res != 0; 375 return res != 0;
@@ -372,7 +380,7 @@ static inline int test_and_clear_bit(unsigned long nr,
372 unsigned long flags; 380 unsigned long flags;
373 381
374 a += nr >> SZLONG_LOG; 382 a += nr >> SZLONG_LOG;
375 mask = 1UL << (nr & SZLONG_MASK); 383 mask = 1UL << bit;
376 local_irq_save(flags); 384 local_irq_save(flags);
377 retval = (mask & *a) != 0; 385 retval = (mask & *a) != 0;
378 *a &= ~mask; 386 *a &= ~mask;
@@ -395,6 +403,8 @@ static inline int test_and_clear_bit(unsigned long nr,
395static inline int test_and_change_bit(unsigned long nr, 403static inline int test_and_change_bit(unsigned long nr,
396 volatile unsigned long *addr) 404 volatile unsigned long *addr)
397{ 405{
406 unsigned short bit = nr & SZLONG_MASK;
407
398 if (cpu_has_llsc && R10000_LLSC_WAR) { 408 if (cpu_has_llsc && R10000_LLSC_WAR) {
399 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 409 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
400 unsigned long temp, res; 410 unsigned long temp, res;
@@ -408,7 +418,7 @@ static inline int test_and_change_bit(unsigned long nr,
408 " and %2, %0, %3 \n" 418 " and %2, %0, %3 \n"
409 " .set mips0 \n" 419 " .set mips0 \n"
410 : "=&r" (temp), "=m" (*m), "=&r" (res) 420 : "=&r" (temp), "=m" (*m), "=&r" (res)
411 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 421 : "r" (1UL << bit), "m" (*m)
412 : "memory"); 422 : "memory");
413 423
414 return res != 0; 424 return res != 0;
@@ -431,7 +441,7 @@ static inline int test_and_change_bit(unsigned long nr,
431 " .previous \n" 441 " .previous \n"
432 " .set pop \n" 442 " .set pop \n"
433 : "=&r" (temp), "=m" (*m), "=&r" (res) 443 : "=&r" (temp), "=m" (*m), "=&r" (res)
434 : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) 444 : "r" (1UL << bit), "m" (*m)
435 : "memory"); 445 : "memory");
436 446
437 return res != 0; 447 return res != 0;
@@ -441,7 +451,7 @@ static inline int test_and_change_bit(unsigned long nr,
441 unsigned long flags; 451 unsigned long flags;
442 452
443 a += nr >> SZLONG_LOG; 453 a += nr >> SZLONG_LOG;
444 mask = 1UL << (nr & SZLONG_MASK); 454 mask = 1UL << bit;
445 local_irq_save(flags); 455 local_irq_save(flags);
446 retval = (mask & *a) != 0; 456 retval = (mask & *a) != 0;
447 *a ^= mask; 457 *a ^= mask;
diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h
index fdfff0b8ce42..8045abc78d0f 100644
--- a/include/asm-mips/mips_mt.h
+++ b/include/asm-mips/mips_mt.h
@@ -6,6 +6,8 @@
6#ifndef __ASM_MIPS_MT_H 6#ifndef __ASM_MIPS_MT_H
7#define __ASM_MIPS_MT_H 7#define __ASM_MIPS_MT_H
8 8
9#include <linux/cpumask.h>
10
9extern cpumask_t mt_fpu_cpumask; 11extern cpumask_t mt_fpu_cpumask;
10extern unsigned long mt_fpemul_threshold; 12extern unsigned long mt_fpemul_threshold;
11 13
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index e1941d1b8726..44dfa4adecf3 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -34,6 +34,9 @@ typedef long asiduse;
34 34
35extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 35extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
36 36
37struct mm_struct;
38struct task_struct;
39
37void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); 40void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
38 41
39void smtc_flush_tlb_asid(unsigned long asid); 42void smtc_flush_tlb_asid(unsigned long asid);
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
index 55f3419f6546..360ea6d250c7 100644
--- a/include/asm-mips/smtc_ipi.h
+++ b/include/asm-mips/smtc_ipi.h
@@ -4,6 +4,8 @@
4#ifndef __ASM_SMTC_IPI_H 4#ifndef __ASM_SMTC_IPI_H
5#define __ASM_SMTC_IPI_H 5#define __ASM_SMTC_IPI_H
6 6
7#include <linux/spinlock.h>
8
7//#define SMTC_IPI_DEBUG 9//#define SMTC_IPI_DEBUG
8 10
9#ifdef SMTC_IPI_DEBUG 11#ifdef SMTC_IPI_DEBUG
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index f1755d28a36a..35e431cd796b 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -287,7 +287,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
287 " .set noreorder # __raw_read_trylock \n" 287 " .set noreorder # __raw_read_trylock \n"
288 " li %2, 0 \n" 288 " li %2, 0 \n"
289 "1: ll %1, %3 \n" 289 "1: ll %1, %3 \n"
290 " bnez %1, 2f \n" 290 " bltz %1, 2f \n"
291 " addu %1, 1 \n" 291 " addu %1, 1 \n"
292 " sc %1, %0 \n" 292 " sc %1, %0 \n"
293 " .set reorder \n" 293 " .set reorder \n"
@@ -304,7 +304,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
304 " .set noreorder # __raw_read_trylock \n" 304 " .set noreorder # __raw_read_trylock \n"
305 " li %2, 0 \n" 305 " li %2, 0 \n"
306 "1: ll %1, %3 \n" 306 "1: ll %1, %3 \n"
307 " bnez %1, 2f \n" 307 " bltz %1, 2f \n"
308 " addu %1, 1 \n" 308 " addu %1, 1 \n"
309 " sc %1, %0 \n" 309 " sc %1, %0 \n"
310 " beqz %1, 1b \n" 310 " beqz %1, 1b \n"
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index c62c20e7b5c6..b25511787ee0 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -435,6 +435,8 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
435 __cu_len; \ 435 __cu_len; \
436}) 436})
437 437
438extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
439
438#define __copy_to_user_inatomic(to,from,n) \ 440#define __copy_to_user_inatomic(to,from,n) \
439({ \ 441({ \
440 void __user *__cu_to; \ 442 void __user *__cu_to; \
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 696cff39a1d3..2f1087b3a202 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -334,16 +334,18 @@
334#define __NR_kexec_load (__NR_Linux + 311) 334#define __NR_kexec_load (__NR_Linux + 311)
335#define __NR_getcpu (__NR_Linux + 312) 335#define __NR_getcpu (__NR_Linux + 312)
336#define __NR_epoll_pwait (__NR_Linux + 313) 336#define __NR_epoll_pwait (__NR_Linux + 313)
337#define __NR_ioprio_set (__NR_Linux + 314)
338#define __NR_ioprio_get (__NR_Linux + 315)
337 339
338/* 340/*
339 * Offset of the last Linux o32 flavoured syscall 341 * Offset of the last Linux o32 flavoured syscall
340 */ 342 */
341#define __NR_Linux_syscalls 313 343#define __NR_Linux_syscalls 315
342 344
343#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 345#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
344 346
345#define __NR_O32_Linux 4000 347#define __NR_O32_Linux 4000
346#define __NR_O32_Linux_syscalls 313 348#define __NR_O32_Linux_syscalls 315
347 349
348#if _MIPS_SIM == _MIPS_SIM_ABI64 350#if _MIPS_SIM == _MIPS_SIM_ABI64
349 351
@@ -624,16 +626,18 @@
624#define __NR_kexec_load (__NR_Linux + 270) 626#define __NR_kexec_load (__NR_Linux + 270)
625#define __NR_getcpu (__NR_Linux + 271) 627#define __NR_getcpu (__NR_Linux + 271)
626#define __NR_epoll_pwait (__NR_Linux + 272) 628#define __NR_epoll_pwait (__NR_Linux + 272)
629#define __NR_ioprio_set (__NR_Linux + 273)
630#define __NR_ioprio_get (__NR_Linux + 274)
627 631
628/* 632/*
629 * Offset of the last Linux 64-bit flavoured syscall 633 * Offset of the last Linux 64-bit flavoured syscall
630 */ 634 */
631#define __NR_Linux_syscalls 272 635#define __NR_Linux_syscalls 274
632 636
633#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 637#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
634 638
635#define __NR_64_Linux 5000 639#define __NR_64_Linux 5000
636#define __NR_64_Linux_syscalls 272 640#define __NR_64_Linux_syscalls 274
637 641
638#if _MIPS_SIM == _MIPS_SIM_NABI32 642#if _MIPS_SIM == _MIPS_SIM_NABI32
639 643
@@ -918,16 +922,18 @@
918#define __NR_kexec_load (__NR_Linux + 274) 922#define __NR_kexec_load (__NR_Linux + 274)
919#define __NR_getcpu (__NR_Linux + 275) 923#define __NR_getcpu (__NR_Linux + 275)
920#define __NR_epoll_pwait (__NR_Linux + 276) 924#define __NR_epoll_pwait (__NR_Linux + 276)
925#define __NR_ioprio_set (__NR_Linux + 277)
926#define __NR_ioprio_get (__NR_Linux + 278)
921 927
922/* 928/*
923 * Offset of the last N32 flavoured syscall 929 * Offset of the last N32 flavoured syscall
924 */ 930 */
925#define __NR_Linux_syscalls 276 931#define __NR_Linux_syscalls 278
926 932
927#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 933#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
928 934
929#define __NR_N32_Linux 6000 935#define __NR_N32_Linux 6000
930#define __NR_N32_Linux_syscalls 276 936#define __NR_N32_Linux_syscalls 278
931 937
932#ifdef __KERNEL__ 938#ifdef __KERNEL__
933 939
diff --git a/include/asm-x86_64/tsc.h b/include/asm-x86_64/tsc.h
index 26c3e9828288..d66ba6ef25f6 100644
--- a/include/asm-x86_64/tsc.h
+++ b/include/asm-x86_64/tsc.h
@@ -1,67 +1 @@
1/* #include <asm-i386/tsc.h>
2 * linux/include/asm-x86_64/tsc.h
3 *
4 * x86_64 TSC related functions
5 */
6#ifndef _ASM_x86_64_TSC_H
7#define _ASM_x86_64_TSC_H
8
9#include <asm/processor.h>
10
11/*
12 * Standard way to access the cycle counter.
13 */
14typedef unsigned long long cycles_t;
15
16extern unsigned int cpu_khz;
17extern unsigned int tsc_khz;
18
19static inline cycles_t get_cycles(void)
20{
21 unsigned long long ret = 0;
22
23#ifndef CONFIG_X86_TSC
24 if (!cpu_has_tsc)
25 return 0;
26#endif
27
28#if defined(CONFIG_X86_GENERIC) || defined(CONFIG_X86_TSC)
29 rdtscll(ret);
30#endif
31 return ret;
32}
33
34/* Like get_cycles, but make sure the CPU is synchronized. */
35static __always_inline cycles_t get_cycles_sync(void)
36{
37 unsigned long long ret;
38#ifdef X86_FEATURE_SYNC_RDTSC
39 unsigned eax;
40
41 /*
42 * Don't do an additional sync on CPUs where we know
43 * RDTSC is already synchronous:
44 */
45 alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
46 "=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
47#else
48 sync_core();
49#endif
50 rdtscll(ret);
51
52 return ret;
53}
54
55extern void tsc_init(void);
56extern void mark_tsc_unstable(void);
57extern int unsynchronized_tsc(void);
58extern void init_tsc_clocksource(void);
59
60/*
61 * Boot-time check whether the TSCs are synchronized across
62 * all CPUs/cores:
63 */
64extern void check_tsc_sync_source(int cpu);
65extern void check_tsc_sync_target(void);
66
67#endif
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 229fa012c893..773e30df11ee 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -24,6 +24,7 @@
24#ifndef _LINUX_AUDIT_H_ 24#ifndef _LINUX_AUDIT_H_
25#define _LINUX_AUDIT_H_ 25#define _LINUX_AUDIT_H_
26 26
27#include <linux/types.h>
27#include <linux/elf-em.h> 28#include <linux/elf-em.h>
28 29
29/* The netlink messages for the audit system is divided into blocks: 30/* The netlink messages for the audit system is divided into blocks:
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 3bef961b58b1..5bdbc744e773 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -47,7 +47,7 @@ enum hrtimer_restart {
47 * HRTIMER_CB_IRQSAFE: Callback may run in hardirq context 47 * HRTIMER_CB_IRQSAFE: Callback may run in hardirq context
48 * HRTIMER_CB_IRQSAFE_NO_RESTART: Callback may run in hardirq context and 48 * HRTIMER_CB_IRQSAFE_NO_RESTART: Callback may run in hardirq context and
49 * does not restart the timer 49 * does not restart the timer
50 * HRTIMER_CB_IRQSAFE_NO_SOFTIRQ: Callback must run in softirq context 50 * HRTIMER_CB_IRQSAFE_NO_SOFTIRQ: Callback must run in hardirq context
51 * Special mode for tick emultation 51 * Special mode for tick emultation
52 */ 52 */
53enum hrtimer_cb_mode { 53enum hrtimer_cb_mode {
@@ -139,7 +139,7 @@ struct hrtimer_sleeper {
139}; 139};
140 140
141/** 141/**
142 * struct hrtimer_base - the timer base for a specific clock 142 * struct hrtimer_clock_base - the timer base for a specific clock
143 * @cpu_base: per cpu clock base 143 * @cpu_base: per cpu clock base
144 * @index: clock type index for per_cpu support when moving a 144 * @index: clock type index for per_cpu support when moving a
145 * timer to a base on another cpu. 145 * timer to a base on another cpu.
diff --git a/include/linux/igmp.h b/include/linux/igmp.h
index 9dbb525c5178..a113fe68d8a1 100644
--- a/include/linux/igmp.h
+++ b/include/linux/igmp.h
@@ -218,5 +218,7 @@ extern void ip_mc_up(struct in_device *);
218extern void ip_mc_down(struct in_device *); 218extern void ip_mc_down(struct in_device *);
219extern void ip_mc_dec_group(struct in_device *in_dev, __be32 addr); 219extern void ip_mc_dec_group(struct in_device *in_dev, __be32 addr);
220extern void ip_mc_inc_group(struct in_device *in_dev, __be32 addr); 220extern void ip_mc_inc_group(struct in_device *in_dev, __be32 addr);
221extern void ip_mc_rejoin_group(struct ip_mc_list *im);
222
221#endif 223#endif
222#endif 224#endif
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 913e5752569f..bfcef8a1ad8b 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -62,6 +62,12 @@ struct mmc_ios {
62 62
63#define MMC_BUS_WIDTH_1 0 63#define MMC_BUS_WIDTH_1 0
64#define MMC_BUS_WIDTH_4 2 64#define MMC_BUS_WIDTH_4 2
65
66 unsigned char timing; /* timing specification used */
67
68#define MMC_TIMING_LEGACY 0
69#define MMC_TIMING_MMC_HS 1
70#define MMC_TIMING_SD_HS 2
65}; 71};
66 72
67struct mmc_host_ops { 73struct mmc_host_ops {
@@ -87,6 +93,8 @@ struct mmc_host {
87#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ 93#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
88#define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */ 94#define MMC_CAP_MULTIWRITE (1 << 1) /* Can accurately report bytes sent to card on error */
89#define MMC_CAP_BYTEBLOCK (1 << 2) /* Can do non-log2 block sizes */ 95#define MMC_CAP_BYTEBLOCK (1 << 2) /* Can do non-log2 block sizes */
96#define MMC_CAP_MMC_HIGHSPEED (1 << 3) /* Can do MMC high-speed timing */
97#define MMC_CAP_SD_HIGHSPEED (1 << 4) /* Can do SD high-speed timing */
90 98
91 /* host specific block data */ 99 /* host specific block data */
92 unsigned int max_seg_size; /* see blk_queue_max_segment_size */ 100 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index e7d4da1cc9fa..c6d4ab86b83c 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -1288,6 +1288,7 @@ struct mv64xxx_i2c_pdata {
1288#define MV643XX_ETH_NAME "mv643xx_eth" 1288#define MV643XX_ETH_NAME "mv643xx_eth"
1289 1289
1290struct mv643xx_eth_platform_data { 1290struct mv643xx_eth_platform_data {
1291 int port_number;
1291 u16 force_phy_addr; /* force override if phy_addr == 0 */ 1292 u16 force_phy_addr; /* force override if phy_addr == 0 */
1292 u16 phy_addr; 1293 u16 phy_addr;
1293 1294
diff --git a/include/linux/ncp_fs_sb.h b/include/linux/ncp_fs_sb.h
index a503052138bd..6330fc76b00f 100644
--- a/include/linux/ncp_fs_sb.h
+++ b/include/linux/ncp_fs_sb.h
@@ -50,6 +50,8 @@ struct ncp_server {
50 int packet_size; 50 int packet_size;
51 unsigned char *packet; /* Here we prepare requests and 51 unsigned char *packet; /* Here we prepare requests and
52 receive replies */ 52 receive replies */
53 unsigned char *txbuf; /* Storage for current request */
54 unsigned char *rxbuf; /* Storage for reply to current request */
53 55
54 int lock; /* To prevent mismatch in protocols. */ 56 int lock; /* To prevent mismatch in protocols. */
55 struct mutex mutex; 57 struct mutex mutex;
diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
index 83b3c7b433aa..35fa4d5aadd0 100644
--- a/include/linux/sunrpc/svc.h
+++ b/include/linux/sunrpc/svc.h
@@ -194,9 +194,7 @@ static inline void svc_putu32(struct kvec *iov, __be32 val)
194 194
195union svc_addr_u { 195union svc_addr_u {
196 struct in_addr addr; 196 struct in_addr addr;
197#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
198 struct in6_addr addr6; 197 struct in6_addr addr6;
199#endif
200}; 198};
201 199
202/* 200/*
diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h
index cccea0a0feb4..7909687557bf 100644
--- a/include/linux/sunrpc/svcsock.h
+++ b/include/linux/sunrpc/svcsock.h
@@ -66,7 +66,7 @@ struct svc_sock {
66 * Function prototypes. 66 * Function prototypes.
67 */ 67 */
68int svc_makesock(struct svc_serv *, int, unsigned short, int flags); 68int svc_makesock(struct svc_serv *, int, unsigned short, int flags);
69void svc_close_socket(struct svc_sock *); 69void svc_force_close_socket(struct svc_sock *);
70int svc_recv(struct svc_rqst *, long); 70int svc_recv(struct svc_rqst *, long);
71int svc_send(struct svc_rqst *); 71int svc_send(struct svc_rqst *);
72void svc_drop(struct svc_rqst *); 72void svc_drop(struct svc_rqst *);
diff --git a/include/sound/version.h b/include/sound/version.h
index a9ba7ee69939..5f7275000102 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
1/* include/version.h. Generated by alsa/ksync script. */ 1/* include/version.h. Generated by alsa/ksync script. */
2#define CONFIG_SND_VERSION "1.0.14rc2" 2#define CONFIG_SND_VERSION "1.0.14rc3"
3#define CONFIG_SND_DATE " (Wed Feb 14 07:42:13 2007 UTC)" 3#define CONFIG_SND_DATE " (Tue Mar 06 13:10:00 2007 UTC)"
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 23:12:44 -0500