2 files changed, 8 insertions, 4 deletions

diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h
index 7641e7b5d931..6c21ef951dab 100644
--- a/include/asm-x86/pgalloc_32.h
+++ b/include/asm-x86/pgalloc_32.h
@@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
         set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
 
         /*
-         * Pentium-II erratum A13: in PAE mode we explicitly have to flush
-         * the TLB via cr3 if the top-level pgd is changed...
+         * According to Intel App note "TLBs, Paging-Structure Caches,
+         * and Their Invalidation", April 2007, document 317080-001,
+         * section 8.1: in PAE mode we explicitly have to flush the
+         * TLB via cr3 if the top-level pgd is changed...
          */
         if (mm == current->active_mm)
                 write_cr3(read_cr3());
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
index ad71960bca3a..1d763eec740f 100644
--- a/include/asm-x86/pgtable-3level.h
+++ b/include/asm-x86/pgtable-3level.h
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp)
         set_pud(pudp, __pud(0));
 
         /*
-         * Pentium-II erratum A13: in PAE mode we explicitly have to flush
-         * the TLB via cr3 if the top-level pgd is changed...
+         * According to Intel App note "TLBs, Paging-Structure Caches,
+         * and Their Invalidation", April 2007, document 317080-001,
+         * section 8.1: in PAE mode we explicitly have to flush the
+         * TLB via cr3 if the top-level pgd is changed...
          *
          * Make sure the pud entry we're updating is within the
          * current pgd to avoid unnecessary TLB flushes.