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-rw-r--r--include/asm-arm/arch-at91/irqs.h3
-rw-r--r--include/asm-arm/arch-omap/irda.h1
-rw-r--r--include/asm-arm/cacheflush.h7
-rw-r--r--include/asm-arm/plat-s3c/map.h12
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h4
-rw-r--r--include/asm-blackfin/string.h129
-rw-r--r--include/asm-generic/termios.h2
-rw-r--r--include/asm-ia64/hpsim.h16
-rw-r--r--include/asm-ia64/sn/arch.h1
-rw-r--r--include/asm-ia64/sn/intr.h1
-rw-r--r--include/asm-ia64/sn/sn_feature_sets.h1
-rw-r--r--include/asm-m32r/assembler.h16
-rw-r--r--include/asm-m32r/m32r.h20
-rw-r--r--include/asm-m68k/unistd.h12
-rw-r--r--include/asm-m68knommu/unistd.h12
-rw-r--r--include/asm-mips/bcache.h1
-rw-r--r--include/asm-mips/edac.h17
-rw-r--r--include/asm-mips/gt64240.h1235
-rw-r--r--include/asm-mips/hazards.h1
-rw-r--r--include/asm-mips/ioctls.h4
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h3
-rw-r--r--include/asm-mips/jmr3927/tx3927.h36
-rw-r--r--include/asm-mips/mach-generic/ide.h83
-rw-r--r--include/asm-mips/mach-ocelot/mach-gt64120.h30
-rw-r--r--include/asm-mips/marvell.h59
-rw-r--r--include/asm-mips/pgtable-32.h16
-rw-r--r--include/asm-mips/pgtable.h12
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h5
-rw-r--r--include/asm-mips/smtc.h10
-rw-r--r--include/asm-mips/stacktrace.h6
-rw-r--r--include/asm-mips/termbits.h7
-rw-r--r--include/asm-mips/termios.h6
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h2
-rw-r--r--include/asm-mips/tx4927/tx4927.h49
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h23
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h25
-rw-r--r--include/asm-mips/tx4938/tx4938.h41
-rw-r--r--include/asm-mips/txx9irq.h30
-rw-r--r--include/asm-parisc/io.h10
-rw-r--r--include/asm-parisc/vga.h6
-rw-r--r--include/asm-powerpc/spu.h2
-rw-r--r--include/asm-sparc/tlbflush.h6
-rw-r--r--include/asm-sparc64/device.h2
-rw-r--r--include/asm-sparc64/irq.h25
-rw-r--r--include/asm-um/common.lds.S124
-rw-r--r--include/asm-um/elf-x86_64.h40
-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/aer.h25
-rw-r--r--include/linux/ata.h13
-rw-r--r--include/linux/cpu.h6
-rw-r--r--include/linux/hugetlb.h10
-rw-r--r--include/linux/ide.h13
-rw-r--r--include/linux/if_pppol2tp.h4
-rw-r--r--include/linux/input.h2
-rw-r--r--include/linux/kernel.h1
-rw-r--r--include/linux/keyboard.h4
-rw-r--r--include/linux/leds.h1
-rw-r--r--include/linux/libata.h1
-rw-r--r--include/linux/netfilter.h5
-rw-r--r--include/linux/nfs_fs.h1
-rw-r--r--include/linux/pci_ids.h6
-rw-r--r--include/linux/pmu.h2
-rw-r--r--include/linux/poll.h2
-rw-r--r--include/linux/rtnetlink.h2
-rw-r--r--include/linux/sched.h1
-rw-r--r--include/linux/slub_def.h8
-rw-r--r--include/media/v4l2-dev.h5
-rw-r--r--include/net/sctp/sm.h2
-rw-r--r--include/net/sctp/structs.h1
-rw-r--r--include/net/sctp/ulpqueue.h1
-rw-r--r--include/scsi/libiscsi.h7
71 files changed, 557 insertions, 1720 deletions
diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h
index 1127a3b5e928..70b1216dce5d 100644
--- a/include/asm-arm/arch-at91/irqs.h
+++ b/include/asm-arm/arch-at91/irqs.h
@@ -42,4 +42,7 @@
42 */ 42 */
43#define NR_IRQS (NR_AIC_IRQS + (5 * 32)) 43#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
44 44
45/* FIQ is AIC source 0. */
46#define FIQ_START AT91_ID_FIQ
47
45#endif 48#endif
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h
index 345a649ec838..96bb12fab438 100644
--- a/include/asm-arm/arch-omap/irda.h
+++ b/include/asm-arm/arch-omap/irda.h
@@ -31,6 +31,7 @@ struct omap_irda_config {
31 unsigned long src_start; 31 unsigned long src_start;
32 int tx_trigger; 32 int tx_trigger;
33 int rx_trigger; 33 int rx_trigger;
34 int mode;
34}; 35};
35 36
36#endif 37#endif
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index d1294a46c70c..6c1c968b2987 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -426,6 +426,13 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
426 */ 426 */
427#define flush_icache_page(vma,page) do { } while (0) 427#define flush_icache_page(vma,page) do { } while (0)
428 428
429static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
430 unsigned offset, size_t size)
431{
432 const void *start = (void __force *)virt + offset;
433 dmac_inv_range(start, start + size);
434}
435
429#define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) 436#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
430#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29)) 437#define __cacheid_type_v7(val) ((val & (7 << 29)) == (4 << 29))
431 438
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
index 95a82b0e84a1..b84289d32a54 100644
--- a/include/asm-arm/plat-s3c/map.h
+++ b/include/asm-arm/plat-s3c/map.h
@@ -30,11 +30,11 @@
30#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) 30#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
31#endif 31#endif
32 32
33#define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */ 33#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
34#define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */ 34#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
35#define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */ 35#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
36#define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */ 36#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
37#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */ 37#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
38#define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */ 38#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
39 39
40#endif /* __ASM_PLAT_MAP_H */ 40#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 6e87ab269ffe..73d4d65249cd 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
83 83
84/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 84/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
85#define bfin_read_SWRST() bfin_read_SICA_SWRST() 85#define bfin_read_SWRST() bfin_read_SICA_SWRST()
86#define bfin_write_SWRST() bfin_write_SICA_SWRST() 86#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
87#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() 87#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
88#define bfin_write_SYSCR() bfin_write_SICA_SYSCR() 88#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
89 89
90/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 90/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
91#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 91#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index 6f1eb7d6d3cb..e8ada91ab002 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -9,13 +9,16 @@ extern inline char *strcpy(char *dest, const char *src)
9 char *xdest = dest; 9 char *xdest = dest;
10 char temp = 0; 10 char temp = 0;
11 11
12 __asm__ __volatile__ 12 __asm__ __volatile__ (
13 ("1:\t%2 = B [%1++] (Z);\n\t" 13 "1:"
14 "B [%0++] = %2;\n\t" 14 "%2 = B [%1++] (Z);"
15 "CC = %2;\n\t" 15 "B [%0++] = %2;"
16 "if cc jump 1b (bp);\n" 16 "CC = %2;"
17 : "+&a" (dest), "+&a" (src), "=&d" (temp) 17 "if cc jump 1b (bp);"
18 ::"memory", "CC"); 18 : "+&a" (dest), "+&a" (src), "=&d" (temp)
19 :
20 : "memory", "CC");
21
19 return xdest; 22 return xdest;
20} 23}
21 24
@@ -28,37 +31,56 @@ extern inline char *strncpy(char *dest, const char *src, size_t n)
28 if (n == 0) 31 if (n == 0)
29 return xdest; 32 return xdest;
30 33
31 __asm__ __volatile__ 34 __asm__ __volatile__ (
32 ("1:\t%3 = B [%1++] (Z);\n\t" 35 "1:"
33 "B [%0++] = %3;\n\t" 36 "%3 = B [%1++] (Z);"
34 "CC = %3;\n\t" 37 "B [%0++] = %3;"
35 "if ! cc jump 2f;\n\t" 38 "CC = %3;"
36 "%2 += -1;\n\t" 39 "if ! cc jump 2f;"
37 "CC = %2 == 0;\n\t" 40 "%2 += -1;"
38 "if ! cc jump 1b (bp);\n" 41 "CC = %2 == 0;"
39 "2:\n" 42 "if ! cc jump 1b (bp);"
40 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp) 43 "jump 4f;"
41 ::"memory", "CC"); 44 "2:"
45 /* if src is shorter than n, we need to null pad bytes now */
46 "%3 = 0;"
47 "3:"
48 "%2 += -1;"
49 "CC = %2 == 0;"
50 "if cc jump 4f;"
51 "B [%0++] = %3;"
52 "jump 3b;"
53 "4:"
54 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
55 :
56 : "memory", "CC");
57
42 return xdest; 58 return xdest;
43} 59}
44 60
45#define __HAVE_ARCH_STRCMP 61#define __HAVE_ARCH_STRCMP
46extern inline int strcmp(const char *cs, const char *ct) 62extern inline int strcmp(const char *cs, const char *ct)
47{ 63{
48 char __res1, __res2; 64 /* need to use int's here so the char's in the assembly don't get
49 65 * sign extended incorrectly when we don't want them to be
50 __asm__ 66 */
51 ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */ 67 int __res1, __res2;
52 "%3 = B[%1++] (Z);\n\t" /* get *ct */ 68
53 "CC = %2 == %3;\n\t" /* compare a byte */ 69 __asm__ __volatile__ (
54 "if ! cc jump 2f;\n\t" /* not equal, break out */ 70 "1:"
55 "CC = %2;\n\t" /* at end of cs? */ 71 "%2 = B[%0++] (Z);" /* get *cs */
56 "if cc jump 1b (bp);\n\t" /* no, keep going */ 72 "%3 = B[%1++] (Z);" /* get *ct */
57 "jump.s 3f;\n" /* strings are equal */ 73 "CC = %2 == %3;" /* compare a byte */
58 "2:\t%2 = %2 - %3;\n" /* *cs - *ct */ 74 "if ! cc jump 2f;" /* not equal, break out */
59 "3:\n" 75 "CC = %2;" /* at end of cs? */
60 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2) 76 "if cc jump 1b (bp);" /* no, keep going */
61 : : "CC"); 77 "jump.s 3f;" /* strings are equal */
78 "2:"
79 "%2 = %2 - %3;" /* *cs - *ct */
80 "3:"
81 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
82 :
83 : "memory", "CC");
62 84
63 return __res1; 85 return __res1;
64} 86}
@@ -66,26 +88,35 @@ extern inline int strcmp(const char *cs, const char *ct)
66#define __HAVE_ARCH_STRNCMP 88#define __HAVE_ARCH_STRNCMP
67extern inline int strncmp(const char *cs, const char *ct, size_t count) 89extern inline int strncmp(const char *cs, const char *ct, size_t count)
68{ 90{
69 char __res1, __res2; 91 /* need to use int's here so the char's in the assembly don't get
92 * sign extended incorrectly when we don't want them to be
93 */
94 int __res1, __res2;
70 95
71 if (!count) 96 if (!count)
72 return 0; 97 return 0;
73 __asm__ 98
74 ("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */ 99 __asm__ __volatile__ (
75 "%4 = B[%1++] (Z);\n\t" /* get *ct */ 100 "1:"
76 "CC = %3 == %4;\n\t" /* compare a byte */ 101 "%3 = B[%0++] (Z);" /* get *cs */
77 "if ! cc jump 3f;\n\t" /* not equal, break out */ 102 "%4 = B[%1++] (Z);" /* get *ct */
78 "CC = %3;\n\t" /* at end of cs? */ 103 "CC = %3 == %4;" /* compare a byte */
79 "if ! cc jump 4f;\n\t" /* yes, all done */ 104 "if ! cc jump 3f;" /* not equal, break out */
80 "%2 += -1;\n\t" /* no, adjust count */ 105 "CC = %3;" /* at end of cs? */
81 "CC = %2 == 0;\n\t" 106 "if ! cc jump 4f;" /* yes, all done */
82 "if ! cc jump 1b;\n" /* more to do, keep going */ 107 "%2 += -1;" /* no, adjust count */
83 "2:\t%3 = 0;\n\t" /* strings are equal */ 108 "CC = %2 == 0;"
84 "jump.s 4f;\n" 109 "if ! cc jump 1b;" /* more to do, keep going */
85 "3:\t%3 = %3 - %4;\n" /* *cs - *ct */ 110 "2:"
86 "4:" 111 "%3 = 0;" /* strings are equal */
87 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2) 112 "jump.s 4f;"
88 : : "CC"); 113 "3:"
114 "%3 = %3 - %4;" /* *cs - *ct */
115 "4:"
116 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
117 :
118 : "memory", "CC");
119
89 return __res1; 120 return __res1;
90} 121}
91 122
diff --git a/include/asm-generic/termios.h b/include/asm-generic/termios.h
index 3769e6bd63b1..33dca30a3c45 100644
--- a/include/asm-generic/termios.h
+++ b/include/asm-generic/termios.h
@@ -63,6 +63,8 @@ static inline int kernel_termios_to_user_termio(struct termio __user *termio,
63 63
64#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) 64#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
65#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) 65#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
66#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
67#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
66 68
67#endif /* __ARCH_TERMIO_GETPUT */ 69#endif /* __ARCH_TERMIO_GETPUT */
68 70
diff --git a/include/asm-ia64/hpsim.h b/include/asm-ia64/hpsim.h
new file mode 100644
index 000000000000..892ab198a9da
--- /dev/null
+++ b/include/asm-ia64/hpsim.h
@@ -0,0 +1,16 @@
1#ifndef _ASMIA64_HPSIM_H
2#define _ASMIA64_HPSIM_H
3
4#ifndef CONFIG_HP_SIMSERIAL_CONSOLE
5static inline int simcons_register(void) { return 1; }
6#else
7int simcons_register(void);
8#endif
9
10struct tty_driver;
11extern struct tty_driver *hp_simserial_driver;
12
13void ia64_ssc_connect_irq(long intr, long irq);
14void ia64_ctl_trace(long on);
15
16#endif
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
index 16adc93d7a72..7caa1f44cd95 100644
--- a/include/asm-ia64/sn/arch.h
+++ b/include/asm-ia64/sn/arch.h
@@ -81,5 +81,6 @@ extern u8 sn_sharing_domain_size;
81extern u8 sn_region_size; 81extern u8 sn_region_size;
82 82
83extern void sn_flush_all_caches(long addr, long bytes); 83extern void sn_flush_all_caches(long addr, long bytes);
84extern bool sn_cpu_disable_allowed(int cpu);
84 85
85#endif /* _ASM_IA64_SN_ARCH_H */ 86#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
index 12b54ddb06be..e0487aa97418 100644
--- a/include/asm-ia64/sn/intr.h
+++ b/include/asm-ia64/sn/intr.h
@@ -60,6 +60,7 @@ extern u64 sn_intr_alloc(nasid_t, int,
60 int, nasid_t, int); 60 int, nasid_t, int);
61extern void sn_intr_free(nasid_t, int, struct sn_irq_info *); 61extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
62extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int); 62extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
63extern void sn_set_err_irq_affinity(unsigned int);
63extern struct list_head **sn_irq_lh; 64extern struct list_head **sn_irq_lh;
64 65
65#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector) 66#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
diff --git a/include/asm-ia64/sn/sn_feature_sets.h b/include/asm-ia64/sn/sn_feature_sets.h
index bfdc36273ed4..8e83ac117ace 100644
--- a/include/asm-ia64/sn/sn_feature_sets.h
+++ b/include/asm-ia64/sn/sn_feature_sets.h
@@ -31,6 +31,7 @@ extern int sn_prom_feature_available(int id);
31#define PRF_PAL_CACHE_FLUSH_SAFE 0 31#define PRF_PAL_CACHE_FLUSH_SAFE 0
32#define PRF_DEVICE_FLUSH_LIST 1 32#define PRF_DEVICE_FLUSH_LIST 1
33#define PRF_HOTPLUG_SUPPORT 2 33#define PRF_HOTPLUG_SUPPORT 2
34#define PRF_CPU_DISABLE_SUPPORT 3
34 35
35/* --------------------- OS Features -------------------------------*/ 36/* --------------------- OS Features -------------------------------*/
36 37
diff --git a/include/asm-m32r/assembler.h b/include/asm-m32r/assembler.h
index 47041d19d4a8..26351539b5ff 100644
--- a/include/asm-m32r/assembler.h
+++ b/include/asm-m32r/assembler.h
@@ -52,27 +52,27 @@
52 .endm 52 .endm
53 53
54#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) 54#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
55#define STI(reg) STI_M reg 55#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
56 .macro STI_M reg 56 .macro ENABLE_INTERRUPTS reg
57 setpsw #0x40 -> nop 57 setpsw #0x40 -> nop
58 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). 58 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
59 .endm 59 .endm
60 60
61#define CLI(reg) CLI_M reg 61#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
62 .macro CLI_M reg 62 .macro DISABLE_INTERRUPTS reg
63 clrpsw #0x40 -> nop 63 clrpsw #0x40 -> nop
64 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). 64 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
65 .endm 65 .endm
66#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ 66#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
67#define STI(reg) STI_M reg 67#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
68 .macro STI_M reg 68 .macro ENABLE_INTERRUPTS reg
69 mvfc \reg, psw 69 mvfc \reg, psw
70 or3 \reg, \reg, #0x0040 70 or3 \reg, \reg, #0x0040
71 mvtc \reg, psw 71 mvtc \reg, psw
72 .endm 72 .endm
73 73
74#define CLI(reg) CLI_M reg 74#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
75 .macro CLI_M reg 75 .macro DISABLE_INTERRUPTS reg
76 mvfc \reg, psw 76 mvfc \reg, psw
77 and3 \reg, \reg, #0xffbf 77 and3 \reg, \reg, #0xffbf
78 mvtc \reg, psw 78 mvtc \reg, psw
diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h
index decfc59907c7..214b44b40757 100644
--- a/include/asm-m32r/m32r.h
+++ b/include/asm-m32r/m32r.h
@@ -22,12 +22,26 @@
22#include <asm/m32700ut/m32700ut_pld.h> 22#include <asm/m32700ut/m32700ut_pld.h>
23#include <asm/m32700ut/m32700ut_lan.h> 23#include <asm/m32700ut/m32700ut_lan.h>
24#include <asm/m32700ut/m32700ut_lcd.h> 24#include <asm/m32700ut/m32700ut_lcd.h>
25/* for ei_handler:linux/arch/m32r/kernel/entry.S */
26#define M32R_INT1ICU_ISTS PLD_ICUISTS
27#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
28#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS
29#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE
30#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS
31#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE
25#endif /* CONFIG_PLAT_M32700UT */ 32#endif /* CONFIG_PLAT_M32700UT */
26 33
27#if defined(CONFIG_PLAT_OPSPUT) 34#if defined(CONFIG_PLAT_OPSPUT)
28#include <asm/opsput/opsput_pld.h> 35#include <asm/opsput/opsput_pld.h>
29#include <asm/opsput/opsput_lan.h> 36#include <asm/opsput/opsput_lan.h>
30#include <asm/opsput/opsput_lcd.h> 37#include <asm/opsput/opsput_lcd.h>
38/* for ei_handler:linux/arch/m32r/kernel/entry.S */
39#define M32R_INT1ICU_ISTS PLD_ICUISTS
40#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE
41#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS
42#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE
43#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS
44#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE
31#endif /* CONFIG_PLAT_OPSPUT */ 45#endif /* CONFIG_PLAT_OPSPUT */
32 46
33#if defined(CONFIG_PLAT_MAPPI2) 47#if defined(CONFIG_PLAT_MAPPI2)
@@ -40,10 +54,16 @@
40 54
41#if defined(CONFIG_PLAT_USRV) 55#if defined(CONFIG_PLAT_USRV)
42#include <asm/m32700ut/m32700ut_pld.h> 56#include <asm/m32700ut/m32700ut_pld.h>
57/* for ei_handler:linux/arch/m32r/kernel/entry.S */
58#define M32R_INT1ICU_ISTS PLD_ICUISTS
59#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
43#endif 60#endif
44 61
45#if defined(CONFIG_PLAT_M32104UT) 62#if defined(CONFIG_PLAT_M32104UT)
46#include <asm/m32104ut/m32104ut_pld.h> 63#include <asm/m32104ut/m32104ut_pld.h>
64/* for ei_handler:linux/arch/m32r/kernel/entry.S */
65#define M32R_INT1ICU_ISTS PLD_ICUISTS
66#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE
47#endif /* CONFIG_PLAT_M32104 */ 67#endif /* CONFIG_PLAT_M32104 */
48 68
49/* 69/*
diff --git a/include/asm-m68k/unistd.h b/include/asm-m68k/unistd.h
index fdbb60e6a0d4..a30fe9c64143 100644
--- a/include/asm-m68k/unistd.h
+++ b/include/asm-m68k/unistd.h
@@ -313,10 +313,20 @@
313#define __NR_tee 308 313#define __NR_tee 308
314#define __NR_vmsplice 309 314#define __NR_vmsplice 309
315#define __NR_move_pages 310 315#define __NR_move_pages 310
316#define __NR_sched_setaffinity 311
317#define __NR_sched_getaffinity 312
318#define __NR_kexec_load 313
319#define __NR_getcpu 314
320#define __NR_epoll_pwait 315
321#define __NR_utimensat 316
322#define __NR_signalfd 317
323#define __NR_timerfd 318
324#define __NR_eventfd 319
325#define __NR_fallocate 320
316 326
317#ifdef __KERNEL__ 327#ifdef __KERNEL__
318 328
319#define NR_syscalls 311 329#define NR_syscalls 321
320 330
321#define __ARCH_WANT_IPC_PARSE_VERSION 331#define __ARCH_WANT_IPC_PARSE_VERSION
322#define __ARCH_WANT_OLD_READDIR 332#define __ARCH_WANT_OLD_READDIR
diff --git a/include/asm-m68knommu/unistd.h b/include/asm-m68knommu/unistd.h
index 82e03195f325..eb1b566793fe 100644
--- a/include/asm-m68knommu/unistd.h
+++ b/include/asm-m68knommu/unistd.h
@@ -314,10 +314,20 @@
314#define __NR_tee 308 314#define __NR_tee 308
315#define __NR_vmsplice 309 315#define __NR_vmsplice 309
316#define __NR_move_pages 310 316#define __NR_move_pages 310
317#define __NR_sched_setaffinity 311
318#define __NR_sched_getaffinity 312
319#define __NR_kexec_load 313
320#define __NR_getcpu 314
321#define __NR_epoll_pwait 315
322#define __NR_utimensat 316
323#define __NR_signalfd 317
324#define __NR_timerfd 318
325#define __NR_eventfd 319
326#define __NR_fallocate 320
317 327
318#ifdef __KERNEL__ 328#ifdef __KERNEL__
319 329
320#define NR_syscalls 311 330#define NR_syscalls 321
321 331
322#define __ARCH_WANT_IPC_PARSE_VERSION 332#define __ARCH_WANT_IPC_PARSE_VERSION
323#define __ARCH_WANT_OLD_READDIR 333#define __ARCH_WANT_OLD_READDIR
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
index 3646a3f2ed38..0ba9d6ef76a7 100644
--- a/include/asm-mips/bcache.h
+++ b/include/asm-mips/bcache.h
@@ -21,7 +21,6 @@ struct bcache_ops {
21}; 21};
22 22
23extern void indy_sc_init(void); 23extern void indy_sc_init(void);
24extern void sni_pcimt_sc_init(void);
25 24
26#ifdef CONFIG_BOARD_SCACHE 25#ifdef CONFIG_BOARD_SCACHE
27 26
diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h
index 83719eee2d13..4da0c1fe30d9 100644
--- a/include/asm-mips/edac.h
+++ b/include/asm-mips/edac.h
@@ -9,8 +9,7 @@ static inline void atomic_scrub(void *va, u32 size)
9 unsigned long temp; 9 unsigned long temp;
10 u32 i; 10 u32 i;
11 11
12 for (i = 0; i < size / sizeof(unsigned long); i++, virt_addr++) { 12 for (i = 0; i < size / sizeof(unsigned long); i++) {
13
14 /* 13 /*
15 * Very carefully read and write to memory atomically 14 * Very carefully read and write to memory atomically
16 * so we are interrupt, DMA and SMP safe. 15 * so we are interrupt, DMA and SMP safe.
@@ -19,16 +18,16 @@ static inline void atomic_scrub(void *va, u32 size)
19 */ 18 */
20 19
21 __asm__ __volatile__ ( 20 __asm__ __volatile__ (
22 " .set mips3 \n" 21 " .set mips2 \n"
23 "1: ll %0, %1 # atomic_add \n" 22 "1: ll %0, %1 # atomic_scrub \n"
24 " ll %0, %1 # atomic_add \n" 23 " addu %0, $0 \n"
25 " addu %0, $0 \n" 24 " sc %0, %1 \n"
26 " sc %0, %1 \n" 25 " beqz %0, 1b \n"
27 " beqz %0, 1b \n" 26 " .set mips0 \n"
28 " .set mips0 \n"
29 : "=&r" (temp), "=m" (*virt_addr) 27 : "=&r" (temp), "=m" (*virt_addr)
30 : "m" (*virt_addr)); 28 : "m" (*virt_addr));
31 29
30 virt_addr++;
32 } 31 }
33} 32}
34 33
diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h
deleted file mode 100644
index 8f9bd341ed49..000000000000
--- a/include/asm-mips/gt64240.h
+++ /dev/null
@@ -1,1235 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright - Galileo technology.
7 * Copyright (C) 2004 by Ralf Baechle
8 */
9#ifndef __ASM_MIPS_MV64240_H
10#define __ASM_MIPS_MV64240_H
11
12#include <asm/addrspace.h>
13#include <asm/marvell.h>
14
15/*
16 * CPU Control Registers
17 */
18
19#define CPU_CONFIGURATION 0x000
20#define CPU_MODE 0x120
21#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170
22#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178
23
24/*
25 * Processor Address Space
26 */
27
28/* Sdram's BAR'S */
29#define SCS_0_LOW_DECODE_ADDRESS 0x008
30#define SCS_0_HIGH_DECODE_ADDRESS 0x010
31#define SCS_1_LOW_DECODE_ADDRESS 0x208
32#define SCS_1_HIGH_DECODE_ADDRESS 0x210
33#define SCS_2_LOW_DECODE_ADDRESS 0x018
34#define SCS_2_HIGH_DECODE_ADDRESS 0x020
35#define SCS_3_LOW_DECODE_ADDRESS 0x218
36#define SCS_3_HIGH_DECODE_ADDRESS 0x220
37/* Devices BAR'S */
38#define CS_0_LOW_DECODE_ADDRESS 0x028
39#define CS_0_HIGH_DECODE_ADDRESS 0x030
40#define CS_1_LOW_DECODE_ADDRESS 0x228
41#define CS_1_HIGH_DECODE_ADDRESS 0x230
42#define CS_2_LOW_DECODE_ADDRESS 0x248
43#define CS_2_HIGH_DECODE_ADDRESS 0x250
44#define CS_3_LOW_DECODE_ADDRESS 0x038
45#define CS_3_HIGH_DECODE_ADDRESS 0x040
46#define BOOTCS_LOW_DECODE_ADDRESS 0x238
47#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
48
49#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
50#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
51#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
52#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
53#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
54#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
55#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
56#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
57#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
58#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
59
60#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
61#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
62#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
63#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
64#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
65#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
66#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
67#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
68#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
69#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
70
71#define INTERNAL_SPACE_DECODE 0x068
72
73#define CPU_0_LOW_DECODE_ADDRESS 0x290
74#define CPU_0_HIGH_DECODE_ADDRESS 0x298
75#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
76#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
77
78#define PCI_0I_O_ADDRESS_REMAP 0x0f0
79#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
80#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
81#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
82#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
83#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
84#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
85#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
86#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
87
88#define PCI_1I_O_ADDRESS_REMAP 0x108
89#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
90#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
91#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
92#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
93#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
94#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
95#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
96#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
97
98/*
99 * CPU Sync Barrier
100 */
101
102#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
103#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
104
105
106/*
107 * CPU Access Protect
108 */
109
110#define CPU_LOW_PROTECT_ADDRESS_0 0X180
111#define CPU_HIGH_PROTECT_ADDRESS_0 0X188
112#define CPU_LOW_PROTECT_ADDRESS_1 0X190
113#define CPU_HIGH_PROTECT_ADDRESS_1 0X198
114#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0
115#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8
116#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0
117#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8
118#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0
119#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8
120#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0
121#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8
122#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0
123#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8
124#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0
125#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8
126
127
128/*
129 * Snoop Control
130 */
131
132#define SNOOP_BASE_ADDRESS_0 0x380
133#define SNOOP_TOP_ADDRESS_0 0x388
134#define SNOOP_BASE_ADDRESS_1 0x390
135#define SNOOP_TOP_ADDRESS_1 0x398
136#define SNOOP_BASE_ADDRESS_2 0x3a0
137#define SNOOP_TOP_ADDRESS_2 0x3a8
138#define SNOOP_BASE_ADDRESS_3 0x3b0
139#define SNOOP_TOP_ADDRESS_3 0x3b8
140
141/*
142 * CPU Error Report
143 */
144
145#define CPU_ERROR_ADDRESS_LOW 0x070
146#define CPU_ERROR_ADDRESS_HIGH 0x078
147#define CPU_ERROR_DATA_LOW 0x128
148#define CPU_ERROR_DATA_HIGH 0x130
149#define CPU_ERROR_PARITY 0x138
150#define CPU_ERROR_CAUSE 0x140
151#define CPU_ERROR_MASK 0x148
152
153/*
154 * Pslave Debug
155 */
156
157#define X_0_ADDRESS 0x360
158#define X_0_COMMAND_ID 0x368
159#define X_1_ADDRESS 0x370
160#define X_1_COMMAND_ID 0x378
161#define WRITE_DATA_LOW 0x3c0
162#define WRITE_DATA_HIGH 0x3c8
163#define WRITE_BYTE_ENABLE 0X3e0
164#define READ_DATA_LOW 0x3d0
165#define READ_DATA_HIGH 0x3d8
166#define READ_ID 0x3e8
167
168
169/*
170 * SDRAM and Device Address Space
171 */
172
173
174/*
175 * SDRAM Configuration
176 */
177
178#define SDRAM_CONFIGURATION 0x448
179#define SDRAM_OPERATION_MODE 0x474
180#define SDRAM_ADDRESS_DECODE 0x47C
181#define SDRAM_TIMING_PARAMETERS 0x4b4
182#define SDRAM_UMA_CONTROL 0x4a4
183#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
184#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
185#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
186
187
188/*
189 * SDRAM Parameters
190 */
191
192#define SDRAM_BANK0PARAMETERS 0x44C
193#define SDRAM_BANK1PARAMETERS 0x450
194#define SDRAM_BANK2PARAMETERS 0x454
195#define SDRAM_BANK3PARAMETERS 0x458
196
197
198/*
199 * SDRAM Error Report
200 */
201
202#define SDRAM_ERROR_DATA_LOW 0x484
203#define SDRAM_ERROR_DATA_HIGH 0x480
204#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
205#define SDRAM_RECEIVED_ECC 0x488
206#define SDRAM_CALCULATED_ECC 0x48c
207#define SDRAM_ECC_CONTROL 0x494
208#define SDRAM_ECC_ERROR_COUNTER 0x498
209
210
211/*
212 * SDunit Debug (for internal use)
213 */
214
215#define X0_ADDRESS 0x500
216#define X0_COMMAND_AND_ID 0x504
217#define X0_WRITE_DATA_LOW 0x508
218#define X0_WRITE_DATA_HIGH 0x50c
219#define X0_WRITE_BYTE_ENABLE 0x518
220#define X0_READ_DATA_LOW 0x510
221#define X0_READ_DATA_HIGH 0x514
222#define X0_READ_ID 0x51c
223#define X1_ADDRESS 0x520
224#define X1_COMMAND_AND_ID 0x524
225#define X1_WRITE_DATA_LOW 0x528
226#define X1_WRITE_DATA_HIGH 0x52c
227#define X1_WRITE_BYTE_ENABLE 0x538
228#define X1_READ_DATA_LOW 0x530
229#define X1_READ_DATA_HIGH 0x534
230#define X1_READ_ID 0x53c
231#define X0_SNOOP_ADDRESS 0x540
232#define X0_SNOOP_COMMAND 0x544
233#define X1_SNOOP_ADDRESS 0x548
234#define X1_SNOOP_COMMAND 0x54c
235
236
237/*
238 * Device Parameters
239 */
240
241#define DEVICE_BANK0PARAMETERS 0x45c
242#define DEVICE_BANK1PARAMETERS 0x460
243#define DEVICE_BANK2PARAMETERS 0x464
244#define DEVICE_BANK3PARAMETERS 0x468
245#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
246#define DEVICE_CONTROL 0x4c0
247#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
248#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
249#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
250
251
252/*
253 * Device Interrupt
254 */
255
256#define DEVICE_INTERRUPT_CAUSE 0x4d0
257#define DEVICE_INTERRUPT_MASK 0x4d4
258#define DEVICE_ERROR_ADDRESS 0x4d8
259
260/*
261 * DMA Record
262 */
263
264#define CHANNEL0_DMA_BYTE_COUNT 0x800
265#define CHANNEL1_DMA_BYTE_COUNT 0x804
266#define CHANNEL2_DMA_BYTE_COUNT 0x808
267#define CHANNEL3_DMA_BYTE_COUNT 0x80C
268#define CHANNEL4_DMA_BYTE_COUNT 0x900
269#define CHANNEL5_DMA_BYTE_COUNT 0x904
270#define CHANNEL6_DMA_BYTE_COUNT 0x908
271#define CHANNEL7_DMA_BYTE_COUNT 0x90C
272#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
273#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
274#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
275#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
276#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
277#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
278#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
279#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
280#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
281#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
282#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
283#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
284#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
285#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
286#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
287#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
288#define CHANNEL0NEXT_RECORD_POINTER 0x830
289#define CHANNEL1NEXT_RECORD_POINTER 0x834
290#define CHANNEL2NEXT_RECORD_POINTER 0x838
291#define CHANNEL3NEXT_RECORD_POINTER 0x83C
292#define CHANNEL4NEXT_RECORD_POINTER 0x930
293#define CHANNEL5NEXT_RECORD_POINTER 0x934
294#define CHANNEL6NEXT_RECORD_POINTER 0x938
295#define CHANNEL7NEXT_RECORD_POINTER 0x93C
296#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
297#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
298#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
299#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
300#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
301#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
302#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
303#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
304#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
305#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
306#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
307#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
308#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
309#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
310#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
311#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
312#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
313#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
314#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
315#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
316#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
317#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
318#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
319#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
320#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
321#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
322#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
323#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
324#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
325#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
326#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
327#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
328
329/*
330 * DMA Channel Control
331 */
332
333#define CHANNEL0CONTROL 0x840
334#define CHANNEL0CONTROL_HIGH 0x880
335
336#define CHANNEL1CONTROL 0x844
337#define CHANNEL1CONTROL_HIGH 0x884
338
339#define CHANNEL2CONTROL 0x848
340#define CHANNEL2CONTROL_HIGH 0x888
341
342#define CHANNEL3CONTROL 0x84C
343#define CHANNEL3CONTROL_HIGH 0x88C
344
345#define CHANNEL4CONTROL 0x940
346#define CHANNEL4CONTROL_HIGH 0x980
347
348#define CHANNEL5CONTROL 0x944
349#define CHANNEL5CONTROL_HIGH 0x984
350
351#define CHANNEL6CONTROL 0x948
352#define CHANNEL6CONTROL_HIGH 0x988
353
354#define CHANNEL7CONTROL 0x94C
355#define CHANNEL7CONTROL_HIGH 0x98C
356
357
358/*
359 * DMA Arbiter
360 */
361
362#define ARBITER_CONTROL_0_3 0x860
363#define ARBITER_CONTROL_4_7 0x960
364
365
366/*
367 * DMA Interrupt
368 */
369
370#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
371#define CHANELS0_3_INTERRUPT_MASK 0x8c4
372#define CHANELS0_3_ERROR_ADDRESS 0x8c8
373#define CHANELS0_3_ERROR_SELECT 0x8cc
374#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
375#define CHANELS4_7_INTERRUPT_MASK 0x9c4
376#define CHANELS4_7_ERROR_ADDRESS 0x9c8
377#define CHANELS4_7_ERROR_SELECT 0x9cc
378
379
380/*
381 * DMA Debug (for internal use)
382 */
383
384#define DMA_X0_ADDRESS 0x8e0
385#define DMA_X0_COMMAND_AND_ID 0x8e4
386#define DMA_X0_WRITE_DATA_LOW 0x8e8
387#define DMA_X0_WRITE_DATA_HIGH 0x8ec
388#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
389#define DMA_X0_READ_DATA_LOW 0x8f0
390#define DMA_X0_READ_DATA_HIGH 0x8f4
391#define DMA_X0_READ_ID 0x8fc
392#define DMA_X1_ADDRESS 0x9e0
393#define DMA_X1_COMMAND_AND_ID 0x9e4
394#define DMA_X1_WRITE_DATA_LOW 0x9e8
395#define DMA_X1_WRITE_DATA_HIGH 0x9ec
396#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
397#define DMA_X1_READ_DATA_LOW 0x9f0
398#define DMA_X1_READ_DATA_HIGH 0x9f4
399#define DMA_X1_READ_ID 0x9fc
400
401/*
402 * Timer_Counter
403 */
404
405#define TIMER_COUNTER0 0x850
406#define TIMER_COUNTER1 0x854
407#define TIMER_COUNTER2 0x858
408#define TIMER_COUNTER3 0x85C
409#define TIMER_COUNTER_0_3_CONTROL 0x864
410#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
411#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
412#define TIMER_COUNTER4 0x950
413#define TIMER_COUNTER5 0x954
414#define TIMER_COUNTER6 0x958
415#define TIMER_COUNTER7 0x95C
416#define TIMER_COUNTER_4_7_CONTROL 0x964
417#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
418#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
419
420/*
421 * PCI Slave Address Decoding
422 */
423
424#define PCI_0SCS_0_BANK_SIZE 0xc08
425#define PCI_1SCS_0_BANK_SIZE 0xc88
426#define PCI_0SCS_1_BANK_SIZE 0xd08
427#define PCI_1SCS_1_BANK_SIZE 0xd88
428#define PCI_0SCS_2_BANK_SIZE 0xc0c
429#define PCI_1SCS_2_BANK_SIZE 0xc8c
430#define PCI_0SCS_3_BANK_SIZE 0xd0c
431#define PCI_1SCS_3_BANK_SIZE 0xd8c
432#define PCI_0CS_0_BANK_SIZE 0xc10
433#define PCI_1CS_0_BANK_SIZE 0xc90
434#define PCI_0CS_1_BANK_SIZE 0xd10
435#define PCI_1CS_1_BANK_SIZE 0xd90
436#define PCI_0CS_2_BANK_SIZE 0xd18
437#define PCI_1CS_2_BANK_SIZE 0xd98
438#define PCI_0CS_3_BANK_SIZE 0xc14
439#define PCI_1CS_3_BANK_SIZE 0xc94
440#define PCI_0CS_BOOT_BANK_SIZE 0xd14
441#define PCI_1CS_BOOT_BANK_SIZE 0xd94
442#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
443#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
444#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
445#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
446#define PCI_0P2P_I_O_BAR_SIZE 0xd24
447#define PCI_1P2P_I_O_BAR_SIZE 0xda4
448#define PCI_0CPU_BAR_SIZE 0xd28
449#define PCI_1CPU_BAR_SIZE 0xda8
450#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
451#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
452#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
453#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
454#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
455#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
456#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
457#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
458#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
459#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
460#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
461#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
462#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
463#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
464#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
465#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
466#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
467#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
468#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
469#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
470#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
471#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
472#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
473#define PCI_1DAC_CPU_BAR_SIZE 0xeac
474#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
475#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
476#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
477#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
478#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
479#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
480#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
481#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
482#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
483#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
484#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
485#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
486#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
487#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
488#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
489#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
490#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
491#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
492#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
493#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
494#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
495#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
496#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
497#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
498#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
499#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
500#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
501#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
502#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
503#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
504#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
505#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
506#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
507#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
508#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
509#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
510#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
511#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
512#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
513#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
514#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
515#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
516#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
517#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
518#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
519#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
520#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
521#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
522#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
523#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
524#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
525#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
526#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
527#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
528#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
529#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
530#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
531#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
532#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
533#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
534#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
535#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
536#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
537#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
538#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
539#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
540
541/*
542 * PCI Control
543 */
544
545#define PCI_0COMMAND 0xc00
546#define PCI_1COMMAND 0xc80
547#define PCI_0MODE 0xd00
548#define PCI_1MODE 0xd80
549#define PCI_0TIMEOUT_RETRY 0xc04
550#define PCI_1TIMEOUT_RETRY 0xc84
551#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
552#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
553#define MSI_0TRIGGER_TIMER 0xc38
554#define MSI_1TRIGGER_TIMER 0xcb8
555#define PCI_0ARBITER_CONTROL 0x1d00
556#define PCI_1ARBITER_CONTROL 0x1d80
557/* changing untill here */
558#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
559#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
560#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
561#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
562#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
563#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
564#define PCI_0P2P_CONFIGURATION 0x1d14
565#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
566#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
567#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
568#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10
569#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
570#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
571#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20
572#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
573#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
574#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30
575#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
576#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
577#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40
578#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
579#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
580#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50
581#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
582#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
583#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60
584#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
585#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
586#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70
587#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
588#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
589#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
590#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
591#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
592#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
593#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
594#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
595#define PCI_1P2P_CONFIGURATION 0x1d94
596#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
597#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
598#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
599#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90
600#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
601#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
602#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0
603#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
604#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
605#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0
606#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
607#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
608#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0
609#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
610#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
611#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0
612#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
613#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
614#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0
615#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
616#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
617#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0
618#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
619#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
620
621/*
622 * PCI Snoop Control
623 */
624
625#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
626#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
627#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
628#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
629#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
630#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
631#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
632#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
633#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
634#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
635#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
636#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
637#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
638#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
639#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
640#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
641#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
642#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
643#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
644#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
645#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
646#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
647#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
648#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
649
650/*
651 * PCI Configuration Address
652 */
653
654#define PCI_0CONFIGURATION_ADDRESS 0xcf8
655#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
656#define PCI_1CONFIGURATION_ADDRESS 0xc78
657#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
658#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
659#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
660
661/*
662 * PCI Error Report
663 */
664
665#define PCI_0SERR_MASK 0xc28
666#define PCI_0ERROR_ADDRESS_LOW 0x1d40
667#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
668#define PCI_0ERROR_DATA_LOW 0x1d48
669#define PCI_0ERROR_DATA_HIGH 0x1d4c
670#define PCI_0ERROR_COMMAND 0x1d50
671#define PCI_0ERROR_CAUSE 0x1d58
672#define PCI_0ERROR_MASK 0x1d5c
673
674#define PCI_1SERR_MASK 0xca8
675#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
676#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
677#define PCI_1ERROR_DATA_LOW 0x1dc8
678#define PCI_1ERROR_DATA_HIGH 0x1dcc
679#define PCI_1ERROR_COMMAND 0x1dd0
680#define PCI_1ERROR_CAUSE 0x1dd8
681#define PCI_1ERROR_MASK 0x1ddc
682
683
684/*
685 * Lslave Debug (for internal use)
686 */
687
688#define L_SLAVE_X0_ADDRESS 0x1d20
689#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
690#define L_SLAVE_X1_ADDRESS 0x1d28
691#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
692#define L_SLAVE_WRITE_DATA_LOW 0x1d30
693#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
694#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
695#define L_SLAVE_READ_DATA_LOW 0x1d38
696#define L_SLAVE_READ_DATA_HIGH 0x1d3c
697#define L_SLAVE_READ_ID 0x1d64
698
699#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */
700
701/*
702 * PCI Configuration Function 0
703 */
704
705#define PCI_DEVICE_AND_VENDOR_ID 0x000
706#define PCI_STATUS_AND_COMMAND 0x004
707#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
708#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
709#define PCI_SCS_0_BASE_ADDRESS 0x010
710#define PCI_SCS_1_BASE_ADDRESS 0x014
711#define PCI_SCS_2_BASE_ADDRESS 0x018
712#define PCI_SCS_3_BASE_ADDRESS 0x01C
713#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
714#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
715#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
716#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
717#define PCI_CAPABILTY_LIST_POINTER 0x034
718#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
719#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
720#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
721#define PCI_VPD_ADDRESS 0x048
722#define PCI_VPD_DATA 0X04c
723#define PCI_MSI_MESSAGE_CONTROL 0x050
724#define PCI_MSI_MESSAGE_ADDRESS 0x054
725#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
726#define PCI_MSI_MESSAGE_DATA 0x05c
727#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
728
729/*
730 * PCI Configuration Function 1
731 */
732
733#define PCI_CS_0_BASE_ADDRESS 0x110
734#define PCI_CS_1_BASE_ADDRESS 0x114
735#define PCI_CS_2_BASE_ADDRESS 0x118
736#define PCI_CS_3_BASE_ADDRESS 0x11c
737#define PCI_BOOTCS_BASE_ADDRESS 0x120
738
739/*
740 * PCI Configuration Function 2
741 */
742
743#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
744#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
745#define PCI_P2P_I_O_BASE_ADDRESS 0x218
746#define PCI_CPU_BASE_ADDRESS 0x21c
747
748/*
749 * PCI Configuration Function 4
750 */
751
752#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
753#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
754#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
755#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
756#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
757#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
758
759
760/*
761 * PCI Configuration Function 5
762 */
763
764#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
765#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
766#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
767#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
768#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
769#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
770
771
772/*
773 * PCI Configuration Function 6
774 */
775
776#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
777#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
778#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
779#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
780#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
781#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
782
783/*
784 * PCI Configuration Function 7
785 */
786
787#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
788#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
789#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
790#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
791#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
792#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
793#endif
794
795/*
796 * Interrupts
797 */
798
799#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
800#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
801#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
802#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
803#define CPU_SELECT_CAUSE_REGISTER 0xc70
804#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
805#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
806#define PCI_0SELECT_CAUSE 0xc74
807#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
808#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
809#define PCI_1SELECT_CAUSE 0xcf4
810#define CPU_INT_0_MASK 0xe60
811#define CPU_INT_1_MASK 0xe64
812#define CPU_INT_2_MASK 0xe68
813#define CPU_INT_3_MASK 0xe6c
814
815/*
816 * I20 Support registers
817 */
818
819#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010
820#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014
821#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018
822#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C
823#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020
824#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024
825#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028
826#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C
827#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030
828#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034
829#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040
830#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044
831#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050
832#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054
833#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060
834#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064
835#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068
836#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C
837#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070
838#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074
839#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8
840#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC
841
842#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090
843#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094
844#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098
845#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C
846#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0
847#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4
848#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8
849#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC
850#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0
851#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4
852#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0
853#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4
854#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0
855#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4
856#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0
857#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4
858#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8
859#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC
860#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0
861#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4
862#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078
863#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C
864
865#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10
866#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14
867#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18
868#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C
869#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20
870#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24
871#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28
872#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C
873#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30
874#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34
875#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40
876#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44
877#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50
878#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54
879#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60
880#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64
881#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68
882#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C
883#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70
884#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74
885#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8
886#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC
887
888#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90
889#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94
890#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98
891#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C
892#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0
893#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4
894#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8
895#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC
896#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0
897#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4
898#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0
899#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4
900#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0
901#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4
902#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0
903#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4
904#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8
905#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC
906#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0
907#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4
908#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78
909#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C
910
911/*
912 * Communication Unit Registers
913 */
914
915#define ETHERNET_0_ADDRESS_CONTROL_LOW
916#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
917#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
918#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
919#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
920#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
921#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
922#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
923#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
924#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
925#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
926#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
927#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
928#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
929#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
930#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
931#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
932#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
933#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
934#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
935#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
936#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
937#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
938#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
939#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
940#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
941#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
942#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0
943#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4
944#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8
945#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac
946#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0
947#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4
948#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0
949#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4
950#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
951#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
952#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
953#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
954#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
955#define SERIAL_INIT_LAST_DATA 0xf324
956#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
957#define COMM_UNIT_ARBITER_CONTROL 0xf300
958#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
959#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
960#define COMM_UNIT_INTERRUPT_MASK 0xf314
961#define COMM_UNIT_ERROR_ADDRESS 0xf314
962
963/*
964 * Cunit Debug (for internal use)
965 */
966
967#define CUNIT_ADDRESS 0xf340
968#define CUNIT_COMMAND_AND_ID 0xf344
969#define CUNIT_WRITE_DATA_LOW 0xf348
970#define CUNIT_WRITE_DATA_HIGH 0xf34c
971#define CUNIT_WRITE_BYTE_ENABLE 0xf358
972#define CUNIT_READ_DATA_LOW 0xf350
973#define CUNIT_READ_DATA_HIGH 0xf354
974#define CUNIT_READ_ID 0xf35c
975
976/*
977 * Fast Ethernet Unit Registers
978 */
979
980/* Ethernet */
981
982#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
983#define ETHERNET_SMI_REGISTER 0x2010
984
985/* Ethernet 0 */
986
987#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
988#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
989#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
990#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
991#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
992#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
993#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
994#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
995#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
996#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
997#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
998#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
999#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
1000#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
1001#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
1002#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
1003#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
1004#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
1005#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
1006#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
1007#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
1008#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
1009#define ETHERNET0_MIB_COUNTER_BASE 0x2500
1010
1011/* Ethernet 1 */
1012
1013#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
1014#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
1015#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
1016#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
1017#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
1018#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
1019#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
1020#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
1021#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
1022#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
1023#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
1024#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
1025#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
1026#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
1027#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
1028#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
1029#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
1030#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
1031#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
1032#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
1033#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
1034#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
1035#define ETHERNET1_MIB_COUNTER_BASE 0x2900
1036
1037/* Ethernet 2 */
1038
1039#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
1040#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
1041#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
1042#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
1043#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
1044#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
1045#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
1046#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
1047#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
1048#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
1049#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
1050#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
1051#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
1052#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
1053#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
1054#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
1055#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
1056#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
1057#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
1058#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
1059#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
1060#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
1061#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
1062
1063/*
1064 * SDMA Registers
1065 */
1066
1067#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
1068#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
1069#define CHANNEL0_COMMAND_REGISTER 0x4008
1070#define CHANNEL0_RX_CMD_STATUS 0x4800
1071#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
1072#define CHANNEL0_RX_BUFFER_POINTER 0x4808
1073#define CHANNEL0_RX_NEXT_POINTER 0x480c
1074#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
1075#define CHANNEL0_TX_CMD_STATUS 0x4C00
1076#define CHANNEL0_TX_PACKET_SIZE 0x4C04
1077#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
1078#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
1079#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
1080#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
1081#define CHANNEL1_CONFIGURATION_REGISTER 0x6000
1082#define CHANNEL1_COMMAND_REGISTER 0x6008
1083#define CHANNEL1_RX_CMD_STATUS 0x6800
1084#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804
1085#define CHANNEL1_RX_BUFFER_POINTER 0x6808
1086#define CHANNEL1_RX_NEXT_POINTER 0x680c
1087#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1088#define CHANNEL1_TX_CMD_STATUS 0x6C00
1089#define CHANNEL1_TX_PACKET_SIZE 0x6C04
1090#define CHANNEL1_TX_BUFFER_POINTER 0x6C08
1091#define CHANNEL1_TX_NEXT_POINTER 0x6C0c
1092#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1093#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
1094#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
1095
1096/* SDMA Interrupt */
1097
1098#define SDMA_CAUSE 0xb820
1099#define SDMA_MASK 0xb8a0
1100
1101
1102/*
1103 * Baude Rate Generators Registers
1104 */
1105
1106/* BRG 0 */
1107
1108#define BRG0_CONFIGURATION_REGISTER 0xb200
1109#define BRG0_BAUDE_TUNING_REGISTER 0xb204
1110
1111/* BRG 1 */
1112
1113#define BRG1_CONFIGURATION_REGISTER 0xb208
1114#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
1115
1116/* BRG 2 */
1117
1118#define BRG2_CONFIGURATION_REGISTER 0xb210
1119#define BRG2_BAUDE_TUNING_REGISTER 0xb214
1120
1121/* BRG Interrupts */
1122
1123#define BRG_CAUSE_REGISTER 0xb834
1124#define BRG_MASK_REGISTER 0xb8b4
1125
1126/* MISC */
1127
1128#define MAIN_ROUTING_REGISTER 0xb400
1129#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
1130#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
1131#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
1132#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
1133#define WATCHDOG_VALUE_REGISTER 0xb414
1134
1135
1136/*
1137 * Flex TDM Registers
1138 */
1139
1140/* FTDM Port */
1141
1142#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
1143#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
1144#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
1145#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
1146#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
1147#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
1148#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
1149
1150/* FTDM Interrupts */
1151
1152#define FTDM_CAUSE_REGISTER 0xb830
1153#define FTDM_MASK_REGISTER 0xb8b0
1154
1155
1156/*
1157 * GPP Interface Registers
1158 */
1159
1160#define GPP_IO_CONTROL 0xf100
1161#define GPP_LEVEL_CONTROL 0xf110
1162#define GPP_VALUE 0xf104
1163#define GPP_INTERRUPT_CAUSE 0xf108
1164#define GPP_INTERRUPT_MASK 0xf10c
1165
1166#define MPP_CONTROL0 0xf000
1167#define MPP_CONTROL1 0xf004
1168#define MPP_CONTROL2 0xf008
1169#define MPP_CONTROL3 0xf00c
1170#define DEBUG_PORT_MULTIPLEX 0xf014
1171#define SERIAL_PORT_MULTIPLEX 0xf010
1172
1173/*
1174 * I2C Registers
1175 */
1176
1177#define I2C_SLAVE_ADDRESS 0xc000
1178#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
1179#define I2C_DATA 0xc004
1180#define I2C_CONTROL 0xc008
1181#define I2C_STATUS_BAUDE_RATE 0xc00C
1182#define I2C_SOFT_RESET 0xc01c
1183
1184/*
1185 * MPSC Registers
1186 */
1187
1188/*
1189 * MPSC0
1190 */
1191
1192#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
1193#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
1194#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
1195#define CHANNEL0_REGISTER1 0x800c
1196#define CHANNEL0_REGISTER2 0x8010
1197#define CHANNEL0_REGISTER3 0x8014
1198#define CHANNEL0_REGISTER4 0x8018
1199#define CHANNEL0_REGISTER5 0x801c
1200#define CHANNEL0_REGISTER6 0x8020
1201#define CHANNEL0_REGISTER7 0x8024
1202#define CHANNEL0_REGISTER8 0x8028
1203#define CHANNEL0_REGISTER9 0x802c
1204#define CHANNEL0_REGISTER10 0x8030
1205#define CHANNEL0_REGISTER11 0x8034
1206
1207/*
1208 * MPSC1
1209 */
1210
1211#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000
1212#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004
1213#define MPSC1_PROTOCOL_CONFIGURATION 0x9008
1214#define CHANNEL1_REGISTER1 0x900c
1215#define CHANNEL1_REGISTER2 0x9010
1216#define CHANNEL1_REGISTER3 0x9014
1217#define CHANNEL1_REGISTER4 0x9018
1218#define CHANNEL1_REGISTER5 0x901c
1219#define CHANNEL1_REGISTER6 0x9020
1220#define CHANNEL1_REGISTER7 0x9024
1221#define CHANNEL1_REGISTER8 0x9028
1222#define CHANNEL1_REGISTER9 0x902c
1223#define CHANNEL1_REGISTER10 0x9030
1224#define CHANNEL1_REGISTER11 0x9034
1225
1226/*
1227 * MPSCs Interupts
1228 */
1229
1230#define MPSC0_CAUSE 0xb804
1231#define MPSC0_MASK 0xb884
1232#define MPSC1_CAUSE 0xb80c
1233#define MPSC1_MASK 0xb88c
1234
1235#endif /* __ASM_MIPS_MV64240_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 918a4894b587..6a5fa32f615b 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -172,6 +172,7 @@ ASMMACRO(tlb_probe_hazard,
172 nop; nop; nop 172 nop; nop; nop
173 ) 173 )
174ASMMACRO(irq_enable_hazard, 174ASMMACRO(irq_enable_hazard,
175 _ssnop; _ssnop; _ssnop;
175 ) 176 )
176ASMMACRO(irq_disable_hazard, 177ASMMACRO(irq_disable_hazard,
177 nop; nop; nop 178 nop; nop; nop
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
index 92f6c36aac4d..5097cbf183a9 100644
--- a/include/asm-mips/ioctls.h
+++ b/include/asm-mips/ioctls.h
@@ -77,6 +77,10 @@
77#define TIOCSBRK 0x5427 /* BSD compatibility */ 77#define TIOCSBRK 0x5427 /* BSD compatibility */
78#define TIOCCBRK 0x5428 /* BSD compatibility */ 78#define TIOCCBRK 0x5428 /* BSD compatibility */
79#define TIOCGSID 0x7416 /* Return the session ID of FD */ 79#define TIOCGSID 0x7416 /* Return the session ID of FD */
80#define TCGETS2 _IOR('T',0x2A, struct termios2)
81#define TCSETS2 _IOW('T',0x2B, struct termios2)
82#define TCSETSW2 _IOW('T',0x2C, struct termios2)
83#define TCSETSF2 _IOW('T',0x2D, struct termios2)
80#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 84#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
81#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 85#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
82 86
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2d..b2dc35f56181 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
13#include <asm/jmr3927/tx3927.h> 13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/system.h> 15#include <asm/system.h>
16#include <asm/txx9irq.h>
16 17
17/* CS */ 18/* CS */
18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
@@ -115,7 +116,7 @@
115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
117 118
118#define JMR3927_IRQ_IRC 16 119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
121 122
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb759..4be2f25f70dd 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
50 volatile unsigned long unused0; 50 volatile unsigned long unused0;
51}; 51};
52 52
53struct tx3927_irc_reg {
54 volatile unsigned long cer;
55 volatile unsigned long cr[2];
56 volatile unsigned long unused0;
57 volatile unsigned long ilr[8];
58 volatile unsigned long unused1[4];
59 volatile unsigned long imr;
60 volatile unsigned long unused2[7];
61 volatile unsigned long scr;
62 volatile unsigned long unused3[7];
63 volatile unsigned long ssr;
64 volatile unsigned long unused4[7];
65 volatile unsigned long csr;
66};
67
68#include <asm/byteorder.h> 53#include <asm/byteorder.h>
69 54
70#ifdef __BIG_ENDIAN 55#ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
225/* 210/*
226 * IRC 211 * IRC
227 */ 212 */
228#define TX3927_IR_MAX_LEVEL 7
229
230/* IRCER : Int. Control Enable */
231#define TX3927_IRCER_ICE 0x00000001
232
233/* IRCR : Int. Control */
234#define TX3927_IRCR_LOW 0x00000000
235#define TX3927_IRCR_HIGH 0x00000001
236#define TX3927_IRCR_DOWN 0x00000002
237#define TX3927_IRCR_UP 0x00000003
238
239/* IRSCR : Int. Status Control */
240#define TX3927_IRSCR_EIClrE 0x00000100
241#define TX3927_IRSCR_EIClr_MASK 0x0000000f
242
243/* IRCSR : Int. Current Status */
244#define TX3927_IRCSR_IF 0x00010000
245#define TX3927_IRCSR_ILV_MASK 0x00000700
246#define TX3927_IRCSR_IVL_MASK 0x0000001f
247
248#define TX3927_IR_INT0 0 213#define TX3927_IR_INT0 0
249#define TX3927_IR_INT1 1 214#define TX3927_IR_INT1 1
250#define TX3927_IR_INT2 2 215#define TX3927_IR_INT2 2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
347#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 312#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
348#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 313#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
349#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 314#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
350#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
351#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 315#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
352#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 316#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
353#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) 317#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 6eba2e576aaa..a77128362a7d 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -33,13 +33,24 @@ static __inline__ int ide_probe_legacy(void)
33{ 33{
34#ifdef CONFIG_PCI 34#ifdef CONFIG_PCI
35 struct pci_dev *dev; 35 struct pci_dev *dev;
36 if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL || 36 /*
37 (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) { 37 * This can be called on the ide_setup() path, super-early in
38 pci_dev_put(dev); 38 * boot. But the down_read() will enable local interrupts,
39 39 * which can cause some machines to crash. So here we detect
40 return 1; 40 * and flag that situation and bail out early.
41 } 41 */
42 if (no_pci_devices())
43 return 0;
44 dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
45 if (dev)
46 goto found;
47 dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
48 if (dev)
49 goto found;
42 return 0; 50 return 0;
51found:
52 pci_dev_put(dev);
53 return 1;
43#elif defined(CONFIG_EISA) || defined(CONFIG_ISA) 54#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
44 return 1; 55 return 1;
45#else 56#else
@@ -49,48 +60,42 @@ static __inline__ int ide_probe_legacy(void)
49 60
50static __inline__ int ide_default_irq(unsigned long base) 61static __inline__ int ide_default_irq(unsigned long base)
51{ 62{
52 if (ide_probe_legacy()) 63 switch (base) {
53 switch (base) { 64 case 0x1f0: return 14;
54 case 0x1f0: 65 case 0x170: return 15;
55 return 14; 66 case 0x1e8: return 11;
56 case 0x170: 67 case 0x168: return 10;
57 return 15; 68 case 0x1e0: return 8;
58 case 0x1e8: 69 case 0x160: return 12;
59 return 11;
60 case 0x168:
61 return 10;
62 case 0x1e0:
63 return 8;
64 case 0x160:
65 return 12;
66 default: 70 default:
67 return 0; 71 return 0;
68 } 72 }
69 else
70 return 0;
71} 73}
72 74
73static __inline__ unsigned long ide_default_io_base(int index) 75static __inline__ unsigned long ide_default_io_base(int index)
74{ 76{
75 if (ide_probe_legacy()) 77 if (!ide_probe_legacy())
78 return 0;
79 /*
80 * If PCI is present then it is not safe to poke around
81 * the other legacy IDE ports. Only 0x1f0 and 0x170 are
82 * defined compatibility mode ports for PCI. A user can
83 * override this using ide= but we must default safe.
84 */
85 if (no_pci_devices()) {
76 switch (index) { 86 switch (index) {
77 case 0: 87 case 2: return 0x1e8;
78 return 0x1f0; 88 case 3: return 0x168;
79 case 1: 89 case 4: return 0x1e0;
80 return 0x170; 90 case 5: return 0x160;
81 case 2:
82 return 0x1e8;
83 case 3:
84 return 0x168;
85 case 4:
86 return 0x1e0;
87 case 5:
88 return 0x160;
89 default:
90 return 0;
91 } 91 }
92 else 92 }
93 switch (index) {
94 case 0: return 0x1f0;
95 case 1: return 0x170;
96 default:
93 return 0; 97 return 0;
98 }
94} 99}
95 100
96#define IDE_ARCH_OBSOLETE_INIT 101#define IDE_ARCH_OBSOLETE_INIT
diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h
deleted file mode 100644
index a62ecb53c751..000000000000
--- a/include/asm-mips/mach-ocelot/mach-gt64120.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
11#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
12
13/*
14 * PCI address allocation
15 */
16#define GT_PCI_MEM_BASE (0x22000000UL)
17#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE
18#define GT_PCI_IO_BASE (0x20000000UL)
19#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE
20
21extern unsigned long gt64120_base;
22
23#define GT64120_BASE (gt64120_base)
24
25/*
26 * GT timer irq
27 */
28#define GT_TIMER 6
29
30#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
deleted file mode 100644
index b6144bafc565..000000000000
--- a/include/asm-mips/marvell.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 */
8#ifndef __ASM_MIPS_MARVELL_H
9#define __ASM_MIPS_MARVELL_H
10
11#include <linux/pci.h>
12
13#include <asm/byteorder.h>
14
15extern unsigned long marvell_base;
16
17/*
18 * Because of an error/peculiarity in the Galileo chip, we need to swap the
19 * bytes when running bigendian.
20 */
21#define __MV_READ(ofs) \
22 (*(volatile u32 *)(marvell_base+(ofs)))
23#define __MV_WRITE(ofs, data) \
24 do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0)
25
26#define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs))
27#define MV_WRITE(ofs, data) __MV_WRITE(ofs, cpu_to_le32(data))
28
29#define MV_READ_16(ofs) \
30 le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs)))
31#define MV_WRITE_16(ofs, data) \
32 *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data)
33
34#define MV_READ_8(ofs) \
35 *(volatile u8 *)(marvell_base+(ofs))
36#define MV_WRITE_8(ofs, data) \
37 *(volatile u8 *)(marvell_base+(ofs)) = data
38
39#define MV_SET_REG_BITS(ofs, bits) \
40 (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits))
41#define MV_RESET_REG_BITS(ofs, bits) \
42 (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits))
43
44extern struct pci_ops mv_pci_ops;
45
46struct mv_pci_controller {
47 struct pci_controller pcic;
48
49 /*
50 * GT-64240/MV-64340 specific, per host bus information
51 */
52 unsigned long config_addr;
53 unsigned long config_vreg;
54};
55
56extern void ll_mv64340_irq(void);
57extern void mv64340_irq_init(unsigned int base);
58
59#endif /* __ASM_MIPS_MARVELL_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 2fbd47eba32d..59c865deb0c7 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
43 */ 43 */
44 44
45/* PGDIR_SHIFT determines what a third-level page table entry can map */ 45/* PGDIR_SHIFT determines what a third-level page table entry can map */
46#ifdef CONFIG_64BIT_PHYS_ADDR 46#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
47#define PGDIR_SHIFT 21
48#else
49#define PGDIR_SHIFT 22
50#endif
51#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 47#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
52#define PGDIR_MASK (~(PGDIR_SIZE-1)) 48#define PGDIR_MASK (~(PGDIR_SIZE-1))
53 49
@@ -55,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
55 * Entries per page directory level: we use two-level, so 51 * Entries per page directory level: we use two-level, so
56 * we don't really have any PUD/PMD directory physically. 52 * we don't really have any PUD/PMD directory physically.
57 */ 53 */
58#ifdef CONFIG_64BIT_PHYS_ADDR 54#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
59#define PGD_ORDER 1 55#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
60#define PUD_ORDER aieeee_attempt_to_allocate_pud 56#define PUD_ORDER aieeee_attempt_to_allocate_pud
61#define PMD_ORDER 1 57#define PMD_ORDER 1
62#define PTE_ORDER 0 58#define PTE_ORDER 0
63#else
64#define PGD_ORDER 0
65#define PUD_ORDER aieeee_attempt_to_allocate_pud
66#define PMD_ORDER 1
67#define PTE_ORDER 0
68#endif
69 59
70#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 60#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
71#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 61#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 2e2d70d13ff6..d2ee28156743 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -168,11 +168,15 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
168#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) 168#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
169#endif 169#endif
170 170
171#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) 171#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
172#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) 172#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
173#define PTE_T_LOG2 ffz(~sizeof(pte_t)) 173#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
174 174
175extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 175/*
176 * We used to declare this array with size but gcc 3.3 and older are not able
177 * to find that this expression is a constant, so the size is dropped.
178 */
179extern pgd_t swapper_pg_dir[];
176 180
177/* 181/*
178 * The following only work if pte_present() is true. 182 * The following only work if pte_present() is true.
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index 2738c1366f66..c34d36b6b8c2 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -227,10 +227,15 @@
227 (A_BCM1480_DUART(chan) + \ 227 (A_BCM1480_DUART(chan) + \
228 BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) 228 BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
229 229
230#define DUART_IMRISR_SPACING 0x20
231#define DUART_INCHNG_SPACING 0x10
232
230#define R_BCM1480_DUART_IMRREG(chan) \ 233#define R_BCM1480_DUART_IMRREG(chan) \
231 (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) 234 (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
232#define R_BCM1480_DUART_ISRREG(chan) \ 235#define R_BCM1480_DUART_ISRREG(chan) \
233 (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) 236 (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
237#define R_BCM1480_DUART_INCHREG(chan) \
238 (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
234 239
235#define A_BCM1480_DUART_IMRREG(chan) \ 240#define A_BCM1480_DUART_IMRREG(chan) \
236 (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) 241 (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf3..ff3e8936b493 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
55 55
56#define PARKED_INDEX ((unsigned int)0x80000000) 56#define PARKED_INDEX ((unsigned int)0x80000000)
57 57
58/*
59 * Define low-level interrupt mask for IPIs, if necessary.
60 * By default, use SW interrupt 1, which requires no external
61 * hardware support, but which works only for single-core
62 * MIPS MT systems.
63 */
64#ifndef MIPS_CPU_IPI_IRQ
65#define MIPS_CPU_IPI_IRQ 1
66#endif
67
58#endif /* _ASM_SMTC_MT_H */ 68#endif /* _ASM_SMTC_MT_H */
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
index 07f873351a86..0bf82818aa53 100644
--- a/include/asm-mips/stacktrace.h
+++ b/include/asm-mips/stacktrace.h
@@ -9,7 +9,11 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
9 unsigned long pc, unsigned long *ra); 9 unsigned long pc, unsigned long *ra);
10#else 10#else
11#define raw_show_trace 1 11#define raw_show_trace 1
12#define unwind_stack(task, sp, pc, ra) 0 12static inline unsigned long unwind_stack(struct task_struct *task,
13 unsigned long *sp, unsigned long pc, unsigned long *ra)
14{
15 return 0;
16}
13#endif 17#endif
14 18
15static __always_inline void prepare_frametrace(struct pt_regs *regs) 19static __always_inline void prepare_frametrace(struct pt_regs *regs)
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
index 5bfdc3b64510..c83c68444e86 100644
--- a/include/asm-mips/termbits.h
+++ b/include/asm-mips/termbits.h
@@ -164,6 +164,7 @@ struct ktermios {
164#define HUPCL 0002000 /* Hang up on last close. */ 164#define HUPCL 0002000 /* Hang up on last close. */
165#define CLOCAL 0004000 /* Ignore modem status lines. */ 165#define CLOCAL 0004000 /* Ignore modem status lines. */
166#define CBAUDEX 0010000 166#define CBAUDEX 0010000
167#define BOTHER 0010000
167#define B57600 0010001 168#define B57600 0010001
168#define B115200 0010002 169#define B115200 0010002
169#define B230400 0010003 170#define B230400 0010003
@@ -179,9 +180,11 @@ struct ktermios {
179#define B3000000 0010015 180#define B3000000 0010015
180#define B3500000 0010016 181#define B3500000 0010016
181#define B4000000 0010017 182#define B4000000 0010017
182#define CIBAUD 002003600000 /* input baud rate (not used) */ 183#define CIBAUD 002003600000 /* input baud rate */
183#define CMSPAR 010000000000 /* mark or space (stick) parity */ 184#define CMSPAR 010000000000 /* mark or space (stick) parity */
184#define CRTSCTS 020000000000 /* flow control */ 185#define CRTSCTS 020000000000 /* flow control */
186
187#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
185 188
186/* c_lflag bits */ 189/* c_lflag bits */
187#define ISIG 0000001 /* Enable signals. */ 190#define ISIG 0000001 /* Enable signals. */
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h
index 2ce07f4be369..a275661fa7e1 100644
--- a/include/asm-mips/termios.h
+++ b/include/asm-mips/termios.h
@@ -122,8 +122,10 @@ struct termio {
122 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ 122 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
123}) 123})
124 124
125#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) 125#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
126#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) 126#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
127#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
128#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
127 129
128#endif /* defined(__KERNEL__) */ 130#endif /* defined(__KERNEL__) */
129 131
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
50 50
51 51
52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
53#define RBTX4927_RTL_8019_IRQ (29) 53#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
54 54
55int toshiba_rbtx4927_irq_nested(int sw_irq); 55int toshiba_rbtx4927_irq_nested(int sw_irq);
56 56
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
28#define __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H
29 29
30#include <asm/tx4927/tx4927_mips.h> 30#include <asm/tx4927/tx4927_mips.h>
31#include <asm/txx9irq.h>
31 32
32/* 33/*
33 This register naming came from the integrated CPU/controller name TX4927 34 This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
421#define TX4927_PIO_LIMIT 0xf50f 422#define TX4927_PIO_LIMIT 0xf50f
422 423
423 424
424/* TX4927 Interrupt Controller (32-bit registers) */
425#define TX4927_IRC_BASE 0xf510
426#define TX4927_IRC_IRFLAG0 0xf510
427#define TX4927_IRC_IRFLAG1 0xf514
428#define TX4927_IRC_IRPOL 0xf518
429#define TX4927_IRC_IRRCNT 0xf51c
430#define TX4927_IRC_IRMASKINT 0xf520
431#define TX4927_IRC_IRMASKEXT 0xf524
432#define TX4927_IRC_IRDEN 0xf600
433#define TX4927_IRC_IRDM0 0xf604
434#define TX4927_IRC_IRDM1 0xf608
435#define TX4927_IRC_IRLVL0 0xf610
436#define TX4927_IRC_IRLVL1 0xf614
437#define TX4927_IRC_IRLVL2 0xf618
438#define TX4927_IRC_IRLVL3 0xf61c
439#define TX4927_IRC_IRLVL4 0xf620
440#define TX4927_IRC_IRLVL5 0xf624
441#define TX4927_IRC_IRLVL6 0xf628
442#define TX4927_IRC_IRLVL7 0xf62c
443#define TX4927_IRC_IRMSK 0xf640
444#define TX4927_IRC_IREDC 0xf660
445#define TX4927_IRC_IRPND 0xf680
446#define TX4927_IRC_IRCS 0xf6a0
447#define TX4927_IRC_LIMIT 0xf6ff
448
449
450/* TX4927 AC-link controller (32-bit registers) */ 425/* TX4927 AC-link controller (32-bit registers) */
451#define TX4927_ACLC_BASE 0xf700 426#define TX4927_ACLC_BASE 0xf700
452#define TX4927_ACLC_ACCTLEN 0xf700 427#define TX4927_ACLC_ACCTLEN 0xf700
@@ -493,25 +468,11 @@
493#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) 468#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
494 469
495 470
471#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
472#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
496 473
497 474#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
498 475#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
499#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
500#define MI8259_IRQ_ISA_RAW_END 15
501#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */
502#define TX4927_IRQ_CP0_RAW_END 7
503#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */
504#define TX4927_IRQ_PIC_RAW_END 31
505
506
507#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
508#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
509
510#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */
511#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */
512
513#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */
514#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */
515 476
516 477
517#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 478#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
48#define TX4927_PCI_CLK_ACK 0x04 48#define TX4927_PCI_CLK_ACK 0x04
49#define TX4927_PCI_CLK_ACE 0x02 49#define TX4927_PCI_CLK_ACE 0x02
50#define TX4927_PCI_CLK_ENDIAN 0x01 50#define TX4927_PCI_CLK_ENDIAN 0x01
51#define TX4927_NR_IRQ_LOCAL (8+16) 51#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ 52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
53 53
54#define TX4927_IR_PCIC 16 54#define TX4927_IR_PCIC 16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
99 volatile unsigned long long ramp; 99 volatile unsigned long long ramp;
100}; 100};
101 101
102struct tx4927_irc_reg {
103 volatile unsigned long cer;
104 volatile unsigned long cr[2];
105 volatile unsigned long unused0;
106 volatile unsigned long ilr[8];
107 volatile unsigned long unused1[4];
108 volatile unsigned long imr;
109 volatile unsigned long unused2[7];
110 volatile unsigned long scr;
111 volatile unsigned long unused3[7];
112 volatile unsigned long ssr;
113 volatile unsigned long unused4[7];
114 volatile unsigned long csr;
115};
116
117struct tx4927_pcic_reg { 102struct tx4927_pcic_reg {
118 volatile unsigned long pciid; 103 volatile unsigned long pciid;
119 volatile unsigned long pcistatus; 104 volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
182 167
183#endif /* _LANGUAGE_ASSEMBLY */ 168#endif /* _LANGUAGE_ASSEMBLY */
184 169
185/* IRCSR : Int. Current Status */
186#define TX4927_IRCSR_IF 0x00010000
187#define TX4927_IRCSR_ILV_MASK 0x00000700
188#define TX4927_IRCSR_IVL_MASK 0x0000001f
189
190/* 170/*
191 * PCIC 171 * PCIC
192 */ 172 */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
278#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) 258#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
279#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) 259#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
280#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 260#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
281#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG)
282 261
283#endif /* _LANGUAGE_ASSEMBLY */ 262#endif /* _LANGUAGE_ASSEMBLY */
284 263
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e58..b14acb575be2 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
14 14
15#include <asm/addrspace.h> 15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h> 16#include <asm/tx4938/tx4938.h>
17#include <asm/txx9irq.h>
17 18
18/* CS */ 19/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */ 20#define RBTX4938_CE0 0x1c000000 /* 64M */
@@ -123,21 +124,11 @@
123#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ 124#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
124#define RBTX4938_NR_IRQ_IOC 8 125#define RBTX4938_NR_IRQ_IOC 8
125 126
126#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ 127#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
127#define MI8259_IRQ_ISA_RAW_END 15 128#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
128#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
129#define TX4938_IRQ_CP0_RAW_END 7
130#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
131#define TX4938_IRQ_PIC_RAW_END 31
132 129
133#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ 130#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
134#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ 131#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
135
136#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
137#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
138
139#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
140#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
141#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) 132#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
142#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) 133#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
143#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) 134#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
192#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) 183#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
193#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) 184#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
194 185
195/* IRCR : Int. Control */
196#define TX4938_IRCR_LOW 0x00000000
197#define TX4938_IRCR_HIGH 0x00000001
198#define TX4938_IRCR_DOWN 0x00000002
199#define TX4938_IRCR_UP 0x00000003
200
201#endif /* __ASM_TX_BOARDS_RBTX4938_H */ 186#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975cb..afdb19813ca1 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
272 volatile unsigned long maskcpu; 272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext; 273 volatile unsigned long maskext;
274}; 274};
275struct tx4938_irc_reg {
276 volatile unsigned long cer;
277 volatile unsigned long cr[2];
278 volatile unsigned long unused0;
279 volatile unsigned long ilr[8];
280 volatile unsigned long unused1[4];
281 volatile unsigned long imr;
282 volatile unsigned long unused2[7];
283 volatile unsigned long scr;
284 volatile unsigned long unused3[7];
285 volatile unsigned long ssr;
286 volatile unsigned long unused4[7];
287 volatile unsigned long csr;
288};
289 275
290struct tx4938_ndfmc_reg { 276struct tx4938_ndfmc_reg {
291 endian_def_l2(unused0, dtr); 277 endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
646#define TX4938_DMA_CSR_DESERR 0x00000002 632#define TX4938_DMA_CSR_DESERR 0x00000002
647#define TX4938_DMA_CSR_SORERR 0x00000001 633#define TX4938_DMA_CSR_SORERR 0x00000001
648 634
649/* TX4938 Interrupt Controller (32-bit registers) */
650#define TX4938_IRC_BASE 0xf510
651#define TX4938_IRC_IRFLAG0 0xf510
652#define TX4938_IRC_IRFLAG1 0xf514
653#define TX4938_IRC_IRPOL 0xf518
654#define TX4938_IRC_IRRCNT 0xf51c
655#define TX4938_IRC_IRMASKINT 0xf520
656#define TX4938_IRC_IRMASKEXT 0xf524
657#define TX4938_IRC_IRDEN 0xf600
658#define TX4938_IRC_IRDM0 0xf604
659#define TX4938_IRC_IRDM1 0xf608
660#define TX4938_IRC_IRLVL0 0xf610
661#define TX4938_IRC_IRLVL1 0xf614
662#define TX4938_IRC_IRLVL2 0xf618
663#define TX4938_IRC_IRLVL3 0xf61c
664#define TX4938_IRC_IRLVL4 0xf620
665#define TX4938_IRC_IRLVL5 0xf624
666#define TX4938_IRC_IRLVL6 0xf628
667#define TX4938_IRC_IRLVL7 0xf62c
668#define TX4938_IRC_IRMSK 0xf640
669#define TX4938_IRC_IREDC 0xf660
670#define TX4938_IRC_IRPND 0xf680
671#define TX4938_IRC_IRCS 0xf6a0
672#define TX4938_IRC_LIMIT 0xf6ff
673
674
675#ifndef __ASSEMBLY__ 635#ifndef __ASSEMBLY__
676 636
677#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 637#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
678#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 638#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
679#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) 639#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
680#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) 640#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
681#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG)
682#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
683#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
684#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
new file mode 100644
index 000000000000..1c439e51b875
--- /dev/null
+++ b/include/asm-mips/txx9irq.h
@@ -0,0 +1,30 @@
1/*
2 * include/asm-mips/txx9irq.h
3 * TX39/TX49 interrupt controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9IRQ_H
10#define __ASM_TXX9IRQ_H
11
12#include <irq.h>
13
14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else
17#define TXX9_IRQ_BASE 0
18#endif
19
20#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16
22#else
23#define TXx9_MAX_IR 32
24#endif
25
26void txx9_irq_init(unsigned long baseaddr);
27int txx9_irq(void);
28int txx9_irq_set_pri(int irc_irq, int new_pri);
29
30#endif /* __ASM_TXX9IRQ_H */
diff --git a/include/asm-parisc/io.h b/include/asm-parisc/io.h
index c0fed91da3a2..4cc9bcec0564 100644
--- a/include/asm-parisc/io.h
+++ b/include/asm-parisc/io.h
@@ -15,6 +15,16 @@ extern unsigned long parisc_vmerge_max_size;
15#define virt_to_bus virt_to_phys 15#define virt_to_bus virt_to_phys
16#define bus_to_virt phys_to_virt 16#define bus_to_virt phys_to_virt
17 17
18static inline unsigned long isa_bus_to_virt(unsigned long addr) {
19 BUG();
20 return 0;
21}
22
23static inline unsigned long isa_virt_to_bus(void *addr) {
24 BUG();
25 return 0;
26}
27
18/* 28/*
19 * Memory mapped I/O 29 * Memory mapped I/O
20 * 30 *
diff --git a/include/asm-parisc/vga.h b/include/asm-parisc/vga.h
new file mode 100644
index 000000000000..154a84c843a7
--- /dev/null
+++ b/include/asm-parisc/vga.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_PARISC_VGA_H__
2#define __ASM_PARISC_VGA_H__
3
4/* nothing */
5
6#endif __ASM_PARISC_VGA_H__
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 8836c0f1f2f7..5bde3980bf49 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -130,6 +130,7 @@ struct spu {
130 u64 flags; 130 u64 flags;
131 u64 dar; 131 u64 dar;
132 u64 dsisr; 132 u64 dsisr;
133 u64 class_0_pending;
133 size_t ls_size; 134 size_t ls_size;
134 unsigned int slb_replace; 135 unsigned int slb_replace;
135 struct mm_struct *mm; 136 struct mm_struct *mm;
@@ -138,7 +139,6 @@ struct spu {
138 unsigned long long timestamp; 139 unsigned long long timestamp;
139 pid_t pid; 140 pid_t pid;
140 pid_t tgid; 141 pid_t tgid;
141 int class_0_pending;
142 spinlock_t register_lock; 142 spinlock_t register_lock;
143 143
144 void (* wbox_callback)(struct spu *spu); 144 void (* wbox_callback)(struct spu *spu);
diff --git a/include/asm-sparc/tlbflush.h b/include/asm-sparc/tlbflush.h
index 4a3b66618e75..a619da5cfaa9 100644
--- a/include/asm-sparc/tlbflush.h
+++ b/include/asm-sparc/tlbflush.h
@@ -57,6 +57,10 @@ BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
57/* 57/*
58 * This is a kludge, until I know better. --zaitcev XXX 58 * This is a kludge, until I know better. --zaitcev XXX
59 */ 59 */
60#define flush_tlb_kernel_range(start, end) flush_tlb_all() 60static inline void flush_tlb_kernel_range(unsigned long start,
61 unsigned long end)
62{
63 flush_tlb_all();
64}
61 65
62#endif /* _SPARC_TLBFLUSH_H */ 66#endif /* _SPARC_TLBFLUSH_H */
diff --git a/include/asm-sparc64/device.h b/include/asm-sparc64/device.h
index d5a4559b9555..5111e8717be3 100644
--- a/include/asm-sparc64/device.h
+++ b/include/asm-sparc64/device.h
@@ -16,8 +16,6 @@ struct dev_archdata {
16 16
17 struct device_node *prom_node; 17 struct device_node *prom_node;
18 struct of_device *op; 18 struct of_device *op;
19
20 unsigned int msi_num;
21}; 19};
22 20
23#endif /* _ASM_SPARC64_DEVICE_H */ 21#endif /* _ASM_SPARC64_DEVICE_H */
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index e6c436ef9356..c00ad152771b 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -16,21 +16,21 @@
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17 17
18/* IMAP/ICLR register defines */ 18/* IMAP/ICLR register defines */
19#define IMAP_VALID 0x80000000 /* IRQ Enabled */ 19#define IMAP_VALID 0x80000000UL /* IRQ Enabled */
20#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ 20#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */
21#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */ 21#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */
22#define IMAP_TID_SHIFT 26 22#define IMAP_TID_SHIFT 26
23#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */ 23#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */
24#define IMAP_AID_SHIFT 26 24#define IMAP_AID_SHIFT 26
25#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */ 25#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */
26#define IMAP_NID_SHIFT 21 26#define IMAP_NID_SHIFT 21
27#define IMAP_IGN 0x000007c0 /* IRQ Group Number */ 27#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */
28#define IMAP_INO 0x0000003f /* IRQ Number */ 28#define IMAP_INO 0x0000003fUL /* IRQ Number */
29#define IMAP_INR 0x000007ff /* Full interrupt number*/ 29#define IMAP_INR 0x000007ffUL /* Full interrupt number*/
30 30
31#define ICLR_IDLE 0x00000000 /* Idle state */ 31#define ICLR_IDLE 0x00000000UL /* Idle state */
32#define ICLR_TRANSMIT 0x00000001 /* Transmit state */ 32#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */
33#define ICLR_PENDING 0x00000003 /* Pending state */ 33#define ICLR_PENDING 0x00000003UL /* Pending state */
34 34
35/* The largest number of unique interrupt sources we support. 35/* The largest number of unique interrupt sources we support.
36 * If this needs to ever be larger than 255, you need to change 36 * If this needs to ever be larger than 255, you need to change
@@ -53,6 +53,9 @@ extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
53extern void sun4v_destroy_msi(unsigned int virt_irq); 53extern void sun4v_destroy_msi(unsigned int virt_irq);
54extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); 54extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
55 55
56extern void sparc64_set_msi(unsigned int virt_irq, u32 msi);
57extern u32 sparc64_get_msi(unsigned int virt_irq);
58
56extern void fixup_irqs(void); 59extern void fixup_irqs(void);
57 60
58static __inline__ void set_softint(unsigned long bits) 61static __inline__ void set_softint(unsigned long bits)
diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S
index e3f010bd12b3..cb0248616d49 100644
--- a/include/asm-um/common.lds.S
+++ b/include/asm-um/common.lds.S
@@ -16,82 +16,112 @@
16 16
17 . = ALIGN(4096); 17 . = ALIGN(4096);
18 .note : { *(.note.*) } 18 .note : { *(.note.*) }
19 __start___ex_table = .; 19 __ex_table : {
20 __ex_table : { *(__ex_table) } 20 __start___ex_table = .;
21 __stop___ex_table = .; 21 *(__ex_table)
22 __stop___ex_table = .;
23 }
22 24
23 BUG_TABLE 25 BUG_TABLE
24 26
25 __uml_setup_start = .; 27 .uml.setup.init : {
26 .uml.setup.init : { *(.uml.setup.init) } 28 __uml_setup_start = .;
27 __uml_setup_end = .; 29 *(.uml.setup.init)
30 __uml_setup_end = .;
31 }
28 32
29 __uml_help_start = .; 33 .uml.help.init : {
30 .uml.help.init : { *(.uml.help.init) } 34 __uml_help_start = .;
31 __uml_help_end = .; 35 *(.uml.help.init)
36 __uml_help_end = .;
37 }
32 38
33 __uml_postsetup_start = .; 39 .uml.postsetup.init : {
34 .uml.postsetup.init : { *(.uml.postsetup.init) } 40 __uml_postsetup_start = .;
35 __uml_postsetup_end = .; 41 *(.uml.postsetup.init)
42 __uml_postsetup_end = .;
43 }
36 44
37 __setup_start = .; 45 .init.setup : {
38 .init.setup : { *(.init.setup) } 46 __setup_start = .;
39 __setup_end = .; 47 *(.init.setup)
48 __setup_end = .;
49 }
40 50
41 . = ALIGN(32); 51 . = ALIGN(32);
42 __per_cpu_start = . ; 52 .data.percpu : {
43 .data.percpu : { *(.data.percpu) } 53 __per_cpu_start = . ;
44 __per_cpu_end = . ; 54 *(.data.percpu)
55 __per_cpu_end = . ;
56 }
45 57
46 __initcall_start = .;
47 .initcall.init : { 58 .initcall.init : {
59 __initcall_start = .;
48 INITCALLS 60 INITCALLS
61 __initcall_end = .;
49 } 62 }
50 __initcall_end = .;
51 63
52 __con_initcall_start = .; 64 .con_initcall.init : {
53 .con_initcall.init : { *(.con_initcall.init) } 65 __con_initcall_start = .;
54 __con_initcall_end = .; 66 *(.con_initcall.init)
67 __con_initcall_end = .;
68 }
55 69
56 __uml_initcall_start = .; 70 .uml.initcall.init : {
57 .uml.initcall.init : { *(.uml.initcall.init) } 71 __uml_initcall_start = .;
58 __uml_initcall_end = .; 72 *(.uml.initcall.init)
73 __uml_initcall_end = .;
74 }
59 __init_end = .; 75 __init_end = .;
60 76
61 SECURITY_INIT 77 SECURITY_INIT
62 78
63 __exitcall_begin = .; 79 .exitcall : {
64 .exitcall : { *(.exitcall.exit) } 80 __exitcall_begin = .;
65 __exitcall_end = .; 81 *(.exitcall.exit)
82 __exitcall_end = .;
83 }
66 84
67 __uml_exitcall_begin = .; 85 .uml.exitcall : {
68 .uml.exitcall : { *(.uml.exitcall.exit) } 86 __uml_exitcall_begin = .;
69 __uml_exitcall_end = .; 87 *(.uml.exitcall.exit)
88 __uml_exitcall_end = .;
89 }
70 90
71 . = ALIGN(4); 91 . = ALIGN(4);
72 __alt_instructions = .; 92 .altinstructions : {
73 .altinstructions : { *(.altinstructions) } 93 __alt_instructions = .;
74 __alt_instructions_end = .; 94 *(.altinstructions)
95 __alt_instructions_end = .;
96 }
75 .altinstr_replacement : { *(.altinstr_replacement) } 97 .altinstr_replacement : { *(.altinstr_replacement) }
76 /* .exit.text is discard at runtime, not link time, to deal with references 98 /* .exit.text is discard at runtime, not link time, to deal with references
77 from .altinstructions and .eh_frame */ 99 from .altinstructions and .eh_frame */
78 .exit.text : { *(.exit.text) } 100 .exit.text : { *(.exit.text) }
79 .exit.data : { *(.exit.data) } 101 .exit.data : { *(.exit.data) }
80 102
81 __preinit_array_start = .; 103 .preinit_array : {
82 .preinit_array : { *(.preinit_array) } 104 __preinit_array_start = .;
83 __preinit_array_end = .; 105 *(.preinit_array)
84 __init_array_start = .; 106 __preinit_array_end = .;
85 .init_array : { *(.init_array) } 107 }
86 __init_array_end = .; 108 .init_array : {
87 __fini_array_start = .; 109 __init_array_start = .;
88 .fini_array : { *(.fini_array) } 110 *(.init_array)
89 __fini_array_end = .; 111 __init_array_end = .;
112 }
113 .fini_array : {
114 __fini_array_start = .;
115 *(.fini_array)
116 __fini_array_end = .;
117 }
90 118
91 . = ALIGN(4096); 119 . = ALIGN(4096);
92 __initramfs_start = .; 120 .init.ramfs : {
93 .init.ramfs : { *(.init.ramfs) } 121 __initramfs_start = .;
94 __initramfs_end = .; 122 *(.init.ramfs)
123 __initramfs_end = .;
124 }
95 125
96 /* Sections to be discarded */ 126 /* Sections to be discarded */
97 /DISCARD/ : { 127 /DISCARD/ : {
diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h
index 8a8246d03936..857471c49dac 100644
--- a/include/asm-um/elf-x86_64.h
+++ b/include/asm-um/elf-x86_64.h
@@ -6,7 +6,9 @@
6#ifndef __UM_ELF_X86_64_H 6#ifndef __UM_ELF_X86_64_H
7#define __UM_ELF_X86_64_H 7#define __UM_ELF_X86_64_H
8 8
9#include <linux/sched.h>
9#include <asm/user.h> 10#include <asm/user.h>
11#include "skas.h"
10 12
11/* x86-64 relocation types, taken from asm-x86_64/elf.h */ 13/* x86-64 relocation types, taken from asm-x86_64/elf.h */
12#define R_X86_64_NONE 0 /* No reloc */ 14#define R_X86_64_NONE 0 /* No reloc */
@@ -64,6 +66,44 @@ typedef struct { } elf_fpregset_t;
64 PT_REGS_R15(regs) = 0; \ 66 PT_REGS_R15(regs) = 0; \
65} while (0) 67} while (0)
66 68
69#define ELF_CORE_COPY_REGS(pr_reg, regs) \
70 (pr_reg)[0] = (regs)->regs.skas.regs[0]; \
71 (pr_reg)[1] = (regs)->regs.skas.regs[1]; \
72 (pr_reg)[2] = (regs)->regs.skas.regs[2]; \
73 (pr_reg)[3] = (regs)->regs.skas.regs[3]; \
74 (pr_reg)[4] = (regs)->regs.skas.regs[4]; \
75 (pr_reg)[5] = (regs)->regs.skas.regs[5]; \
76 (pr_reg)[6] = (regs)->regs.skas.regs[6]; \
77 (pr_reg)[7] = (regs)->regs.skas.regs[7]; \
78 (pr_reg)[8] = (regs)->regs.skas.regs[8]; \
79 (pr_reg)[9] = (regs)->regs.skas.regs[9]; \
80 (pr_reg)[10] = (regs)->regs.skas.regs[10]; \
81 (pr_reg)[11] = (regs)->regs.skas.regs[11]; \
82 (pr_reg)[12] = (regs)->regs.skas.regs[12]; \
83 (pr_reg)[13] = (regs)->regs.skas.regs[13]; \
84 (pr_reg)[14] = (regs)->regs.skas.regs[14]; \
85 (pr_reg)[15] = (regs)->regs.skas.regs[15]; \
86 (pr_reg)[16] = (regs)->regs.skas.regs[16]; \
87 (pr_reg)[17] = (regs)->regs.skas.regs[17]; \
88 (pr_reg)[18] = (regs)->regs.skas.regs[18]; \
89 (pr_reg)[19] = (regs)->regs.skas.regs[19]; \
90 (pr_reg)[20] = (regs)->regs.skas.regs[20]; \
91 (pr_reg)[21] = current->thread.arch.fs; \
92 (pr_reg)[22] = 0; \
93 (pr_reg)[23] = 0; \
94 (pr_reg)[24] = 0; \
95 (pr_reg)[25] = 0; \
96 (pr_reg)[26] = 0;
97
98static inline int elf_core_copy_fpregs(struct task_struct *t,
99 elf_fpregset_t *fpu)
100{
101 int cpu = current_thread->cpu;
102 return save_fp_registers(userspace_pid[cpu], (unsigned long *) fpu);
103}
104
105#define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu)
106
67#ifdef TIF_IA32 /* XXX */ 107#ifdef TIF_IA32 /* XXX */
68#error XXX, indeed 108#error XXX, indeed
69 clear_thread_flag(TIF_IA32); 109 clear_thread_flag(TIF_IA32);
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index ad7f71a81b0a..818cc3a50e6b 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -7,6 +7,7 @@ header-y += raid/
7header-y += spi/ 7header-y += spi/
8header-y += sunrpc/ 8header-y += sunrpc/
9header-y += tc_act/ 9header-y += tc_act/
10header-y += tc_ematch/
10header-y += netfilter/ 11header-y += netfilter/
11header-y += netfilter_arp/ 12header-y += netfilter_arp/
12header-y += netfilter_bridge/ 13header-y += netfilter_bridge/
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 509656286e53..bcf236d825e8 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -15,11 +15,26 @@ extern int pci_disable_pcie_error_reporting(struct pci_dev *dev);
15extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); 15extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
16extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev); 16extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev);
17#else 17#else
18#define pci_enable_pcie_error_reporting(dev) (-EINVAL) 18static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
19#define pci_find_aer_capability(dev) (0) 19{
20#define pci_disable_pcie_error_reporting(dev) (-EINVAL) 20 return -EINVAL;
21#define pci_cleanup_aer_uncorrect_error_status(dev) (-EINVAL) 21}
22#define pci_cleanup_aer_correct_error_status(dev) (-EINVAL) 22static inline int pci_find_aer_capability(struct pci_dev *dev)
23{
24 return 0;
25}
26static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev)
27{
28 return -EINVAL;
29}
30static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
31{
32 return -EINVAL;
33}
34static inline int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
35{
36 return -EINVAL;
37}
23#endif 38#endif
24 39
25#endif //_AER_H_ 40#endif //_AER_H_
diff --git a/include/linux/ata.h b/include/linux/ata.h
index 23a22df039d8..c043c1ccf1c5 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -73,6 +73,19 @@ enum {
73 ATA_PIO5 = ATA_PIO4 | (1 << 5), 73 ATA_PIO5 = ATA_PIO4 | (1 << 5),
74 ATA_PIO6 = ATA_PIO5 | (1 << 6), 74 ATA_PIO6 = ATA_PIO5 | (1 << 6),
75 75
76 ATA_SWDMA0 = (1 << 0),
77 ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1),
78 ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2),
79
80 ATA_SWDMA2_ONLY = (1 << 2),
81
82 ATA_MWDMA0 = (1 << 0),
83 ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1),
84 ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2),
85
86 ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2),
87 ATA_MWDMA2_ONLY = (1 << 2),
88
76 ATA_UDMA0 = (1 << 0), 89 ATA_UDMA0 = (1 << 0),
77 ATA_UDMA1 = ATA_UDMA0 | (1 << 1), 90 ATA_UDMA1 = ATA_UDMA0 | (1 << 1),
78 ATA_UDMA2 = ATA_UDMA1 | (1 << 2), 91 ATA_UDMA2 = ATA_UDMA1 | (1 << 2),
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 1d5ded0836ee..0ad72c4cf312 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -126,16 +126,16 @@ static inline void cpuhotplug_mutex_unlock(struct mutex *cpu_hp_mutex)
126static inline int cpu_is_offline(int cpu) { return 0; } 126static inline int cpu_is_offline(int cpu) { return 0; }
127#endif /* CONFIG_HOTPLUG_CPU */ 127#endif /* CONFIG_HOTPLUG_CPU */
128 128
129#ifdef CONFIG_SUSPEND_SMP 129#ifdef CONFIG_PM_SLEEP_SMP
130extern int suspend_cpu_hotplug; 130extern int suspend_cpu_hotplug;
131 131
132extern int disable_nonboot_cpus(void); 132extern int disable_nonboot_cpus(void);
133extern void enable_nonboot_cpus(void); 133extern void enable_nonboot_cpus(void);
134#else 134#else /* !CONFIG_PM_SLEEP_SMP */
135#define suspend_cpu_hotplug 0 135#define suspend_cpu_hotplug 0
136 136
137static inline int disable_nonboot_cpus(void) { return 0; } 137static inline int disable_nonboot_cpus(void) { return 0; }
138static inline void enable_nonboot_cpus(void) {} 138static inline void enable_nonboot_cpus(void) {}
139#endif 139#endif /* !CONFIG_PM_SLEEP_SMP */
140 140
141#endif /* _LINUX_CPU_H_ */ 141#endif /* _LINUX_CPU_H_ */
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index e6a71c82d204..3a19b032c0eb 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -66,11 +66,8 @@ void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
66 * If the arch doesn't supply something else, assume that hugepage 66 * If the arch doesn't supply something else, assume that hugepage
67 * size aligned regions are ok without further preparation. 67 * size aligned regions are ok without further preparation.
68 */ 68 */
69static inline int prepare_hugepage_range(unsigned long addr, unsigned long len, 69static inline int prepare_hugepage_range(unsigned long addr, unsigned long len)
70 pgoff_t pgoff)
71{ 70{
72 if (pgoff & (~HPAGE_MASK >> PAGE_SHIFT))
73 return -EINVAL;
74 if (len & ~HPAGE_MASK) 71 if (len & ~HPAGE_MASK)
75 return -EINVAL; 72 return -EINVAL;
76 if (addr & ~HPAGE_MASK) 73 if (addr & ~HPAGE_MASK)
@@ -78,8 +75,7 @@ static inline int prepare_hugepage_range(unsigned long addr, unsigned long len,
78 return 0; 75 return 0;
79} 76}
80#else 77#else
81int prepare_hugepage_range(unsigned long addr, unsigned long len, 78int prepare_hugepage_range(unsigned long addr, unsigned long len);
82 pgoff_t pgoff);
83#endif 79#endif
84 80
85#ifndef ARCH_HAS_SETCLEAR_HUGE_PTE 81#ifndef ARCH_HAS_SETCLEAR_HUGE_PTE
@@ -117,7 +113,7 @@ static inline unsigned long hugetlb_total_pages(void)
117#define hugetlb_report_meminfo(buf) 0 113#define hugetlb_report_meminfo(buf) 0
118#define hugetlb_report_node_meminfo(n, buf) 0 114#define hugetlb_report_node_meminfo(n, buf) 0
119#define follow_huge_pmd(mm, addr, pmd, write) NULL 115#define follow_huge_pmd(mm, addr, pmd, write) NULL
120#define prepare_hugepage_range(addr,len,pgoff) (-EINVAL) 116#define prepare_hugepage_range(addr,len) (-EINVAL)
121#define pmd_huge(x) 0 117#define pmd_huge(x) 0
122#define is_hugepage_only_range(mm, addr, len) 0 118#define is_hugepage_only_range(mm, addr, len) 0
123#define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) ({BUG(); 0; }) 119#define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) ({BUG(); 0; })
diff --git a/include/linux/ide.h b/include/linux/ide.h
index c792b4fd1588..b9f66c10caa0 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -1378,6 +1378,19 @@ static inline int ide_dev_has_iordy(struct hd_driveid *id)
1378 return ((id->field_valid & 2) && (id->capability & 8)) ? 1 : 0; 1378 return ((id->field_valid & 2) && (id->capability & 8)) ? 1 : 0;
1379} 1379}
1380 1380
1381static inline int ide_dev_is_sata(struct hd_driveid *id)
1382{
1383 /*
1384 * See if word 93 is 0 AND drive is at least ATA-5 compatible
1385 * verifying that word 80 by casting it to a signed type --
1386 * this trick allows us to filter out the reserved values of
1387 * 0x0000 and 0xffff along with the earlier ATA revisions...
1388 */
1389 if (id->hw_config == 0 && (short)id->major_rev_num >= 0x0020)
1390 return 1;
1391 return 0;
1392}
1393
1381u8 ide_dump_status(ide_drive_t *, const char *, u8); 1394u8 ide_dump_status(ide_drive_t *, const char *, u8);
1382 1395
1383typedef struct ide_pio_timings_s { 1396typedef struct ide_pio_timings_s {
diff --git a/include/linux/if_pppol2tp.h b/include/linux/if_pppol2tp.h
index 516203b6fdeb..a7d6a2234b31 100644
--- a/include/linux/if_pppol2tp.h
+++ b/include/linux/if_pppol2tp.h
@@ -32,8 +32,8 @@ struct pppol2tp_addr
32 32
33 struct sockaddr_in addr; /* IP address and port to send to */ 33 struct sockaddr_in addr; /* IP address and port to send to */
34 34
35 __be16 s_tunnel, s_session; /* For matching incoming packets */ 35 __u16 s_tunnel, s_session; /* For matching incoming packets */
36 __be16 d_tunnel, d_session; /* For sending outgoing packets */ 36 __u16 d_tunnel, d_session; /* For sending outgoing packets */
37}; 37};
38 38
39/* Socket options: 39/* Socket options:
diff --git a/include/linux/input.h b/include/linux/input.h
index cf2b5619aa13..36e00aa6f03b 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -558,6 +558,8 @@ struct input_absinfo {
558#define KEY_BRL_DOT6 0x1f6 558#define KEY_BRL_DOT6 0x1f6
559#define KEY_BRL_DOT7 0x1f7 559#define KEY_BRL_DOT7 0x1f7
560#define KEY_BRL_DOT8 0x1f8 560#define KEY_BRL_DOT8 0x1f8
561#define KEY_BRL_DOT9 0x1f9
562#define KEY_BRL_DOT10 0x1fa
561 563
562/* We avoid low common keys in module aliases so they don't get huge. */ 564/* We avoid low common keys in module aliases so they don't get huge. */
563#define KEY_MIN_INTERESTING KEY_MUTE 565#define KEY_MIN_INTERESTING KEY_MUTE
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index f592df74b3cf..47160fe378c9 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -34,6 +34,7 @@ extern const char linux_proc_banner[];
34 34
35#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) 35#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
36#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 36#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
37#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
37 38
38#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) 39#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
39 40
diff --git a/include/linux/keyboard.h b/include/linux/keyboard.h
index de76843bbe8a..7ddbc30aa8e7 100644
--- a/include/linux/keyboard.h
+++ b/include/linux/keyboard.h
@@ -437,8 +437,10 @@ extern unsigned short plain_map[NR_KEYS];
437#define K_BRL_DOT6 K(KT_BRL, 6) 437#define K_BRL_DOT6 K(KT_BRL, 6)
438#define K_BRL_DOT7 K(KT_BRL, 7) 438#define K_BRL_DOT7 K(KT_BRL, 7)
439#define K_BRL_DOT8 K(KT_BRL, 8) 439#define K_BRL_DOT8 K(KT_BRL, 8)
440#define K_BRL_DOT9 K(KT_BRL, 9)
441#define K_BRL_DOT10 K(KT_BRL, 10)
440 442
441#define NR_BRL 9 443#define NR_BRL 11
442 444
443#define MAX_DIACR 256 445#define MAX_DIACR 256
444#endif 446#endif
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 421175092ee2..dc1178f6184b 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -13,6 +13,7 @@
13#define __LINUX_LEDS_H_INCLUDED 13#define __LINUX_LEDS_H_INCLUDED
14 14
15#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/spinlock.h>
16 17
17struct device; 18struct device;
18/* 19/*
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 41978a557318..a67bb9075e9b 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -303,6 +303,7 @@ enum {
303 ATA_HORKAGE_NODMA = (1 << 1), /* DMA problems */ 303 ATA_HORKAGE_NODMA = (1 << 1), /* DMA problems */
304 ATA_HORKAGE_NONCQ = (1 << 2), /* Don't use NCQ */ 304 ATA_HORKAGE_NONCQ = (1 << 2), /* Don't use NCQ */
305 ATA_HORKAGE_MAX_SEC_128 = (1 << 3), /* Limit max sects to 128 */ 305 ATA_HORKAGE_MAX_SEC_128 = (1 << 3), /* Limit max sects to 128 */
306 ATA_HORKAGE_BROKEN_HPA = (1 << 4), /* Broken HPA */
306}; 307};
307 308
308enum hsm_task_states { 309enum hsm_task_states {
diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h
index 0eed0b7ab2df..1dd075eda595 100644
--- a/include/linux/netfilter.h
+++ b/include/linux/netfilter.h
@@ -88,9 +88,8 @@ struct nf_sockopt_ops
88 int (*compat_get)(struct sock *sk, int optval, 88 int (*compat_get)(struct sock *sk, int optval,
89 void __user *user, int *len); 89 void __user *user, int *len);
90 90
91 /* Number of users inside set() or get(). */ 91 /* Use the module struct to lock set/get code in place */
92 unsigned int use; 92 struct module *owner;
93 struct task_struct *cleanup_task;
94}; 93};
95 94
96/* Each queued (to userspace) skbuff has one of these. */ 95/* Each queued (to userspace) skbuff has one of these. */
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 157dcb055b5c..7250eeadd7b5 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -431,6 +431,7 @@ extern int nfs_sync_mapping_range(struct address_space *, loff_t, loff_t, int);
431extern int nfs_wb_all(struct inode *inode); 431extern int nfs_wb_all(struct inode *inode);
432extern int nfs_wb_page(struct inode *inode, struct page* page); 432extern int nfs_wb_page(struct inode *inode, struct page* page);
433extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how); 433extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how);
434extern int nfs_wb_page_cancel(struct inode *inode, struct page* page);
434#if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) 435#if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
435extern int nfs_commit_inode(struct inode *, int); 436extern int nfs_commit_inode(struct inode *, int);
436extern struct nfs_write_data *nfs_commit_alloc(void); 437extern struct nfs_write_data *nfs_commit_alloc(void);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 06d23e10a16d..55f307ffbf96 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -374,10 +374,9 @@
374#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 374#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379
375#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a 375#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a
376#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380 376#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380
377#define PCI_DEVICE_ID_ATI_IXP600_SMBUS 0x4385 377#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385
378#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c 378#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c
379#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390 379#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390
380#define PCI_DEVICE_ID_ATI_IXP700_SMBUS 0x4395
381#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c 380#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c
382 381
383#define PCI_VENDOR_ID_VLSI 0x1004 382#define PCI_VENDOR_ID_VLSI 0x1004
@@ -1344,6 +1343,7 @@
1344#define PCI_DEVICE_ID_VIA_8231_4 0x8235 1343#define PCI_DEVICE_ID_VIA_8231_4 0x8235
1345#define PCI_DEVICE_ID_VIA_8365_1 0x8305 1344#define PCI_DEVICE_ID_VIA_8365_1 0x8305
1346#define PCI_DEVICE_ID_VIA_CX700 0x8324 1345#define PCI_DEVICE_ID_VIA_CX700 0x8324
1346#define PCI_DEVICE_ID_VIA_VX800 0x8353
1347#define PCI_DEVICE_ID_VIA_8371_1 0x8391 1347#define PCI_DEVICE_ID_VIA_8371_1 0x8391
1348#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 1348#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
1349#define PCI_DEVICE_ID_VIA_838X_1 0xB188 1349#define PCI_DEVICE_ID_VIA_838X_1 0xB188
@@ -2293,6 +2293,8 @@
2293#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 2293#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599
2294#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a 2294#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a
2295#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e 2295#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e
2296#define PCI_DEVICE_ID_INTEL_TOLAPAI_0 0x5031
2297#define PCI_DEVICE_ID_INTEL_TOLAPAI_1 0x5032
2296#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 2298#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
2297#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 2299#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
2298#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 2300#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
diff --git a/include/linux/pmu.h b/include/linux/pmu.h
index 5ad913ff02b2..b7824c215354 100644
--- a/include/linux/pmu.h
+++ b/include/linux/pmu.h
@@ -226,7 +226,7 @@ extern unsigned int pmu_power_flags;
226extern void pmu_backlight_init(void); 226extern void pmu_backlight_init(void);
227 227
228/* some code needs to know if the PMU was suspended for hibernation */ 228/* some code needs to know if the PMU was suspended for hibernation */
229#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 229#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PPC32)
230extern int pmu_sys_suspended; 230extern int pmu_sys_suspended;
231#else 231#else
232/* if power management is not configured it can't be suspended */ 232/* if power management is not configured it can't be suspended */
diff --git a/include/linux/poll.h b/include/linux/poll.h
index 27690798623f..16d813b364ef 100644
--- a/include/linux/poll.h
+++ b/include/linux/poll.h
@@ -21,6 +21,8 @@
21#define WQUEUES_STACK_ALLOC (MAX_STACK_ALLOC - FRONTEND_STACK_ALLOC) 21#define WQUEUES_STACK_ALLOC (MAX_STACK_ALLOC - FRONTEND_STACK_ALLOC)
22#define N_INLINE_POLL_ENTRIES (WQUEUES_STACK_ALLOC / sizeof(struct poll_table_entry)) 22#define N_INLINE_POLL_ENTRIES (WQUEUES_STACK_ALLOC / sizeof(struct poll_table_entry))
23 23
24#define DEFAULT_POLLMASK (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM)
25
24struct poll_table_struct; 26struct poll_table_struct;
25 27
26/* 28/*
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index c91476ce314a..dff3192374f8 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -351,6 +351,8 @@ enum
351#define RTAX_INITCWND RTAX_INITCWND 351#define RTAX_INITCWND RTAX_INITCWND
352 RTAX_FEATURES, 352 RTAX_FEATURES,
353#define RTAX_FEATURES RTAX_FEATURES 353#define RTAX_FEATURES RTAX_FEATURES
354 RTAX_RTO_MIN,
355#define RTAX_RTO_MIN RTAX_RTO_MIN
354 __RTAX_MAX 356 __RTAX_MAX
355}; 357};
356 358
diff --git a/include/linux/sched.h b/include/linux/sched.h
index bd6a0320a770..f4e324ed2e44 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -904,6 +904,7 @@ struct sched_entity {
904 904
905 u64 exec_start; 905 u64 exec_start;
906 u64 sum_exec_runtime; 906 u64 sum_exec_runtime;
907 u64 prev_sum_exec_runtime;
907 u64 wait_start_fair; 908 u64 wait_start_fair;
908 u64 sleep_start_fair; 909 u64 sleep_start_fair;
909 910
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
index 124270df8734..74962077f632 100644
--- a/include/linux/slub_def.h
+++ b/include/linux/slub_def.h
@@ -78,7 +78,7 @@ extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_HIGH + 1];
78 * Sorry that the following has to be that ugly but some versions of GCC 78 * Sorry that the following has to be that ugly but some versions of GCC
79 * have trouble with constant propagation and loops. 79 * have trouble with constant propagation and loops.
80 */ 80 */
81static inline int kmalloc_index(size_t size) 81static __always_inline int kmalloc_index(size_t size)
82{ 82{
83 if (!size) 83 if (!size)
84 return 0; 84 return 0;
@@ -133,7 +133,7 @@ static inline int kmalloc_index(size_t size)
133 * This ought to end up with a global pointer to the right cache 133 * This ought to end up with a global pointer to the right cache
134 * in kmalloc_caches. 134 * in kmalloc_caches.
135 */ 135 */
136static inline struct kmem_cache *kmalloc_slab(size_t size) 136static __always_inline struct kmem_cache *kmalloc_slab(size_t size)
137{ 137{
138 int index = kmalloc_index(size); 138 int index = kmalloc_index(size);
139 139
@@ -166,7 +166,7 @@ static inline struct kmem_cache *kmalloc_slab(size_t size)
166void *kmem_cache_alloc(struct kmem_cache *, gfp_t); 166void *kmem_cache_alloc(struct kmem_cache *, gfp_t);
167void *__kmalloc(size_t size, gfp_t flags); 167void *__kmalloc(size_t size, gfp_t flags);
168 168
169static inline void *kmalloc(size_t size, gfp_t flags) 169static __always_inline void *kmalloc(size_t size, gfp_t flags)
170{ 170{
171 if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { 171 if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) {
172 struct kmem_cache *s = kmalloc_slab(size); 172 struct kmem_cache *s = kmalloc_slab(size);
@@ -183,7 +183,7 @@ static inline void *kmalloc(size_t size, gfp_t flags)
183void *__kmalloc_node(size_t size, gfp_t flags, int node); 183void *__kmalloc_node(size_t size, gfp_t flags, int node);
184void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node); 184void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node);
185 185
186static inline void *kmalloc_node(size_t size, gfp_t flags, int node) 186static __always_inline void *kmalloc_node(size_t size, gfp_t flags, int node)
187{ 187{
188 if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { 188 if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) {
189 struct kmem_cache *s = kmalloc_slab(size); 189 struct kmem_cache *s = kmalloc_slab(size);
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index d62847f846c2..17f8f3a2f0a3 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -337,6 +337,9 @@ void *priv;
337 struct class_device class_dev; /* sysfs */ 337 struct class_device class_dev; /* sysfs */
338}; 338};
339 339
340/* Class-dev to video-device */
341#define to_video_device(cd) container_of(cd, struct video_device, class_dev)
342
340/* Version 2 functions */ 343/* Version 2 functions */
341extern int video_register_device(struct video_device *vfd, int type, int nr); 344extern int video_register_device(struct video_device *vfd, int type, int nr);
342void video_unregister_device(struct video_device *); 345void video_unregister_device(struct video_device *);
@@ -354,11 +357,9 @@ extern int video_usercopy(struct inode *inode, struct file *file,
354 int (*func)(struct inode *inode, struct file *file, 357 int (*func)(struct inode *inode, struct file *file,
355 unsigned int cmd, void *arg)); 358 unsigned int cmd, void *arg));
356 359
357
358#ifdef CONFIG_VIDEO_V4L1_COMPAT 360#ifdef CONFIG_VIDEO_V4L1_COMPAT
359#include <linux/mm.h> 361#include <linux/mm.h>
360 362
361#define to_video_device(cd) container_of(cd, struct video_device, class_dev)
362static inline int __must_check 363static inline int __must_check
363video_device_create_file(struct video_device *vfd, 364video_device_create_file(struct video_device *vfd,
364 struct class_device_attribute *attr) 365 struct class_device_attribute *attr)
diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h
index 73cb9943c8a8..991c85bb9e36 100644
--- a/include/net/sctp/sm.h
+++ b/include/net/sctp/sm.h
@@ -214,7 +214,7 @@ struct sctp_chunk *sctp_make_shutdown_ack(const struct sctp_association *asoc,
214 const struct sctp_chunk *); 214 const struct sctp_chunk *);
215struct sctp_chunk *sctp_make_shutdown_complete(const struct sctp_association *, 215struct sctp_chunk *sctp_make_shutdown_complete(const struct sctp_association *,
216 const struct sctp_chunk *); 216 const struct sctp_chunk *);
217void sctp_init_cause(struct sctp_chunk *, __be16 cause, const void *, size_t); 217void sctp_init_cause(struct sctp_chunk *, __be16 cause, size_t);
218struct sctp_chunk *sctp_make_abort(const struct sctp_association *, 218struct sctp_chunk *sctp_make_abort(const struct sctp_association *,
219 const struct sctp_chunk *, 219 const struct sctp_chunk *,
220 const size_t hint); 220 const size_t hint);
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index ee4559b11302..c0d5848c33dc 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -726,6 +726,7 @@ int sctp_user_addto_chunk(struct sctp_chunk *chunk, int off, int len,
726 struct iovec *data); 726 struct iovec *data);
727void sctp_chunk_free(struct sctp_chunk *); 727void sctp_chunk_free(struct sctp_chunk *);
728void *sctp_addto_chunk(struct sctp_chunk *, int len, const void *data); 728void *sctp_addto_chunk(struct sctp_chunk *, int len, const void *data);
729void *sctp_addto_param(struct sctp_chunk *, int len, const void *data);
729struct sctp_chunk *sctp_chunkify(struct sk_buff *, 730struct sctp_chunk *sctp_chunkify(struct sk_buff *,
730 const struct sctp_association *, 731 const struct sctp_association *,
731 struct sock *); 732 struct sock *);
diff --git a/include/net/sctp/ulpqueue.h b/include/net/sctp/ulpqueue.h
index 39ea3f442b47..cd33270e86dd 100644
--- a/include/net/sctp/ulpqueue.h
+++ b/include/net/sctp/ulpqueue.h
@@ -83,6 +83,7 @@ int sctp_clear_pd(struct sock *sk, struct sctp_association *asoc);
83/* Skip over an SSN. */ 83/* Skip over an SSN. */
84void sctp_ulpq_skip(struct sctp_ulpq *ulpq, __u16 sid, __u16 ssn); 84void sctp_ulpq_skip(struct sctp_ulpq *ulpq, __u16 sid, __u16 ssn);
85 85
86void sctp_ulpq_reasm_flushtsn(struct sctp_ulpq *, __u32);
86#endif /* __sctp_ulpqueue_h__ */ 87#endif /* __sctp_ulpqueue_h__ */
87 88
88 89
diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
index 007d442412e2..b4b31132618b 100644
--- a/include/scsi/libiscsi.h
+++ b/include/scsi/libiscsi.h
@@ -205,6 +205,13 @@ struct iscsi_queue {
205}; 205};
206 206
207struct iscsi_session { 207struct iscsi_session {
208 /*
209 * Syncs up the scsi eh thread with the iscsi eh thread when sending
210 * task management functions. This must be taken before the session
211 * and recv lock.
212 */
213 struct mutex eh_mutex;
214
208 /* iSCSI session-wide sequencing */ 215 /* iSCSI session-wide sequencing */
209 uint32_t cmdsn; 216 uint32_t cmdsn;
210 uint32_t exp_cmdsn; 217 uint32_t exp_cmdsn;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 18:35:38 -0500