diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/amba/pl08x.h | 141 |
1 files changed, 2 insertions, 139 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h index 88765a62c8f2..48d02bf66ec9 100644 --- a/include/linux/amba/pl08x.h +++ b/include/linux/amba/pl08x.h | |||
@@ -21,8 +21,9 @@ | |||
21 | #include <linux/dmaengine.h> | 21 | #include <linux/dmaengine.h> |
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | 23 | ||
24 | struct pl08x_lli; | ||
25 | struct pl08x_driver_data; | 24 | struct pl08x_driver_data; |
25 | struct pl08x_phy_chan; | ||
26 | struct pl08x_txd; | ||
26 | 27 | ||
27 | /* Bitmasks for selecting AHB ports for DMA transfers */ | 28 | /* Bitmasks for selecting AHB ports for DMA transfers */ |
28 | enum { | 29 | enum { |
@@ -68,144 +69,6 @@ struct pl08x_channel_data { | |||
68 | }; | 69 | }; |
69 | 70 | ||
70 | /** | 71 | /** |
71 | * Struct pl08x_bus_data - information of source or destination | ||
72 | * busses for a transfer | ||
73 | * @addr: current address | ||
74 | * @maxwidth: the maximum width of a transfer on this bus | ||
75 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | ||
76 | */ | ||
77 | struct pl08x_bus_data { | ||
78 | dma_addr_t addr; | ||
79 | u8 maxwidth; | ||
80 | u8 buswidth; | ||
81 | }; | ||
82 | |||
83 | /** | ||
84 | * struct pl08x_phy_chan - holder for the physical channels | ||
85 | * @id: physical index to this channel | ||
86 | * @lock: a lock to use when altering an instance of this struct | ||
87 | * @signal: the physical signal (aka channel) serving this physical channel | ||
88 | * right now | ||
89 | * @serving: the virtual channel currently being served by this physical | ||
90 | * channel | ||
91 | * @locked: channel unavailable for the system, e.g. dedicated to secure | ||
92 | * world | ||
93 | */ | ||
94 | struct pl08x_phy_chan { | ||
95 | unsigned int id; | ||
96 | void __iomem *base; | ||
97 | spinlock_t lock; | ||
98 | int signal; | ||
99 | struct pl08x_dma_chan *serving; | ||
100 | bool locked; | ||
101 | }; | ||
102 | |||
103 | /** | ||
104 | * struct pl08x_sg - structure containing data per sg | ||
105 | * @src_addr: src address of sg | ||
106 | * @dst_addr: dst address of sg | ||
107 | * @len: transfer len in bytes | ||
108 | * @node: node for txd's dsg_list | ||
109 | */ | ||
110 | struct pl08x_sg { | ||
111 | dma_addr_t src_addr; | ||
112 | dma_addr_t dst_addr; | ||
113 | size_t len; | ||
114 | struct list_head node; | ||
115 | }; | ||
116 | |||
117 | /** | ||
118 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | ||
119 | * @tx: async tx descriptor | ||
120 | * @node: node for txd list for channels | ||
121 | * @dsg_list: list of children sg's | ||
122 | * @direction: direction of transfer | ||
123 | * @llis_bus: DMA memory address (physical) start for the LLIs | ||
124 | * @llis_va: virtual memory address start for the LLIs | ||
125 | * @cctl: control reg values for current txd | ||
126 | * @ccfg: config reg values for current txd | ||
127 | */ | ||
128 | struct pl08x_txd { | ||
129 | struct dma_async_tx_descriptor tx; | ||
130 | struct list_head node; | ||
131 | struct list_head dsg_list; | ||
132 | enum dma_transfer_direction direction; | ||
133 | dma_addr_t llis_bus; | ||
134 | struct pl08x_lli *llis_va; | ||
135 | /* Default cctl value for LLIs */ | ||
136 | u32 cctl; | ||
137 | /* | ||
138 | * Settings to be put into the physical channel when we | ||
139 | * trigger this txd. Other registers are in llis_va[0]. | ||
140 | */ | ||
141 | u32 ccfg; | ||
142 | }; | ||
143 | |||
144 | /** | ||
145 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | ||
146 | * states | ||
147 | * @PL08X_CHAN_IDLE: the channel is idle | ||
148 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | ||
149 | * channel and is running a transfer on it | ||
150 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | ||
151 | * channel, but the transfer is currently paused | ||
152 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | ||
153 | * channel to become available (only pertains to memcpy channels) | ||
154 | */ | ||
155 | enum pl08x_dma_chan_state { | ||
156 | PL08X_CHAN_IDLE, | ||
157 | PL08X_CHAN_RUNNING, | ||
158 | PL08X_CHAN_PAUSED, | ||
159 | PL08X_CHAN_WAITING, | ||
160 | }; | ||
161 | |||
162 | /** | ||
163 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | ||
164 | * @chan: wrappped abstract channel | ||
165 | * @phychan: the physical channel utilized by this channel, if there is one | ||
166 | * @phychan_hold: if non-zero, hold on to the physical channel even if we | ||
167 | * have no pending entries | ||
168 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc | ||
169 | * @name: name of channel | ||
170 | * @cd: channel platform data | ||
171 | * @runtime_addr: address for RX/TX according to the runtime config | ||
172 | * @runtime_direction: current direction of this channel according to | ||
173 | * runtime config | ||
174 | * @pend_list: queued transactions pending on this channel | ||
175 | * @at: active transaction on this channel | ||
176 | * @lock: a lock for this channel data | ||
177 | * @host: a pointer to the host (internal use) | ||
178 | * @state: whether the channel is idle, paused, running etc | ||
179 | * @slave: whether this channel is a device (slave) or for memcpy | ||
180 | * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave | ||
181 | * channels. Fill with 'true' if peripheral should be flow controller. Direction | ||
182 | * will be selected at Runtime. | ||
183 | * @waiting: a TX descriptor on this channel which is waiting for a physical | ||
184 | * channel to become available | ||
185 | */ | ||
186 | struct pl08x_dma_chan { | ||
187 | struct dma_chan chan; | ||
188 | struct pl08x_phy_chan *phychan; | ||
189 | int phychan_hold; | ||
190 | struct tasklet_struct tasklet; | ||
191 | char *name; | ||
192 | const struct pl08x_channel_data *cd; | ||
193 | dma_addr_t src_addr; | ||
194 | dma_addr_t dst_addr; | ||
195 | u32 src_cctl; | ||
196 | u32 dst_cctl; | ||
197 | enum dma_transfer_direction runtime_direction; | ||
198 | struct list_head pend_list; | ||
199 | struct pl08x_txd *at; | ||
200 | spinlock_t lock; | ||
201 | struct pl08x_driver_data *host; | ||
202 | enum pl08x_dma_chan_state state; | ||
203 | bool slave; | ||
204 | bool device_fc; | ||
205 | struct pl08x_txd *waiting; | ||
206 | }; | ||
207 | |||
208 | /** | ||
209 | * struct pl08x_platform_data - the platform configuration for the PL08x | 72 | * struct pl08x_platform_data - the platform configuration for the PL08x |
210 | * PrimeCells. | 73 | * PrimeCells. |
211 | * @slave_channels: the channels defined for the different devices on the | 74 | * @slave_channels: the channels defined for the different devices on the |