5 files changed, 129 insertions, 93 deletions
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index c3c280e3d591..042f821899a8 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -9,86 +9,104 @@
 #ifndef __ASM_IP32_INTS_H
 #define __ASM_IP32_INTS_H
+#include <asm/irq.h>
 /*
 * This list reflects the assignment of interrupt numbers to
 * interrupting events.  Order is fairly irrelevant to handling
 * priority.  This differs from irix.
 */
-/* CPU */
+enum ip32_irq_no {
-#define IP32_R4K_TIMER_IRQ              0
+        /*
+         * CPU interrupts are 0 ... 7
+         */
-/* MACE */
+        /*
-#define MACE_VID_IN1_IRQ                1
+         * MACE
-#define MACE_VID_IN2_IRQ                2
+         */
-#define MACE_VID_OUT_IRQ                3
+        MACE_VID_IN1_IRQ                = MIPS_CPU_IRQ_BASE + 8,
-#define MACE_ETHERNET_IRQ               4
+        MACE_VID_IN2_IRQ,
-/* SUPERIO, MISC, and AUDIO are MACEISA */
+        MACE_VID_OUT_IRQ,
-#define MACE_PCI_BRIDGE_IRQ             8
+        MACE_ETHERNET_IRQ,
+        /* SUPERIO, MISC, and AUDIO are MACEISA */
+        __MACE_SUPERIO,
+        __MACE_MISC,
+        __MACE_AUDIO,
+        MACE_PCI_BRIDGE_IRQ,
-/* MACEPCI */
+        /*
-#define MACEPCI_SCSI0_IRQ               9
+         * MACEPCI
-#define MACEPCI_SCSI1_IRQ               10
+         */
-#define MACEPCI_SLOT0_IRQ               11
+        MACEPCI_SCSI0_IRQ,
-#define MACEPCI_SLOT1_IRQ               12
+        MACEPCI_SCSI1_IRQ,
-#define MACEPCI_SLOT2_IRQ               13
+        MACEPCI_SLOT0_IRQ,
-#define MACEPCI_SHARED0_IRQ             14
+        MACEPCI_SLOT1_IRQ,
-#define MACEPCI_SHARED1_IRQ             15
+        MACEPCI_SLOT2_IRQ,
-#define MACEPCI_SHARED2_IRQ             16
+        MACEPCI_SHARED0_IRQ,
+        MACEPCI_SHARED1_IRQ,
+        MACEPCI_SHARED2_IRQ,
-/* CRIME */
+        /*
-#define CRIME_GBE0_IRQ                  17
+         * CRIME
-#define CRIME_GBE1_IRQ                  18
+         */
-#define CRIME_GBE2_IRQ                  19
+        CRIME_GBE0_IRQ,
-#define CRIME_GBE3_IRQ                  20
+        CRIME_GBE1_IRQ,
-#define CRIME_CPUERR_IRQ                21
+        CRIME_GBE2_IRQ,
-#define CRIME_MEMERR_IRQ                22
+        CRIME_GBE3_IRQ,
-#define CRIME_RE_EMPTY_E_IRQ            23
+        CRIME_CPUERR_IRQ,
-#define CRIME_RE_FULL_E_IRQ             24
+        CRIME_MEMERR_IRQ,
-#define CRIME_RE_IDLE_E_IRQ             25
+        CRIME_RE_EMPTY_E_IRQ,
-#define CRIME_RE_EMPTY_L_IRQ            26
+        CRIME_RE_FULL_E_IRQ,
-#define CRIME_RE_FULL_L_IRQ             27
+        CRIME_RE_IDLE_E_IRQ,
-#define CRIME_RE_IDLE_L_IRQ             28
+        CRIME_RE_EMPTY_L_IRQ,
-#define CRIME_SOFT0_IRQ                 29
+        CRIME_RE_FULL_L_IRQ,
-#define CRIME_SOFT1_IRQ                 30
+        CRIME_RE_IDLE_L_IRQ,
-#define CRIME_SOFT2_IRQ                 31
+        CRIME_SOFT0_IRQ,
-#define CRIME_SYSCORERR_IRQ             CRIME_SOFT2_IRQ
+        CRIME_SOFT1_IRQ,
-#define CRIME_VICE_IRQ                  32
+        CRIME_SOFT2_IRQ,
+        CRIME_SYSCORERR_IRQ             = CRIME_SOFT2_IRQ,
+        CRIME_VICE_IRQ,
-/* MACEISA */
+        /*
-#define MACEISA_AUDIO_SW_IRQ            33
+         * MACEISA
-#define MACEISA_AUDIO_SC_IRQ            34
+         */
-#define MACEISA_AUDIO1_DMAT_IRQ         35
+        MACEISA_AUDIO_SW_IRQ,
-#define MACEISA_AUDIO1_OF_IRQ           36
+        MACEISA_AUDIO_SC_IRQ,
-#define MACEISA_AUDIO2_DMAT_IRQ         37
+        MACEISA_AUDIO1_DMAT_IRQ,
-#define MACEISA_AUDIO2_MERR_IRQ         38
+        MACEISA_AUDIO1_OF_IRQ,
-#define MACEISA_AUDIO3_DMAT_IRQ         39
+        MACEISA_AUDIO2_DMAT_IRQ,
-#define MACEISA_AUDIO3_MERR_IRQ         40
+        MACEISA_AUDIO2_MERR_IRQ,
-#define MACEISA_RTC_IRQ                 41
+        MACEISA_AUDIO3_DMAT_IRQ,
-#define MACEISA_KEYB_IRQ                42
+        MACEISA_AUDIO3_MERR_IRQ,
-/* MACEISA_KEYB_POLL is not an IRQ */
+        MACEISA_RTC_IRQ,
-#define MACEISA_MOUSE_IRQ               44
+        MACEISA_KEYB_IRQ,
-/* MACEISA_MOUSE_POLL is not an IRQ */
+        /* MACEISA_KEYB_POLL is not an IRQ */
-#define MACEISA_TIMER0_IRQ              46
+        __MACEISA_KEYB_POLL,
-#define MACEISA_TIMER1_IRQ              47
+        MACEISA_MOUSE_IRQ,
-#define MACEISA_TIMER2_IRQ              48
+        /* MACEISA_MOUSE_POLL is not an IRQ */
-#define MACEISA_PARALLEL_IRQ            49
+        __MACEISA_MOUSE_POLL,
-#define MACEISA_PAR_CTXA_IRQ            50
+        MACEISA_TIMER0_IRQ,
-#define MACEISA_PAR_CTXB_IRQ            51
+        MACEISA_TIMER1_IRQ,
-#define MACEISA_PAR_MERR_IRQ            52
+        MACEISA_TIMER2_IRQ,
-#define MACEISA_SERIAL1_IRQ             53
+        MACEISA_PARALLEL_IRQ,
-#define MACEISA_SERIAL1_TDMAT_IRQ       54
+        MACEISA_PAR_CTXA_IRQ,
-#define MACEISA_SERIAL1_TDMAPR_IRQ      55
+        MACEISA_PAR_CTXB_IRQ,
-#define MACEISA_SERIAL1_TDMAME_IRQ      56
+        MACEISA_PAR_MERR_IRQ,
-#define MACEISA_SERIAL1_RDMAT_IRQ       57
+        MACEISA_SERIAL1_IRQ,
-#define MACEISA_SERIAL1_RDMAOR_IRQ      58
+        MACEISA_SERIAL1_TDMAT_IRQ,
-#define MACEISA_SERIAL2_IRQ             59
+        MACEISA_SERIAL1_TDMAPR_IRQ,
-#define MACEISA_SERIAL2_TDMAT_IRQ       60
+        MACEISA_SERIAL1_TDMAME_IRQ,
-#define MACEISA_SERIAL2_TDMAPR_IRQ      61
+        MACEISA_SERIAL1_RDMAT_IRQ,
-#define MACEISA_SERIAL2_TDMAME_IRQ      62
+        MACEISA_SERIAL1_RDMAOR_IRQ,
-#define MACEISA_SERIAL2_RDMAT_IRQ       63
+        MACEISA_SERIAL2_IRQ,
-#define MACEISA_SERIAL2_RDMAOR_IRQ      64
+        MACEISA_SERIAL2_TDMAT_IRQ,
+        MACEISA_SERIAL2_TDMAPR_IRQ,
+        MACEISA_SERIAL2_TDMAME_IRQ,
+        MACEISA_SERIAL2_RDMAT_IRQ,
+        MACEISA_SERIAL2_RDMAOR_IRQ,
-#define IP32_IRQ_MAX                    MACEISA_SERIAL2_RDMAOR_IRQ
+        IP32_IRQ_MAX                    = MACEISA_SERIAL2_RDMAOR_IRQ
+};
 #endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
index 065474feeccc..581dc45685a2 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/include/asm-mips/lasat/lasatint.h
@@ -1,4 +1,10 @@
-#define LASATINT_END 16
+#ifndef __ASM_LASAT_LASATINT_H
+#define __ASM_LASAT_LASATINT_H
+#include <linux/irq.h>
+#define LASATINT_BASE   MIPS_CPU_IRQ_BASE
+#define LASATINT_END    (LASATINT_BASE + 16)
 /* lasat 100 */
 #define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
@@ -10,3 +16,4 @@
 #define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
 #define LASATINT_MASK_SHIFT_200         16
+#endif /* __ASM_LASAT_LASATINT_H */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 10f613f23c33..b37baf8cf624 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -91,23 +91,6 @@ static inline u32 au_readl(unsigned long reg)
 }
-static __inline__ int au_ffz(unsigned int x)
-{
-        if ((x = ~x) == 0)
-                return 32;
-        return __ilog2(x & -x);
-}
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
-        return __ilog2(x & -x) + 1;
-}
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
@@ -119,16 +102,16 @@ extern unsigned int get_au1x00_lcd_clock(void);
 /*
 * Every board describes its IRQ mapping with this table.
 */
-typedef struct au1xxx_irqmap {
+struct au1xxx_irqmap {
        int     im_irq;
        int     im_type;
        int     im_request;
-} au1xxx_irq_map_t;
+};
 /*
 * init_IRQ looks for a table with this name.
 */
-extern au1xxx_irq_map_t au1xxx_irq_map[];
+extern struct au1xxx_irqmap au1xxx_irq_map[];
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h
new file mode 100644
index 000000000000..0bf48fc1892b
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
+#define __ASM_MIPS_PMC_SIERRA_WAR_H
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 85b44366343a..786f7e3c99bc 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -86,9 +86,9 @@ struct pt_regs {
 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
-extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
+extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
-static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
 {
        if (unlikely(!user_mode(regs)))
                die(str, regs);

diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h index c3c280e3d591..042f821899a8 100644 --- a/include/asm-mips/ip32/ip32_ints.h +++ b/include/asm-mips/ip32/ip32_ints.h
@@ -9,86 +9,104 @@
9	#ifndef __ASM_IP32_INTS_H	9	#ifndef __ASM_IP32_INTS_H
10	#define __ASM_IP32_INTS_H	10	#define __ASM_IP32_INTS_H
11		11
		12	#include <asm/irq.h>
		13
12	/*	14	/*
13	* This list reflects the assignment of interrupt numbers to	15	* This list reflects the assignment of interrupt numbers to
14	* interrupting events. Order is fairly irrelevant to handling	16	* interrupting events. Order is fairly irrelevant to handling
15	* priority. This differs from irix.	17	* priority. This differs from irix.
16	*/	18	*/
17		19
18	/* CPU */	20	enum ip32_irq_no {
19	#define IP32_R4K_TIMER_IRQ 0	21	/*
		22	* CPU interrupts are 0 ... 7
		23	*/
20		24
21	/* MACE */	25	/*
22	#define MACE_VID_IN1_IRQ 1	26	* MACE
23	#define MACE_VID_IN2_IRQ 2	27	*/
24	#define MACE_VID_OUT_IRQ 3	28	MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8,
25	#define MACE_ETHERNET_IRQ 4	29	MACE_VID_IN2_IRQ,
26	/* SUPERIO, MISC, and AUDIO are MACEISA */	30	MACE_VID_OUT_IRQ,
27	#define MACE_PCI_BRIDGE_IRQ 8	31	MACE_ETHERNET_IRQ,
		32	/* SUPERIO, MISC, and AUDIO are MACEISA */
		33	__MACE_SUPERIO,
		34	__MACE_MISC,
		35	__MACE_AUDIO,
		36	MACE_PCI_BRIDGE_IRQ,
28		37
29	/* MACEPCI */	38	/*
30	#define MACEPCI_SCSI0_IRQ 9	39	* MACEPCI
31	#define MACEPCI_SCSI1_IRQ 10	40	*/
32	#define MACEPCI_SLOT0_IRQ 11	41	MACEPCI_SCSI0_IRQ,
33	#define MACEPCI_SLOT1_IRQ 12	42	MACEPCI_SCSI1_IRQ,
34	#define MACEPCI_SLOT2_IRQ 13	43	MACEPCI_SLOT0_IRQ,
35	#define MACEPCI_SHARED0_IRQ 14	44	MACEPCI_SLOT1_IRQ,
36	#define MACEPCI_SHARED1_IRQ 15	45	MACEPCI_SLOT2_IRQ,
37	#define MACEPCI_SHARED2_IRQ 16	46	MACEPCI_SHARED0_IRQ,
		47	MACEPCI_SHARED1_IRQ,
		48	MACEPCI_SHARED2_IRQ,
38		49
39	/* CRIME */	50	/*
40	#define CRIME_GBE0_IRQ 17	51	* CRIME
41	#define CRIME_GBE1_IRQ 18	52	*/
42	#define CRIME_GBE2_IRQ 19	53	CRIME_GBE0_IRQ,
43	#define CRIME_GBE3_IRQ 20	54	CRIME_GBE1_IRQ,
44	#define CRIME_CPUERR_IRQ 21	55	CRIME_GBE2_IRQ,
45	#define CRIME_MEMERR_IRQ 22	56	CRIME_GBE3_IRQ,
46	#define CRIME_RE_EMPTY_E_IRQ 23	57	CRIME_CPUERR_IRQ,
47	#define CRIME_RE_FULL_E_IRQ 24	58	CRIME_MEMERR_IRQ,
48	#define CRIME_RE_IDLE_E_IRQ 25	59	CRIME_RE_EMPTY_E_IRQ,
49	#define CRIME_RE_EMPTY_L_IRQ 26	60	CRIME_RE_FULL_E_IRQ,
50	#define CRIME_RE_FULL_L_IRQ 27	61	CRIME_RE_IDLE_E_IRQ,
51	#define CRIME_RE_IDLE_L_IRQ 28	62	CRIME_RE_EMPTY_L_IRQ,
52	#define CRIME_SOFT0_IRQ 29	63	CRIME_RE_FULL_L_IRQ,
53	#define CRIME_SOFT1_IRQ 30	64	CRIME_RE_IDLE_L_IRQ,
54	#define CRIME_SOFT2_IRQ 31	65	CRIME_SOFT0_IRQ,
55	#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ	66	CRIME_SOFT1_IRQ,
56	#define CRIME_VICE_IRQ 32	67	CRIME_SOFT2_IRQ,
		68	CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
		69	CRIME_VICE_IRQ,
57		70
58	/* MACEISA */	71	/*
59	#define MACEISA_AUDIO_SW_IRQ 33	72	* MACEISA
60	#define MACEISA_AUDIO_SC_IRQ 34	73	*/
61	#define MACEISA_AUDIO1_DMAT_IRQ 35	74	MACEISA_AUDIO_SW_IRQ,
62	#define MACEISA_AUDIO1_OF_IRQ 36	75	MACEISA_AUDIO_SC_IRQ,
63	#define MACEISA_AUDIO2_DMAT_IRQ 37	76	MACEISA_AUDIO1_DMAT_IRQ,
64	#define MACEISA_AUDIO2_MERR_IRQ 38	77	MACEISA_AUDIO1_OF_IRQ,
65	#define MACEISA_AUDIO3_DMAT_IRQ 39	78	MACEISA_AUDIO2_DMAT_IRQ,
66	#define MACEISA_AUDIO3_MERR_IRQ 40	79	MACEISA_AUDIO2_MERR_IRQ,
67	#define MACEISA_RTC_IRQ 41	80	MACEISA_AUDIO3_DMAT_IRQ,
68	#define MACEISA_KEYB_IRQ 42	81	MACEISA_AUDIO3_MERR_IRQ,
69	/* MACEISA_KEYB_POLL is not an IRQ */	82	MACEISA_RTC_IRQ,
70	#define MACEISA_MOUSE_IRQ 44	83	MACEISA_KEYB_IRQ,
71	/* MACEISA_MOUSE_POLL is not an IRQ */	84	/* MACEISA_KEYB_POLL is not an IRQ */
72	#define MACEISA_TIMER0_IRQ 46	85	__MACEISA_KEYB_POLL,
73	#define MACEISA_TIMER1_IRQ 47	86	MACEISA_MOUSE_IRQ,
74	#define MACEISA_TIMER2_IRQ 48	87	/* MACEISA_MOUSE_POLL is not an IRQ */
75	#define MACEISA_PARALLEL_IRQ 49	88	__MACEISA_MOUSE_POLL,
76	#define MACEISA_PAR_CTXA_IRQ 50	89	MACEISA_TIMER0_IRQ,
77	#define MACEISA_PAR_CTXB_IRQ 51	90	MACEISA_TIMER1_IRQ,
78	#define MACEISA_PAR_MERR_IRQ 52	91	MACEISA_TIMER2_IRQ,
79	#define MACEISA_SERIAL1_IRQ 53	92	MACEISA_PARALLEL_IRQ,
80	#define MACEISA_SERIAL1_TDMAT_IRQ 54	93	MACEISA_PAR_CTXA_IRQ,
81	#define MACEISA_SERIAL1_TDMAPR_IRQ 55	94	MACEISA_PAR_CTXB_IRQ,
82	#define MACEISA_SERIAL1_TDMAME_IRQ 56	95	MACEISA_PAR_MERR_IRQ,
83	#define MACEISA_SERIAL1_RDMAT_IRQ 57	96	MACEISA_SERIAL1_IRQ,
84	#define MACEISA_SERIAL1_RDMAOR_IRQ 58	97	MACEISA_SERIAL1_TDMAT_IRQ,
85	#define MACEISA_SERIAL2_IRQ 59	98	MACEISA_SERIAL1_TDMAPR_IRQ,
86	#define MACEISA_SERIAL2_TDMAT_IRQ 60	99	MACEISA_SERIAL1_TDMAME_IRQ,
87	#define MACEISA_SERIAL2_TDMAPR_IRQ 61	100	MACEISA_SERIAL1_RDMAT_IRQ,
88	#define MACEISA_SERIAL2_TDMAME_IRQ 62	101	MACEISA_SERIAL1_RDMAOR_IRQ,
89	#define MACEISA_SERIAL2_RDMAT_IRQ 63	102	MACEISA_SERIAL2_IRQ,
90	#define MACEISA_SERIAL2_RDMAOR_IRQ 64	103	MACEISA_SERIAL2_TDMAT_IRQ,
		104	MACEISA_SERIAL2_TDMAPR_IRQ,
		105	MACEISA_SERIAL2_TDMAME_IRQ,
		106	MACEISA_SERIAL2_RDMAT_IRQ,
		107	MACEISA_SERIAL2_RDMAOR_IRQ,
91		108
92	#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ	109	IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
		110	};
93		111
94	#endif /* __ASM_IP32_INTS_H */	112	#endif /* __ASM_IP32_INTS_H */


diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h index 065474feeccc..581dc45685a2 100644 --- a/include/asm-mips/lasat/lasatint.h +++ b/include/asm-mips/lasat/lasatint.h
@@ -1,4 +1,10 @@
1	#define LASATINT_END 16	1	#ifndef __ASM_LASAT_LASATINT_H
		2	#define __ASM_LASAT_LASATINT_H
		3
		4	#include <linux/irq.h>
		5
		6	#define LASATINT_BASE MIPS_CPU_IRQ_BASE
		7	#define LASATINT_END (LASATINT_BASE + 16)
2		8
3	/* lasat 100 */	9	/* lasat 100 */
4	#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))	10	#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
@@ -10,3 +16,4 @@
10	#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))	16	#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
11	#define LASATINT_MASK_SHIFT_200 16	17	#define LASATINT_MASK_SHIFT_200 16
12		18
		19	#endif /* __ASM_LASAT_LASATINT_H */


diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 10f613f23c33..b37baf8cf624 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -91,23 +91,6 @@ static inline u32 au_readl(unsigned long reg)
91	}	91	}
92		92
93		93
94	static __inline__ int au_ffz(unsigned int x)
95	{
96	if ((x = ~x) == 0)
97	return 32;
98	return __ilog2(x & -x);
99	}
100
101	/*
102	* ffs: find first bit set. This is defined the same way as
103	* the libc and compiler builtin ffs routines, therefore
104	* differs in spirit from the above ffz (man ffs).
105	*/
106	static __inline__ int au_ffs(int x)
107	{
108	return __ilog2(x & -x) + 1;
109	}
110
111	/* arch/mips/au1000/common/clocks.c */	94	/* arch/mips/au1000/common/clocks.c */
112	extern void set_au1x00_speed(unsigned int new_freq);	95	extern void set_au1x00_speed(unsigned int new_freq);
113	extern unsigned int get_au1x00_speed(void);	96	extern unsigned int get_au1x00_speed(void);
@@ -119,16 +102,16 @@ extern unsigned int get_au1x00_lcd_clock(void);
119	/*	102	/*
120	* Every board describes its IRQ mapping with this table.	103	* Every board describes its IRQ mapping with this table.
121	*/	104	*/
122	typedef struct au1xxx_irqmap {	105	struct au1xxx_irqmap {
123	int im_irq;	106	int im_irq;
124	int im_type;	107	int im_type;
125	int im_request;	108	int im_request;
126	} au1xxx_irq_map_t;	109	};
127		110
128	/*	111	/*
129	* init_IRQ looks for a table with this name.	112	* init_IRQ looks for a table with this name.
130	*/	113	*/
131	extern au1xxx_irq_map_t au1xxx_irq_map[];	114	extern struct au1xxx_irqmap au1xxx_irq_map[];
132		115
133	#endif /* !defined (_LANGUAGE_ASSEMBLY) */	116	#endif /* !defined (_LANGUAGE_ASSEMBLY) */
134		117


diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h new file mode 100644 index 000000000000..0bf48fc1892b --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
		1	/*
		2	* This file is subject to the terms and conditions of the GNU General Public
		3	* License. See the file "COPYING" in the main directory of this archive
		4	* for more details.
		5	*
		6	* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
		7	*/
		8	#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
		9	#define __ASM_MIPS_PMC_SIERRA_WAR_H
		10
		11	#define R4600_V1_INDEX_ICACHEOP_WAR 0
		12	#define R4600_V1_HIT_CACHEOP_WAR 0
		13	#define R4600_V2_HIT_CACHEOP_WAR 0
		14	#define R5432_CP0_INTERRUPT_WAR 0
		15	#define BCM1250_M3_WAR 0
		16	#define SIBYTE_1956_WAR 0
		17	#define MIPS4K_ICACHE_REFILL_WAR 0
		18	#define MIPS_CACHE_SYNC_WAR 0
		19	#define TX49XX_ICACHE_INDEX_INV_WAR 0
		20	#define RM9000_CDEX_SMP_WAR 0
		21	#define ICACHE_REFILLS_WORKAROUND_WAR 0
		22	#define R10000_LLSC_WAR 0
		23	#if defined(CONFIG_PMC_MSP7120_EVAL) \|\| defined(CONFIG_PMC_MSP7120_GW) \|\| \
		24	defined(CONFIG_PMC_MSP7120_FPGA)
		25	#define MIPS34K_MISSED_ITLB_WAR 1
		26	#endif
		27
		28	#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */


diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 85b44366343a..786f7e3c99bc 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h
@@ -86,9 +86,9 @@ struct pt_regs {
86		86
87	extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);	87	extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
88		88
89	extern NORET_TYPE void die(const char , struct pt_regs ) ATTRIB_NORET;	89	extern NORET_TYPE void die(const char , const struct pt_regs ) ATTRIB_NORET;
90		90
91	static inline void die_if_kernel(const char str, struct pt_regs regs)	91	static inline void die_if_kernel(const char str, const struct pt_regs regs)
92	{	92	{
93	if (unlikely(!user_mode(regs)))	93	if (unlikely(!user_mode(regs)))
94	die(str, regs);	94	die(str, regs);