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-rw-r--r--include/asm-arm/arch-orion/irqs.h62
-rw-r--r--include/asm-arm/arch-orion/orion.h159
-rw-r--r--include/asm-arm/arch-orion5x/debug-macro.S (renamed from include/asm-arm/arch-orion/debug-macro.S)8
-rw-r--r--include/asm-arm/arch-orion5x/dma.h (renamed from include/asm-arm/arch-orion/dma.h)0
-rw-r--r--include/asm-arm/arch-orion5x/entry-macro.S (renamed from include/asm-arm/arch-orion/entry-macro.S)4
-rw-r--r--include/asm-arm/arch-orion5x/gpio.h (renamed from include/asm-arm/arch-orion/gpio.h)8
-rw-r--r--include/asm-arm/arch-orion5x/hardware.h (renamed from include/asm-arm/arch-orion/hardware.h)6
-rw-r--r--include/asm-arm/arch-orion5x/io.h (renamed from include/asm-arm/arch-orion/io.h)26
-rw-r--r--include/asm-arm/arch-orion5x/irqs.h62
-rw-r--r--include/asm-arm/arch-orion5x/memory.h (renamed from include/asm-arm/arch-orion/memory.h)2
-rw-r--r--include/asm-arm/arch-orion5x/orion5x.h159
-rw-r--r--include/asm-arm/arch-orion5x/system.h (renamed from include/asm-arm/arch-orion/system.h)8
-rw-r--r--include/asm-arm/arch-orion5x/timex.h (renamed from include/asm-arm/arch-orion/timex.h)4
-rw-r--r--include/asm-arm/arch-orion5x/uncompress.h (renamed from include/asm-arm/arch-orion/uncompress.h)4
-rw-r--r--include/asm-arm/arch-orion5x/vmalloc.h (renamed from include/asm-arm/arch-orion/vmalloc.h)2
15 files changed, 257 insertions, 257 deletions
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
deleted file mode 100644
index 70a2420456a3..000000000000
--- a/include/asm-arm/arch-orion/irqs.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * include/asm-arm/arch-orion/irqs.h
3 *
4 * IRQ definitions for Orion SoC
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H
15
16#include "orion.h" /* need GPIO_MAX */
17
18/*
19 * Orion Main Interrupt Controller
20 */
21#define IRQ_ORION_BRIDGE 0
22#define IRQ_ORION_DOORBELL_H2C 1
23#define IRQ_ORION_DOORBELL_C2H 2
24#define IRQ_ORION_UART0 3
25#define IRQ_ORION_UART1 4
26#define IRQ_ORION_I2C 5
27#define IRQ_ORION_GPIO_0_7 6
28#define IRQ_ORION_GPIO_8_15 7
29#define IRQ_ORION_GPIO_16_23 8
30#define IRQ_ORION_GPIO_24_31 9
31#define IRQ_ORION_PCIE0_ERR 10
32#define IRQ_ORION_PCIE0_INT 11
33#define IRQ_ORION_USB1_CTRL 12
34#define IRQ_ORION_DEV_BUS_ERR 14
35#define IRQ_ORION_PCI_ERR 15
36#define IRQ_ORION_USB_BR_ERR 16
37#define IRQ_ORION_USB0_CTRL 17
38#define IRQ_ORION_ETH_RX 18
39#define IRQ_ORION_ETH_TX 19
40#define IRQ_ORION_ETH_MISC 20
41#define IRQ_ORION_ETH_SUM 21
42#define IRQ_ORION_ETH_ERR 22
43#define IRQ_ORION_IDMA_ERR 23
44#define IRQ_ORION_IDMA_0 24
45#define IRQ_ORION_IDMA_1 25
46#define IRQ_ORION_IDMA_2 26
47#define IRQ_ORION_IDMA_3 27
48#define IRQ_ORION_CESA 28
49#define IRQ_ORION_SATA 29
50#define IRQ_ORION_XOR0 30
51#define IRQ_ORION_XOR1 31
52
53/*
54 * Orion General Purpose Pins
55 */
56#define IRQ_ORION_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX
58
59#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
60
61
62#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
deleted file mode 100644
index 01f1299472d1..000000000000
--- a/include/asm-arm/arch-orion/orion.h
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * include/asm-arm/arch-orion/orion.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION_H
15#define __ASM_ARCH_ORION_H
16
17/*****************************************************************************
18 * Orion Address Maps
19 *
20 * phys
21 * e0000000 PCIe MEM space
22 * e8000000 PCI MEM space
23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only)
24 * f1000000 on-chip peripheral registers
25 * f2000000 PCIe I/O space
26 * f2100000 PCI I/O space
27 * f4000000 device bus mappings (boot)
28 * fa000000 device bus mappings (cs0)
29 * fa800000 device bus mappings (cs2)
30 * fc000000 device bus mappings (cs0/cs1)
31 *
32 * virt phys size
33 * fdd00000 f1000000 1M on-chip peripheral registers
34 * fde00000 f2000000 1M PCIe I/O space
35 * fdf00000 f2100000 1M PCI I/O space
36 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
37 ****************************************************************************/
38#define ORION_REGS_PHYS_BASE 0xf1000000
39#define ORION_REGS_VIRT_BASE 0xfdd00000
40#define ORION_REGS_SIZE SZ_1M
41
42#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
43#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
44#define ORION_PCIE_IO_BUS_BASE 0x00000000
45#define ORION_PCIE_IO_SIZE SZ_1M
46
47#define ORION_PCI_IO_PHYS_BASE 0xf2100000
48#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
49#define ORION_PCI_IO_BUS_BASE 0x00100000
50#define ORION_PCI_IO_SIZE SZ_1M
51
52/* Relevant only for Orion-1/Orion-NAS */
53#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
54#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
55#define ORION_PCIE_WA_SIZE SZ_16M
56
57#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
58#define ORION_PCIE_MEM_SIZE SZ_128M
59
60#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
61#define ORION_PCI_MEM_SIZE SZ_128M
62
63/*******************************************************************************
64 * Supported Devices & Revisions
65 ******************************************************************************/
66/* Orion-1 (88F5181) */
67#define MV88F5181_DEV_ID 0x5181
68#define MV88F5181_REV_B1 3
69/* Orion-NAS (88F5182) */
70#define MV88F5182_DEV_ID 0x5182
71#define MV88F5182_REV_A2 2
72/* Orion-2 (88F5281) */
73#define MV88F5281_DEV_ID 0x5281
74#define MV88F5281_REV_D1 5
75#define MV88F5281_REV_D2 6
76
77/*******************************************************************************
78 * Orion Registers Map
79 ******************************************************************************/
80#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
81#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
82
83#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
84#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
85#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
86#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
87#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
88#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
89#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
90#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
91
92#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
93#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
94#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300)
95
96#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
97#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
98
99#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
100#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
101
102#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
103#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
104#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
105
106#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
107#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
108#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
109
110#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
111#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
112#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
113
114#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
115#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
116#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
117
118/*******************************************************************************
119 * Device Bus Registers
120 ******************************************************************************/
121#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
122#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
123#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
124#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
125#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
126#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
127#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
128#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
129#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
130#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
131#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
132#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
133#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
134#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
135#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
136#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
137#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
138#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
139#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
140#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
141#define GPIO_MAX 32
142
143/***************************************************************************
144 * Orion CPU Bridge Registers
145 **************************************************************************/
146#define CPU_CONF ORION_BRIDGE_REG(0x100)
147#define CPU_CTRL ORION_BRIDGE_REG(0x104)
148#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
149#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
150#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
151#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
152#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
153#define BRIDGE_INT_TIMER0 0x0002
154#define BRIDGE_INT_TIMER1 0x0004
155#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
156#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
157
158
159#endif
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
index c847f8c92506..4f98f3ba2929 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion5x/debug-macro.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/debug-macro.S 2 * include/asm-arm/arch-orion5x/debug-macro.S
3 * 3 *
4 * Debugging macro include header 4 * Debugging macro include header
5 * 5 *
@@ -8,13 +8,13 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9*/ 9*/
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion5x.h>
12 12
13 .macro addruart,rx 13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0 14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled? 15 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =ORION_REGS_PHYS_BASE 16 ldreq \rx, =ORION5X_REGS_PHYS_BASE
17 ldrne \rx, =ORION_REGS_VIRT_BASE 17 ldrne \rx, =ORION5X_REGS_VIRT_BASE
18 orr \rx, \rx, #0x00012000 18 orr \rx, \rx, #0x00012000
19 .endm 19 .endm
20 20
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-orion/dma.h
+++ b/include/asm-arm/arch-orion5x/dma.h
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
index cda096b2acfd..d8ef54c0ee9a 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion5x/entry-macro.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/entry-macro.S 2 * include/asm-arm/arch-orion5x/entry-macro.S
3 * 3 *
4 * Low-level IRQ helper macros for Orion platforms 4 * Low-level IRQ helper macros for Orion platforms
5 * 5 *
@@ -8,7 +8,7 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion5x.h>
12 12
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
index d66284f9a14c..c85e498388b6 100644
--- a/include/asm-arm/arch-orion/gpio.h
+++ b/include/asm-arm/arch-orion5x/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/gpio.h 2 * include/asm-arm/arch-orion5x/gpio.h
3 * 3 *
4 * This file is licensed under the terms of the GNU General Public 4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any 5 * License version 2. This program is licensed "as is" without any
@@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin);
12extern int gpio_direction_output(unsigned pin, int value); 12extern int gpio_direction_output(unsigned pin, int value);
13extern int gpio_get_value(unsigned pin); 13extern int gpio_get_value(unsigned pin);
14extern void gpio_set_value(unsigned pin, int value); 14extern void gpio_set_value(unsigned pin, int value);
15extern void orion_gpio_set_blink(unsigned pin, int blink); 15extern void orion5x_gpio_set_blink(unsigned pin, int blink);
16extern void gpio_display(void); /* debug */ 16extern void gpio_display(void); /* debug */
17 17
18static inline int gpio_to_irq(int pin) 18static inline int gpio_to_irq(int pin)
19{ 19{
20 return pin + IRQ_ORION_GPIO_START; 20 return pin + IRQ_ORION5X_GPIO_START;
21} 21}
22 22
23static inline int irq_to_gpio(int irq) 23static inline int irq_to_gpio(int irq)
24{ 24{
25 return irq - IRQ_ORION_GPIO_START; 25 return irq - IRQ_ORION5X_GPIO_START;
26} 26}
27 27
28#include <asm-generic/gpio.h> /* cansleep wrappers */ 28#include <asm-generic/gpio.h> /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
index 998af6029c7d..5d2d8e0b5630 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion5x/hardware.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/hardware.h 2 * include/asm-arm/arch-orion5x/hardware.h
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -9,13 +9,13 @@
9#ifndef __ASM_ARCH_HARDWARE_H 9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H 10#define __ASM_ARCH_HARDWARE_H
11 11
12#include "orion.h" 12#include "orion5x.h"
13 13
14#define pcibios_assign_all_busses() 1 14#define pcibios_assign_all_busses() 1
15 15
16#define PCIBIOS_MIN_IO 0x00001000 16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000 17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE 18#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE
19 19
20 20
21#endif 21#endif
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion5x/io.h
index 23820153b61c..5148ab7ad1f8 100644
--- a/include/asm-arm/arch-orion/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/io.h 2 * include/asm-arm/arch-orion5x/io.h
3 * 3 *
4 * Tzachi Perelstein <tzachi@marvell.com> 4 * Tzachi Perelstein <tzachi@marvell.com>
5 * 5 *
@@ -11,20 +11,20 @@
11#ifndef __ASM_ARCH_IO_H 11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H 12#define __ASM_ARCH_IO_H
13 13
14#include "orion.h" 14#include "orion5x.h"
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE 17#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE
18 18
19static inline void __iomem * 19static inline void __iomem *
20__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) 20__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
21{ 21{
22 void __iomem *retval; 22 void __iomem *retval;
23 23
24 if (mtype == MT_DEVICE && size && paddr >= ORION_REGS_PHYS_BASE && 24 if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE &&
25 paddr + size <= ORION_REGS_PHYS_BASE + ORION_REGS_SIZE) { 25 paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) {
26 retval = (void __iomem *)ORION_REGS_VIRT_BASE + 26 retval = (void __iomem *)ORION5X_REGS_VIRT_BASE +
27 (paddr - ORION_REGS_PHYS_BASE); 27 (paddr - ORION5X_REGS_PHYS_BASE);
28 } else { 28 } else {
29 retval = __arm_ioremap(paddr, size, mtype); 29 retval = __arm_ioremap(paddr, size, mtype);
30 } 30 }
@@ -35,8 +35,8 @@ __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
35static inline void 35static inline void
36__arch_iounmap(void __iomem *addr) 36__arch_iounmap(void __iomem *addr)
37{ 37{
38 if (addr < (void __iomem *)ORION_REGS_VIRT_BASE || 38 if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
39 addr >= (void __iomem *)(ORION_REGS_VIRT_BASE + ORION_REGS_SIZE)) 39 addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
40 __iounmap(addr); 40 __iounmap(addr);
41} 41}
42 42
@@ -54,15 +54,15 @@ static inline void __iomem *__io(unsigned long addr)
54/***************************************************************************** 54/*****************************************************************************
55 * Helpers to access Orion registers 55 * Helpers to access Orion registers
56 ****************************************************************************/ 56 ****************************************************************************/
57#define orion_read(r) __raw_readl(r) 57#define orion5x_read(r) __raw_readl(r)
58#define orion_write(r, val) __raw_writel(val, r) 58#define orion5x_write(r, val) __raw_writel(val, r)
59 59
60/* 60/*
61 * These are not preempt-safe. Locks, if needed, must be taken 61 * These are not preempt-safe. Locks, if needed, must be taken
62 * care of by the caller. 62 * care of by the caller.
63 */ 63 */
64#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) 64#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask))
65#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) 65#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask))
66 66
67 67
68#endif 68#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
new file mode 100644
index 000000000000..abdd61a4833a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/irqs.h
@@ -0,0 +1,62 @@
1/*
2 * include/asm-arm/arch-orion5x/irqs.h
3 *
4 * IRQ definitions for Orion SoC
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H
15
16#include "orion5x.h" /* need GPIO_MAX */
17
18/*
19 * Orion Main Interrupt Controller
20 */
21#define IRQ_ORION5X_BRIDGE 0
22#define IRQ_ORION5X_DOORBELL_H2C 1
23#define IRQ_ORION5X_DOORBELL_C2H 2
24#define IRQ_ORION5X_UART0 3
25#define IRQ_ORION5X_UART1 4
26#define IRQ_ORION5X_I2C 5
27#define IRQ_ORION5X_GPIO_0_7 6
28#define IRQ_ORION5X_GPIO_8_15 7
29#define IRQ_ORION5X_GPIO_16_23 8
30#define IRQ_ORION5X_GPIO_24_31 9
31#define IRQ_ORION5X_PCIE0_ERR 10
32#define IRQ_ORION5X_PCIE0_INT 11
33#define IRQ_ORION5X_USB1_CTRL 12
34#define IRQ_ORION5X_DEV_BUS_ERR 14
35#define IRQ_ORION5X_PCI_ERR 15
36#define IRQ_ORION5X_USB_BR_ERR 16
37#define IRQ_ORION5X_USB0_CTRL 17
38#define IRQ_ORION5X_ETH_RX 18
39#define IRQ_ORION5X_ETH_TX 19
40#define IRQ_ORION5X_ETH_MISC 20
41#define IRQ_ORION5X_ETH_SUM 21
42#define IRQ_ORION5X_ETH_ERR 22
43#define IRQ_ORION5X_IDMA_ERR 23
44#define IRQ_ORION5X_IDMA_0 24
45#define IRQ_ORION5X_IDMA_1 25
46#define IRQ_ORION5X_IDMA_2 26
47#define IRQ_ORION5X_IDMA_3 27
48#define IRQ_ORION5X_CESA 28
49#define IRQ_ORION5X_SATA 29
50#define IRQ_ORION5X_XOR0 30
51#define IRQ_ORION5X_XOR1 31
52
53/*
54 * Orion General Purpose Pins
55 */
56#define IRQ_ORION5X_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX
58
59#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
60
61
62#endif
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h
index d9300d62a534..80053a7afc7a 100644
--- a/include/asm-arm/arch-orion/memory.h
+++ b/include/asm-arm/arch-orion5x/memory.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/memory.h 2 * include/asm-arm/arch-orion5x/memory.h
3 * 3 *
4 * Marvell Orion memory definitions 4 * Marvell Orion memory definitions
5 */ 5 */
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 000000000000..206ddd71e193
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,159 @@
1/*
2 * include/asm-arm/arch-orion5x/orion5x.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION5X_H
15#define __ASM_ARCH_ORION5X_H
16
17/*****************************************************************************
18 * Orion Address Maps
19 *
20 * phys
21 * e0000000 PCIe MEM space
22 * e8000000 PCI MEM space
23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only)
24 * f1000000 on-chip peripheral registers
25 * f2000000 PCIe I/O space
26 * f2100000 PCI I/O space
27 * f4000000 device bus mappings (boot)
28 * fa000000 device bus mappings (cs0)
29 * fa800000 device bus mappings (cs2)
30 * fc000000 device bus mappings (cs0/cs1)
31 *
32 * virt phys size
33 * fdd00000 f1000000 1M on-chip peripheral registers
34 * fde00000 f2000000 1M PCIe I/O space
35 * fdf00000 f2100000 1M PCI I/O space
36 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
37 ****************************************************************************/
38#define ORION5X_REGS_PHYS_BASE 0xf1000000
39#define ORION5X_REGS_VIRT_BASE 0xfdd00000
40#define ORION5X_REGS_SIZE SZ_1M
41
42#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
43#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
44#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
45#define ORION5X_PCIE_IO_SIZE SZ_1M
46
47#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
48#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
49#define ORION5X_PCI_IO_BUS_BASE 0x00100000
50#define ORION5X_PCI_IO_SIZE SZ_1M
51
52/* Relevant only for Orion-1/Orion-NAS */
53#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
54#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
55#define ORION5X_PCIE_WA_SIZE SZ_16M
56
57#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
58#define ORION5X_PCIE_MEM_SIZE SZ_128M
59
60#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
61#define ORION5X_PCI_MEM_SIZE SZ_128M
62
63/*******************************************************************************
64 * Supported Devices & Revisions
65 ******************************************************************************/
66/* Orion-1 (88F5181) */
67#define MV88F5181_DEV_ID 0x5181
68#define MV88F5181_REV_B1 3
69/* Orion-NAS (88F5182) */
70#define MV88F5182_DEV_ID 0x5182
71#define MV88F5182_REV_A2 2
72/* Orion-2 (88F5281) */
73#define MV88F5281_DEV_ID 0x5281
74#define MV88F5281_REV_D1 5
75#define MV88F5281_REV_D2 6
76
77/*******************************************************************************
78 * Orion Registers Map
79 ******************************************************************************/
80#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
81#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
82
83#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
84#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
85#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
86#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
87#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
88#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
89#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
90#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
91
92#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
93#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
94#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
95
96#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
97#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
98
99#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
100#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
101
102#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
103#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
104#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
105
106#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
107#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
108#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
109
110#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
111#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
112#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
113
114#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
115#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
116#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
117
118/*******************************************************************************
119 * Device Bus Registers
120 ******************************************************************************/
121#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
122#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
123#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
124#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
125#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
126#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100)
127#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104)
128#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108)
129#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c)
130#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110)
131#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
132#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
133#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
134#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
135#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
136#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
137#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
138#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
139#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
140#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
141#define GPIO_MAX 32
142
143/***************************************************************************
144 * Orion CPU Bridge Registers
145 **************************************************************************/
146#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
147#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
148#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
149#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
150#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
151#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
152#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
153#define BRIDGE_INT_TIMER0 0x0002
154#define BRIDGE_INT_TIMER1 0x0004
155#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
156#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
157
158
159#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h
index 653f992bbe60..3f1d1e2d38f8 100644
--- a/include/asm-arm/arch-orion/system.h
+++ b/include/asm-arm/arch-orion5x/system.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/system.h 2 * include/asm-arm/arch-orion5x/system.h
3 * 3 *
4 * Tzachi Perelstein <tzachi@marvell.com> 4 * Tzachi Perelstein <tzachi@marvell.com>
5 * 5 *
@@ -12,7 +12,7 @@
12#define __ASM_ARCH_SYSTEM_H 12#define __ASM_ARCH_SYSTEM_H
13 13
14#include <asm/arch/hardware.h> 14#include <asm/arch/hardware.h>
15#include <asm/arch/orion.h> 15#include <asm/arch/orion5x.h>
16 16
17static inline void arch_idle(void) 17static inline void arch_idle(void)
18{ 18{
@@ -24,8 +24,8 @@ static inline void arch_reset(char mode)
24 /* 24 /*
25 * Enable and issue soft reset 25 * Enable and issue soft reset
26 */ 26 */
27 orion_setbits(CPU_RESET_MASK, (1 << 2)); 27 orion5x_setbits(CPU_RESET_MASK, (1 << 2));
28 orion_setbits(CPU_SOFT_RESET, 1); 28 orion5x_setbits(CPU_SOFT_RESET, 1);
29} 29}
30 30
31 31
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion5x/timex.h
index 85588d9c22ef..31c568e28cc3 100644
--- a/include/asm-arm/arch-orion/timex.h
+++ b/include/asm-arm/arch-orion5x/timex.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/timex.h 2 * include/asm-arm/arch-orion5x/timex.h
3 * 3 *
4 * Tzachi Perelstein <tzachi@marvell.com> 4 * Tzachi Perelstein <tzachi@marvell.com>
5 * 5 *
@@ -10,4 +10,4 @@
10 10
11#define CLOCK_TICK_RATE (100 * HZ) 11#define CLOCK_TICK_RATE (100 * HZ)
12 12
13#define ORION_TCLK 166666667 13#define ORION5X_TCLK 166666667
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 03306cdd51be..5c13d4fafb4e 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/uncompress.h 2 * include/asm-arm/arch-orion5x/uncompress.h
3 * 3 *
4 * Tzachi Perelstein <tzachi@marvell.com> 4 * Tzachi Perelstein <tzachi@marvell.com>
5 * 5 *
@@ -8,7 +8,7 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11#include <asm/arch/orion.h> 11#include <asm/arch/orion5x.h>
12 12
13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) 13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) 14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
index 9d580278d2bc..2b3061e90dc1 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion5x/vmalloc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-orion/vmalloc.h 2 * include/asm-arm/arch-orion5x/vmalloc.h
3 */ 3 */
4 4
5#define VMALLOC_END 0xfd800000 5#define VMALLOC_END 0xfd800000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 03:49:05 -0500