diff options
Diffstat (limited to 'include')
43 files changed, 994 insertions, 630 deletions
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h index 2e7d1139a799..4fdef13d01d4 100644 --- a/include/asm-arm/arch-at91rm9200/board.h +++ b/include/asm-arm/arch-at91rm9200/board.h | |||
@@ -38,6 +38,8 @@ extern unsigned long at91_master_clock; | |||
38 | extern int at91_serial_map[AT91_NR_UART]; | 38 | extern int at91_serial_map[AT91_NR_UART]; |
39 | extern int at91_console_port; | 39 | extern int at91_console_port; |
40 | 40 | ||
41 | #include <linux/mtd/partitions.h> | ||
42 | |||
41 | /* USB Device */ | 43 | /* USB Device */ |
42 | struct at91_udc_data { | 44 | struct at91_udc_data { |
43 | u8 vbus_pin; /* high == host powering us */ | 45 | u8 vbus_pin; /* high == host powering us */ |
@@ -77,4 +79,26 @@ struct at91_usbh_data { | |||
77 | }; | 79 | }; |
78 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | 80 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); |
79 | 81 | ||
82 | /* NAND / SmartMedia */ | ||
83 | struct at91_nand_data { | ||
84 | u8 enable_pin; /* chip enable */ | ||
85 | u8 det_pin; /* card detect */ | ||
86 | u8 rdy_pin; /* ready/busy */ | ||
87 | u8 ale; /* address line number connected to ALE */ | ||
88 | u8 cle; /* address line number connected to CLE */ | ||
89 | struct mtd_partition* (*partition_info)(int, int*); | ||
90 | }; | ||
91 | extern void __init at91_add_device_nand(struct at91_nand_data *data); | ||
92 | |||
93 | /* I2C*/ | ||
94 | void __init at91_add_device_i2c(void); | ||
95 | |||
96 | /* RTC */ | ||
97 | void __init at91_add_device_rtc(void); | ||
98 | |||
99 | /* LEDs */ | ||
100 | extern u8 at91_leds_cpu; | ||
101 | extern u8 at91_leds_timer; | ||
102 | extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); | ||
103 | |||
80 | #endif | 104 | #endif |
diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h index 412215e77f44..a94f63ff0535 100644 --- a/include/asm-arm/arch-ep93xx/ts72xx.h +++ b/include/asm-arm/arch-ep93xx/ts72xx.h | |||
@@ -12,6 +12,8 @@ | |||
12 | * febfc000 [67]0000000 4K NAND data register | 12 | * febfc000 [67]0000000 4K NAND data register |
13 | * febfb000 [67]0400000 4K NAND control register | 13 | * febfb000 [67]0400000 4K NAND control register |
14 | * febfa000 [67]0800000 4K NAND busy register | 14 | * febfa000 [67]0800000 4K NAND busy register |
15 | * febf9000 10800000 4K TS-5620 RTC index register | ||
16 | * febf8000 11700000 4K TS-5620 RTC data register | ||
15 | */ | 17 | */ |
16 | 18 | ||
17 | #define TS72XX_MODEL_PHYS_BASE 0x22000000 | 19 | #define TS72XX_MODEL_PHYS_BASE 0x22000000 |
@@ -58,6 +60,15 @@ | |||
58 | #define TS72XX_NAND_BUSY_SIZE 0x00001000 | 60 | #define TS72XX_NAND_BUSY_SIZE 0x00001000 |
59 | 61 | ||
60 | 62 | ||
63 | #define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 | ||
64 | #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 | ||
65 | #define TS72XX_RTC_INDEX_SIZE 0x00001000 | ||
66 | |||
67 | #define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 | ||
68 | #define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 | ||
69 | #define TS72XX_RTC_DATA_SIZE 0x00001000 | ||
70 | |||
71 | |||
61 | #ifndef __ASSEMBLY__ | 72 | #ifndef __ASSEMBLY__ |
62 | #include <asm/io.h> | 73 | #include <asm/io.h> |
63 | 74 | ||
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h index b45fa367d71e..621ff2c730f2 100644 --- a/include/asm-arm/arch-imx/dma.h +++ b/include/asm-arm/arch-imx/dma.h | |||
@@ -17,27 +17,16 @@ | |||
17 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
19 | */ | 19 | */ |
20 | |||
20 | #ifndef __ASM_ARCH_DMA_H | 21 | #ifndef __ASM_ARCH_DMA_H |
21 | #define __ASM_ARCH_DMA_H | 22 | #define __ASM_ARCH_DMA_H |
22 | 23 | ||
23 | /* | ||
24 | * DMA registration | ||
25 | */ | ||
26 | |||
27 | typedef enum { | 24 | typedef enum { |
28 | DMA_PRIO_HIGH = 0, | 25 | DMA_PRIO_HIGH = 0, |
29 | DMA_PRIO_MEDIUM = 3, | 26 | DMA_PRIO_MEDIUM = 1, |
30 | DMA_PRIO_LOW = 6 | 27 | DMA_PRIO_LOW = 2 |
31 | } imx_dma_prio; | 28 | } imx_dma_prio; |
32 | 29 | ||
33 | int imx_request_dma(char *name, imx_dma_prio prio, | ||
34 | void (*irq_handler) (int, void *, struct pt_regs *), | ||
35 | void (*err_handler) (int, void *, struct pt_regs *), | ||
36 | void *data); | ||
37 | |||
38 | void imx_free_dma(int dma_ch); | ||
39 | |||
40 | |||
41 | #define DMA_REQ_UART3_T 2 | 30 | #define DMA_REQ_UART3_T 2 |
42 | #define DMA_REQ_UART3_R 3 | 31 | #define DMA_REQ_UART3_R 3 |
43 | #define DMA_REQ_SSI2_T 4 | 32 | #define DMA_REQ_SSI2_T 4 |
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h new file mode 100644 index 000000000000..f2063c1d610d --- /dev/null +++ b/include/asm-arm/arch-imx/imx-dma.h | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/imxads/dma.h | ||
3 | * | ||
4 | * Copyright (C) 1997,1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #include <asm/dma.h> | ||
22 | |||
23 | #ifndef __ASM_ARCH_IMX_DMA_H | ||
24 | #define __ASM_ARCH_IMX_DMA_H | ||
25 | |||
26 | #define IMX_DMA_CHANNELS 11 | ||
27 | |||
28 | /* | ||
29 | * struct imx_dma_channel - i.MX specific DMA extension | ||
30 | * @name: name specified by DMA client | ||
31 | * @irq_handler: client callback for end of transfer | ||
32 | * @err_handler: client callback for error condition | ||
33 | * @data: clients context data for callbacks | ||
34 | * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE | ||
35 | * @sg: pointer to the actual read/written chunk for scatter-gather emulation | ||
36 | * @sgbc: counter of processed bytes in the actual read/written chunk | ||
37 | * @resbytes: total residual number of bytes to transfer | ||
38 | * (it can be lower or same as sum of SG mapped chunk sizes) | ||
39 | * @sgcount: number of chunks to be read/written | ||
40 | * | ||
41 | * Structure is used for IMX DMA processing. It would be probably good | ||
42 | * @struct dma_struct in the future for external interfacing and use | ||
43 | * @struct imx_dma_channel only as extension to it. | ||
44 | */ | ||
45 | |||
46 | struct imx_dma_channel { | ||
47 | const char *name; | ||
48 | void (*irq_handler) (int, void *, struct pt_regs *); | ||
49 | void (*err_handler) (int, void *, struct pt_regs *); | ||
50 | void *data; | ||
51 | dmamode_t dma_mode; | ||
52 | struct scatterlist *sg; | ||
53 | unsigned int sgbc; | ||
54 | unsigned int sgcount; | ||
55 | unsigned int resbytes; | ||
56 | int dma_num; | ||
57 | }; | ||
58 | |||
59 | extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; | ||
60 | |||
61 | |||
62 | /* The type to distinguish channel numbers parameter from ordinal int type */ | ||
63 | typedef int imx_dmach_t; | ||
64 | |||
65 | int | ||
66 | imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, | ||
67 | unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode); | ||
68 | |||
69 | int | ||
70 | imx_dma_setup_sg(imx_dmach_t dma_ch, | ||
71 | struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, | ||
72 | unsigned int dev_addr, dmamode_t dmamode); | ||
73 | |||
74 | int | ||
75 | imx_dma_setup_handlers(imx_dmach_t dma_ch, | ||
76 | void (*irq_handler) (int, void *, struct pt_regs *), | ||
77 | void (*err_handler) (int, void *, struct pt_regs *), void *data); | ||
78 | |||
79 | void imx_dma_enable(imx_dmach_t dma_ch); | ||
80 | |||
81 | void imx_dma_disable(imx_dmach_t dma_ch); | ||
82 | |||
83 | int imx_dma_request(imx_dmach_t dma_ch, const char *name); | ||
84 | |||
85 | void imx_dma_free(imx_dmach_t dma_ch); | ||
86 | |||
87 | int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio); | ||
88 | |||
89 | |||
90 | #endif /* _ASM_ARCH_IMX_DMA_H */ | ||
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h index bebcf0aa0d72..6e19f46d54d1 100644 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ b/include/asm-arm/arch-ixp23xx/memory.h | |||
@@ -28,6 +28,7 @@ | |||
28 | * to an address that the kernel can use. | 28 | * to an address that the kernel can use. |
29 | */ | 29 | */ |
30 | #ifndef __ASSEMBLY__ | 30 | #ifndef __ASSEMBLY__ |
31 | #include <asm/mach-types.h> | ||
31 | 32 | ||
32 | #define __virt_to_bus(v) \ | 33 | #define __virt_to_bus(v) \ |
33 | ({ unsigned int ret; \ | 34 | ({ unsigned int ret; \ |
@@ -40,6 +41,22 @@ | |||
40 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ | 41 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ |
41 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) | 42 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) |
42 | 43 | ||
44 | /* | ||
45 | * Coherency support. Only supported on A2 CPUs or on A1 | ||
46 | * systems that have the cache coherency workaround. | ||
47 | */ | ||
48 | static inline int __ixp23xx_arch_is_coherent(void) | ||
49 | { | ||
50 | extern unsigned int processor_id; | ||
51 | |||
52 | if (((processor_id & 15) >= 2) || machine_is_roadrunner()) | ||
53 | return 1; | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | #define arch_is_coherent() __ixp23xx_arch_is_coherent() | ||
59 | |||
43 | #endif | 60 | #endif |
44 | 61 | ||
45 | 62 | ||
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h index f85b4685a491..e4d99060a049 100644 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ b/include/asm-arm/arch-ixp23xx/platform.h | |||
@@ -22,6 +22,7 @@ void ixp23xx_sys_init(void); | |||
22 | int ixp23xx_pci_setup(int, struct pci_sys_data *); | 22 | int ixp23xx_pci_setup(int, struct pci_sys_data *); |
23 | void ixp23xx_pci_preinit(void); | 23 | void ixp23xx_pci_preinit(void); |
24 | struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); | 24 | struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); |
25 | void ixp23xx_pci_slave_init(void); | ||
25 | 26 | ||
26 | extern struct sys_timer ixp23xx_timer; | 27 | extern struct sys_timer ixp23xx_timer; |
27 | 28 | ||
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h index 590bac25b7c4..6513065941d0 100644 --- a/include/asm-arm/arch-omap/aic23.h +++ b/include/asm-arm/arch-omap/aic23.h | |||
@@ -57,6 +57,7 @@ | |||
57 | #define LHV_MIN 0x0000 | 57 | #define LHV_MIN 0x0000 |
58 | 58 | ||
59 | // Analog audio path control register | 59 | // Analog audio path control register |
60 | #define STA_REG(x) ((x)<<6) | ||
60 | #define STE_ENABLED 0x0020 | 61 | #define STE_ENABLED 0x0020 |
61 | #define DAC_SELECTED 0x0010 | 62 | #define DAC_SELECTED 0x0010 |
62 | #define BYPASS_ON 0x0008 | 63 | #define BYPASS_ON 0x0008 |
@@ -109,4 +110,7 @@ | |||
109 | #define TLV320AIC23ID1 (0x1a) // cs low | 110 | #define TLV320AIC23ID1 (0x1a) // cs low |
110 | #define TLV320AIC23ID2 (0x1b) // cs high | 111 | #define TLV320AIC23ID2 (0x1b) // cs high |
111 | 112 | ||
113 | void tlv320aic23_power_up(void); | ||
114 | void tlv320aic23_power_down(void); | ||
115 | |||
112 | #endif /* __ASM_ARCH_AIC23_H */ | 116 | #endif /* __ASM_ARCH_AIC23_H */ |
diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h new file mode 100644 index 000000000000..0070f6d3b75c --- /dev/null +++ b/include/asm-arm/arch-omap/board-ams-delta.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/board-ams-delta.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | */ | ||
26 | #ifndef __ASM_ARCH_OMAP_AMS_DELTA_H | ||
27 | #define __ASM_ARCH_OMAP_AMS_DELTA_H | ||
28 | |||
29 | #if defined (CONFIG_MACH_AMS_DELTA) | ||
30 | |||
31 | #define AMS_DELTA_LATCH1_PHYS 0x01000000 | ||
32 | #define AMS_DELTA_LATCH1_VIRT 0xEA000000 | ||
33 | #define AMS_DELTA_MODEM_PHYS 0x04000000 | ||
34 | #define AMS_DELTA_MODEM_VIRT 0xEB000000 | ||
35 | #define AMS_DELTA_LATCH2_PHYS 0x08000000 | ||
36 | #define AMS_DELTA_LATCH2_VIRT 0xEC000000 | ||
37 | |||
38 | #define AMS_DELTA_LATCH1_LED_CAMERA 0x01 | ||
39 | #define AMS_DELTA_LATCH1_LED_ADVERT 0x02 | ||
40 | #define AMS_DELTA_LATCH1_LED_EMAIL 0x04 | ||
41 | #define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08 | ||
42 | #define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10 | ||
43 | #define AMS_DELTA_LATCH1_LED_VOICE 0x20 | ||
44 | |||
45 | #define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001 | ||
46 | #define AMS_DELTA_LATCH2_LCD_NDISP 0x0002 | ||
47 | #define AMS_DELTA_LATCH2_NAND_NCE 0x0004 | ||
48 | #define AMS_DELTA_LATCH2_NAND_NRE 0x0008 | ||
49 | #define AMS_DELTA_LATCH2_NAND_NWP 0x0010 | ||
50 | #define AMS_DELTA_LATCH2_NAND_NWE 0x0020 | ||
51 | #define AMS_DELTA_LATCH2_NAND_ALE 0x0040 | ||
52 | #define AMS_DELTA_LATCH2_NAND_CLE 0x0080 | ||
53 | #define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000 | ||
54 | #define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 | ||
55 | |||
56 | #define AMS_DELTA_GPIO_PIN_NAND_RB 12 | ||
57 | |||
58 | #ifndef __ASSEMBLY__ | ||
59 | void ams_delta_latch1_write(u8 mask, u8 value); | ||
60 | void ams_delta_latch2_write(u16 mask, u16 value); | ||
61 | #endif | ||
62 | |||
63 | #endif /* CONFIG_MACH_AMS_DELTA */ | ||
64 | |||
65 | #endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h new file mode 100644 index 000000000000..de0c5b792c58 --- /dev/null +++ b/include/asm-arm/arch-omap/board-apollon.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/board-apollon.h | ||
3 | * | ||
4 | * Hardware definitions for Samsung OMAP24XX Apollon board. | ||
5 | * | ||
6 | * Initial creation by Kyungmin Park <kyungmin.park@samsung.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License along | ||
25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
27 | */ | ||
28 | |||
29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H | ||
30 | #define __ASM_ARCH_OMAP_APOLLON_H | ||
31 | |||
32 | /* Placeholder for APOLLON specific defines */ | ||
33 | /* GPMC CS0 */ | ||
34 | #define APOLLON_CS0_BASE 0x00000000 | ||
35 | /* GPMC CS1 */ | ||
36 | #define APOLLON_CS1_BASE 0x08000000 | ||
37 | #define APOLLON_ETHR_START (APOLLON_CS1_BASE + 0x300) | ||
38 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
39 | /* GPMC CS2 - reserved for OneNAND */ | ||
40 | #define APOLLON_CS2_BASE 0x10000000 | ||
41 | /* GPMC CS3 - reserved for NOR or NAND */ | ||
42 | #define APOLLON_CS3_BASE 0x18000000 | ||
43 | |||
44 | #endif /* __ASM_ARCH_OMAP_APOLLON_H */ | ||
45 | |||
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h index 39ca5a31aeea..b2888ef9e9b4 100644 --- a/include/asm-arm/arch-omap/board-h2.h +++ b/include/asm-arm/arch-omap/board-h2.h | |||
@@ -34,9 +34,5 @@ | |||
34 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | 34 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ |
35 | #define OMAP1610_ETHR_START 0x04000300 | 35 | #define OMAP1610_ETHR_START 0x04000300 |
36 | 36 | ||
37 | /* Samsung NAND flash at CS2B or CS3(NAND Boot) */ | ||
38 | #define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ | ||
39 | #define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ | ||
40 | |||
41 | #endif /* __ASM_ARCH_OMAP_H2_H */ | 37 | #endif /* __ASM_ARCH_OMAP_H2_H */ |
42 | 38 | ||
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h index 1b12c1dcc2fa..761ea0a17897 100644 --- a/include/asm-arm/arch-omap/board-h3.h +++ b/include/asm-arm/arch-omap/board-h3.h | |||
@@ -30,10 +30,6 @@ | |||
30 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | 30 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ |
31 | #define OMAP1710_ETHR_START 0x04000300 | 31 | #define OMAP1710_ETHR_START 0x04000300 |
32 | 32 | ||
33 | /* Samsung NAND flash at CS2B or CS3(NAND Boot) */ | ||
34 | #define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ | ||
35 | #define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ | ||
36 | |||
37 | #define MAXIRQNUM (IH_BOARD_BASE) | 33 | #define MAXIRQNUM (IH_BOARD_BASE) |
38 | #define MAXFIQNUM MAXIRQNUM | 34 | #define MAXFIQNUM MAXIRQNUM |
39 | #define MAXSWINUM MAXIRQNUM | 35 | #define MAXSWINUM MAXIRQNUM |
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h index 33ea29a41654..7ef664bc9e33 100644 --- a/include/asm-arm/arch-omap/board-h4.h +++ b/include/asm-arm/arch-omap/board-h4.h | |||
@@ -33,12 +33,6 @@ | |||
33 | /* GPMC CS1 */ | 33 | /* GPMC CS1 */ |
34 | #define OMAP24XX_ETHR_START 0x08000300 | 34 | #define OMAP24XX_ETHR_START 0x08000300 |
35 | #define OMAP24XX_ETHR_GPIO_IRQ 92 | 35 | #define OMAP24XX_ETHR_GPIO_IRQ 92 |
36 | 36 | #define H4_CS0_BASE 0x04000000 | |
37 | #define H4_CS0_BASE 0x04000000 | ||
38 | |||
39 | #define H4_CS0_BASE 0x04000000 | ||
40 | |||
41 | #define H4_CS0_BASE 0x04000000 | ||
42 | |||
43 | #endif /* __ASM_ARCH_OMAP_H4_H */ | 37 | #endif /* __ASM_ARCH_OMAP_H4_H */ |
44 | 38 | ||
diff --git a/include/asm-arm/arch-omap/board-netstar.h b/include/asm-arm/arch-omap/board-netstar.h deleted file mode 100644 index 77cc0fb54d54..000000000000 --- a/include/asm-arm/arch-omap/board-netstar.h +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz> | ||
3 | * | ||
4 | * Hardware definitions for OMAP5910 based NetStar board. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_NETSTAR_H | ||
12 | #define __ASM_ARCH_NETSTAR_H | ||
13 | |||
14 | #include <asm/arch/tc.h> | ||
15 | |||
16 | #define OMAP_NAND_FLASH_START1 OMAP_CS1_PHYS + (1 << 23) | ||
17 | #define OMAP_NAND_FLASH_START2 OMAP_CS1_PHYS + (2 << 23) | ||
18 | |||
19 | #endif /* __ASM_ARCH_NETSTAR_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-nokia.h b/include/asm-arm/arch-omap/board-nokia.h new file mode 100644 index 000000000000..72deea203493 --- /dev/null +++ b/include/asm-arm/arch-omap/board-nokia.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/board-nokia.h | ||
3 | * | ||
4 | * Information structures for Nokia-specific board config data | ||
5 | * | ||
6 | * Copyright (C) 2005 Nokia Corporation | ||
7 | */ | ||
8 | |||
9 | #ifndef _OMAP_BOARD_NOKIA_H | ||
10 | #define _OMAP_BOARD_NOKIA_H | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | |||
14 | #define OMAP_TAG_NOKIA_BT 0x4e01 | ||
15 | #define OMAP_TAG_WLAN_CX3110X 0x4e02 | ||
16 | #define OMAP_TAG_CBUS 0x4e03 | ||
17 | #define OMAP_TAG_EM_ASIC_BB5 0x4e04 | ||
18 | |||
19 | |||
20 | #define BT_CHIP_CSR 1 | ||
21 | #define BT_CHIP_TI 2 | ||
22 | |||
23 | #define BT_SYSCLK_12 1 | ||
24 | #define BT_SYSCLK_38_4 2 | ||
25 | |||
26 | struct omap_bluetooth_config { | ||
27 | u8 chip_type; | ||
28 | u8 bt_wakeup_gpio; | ||
29 | u8 host_wakeup_gpio; | ||
30 | u8 reset_gpio; | ||
31 | u8 bt_uart; | ||
32 | u8 bd_addr[6]; | ||
33 | u8 bt_sysclk; | ||
34 | }; | ||
35 | |||
36 | struct omap_wlan_cx3110x_config { | ||
37 | u8 chip_type; | ||
38 | s16 power_gpio; | ||
39 | s16 irq_gpio; | ||
40 | s16 spi_cs_gpio; | ||
41 | }; | ||
42 | |||
43 | struct omap_cbus_config { | ||
44 | s16 clk_gpio; | ||
45 | s16 dat_gpio; | ||
46 | s16 sel_gpio; | ||
47 | }; | ||
48 | |||
49 | struct omap_em_asic_bb5_config { | ||
50 | s16 retu_irq_gpio; | ||
51 | s16 tahvo_irq_gpio; | ||
52 | }; | ||
53 | |||
54 | #endif | ||
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h index 691e52a52b43..eb74420cb439 100644 --- a/include/asm-arm/arch-omap/board-perseus2.h +++ b/include/asm-arm/arch-omap/board-perseus2.h | |||
@@ -42,8 +42,4 @@ | |||
42 | 42 | ||
43 | #define NR_IRQS (MAXIRQNUM + 1) | 43 | #define NR_IRQS (MAXIRQNUM + 1) |
44 | 44 | ||
45 | /* Samsung NAND flash at CS2B or CS3(NAND Boot) */ | ||
46 | #define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ | ||
47 | #define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ | ||
48 | |||
49 | #endif | 45 | #endif |
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h index a0040cd86639..6d6240a4681c 100644 --- a/include/asm-arm/arch-omap/board.h +++ b/include/asm-arm/arch-omap/board.h | |||
@@ -21,9 +21,12 @@ | |||
21 | #define OMAP_TAG_LCD 0x4f05 | 21 | #define OMAP_TAG_LCD 0x4f05 |
22 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 | 22 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
23 | #define OMAP_TAG_UART 0x4f07 | 23 | #define OMAP_TAG_UART 0x4f07 |
24 | #define OMAP_TAG_FBMEM 0x4f08 | ||
25 | #define OMAP_TAG_STI_CONSOLE 0x4f09 | ||
24 | 26 | ||
25 | #define OMAP_TAG_BOOT_REASON 0x4f80 | 27 | #define OMAP_TAG_BOOT_REASON 0x4f80 |
26 | #define OMAP_TAG_FLASH_PART 0x4f81 | 28 | #define OMAP_TAG_FLASH_PART 0x4f81 |
29 | #define OMAP_TAG_VERSION_STR 0x4f82 | ||
27 | 30 | ||
28 | struct omap_clock_config { | 31 | struct omap_clock_config { |
29 | /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ | 32 | /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ |
@@ -54,6 +57,11 @@ struct omap_serial_console_config { | |||
54 | u32 console_speed; | 57 | u32 console_speed; |
55 | }; | 58 | }; |
56 | 59 | ||
60 | struct omap_sti_console_config { | ||
61 | unsigned enable:1; | ||
62 | u8 channel; | ||
63 | }; | ||
64 | |||
57 | struct omap_usb_config { | 65 | struct omap_usb_config { |
58 | /* Configure drivers according to the connectors on your board: | 66 | /* Configure drivers according to the connectors on your board: |
59 | * - "A" connector (rectagular) | 67 | * - "A" connector (rectagular) |
@@ -87,6 +95,13 @@ struct omap_lcd_config { | |||
87 | char ctrl_name[16]; | 95 | char ctrl_name[16]; |
88 | }; | 96 | }; |
89 | 97 | ||
98 | struct omap_fbmem_config { | ||
99 | u32 fb_sram_start; | ||
100 | u32 fb_sram_size; | ||
101 | u32 fb_sdram_start; | ||
102 | u32 fb_sdram_size; | ||
103 | }; | ||
104 | |||
90 | /* Cover: | 105 | /* Cover: |
91 | * high -> closed | 106 | * high -> closed |
92 | * low -> open | 107 | * low -> open |
@@ -106,6 +121,12 @@ struct omap_gpio_switch_config { | |||
106 | int key_code:24; /* Linux key code */ | 121 | int key_code:24; /* Linux key code */ |
107 | }; | 122 | }; |
108 | 123 | ||
124 | struct omap_uart_config { | ||
125 | /* Bit field of UARTs present; bit 0 --> UART1 */ | ||
126 | unsigned int enabled_uarts; | ||
127 | }; | ||
128 | |||
129 | |||
109 | struct omap_flash_part_config { | 130 | struct omap_flash_part_config { |
110 | char part_table[0]; | 131 | char part_table[0]; |
111 | }; | 132 | }; |
@@ -114,11 +135,14 @@ struct omap_boot_reason_config { | |||
114 | char reason_str[12]; | 135 | char reason_str[12]; |
115 | }; | 136 | }; |
116 | 137 | ||
117 | struct omap_uart_config { | 138 | struct omap_version_config { |
118 | /* Bit field of UARTs present; bit 0 --> UART1 */ | 139 | char component[12]; |
119 | unsigned int enabled_uarts; | 140 | char version[12]; |
120 | }; | 141 | }; |
121 | 142 | ||
143 | |||
144 | #include <asm-arm/arch-omap/board-nokia.h> | ||
145 | |||
122 | struct omap_board_config_entry { | 146 | struct omap_board_config_entry { |
123 | u16 tag; | 147 | u16 tag; |
124 | u16 len; | 148 | u16 len; |
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 46a0402696de..3c4eb9fbe48a 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h | |||
@@ -19,6 +19,7 @@ struct clk { | |||
19 | struct list_head node; | 19 | struct list_head node; |
20 | struct module *owner; | 20 | struct module *owner; |
21 | const char *name; | 21 | const char *name; |
22 | int id; | ||
22 | struct clk *parent; | 23 | struct clk *parent; |
23 | unsigned long rate; | 24 | unsigned long rate; |
24 | __u32 flags; | 25 | __u32 flags; |
@@ -57,6 +58,7 @@ extern void propagate_rate(struct clk *clk); | |||
57 | extern void followparent_recalc(struct clk * clk); | 58 | extern void followparent_recalc(struct clk * clk); |
58 | extern void clk_allow_idle(struct clk *clk); | 59 | extern void clk_allow_idle(struct clk *clk); |
59 | extern void clk_deny_idle(struct clk *clk); | 60 | extern void clk_deny_idle(struct clk *clk); |
61 | extern int clk_get_usecount(struct clk *clk); | ||
60 | 62 | ||
61 | /* Clock flags */ | 63 | /* Clock flags */ |
62 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | 64 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ |
@@ -80,10 +82,11 @@ extern void clk_deny_idle(struct clk *clk); | |||
80 | #define CM_PLL_SEL1 (1 << 18) | 82 | #define CM_PLL_SEL1 (1 << 18) |
81 | #define CM_PLL_SEL2 (1 << 19) | 83 | #define CM_PLL_SEL2 (1 << 19) |
82 | #define CM_SYSCLKOUT_SEL1 (1 << 20) | 84 | #define CM_SYSCLKOUT_SEL1 (1 << 20) |
83 | #define CLOCK_IN_OMAP730 (1 << 21) | 85 | #define CLOCK_IN_OMAP310 (1 << 21) |
84 | #define CLOCK_IN_OMAP1510 (1 << 22) | 86 | #define CLOCK_IN_OMAP730 (1 << 22) |
85 | #define CLOCK_IN_OMAP16XX (1 << 23) | 87 | #define CLOCK_IN_OMAP1510 (1 << 23) |
86 | #define CLOCK_IN_OMAP242X (1 << 24) | 88 | #define CLOCK_IN_OMAP16XX (1 << 24) |
87 | #define CLOCK_IN_OMAP243X (1 << 25) | 89 | #define CLOCK_IN_OMAP242X (1 << 25) |
90 | #define CLOCK_IN_OMAP243X (1 << 26) | ||
88 | 91 | ||
89 | #endif | 92 | #endif |
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index d4e73efcb816..ca1202312a45 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h | |||
@@ -404,6 +404,7 @@ extern void omap_free_lcd_dma(void); | |||
404 | extern void omap_setup_lcd_dma(void); | 404 | extern void omap_setup_lcd_dma(void); |
405 | extern void omap_enable_lcd_dma(void); | 405 | extern void omap_enable_lcd_dma(void); |
406 | extern void omap_stop_lcd_dma(void); | 406 | extern void omap_stop_lcd_dma(void); |
407 | extern int omap_lcd_dma_ext_running(void); | ||
407 | extern void omap_set_lcd_dma_ext_controller(int external); | 408 | extern void omap_set_lcd_dma_ext_controller(int external); |
408 | extern void omap_set_lcd_dma_single_transfer(int single); | 409 | extern void omap_set_lcd_dma_single_transfer(int single); |
409 | extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | 410 | extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, |
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h index 11772c792f3e..e6522e6a3834 100644 --- a/include/asm-arm/arch-omap/dmtimer.h +++ b/include/asm-arm/arch-omap/dmtimer.h | |||
@@ -88,5 +88,6 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); | |||
88 | void omap_dm_timer_reset_counter(struct omap_dm_timer *timer); | 88 | void omap_dm_timer_reset_counter(struct omap_dm_timer *timer); |
89 | 89 | ||
90 | int omap_dm_timers_active(void); | 90 | int omap_dm_timers_active(void); |
91 | u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); | ||
91 | 92 | ||
92 | #endif /* __ASM_ARCH_TIMER_H */ | 93 | #endif /* __ASM_ARCH_TIMER_H */ |
diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h index 57bf4f39ca58..06dad83dd41f 100644 --- a/include/asm-arm/arch-omap/dsp.h +++ b/include/asm-arm/arch-omap/dsp.h | |||
@@ -181,10 +181,16 @@ struct omap_dsp_varinfo { | |||
181 | #define OMAP_DSP_MBCMD_PM_ENABLE 0x01 | 181 | #define OMAP_DSP_MBCMD_PM_ENABLE 0x01 |
182 | 182 | ||
183 | #define OMAP_DSP_MBCMD_KFUNC_FBCTL 0x00 | 183 | #define OMAP_DSP_MBCMD_KFUNC_FBCTL 0x00 |
184 | #define OMAP_DSP_MBCMD_KFUNC_AUDIO_PWR 0x01 | ||
184 | 185 | ||
186 | #define OMAP_DSP_MBCMD_FBCTL_UPD 0x0000 | ||
185 | #define OMAP_DSP_MBCMD_FBCTL_ENABLE 0x0002 | 187 | #define OMAP_DSP_MBCMD_FBCTL_ENABLE 0x0002 |
186 | #define OMAP_DSP_MBCMD_FBCTL_DISABLE 0x0003 | 188 | #define OMAP_DSP_MBCMD_FBCTL_DISABLE 0x0003 |
187 | 189 | ||
190 | #define OMAP_DSP_MBCMD_AUDIO_PWR_UP 0x0000 | ||
191 | #define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN1 0x0001 | ||
192 | #define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN2 0x0002 | ||
193 | |||
188 | #define OMAP_DSP_MBCMD_TDEL_SAFE 0x0000 | 194 | #define OMAP_DSP_MBCMD_TDEL_SAFE 0x0000 |
189 | #define OMAP_DSP_MBCMD_TDEL_KILL 0x0001 | 195 | #define OMAP_DSP_MBCMD_TDEL_KILL 0x0001 |
190 | 196 | ||
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h index 4fcce6944056..16a459dfa714 100644 --- a/include/asm-arm/arch-omap/dsp_common.h +++ b/include/asm-arm/arch-omap/dsp_common.h | |||
@@ -27,11 +27,12 @@ | |||
27 | #ifndef ASM_ARCH_DSP_COMMON_H | 27 | #ifndef ASM_ARCH_DSP_COMMON_H |
28 | #define ASM_ARCH_DSP_COMMON_H | 28 | #define ASM_ARCH_DSP_COMMON_H |
29 | 29 | ||
30 | void omap_dsp_pm_suspend(void); | 30 | extern void omap_dsp_request_mpui(void); |
31 | void omap_dsp_pm_resume(void); | 31 | extern void omap_dsp_release_mpui(void); |
32 | void omap_dsp_request_mpui(void); | 32 | extern int omap_dsp_request_mem(void); |
33 | void omap_dsp_release_mpui(void); | 33 | extern int omap_dsp_release_mem(void); |
34 | int omap_dsp_request_mem(void); | 34 | |
35 | int omap_dsp_release_mem(void); | 35 | extern void (*omap_dsp_audio_pwr_up_request)(int stage); |
36 | extern void (*omap_dsp_audio_pwr_down_request)(int stage); | ||
36 | 37 | ||
37 | #endif /* ASM_ARCH_DSP_COMMON_H */ | 38 | #endif /* ASM_ARCH_DSP_COMMON_H */ |
diff --git a/include/asm-arm/arch-omap/gpioexpander.h b/include/asm-arm/arch-omap/gpioexpander.h new file mode 100644 index 000000000000..7a43b0a912e4 --- /dev/null +++ b/include/asm-arm/arch-omap/gpioexpander.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/gpioexpander.h | ||
3 | * | ||
4 | * | ||
5 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
6 | * | ||
7 | * This package is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | ||
12 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | ||
13 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H | ||
17 | #define __ASM_ARCH_OMAP_GPIOEXPANDER_H | ||
18 | |||
19 | /* Function Prototypes for GPIO Expander functions */ | ||
20 | |||
21 | int read_gpio_expa(u8 *, int); | ||
22 | int write_gpio_expa(u8 , int); | ||
23 | |||
24 | #endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */ | ||
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 5406b875c422..7909b729826c 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h | |||
@@ -306,6 +306,10 @@ | |||
306 | #include "board-h4.h" | 306 | #include "board-h4.h" |
307 | #endif | 307 | #endif |
308 | 308 | ||
309 | #ifdef CONFIG_MACH_OMAP_APOLLON | ||
310 | #include "board-apollon.h" | ||
311 | #endif | ||
312 | |||
309 | #ifdef CONFIG_MACH_OMAP_OSK | 313 | #ifdef CONFIG_MACH_OMAP_OSK |
310 | #include "board-osk.h" | 314 | #include "board-osk.h" |
311 | #endif | 315 | #endif |
@@ -314,10 +318,6 @@ | |||
314 | #include "board-voiceblue.h" | 318 | #include "board-voiceblue.h" |
315 | #endif | 319 | #endif |
316 | 320 | ||
317 | #ifdef CONFIG_MACH_NETSTAR | ||
318 | #include "board-netstar.h" | ||
319 | #endif | ||
320 | |||
321 | #endif /* !__ASSEMBLER__ */ | 321 | #endif /* !__ASSEMBLER__ */ |
322 | 322 | ||
323 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | 323 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ |
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h new file mode 100644 index 000000000000..805ae3575e44 --- /dev/null +++ b/include/asm-arm/arch-omap/irda.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/irda.h | ||
3 | * | ||
4 | * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef ASMARM_ARCH_IRDA_H | ||
11 | #define ASMARM_ARCH_IRDA_H | ||
12 | |||
13 | /* board specific transceiver capabilities */ | ||
14 | |||
15 | #define IR_SEL 1 /* Selects IrDA */ | ||
16 | #define IR_SIRMODE 2 | ||
17 | #define IR_FIRMODE 4 | ||
18 | #define IR_MIRMODE 8 | ||
19 | |||
20 | struct omap_irda_config { | ||
21 | int transceiver_cap; | ||
22 | int (*transceiver_mode)(struct device *dev, int mode); | ||
23 | int (*select_irda)(struct device *dev, int state); | ||
24 | /* Very specific to the needs of some platforms (h3,h4) | ||
25 | * having calls which can sleep in irda_set_speed. | ||
26 | */ | ||
27 | struct work_struct gpio_expa; | ||
28 | int rx_channel; | ||
29 | int tx_channel; | ||
30 | unsigned long dest_start; | ||
31 | unsigned long src_start; | ||
32 | int tx_trigger; | ||
33 | int rx_trigger; | ||
34 | }; | ||
35 | |||
36 | #endif | ||
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 4ffce1d77759..42098d99f302 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h | |||
@@ -242,6 +242,11 @@ | |||
242 | #define INT_24XX_GPIO_BANK2 30 | 242 | #define INT_24XX_GPIO_BANK2 30 |
243 | #define INT_24XX_GPIO_BANK3 31 | 243 | #define INT_24XX_GPIO_BANK3 31 |
244 | #define INT_24XX_GPIO_BANK4 32 | 244 | #define INT_24XX_GPIO_BANK4 32 |
245 | #define INT_24XX_MCBSP1_IRQ_TX 59 | ||
246 | #define INT_24XX_MCBSP1_IRQ_RX 60 | ||
247 | #define INT_24XX_MCBSP2_IRQ_TX 62 | ||
248 | #define INT_24XX_MCBSP2_IRQ_RX 63 | ||
249 | #define INT_24XX_UART3_IRQ 74 | ||
245 | 250 | ||
246 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and | 251 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and |
247 | * 16 MPUIO lines */ | 252 | * 16 MPUIO lines */ |
diff --git a/include/asm-arm/arch-omap/keypad.h b/include/asm-arm/arch-omap/keypad.h new file mode 100644 index 000000000000..8a023a984acb --- /dev/null +++ b/include/asm-arm/arch-omap/keypad.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/keypad.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef ASMARM_ARCH_KEYPAD_H | ||
11 | #define ASMARM_ARCH_KEYPAD_H | ||
12 | |||
13 | struct omap_kp_platform_data { | ||
14 | int rows; | ||
15 | int cols; | ||
16 | int *keymap; | ||
17 | unsigned int rep:1; | ||
18 | /* specific to OMAP242x*/ | ||
19 | unsigned int *row_gpios; | ||
20 | unsigned int *col_gpios; | ||
21 | }; | ||
22 | |||
23 | /* Group (0..3) -- when multiple keys are pressed, only the | ||
24 | * keys pressed in the same group are considered as pressed. This is | ||
25 | * in order to workaround certain crappy HW designs that produce ghost | ||
26 | * keypresses. */ | ||
27 | #define GROUP_0 (0 << 16) | ||
28 | #define GROUP_1 (1 << 16) | ||
29 | #define GROUP_2 (2 << 16) | ||
30 | #define GROUP_3 (3 << 16) | ||
31 | #define GROUP_MASK GROUP_3 | ||
32 | |||
33 | #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) | ||
34 | |||
35 | #endif | ||
36 | |||
diff --git a/include/asm-arm/arch-omap/lcd_lph8923.h b/include/asm-arm/arch-omap/lcd_lph8923.h new file mode 100644 index 000000000000..004e67e22ca7 --- /dev/null +++ b/include/asm-arm/arch-omap/lcd_lph8923.h | |||
@@ -0,0 +1,14 @@ | |||
1 | #ifndef __LCD_LPH8923_H | ||
2 | #define __LCD_LPH8923_H | ||
3 | |||
4 | enum lcd_lph8923_test_num { | ||
5 | LCD_LPH8923_TEST_RGB_LINES, | ||
6 | }; | ||
7 | |||
8 | enum lcd_lph8923_test_result { | ||
9 | LCD_LPH8923_TEST_SUCCESS, | ||
10 | LCD_LPH8923_TEST_INVALID, | ||
11 | LCD_LPH8923_TEST_FAILED, | ||
12 | }; | ||
13 | |||
14 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h index e79d98ab2ab6..ed0dde4f7219 100644 --- a/include/asm-arm/arch-omap/mcbsp.h +++ b/include/asm-arm/arch-omap/mcbsp.h | |||
@@ -37,6 +37,11 @@ | |||
37 | #define OMAP1610_MCBSP2_BASE 0xfffb1000 | 37 | #define OMAP1610_MCBSP2_BASE 0xfffb1000 |
38 | #define OMAP1610_MCBSP3_BASE 0xe1017000 | 38 | #define OMAP1610_MCBSP3_BASE 0xe1017000 |
39 | 39 | ||
40 | #define OMAP24XX_MCBSP1_BASE 0x48074000 | ||
41 | #define OMAP24XX_MCBSP2_BASE 0x48076000 | ||
42 | |||
43 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) | ||
44 | |||
40 | #define OMAP_MCBSP_REG_DRR2 0x00 | 45 | #define OMAP_MCBSP_REG_DRR2 0x00 |
41 | #define OMAP_MCBSP_REG_DRR1 0x02 | 46 | #define OMAP_MCBSP_REG_DRR1 0x02 |
42 | #define OMAP_MCBSP_REG_DXR2 0x04 | 47 | #define OMAP_MCBSP_REG_DXR2 0x04 |
@@ -71,9 +76,62 @@ | |||
71 | 76 | ||
72 | #define OMAP_MAX_MCBSP_COUNT 3 | 77 | #define OMAP_MAX_MCBSP_COUNT 3 |
73 | 78 | ||
79 | #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) | ||
80 | #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) | ||
81 | |||
82 | #define AUDIO_MCBSP OMAP_MCBSP1 | ||
83 | #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX | ||
84 | #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX | ||
85 | |||
86 | #elif defined(CONFIG_ARCH_OMAP24XX) | ||
87 | |||
88 | #define OMAP_MCBSP_REG_DRR2 0x00 | ||
89 | #define OMAP_MCBSP_REG_DRR1 0x04 | ||
90 | #define OMAP_MCBSP_REG_DXR2 0x08 | ||
91 | #define OMAP_MCBSP_REG_DXR1 0x0C | ||
92 | #define OMAP_MCBSP_REG_SPCR2 0x10 | ||
93 | #define OMAP_MCBSP_REG_SPCR1 0x14 | ||
94 | #define OMAP_MCBSP_REG_RCR2 0x18 | ||
95 | #define OMAP_MCBSP_REG_RCR1 0x1C | ||
96 | #define OMAP_MCBSP_REG_XCR2 0x20 | ||
97 | #define OMAP_MCBSP_REG_XCR1 0x24 | ||
98 | #define OMAP_MCBSP_REG_SRGR2 0x28 | ||
99 | #define OMAP_MCBSP_REG_SRGR1 0x2C | ||
100 | #define OMAP_MCBSP_REG_MCR2 0x30 | ||
101 | #define OMAP_MCBSP_REG_MCR1 0x34 | ||
102 | #define OMAP_MCBSP_REG_RCERA 0x38 | ||
103 | #define OMAP_MCBSP_REG_RCERB 0x3C | ||
104 | #define OMAP_MCBSP_REG_XCERA 0x40 | ||
105 | #define OMAP_MCBSP_REG_XCERB 0x44 | ||
106 | #define OMAP_MCBSP_REG_PCR0 0x48 | ||
107 | #define OMAP_MCBSP_REG_RCERC 0x4C | ||
108 | #define OMAP_MCBSP_REG_RCERD 0x50 | ||
109 | #define OMAP_MCBSP_REG_XCERC 0x54 | ||
110 | #define OMAP_MCBSP_REG_XCERD 0x58 | ||
111 | #define OMAP_MCBSP_REG_RCERE 0x5C | ||
112 | #define OMAP_MCBSP_REG_RCERF 0x60 | ||
113 | #define OMAP_MCBSP_REG_XCERE 0x64 | ||
114 | #define OMAP_MCBSP_REG_XCERF 0x68 | ||
115 | #define OMAP_MCBSP_REG_RCERG 0x6C | ||
116 | #define OMAP_MCBSP_REG_RCERH 0x70 | ||
117 | #define OMAP_MCBSP_REG_XCERG 0x74 | ||
118 | #define OMAP_MCBSP_REG_XCERH 0x78 | ||
119 | |||
120 | #define OMAP_MAX_MCBSP_COUNT 2 | ||
121 | |||
122 | #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) | ||
123 | #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) | ||
124 | |||
125 | #define AUDIO_MCBSP OMAP_MCBSP2 | ||
126 | #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX | ||
127 | #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX | ||
128 | |||
129 | #endif | ||
130 | |||
74 | #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg) | 131 | #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg) |
75 | #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg) | 132 | #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg) |
76 | 133 | ||
134 | |||
77 | /************************** McBSP SPCR1 bit definitions ***********************/ | 135 | /************************** McBSP SPCR1 bit definitions ***********************/ |
78 | #define RRST 0x0001 | 136 | #define RRST 0x0001 |
79 | #define RRDY 0x0002 | 137 | #define RRDY 0x0002 |
@@ -195,6 +253,10 @@ typedef enum { | |||
195 | OMAP_MCBSP3, | 253 | OMAP_MCBSP3, |
196 | } omap_mcbsp_id; | 254 | } omap_mcbsp_id; |
197 | 255 | ||
256 | typedef int __bitwise omap_mcbsp_io_type_t; | ||
257 | #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1) | ||
258 | #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2) | ||
259 | |||
198 | typedef enum { | 260 | typedef enum { |
199 | OMAP_MCBSP_WORD_8 = 0, | 261 | OMAP_MCBSP_WORD_8 = 0, |
200 | OMAP_MCBSP_WORD_12, | 262 | OMAP_MCBSP_WORD_12, |
@@ -246,6 +308,9 @@ u32 omap_mcbsp_recv_word(unsigned int id); | |||
246 | 308 | ||
247 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | 309 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); |
248 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | 310 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); |
311 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); | ||
312 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); | ||
313 | |||
249 | 314 | ||
250 | /* SPI specific API */ | 315 | /* SPI specific API */ |
251 | void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); | 316 | void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); |
diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h new file mode 100644 index 000000000000..9e7f40a88e1b --- /dev/null +++ b/include/asm-arm/arch-omap/mcspi.h | |||
@@ -0,0 +1,16 @@ | |||
1 | #ifndef _OMAP2_MCSPI_H | ||
2 | #define _OMAP2_MCSPI_H | ||
3 | |||
4 | struct omap2_mcspi_platform_config { | ||
5 | unsigned long base; | ||
6 | unsigned short num_cs; | ||
7 | }; | ||
8 | |||
9 | struct omap2_mcspi_device_config { | ||
10 | unsigned turbo_mode:1; | ||
11 | |||
12 | /* Do we want one channel enabled at the same time? */ | ||
13 | unsigned single_channel:1; | ||
14 | }; | ||
15 | |||
16 | #endif | ||
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h index 46be8b8d6346..88cd4c87f0de 100644 --- a/include/asm-arm/arch-omap/menelaus.h +++ b/include/asm-arm/arch-omap/menelaus.h | |||
@@ -7,7 +7,7 @@ | |||
7 | #ifndef __ASM_ARCH_MENELAUS_H | 7 | #ifndef __ASM_ARCH_MENELAUS_H |
8 | #define __ASM_ARCH_MENELAUS_H | 8 | #define __ASM_ARCH_MENELAUS_H |
9 | 9 | ||
10 | extern void menelaus_mmc_register(void (*callback)(u8 card_mask), | 10 | extern void menelaus_mmc_register(void (*callback)(unsigned long data, u8 card_mask), |
11 | unsigned long data); | 11 | unsigned long data); |
12 | extern void menelaus_mmc_remove(void); | 12 | extern void menelaus_mmc_remove(void); |
13 | extern void menelaus_mmc_opendrain(int enable); | 13 | extern void menelaus_mmc_opendrain(int enable); |
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 13415a9aab06..0dc24d4ba59c 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h | |||
@@ -112,14 +112,13 @@ | |||
112 | * as mux config | 112 | * as mux config |
113 | */ | 113 | */ |
114 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ | 114 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ |
115 | pull_reg, pull_bit, pull_status, \ | 115 | pull_bit, pull_status, debug_status)\ |
116 | pu_pd_reg, pu_pd_status, debug_status)\ | ||
117 | { \ | 116 | { \ |
118 | .name = desc, \ | 117 | .name = desc, \ |
119 | .debug = debug_status, \ | 118 | .debug = debug_status, \ |
120 | MUX_REG_730(mux_reg, mode_offset, mode) \ | 119 | MUX_REG_730(mux_reg, mode_offset, mode) \ |
121 | PULL_REG_730(mux_reg, pull_bit, pull_status) \ | 120 | PULL_REG_730(mux_reg, pull_bit, pull_status) \ |
122 | PU_PD_REG(pu_pd_reg, pu_pd_status) \ | 121 | PU_PD_REG(NA, 0) \ |
123 | }, | 122 | }, |
124 | 123 | ||
125 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | 124 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ |
@@ -172,6 +171,11 @@ enum omap730_index { | |||
172 | E4_730_KBC2, | 171 | E4_730_KBC2, |
173 | F4_730_KBC3, | 172 | F4_730_KBC3, |
174 | E3_730_KBC4, | 173 | E3_730_KBC4, |
174 | |||
175 | /* USB */ | ||
176 | AA17_730_USB_DM, | ||
177 | W16_730_USB_PU_EN, | ||
178 | W17_730_USB_VBUSI, | ||
175 | }; | 179 | }; |
176 | 180 | ||
177 | enum omap1xxx_index { | 181 | enum omap1xxx_index { |
@@ -403,9 +407,53 @@ enum omap24xx_index { | |||
403 | /* 24xx Menelaus interrupt */ | 407 | /* 24xx Menelaus interrupt */ |
404 | W19_24XX_SYS_NIRQ, | 408 | W19_24XX_SYS_NIRQ, |
405 | 409 | ||
410 | /* 24xx clock */ | ||
411 | W14_24XX_SYS_CLKOUT, | ||
412 | |||
413 | /* 242X McBSP */ | ||
414 | Y15_24XX_MCBSP2_CLKX, | ||
415 | R14_24XX_MCBSP2_FSX, | ||
416 | W15_24XX_MCBSP2_DR, | ||
417 | V15_24XX_MCBSP2_DX, | ||
418 | |||
406 | /* 24xx GPIO */ | 419 | /* 24xx GPIO */ |
420 | M21_242X_GPIO11, | ||
421 | AA10_242X_GPIO13, | ||
422 | AA6_242X_GPIO14, | ||
423 | AA4_242X_GPIO15, | ||
424 | Y11_242X_GPIO16, | ||
425 | AA12_242X_GPIO17, | ||
426 | AA8_242X_GPIO58, | ||
407 | Y20_24XX_GPIO60, | 427 | Y20_24XX_GPIO60, |
428 | W4__24XX_GPIO74, | ||
408 | M15_24XX_GPIO92, | 429 | M15_24XX_GPIO92, |
430 | V14_24XX_GPIO117, | ||
431 | |||
432 | P20_24XX_TSC_IRQ, | ||
433 | |||
434 | /* UART3 */ | ||
435 | K15_24XX_UART3_TX, | ||
436 | K14_24XX_UART3_RX, | ||
437 | |||
438 | /* Keypad GPIO*/ | ||
439 | T19_24XX_KBR0, | ||
440 | R19_24XX_KBR1, | ||
441 | V18_24XX_KBR2, | ||
442 | M21_24XX_KBR3, | ||
443 | E5__24XX_KBR4, | ||
444 | M18_24XX_KBR5, | ||
445 | R20_24XX_KBC0, | ||
446 | M14_24XX_KBC1, | ||
447 | H19_24XX_KBC2, | ||
448 | V17_24XX_KBC3, | ||
449 | P21_24XX_KBC4, | ||
450 | L14_24XX_KBC5, | ||
451 | N19_24XX_KBC6, | ||
452 | |||
453 | /* 24xx Menelaus Keypad GPIO */ | ||
454 | B3__24XX_KBR5, | ||
455 | AA4_24XX_KBC2, | ||
456 | B13_24XX_KBC6, | ||
409 | }; | 457 | }; |
410 | 458 | ||
411 | #ifdef CONFIG_OMAP_MUX | 459 | #ifdef CONFIG_OMAP_MUX |
diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h new file mode 100644 index 000000000000..df4695474e3d --- /dev/null +++ b/include/asm-arm/arch-omap/omap-alsa.h | |||
@@ -0,0 +1,124 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/omap-alsa.h | ||
3 | * | ||
4 | * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards. | ||
5 | * | ||
6 | * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi> | ||
7 | * | ||
8 | * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil | ||
9 | * Written by Daniel Petrini, David Cohen, Anderson Briglia | ||
10 | * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify it | ||
13 | * under the terms of the GNU General Public License as published by the | ||
14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
15 | * option) any later version. | ||
16 | * | ||
17 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
20 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | ||
28 | * You should have received a copy of the GNU General Public License along | ||
29 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
31 | * | ||
32 | * History | ||
33 | * ------- | ||
34 | * | ||
35 | * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk, | ||
36 | * original version based in sa1100 driver | ||
37 | * and omap oss driver. | ||
38 | */ | ||
39 | |||
40 | #ifndef __OMAP_ALSA_H | ||
41 | #define __OMAP_ALSA_H | ||
42 | |||
43 | #include <sound/driver.h> | ||
44 | #include <asm/arch/dma.h> | ||
45 | #include <sound/core.h> | ||
46 | #include <sound/pcm.h> | ||
47 | #include <asm/arch/mcbsp.h> | ||
48 | #include <linux/platform_device.h> | ||
49 | |||
50 | #define DMA_BUF_SIZE (1024 * 8) | ||
51 | |||
52 | /* | ||
53 | * Buffer management for alsa and dma | ||
54 | */ | ||
55 | struct audio_stream { | ||
56 | char *id; /* identification string */ | ||
57 | int stream_id; /* numeric identification */ | ||
58 | int dma_dev; /* dma number of that device */ | ||
59 | int *lch; /* Chain of channels this stream is linked to */ | ||
60 | char started; /* to store if the chain was started or not */ | ||
61 | int dma_q_head; /* DMA Channel Q Head */ | ||
62 | int dma_q_tail; /* DMA Channel Q Tail */ | ||
63 | char dma_q_count; /* DMA Channel Q Count */ | ||
64 | int active:1; /* we are using this stream for transfer now */ | ||
65 | int period; /* current transfer period */ | ||
66 | int periods; /* current count of periods registerd in the DMA engine */ | ||
67 | spinlock_t dma_lock; /* for locking in DMA operations */ | ||
68 | snd_pcm_substream_t *stream; /* the pcm stream */ | ||
69 | unsigned linked:1; /* dma channels linked */ | ||
70 | int offset; /* store start position of the last period in the alsa buffer */ | ||
71 | int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */ | ||
72 | int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */ | ||
73 | }; | ||
74 | |||
75 | /* | ||
76 | * Alsa card structure for aic23 | ||
77 | */ | ||
78 | struct snd_card_omap_codec { | ||
79 | snd_card_t *card; | ||
80 | snd_pcm_t *pcm; | ||
81 | long samplerate; | ||
82 | struct audio_stream s[2]; /* playback & capture */ | ||
83 | }; | ||
84 | |||
85 | /* Codec specific information and function pointers. | ||
86 | * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c) | ||
87 | * are responsible for defining the function pointers. | ||
88 | */ | ||
89 | struct omap_alsa_codec_config { | ||
90 | char *name; | ||
91 | struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa; | ||
92 | snd_pcm_hw_constraint_list_t *hw_constraints_rates; | ||
93 | snd_pcm_hardware_t *snd_omap_alsa_playback; | ||
94 | snd_pcm_hardware_t *snd_omap_alsa_capture; | ||
95 | void (*codec_configure_dev)(void); | ||
96 | void (*codec_set_samplerate)(long); | ||
97 | void (*codec_clock_setup)(void); | ||
98 | int (*codec_clock_on)(void); | ||
99 | int (*codec_clock_off)(void); | ||
100 | int (*get_default_samplerate)(void); | ||
101 | }; | ||
102 | |||
103 | /*********** Mixer function prototypes *************************/ | ||
104 | int snd_omap_mixer(struct snd_card_omap_codec *); | ||
105 | void snd_omap_init_mixer(void); | ||
106 | |||
107 | #ifdef CONFIG_PM | ||
108 | void snd_omap_suspend_mixer(void); | ||
109 | void snd_omap_resume_mixer(void); | ||
110 | #endif | ||
111 | |||
112 | int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config); | ||
113 | int snd_omap_alsa_remove(struct platform_device *pdev); | ||
114 | #ifdef CONFIG_PM | ||
115 | int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state); | ||
116 | int snd_omap_alsa_resume(struct platform_device *pdev); | ||
117 | #else | ||
118 | #define snd_omap_alsa_suspend NULL | ||
119 | #define snd_omap_alsa_resume NULL | ||
120 | #endif | ||
121 | |||
122 | void callback_omap_alsa_sound_dma(void *); | ||
123 | |||
124 | #endif | ||
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h index 4ba2622cc142..fccdb3db025f 100644 --- a/include/asm-arm/arch-omap/omapfb.h +++ b/include/asm-arm/arch-omap/omapfb.h | |||
@@ -34,9 +34,10 @@ | |||
34 | #define OMAPFB_MIRROR OMAP_IOW(31, int) | 34 | #define OMAPFB_MIRROR OMAP_IOW(31, int) |
35 | #define OMAPFB_SYNC_GFX OMAP_IO(37) | 35 | #define OMAPFB_SYNC_GFX OMAP_IO(37) |
36 | #define OMAPFB_VSYNC OMAP_IO(38) | 36 | #define OMAPFB_VSYNC OMAP_IO(38) |
37 | #define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, enum omapfb_update_mode) | 37 | #define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) |
38 | #define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(41, struct omapfb_update_window_old) | ||
38 | #define OMAPFB_GET_CAPS OMAP_IOR(42, unsigned long) | 39 | #define OMAPFB_GET_CAPS OMAP_IOR(42, unsigned long) |
39 | #define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, enum omapfb_update_mode) | 40 | #define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) |
40 | #define OMAPFB_LCD_TEST OMAP_IOW(45, int) | 41 | #define OMAPFB_LCD_TEST OMAP_IOW(45, int) |
41 | #define OMAPFB_CTRL_TEST OMAP_IOW(46, int) | 42 | #define OMAPFB_CTRL_TEST OMAP_IOW(46, int) |
42 | #define OMAPFB_UPDATE_WINDOW OMAP_IOW(47, struct omapfb_update_window) | 43 | #define OMAPFB_UPDATE_WINDOW OMAP_IOW(47, struct omapfb_update_window) |
@@ -66,9 +67,14 @@ enum omapfb_color_format { | |||
66 | }; | 67 | }; |
67 | 68 | ||
68 | struct omapfb_update_window { | 69 | struct omapfb_update_window { |
69 | u32 x, y; | 70 | __u32 x, y; |
70 | u32 width, height; | 71 | __u32 width, height; |
71 | u32 format; | 72 | __u32 format; |
73 | }; | ||
74 | |||
75 | struct omapfb_update_window_old { | ||
76 | __u32 x, y; | ||
77 | __u32 width, height; | ||
72 | }; | 78 | }; |
73 | 79 | ||
74 | enum omapfb_plane { | 80 | enum omapfb_plane { |
@@ -83,17 +89,17 @@ enum omapfb_channel_out { | |||
83 | }; | 89 | }; |
84 | 90 | ||
85 | struct omapfb_setup_plane { | 91 | struct omapfb_setup_plane { |
86 | u8 plane; | 92 | __u8 plane; |
87 | u8 channel_out; | 93 | __u8 channel_out; |
88 | u32 offset; | 94 | __u32 offset; |
89 | u32 pos_x, pos_y; | 95 | __u32 pos_x, pos_y; |
90 | u32 width, height; | 96 | __u32 width, height; |
91 | u32 color_mode; | 97 | __u32 color_mode; |
92 | }; | 98 | }; |
93 | 99 | ||
94 | struct omapfb_enable_plane { | 100 | struct omapfb_enable_plane { |
95 | u8 plane; | 101 | __u8 plane; |
96 | u8 enable; | 102 | __u8 enable; |
97 | }; | 103 | }; |
98 | 104 | ||
99 | enum omapfb_color_key_type { | 105 | enum omapfb_color_key_type { |
@@ -103,10 +109,10 @@ enum omapfb_color_key_type { | |||
103 | }; | 109 | }; |
104 | 110 | ||
105 | struct omapfb_color_key { | 111 | struct omapfb_color_key { |
106 | u8 channel_out; | 112 | __u8 channel_out; |
107 | u32 background; | 113 | __u32 background; |
108 | u32 trans_key; | 114 | __u32 trans_key; |
109 | u8 key_type; | 115 | __u8 key_type; |
110 | }; | 116 | }; |
111 | 117 | ||
112 | enum omapfb_update_mode { | 118 | enum omapfb_update_mode { |
@@ -120,6 +126,9 @@ enum omapfb_update_mode { | |||
120 | #include <linux/completion.h> | 126 | #include <linux/completion.h> |
121 | #include <linux/interrupt.h> | 127 | #include <linux/interrupt.h> |
122 | #include <linux/fb.h> | 128 | #include <linux/fb.h> |
129 | #include <linux/mutex.h> | ||
130 | |||
131 | #include <asm/arch/board.h> | ||
123 | 132 | ||
124 | #define OMAP_LCDC_INV_VSYNC 0x0001 | 133 | #define OMAP_LCDC_INV_VSYNC 0x0001 |
125 | #define OMAP_LCDC_INV_HSYNC 0x0002 | 134 | #define OMAP_LCDC_INV_HSYNC 0x0002 |
@@ -184,19 +193,38 @@ struct extif_timings { | |||
184 | int re_cycle_time; | 193 | int re_cycle_time; |
185 | int cs_pulse_width; | 194 | int cs_pulse_width; |
186 | int access_time; | 195 | int access_time; |
196 | |||
197 | int clk_div; | ||
198 | |||
199 | u32 tim[5]; /* set by extif->convert_timings */ | ||
200 | |||
201 | int converted; | ||
187 | }; | 202 | }; |
188 | 203 | ||
189 | struct lcd_ctrl_extif { | 204 | struct lcd_ctrl_extif { |
190 | int (*init) (void); | 205 | int (*init) (void); |
191 | void (*cleanup) (void); | 206 | void (*cleanup) (void); |
207 | void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); | ||
208 | int (*convert_timings) (struct extif_timings *timings); | ||
192 | void (*set_timings) (const struct extif_timings *timings); | 209 | void (*set_timings) (const struct extif_timings *timings); |
193 | void (*write_command) (u32 cmd); | 210 | void (*set_bits_per_cycle)(int bpc); |
194 | u32 (*read_data) (void); | 211 | void (*write_command) (const void *buf, unsigned int len); |
195 | void (*write_data) (u32 data); | 212 | void (*read_data) (void *buf, unsigned int len); |
213 | void (*write_data) (const void *buf, unsigned int len); | ||
196 | void (*transfer_area) (int width, int height, | 214 | void (*transfer_area) (int width, int height, |
197 | void (callback)(void * data), void *data); | 215 | void (callback)(void * data), void *data); |
216 | unsigned long max_transmit_size; | ||
198 | }; | 217 | }; |
199 | 218 | ||
219 | struct omapfb_notifier_block { | ||
220 | struct notifier_block nb; | ||
221 | void *data; | ||
222 | }; | ||
223 | |||
224 | typedef int (*omapfb_notifier_callback_t)(struct omapfb_notifier_block *, | ||
225 | unsigned long event, | ||
226 | struct omapfb_device *fbdev); | ||
227 | |||
200 | struct lcd_ctrl { | 228 | struct lcd_ctrl { |
201 | const char *name; | 229 | const char *name; |
202 | void *data; | 230 | void *data; |
@@ -204,9 +232,11 @@ struct lcd_ctrl { | |||
204 | int (*init) (struct omapfb_device *fbdev, | 232 | int (*init) (struct omapfb_device *fbdev, |
205 | int ext_mode, int req_vram_size); | 233 | int ext_mode, int req_vram_size); |
206 | void (*cleanup) (void); | 234 | void (*cleanup) (void); |
235 | void (*bind_client) (struct omapfb_notifier_block *nb); | ||
207 | void (*get_vram_layout)(unsigned long *size, | 236 | void (*get_vram_layout)(unsigned long *size, |
208 | void **virt_base, | 237 | void **virt_base, |
209 | dma_addr_t *phys_base); | 238 | dma_addr_t *phys_base); |
239 | int (*mmap) (struct vm_area_struct *vma); | ||
210 | unsigned long (*get_caps) (void); | 240 | unsigned long (*get_caps) (void); |
211 | int (*set_update_mode)(enum omapfb_update_mode mode); | 241 | int (*set_update_mode)(enum omapfb_update_mode mode); |
212 | enum omapfb_update_mode (*get_update_mode)(void); | 242 | enum omapfb_update_mode (*get_update_mode)(void); |
@@ -240,7 +270,7 @@ struct omapfb_device { | |||
240 | int state; | 270 | int state; |
241 | int ext_lcdc; /* Using external | 271 | int ext_lcdc; /* Using external |
242 | LCD controller */ | 272 | LCD controller */ |
243 | struct semaphore rqueue_sema; | 273 | struct mutex rqueue_mutex; |
244 | 274 | ||
245 | void *vram_virt_base; | 275 | void *vram_virt_base; |
246 | dma_addr_t vram_phys_base; | 276 | dma_addr_t vram_phys_base; |
@@ -261,12 +291,13 @@ struct omapfb_device { | |||
261 | struct device *dev; | 291 | struct device *dev; |
262 | }; | 292 | }; |
263 | 293 | ||
264 | extern struct lcd_panel h3_panel; | 294 | struct omapfb_platform_data { |
265 | extern struct lcd_panel h2_panel; | 295 | struct omap_lcd_config lcd; |
266 | extern struct lcd_panel p2_panel; | 296 | struct omap_fbmem_config fbmem; |
267 | extern struct lcd_panel osk_panel; | 297 | }; |
268 | extern struct lcd_panel innovator1610_panel; | 298 | |
269 | extern struct lcd_panel innovator1510_panel; | 299 | #define OMAPFB_EVENT_READY 1 |
300 | #define OMAPFB_EVENT_DISABLED 2 | ||
270 | 301 | ||
271 | #ifdef CONFIG_ARCH_OMAP1 | 302 | #ifdef CONFIG_ARCH_OMAP1 |
272 | extern struct lcd_ctrl omap1_lcd_ctrl; | 303 | extern struct lcd_ctrl omap1_lcd_ctrl; |
@@ -274,7 +305,20 @@ extern struct lcd_ctrl omap1_lcd_ctrl; | |||
274 | extern struct lcd_ctrl omap2_disp_ctrl; | 305 | extern struct lcd_ctrl omap2_disp_ctrl; |
275 | #endif | 306 | #endif |
276 | 307 | ||
308 | extern void omapfb_register_panel(struct lcd_panel *panel); | ||
277 | extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); | 309 | extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); |
310 | extern void omapfb_notify_clients(struct omapfb_device *fbdev, | ||
311 | unsigned long event); | ||
312 | extern int omapfb_register_client(struct omapfb_notifier_block *nb, | ||
313 | omapfb_notifier_callback_t callback, | ||
314 | void *callback_data); | ||
315 | extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); | ||
316 | extern int omapfb_update_window_async(struct omapfb_update_window *win, | ||
317 | void (*callback)(void *), | ||
318 | void *callback_data); | ||
319 | |||
320 | /* in arch/arm/plat-omap/devices.c */ | ||
321 | extern void omapfb_reserve_mem(void); | ||
278 | 322 | ||
279 | #endif /* __KERNEL__ */ | 323 | #endif /* __KERNEL__ */ |
280 | 324 | ||
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h new file mode 100644 index 000000000000..face9ad41e97 --- /dev/null +++ b/include/asm-arm/arch-omap/param.h | |||
@@ -0,0 +1,8 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-omap/param.h | ||
3 | * | ||
4 | */ | ||
5 | |||
6 | #ifdef CONFIG_OMAP_32K_TIMER_HZ | ||
7 | #define HZ CONFIG_OMAP_32K_TIMER_HZ | ||
8 | #endif | ||
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h index 7c790425e363..05b003f3a94c 100644 --- a/include/asm-arm/arch-omap/pm.h +++ b/include/asm-arm/arch-omap/pm.h | |||
@@ -49,7 +49,7 @@ | |||
49 | 49 | ||
50 | /* | 50 | /* |
51 | * ---------------------------------------------------------------------------- | 51 | * ---------------------------------------------------------------------------- |
52 | * Powermanagement bitmasks | 52 | * Power management bitmasks |
53 | * ---------------------------------------------------------------------------- | 53 | * ---------------------------------------------------------------------------- |
54 | */ | 54 | */ |
55 | #define IDLE_WAIT_CYCLES 0x00000fff | 55 | #define IDLE_WAIT_CYCLES 0x00000fff |
@@ -112,32 +112,59 @@ | |||
112 | #endif | 112 | #endif |
113 | 113 | ||
114 | #ifndef __ASSEMBLER__ | 114 | #ifndef __ASSEMBLER__ |
115 | |||
116 | #include <linux/clk.h> | ||
117 | |||
118 | extern void prevent_idle_sleep(void); | ||
119 | extern void allow_idle_sleep(void); | ||
120 | |||
121 | /** | ||
122 | * clk_deny_idle - Prevents the clock from being idled during MPU idle | ||
123 | * @clk: clock signal handle | ||
124 | */ | ||
125 | void clk_deny_idle(struct clk *clk); | ||
126 | |||
127 | /** | ||
128 | * clk_allow_idle - Counters previous clk_deny_idle | ||
129 | * @clk: clock signal handle | ||
130 | */ | ||
131 | void clk_deny_idle(struct clk *clk); | ||
132 | |||
115 | extern void omap_pm_idle(void); | 133 | extern void omap_pm_idle(void); |
116 | extern void omap_pm_suspend(void); | 134 | extern void omap_pm_suspend(void); |
117 | extern void omap730_cpu_suspend(unsigned short, unsigned short); | 135 | extern void omap730_cpu_suspend(unsigned short, unsigned short); |
118 | extern void omap1510_cpu_suspend(unsigned short, unsigned short); | 136 | extern void omap1510_cpu_suspend(unsigned short, unsigned short); |
119 | extern void omap1610_cpu_suspend(unsigned short, unsigned short); | 137 | extern void omap1610_cpu_suspend(unsigned short, unsigned short); |
138 | extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); | ||
120 | extern void omap730_idle_loop_suspend(void); | 139 | extern void omap730_idle_loop_suspend(void); |
121 | extern void omap1510_idle_loop_suspend(void); | 140 | extern void omap1510_idle_loop_suspend(void); |
122 | extern void omap1610_idle_loop_suspend(void); | 141 | extern void omap1610_idle_loop_suspend(void); |
142 | extern void omap24xx_idle_loop_suspend(void); | ||
143 | |||
144 | extern unsigned int omap730_cpu_suspend_sz; | ||
145 | extern unsigned int omap1510_cpu_suspend_sz; | ||
146 | extern unsigned int omap1610_cpu_suspend_sz; | ||
147 | extern unsigned int omap24xx_cpu_suspend_sz; | ||
148 | extern unsigned int omap730_idle_loop_suspend_sz; | ||
149 | extern unsigned int omap1510_idle_loop_suspend_sz; | ||
150 | extern unsigned int omap1610_idle_loop_suspend_sz; | ||
151 | extern unsigned int omap24xx_idle_loop_suspend_sz; | ||
123 | 152 | ||
124 | #ifdef CONFIG_OMAP_SERIAL_WAKE | 153 | #ifdef CONFIG_OMAP_SERIAL_WAKE |
125 | extern void omap_serial_wake_trigger(int enable); | 154 | extern void omap_serial_wake_trigger(int enable); |
126 | #else | 155 | #else |
156 | #define omap_serial_wakeup_init() {} | ||
127 | #define omap_serial_wake_trigger(x) {} | 157 | #define omap_serial_wake_trigger(x) {} |
128 | #endif /* CONFIG_OMAP_SERIAL_WAKE */ | 158 | #endif /* CONFIG_OMAP_SERIAL_WAKE */ |
129 | 159 | ||
130 | extern unsigned int omap730_cpu_suspend_sz; | ||
131 | extern unsigned int omap730_idle_loop_suspend_sz; | ||
132 | extern unsigned int omap1510_cpu_suspend_sz; | ||
133 | extern unsigned int omap1510_idle_loop_suspend_sz; | ||
134 | extern unsigned int omap1610_cpu_suspend_sz; | ||
135 | extern unsigned int omap1610_idle_loop_suspend_sz; | ||
136 | |||
137 | #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) | 160 | #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) |
138 | #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) | 161 | #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) |
139 | #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] | 162 | #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] |
140 | 163 | ||
164 | #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) | ||
165 | #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) | ||
166 | #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] | ||
167 | |||
141 | #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) | 168 | #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) |
142 | #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) | 169 | #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) |
143 | #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] | 170 | #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] |
@@ -154,6 +181,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz; | |||
154 | #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) | 181 | #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) |
155 | #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] | 182 | #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] |
156 | 183 | ||
184 | #define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x | ||
185 | #define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] | ||
186 | #define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] | ||
187 | |||
157 | /* | 188 | /* |
158 | * List of global OMAP registers to preserve. | 189 | * List of global OMAP registers to preserve. |
159 | * More ones like CP and general purpose register values are preserved | 190 | * More ones like CP and general purpose register values are preserved |
@@ -176,6 +207,15 @@ enum arm_save_state { | |||
176 | ARM_SLEEP_SAVE_SIZE | 207 | ARM_SLEEP_SAVE_SIZE |
177 | }; | 208 | }; |
178 | 209 | ||
210 | enum dsp_save_state { | ||
211 | DSP_SLEEP_SAVE_START = 0, | ||
212 | /* | ||
213 | * DSP registers 16 bits | ||
214 | */ | ||
215 | DSP_SLEEP_SAVE_DSP_IDLECT2, | ||
216 | DSP_SLEEP_SAVE_SIZE | ||
217 | }; | ||
218 | |||
179 | enum ulpd_save_state { | 219 | enum ulpd_save_state { |
180 | ULPD_SLEEP_SAVE_START = 0, | 220 | ULPD_SLEEP_SAVE_START = 0, |
181 | /* | 221 | /* |
@@ -254,5 +294,30 @@ enum mpui1610_save_state { | |||
254 | #endif | 294 | #endif |
255 | }; | 295 | }; |
256 | 296 | ||
297 | enum omap24xx_save_state { | ||
298 | OMAP24XX_SLEEP_SAVE_START = 0, | ||
299 | OMAP24XX_SLEEP_SAVE_INTC_MIR0, | ||
300 | OMAP24XX_SLEEP_SAVE_INTC_MIR1, | ||
301 | OMAP24XX_SLEEP_SAVE_INTC_MIR2, | ||
302 | OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, | ||
303 | OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, | ||
304 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, | ||
305 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, | ||
306 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, | ||
307 | OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, | ||
308 | OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, | ||
309 | OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, | ||
310 | OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, | ||
311 | OMAP24XX_SLEEP_SAVE_GPIO3_OE, | ||
312 | OMAP24XX_SLEEP_SAVE_GPIO4_OE, | ||
313 | OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, | ||
314 | OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, | ||
315 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, | ||
316 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, | ||
317 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, | ||
318 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, | ||
319 | OMAP24XX_SLEEP_SAVE_SIZE | ||
320 | }; | ||
321 | |||
257 | #endif /* ASSEMBLER */ | 322 | #endif /* ASSEMBLER */ |
258 | #endif /* __ASM_ARCH_OMAP_PM_H */ | 323 | #endif /* __ASM_ARCH_OMAP_PM_H */ |
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h index 7b48a5cbb15f..7bcaf94bde9f 100644 --- a/include/asm-arm/arch-omap/prcm.h +++ b/include/asm-arm/arch-omap/prcm.h | |||
@@ -1,5 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * prcm.h - Access definations for use in OMAP24XX clock and power management | 2 | * linux/include/asm-arm/arch-omap/prcm.h |
3 | * | ||
4 | * Access definations for use in OMAP24XX clock and power management | ||
3 | * | 5 | * |
4 | * Copyright (C) 2005 Texas Instruments, Inc. | 6 | * Copyright (C) 2005 Texas Instruments, Inc. |
5 | * | 7 | * |
@@ -21,405 +23,7 @@ | |||
21 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H | 23 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H |
22 | #define __ASM_ARM_ARCH_DPM_PRCM_H | 24 | #define __ASM_ARM_ARCH_DPM_PRCM_H |
23 | 25 | ||
24 | /* SET_PERFORMANCE_LEVEL PARAMETERS */ | 26 | u32 omap_prcm_get_reset_sources(void); |
25 | #define PRCM_HALF_SPEED 1 | ||
26 | #define PRCM_FULL_SPEED 2 | ||
27 | |||
28 | #ifndef __ASSEMBLER__ | ||
29 | |||
30 | #define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) | ||
31 | |||
32 | #define PRCM_REVISION PRCM_REG32(0x000) | ||
33 | #define PRCM_SYSCONFIG PRCM_REG32(0x010) | ||
34 | #define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) | ||
35 | #define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) | ||
36 | #define PRCM_VOLTCTRL PRCM_REG32(0x050) | ||
37 | #define PRCM_VOLTST PRCM_REG32(0x054) | ||
38 | #define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) | ||
39 | #define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) | ||
40 | #define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) | ||
41 | #define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) | ||
42 | #define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) | ||
43 | #define PRCM_VOLTSETUP PRCM_REG32(0x090) | ||
44 | #define PRCM_CLKSSETUP PRCM_REG32(0x094) | ||
45 | #define PRCM_POLCTRL PRCM_REG32(0x098) | ||
46 | |||
47 | /* GENERAL PURPOSE */ | ||
48 | #define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) | ||
49 | #define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) | ||
50 | #define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) | ||
51 | #define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) | ||
52 | #define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) | ||
53 | #define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) | ||
54 | #define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) | ||
55 | #define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) | ||
56 | #define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) | ||
57 | #define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) | ||
58 | #define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) | ||
59 | #define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) | ||
60 | #define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) | ||
61 | #define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) | ||
62 | #define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) | ||
63 | #define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) | ||
64 | #define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) | ||
65 | #define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) | ||
66 | #define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) | ||
67 | #define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) | ||
68 | |||
69 | /* MPU */ | ||
70 | #define CM_CLKSEL_MPU PRCM_REG32(0x140) | ||
71 | #define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) | ||
72 | #define RM_RSTST_MPU PRCM_REG32(0x158) | ||
73 | #define PM_WKDEP_MPU PRCM_REG32(0x1C8) | ||
74 | #define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) | ||
75 | #define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) | ||
76 | #define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) | ||
77 | #define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) | ||
78 | #define PM_PWSTST_MPU PRCM_REG32(0x1E4) | ||
79 | |||
80 | /* CORE */ | ||
81 | #define CM_FCLKEN1_CORE PRCM_REG32(0x200) | ||
82 | #define CM_FCLKEN2_CORE PRCM_REG32(0x204) | ||
83 | #define CM_FCLKEN3_CORE PRCM_REG32(0x208) | ||
84 | #define CM_ICLKEN1_CORE PRCM_REG32(0x210) | ||
85 | #define CM_ICLKEN2_CORE PRCM_REG32(0x214) | ||
86 | #define CM_ICLKEN3_CORE PRCM_REG32(0x218) | ||
87 | #define CM_ICLKEN4_CORE PRCM_REG32(0x21C) | ||
88 | #define CM_IDLEST1_CORE PRCM_REG32(0x220) | ||
89 | #define CM_IDLEST2_CORE PRCM_REG32(0x224) | ||
90 | #define CM_IDLEST3_CORE PRCM_REG32(0x228) | ||
91 | #define CM_IDLEST4_CORE PRCM_REG32(0x22C) | ||
92 | #define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) | ||
93 | #define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) | ||
94 | #define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) | ||
95 | #define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) | ||
96 | #define CM_CLKSEL1_CORE PRCM_REG32(0x240) | ||
97 | #define CM_CLKSEL2_CORE PRCM_REG32(0x244) | ||
98 | #define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) | ||
99 | #define PM_WKEN1_CORE PRCM_REG32(0x2A0) | ||
100 | #define PM_WKEN2_CORE PRCM_REG32(0x2A4) | ||
101 | #define PM_WKST1_CORE PRCM_REG32(0x2B0) | ||
102 | #define PM_WKST2_CORE PRCM_REG32(0x2B4) | ||
103 | #define PM_WKDEP_CORE PRCM_REG32(0x2C8) | ||
104 | #define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) | ||
105 | #define PM_PWSTST_CORE PRCM_REG32(0x2E4) | ||
106 | |||
107 | /* GFX */ | ||
108 | #define CM_FCLKEN_GFX PRCM_REG32(0x300) | ||
109 | #define CM_ICLKEN_GFX PRCM_REG32(0x310) | ||
110 | #define CM_IDLEST_GFX PRCM_REG32(0x320) | ||
111 | #define CM_CLKSEL_GFX PRCM_REG32(0x340) | ||
112 | #define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) | ||
113 | #define RM_RSTCTRL_GFX PRCM_REG32(0x350) | ||
114 | #define RM_RSTST_GFX PRCM_REG32(0x358) | ||
115 | #define PM_WKDEP_GFX PRCM_REG32(0x3C8) | ||
116 | #define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) | ||
117 | #define PM_PWSTST_GFX PRCM_REG32(0x3E4) | ||
118 | |||
119 | /* WAKE-UP */ | ||
120 | #define CM_FCLKEN_WKUP PRCM_REG32(0x400) | ||
121 | #define CM_ICLKEN_WKUP PRCM_REG32(0x410) | ||
122 | #define CM_IDLEST_WKUP PRCM_REG32(0x420) | ||
123 | #define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) | ||
124 | #define CM_CLKSEL_WKUP PRCM_REG32(0x440) | ||
125 | #define RM_RSTCTRL_WKUP PRCM_REG32(0x450) | ||
126 | #define RM_RSTTIME_WKUP PRCM_REG32(0x454) | ||
127 | #define RM_RSTST_WKUP PRCM_REG32(0x458) | ||
128 | #define PM_WKEN_WKUP PRCM_REG32(0x4A0) | ||
129 | #define PM_WKST_WKUP PRCM_REG32(0x4B0) | ||
130 | |||
131 | /* CLOCKS */ | ||
132 | #define CM_CLKEN_PLL PRCM_REG32(0x500) | ||
133 | #define CM_IDLEST_CKGEN PRCM_REG32(0x520) | ||
134 | #define CM_AUTOIDLE_PLL PRCM_REG32(0x530) | ||
135 | #define CM_CLKSEL1_PLL PRCM_REG32(0x540) | ||
136 | #define CM_CLKSEL2_PLL PRCM_REG32(0x544) | ||
137 | |||
138 | /* DSP */ | ||
139 | #define CM_FCLKEN_DSP PRCM_REG32(0x800) | ||
140 | #define CM_ICLKEN_DSP PRCM_REG32(0x810) | ||
141 | #define CM_IDLEST_DSP PRCM_REG32(0x820) | ||
142 | #define CM_AUTOIDLE_DSP PRCM_REG32(0x830) | ||
143 | #define CM_CLKSEL_DSP PRCM_REG32(0x840) | ||
144 | #define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) | ||
145 | #define RM_RSTCTRL_DSP PRCM_REG32(0x850) | ||
146 | #define RM_RSTST_DSP PRCM_REG32(0x858) | ||
147 | #define PM_WKEN_DSP PRCM_REG32(0x8A0) | ||
148 | #define PM_WKDEP_DSP PRCM_REG32(0x8C8) | ||
149 | #define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) | ||
150 | #define PM_PWSTST_DSP PRCM_REG32(0x8E4) | ||
151 | #define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) | ||
152 | #define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) | ||
153 | |||
154 | /* IVA */ | ||
155 | #define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) | ||
156 | #define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) | ||
157 | |||
158 | /* Modem on 2430 */ | ||
159 | #define CM_FCLKEN_MDM PRCM_REG32(0xC00) | ||
160 | #define CM_ICLKEN_MDM PRCM_REG32(0xC10) | ||
161 | #define CM_IDLEST_MDM PRCM_REG32(0xC20) | ||
162 | #define CM_CLKSEL_MDM PRCM_REG32(0xC40) | ||
163 | |||
164 | /* FIXME: Move to header for 2430 */ | ||
165 | #define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) | ||
166 | #define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) | ||
167 | |||
168 | #define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000) | ||
169 | #define GPMC_BASE (OMAP24XX_GPMC_BASE) | ||
170 | #define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) | ||
171 | |||
172 | #define GPT1_BASE (OMAP24XX_GPT1) | ||
173 | #define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) | ||
174 | |||
175 | /* Misc sysconfig */ | ||
176 | #define DISPC_SYSCONFIG DISP_REG32(0x410) | ||
177 | #define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) | ||
178 | #define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) | ||
179 | #define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) | ||
180 | |||
181 | //#define DSP_MMU_SYSCONFIG 0x5A000010 | ||
182 | #define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) | ||
183 | //#define IVA_MMU_SYSCONFIG 0x5D000010 | ||
184 | //#define DSP_DMA_SYSCONFIG 0x00FCC02C | ||
185 | #define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C) | ||
186 | #define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C) | ||
187 | #define GPMC_SYSCONFIG GPMC_REG32(0x010) | ||
188 | #define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) | ||
189 | #define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) | ||
190 | #define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) | ||
191 | #define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) | ||
192 | //#define IVA_SYSCONFIG 0x5C060010 | ||
193 | #define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) | ||
194 | #define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) | ||
195 | #define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) | ||
196 | //#define VLYNQ_SYSCONFIG 0x67FFFE10 | ||
197 | |||
198 | /* rkw - good cannidates for PM_ to start what nm was trying */ | ||
199 | #define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) | ||
200 | #define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) | ||
201 | #define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) | ||
202 | #define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) | ||
203 | #define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) | ||
204 | #define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) | ||
205 | #define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) | ||
206 | #define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) | ||
207 | #define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) | ||
208 | #define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) | ||
209 | #define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) | ||
210 | |||
211 | #define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) | ||
212 | #define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) | ||
213 | #define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) | ||
214 | #define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) | ||
215 | #define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) | ||
216 | #define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) | ||
217 | #define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) | ||
218 | #define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) | ||
219 | #define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) | ||
220 | #define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) | ||
221 | #define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) | ||
222 | #define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) | ||
223 | |||
224 | #define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) | ||
225 | |||
226 | #define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) | ||
227 | #define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) | ||
228 | #define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) | ||
229 | #define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10)) | ||
230 | |||
231 | /* GP TIMER 1 */ | ||
232 | #define GPTIMER1_TISTAT GPT1_REG32(0x014) | ||
233 | #define GPTIMER1_TISR GPT1_REG32(0x018) | ||
234 | #define GPTIMER1_TIER GPT1_REG32(0x01C) | ||
235 | #define GPTIMER1_TWER GPT1_REG32(0x020) | ||
236 | #define GPTIMER1_TCLR GPT1_REG32(0x024) | ||
237 | #define GPTIMER1_TCRR GPT1_REG32(0x028) | ||
238 | #define GPTIMER1_TLDR GPT1_REG32(0x02C) | ||
239 | #define GPTIMER1_TTGR GPT1_REG32(0x030) | ||
240 | #define GPTIMER1_TWPS GPT1_REG32(0x034) | ||
241 | #define GPTIMER1_TMAR GPT1_REG32(0x038) | ||
242 | #define GPTIMER1_TCAR1 GPT1_REG32(0x03C) | ||
243 | #define GPTIMER1_TSICR GPT1_REG32(0x040) | ||
244 | #define GPTIMER1_TCAR2 GPT1_REG32(0x044) | ||
245 | |||
246 | /* rkw -- base fix up please... */ | ||
247 | #define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) | ||
248 | |||
249 | /* SDRC */ | ||
250 | #define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) | ||
251 | #define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) | ||
252 | #define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) | ||
253 | #define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) | ||
254 | #define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) | ||
255 | #define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) | ||
256 | |||
257 | /* GPIO 1 */ | ||
258 | #define GPIO1_BASE GPIOX_BASE(1) | ||
259 | #define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) | ||
260 | #define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) | ||
261 | #define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) | ||
262 | #define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) | ||
263 | #define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) | ||
264 | #define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) | ||
265 | #define GPIO1_RISINGDETECT GPIO1_REG32(0x048) | ||
266 | #define GPIO1_DATAIN GPIO1_REG32(0x038) | ||
267 | #define GPIO1_OE GPIO1_REG32(0x034) | ||
268 | #define GPIO1_DATAOUT GPIO1_REG32(0x03C) | ||
269 | |||
270 | /* GPIO2 */ | ||
271 | #define GPIO2_BASE GPIOX_BASE(2) | ||
272 | #define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) | ||
273 | #define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) | ||
274 | #define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) | ||
275 | #define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) | ||
276 | #define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) | ||
277 | #define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) | ||
278 | #define GPIO2_RISINGDETECT GPIO2_REG32(0x048) | ||
279 | #define GPIO2_DATAIN GPIO2_REG32(0x038) | ||
280 | #define GPIO2_OE GPIO2_REG32(0x034) | ||
281 | #define GPIO2_DATAOUT GPIO2_REG32(0x03C) | ||
282 | |||
283 | /* GPIO 3 */ | ||
284 | #define GPIO3_BASE GPIOX_BASE(3) | ||
285 | #define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) | ||
286 | #define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) | ||
287 | #define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) | ||
288 | #define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) | ||
289 | #define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) | ||
290 | #define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) | ||
291 | #define GPIO3_RISINGDETECT GPIO3_REG32(0x048) | ||
292 | #define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) | ||
293 | #define GPIO3_DATAIN GPIO3_REG32(0x038) | ||
294 | #define GPIO3_OE GPIO3_REG32(0x034) | ||
295 | #define GPIO3_DATAOUT GPIO3_REG32(0x03C) | ||
296 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) | ||
297 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) | ||
298 | |||
299 | /* GPIO 4 */ | ||
300 | #define GPIO4_BASE GPIOX_BASE(4) | ||
301 | #define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) | ||
302 | #define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) | ||
303 | #define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) | ||
304 | #define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) | ||
305 | #define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) | ||
306 | #define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) | ||
307 | #define GPIO4_RISINGDETECT GPIO4_REG32(0x048) | ||
308 | #define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) | ||
309 | #define GPIO4_DATAIN GPIO4_REG32(0x038) | ||
310 | #define GPIO4_OE GPIO4_REG32(0x034) | ||
311 | #define GPIO4_DATAOUT GPIO4_REG32(0x03C) | ||
312 | #define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) | ||
313 | #define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) | ||
314 | |||
315 | |||
316 | /* IO CONFIG */ | ||
317 | #define CONTROL_BASE (OMAP24XX_CTRL_BASE) | ||
318 | #define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) | ||
319 | |||
320 | #define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) | ||
321 | #define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) | ||
322 | #define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) | ||
323 | #define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) | ||
324 | #define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) | ||
325 | #define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) | ||
326 | #define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) | ||
327 | #define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) | ||
328 | #define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) | ||
329 | |||
330 | /* CONTROL */ | ||
331 | #define CONTROL_DEVCONF CONTROL_REG32(0x274) | ||
332 | |||
333 | /* INTERRUPT CONTROLLER */ | ||
334 | #define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) | ||
335 | #define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) | ||
336 | |||
337 | #define INTC1_U_BASE INTC_REG32(0x000) | ||
338 | #define INTC_MIR0 INTC_REG32(0x084) | ||
339 | #define INTC_MIR_SET0 INTC_REG32(0x08C) | ||
340 | #define INTC_MIR_CLEAR0 INTC_REG32(0x088) | ||
341 | #define INTC_ISR_CLEAR0 INTC_REG32(0x094) | ||
342 | #define INTC_MIR1 INTC_REG32(0x0A4) | ||
343 | #define INTC_MIR_SET1 INTC_REG32(0x0AC) | ||
344 | #define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) | ||
345 | #define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) | ||
346 | #define INTC_MIR2 INTC_REG32(0x0C4) | ||
347 | #define INTC_MIR_SET2 INTC_REG32(0x0CC) | ||
348 | #define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) | ||
349 | #define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) | ||
350 | #define INTC_SIR_IRQ INTC_REG32(0x040) | ||
351 | #define INTC_CONTROL INTC_REG32(0x048) | ||
352 | #define INTC_ILR11 INTC_REG32(0x12C) | ||
353 | #define INTC_ILR32 INTC_REG32(0x180) | ||
354 | #define INTC_ILR37 INTC_REG32(0x194) | ||
355 | #define INTC_SYSCONFIG INTC_REG32(0x010) | ||
356 | |||
357 | /* RAM FIREWALL */ | ||
358 | #define RAMFW_BASE (0x68005000) | ||
359 | #define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) | ||
360 | |||
361 | #define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) | ||
362 | #define RAMFW_READPERM0 RAMFW_REG32(0x050) | ||
363 | #define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) | ||
364 | |||
365 | /* GPMC CS1 FPGA ON USER INTERFACE MODULE */ | ||
366 | //#define DEBUG_BOARD_LED_REGISTER 0x04000014 | ||
367 | |||
368 | /* GPMC CS0 */ | ||
369 | #define GPMC_CONFIG1_0 GPMC_REG32(0x060) | ||
370 | #define GPMC_CONFIG2_0 GPMC_REG32(0x064) | ||
371 | #define GPMC_CONFIG3_0 GPMC_REG32(0x068) | ||
372 | #define GPMC_CONFIG4_0 GPMC_REG32(0x06C) | ||
373 | #define GPMC_CONFIG5_0 GPMC_REG32(0x070) | ||
374 | #define GPMC_CONFIG6_0 GPMC_REG32(0x074) | ||
375 | #define GPMC_CONFIG7_0 GPMC_REG32(0x078) | ||
376 | |||
377 | /* GPMC CS1 */ | ||
378 | #define GPMC_CONFIG1_1 GPMC_REG32(0x090) | ||
379 | #define GPMC_CONFIG2_1 GPMC_REG32(0x094) | ||
380 | #define GPMC_CONFIG3_1 GPMC_REG32(0x098) | ||
381 | #define GPMC_CONFIG4_1 GPMC_REG32(0x09C) | ||
382 | #define GPMC_CONFIG5_1 GPMC_REG32(0x0a0) | ||
383 | #define GPMC_CONFIG6_1 GPMC_REG32(0x0a4) | ||
384 | #define GPMC_CONFIG7_1 GPMC_REG32(0x0a8) | ||
385 | |||
386 | /* DSS */ | ||
387 | #define DSS_CONTROL DISP_REG32(0x040) | ||
388 | #define DISPC_CONTROL DISP_REG32(0x440) | ||
389 | #define DISPC_SYSSTATUS DISP_REG32(0x414) | ||
390 | #define DISPC_IRQSTATUS DISP_REG32(0x418) | ||
391 | #define DISPC_IRQENABLE DISP_REG32(0x41C) | ||
392 | #define DISPC_CONFIG DISP_REG32(0x444) | ||
393 | #define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) | ||
394 | #define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) | ||
395 | #define DISPC_TRANS_COLOR0 DISP_REG32(0x454) | ||
396 | #define DISPC_TRANS_COLOR1 DISP_REG32(0x458) | ||
397 | #define DISPC_LINE_NUMBER DISP_REG32(0x460) | ||
398 | #define DISPC_TIMING_H DISP_REG32(0x464) | ||
399 | #define DISPC_TIMING_V DISP_REG32(0x468) | ||
400 | #define DISPC_POL_FREQ DISP_REG32(0x46C) | ||
401 | #define DISPC_DIVISOR DISP_REG32(0x470) | ||
402 | #define DISPC_SIZE_DIG DISP_REG32(0x478) | ||
403 | #define DISPC_SIZE_LCD DISP_REG32(0x47C) | ||
404 | #define DISPC_GFX_BA0 DISP_REG32(0x480) | ||
405 | #define DISPC_GFX_BA1 DISP_REG32(0x484) | ||
406 | #define DISPC_GFX_POSITION DISP_REG32(0x488) | ||
407 | #define DISPC_GFX_SIZE DISP_REG32(0x48C) | ||
408 | #define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) | ||
409 | #define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) | ||
410 | #define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) | ||
411 | #define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) | ||
412 | #define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) | ||
413 | #define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) | ||
414 | #define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) | ||
415 | #define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) | ||
416 | #define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) | ||
417 | |||
418 | /* Wake up define for board */ | ||
419 | #define GPIO97 (1 << 1) | ||
420 | #define GPIO88 (1 << 24) | ||
421 | |||
422 | #endif /* __ASSEMBLER__ */ | ||
423 | 27 | ||
424 | #endif | 28 | #endif |
425 | 29 | ||
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h index e72ccbf0fe06..6fc0dd57b7c3 100644 --- a/include/asm-arm/arch-omap/sram.h +++ b/include/asm-arm/arch-omap/sram.h | |||
@@ -20,6 +20,8 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | |||
20 | u32 mem_type); | 20 | u32 mem_type); |
21 | extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | 21 | extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); |
22 | 22 | ||
23 | extern unsigned long omap_fb_sram_start; | ||
24 | extern unsigned long omap_fb_sram_size; | ||
23 | 25 | ||
24 | /* Do not use these */ | 26 | /* Do not use these */ |
25 | extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); | 27 | extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); |
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h index 6724a81bd10b..67970d1a2020 100644 --- a/include/asm-arm/arch-omap/system.h +++ b/include/asm-arm/arch-omap/system.h | |||
@@ -9,12 +9,13 @@ | |||
9 | 9 | ||
10 | #include <asm/mach-types.h> | 10 | #include <asm/mach-types.h> |
11 | #include <asm/hardware.h> | 11 | #include <asm/hardware.h> |
12 | #include <asm/arch/prcm.h> | ||
13 | 12 | ||
14 | #ifndef CONFIG_MACH_VOICEBLUE | 13 | #ifndef CONFIG_MACH_VOICEBLUE |
15 | #define voiceblue_reset() do {} while (0) | 14 | #define voiceblue_reset() do {} while (0) |
16 | #endif | 15 | #endif |
17 | 16 | ||
17 | extern void omap_prcm_arch_reset(char mode); | ||
18 | |||
18 | static inline void arch_idle(void) | 19 | static inline void arch_idle(void) |
19 | { | 20 | { |
20 | cpu_do_idle(); | 21 | cpu_do_idle(); |
@@ -38,24 +39,12 @@ static inline void omap1_arch_reset(char mode) | |||
38 | omap_writew(1, ARM_RSTCT1); | 39 | omap_writew(1, ARM_RSTCT1); |
39 | } | 40 | } |
40 | 41 | ||
41 | static inline void omap2_arch_reset(char mode) | ||
42 | { | ||
43 | u32 rate; | ||
44 | struct clk *vclk, *sclk; | ||
45 | |||
46 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
47 | sclk = clk_get(NULL, "sys_ck"); | ||
48 | rate = clk_get_rate(sclk); | ||
49 | clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */ | ||
50 | RM_RSTCTRL_WKUP |= 2; | ||
51 | } | ||
52 | |||
53 | static inline void arch_reset(char mode) | 42 | static inline void arch_reset(char mode) |
54 | { | 43 | { |
55 | if (!cpu_is_omap24xx()) | 44 | if (!cpu_is_omap24xx()) |
56 | omap1_arch_reset(mode); | 45 | omap1_arch_reset(mode); |
57 | else | 46 | else |
58 | omap2_arch_reset(mode); | 47 | omap_prcm_arch_reset(mode); |
59 | } | 48 | } |
60 | 49 | ||
61 | #endif | 50 | #endif |
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S index cc06b1bd37b2..894c35cf3b1e 100644 --- a/include/asm-arm/arch-s3c2410/entry-macro.S +++ b/include/asm-arm/arch-s3c2410/entry-macro.S | |||
@@ -6,116 +6,83 @@ | |||
6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | ||
10 | |||
11 | /* We have a problem that the INTOFFSET register does not always | ||
12 | * show one interrupt. Occasionally we get two interrupts through | ||
13 | * the prioritiser, and this causes the INTOFFSET register to show | ||
14 | * what looks like the logical-or of the two interrupt numbers. | ||
15 | * | ||
16 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | ||
17 | */ | ||
18 | |||
19 | #define INTPND (0x10) | ||
20 | #define INTOFFSET (0x14) | ||
21 | #define EXTINTPEND (0xa8) | ||
22 | #define EXTINTMASK (0xa4) | ||
9 | 23 | ||
10 | * Modifications: | ||
11 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | ||
12 | */ | ||
13 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
14 | #include <asm/arch/irqs.h> | 25 | #include <asm/arch/irqs.h> |
15 | 26 | ||
16 | |||
17 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
18 | 28 | ||
19 | mov \tmp, #S3C24XX_VA_IRQ | 29 | mov \base, #S3C24XX_VA_IRQ |
20 | ldr \irqnr, [ \tmp, #0x14 ] @ get irq no | 30 | |
21 | 30000: | 31 | ldr \irqstat, [ \base, #INTPND] |
22 | teq \irqnr, #4 | 32 | bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ |
23 | teqne \irqnr, #5 | 33 | beq 2000f |
24 | beq 1002f @ external irq reg | 34 | |
25 | 35 | @@ try the interrupt offset register, since it is there | |
26 | @ debug check to see if interrupt reported is the same | 36 | |
27 | @ as the offset.... | 37 | ldr \irqnr, [ \base, #INTOFFSET ] |
28 | 38 | mov \tmp, #1 | |
29 | teq \irqnr, #0 | 39 | tst \irqstat, \tmp, lsl \irqnr |
30 | beq 20002f | 40 | addne \irqnr, \irqnr, #IRQ_EINT0 |
31 | ldr \irqstat, [ \tmp, #0x10 ] @ INTPND | 41 | bne 1001f |
32 | mov \irqstat, \irqstat, lsr \irqnr | 42 | |
33 | tst \irqstat, #1 | 43 | @@ the number specified is not a valid irq, so try |
34 | bne 20002f | 44 | @@ and work it out for ourselves |
35 | 45 | ||
36 | /* debug/warning if we get an invalud response from the | 46 | mov \irqnr, #IRQ_EINT0 @@ start here |
37 | * INTOFFSET register */ | 47 | b 3000f |
38 | #if 1 | 48 | |
39 | stmfd r13!, { r0 - r4 , r8-r12, r14 } | 49 | 2000: |
40 | ldr r1, [ \tmp, #0x14 ] @ INTOFFSET | 50 | @@ load the GPIO interrupt register, and check it |
41 | ldr r2, [ \tmp, #0x10 ] @ INTPND | 51 | |
42 | ldr r3, [ \tmp, #0x00 ] @ SRCPND | 52 | add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ |
43 | adr r0, 20003f | 53 | ldr \irqstat, [ \tmp, # EXTINTPEND ] |
44 | bl printk | 54 | ldr \irqnr, [ \tmp, # EXTINTMASK ] |
45 | b 20004f | 55 | bics \irqstat, \irqstat, \irqnr |
46 | 56 | beq 1001f | |
47 | 20003: | 57 | |
48 | .ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n" | 58 | mov \irqnr, #(IRQ_EINT4 - 4) |
49 | .byte 0 | 59 | |
50 | .align 4 | 60 | @@ work out which irq (if any) we got |
51 | 20004: | 61 | 3000: |
52 | mov r1, #1 | 62 | movs \tmp, \irqstat, lsl#16 |
53 | mov \tmp, #S3C24XX_VA_IRQ | 63 | addeq \irqnr, \irqnr, #16 |
54 | ldmfd r13!, { r0 - r4 , r8-r12, r14 } | 64 | moveq \irqstat, \irqstat, lsr#16 |
55 | #endif | 65 | tst \irqstat, #0xff |
56 | 66 | addeq \irqnr, \irqnr, #8 | |
57 | @ try working out interrupt number for ourselves | 67 | moveq \irqstat, \irqstat, lsr#8 |
58 | mov \irqnr, #0 | 68 | tst \irqstat, #0xf |
59 | ldr \irqstat, [ \tmp, #0x10 ] @ INTPND | 69 | addeq \irqnr, \irqnr, #4 |
60 | 10021: | 70 | moveq \irqstat, \irqstat, lsr#4 |
61 | movs \irqstat, \irqstat, lsr#1 | 71 | tst \irqstat, #0x3 |
62 | bcs 30000b @ try and re-start the proccess | 72 | addeq \irqnr, \irqnr, #2 |
63 | add \irqnr, \irqnr, #1 | 73 | moveq \irqstat, \irqstat, lsr#2 |
64 | cmp \irqnr, #32 | 74 | tst \irqstat, #0x1 |
65 | ble 10021b | 75 | addeq \irqnr, \irqnr, #1 |
66 | 76 | ||
67 | @ found no interrupt, set Z flag and leave | 77 | @@ we have the value |
68 | movs \irqnr, #0 | 78 | movs \irqnr, \irqnr |
69 | b 1001f | 79 | |
70 | |||
71 | 20005: | ||
72 | 20002: @ exit | ||
73 | @ we base the s3c2410x interrupts at 16 and above to allow | ||
74 | @ isa peripherals to have their standard interrupts, also | ||
75 | @ ensure that Z flag is un-set on exit | ||
76 | |||
77 | @ note, we cannot be sure if we get IRQ_EINT0 (0) that | ||
78 | @ there is simply no interrupt pending, so in all other | ||
79 | @ cases we jump to say we have found something, otherwise | ||
80 | @ we check to see if the interrupt really is assrted | ||
81 | adds \irqnr, \irqnr, #IRQ_EINT0 | ||
82 | teq \irqnr, #IRQ_EINT0 | ||
83 | bne 1001f @ exit | ||
84 | ldr \irqstat, [ \tmp, #0x10 ] @ INTPND | ||
85 | teq \irqstat, #0 | ||
86 | moveq \irqnr, #0 | ||
87 | b 1001f | ||
88 | |||
89 | @ we get here from no main or external interrupts pending | ||
90 | 1002: | ||
91 | add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ | ||
92 | ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND | ||
93 | ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK | ||
94 | |||
95 | bic \irqstat, \irqstat, \irqnr @ clear masked irqs | ||
96 | |||
97 | mov \irqnr, #IRQ_EINT4 @ start extint nos | ||
98 | mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits | ||
99 | 10021: | ||
100 | movs \irqstat, \irqstat, lsr#1 | ||
101 | bcs 1004f | ||
102 | add \irqnr, \irqnr, #1 | ||
103 | cmp \irqnr, #IRQ_EINT23 | ||
104 | ble 10021b | ||
105 | |||
106 | @ found no interrupt, set Z flag and leave | ||
107 | movs \irqnr, #0 | ||
108 | |||
109 | 1004: @ ensure Z flag clear in case our MOVS shifted out the last bit | ||
110 | teq \irqnr, #0 | ||
111 | 1001: | 80 | 1001: |
112 | @ exit irq routine | 81 | @@ exit here, Z flag unset if IRQ |
113 | .endm | ||
114 | 82 | ||
83 | .endm | ||
115 | 84 | ||
116 | /* currently don't need an disable_fiq macro */ | 85 | /* currently don't need an disable_fiq macro */ |
117 | 86 | ||
118 | .macro disable_fiq | 87 | .macro disable_fiq |
119 | .endm | 88 | .endm |
120 | |||
121 | |||
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index e3e8541ee63b..63ca7412a462 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h | |||
@@ -47,7 +47,7 @@ static inline int dma_get_cache_alignment(void) | |||
47 | 47 | ||
48 | static inline int dma_is_consistent(dma_addr_t handle) | 48 | static inline int dma_is_consistent(dma_addr_t handle) |
49 | { | 49 | { |
50 | return 0; | 50 | return !!arch_is_coherent(); |
51 | } | 51 | } |
52 | 52 | ||
53 | /* | 53 | /* |
@@ -145,7 +145,9 @@ static inline dma_addr_t | |||
145 | dma_map_single(struct device *dev, void *cpu_addr, size_t size, | 145 | dma_map_single(struct device *dev, void *cpu_addr, size_t size, |
146 | enum dma_data_direction dir) | 146 | enum dma_data_direction dir) |
147 | { | 147 | { |
148 | consistent_sync(cpu_addr, size, dir); | 148 | if (!arch_is_coherent()) |
149 | consistent_sync(cpu_addr, size, dir); | ||
150 | |||
149 | return virt_to_dma(dev, (unsigned long)cpu_addr); | 151 | return virt_to_dma(dev, (unsigned long)cpu_addr); |
150 | } | 152 | } |
151 | #else | 153 | #else |
@@ -255,7 +257,9 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |||
255 | 257 | ||
256 | sg->dma_address = page_to_dma(dev, sg->page) + sg->offset; | 258 | sg->dma_address = page_to_dma(dev, sg->page) + sg->offset; |
257 | virt = page_address(sg->page) + sg->offset; | 259 | virt = page_address(sg->page) + sg->offset; |
258 | consistent_sync(virt, sg->length, dir); | 260 | |
261 | if (!arch_is_coherent()) | ||
262 | consistent_sync(virt, sg->length, dir); | ||
259 | } | 263 | } |
260 | 264 | ||
261 | return nents; | 265 | return nents; |
@@ -310,14 +314,16 @@ static inline void | |||
310 | dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, | 314 | dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, |
311 | enum dma_data_direction dir) | 315 | enum dma_data_direction dir) |
312 | { | 316 | { |
313 | consistent_sync((void *)dma_to_virt(dev, handle), size, dir); | 317 | if (!arch_is_coherent()) |
318 | consistent_sync((void *)dma_to_virt(dev, handle), size, dir); | ||
314 | } | 319 | } |
315 | 320 | ||
316 | static inline void | 321 | static inline void |
317 | dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, | 322 | dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, |
318 | enum dma_data_direction dir) | 323 | enum dma_data_direction dir) |
319 | { | 324 | { |
320 | consistent_sync((void *)dma_to_virt(dev, handle), size, dir); | 325 | if (!arch_is_coherent()) |
326 | consistent_sync((void *)dma_to_virt(dev, handle), size, dir); | ||
321 | } | 327 | } |
322 | #else | 328 | #else |
323 | extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); | 329 | extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); |
@@ -347,7 +353,8 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, | |||
347 | 353 | ||
348 | for (i = 0; i < nents; i++, sg++) { | 354 | for (i = 0; i < nents; i++, sg++) { |
349 | char *virt = page_address(sg->page) + sg->offset; | 355 | char *virt = page_address(sg->page) + sg->offset; |
350 | consistent_sync(virt, sg->length, dir); | 356 | if (!arch_is_coherent()) |
357 | consistent_sync(virt, sg->length, dir); | ||
351 | } | 358 | } |
352 | } | 359 | } |
353 | 360 | ||
@@ -359,7 +366,8 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, | |||
359 | 366 | ||
360 | for (i = 0; i < nents; i++, sg++) { | 367 | for (i = 0; i < nents; i++, sg++) { |
361 | char *virt = page_address(sg->page) + sg->offset; | 368 | char *virt = page_address(sg->page) + sg->offset; |
362 | consistent_sync(virt, sg->length, dir); | 369 | if (!arch_is_coherent()) |
370 | consistent_sync(virt, sg->length, dir); | ||
363 | } | 371 | } |
364 | } | 372 | } |
365 | #else | 373 | #else |
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index afa5c3ea077c..2b3cf69b3ed9 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h | |||
@@ -234,6 +234,14 @@ static inline __deprecated void *bus_to_virt(unsigned long x) | |||
234 | #define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) | 234 | #define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) |
235 | #endif | 235 | #endif |
236 | 236 | ||
237 | /* | ||
238 | * Optional coherency support. Currently used only by selected | ||
239 | * Intel XSC3-based systems. | ||
240 | */ | ||
241 | #ifndef arch_is_coherent | ||
242 | #define arch_is_coherent() 0 | ||
243 | #endif | ||
244 | |||
237 | #endif | 245 | #endif |
238 | 246 | ||
239 | #include <asm-generic/memory_model.h> | 247 | #include <asm-generic/memory_model.h> |
diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h index 1d033495cc75..1bc1f997bda2 100644 --- a/include/asm-arm/pgtable-hwdef.h +++ b/include/asm-arm/pgtable-hwdef.h | |||
@@ -73,6 +73,7 @@ | |||
73 | #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) | 73 | #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) |
74 | #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ | 74 | #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ |
75 | #define PTE_EXT_APX (1 << 9) /* v6 */ | 75 | #define PTE_EXT_APX (1 << 9) /* v6 */ |
76 | #define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ | ||
76 | #define PTE_EXT_SHARED (1 << 10) /* v6 */ | 77 | #define PTE_EXT_SHARED (1 << 10) /* v6 */ |
77 | #define PTE_EXT_NG (1 << 11) /* v6 */ | 78 | #define PTE_EXT_NG (1 << 11) /* v6 */ |
78 | 79 | ||
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index e595ae24efe2..e85c08d78dda 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h | |||
@@ -156,6 +156,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); | |||
156 | #define L_PTE_WRITE (1 << 5) | 156 | #define L_PTE_WRITE (1 << 5) |
157 | #define L_PTE_EXEC (1 << 6) | 157 | #define L_PTE_EXEC (1 << 6) |
158 | #define L_PTE_DIRTY (1 << 7) | 158 | #define L_PTE_DIRTY (1 << 7) |
159 | #define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ | ||
159 | #define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ | 160 | #define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ |
160 | #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ | 161 | #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ |
161 | 162 | ||