7 files changed, 443 insertions, 10 deletions

diff --git a/include/asm-powerpc/cell-regs.h b/include/asm-powerpc/cell-regs.h
new file mode 100644
index 000000000000..fd6fd00434ef
--- /dev/null
+++ b/include/asm-powerpc/cell-regs.h
@@ -0,0 +1,315 @@
+/*
+ * cbe_regs.h
+ *
+ * This file is intended to hold the various register definitions for CBE
+ * on-chip system devices (memory controller, IO controller, etc...)
+ *
+ * (C) Copyright IBM Corporation 2001,2006
+ *
+ * Authors: Maximino Aguilar (maguilar@us.ibm.com)
+ *          David J. Erb (djerb@us.ibm.com)
+ *
+ * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ */
+
+#ifndef CBE_REGS_H
+#define CBE_REGS_H
+
+#include <asm/cell-pmu.h>
+
+/*
+ *
+ * Some HID register definitions
+ *
+ */
+
+/* CBE specific HID0 bits */
+#define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
+#define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
+#define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
+#define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
+
+#define MAX_CBE         2
+
+/*
+ *
+ * Pervasive unit register definitions
+ *
+ */
+
+union spe_reg {
+        u64 val;
+        u8 spe[8];
+};
+
+union ppe_spe_reg {
+        u64 val;
+        struct {
+                u32 ppe;
+                u32 spe;
+        };
+};
+
+
+struct cbe_pmd_regs {
+        /* Debug Bus Control */
+        u64     pad_0x0000;                                     /* 0x0000 */
+
+        u64     group_control;                                  /* 0x0008 */
+
+        u8      pad_0x0010_0x00a8 [0x00a8 - 0x0010];            /* 0x0010 */
+
+        u64     debug_bus_control;                              /* 0x00a8 */
+
+        u8      pad_0x00b0_0x0100 [0x0100 - 0x00b0];            /* 0x00b0 */
+
+        u64     trace_aux_data;                                 /* 0x0100 */
+        u64     trace_buffer_0_63;                              /* 0x0108 */
+        u64     trace_buffer_64_127;                            /* 0x0110 */
+        u64     trace_address;                                  /* 0x0118 */
+        u64     ext_tr_timer;                                   /* 0x0120 */
+
+        u8      pad_0x0128_0x0400 [0x0400 - 0x0128];            /* 0x0128 */
+
+        /* Performance Monitor */
+        u64     pm_status;                                      /* 0x0400 */
+        u64     pm_control;                                     /* 0x0408 */
+        u64     pm_interval;                                    /* 0x0410 */
+        u64     pm_ctr[4];                                      /* 0x0418 */
+        u64     pm_start_stop;                                  /* 0x0438 */
+        u64     pm07_control[8];                                /* 0x0440 */
+
+        u8      pad_0x0480_0x0800 [0x0800 - 0x0480];            /* 0x0480 */
+
+        /* Thermal Sensor Registers */
+        union   spe_reg ts_ctsr1;                               /* 0x0800 */
+        u64     ts_ctsr2;                                       /* 0x0808 */
+        union   spe_reg ts_mtsr1;                               /* 0x0810 */
+        u64     ts_mtsr2;                                       /* 0x0818 */
+        union   spe_reg ts_itr1;                                /* 0x0820 */
+        u64     ts_itr2;                                        /* 0x0828 */
+        u64     ts_gitr;                                        /* 0x0830 */
+        u64     ts_isr;                                         /* 0x0838 */
+        u64     ts_imr;                                         /* 0x0840 */
+        union   spe_reg tm_cr1;                                 /* 0x0848 */
+        u64     tm_cr2;                                         /* 0x0850 */
+        u64     tm_simr;                                        /* 0x0858 */
+        union   ppe_spe_reg tm_tpr;                             /* 0x0860 */
+        union   spe_reg tm_str1;                                /* 0x0868 */
+        u64     tm_str2;                                        /* 0x0870 */
+        union   ppe_spe_reg tm_tsr;                             /* 0x0878 */
+
+        /* Power Management */
+        u64     pmcr;                                           /* 0x0880 */
+#define CBE_PMD_PAUSE_ZERO_CONTROL      0x10000
+        u64     pmsr;                                           /* 0x0888 */
+
+        /* Time Base Register */
+        u64     tbr;                                            /* 0x0890 */
+
+        u8      pad_0x0898_0x0c00 [0x0c00 - 0x0898];            /* 0x0898 */
+
+        /* Fault Isolation Registers */
+        u64     checkstop_fir;                                  /* 0x0c00 */
+        u64     recoverable_fir;                                /* 0x0c08 */
+        u64     spec_att_mchk_fir;                              /* 0x0c10 */
+        u32     fir_mode_reg;                                   /* 0x0c18 */
+        u8      pad_0x0c1c_0x0c20 [4];                          /* 0x0c1c */
+#define CBE_PMD_FIR_MODE_M8             0x00800
+        u64     fir_enable_mask;                                /* 0x0c20 */
+
+        u8      pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];            /* 0x0c28 */
+        u64     ras_esc_0;                                      /* 0x0ca8 */
+        u8      pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];            /* 0x0cb0 */
+};
+
+extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
+extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
+
+/*
+ * PMU shadow registers
+ *
+ * Many of the registers in the performance monitoring unit are write-only,
+ * so we need to save a copy of what we write to those registers.
+ *
+ * The actual data counters are read/write. However, writing to the counters
+ * only takes effect if the PMU is enabled. Otherwise the value is stored in
+ * a hardware latch until the next time the PMU is enabled. So we save a copy
+ * of the counter values if we need to read them back while the PMU is
+ * disabled. The counter_value_in_latch field is a bitmap indicating which
+ * counters currently have a value waiting to be written.
+ */
+
+struct cbe_pmd_shadow_regs {
+        u32 group_control;
+        u32 debug_bus_control;
+        u32 trace_address;
+        u32 ext_tr_timer;
+        u32 pm_status;
+        u32 pm_control;
+        u32 pm_interval;
+        u32 pm_start_stop;
+        u32 pm07_control[NR_CTRS];
+
+        u32 pm_ctr[NR_PHYS_CTRS];
+        u32 counter_value_in_latch;
+};
+
+extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
+extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
+
+/*
+ *
+ * IIC unit register definitions
+ *
+ */
+
+struct cbe_iic_pending_bits {
+        u32 data;
+        u8 flags;
+        u8 class;
+        u8 source;
+        u8 prio;
+};
+
+#define CBE_IIC_IRQ_VALID       0x80
+#define CBE_IIC_IRQ_IPI         0x40
+
+struct cbe_iic_thread_regs {
+        struct cbe_iic_pending_bits pending;
+        struct cbe_iic_pending_bits pending_destr;
+        u64 generate;
+        u64 prio;
+};
+
+struct cbe_iic_regs {
+        u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
+
+        /* IIC interrupt registers */
+        struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
+
+        u64     iic_ir;                                         /* 0x0440 */
+#define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
+#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
+#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
+#define CBE_IIC_IR_IOC_0        0x0
+#define CBE_IIC_IR_IOC_1S       0xb
+#define CBE_IIC_IR_PT_0         0xe
+#define CBE_IIC_IR_PT_1         0xf
+
+        u64     iic_is;                                         /* 0x0448 */
+#define CBE_IIC_IS_PMI          0x2
+
+        u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
+
+        /* IOC FIR */
+        u64     ioc_fir_reset;                                  /* 0x0500 */
+        u64     ioc_fir_set;                                    /* 0x0508 */
+        u64     ioc_checkstop_enable;                           /* 0x0510 */
+        u64     ioc_fir_error_mask;                             /* 0x0518 */
+        u64     ioc_syserr_enable;                              /* 0x0520 */
+        u64     ioc_fir;                                        /* 0x0528 */
+
+        u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
+};
+
+extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
+extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
+
+
+struct cbe_mic_tm_regs {
+        u8      pad_0x0000_0x0040[0x0040 - 0x0000];             /* 0x0000 */
+
+        u64     mic_ctl_cnfg2;                                  /* 0x0040 */
+#define CBE_MIC_ENABLE_AUX_TRC          0x8000000000000000LL
+#define CBE_MIC_DISABLE_PWR_SAV_2       0x0200000000000000LL
+#define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
+#define CBE_MIC_ENABLE_AUX_TRC_INT      0x0080000000000000LL
+
+        u64     pad_0x0048;                                     /* 0x0048 */
+
+        u64     mic_aux_trc_base;                               /* 0x0050 */
+        u64     mic_aux_trc_max_addr;                           /* 0x0058 */
+        u64     mic_aux_trc_cur_addr;                           /* 0x0060 */
+        u64     mic_aux_trc_grf_addr;                           /* 0x0068 */
+        u64     mic_aux_trc_grf_data;                           /* 0x0070 */
+
+        u64     pad_0x0078;                                     /* 0x0078 */
+
+        u64     mic_ctl_cnfg_0;                                 /* 0x0080 */
+#define CBE_MIC_DISABLE_PWR_SAV_0       0x8000000000000000LL
+
+        u64     pad_0x0088;                                     /* 0x0088 */
+
+        u64     slow_fast_timer_0;                              /* 0x0090 */
+        u64     slow_next_timer_0;                              /* 0x0098 */
+
+        u8      pad_0x00a0_0x00f8[0x00f8 - 0x00a0];             /* 0x00a0 */
+        u64     mic_df_ecc_address_0;                           /* 0x00f8 */
+
+        u8      pad_0x0100_0x01b8[0x01b8 - 0x0100];             /* 0x0100 */
+        u64     mic_df_ecc_address_1;                           /* 0x01b8 */
+
+        u64     mic_ctl_cnfg_1;                                 /* 0x01c0 */
+#define CBE_MIC_DISABLE_PWR_SAV_1       0x8000000000000000LL
+
+        u64     pad_0x01c8;                                     /* 0x01c8 */
+
+        u64     slow_fast_timer_1;                              /* 0x01d0 */
+        u64     slow_next_timer_1;                              /* 0x01d8 */
+
+        u8      pad_0x01e0_0x0208[0x0208 - 0x01e0];             /* 0x01e0 */
+        u64     mic_exc;                                        /* 0x0208 */
+#define CBE_MIC_EXC_BLOCK_SCRUB         0x0800000000000000ULL
+#define CBE_MIC_EXC_FAST_SCRUB          0x0100000000000000ULL
+
+        u64     mic_mnt_cfg;                                    /* 0x0210 */
+#define CBE_MIC_MNT_CFG_CHAN_0_POP      0x0002000000000000ULL
+#define CBE_MIC_MNT_CFG_CHAN_1_POP      0x0004000000000000ULL
+
+        u64     mic_df_config;                                  /* 0x0218 */
+#define CBE_MIC_ECC_DISABLE_0           0x4000000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_0        0x2000000000000000ULL
+#define CBE_MIC_ECC_DISABLE_1           0x0080000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_1        0x0040000000000000ULL
+
+        u8      pad_0x0220_0x0230[0x0230 - 0x0220];             /* 0x0220 */
+        u64     mic_fir;                                        /* 0x0230 */
+#define CBE_MIC_FIR_ECC_SINGLE_0_ERR    0x0200000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_ERR     0x0100000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_ERR    0x0080000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_ERR     0x0040000000000000ULL
+#define CBE_MIC_FIR_ECC_ERR_MASK        0xffff000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_CTE    0x0000020000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_CTE     0x0000010000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_CTE    0x0000008000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_CTE     0x0000004000000000ULL
+#define CBE_MIC_FIR_ECC_CTE_MASK        0x0000ffff00000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_RESET  0x0000000002000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_RESET   0x0000000001000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_RESET  0x0000000000800000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_RESET   0x0000000000400000ULL
+#define CBE_MIC_FIR_ECC_RESET_MASK      0x00000000ffff0000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_SET    0x0000000000000200ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_SET     0x0000000000000100ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_SET    0x0000000000000080ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_SET     0x0000000000000040ULL
+#define CBE_MIC_FIR_ECC_SET_MASK        0x000000000000ffffULL
+        u64     mic_fir_debug;                                  /* 0x0238 */
+
+        u8      pad_0x0240_0x1000[0x1000 - 0x0240];             /* 0x0240 */
+};
+
+extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
+extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
+
+/* some utility functions to deal with SMT */
+extern u32 cbe_get_hw_thread_id(int cpu);
+extern u32 cbe_cpu_to_node(int cpu);
+extern u32 cbe_node_to_cpu(int node);
+
+/* Init this module early */
+extern void cbe_regs_init(void);
+
+
+#endif /* CBE_REGS_H */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index c9b8f64bbb45..d913f460e710 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -57,6 +57,7 @@ enum powerpc_pmc_type {
         PPC_PMC_PA6T = 2,
 };
 
+/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
 struct cpu_spec {
         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
         unsigned int    pvr_mask;
diff --git a/include/asm-powerpc/iseries/hv_call_event.h b/include/asm-powerpc/iseries/hv_call_event.h
index 4cec4762076d..cc029d388e11 100644
--- a/include/asm-powerpc/iseries/hv_call_event.h
+++ b/include/asm-powerpc/iseries/hv_call_event.h
@@ -21,6 +21,9 @@
 #ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
 #define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
 
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+
 #include <asm/iseries/hv_call_sc.h>
 #include <asm/iseries/hv_types.h>
 #include <asm/abs_addr.h>
@@ -113,6 +116,13 @@ static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
                         eventData3, eventData4, eventData5);
 }
 
+extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag);
+extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle);
+extern dma_addr_t iseries_hv_map(void *vaddr, size_t size,
+                        enum dma_data_direction direction);
+extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
+                        enum dma_data_direction direction);
+
 static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
 {
         return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event));
diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h
index 6e323a13ac30..c59ee7e4bed1 100644
--- a/include/asm-powerpc/iseries/iommu.h
+++ b/include/asm-powerpc/iseries/iommu.h
@@ -22,6 +22,7 @@
  */
 
 struct pci_dev;
+struct vio_dev;
 struct device_node;
 struct iommu_table;
 
@@ -34,4 +35,7 @@ extern void iommu_table_getparms_iSeries(unsigned long busno,
                 unsigned char slotno, unsigned char virtbus,
                 struct iommu_table *tbl);
 
+extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev);
+extern void iommu_vio_init(void);
+
 #endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/include/asm-powerpc/iseries/vio.h b/include/asm-powerpc/iseries/vio.h
index 7a95d296abd1..f9ac0d00b951 100644
--- a/include/asm-powerpc/iseries/vio.h
+++ b/include/asm-powerpc/iseries/vio.h
@@ -51,6 +51,116 @@
  */
 #define VIO_MAX_SUBTYPES 8
 
+#define VIOMAXBLOCKDMA  12
+
+struct open_data {
+        u64     disk_size;
+        u16     max_disk;
+        u16     cylinders;
+        u16     tracks;
+        u16     sectors;
+        u16     bytes_per_sector;
+};
+
+struct rw_data {
+        u64     offset;
+        struct {
+                u32     token;
+                u32     reserved;
+                u64     len;
+        } dma_info[VIOMAXBLOCKDMA];
+};
+
+struct vioblocklpevent {
+        struct HvLpEvent        event;
+        u32                     reserved;
+        u16                     version;
+        u16                     sub_result;
+        u16                     disk;
+        u16                     flags;
+        union {
+                struct open_data        open_data;
+                struct rw_data          rw_data;
+                u64                     changed;
+        } u;
+};
+
+#define vioblockflags_ro   0x0001
+
+enum vioblocksubtype {
+        vioblockopen = 0x0001,
+        vioblockclose = 0x0002,
+        vioblockread = 0x0003,
+        vioblockwrite = 0x0004,
+        vioblockflush = 0x0005,
+        vioblockcheck = 0x0007
+};
+
+struct viocdlpevent {
+        struct HvLpEvent        event;
+        u32                     reserved;
+        u16                     version;
+        u16                     sub_result;
+        u16                     disk;
+        u16                     flags;
+        u32                     token;
+        u64                     offset;         /* On open, max number of disks */
+        u64                     len;            /* On open, size of the disk */
+        u32                     block_size;     /* Only set on open */
+        u32                     media_size;     /* Only set on open */
+};
+
+enum viocdsubtype {
+        viocdopen = 0x0001,
+        viocdclose = 0x0002,
+        viocdread = 0x0003,
+        viocdwrite = 0x0004,
+        viocdlockdoor = 0x0005,
+        viocdgetinfo = 0x0006,
+        viocdcheck = 0x0007
+};
+
+struct viotapelpevent {
+        struct HvLpEvent event;
+        u32 reserved;
+        u16 version;
+        u16 sub_type_result;
+        u16 tape;
+        u16 flags;
+        u32 token;
+        u64 len;
+        union {
+                struct {
+                        u32 tape_op;
+                        u32 count;
+                } op;
+                struct {
+                        u32 type;
+                        u32 resid;
+                        u32 dsreg;
+                        u32 gstat;
+                        u32 erreg;
+                        u32 file_no;
+                        u32 block_no;
+                } get_status;
+                struct {
+                        u32 block_no;
+                } get_pos;
+        } u;
+};
+
+enum viotapesubtype {
+        viotapeopen = 0x0001,
+        viotapeclose = 0x0002,
+        viotaperead = 0x0003,
+        viotapewrite = 0x0004,
+        viotapegetinfo = 0x0005,
+        viotapeop = 0x0006,
+        viotapegetpos = 0x0007,
+        viotapesetpos = 0x0008,
+        viotapegetstatus = 0x0009
+};
+
 /*
  * Each subtype can register a handler to process their events.
  * The handler must have this interface.
@@ -68,6 +178,8 @@ extern void vio_set_hostlp(void);
 extern void *vio_get_event_buffer(int subtype);
 extern void vio_free_event_buffer(int subtype, void *buffer);
 
+extern struct vio_dev *vio_create_viodasd(u32 unit);
+
 extern HvLpIndex viopath_hostLp;
 extern HvLpIndex viopath_ourLp;
 
@@ -150,8 +262,4 @@ enum viochar_rc {
         viochar_rc_ebusy = 1
 };
 
-struct device;
-
-extern struct device *iSeries_vio_dev;
-
 #endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 71c6e7eb2a26..cc7c17f16a9a 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -99,7 +99,7 @@ struct machdep_calls {
 #endif /* CONFIG_PPC64 */
 
         int             (*probe)(void);
-        void            (*setup_arch)(void);
+        void            (*setup_arch)(void); /* Optional, may be NULL */
         void            (*init_early)(void);
         /* Optional, may be NULL. */
         void            (*show_cpuinfo)(struct seq_file *m);
diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h
index 598d111e8098..9204c15839c5 100644
--- a/include/asm-powerpc/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -53,17 +53,12 @@ struct vio_dev {
 };
 
 struct vio_driver {
-        struct list_head node;
         const struct vio_device_id *id_table;
         int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
         int (*remove)(struct vio_dev *dev);
-        void (*shutdown)(struct vio_dev *dev);
-        unsigned long driver_data;
         struct device_driver driver;
 };
 
-extern struct dma_mapping_ops vio_dma_ops;
-
 extern int vio_register_driver(struct vio_driver *drv);
 extern void vio_unregister_driver(struct vio_driver *drv);