diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/Kbuild | 1 | ||||
-rw-r--r-- | include/drm/Kbuild | 10 | ||||
-rw-r--r-- | include/drm/drm.h | 694 | ||||
-rw-r--r-- | include/drm/drmP.h | 1153 | ||||
-rw-r--r-- | include/drm/drm_core.h | 34 | ||||
-rw-r--r-- | include/drm/drm_hashtab.h | 67 | ||||
-rw-r--r-- | include/drm/drm_memory.h | 61 | ||||
-rw-r--r-- | include/drm/drm_memory_debug.h | 309 | ||||
-rw-r--r-- | include/drm/drm_os_linux.h | 108 | ||||
-rw-r--r-- | include/drm/drm_pciids.h | 415 | ||||
-rw-r--r-- | include/drm/drm_sarea.h | 84 | ||||
-rw-r--r-- | include/drm/drm_sman.h | 176 | ||||
-rw-r--r-- | include/drm/i810_drm.h | 281 | ||||
-rw-r--r-- | include/drm/i830_drm.h | 342 | ||||
-rw-r--r-- | include/drm/i915_drm.h | 270 | ||||
-rw-r--r-- | include/drm/mga_drm.h | 417 | ||||
-rw-r--r-- | include/drm/r128_drm.h | 326 | ||||
-rw-r--r-- | include/drm/radeon_drm.h | 749 | ||||
-rw-r--r-- | include/drm/savage_drm.h | 210 | ||||
-rw-r--r-- | include/drm/sis_drm.h | 67 | ||||
-rw-r--r-- | include/drm/via_drm.h | 275 |
21 files changed, 6049 insertions, 0 deletions
diff --git a/include/Kbuild b/include/Kbuild index b52288774345..bdca155028ec 100644 --- a/include/Kbuild +++ b/include/Kbuild | |||
@@ -4,5 +4,6 @@ header-y += sound/ | |||
4 | header-y += mtd/ | 4 | header-y += mtd/ |
5 | header-y += rdma/ | 5 | header-y += rdma/ |
6 | header-y += video/ | 6 | header-y += video/ |
7 | header-y += drm/ | ||
7 | 8 | ||
8 | header-y += asm-$(ARCH)/ | 9 | header-y += asm-$(ARCH)/ |
diff --git a/include/drm/Kbuild b/include/drm/Kbuild new file mode 100644 index 000000000000..82b6983b7fbb --- /dev/null +++ b/include/drm/Kbuild | |||
@@ -0,0 +1,10 @@ | |||
1 | unifdef-y += drm.h drm_sarea.h | ||
2 | unifdef-y += i810_drm.h | ||
3 | unifdef-y += i830_drm.h | ||
4 | unifdef-y += i915_drm.h | ||
5 | unifdef-y += mga_drm.h | ||
6 | unifdef-y += r128_drm.h | ||
7 | unifdef-y += radeon_drm.h | ||
8 | unifdef-y += sis_drm.h | ||
9 | unifdef-y += savage_drm.h | ||
10 | unifdef-y += via_drm.h | ||
diff --git a/include/drm/drm.h b/include/drm/drm.h new file mode 100644 index 000000000000..38d3c6b8276a --- /dev/null +++ b/include/drm/drm.h | |||
@@ -0,0 +1,694 @@ | |||
1 | /** | ||
2 | * \file drm.h | ||
3 | * Header for the Direct Rendering Manager | ||
4 | * | ||
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> | ||
6 | * | ||
7 | * \par Acknowledgments: | ||
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | ||
9 | */ | ||
10 | |||
11 | /* | ||
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | ||
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
14 | * All rights reserved. | ||
15 | * | ||
16 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
17 | * copy of this software and associated documentation files (the "Software"), | ||
18 | * to deal in the Software without restriction, including without limitation | ||
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
20 | * and/or sell copies of the Software, and to permit persons to whom the | ||
21 | * Software is furnished to do so, subject to the following conditions: | ||
22 | * | ||
23 | * The above copyright notice and this permission notice (including the next | ||
24 | * paragraph) shall be included in all copies or substantial portions of the | ||
25 | * Software. | ||
26 | * | ||
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
33 | * OTHER DEALINGS IN THE SOFTWARE. | ||
34 | */ | ||
35 | |||
36 | #ifndef _DRM_H_ | ||
37 | #define _DRM_H_ | ||
38 | |||
39 | #if defined(__linux__) | ||
40 | #if defined(__KERNEL__) | ||
41 | #endif | ||
42 | #include <asm/ioctl.h> /* For _IO* macros */ | ||
43 | #define DRM_IOCTL_NR(n) _IOC_NR(n) | ||
44 | #define DRM_IOC_VOID _IOC_NONE | ||
45 | #define DRM_IOC_READ _IOC_READ | ||
46 | #define DRM_IOC_WRITE _IOC_WRITE | ||
47 | #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE | ||
48 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | ||
49 | #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) | ||
50 | #if defined(__FreeBSD__) && defined(IN_MODULE) | ||
51 | /* Prevent name collision when including sys/ioccom.h */ | ||
52 | #undef ioctl | ||
53 | #include <sys/ioccom.h> | ||
54 | #define ioctl(a,b,c) xf86ioctl(a,b,c) | ||
55 | #else | ||
56 | #include <sys/ioccom.h> | ||
57 | #endif /* __FreeBSD__ && xf86ioctl */ | ||
58 | #define DRM_IOCTL_NR(n) ((n) & 0xff) | ||
59 | #define DRM_IOC_VOID IOC_VOID | ||
60 | #define DRM_IOC_READ IOC_OUT | ||
61 | #define DRM_IOC_WRITE IOC_IN | ||
62 | #define DRM_IOC_READWRITE IOC_INOUT | ||
63 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | ||
64 | #endif | ||
65 | |||
66 | #define DRM_MAJOR 226 | ||
67 | #define DRM_MAX_MINOR 15 | ||
68 | |||
69 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ | ||
70 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | ||
71 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | ||
72 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | ||
73 | |||
74 | #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ | ||
75 | #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ | ||
76 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) | ||
77 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | ||
78 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | ||
79 | |||
80 | typedef unsigned int drm_handle_t; | ||
81 | typedef unsigned int drm_context_t; | ||
82 | typedef unsigned int drm_drawable_t; | ||
83 | typedef unsigned int drm_magic_t; | ||
84 | |||
85 | /** | ||
86 | * Cliprect. | ||
87 | * | ||
88 | * \warning: If you change this structure, make sure you change | ||
89 | * XF86DRIClipRectRec in the server as well | ||
90 | * | ||
91 | * \note KW: Actually it's illegal to change either for | ||
92 | * backwards-compatibility reasons. | ||
93 | */ | ||
94 | struct drm_clip_rect { | ||
95 | unsigned short x1; | ||
96 | unsigned short y1; | ||
97 | unsigned short x2; | ||
98 | unsigned short y2; | ||
99 | }; | ||
100 | |||
101 | /** | ||
102 | * Drawable information. | ||
103 | */ | ||
104 | struct drm_drawable_info { | ||
105 | unsigned int num_rects; | ||
106 | struct drm_clip_rect *rects; | ||
107 | }; | ||
108 | |||
109 | /** | ||
110 | * Texture region, | ||
111 | */ | ||
112 | struct drm_tex_region { | ||
113 | unsigned char next; | ||
114 | unsigned char prev; | ||
115 | unsigned char in_use; | ||
116 | unsigned char padding; | ||
117 | unsigned int age; | ||
118 | }; | ||
119 | |||
120 | /** | ||
121 | * Hardware lock. | ||
122 | * | ||
123 | * The lock structure is a simple cache-line aligned integer. To avoid | ||
124 | * processor bus contention on a multiprocessor system, there should not be any | ||
125 | * other data stored in the same cache line. | ||
126 | */ | ||
127 | struct drm_hw_lock { | ||
128 | __volatile__ unsigned int lock; /**< lock variable */ | ||
129 | char padding[60]; /**< Pad to cache line */ | ||
130 | }; | ||
131 | |||
132 | /** | ||
133 | * DRM_IOCTL_VERSION ioctl argument type. | ||
134 | * | ||
135 | * \sa drmGetVersion(). | ||
136 | */ | ||
137 | struct drm_version { | ||
138 | int version_major; /**< Major version */ | ||
139 | int version_minor; /**< Minor version */ | ||
140 | int version_patchlevel; /**< Patch level */ | ||
141 | size_t name_len; /**< Length of name buffer */ | ||
142 | char __user *name; /**< Name of driver */ | ||
143 | size_t date_len; /**< Length of date buffer */ | ||
144 | char __user *date; /**< User-space buffer to hold date */ | ||
145 | size_t desc_len; /**< Length of desc buffer */ | ||
146 | char __user *desc; /**< User-space buffer to hold desc */ | ||
147 | }; | ||
148 | |||
149 | /** | ||
150 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | ||
151 | * | ||
152 | * \sa drmGetBusid() and drmSetBusId(). | ||
153 | */ | ||
154 | struct drm_unique { | ||
155 | size_t unique_len; /**< Length of unique */ | ||
156 | char __user *unique; /**< Unique name for driver instantiation */ | ||
157 | }; | ||
158 | |||
159 | struct drm_list { | ||
160 | int count; /**< Length of user-space structures */ | ||
161 | struct drm_version __user *version; | ||
162 | }; | ||
163 | |||
164 | struct drm_block { | ||
165 | int unused; | ||
166 | }; | ||
167 | |||
168 | /** | ||
169 | * DRM_IOCTL_CONTROL ioctl argument type. | ||
170 | * | ||
171 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | ||
172 | */ | ||
173 | struct drm_control { | ||
174 | enum { | ||
175 | DRM_ADD_COMMAND, | ||
176 | DRM_RM_COMMAND, | ||
177 | DRM_INST_HANDLER, | ||
178 | DRM_UNINST_HANDLER | ||
179 | } func; | ||
180 | int irq; | ||
181 | }; | ||
182 | |||
183 | /** | ||
184 | * Type of memory to map. | ||
185 | */ | ||
186 | enum drm_map_type { | ||
187 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ | ||
188 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | ||
189 | _DRM_SHM = 2, /**< shared, cached */ | ||
190 | _DRM_AGP = 3, /**< AGP/GART */ | ||
191 | _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ | ||
192 | _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ | ||
193 | }; | ||
194 | |||
195 | /** | ||
196 | * Memory mapping flags. | ||
197 | */ | ||
198 | enum drm_map_flags { | ||
199 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ | ||
200 | _DRM_READ_ONLY = 0x02, | ||
201 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | ||
202 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | ||
203 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ | ||
204 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ | ||
205 | _DRM_REMOVABLE = 0x40, /**< Removable mapping */ | ||
206 | _DRM_DRIVER = 0x80 /**< Managed by driver */ | ||
207 | }; | ||
208 | |||
209 | struct drm_ctx_priv_map { | ||
210 | unsigned int ctx_id; /**< Context requesting private mapping */ | ||
211 | void *handle; /**< Handle of map */ | ||
212 | }; | ||
213 | |||
214 | /** | ||
215 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | ||
216 | * argument type. | ||
217 | * | ||
218 | * \sa drmAddMap(). | ||
219 | */ | ||
220 | struct drm_map { | ||
221 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ | ||
222 | unsigned long size; /**< Requested physical size (bytes) */ | ||
223 | enum drm_map_type type; /**< Type of memory to map */ | ||
224 | enum drm_map_flags flags; /**< Flags */ | ||
225 | void *handle; /**< User-space: "Handle" to pass to mmap() */ | ||
226 | /**< Kernel-space: kernel-virtual address */ | ||
227 | int mtrr; /**< MTRR slot used */ | ||
228 | /* Private data */ | ||
229 | }; | ||
230 | |||
231 | /** | ||
232 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | ||
233 | */ | ||
234 | struct drm_client { | ||
235 | int idx; /**< Which client desired? */ | ||
236 | int auth; /**< Is client authenticated? */ | ||
237 | unsigned long pid; /**< Process ID */ | ||
238 | unsigned long uid; /**< User ID */ | ||
239 | unsigned long magic; /**< Magic */ | ||
240 | unsigned long iocs; /**< Ioctl count */ | ||
241 | }; | ||
242 | |||
243 | enum drm_stat_type { | ||
244 | _DRM_STAT_LOCK, | ||
245 | _DRM_STAT_OPENS, | ||
246 | _DRM_STAT_CLOSES, | ||
247 | _DRM_STAT_IOCTLS, | ||
248 | _DRM_STAT_LOCKS, | ||
249 | _DRM_STAT_UNLOCKS, | ||
250 | _DRM_STAT_VALUE, /**< Generic value */ | ||
251 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | ||
252 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | ||
253 | |||
254 | _DRM_STAT_IRQ, /**< IRQ */ | ||
255 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | ||
256 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | ||
257 | _DRM_STAT_DMA, /**< DMA */ | ||
258 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | ||
259 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | ||
260 | /* Add to the *END* of the list */ | ||
261 | }; | ||
262 | |||
263 | /** | ||
264 | * DRM_IOCTL_GET_STATS ioctl argument type. | ||
265 | */ | ||
266 | struct drm_stats { | ||
267 | unsigned long count; | ||
268 | struct { | ||
269 | unsigned long value; | ||
270 | enum drm_stat_type type; | ||
271 | } data[15]; | ||
272 | }; | ||
273 | |||
274 | /** | ||
275 | * Hardware locking flags. | ||
276 | */ | ||
277 | enum drm_lock_flags { | ||
278 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ | ||
279 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | ||
280 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | ||
281 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | ||
282 | /* These *HALT* flags aren't supported yet | ||
283 | -- they will be used to support the | ||
284 | full-screen DGA-like mode. */ | ||
285 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ | ||
286 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | ||
287 | }; | ||
288 | |||
289 | /** | ||
290 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | ||
291 | * | ||
292 | * \sa drmGetLock() and drmUnlock(). | ||
293 | */ | ||
294 | struct drm_lock { | ||
295 | int context; | ||
296 | enum drm_lock_flags flags; | ||
297 | }; | ||
298 | |||
299 | /** | ||
300 | * DMA flags | ||
301 | * | ||
302 | * \warning | ||
303 | * These values \e must match xf86drm.h. | ||
304 | * | ||
305 | * \sa drm_dma. | ||
306 | */ | ||
307 | enum drm_dma_flags { | ||
308 | /* Flags for DMA buffer dispatch */ | ||
309 | _DRM_DMA_BLOCK = 0x01, /**< | ||
310 | * Block until buffer dispatched. | ||
311 | * | ||
312 | * \note The buffer may not yet have | ||
313 | * been processed by the hardware -- | ||
314 | * getting a hardware lock with the | ||
315 | * hardware quiescent will ensure | ||
316 | * that the buffer has been | ||
317 | * processed. | ||
318 | */ | ||
319 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | ||
320 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ | ||
321 | |||
322 | /* Flags for DMA buffer request */ | ||
323 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | ||
324 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | ||
325 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | ||
326 | }; | ||
327 | |||
328 | /** | ||
329 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | ||
330 | * | ||
331 | * \sa drmAddBufs(). | ||
332 | */ | ||
333 | struct drm_buf_desc { | ||
334 | int count; /**< Number of buffers of this size */ | ||
335 | int size; /**< Size in bytes */ | ||
336 | int low_mark; /**< Low water mark */ | ||
337 | int high_mark; /**< High water mark */ | ||
338 | enum { | ||
339 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ | ||
340 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | ||
341 | _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ | ||
342 | _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ | ||
343 | _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ | ||
344 | } flags; | ||
345 | unsigned long agp_start; /**< | ||
346 | * Start address of where the AGP buffers are | ||
347 | * in the AGP aperture | ||
348 | */ | ||
349 | }; | ||
350 | |||
351 | /** | ||
352 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | ||
353 | */ | ||
354 | struct drm_buf_info { | ||
355 | int count; /**< Entries in list */ | ||
356 | struct drm_buf_desc __user *list; | ||
357 | }; | ||
358 | |||
359 | /** | ||
360 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | ||
361 | */ | ||
362 | struct drm_buf_free { | ||
363 | int count; | ||
364 | int __user *list; | ||
365 | }; | ||
366 | |||
367 | /** | ||
368 | * Buffer information | ||
369 | * | ||
370 | * \sa drm_buf_map. | ||
371 | */ | ||
372 | struct drm_buf_pub { | ||
373 | int idx; /**< Index into the master buffer list */ | ||
374 | int total; /**< Buffer size */ | ||
375 | int used; /**< Amount of buffer in use (for DMA) */ | ||
376 | void __user *address; /**< Address of buffer */ | ||
377 | }; | ||
378 | |||
379 | /** | ||
380 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | ||
381 | */ | ||
382 | struct drm_buf_map { | ||
383 | int count; /**< Length of the buffer list */ | ||
384 | void __user *virtual; /**< Mmap'd area in user-virtual */ | ||
385 | struct drm_buf_pub __user *list; /**< Buffer information */ | ||
386 | }; | ||
387 | |||
388 | /** | ||
389 | * DRM_IOCTL_DMA ioctl argument type. | ||
390 | * | ||
391 | * Indices here refer to the offset into the buffer list in drm_buf_get. | ||
392 | * | ||
393 | * \sa drmDMA(). | ||
394 | */ | ||
395 | struct drm_dma { | ||
396 | int context; /**< Context handle */ | ||
397 | int send_count; /**< Number of buffers to send */ | ||
398 | int __user *send_indices; /**< List of handles to buffers */ | ||
399 | int __user *send_sizes; /**< Lengths of data to send */ | ||
400 | enum drm_dma_flags flags; /**< Flags */ | ||
401 | int request_count; /**< Number of buffers requested */ | ||
402 | int request_size; /**< Desired size for buffers */ | ||
403 | int __user *request_indices; /**< Buffer information */ | ||
404 | int __user *request_sizes; | ||
405 | int granted_count; /**< Number of buffers granted */ | ||
406 | }; | ||
407 | |||
408 | enum drm_ctx_flags { | ||
409 | _DRM_CONTEXT_PRESERVED = 0x01, | ||
410 | _DRM_CONTEXT_2DONLY = 0x02 | ||
411 | }; | ||
412 | |||
413 | /** | ||
414 | * DRM_IOCTL_ADD_CTX ioctl argument type. | ||
415 | * | ||
416 | * \sa drmCreateContext() and drmDestroyContext(). | ||
417 | */ | ||
418 | struct drm_ctx { | ||
419 | drm_context_t handle; | ||
420 | enum drm_ctx_flags flags; | ||
421 | }; | ||
422 | |||
423 | /** | ||
424 | * DRM_IOCTL_RES_CTX ioctl argument type. | ||
425 | */ | ||
426 | struct drm_ctx_res { | ||
427 | int count; | ||
428 | struct drm_ctx __user *contexts; | ||
429 | }; | ||
430 | |||
431 | /** | ||
432 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | ||
433 | */ | ||
434 | struct drm_draw { | ||
435 | drm_drawable_t handle; | ||
436 | }; | ||
437 | |||
438 | /** | ||
439 | * DRM_IOCTL_UPDATE_DRAW ioctl argument type. | ||
440 | */ | ||
441 | typedef enum { | ||
442 | DRM_DRAWABLE_CLIPRECTS, | ||
443 | } drm_drawable_info_type_t; | ||
444 | |||
445 | struct drm_update_draw { | ||
446 | drm_drawable_t handle; | ||
447 | unsigned int type; | ||
448 | unsigned int num; | ||
449 | unsigned long long data; | ||
450 | }; | ||
451 | |||
452 | /** | ||
453 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | ||
454 | */ | ||
455 | struct drm_auth { | ||
456 | drm_magic_t magic; | ||
457 | }; | ||
458 | |||
459 | /** | ||
460 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | ||
461 | * | ||
462 | * \sa drmGetInterruptFromBusID(). | ||
463 | */ | ||
464 | struct drm_irq_busid { | ||
465 | int irq; /**< IRQ number */ | ||
466 | int busnum; /**< bus number */ | ||
467 | int devnum; /**< device number */ | ||
468 | int funcnum; /**< function number */ | ||
469 | }; | ||
470 | |||
471 | enum drm_vblank_seq_type { | ||
472 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ | ||
473 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | ||
474 | _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ | ||
475 | _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ | ||
476 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ | ||
477 | }; | ||
478 | |||
479 | #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) | ||
480 | #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ | ||
481 | _DRM_VBLANK_NEXTONMISS) | ||
482 | |||
483 | struct drm_wait_vblank_request { | ||
484 | enum drm_vblank_seq_type type; | ||
485 | unsigned int sequence; | ||
486 | unsigned long signal; | ||
487 | }; | ||
488 | |||
489 | struct drm_wait_vblank_reply { | ||
490 | enum drm_vblank_seq_type type; | ||
491 | unsigned int sequence; | ||
492 | long tval_sec; | ||
493 | long tval_usec; | ||
494 | }; | ||
495 | |||
496 | /** | ||
497 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | ||
498 | * | ||
499 | * \sa drmWaitVBlank(). | ||
500 | */ | ||
501 | union drm_wait_vblank { | ||
502 | struct drm_wait_vblank_request request; | ||
503 | struct drm_wait_vblank_reply reply; | ||
504 | }; | ||
505 | |||
506 | /** | ||
507 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | ||
508 | * | ||
509 | * \sa drmAgpEnable(). | ||
510 | */ | ||
511 | struct drm_agp_mode { | ||
512 | unsigned long mode; /**< AGP mode */ | ||
513 | }; | ||
514 | |||
515 | /** | ||
516 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | ||
517 | * | ||
518 | * \sa drmAgpAlloc() and drmAgpFree(). | ||
519 | */ | ||
520 | struct drm_agp_buffer { | ||
521 | unsigned long size; /**< In bytes -- will round to page boundary */ | ||
522 | unsigned long handle; /**< Used for binding / unbinding */ | ||
523 | unsigned long type; /**< Type of memory to allocate */ | ||
524 | unsigned long physical; /**< Physical used by i810 */ | ||
525 | }; | ||
526 | |||
527 | /** | ||
528 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | ||
529 | * | ||
530 | * \sa drmAgpBind() and drmAgpUnbind(). | ||
531 | */ | ||
532 | struct drm_agp_binding { | ||
533 | unsigned long handle; /**< From drm_agp_buffer */ | ||
534 | unsigned long offset; /**< In bytes -- will round to page boundary */ | ||
535 | }; | ||
536 | |||
537 | /** | ||
538 | * DRM_IOCTL_AGP_INFO ioctl argument type. | ||
539 | * | ||
540 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | ||
541 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | ||
542 | * drmAgpVendorId() and drmAgpDeviceId(). | ||
543 | */ | ||
544 | struct drm_agp_info { | ||
545 | int agp_version_major; | ||
546 | int agp_version_minor; | ||
547 | unsigned long mode; | ||
548 | unsigned long aperture_base; /* physical address */ | ||
549 | unsigned long aperture_size; /* bytes */ | ||
550 | unsigned long memory_allowed; /* bytes */ | ||
551 | unsigned long memory_used; | ||
552 | |||
553 | /* PCI information */ | ||
554 | unsigned short id_vendor; | ||
555 | unsigned short id_device; | ||
556 | }; | ||
557 | |||
558 | /** | ||
559 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | ||
560 | */ | ||
561 | struct drm_scatter_gather { | ||
562 | unsigned long size; /**< In bytes -- will round to page boundary */ | ||
563 | unsigned long handle; /**< Used for mapping / unmapping */ | ||
564 | }; | ||
565 | |||
566 | /** | ||
567 | * DRM_IOCTL_SET_VERSION ioctl argument type. | ||
568 | */ | ||
569 | struct drm_set_version { | ||
570 | int drm_di_major; | ||
571 | int drm_di_minor; | ||
572 | int drm_dd_major; | ||
573 | int drm_dd_minor; | ||
574 | }; | ||
575 | |||
576 | #define DRM_IOCTL_BASE 'd' | ||
577 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | ||
578 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | ||
579 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | ||
580 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | ||
581 | |||
582 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) | ||
583 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) | ||
584 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) | ||
585 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) | ||
586 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) | ||
587 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) | ||
588 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) | ||
589 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) | ||
590 | |||
591 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) | ||
592 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) | ||
593 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) | ||
594 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) | ||
595 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) | ||
596 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) | ||
597 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) | ||
598 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) | ||
599 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) | ||
600 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) | ||
601 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) | ||
602 | |||
603 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) | ||
604 | |||
605 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) | ||
606 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) | ||
607 | |||
608 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) | ||
609 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) | ||
610 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) | ||
611 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) | ||
612 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) | ||
613 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) | ||
614 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) | ||
615 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) | ||
616 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) | ||
617 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) | ||
618 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) | ||
619 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) | ||
620 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) | ||
621 | |||
622 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) | ||
623 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | ||
624 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) | ||
625 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) | ||
626 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) | ||
627 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) | ||
628 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) | ||
629 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) | ||
630 | |||
631 | #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) | ||
632 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) | ||
633 | |||
634 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) | ||
635 | |||
636 | #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) | ||
637 | |||
638 | /** | ||
639 | * Device specific ioctls should only be in their respective headers | ||
640 | * The device specific ioctl range is from 0x40 to 0x99. | ||
641 | * Generic IOCTLS restart at 0xA0. | ||
642 | * | ||
643 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | ||
644 | * drmCommandReadWrite(). | ||
645 | */ | ||
646 | #define DRM_COMMAND_BASE 0x40 | ||
647 | #define DRM_COMMAND_END 0xA0 | ||
648 | |||
649 | /* typedef area */ | ||
650 | #ifndef __KERNEL__ | ||
651 | typedef struct drm_clip_rect drm_clip_rect_t; | ||
652 | typedef struct drm_drawable_info drm_drawable_info_t; | ||
653 | typedef struct drm_tex_region drm_tex_region_t; | ||
654 | typedef struct drm_hw_lock drm_hw_lock_t; | ||
655 | typedef struct drm_version drm_version_t; | ||
656 | typedef struct drm_unique drm_unique_t; | ||
657 | typedef struct drm_list drm_list_t; | ||
658 | typedef struct drm_block drm_block_t; | ||
659 | typedef struct drm_control drm_control_t; | ||
660 | typedef enum drm_map_type drm_map_type_t; | ||
661 | typedef enum drm_map_flags drm_map_flags_t; | ||
662 | typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; | ||
663 | typedef struct drm_map drm_map_t; | ||
664 | typedef struct drm_client drm_client_t; | ||
665 | typedef enum drm_stat_type drm_stat_type_t; | ||
666 | typedef struct drm_stats drm_stats_t; | ||
667 | typedef enum drm_lock_flags drm_lock_flags_t; | ||
668 | typedef struct drm_lock drm_lock_t; | ||
669 | typedef enum drm_dma_flags drm_dma_flags_t; | ||
670 | typedef struct drm_buf_desc drm_buf_desc_t; | ||
671 | typedef struct drm_buf_info drm_buf_info_t; | ||
672 | typedef struct drm_buf_free drm_buf_free_t; | ||
673 | typedef struct drm_buf_pub drm_buf_pub_t; | ||
674 | typedef struct drm_buf_map drm_buf_map_t; | ||
675 | typedef struct drm_dma drm_dma_t; | ||
676 | typedef union drm_wait_vblank drm_wait_vblank_t; | ||
677 | typedef struct drm_agp_mode drm_agp_mode_t; | ||
678 | typedef enum drm_ctx_flags drm_ctx_flags_t; | ||
679 | typedef struct drm_ctx drm_ctx_t; | ||
680 | typedef struct drm_ctx_res drm_ctx_res_t; | ||
681 | typedef struct drm_draw drm_draw_t; | ||
682 | typedef struct drm_update_draw drm_update_draw_t; | ||
683 | typedef struct drm_auth drm_auth_t; | ||
684 | typedef struct drm_irq_busid drm_irq_busid_t; | ||
685 | typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; | ||
686 | |||
687 | typedef struct drm_agp_buffer drm_agp_buffer_t; | ||
688 | typedef struct drm_agp_binding drm_agp_binding_t; | ||
689 | typedef struct drm_agp_info drm_agp_info_t; | ||
690 | typedef struct drm_scatter_gather drm_scatter_gather_t; | ||
691 | typedef struct drm_set_version drm_set_version_t; | ||
692 | #endif | ||
693 | |||
694 | #endif | ||
diff --git a/include/drm/drmP.h b/include/drm/drmP.h new file mode 100644 index 000000000000..0764b662b339 --- /dev/null +++ b/include/drm/drmP.h | |||
@@ -0,0 +1,1153 @@ | |||
1 | /** | ||
2 | * \file drmP.h | ||
3 | * Private header for Direct Rendering Manager | ||
4 | * | ||
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> | ||
6 | * \author Gareth Hughes <gareth@valinux.com> | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | ||
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
12 | * All rights reserved. | ||
13 | * | ||
14 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
15 | * copy of this software and associated documentation files (the "Software"), | ||
16 | * to deal in the Software without restriction, including without limitation | ||
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
18 | * and/or sell copies of the Software, and to permit persons to whom the | ||
19 | * Software is furnished to do so, subject to the following conditions: | ||
20 | * | ||
21 | * The above copyright notice and this permission notice (including the next | ||
22 | * paragraph) shall be included in all copies or substantial portions of the | ||
23 | * Software. | ||
24 | * | ||
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
28 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
31 | * OTHER DEALINGS IN THE SOFTWARE. | ||
32 | */ | ||
33 | |||
34 | #ifndef _DRM_P_H_ | ||
35 | #define _DRM_P_H_ | ||
36 | |||
37 | /* If you want the memory alloc debug functionality, change define below */ | ||
38 | /* #define DEBUG_MEMORY */ | ||
39 | |||
40 | #ifdef __KERNEL__ | ||
41 | #ifdef __alpha__ | ||
42 | /* add include of current.h so that "current" is defined | ||
43 | * before static inline funcs in wait.h. Doing this so we | ||
44 | * can build the DRM (part of PI DRI). 4/21/2000 S + B */ | ||
45 | #include <asm/current.h> | ||
46 | #endif /* __alpha__ */ | ||
47 | #include <linux/module.h> | ||
48 | #include <linux/kernel.h> | ||
49 | #include <linux/miscdevice.h> | ||
50 | #include <linux/fs.h> | ||
51 | #include <linux/proc_fs.h> | ||
52 | #include <linux/init.h> | ||
53 | #include <linux/file.h> | ||
54 | #include <linux/pci.h> | ||
55 | #include <linux/jiffies.h> | ||
56 | #include <linux/smp_lock.h> /* For (un)lock_kernel */ | ||
57 | #include <linux/dma-mapping.h> | ||
58 | #include <linux/mm.h> | ||
59 | #include <linux/cdev.h> | ||
60 | #include <linux/mutex.h> | ||
61 | #if defined(__alpha__) || defined(__powerpc__) | ||
62 | #include <asm/pgtable.h> /* For pte_wrprotect */ | ||
63 | #endif | ||
64 | #include <asm/io.h> | ||
65 | #include <asm/mman.h> | ||
66 | #include <asm/uaccess.h> | ||
67 | #ifdef CONFIG_MTRR | ||
68 | #include <asm/mtrr.h> | ||
69 | #endif | ||
70 | #if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE) | ||
71 | #include <linux/types.h> | ||
72 | #include <linux/agp_backend.h> | ||
73 | #endif | ||
74 | #include <linux/workqueue.h> | ||
75 | #include <linux/poll.h> | ||
76 | #include <asm/pgalloc.h> | ||
77 | #include "drm.h" | ||
78 | |||
79 | #include <linux/idr.h> | ||
80 | |||
81 | #define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) | ||
82 | #define __OS_HAS_MTRR (defined(CONFIG_MTRR)) | ||
83 | |||
84 | struct drm_file; | ||
85 | struct drm_device; | ||
86 | |||
87 | #include "drm_os_linux.h" | ||
88 | #include "drm_hashtab.h" | ||
89 | |||
90 | /***********************************************************************/ | ||
91 | /** \name DRM template customization defaults */ | ||
92 | /*@{*/ | ||
93 | |||
94 | /* driver capabilities and requirements mask */ | ||
95 | #define DRIVER_USE_AGP 0x1 | ||
96 | #define DRIVER_REQUIRE_AGP 0x2 | ||
97 | #define DRIVER_USE_MTRR 0x4 | ||
98 | #define DRIVER_PCI_DMA 0x8 | ||
99 | #define DRIVER_SG 0x10 | ||
100 | #define DRIVER_HAVE_DMA 0x20 | ||
101 | #define DRIVER_HAVE_IRQ 0x40 | ||
102 | #define DRIVER_IRQ_SHARED 0x80 | ||
103 | #define DRIVER_IRQ_VBL 0x100 | ||
104 | #define DRIVER_DMA_QUEUE 0x200 | ||
105 | #define DRIVER_FB_DMA 0x400 | ||
106 | #define DRIVER_IRQ_VBL2 0x800 | ||
107 | |||
108 | /***********************************************************************/ | ||
109 | /** \name Begin the DRM... */ | ||
110 | /*@{*/ | ||
111 | |||
112 | #define DRM_DEBUG_CODE 2 /**< Include debugging code if > 1, then | ||
113 | also include looping detection. */ | ||
114 | |||
115 | #define DRM_MAGIC_HASH_ORDER 4 /**< Size of key hash table. Must be power of 2. */ | ||
116 | #define DRM_KERNEL_CONTEXT 0 /**< Change drm_resctx if changed */ | ||
117 | #define DRM_RESERVED_CONTEXTS 1 /**< Change drm_resctx if changed */ | ||
118 | #define DRM_LOOPING_LIMIT 5000000 | ||
119 | #define DRM_TIME_SLICE (HZ/20) /**< Time slice for GLXContexts */ | ||
120 | #define DRM_LOCK_SLICE 1 /**< Time slice for lock, in jiffies */ | ||
121 | |||
122 | #define DRM_FLAG_DEBUG 0x01 | ||
123 | |||
124 | #define DRM_MEM_DMA 0 | ||
125 | #define DRM_MEM_SAREA 1 | ||
126 | #define DRM_MEM_DRIVER 2 | ||
127 | #define DRM_MEM_MAGIC 3 | ||
128 | #define DRM_MEM_IOCTLS 4 | ||
129 | #define DRM_MEM_MAPS 5 | ||
130 | #define DRM_MEM_VMAS 6 | ||
131 | #define DRM_MEM_BUFS 7 | ||
132 | #define DRM_MEM_SEGS 8 | ||
133 | #define DRM_MEM_PAGES 9 | ||
134 | #define DRM_MEM_FILES 10 | ||
135 | #define DRM_MEM_QUEUES 11 | ||
136 | #define DRM_MEM_CMDS 12 | ||
137 | #define DRM_MEM_MAPPINGS 13 | ||
138 | #define DRM_MEM_BUFLISTS 14 | ||
139 | #define DRM_MEM_AGPLISTS 15 | ||
140 | #define DRM_MEM_TOTALAGP 16 | ||
141 | #define DRM_MEM_BOUNDAGP 17 | ||
142 | #define DRM_MEM_CTXBITMAP 18 | ||
143 | #define DRM_MEM_STUB 19 | ||
144 | #define DRM_MEM_SGLISTS 20 | ||
145 | #define DRM_MEM_CTXLIST 21 | ||
146 | #define DRM_MEM_MM 22 | ||
147 | #define DRM_MEM_HASHTAB 23 | ||
148 | |||
149 | #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) | ||
150 | #define DRM_MAP_HASH_OFFSET 0x10000000 | ||
151 | |||
152 | /*@}*/ | ||
153 | |||
154 | /***********************************************************************/ | ||
155 | /** \name Macros to make printk easier */ | ||
156 | /*@{*/ | ||
157 | |||
158 | /** | ||
159 | * Error output. | ||
160 | * | ||
161 | * \param fmt printf() like format string. | ||
162 | * \param arg arguments | ||
163 | */ | ||
164 | #define DRM_ERROR(fmt, arg...) \ | ||
165 | printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) | ||
166 | |||
167 | /** | ||
168 | * Memory error output. | ||
169 | * | ||
170 | * \param area memory area where the error occurred. | ||
171 | * \param fmt printf() like format string. | ||
172 | * \param arg arguments | ||
173 | */ | ||
174 | #define DRM_MEM_ERROR(area, fmt, arg...) \ | ||
175 | printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __func__, \ | ||
176 | drm_mem_stats[area].name , ##arg) | ||
177 | |||
178 | #define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg) | ||
179 | |||
180 | /** | ||
181 | * Debug output. | ||
182 | * | ||
183 | * \param fmt printf() like format string. | ||
184 | * \param arg arguments | ||
185 | */ | ||
186 | #if DRM_DEBUG_CODE | ||
187 | #define DRM_DEBUG(fmt, arg...) \ | ||
188 | do { \ | ||
189 | if ( drm_debug ) \ | ||
190 | printk(KERN_DEBUG \ | ||
191 | "[" DRM_NAME ":%s] " fmt , \ | ||
192 | __func__ , ##arg); \ | ||
193 | } while (0) | ||
194 | #else | ||
195 | #define DRM_DEBUG(fmt, arg...) do { } while (0) | ||
196 | #endif | ||
197 | |||
198 | #define DRM_PROC_LIMIT (PAGE_SIZE-80) | ||
199 | |||
200 | #define DRM_PROC_PRINT(fmt, arg...) \ | ||
201 | len += sprintf(&buf[len], fmt , ##arg); \ | ||
202 | if (len > DRM_PROC_LIMIT) { *eof = 1; return len - offset; } | ||
203 | |||
204 | #define DRM_PROC_PRINT_RET(ret, fmt, arg...) \ | ||
205 | len += sprintf(&buf[len], fmt , ##arg); \ | ||
206 | if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; } | ||
207 | |||
208 | /*@}*/ | ||
209 | |||
210 | /***********************************************************************/ | ||
211 | /** \name Internal types and structures */ | ||
212 | /*@{*/ | ||
213 | |||
214 | #define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x) | ||
215 | |||
216 | #define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1)) | ||
217 | #define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x)) | ||
218 | #define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist) | ||
219 | |||
220 | #define DRM_IF_VERSION(maj, min) (maj << 16 | min) | ||
221 | /** | ||
222 | * Get the private SAREA mapping. | ||
223 | * | ||
224 | * \param _dev DRM device. | ||
225 | * \param _ctx context number. | ||
226 | * \param _map output mapping. | ||
227 | */ | ||
228 | #define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do { \ | ||
229 | (_map) = (_dev)->context_sareas[_ctx]; \ | ||
230 | } while(0) | ||
231 | |||
232 | /** | ||
233 | * Test that the hardware lock is held by the caller, returning otherwise. | ||
234 | * | ||
235 | * \param dev DRM device. | ||
236 | * \param filp file pointer of the caller. | ||
237 | */ | ||
238 | #define LOCK_TEST_WITH_RETURN( dev, file_priv ) \ | ||
239 | do { \ | ||
240 | if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ | ||
241 | dev->lock.file_priv != file_priv ) { \ | ||
242 | DRM_ERROR( "%s called without lock held, held %d owner %p %p\n",\ | ||
243 | __func__, _DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ),\ | ||
244 | dev->lock.file_priv, file_priv ); \ | ||
245 | return -EINVAL; \ | ||
246 | } \ | ||
247 | } while (0) | ||
248 | |||
249 | /** | ||
250 | * Copy and IOCTL return string to user space | ||
251 | */ | ||
252 | #define DRM_COPY( name, value ) \ | ||
253 | len = strlen( value ); \ | ||
254 | if ( len > name##_len ) len = name##_len; \ | ||
255 | name##_len = strlen( value ); \ | ||
256 | if ( len && name ) { \ | ||
257 | if ( copy_to_user( name, value, len ) ) \ | ||
258 | return -EFAULT; \ | ||
259 | } | ||
260 | |||
261 | /** | ||
262 | * Ioctl function type. | ||
263 | * | ||
264 | * \param inode device inode. | ||
265 | * \param file_priv DRM file private pointer. | ||
266 | * \param cmd command. | ||
267 | * \param arg argument. | ||
268 | */ | ||
269 | typedef int drm_ioctl_t(struct drm_device *dev, void *data, | ||
270 | struct drm_file *file_priv); | ||
271 | |||
272 | typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd, | ||
273 | unsigned long arg); | ||
274 | |||
275 | #define DRM_AUTH 0x1 | ||
276 | #define DRM_MASTER 0x2 | ||
277 | #define DRM_ROOT_ONLY 0x4 | ||
278 | |||
279 | struct drm_ioctl_desc { | ||
280 | unsigned int cmd; | ||
281 | drm_ioctl_t *func; | ||
282 | int flags; | ||
283 | }; | ||
284 | |||
285 | /** | ||
286 | * Creates a driver or general drm_ioctl_desc array entry for the given | ||
287 | * ioctl, for use by drm_ioctl(). | ||
288 | */ | ||
289 | #define DRM_IOCTL_DEF(ioctl, func, flags) \ | ||
290 | [DRM_IOCTL_NR(ioctl)] = {ioctl, func, flags} | ||
291 | |||
292 | struct drm_magic_entry { | ||
293 | struct list_head head; | ||
294 | struct drm_hash_item hash_item; | ||
295 | struct drm_file *priv; | ||
296 | }; | ||
297 | |||
298 | struct drm_vma_entry { | ||
299 | struct list_head head; | ||
300 | struct vm_area_struct *vma; | ||
301 | pid_t pid; | ||
302 | }; | ||
303 | |||
304 | /** | ||
305 | * DMA buffer. | ||
306 | */ | ||
307 | struct drm_buf { | ||
308 | int idx; /**< Index into master buflist */ | ||
309 | int total; /**< Buffer size */ | ||
310 | int order; /**< log-base-2(total) */ | ||
311 | int used; /**< Amount of buffer in use (for DMA) */ | ||
312 | unsigned long offset; /**< Byte offset (used internally) */ | ||
313 | void *address; /**< Address of buffer */ | ||
314 | unsigned long bus_address; /**< Bus address of buffer */ | ||
315 | struct drm_buf *next; /**< Kernel-only: used for free list */ | ||
316 | __volatile__ int waiting; /**< On kernel DMA queue */ | ||
317 | __volatile__ int pending; /**< On hardware DMA queue */ | ||
318 | wait_queue_head_t dma_wait; /**< Processes waiting */ | ||
319 | struct drm_file *file_priv; /**< Private of holding file descr */ | ||
320 | int context; /**< Kernel queue for this buffer */ | ||
321 | int while_locked; /**< Dispatch this buffer while locked */ | ||
322 | enum { | ||
323 | DRM_LIST_NONE = 0, | ||
324 | DRM_LIST_FREE = 1, | ||
325 | DRM_LIST_WAIT = 2, | ||
326 | DRM_LIST_PEND = 3, | ||
327 | DRM_LIST_PRIO = 4, | ||
328 | DRM_LIST_RECLAIM = 5 | ||
329 | } list; /**< Which list we're on */ | ||
330 | |||
331 | int dev_priv_size; /**< Size of buffer private storage */ | ||
332 | void *dev_private; /**< Per-buffer private storage */ | ||
333 | }; | ||
334 | |||
335 | /** bufs is one longer than it has to be */ | ||
336 | struct drm_waitlist { | ||
337 | int count; /**< Number of possible buffers */ | ||
338 | struct drm_buf **bufs; /**< List of pointers to buffers */ | ||
339 | struct drm_buf **rp; /**< Read pointer */ | ||
340 | struct drm_buf **wp; /**< Write pointer */ | ||
341 | struct drm_buf **end; /**< End pointer */ | ||
342 | spinlock_t read_lock; | ||
343 | spinlock_t write_lock; | ||
344 | }; | ||
345 | |||
346 | struct drm_freelist { | ||
347 | int initialized; /**< Freelist in use */ | ||
348 | atomic_t count; /**< Number of free buffers */ | ||
349 | struct drm_buf *next; /**< End pointer */ | ||
350 | |||
351 | wait_queue_head_t waiting; /**< Processes waiting on free bufs */ | ||
352 | int low_mark; /**< Low water mark */ | ||
353 | int high_mark; /**< High water mark */ | ||
354 | atomic_t wfh; /**< If waiting for high mark */ | ||
355 | spinlock_t lock; | ||
356 | }; | ||
357 | |||
358 | typedef struct drm_dma_handle { | ||
359 | dma_addr_t busaddr; | ||
360 | void *vaddr; | ||
361 | size_t size; | ||
362 | } drm_dma_handle_t; | ||
363 | |||
364 | /** | ||
365 | * Buffer entry. There is one of this for each buffer size order. | ||
366 | */ | ||
367 | struct drm_buf_entry { | ||
368 | int buf_size; /**< size */ | ||
369 | int buf_count; /**< number of buffers */ | ||
370 | struct drm_buf *buflist; /**< buffer list */ | ||
371 | int seg_count; | ||
372 | int page_order; | ||
373 | struct drm_dma_handle **seglist; | ||
374 | |||
375 | struct drm_freelist freelist; | ||
376 | }; | ||
377 | |||
378 | /** File private data */ | ||
379 | struct drm_file { | ||
380 | int authenticated; | ||
381 | int master; | ||
382 | pid_t pid; | ||
383 | uid_t uid; | ||
384 | drm_magic_t magic; | ||
385 | unsigned long ioctl_count; | ||
386 | struct list_head lhead; | ||
387 | struct drm_minor *minor; | ||
388 | int remove_auth_on_close; | ||
389 | unsigned long lock_count; | ||
390 | struct file *filp; | ||
391 | void *driver_priv; | ||
392 | }; | ||
393 | |||
394 | /** Wait queue */ | ||
395 | struct drm_queue { | ||
396 | atomic_t use_count; /**< Outstanding uses (+1) */ | ||
397 | atomic_t finalization; /**< Finalization in progress */ | ||
398 | atomic_t block_count; /**< Count of processes waiting */ | ||
399 | atomic_t block_read; /**< Queue blocked for reads */ | ||
400 | wait_queue_head_t read_queue; /**< Processes waiting on block_read */ | ||
401 | atomic_t block_write; /**< Queue blocked for writes */ | ||
402 | wait_queue_head_t write_queue; /**< Processes waiting on block_write */ | ||
403 | atomic_t total_queued; /**< Total queued statistic */ | ||
404 | atomic_t total_flushed; /**< Total flushes statistic */ | ||
405 | atomic_t total_locks; /**< Total locks statistics */ | ||
406 | enum drm_ctx_flags flags; /**< Context preserving and 2D-only */ | ||
407 | struct drm_waitlist waitlist; /**< Pending buffers */ | ||
408 | wait_queue_head_t flush_queue; /**< Processes waiting until flush */ | ||
409 | }; | ||
410 | |||
411 | /** | ||
412 | * Lock data. | ||
413 | */ | ||
414 | struct drm_lock_data { | ||
415 | struct drm_hw_lock *hw_lock; /**< Hardware lock */ | ||
416 | /** Private of lock holder's file (NULL=kernel) */ | ||
417 | struct drm_file *file_priv; | ||
418 | wait_queue_head_t lock_queue; /**< Queue of blocked processes */ | ||
419 | unsigned long lock_time; /**< Time of last lock in jiffies */ | ||
420 | spinlock_t spinlock; | ||
421 | uint32_t kernel_waiters; | ||
422 | uint32_t user_waiters; | ||
423 | int idle_has_lock; | ||
424 | }; | ||
425 | |||
426 | /** | ||
427 | * DMA data. | ||
428 | */ | ||
429 | struct drm_device_dma { | ||
430 | |||
431 | struct drm_buf_entry bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */ | ||
432 | int buf_count; /**< total number of buffers */ | ||
433 | struct drm_buf **buflist; /**< Vector of pointers into drm_device_dma::bufs */ | ||
434 | int seg_count; | ||
435 | int page_count; /**< number of pages */ | ||
436 | unsigned long *pagelist; /**< page list */ | ||
437 | unsigned long byte_count; | ||
438 | enum { | ||
439 | _DRM_DMA_USE_AGP = 0x01, | ||
440 | _DRM_DMA_USE_SG = 0x02, | ||
441 | _DRM_DMA_USE_FB = 0x04, | ||
442 | _DRM_DMA_USE_PCI_RO = 0x08 | ||
443 | } flags; | ||
444 | |||
445 | }; | ||
446 | |||
447 | /** | ||
448 | * AGP memory entry. Stored as a doubly linked list. | ||
449 | */ | ||
450 | struct drm_agp_mem { | ||
451 | unsigned long handle; /**< handle */ | ||
452 | DRM_AGP_MEM *memory; | ||
453 | unsigned long bound; /**< address */ | ||
454 | int pages; | ||
455 | struct list_head head; | ||
456 | }; | ||
457 | |||
458 | /** | ||
459 | * AGP data. | ||
460 | * | ||
461 | * \sa drm_agp_init() and drm_device::agp. | ||
462 | */ | ||
463 | struct drm_agp_head { | ||
464 | DRM_AGP_KERN agp_info; /**< AGP device information */ | ||
465 | struct list_head memory; | ||
466 | unsigned long mode; /**< AGP mode */ | ||
467 | struct agp_bridge_data *bridge; | ||
468 | int enabled; /**< whether the AGP bus as been enabled */ | ||
469 | int acquired; /**< whether the AGP device has been acquired */ | ||
470 | unsigned long base; | ||
471 | int agp_mtrr; | ||
472 | int cant_use_aperture; | ||
473 | unsigned long page_mask; | ||
474 | }; | ||
475 | |||
476 | /** | ||
477 | * Scatter-gather memory. | ||
478 | */ | ||
479 | struct drm_sg_mem { | ||
480 | unsigned long handle; | ||
481 | void *virtual; | ||
482 | int pages; | ||
483 | struct page **pagelist; | ||
484 | dma_addr_t *busaddr; | ||
485 | }; | ||
486 | |||
487 | struct drm_sigdata { | ||
488 | int context; | ||
489 | struct drm_hw_lock *lock; | ||
490 | }; | ||
491 | |||
492 | |||
493 | /* | ||
494 | * Generic memory manager structs | ||
495 | */ | ||
496 | |||
497 | struct drm_mm_node { | ||
498 | struct list_head fl_entry; | ||
499 | struct list_head ml_entry; | ||
500 | int free; | ||
501 | unsigned long start; | ||
502 | unsigned long size; | ||
503 | struct drm_mm *mm; | ||
504 | void *private; | ||
505 | }; | ||
506 | |||
507 | struct drm_mm { | ||
508 | struct list_head fl_entry; | ||
509 | struct list_head ml_entry; | ||
510 | }; | ||
511 | |||
512 | |||
513 | /** | ||
514 | * Mappings list | ||
515 | */ | ||
516 | struct drm_map_list { | ||
517 | struct list_head head; /**< list head */ | ||
518 | struct drm_hash_item hash; | ||
519 | struct drm_map *map; /**< mapping */ | ||
520 | uint64_t user_token; | ||
521 | }; | ||
522 | |||
523 | typedef struct drm_map drm_local_map_t; | ||
524 | |||
525 | /** | ||
526 | * Context handle list | ||
527 | */ | ||
528 | struct drm_ctx_list { | ||
529 | struct list_head head; /**< list head */ | ||
530 | drm_context_t handle; /**< context handle */ | ||
531 | struct drm_file *tag; /**< associated fd private data */ | ||
532 | }; | ||
533 | |||
534 | struct drm_vbl_sig { | ||
535 | struct list_head head; | ||
536 | unsigned int sequence; | ||
537 | struct siginfo info; | ||
538 | struct task_struct *task; | ||
539 | }; | ||
540 | |||
541 | /* location of GART table */ | ||
542 | #define DRM_ATI_GART_MAIN 1 | ||
543 | #define DRM_ATI_GART_FB 2 | ||
544 | |||
545 | #define DRM_ATI_GART_PCI 1 | ||
546 | #define DRM_ATI_GART_PCIE 2 | ||
547 | #define DRM_ATI_GART_IGP 3 | ||
548 | |||
549 | struct drm_ati_pcigart_info { | ||
550 | int gart_table_location; | ||
551 | int gart_reg_if; | ||
552 | void *addr; | ||
553 | dma_addr_t bus_addr; | ||
554 | dma_addr_t table_mask; | ||
555 | struct drm_dma_handle *table_handle; | ||
556 | drm_local_map_t mapping; | ||
557 | int table_size; | ||
558 | }; | ||
559 | |||
560 | /** | ||
561 | * DRM driver structure. This structure represent the common code for | ||
562 | * a family of cards. There will one drm_device for each card present | ||
563 | * in this family | ||
564 | */ | ||
565 | struct drm_driver { | ||
566 | int (*load) (struct drm_device *, unsigned long flags); | ||
567 | int (*firstopen) (struct drm_device *); | ||
568 | int (*open) (struct drm_device *, struct drm_file *); | ||
569 | void (*preclose) (struct drm_device *, struct drm_file *file_priv); | ||
570 | void (*postclose) (struct drm_device *, struct drm_file *); | ||
571 | void (*lastclose) (struct drm_device *); | ||
572 | int (*unload) (struct drm_device *); | ||
573 | int (*suspend) (struct drm_device *, pm_message_t state); | ||
574 | int (*resume) (struct drm_device *); | ||
575 | int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv); | ||
576 | void (*dma_ready) (struct drm_device *); | ||
577 | int (*dma_quiescent) (struct drm_device *); | ||
578 | int (*context_ctor) (struct drm_device *dev, int context); | ||
579 | int (*context_dtor) (struct drm_device *dev, int context); | ||
580 | int (*kernel_context_switch) (struct drm_device *dev, int old, | ||
581 | int new); | ||
582 | void (*kernel_context_switch_unlock) (struct drm_device *dev); | ||
583 | int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence); | ||
584 | int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence); | ||
585 | int (*dri_library_name) (struct drm_device *dev, char *buf); | ||
586 | |||
587 | /** | ||
588 | * Called by \c drm_device_is_agp. Typically used to determine if a | ||
589 | * card is really attached to AGP or not. | ||
590 | * | ||
591 | * \param dev DRM device handle | ||
592 | * | ||
593 | * \returns | ||
594 | * One of three values is returned depending on whether or not the | ||
595 | * card is absolutely \b not AGP (return of 0), absolutely \b is AGP | ||
596 | * (return of 1), or may or may not be AGP (return of 2). | ||
597 | */ | ||
598 | int (*device_is_agp) (struct drm_device *dev); | ||
599 | |||
600 | /* these have to be filled in */ | ||
601 | |||
602 | irqreturn_t(*irq_handler) (DRM_IRQ_ARGS); | ||
603 | void (*irq_preinstall) (struct drm_device *dev); | ||
604 | void (*irq_postinstall) (struct drm_device *dev); | ||
605 | void (*irq_uninstall) (struct drm_device *dev); | ||
606 | void (*reclaim_buffers) (struct drm_device *dev, | ||
607 | struct drm_file * file_priv); | ||
608 | void (*reclaim_buffers_locked) (struct drm_device *dev, | ||
609 | struct drm_file *file_priv); | ||
610 | void (*reclaim_buffers_idlelocked) (struct drm_device *dev, | ||
611 | struct drm_file *file_priv); | ||
612 | unsigned long (*get_map_ofs) (struct drm_map * map); | ||
613 | unsigned long (*get_reg_ofs) (struct drm_device *dev); | ||
614 | void (*set_version) (struct drm_device *dev, | ||
615 | struct drm_set_version *sv); | ||
616 | |||
617 | int major; | ||
618 | int minor; | ||
619 | int patchlevel; | ||
620 | char *name; | ||
621 | char *desc; | ||
622 | char *date; | ||
623 | |||
624 | u32 driver_features; | ||
625 | int dev_priv_size; | ||
626 | struct drm_ioctl_desc *ioctls; | ||
627 | int num_ioctls; | ||
628 | struct file_operations fops; | ||
629 | struct pci_driver pci_driver; | ||
630 | }; | ||
631 | |||
632 | #define DRM_MINOR_UNASSIGNED 0 | ||
633 | #define DRM_MINOR_LEGACY 1 | ||
634 | |||
635 | /** | ||
636 | * DRM minor structure. This structure represents a drm minor number. | ||
637 | */ | ||
638 | struct drm_minor { | ||
639 | int index; /**< Minor device number */ | ||
640 | int type; /**< Control or render */ | ||
641 | dev_t device; /**< Device number for mknod */ | ||
642 | struct device kdev; /**< Linux device */ | ||
643 | struct drm_device *dev; | ||
644 | struct proc_dir_entry *dev_root; /**< proc directory entry */ | ||
645 | }; | ||
646 | |||
647 | /** | ||
648 | * DRM device structure. This structure represent a complete card that | ||
649 | * may contain multiple heads. | ||
650 | */ | ||
651 | struct drm_device { | ||
652 | char *unique; /**< Unique identifier: e.g., busid */ | ||
653 | int unique_len; /**< Length of unique field */ | ||
654 | char *devname; /**< For /proc/interrupts */ | ||
655 | int if_version; /**< Highest interface version set */ | ||
656 | |||
657 | int blocked; /**< Blocked due to VC switch? */ | ||
658 | |||
659 | /** \name Locks */ | ||
660 | /*@{ */ | ||
661 | spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ | ||
662 | struct mutex struct_mutex; /**< For others */ | ||
663 | /*@} */ | ||
664 | |||
665 | /** \name Usage Counters */ | ||
666 | /*@{ */ | ||
667 | int open_count; /**< Outstanding files open */ | ||
668 | atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ | ||
669 | atomic_t vma_count; /**< Outstanding vma areas open */ | ||
670 | int buf_use; /**< Buffers in use -- cannot alloc */ | ||
671 | atomic_t buf_alloc; /**< Buffer allocation in progress */ | ||
672 | /*@} */ | ||
673 | |||
674 | /** \name Performance counters */ | ||
675 | /*@{ */ | ||
676 | unsigned long counters; | ||
677 | enum drm_stat_type types[15]; | ||
678 | atomic_t counts[15]; | ||
679 | /*@} */ | ||
680 | |||
681 | /** \name Authentication */ | ||
682 | /*@{ */ | ||
683 | struct list_head filelist; | ||
684 | struct drm_open_hash magiclist; /**< magic hash table */ | ||
685 | struct list_head magicfree; | ||
686 | /*@} */ | ||
687 | |||
688 | /** \name Memory management */ | ||
689 | /*@{ */ | ||
690 | struct list_head maplist; /**< Linked list of regions */ | ||
691 | int map_count; /**< Number of mappable regions */ | ||
692 | struct drm_open_hash map_hash; /**< User token hash table for maps */ | ||
693 | |||
694 | /** \name Context handle management */ | ||
695 | /*@{ */ | ||
696 | struct list_head ctxlist; /**< Linked list of context handles */ | ||
697 | int ctx_count; /**< Number of context handles */ | ||
698 | struct mutex ctxlist_mutex; /**< For ctxlist */ | ||
699 | |||
700 | struct idr ctx_idr; | ||
701 | |||
702 | struct list_head vmalist; /**< List of vmas (for debugging) */ | ||
703 | struct drm_lock_data lock; /**< Information on hardware lock */ | ||
704 | /*@} */ | ||
705 | |||
706 | /** \name DMA queues (contexts) */ | ||
707 | /*@{ */ | ||
708 | int queue_count; /**< Number of active DMA queues */ | ||
709 | int queue_reserved; /**< Number of reserved DMA queues */ | ||
710 | int queue_slots; /**< Actual length of queuelist */ | ||
711 | struct drm_queue **queuelist; /**< Vector of pointers to DMA queues */ | ||
712 | struct drm_device_dma *dma; /**< Optional pointer for DMA support */ | ||
713 | /*@} */ | ||
714 | |||
715 | /** \name Context support */ | ||
716 | /*@{ */ | ||
717 | int irq; /**< Interrupt used by board */ | ||
718 | int irq_enabled; /**< True if irq handler is enabled */ | ||
719 | __volatile__ long context_flag; /**< Context swapping flag */ | ||
720 | __volatile__ long interrupt_flag; /**< Interruption handler flag */ | ||
721 | __volatile__ long dma_flag; /**< DMA dispatch flag */ | ||
722 | struct timer_list timer; /**< Timer for delaying ctx switch */ | ||
723 | wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ | ||
724 | int last_checked; /**< Last context checked for DMA */ | ||
725 | int last_context; /**< Last current context */ | ||
726 | unsigned long last_switch; /**< jiffies at last context switch */ | ||
727 | /*@} */ | ||
728 | |||
729 | struct work_struct work; | ||
730 | /** \name VBLANK IRQ support */ | ||
731 | /*@{ */ | ||
732 | |||
733 | wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ | ||
734 | atomic_t vbl_received; | ||
735 | atomic_t vbl_received2; /**< number of secondary VBLANK interrupts */ | ||
736 | spinlock_t vbl_lock; | ||
737 | struct list_head vbl_sigs; /**< signal list to send on VBLANK */ | ||
738 | struct list_head vbl_sigs2; /**< signals to send on secondary VBLANK */ | ||
739 | unsigned int vbl_pending; | ||
740 | spinlock_t tasklet_lock; /**< For drm_locked_tasklet */ | ||
741 | void (*locked_tasklet_func)(struct drm_device *dev); | ||
742 | |||
743 | /*@} */ | ||
744 | cycles_t ctx_start; | ||
745 | cycles_t lck_start; | ||
746 | |||
747 | struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ | ||
748 | wait_queue_head_t buf_readers; /**< Processes waiting to read */ | ||
749 | wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ | ||
750 | |||
751 | struct drm_agp_head *agp; /**< AGP data */ | ||
752 | |||
753 | struct pci_dev *pdev; /**< PCI device structure */ | ||
754 | int pci_vendor; /**< PCI vendor id */ | ||
755 | int pci_device; /**< PCI device id */ | ||
756 | #ifdef __alpha__ | ||
757 | struct pci_controller *hose; | ||
758 | #endif | ||
759 | struct drm_sg_mem *sg; /**< Scatter gather memory */ | ||
760 | void *dev_private; /**< device private data */ | ||
761 | struct drm_sigdata sigdata; /**< For block_all_signals */ | ||
762 | sigset_t sigmask; | ||
763 | |||
764 | struct drm_driver *driver; | ||
765 | drm_local_map_t *agp_buffer_map; | ||
766 | unsigned int agp_buffer_token; | ||
767 | struct drm_minor *primary; /**< render type primary screen head */ | ||
768 | |||
769 | /** \name Drawable information */ | ||
770 | /*@{ */ | ||
771 | spinlock_t drw_lock; | ||
772 | struct idr drw_idr; | ||
773 | /*@} */ | ||
774 | }; | ||
775 | |||
776 | static __inline__ int drm_core_check_feature(struct drm_device *dev, | ||
777 | int feature) | ||
778 | { | ||
779 | return ((dev->driver->driver_features & feature) ? 1 : 0); | ||
780 | } | ||
781 | |||
782 | #ifdef __alpha__ | ||
783 | #define drm_get_pci_domain(dev) dev->hose->index | ||
784 | #else | ||
785 | #define drm_get_pci_domain(dev) 0 | ||
786 | #endif | ||
787 | |||
788 | #if __OS_HAS_AGP | ||
789 | static inline int drm_core_has_AGP(struct drm_device *dev) | ||
790 | { | ||
791 | return drm_core_check_feature(dev, DRIVER_USE_AGP); | ||
792 | } | ||
793 | #else | ||
794 | #define drm_core_has_AGP(dev) (0) | ||
795 | #endif | ||
796 | |||
797 | #if __OS_HAS_MTRR | ||
798 | static inline int drm_core_has_MTRR(struct drm_device *dev) | ||
799 | { | ||
800 | return drm_core_check_feature(dev, DRIVER_USE_MTRR); | ||
801 | } | ||
802 | |||
803 | #define DRM_MTRR_WC MTRR_TYPE_WRCOMB | ||
804 | |||
805 | static inline int drm_mtrr_add(unsigned long offset, unsigned long size, | ||
806 | unsigned int flags) | ||
807 | { | ||
808 | return mtrr_add(offset, size, flags, 1); | ||
809 | } | ||
810 | |||
811 | static inline int drm_mtrr_del(int handle, unsigned long offset, | ||
812 | unsigned long size, unsigned int flags) | ||
813 | { | ||
814 | return mtrr_del(handle, offset, size); | ||
815 | } | ||
816 | |||
817 | #else | ||
818 | #define drm_core_has_MTRR(dev) (0) | ||
819 | |||
820 | #define DRM_MTRR_WC 0 | ||
821 | |||
822 | static inline int drm_mtrr_add(unsigned long offset, unsigned long size, | ||
823 | unsigned int flags) | ||
824 | { | ||
825 | return 0; | ||
826 | } | ||
827 | |||
828 | static inline int drm_mtrr_del(int handle, unsigned long offset, | ||
829 | unsigned long size, unsigned int flags) | ||
830 | { | ||
831 | return 0; | ||
832 | } | ||
833 | #endif | ||
834 | |||
835 | /******************************************************************/ | ||
836 | /** \name Internal function definitions */ | ||
837 | /*@{*/ | ||
838 | |||
839 | /* Driver support (drm_drv.h) */ | ||
840 | extern int drm_init(struct drm_driver *driver); | ||
841 | extern void drm_exit(struct drm_driver *driver); | ||
842 | extern int drm_ioctl(struct inode *inode, struct file *filp, | ||
843 | unsigned int cmd, unsigned long arg); | ||
844 | extern long drm_compat_ioctl(struct file *filp, | ||
845 | unsigned int cmd, unsigned long arg); | ||
846 | extern int drm_lastclose(struct drm_device *dev); | ||
847 | |||
848 | /* Device support (drm_fops.h) */ | ||
849 | extern int drm_open(struct inode *inode, struct file *filp); | ||
850 | extern int drm_stub_open(struct inode *inode, struct file *filp); | ||
851 | extern int drm_fasync(int fd, struct file *filp, int on); | ||
852 | extern int drm_release(struct inode *inode, struct file *filp); | ||
853 | |||
854 | /* Mapping support (drm_vm.h) */ | ||
855 | extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); | ||
856 | extern unsigned long drm_core_get_map_ofs(struct drm_map * map); | ||
857 | extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); | ||
858 | extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); | ||
859 | |||
860 | /* Memory management support (drm_memory.h) */ | ||
861 | #include "drm_memory.h" | ||
862 | extern void drm_mem_init(void); | ||
863 | extern int drm_mem_info(char *buf, char **start, off_t offset, | ||
864 | int request, int *eof, void *data); | ||
865 | extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area); | ||
866 | |||
867 | extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type); | ||
868 | extern int drm_free_agp(DRM_AGP_MEM * handle, int pages); | ||
869 | extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); | ||
870 | extern int drm_unbind_agp(DRM_AGP_MEM * handle); | ||
871 | |||
872 | /* Misc. IOCTL support (drm_ioctl.h) */ | ||
873 | extern int drm_irq_by_busid(struct drm_device *dev, void *data, | ||
874 | struct drm_file *file_priv); | ||
875 | extern int drm_getunique(struct drm_device *dev, void *data, | ||
876 | struct drm_file *file_priv); | ||
877 | extern int drm_setunique(struct drm_device *dev, void *data, | ||
878 | struct drm_file *file_priv); | ||
879 | extern int drm_getmap(struct drm_device *dev, void *data, | ||
880 | struct drm_file *file_priv); | ||
881 | extern int drm_getclient(struct drm_device *dev, void *data, | ||
882 | struct drm_file *file_priv); | ||
883 | extern int drm_getstats(struct drm_device *dev, void *data, | ||
884 | struct drm_file *file_priv); | ||
885 | extern int drm_setversion(struct drm_device *dev, void *data, | ||
886 | struct drm_file *file_priv); | ||
887 | extern int drm_noop(struct drm_device *dev, void *data, | ||
888 | struct drm_file *file_priv); | ||
889 | |||
890 | /* Context IOCTL support (drm_context.h) */ | ||
891 | extern int drm_resctx(struct drm_device *dev, void *data, | ||
892 | struct drm_file *file_priv); | ||
893 | extern int drm_addctx(struct drm_device *dev, void *data, | ||
894 | struct drm_file *file_priv); | ||
895 | extern int drm_modctx(struct drm_device *dev, void *data, | ||
896 | struct drm_file *file_priv); | ||
897 | extern int drm_getctx(struct drm_device *dev, void *data, | ||
898 | struct drm_file *file_priv); | ||
899 | extern int drm_switchctx(struct drm_device *dev, void *data, | ||
900 | struct drm_file *file_priv); | ||
901 | extern int drm_newctx(struct drm_device *dev, void *data, | ||
902 | struct drm_file *file_priv); | ||
903 | extern int drm_rmctx(struct drm_device *dev, void *data, | ||
904 | struct drm_file *file_priv); | ||
905 | |||
906 | extern int drm_ctxbitmap_init(struct drm_device *dev); | ||
907 | extern void drm_ctxbitmap_cleanup(struct drm_device *dev); | ||
908 | extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle); | ||
909 | |||
910 | extern int drm_setsareactx(struct drm_device *dev, void *data, | ||
911 | struct drm_file *file_priv); | ||
912 | extern int drm_getsareactx(struct drm_device *dev, void *data, | ||
913 | struct drm_file *file_priv); | ||
914 | |||
915 | /* Drawable IOCTL support (drm_drawable.h) */ | ||
916 | extern int drm_adddraw(struct drm_device *dev, void *data, | ||
917 | struct drm_file *file_priv); | ||
918 | extern int drm_rmdraw(struct drm_device *dev, void *data, | ||
919 | struct drm_file *file_priv); | ||
920 | extern int drm_update_drawable_info(struct drm_device *dev, void *data, | ||
921 | struct drm_file *file_priv); | ||
922 | extern struct drm_drawable_info *drm_get_drawable_info(struct drm_device *dev, | ||
923 | drm_drawable_t id); | ||
924 | extern void drm_drawable_free_all(struct drm_device *dev); | ||
925 | |||
926 | /* Authentication IOCTL support (drm_auth.h) */ | ||
927 | extern int drm_getmagic(struct drm_device *dev, void *data, | ||
928 | struct drm_file *file_priv); | ||
929 | extern int drm_authmagic(struct drm_device *dev, void *data, | ||
930 | struct drm_file *file_priv); | ||
931 | |||
932 | /* Locking IOCTL support (drm_lock.h) */ | ||
933 | extern int drm_lock(struct drm_device *dev, void *data, | ||
934 | struct drm_file *file_priv); | ||
935 | extern int drm_unlock(struct drm_device *dev, void *data, | ||
936 | struct drm_file *file_priv); | ||
937 | extern int drm_lock_take(struct drm_lock_data *lock_data, unsigned int context); | ||
938 | extern int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context); | ||
939 | extern void drm_idlelock_take(struct drm_lock_data *lock_data); | ||
940 | extern void drm_idlelock_release(struct drm_lock_data *lock_data); | ||
941 | |||
942 | /* | ||
943 | * These are exported to drivers so that they can implement fencing using | ||
944 | * DMA quiscent + idle. DMA quiescent usually requires the hardware lock. | ||
945 | */ | ||
946 | |||
947 | extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv); | ||
948 | |||
949 | /* Buffer management support (drm_bufs.h) */ | ||
950 | extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request); | ||
951 | extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request); | ||
952 | extern int drm_addmap(struct drm_device *dev, unsigned int offset, | ||
953 | unsigned int size, enum drm_map_type type, | ||
954 | enum drm_map_flags flags, drm_local_map_t ** map_ptr); | ||
955 | extern int drm_addmap_ioctl(struct drm_device *dev, void *data, | ||
956 | struct drm_file *file_priv); | ||
957 | extern int drm_rmmap(struct drm_device *dev, drm_local_map_t *map); | ||
958 | extern int drm_rmmap_locked(struct drm_device *dev, drm_local_map_t *map); | ||
959 | extern int drm_rmmap_ioctl(struct drm_device *dev, void *data, | ||
960 | struct drm_file *file_priv); | ||
961 | extern int drm_addbufs(struct drm_device *dev, void *data, | ||
962 | struct drm_file *file_priv); | ||
963 | extern int drm_infobufs(struct drm_device *dev, void *data, | ||
964 | struct drm_file *file_priv); | ||
965 | extern int drm_markbufs(struct drm_device *dev, void *data, | ||
966 | struct drm_file *file_priv); | ||
967 | extern int drm_freebufs(struct drm_device *dev, void *data, | ||
968 | struct drm_file *file_priv); | ||
969 | extern int drm_mapbufs(struct drm_device *dev, void *data, | ||
970 | struct drm_file *file_priv); | ||
971 | extern int drm_order(unsigned long size); | ||
972 | extern unsigned long drm_get_resource_start(struct drm_device *dev, | ||
973 | unsigned int resource); | ||
974 | extern unsigned long drm_get_resource_len(struct drm_device *dev, | ||
975 | unsigned int resource); | ||
976 | |||
977 | /* DMA support (drm_dma.h) */ | ||
978 | extern int drm_dma_setup(struct drm_device *dev); | ||
979 | extern void drm_dma_takedown(struct drm_device *dev); | ||
980 | extern void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf); | ||
981 | extern void drm_core_reclaim_buffers(struct drm_device *dev, | ||
982 | struct drm_file *filp); | ||
983 | |||
984 | /* IRQ support (drm_irq.h) */ | ||
985 | extern int drm_control(struct drm_device *dev, void *data, | ||
986 | struct drm_file *file_priv); | ||
987 | extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS); | ||
988 | extern int drm_irq_uninstall(struct drm_device *dev); | ||
989 | extern void drm_driver_irq_preinstall(struct drm_device *dev); | ||
990 | extern void drm_driver_irq_postinstall(struct drm_device *dev); | ||
991 | extern void drm_driver_irq_uninstall(struct drm_device *dev); | ||
992 | |||
993 | extern int drm_wait_vblank(struct drm_device *dev, void *data, | ||
994 | struct drm_file *file_priv); | ||
995 | extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq); | ||
996 | extern void drm_vbl_send_signals(struct drm_device *dev); | ||
997 | extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*)); | ||
998 | |||
999 | /* AGP/GART support (drm_agpsupport.h) */ | ||
1000 | extern struct drm_agp_head *drm_agp_init(struct drm_device *dev); | ||
1001 | extern int drm_agp_acquire(struct drm_device *dev); | ||
1002 | extern int drm_agp_acquire_ioctl(struct drm_device *dev, void *data, | ||
1003 | struct drm_file *file_priv); | ||
1004 | extern int drm_agp_release(struct drm_device *dev); | ||
1005 | extern int drm_agp_release_ioctl(struct drm_device *dev, void *data, | ||
1006 | struct drm_file *file_priv); | ||
1007 | extern int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode); | ||
1008 | extern int drm_agp_enable_ioctl(struct drm_device *dev, void *data, | ||
1009 | struct drm_file *file_priv); | ||
1010 | extern int drm_agp_info(struct drm_device *dev, struct drm_agp_info *info); | ||
1011 | extern int drm_agp_info_ioctl(struct drm_device *dev, void *data, | ||
1012 | struct drm_file *file_priv); | ||
1013 | extern int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request); | ||
1014 | extern int drm_agp_alloc_ioctl(struct drm_device *dev, void *data, | ||
1015 | struct drm_file *file_priv); | ||
1016 | extern int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request); | ||
1017 | extern int drm_agp_free_ioctl(struct drm_device *dev, void *data, | ||
1018 | struct drm_file *file_priv); | ||
1019 | extern int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request); | ||
1020 | extern int drm_agp_unbind_ioctl(struct drm_device *dev, void *data, | ||
1021 | struct drm_file *file_priv); | ||
1022 | extern int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request); | ||
1023 | extern int drm_agp_bind_ioctl(struct drm_device *dev, void *data, | ||
1024 | struct drm_file *file_priv); | ||
1025 | extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type); | ||
1026 | extern int drm_agp_free_memory(DRM_AGP_MEM * handle); | ||
1027 | extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start); | ||
1028 | extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle); | ||
1029 | |||
1030 | /* Stub support (drm_stub.h) */ | ||
1031 | extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, | ||
1032 | struct drm_driver *driver); | ||
1033 | extern int drm_put_dev(struct drm_device *dev); | ||
1034 | extern int drm_put_minor(struct drm_minor **minor); | ||
1035 | extern unsigned int drm_debug; | ||
1036 | |||
1037 | extern struct class *drm_class; | ||
1038 | extern struct proc_dir_entry *drm_proc_root; | ||
1039 | |||
1040 | extern struct idr drm_minors_idr; | ||
1041 | |||
1042 | extern drm_local_map_t *drm_getsarea(struct drm_device *dev); | ||
1043 | |||
1044 | /* Proc support (drm_proc.h) */ | ||
1045 | extern int drm_proc_init(struct drm_minor *minor, int minor_id, | ||
1046 | struct proc_dir_entry *root); | ||
1047 | extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root); | ||
1048 | |||
1049 | /* Scatter Gather Support (drm_scatter.h) */ | ||
1050 | extern void drm_sg_cleanup(struct drm_sg_mem * entry); | ||
1051 | extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data, | ||
1052 | struct drm_file *file_priv); | ||
1053 | extern int drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather * request); | ||
1054 | extern int drm_sg_free(struct drm_device *dev, void *data, | ||
1055 | struct drm_file *file_priv); | ||
1056 | |||
1057 | /* ATI PCIGART support (ati_pcigart.h) */ | ||
1058 | extern int drm_ati_pcigart_init(struct drm_device *dev, | ||
1059 | struct drm_ati_pcigart_info * gart_info); | ||
1060 | extern int drm_ati_pcigart_cleanup(struct drm_device *dev, | ||
1061 | struct drm_ati_pcigart_info * gart_info); | ||
1062 | |||
1063 | extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size, | ||
1064 | size_t align, dma_addr_t maxaddr); | ||
1065 | extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah); | ||
1066 | extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah); | ||
1067 | |||
1068 | /* sysfs support (drm_sysfs.c) */ | ||
1069 | struct drm_sysfs_class; | ||
1070 | extern struct class *drm_sysfs_create(struct module *owner, char *name); | ||
1071 | extern void drm_sysfs_destroy(void); | ||
1072 | extern int drm_sysfs_device_add(struct drm_minor *minor); | ||
1073 | extern void drm_sysfs_device_remove(struct drm_minor *minor); | ||
1074 | |||
1075 | /* | ||
1076 | * Basic memory manager support (drm_mm.c) | ||
1077 | */ | ||
1078 | extern struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent, | ||
1079 | unsigned long size, | ||
1080 | unsigned alignment); | ||
1081 | extern void drm_mm_put_block(struct drm_mm_node * cur); | ||
1082 | extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, unsigned long size, | ||
1083 | unsigned alignment, int best_match); | ||
1084 | extern int drm_mm_init(struct drm_mm *mm, unsigned long start, unsigned long size); | ||
1085 | extern void drm_mm_takedown(struct drm_mm *mm); | ||
1086 | extern int drm_mm_clean(struct drm_mm *mm); | ||
1087 | extern unsigned long drm_mm_tail_space(struct drm_mm *mm); | ||
1088 | extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size); | ||
1089 | extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size); | ||
1090 | |||
1091 | extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev); | ||
1092 | extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev); | ||
1093 | |||
1094 | static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, | ||
1095 | unsigned int token) | ||
1096 | { | ||
1097 | struct drm_map_list *_entry; | ||
1098 | list_for_each_entry(_entry, &dev->maplist, head) | ||
1099 | if (_entry->user_token == token) | ||
1100 | return _entry->map; | ||
1101 | return NULL; | ||
1102 | } | ||
1103 | |||
1104 | static __inline__ int drm_device_is_agp(struct drm_device *dev) | ||
1105 | { | ||
1106 | if (dev->driver->device_is_agp != NULL) { | ||
1107 | int err = (*dev->driver->device_is_agp) (dev); | ||
1108 | |||
1109 | if (err != 2) { | ||
1110 | return err; | ||
1111 | } | ||
1112 | } | ||
1113 | |||
1114 | return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP); | ||
1115 | } | ||
1116 | |||
1117 | static __inline__ int drm_device_is_pcie(struct drm_device *dev) | ||
1118 | { | ||
1119 | return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); | ||
1120 | } | ||
1121 | |||
1122 | static __inline__ void drm_core_dropmap(struct drm_map *map) | ||
1123 | { | ||
1124 | } | ||
1125 | |||
1126 | #ifndef DEBUG_MEMORY | ||
1127 | /** Wrapper around kmalloc() */ | ||
1128 | static __inline__ void *drm_alloc(size_t size, int area) | ||
1129 | { | ||
1130 | return kmalloc(size, GFP_KERNEL); | ||
1131 | } | ||
1132 | |||
1133 | /** Wrapper around kfree() */ | ||
1134 | static __inline__ void drm_free(void *pt, size_t size, int area) | ||
1135 | { | ||
1136 | kfree(pt); | ||
1137 | } | ||
1138 | |||
1139 | /** Wrapper around kcalloc() */ | ||
1140 | static __inline__ void *drm_calloc(size_t nmemb, size_t size, int area) | ||
1141 | { | ||
1142 | return kcalloc(nmemb, size, GFP_KERNEL); | ||
1143 | } | ||
1144 | #else | ||
1145 | extern void *drm_alloc(size_t size, int area); | ||
1146 | extern void drm_free(void *pt, size_t size, int area); | ||
1147 | extern void *drm_calloc(size_t nmemb, size_t size, int area); | ||
1148 | #endif | ||
1149 | |||
1150 | /*@}*/ | ||
1151 | |||
1152 | #endif /* __KERNEL__ */ | ||
1153 | #endif | ||
diff --git a/include/drm/drm_core.h b/include/drm/drm_core.h new file mode 100644 index 000000000000..316739036079 --- /dev/null +++ b/include/drm/drm_core.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright 2004 Jon Smirl <jonsmirl@gmail.com> | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the | ||
12 | * next paragraph) shall be included in all copies or substantial portions | ||
13 | * of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
18 | * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
21 | * DEALINGS IN THE SOFTWARE. | ||
22 | */ | ||
23 | #define CORE_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca, Jon Smirl" | ||
24 | |||
25 | #define CORE_NAME "drm" | ||
26 | #define CORE_DESC "DRM shared core routines" | ||
27 | #define CORE_DATE "20060810" | ||
28 | |||
29 | #define DRM_IF_MAJOR 1 | ||
30 | #define DRM_IF_MINOR 3 | ||
31 | |||
32 | #define CORE_MAJOR 1 | ||
33 | #define CORE_MINOR 1 | ||
34 | #define CORE_PATCHLEVEL 0 | ||
diff --git a/include/drm/drm_hashtab.h b/include/drm/drm_hashtab.h new file mode 100644 index 000000000000..cd2b189e1be6 --- /dev/null +++ b/include/drm/drm_hashtab.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2006 Tungsten Graphics, Inc., Bismack, ND. USA. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | * | ||
27 | **************************************************************************/ | ||
28 | /* | ||
29 | * Simple open hash tab implementation. | ||
30 | * | ||
31 | * Authors: | ||
32 | * Thomas Hellström <thomas-at-tungstengraphics-dot-com> | ||
33 | */ | ||
34 | |||
35 | #ifndef DRM_HASHTAB_H | ||
36 | #define DRM_HASHTAB_H | ||
37 | |||
38 | #define drm_hash_entry(_ptr, _type, _member) container_of(_ptr, _type, _member) | ||
39 | |||
40 | struct drm_hash_item { | ||
41 | struct hlist_node head; | ||
42 | unsigned long key; | ||
43 | }; | ||
44 | |||
45 | struct drm_open_hash { | ||
46 | unsigned int size; | ||
47 | unsigned int order; | ||
48 | unsigned int fill; | ||
49 | struct hlist_head *table; | ||
50 | int use_vmalloc; | ||
51 | }; | ||
52 | |||
53 | |||
54 | extern int drm_ht_create(struct drm_open_hash *ht, unsigned int order); | ||
55 | extern int drm_ht_insert_item(struct drm_open_hash *ht, struct drm_hash_item *item); | ||
56 | extern int drm_ht_just_insert_please(struct drm_open_hash *ht, struct drm_hash_item *item, | ||
57 | unsigned long seed, int bits, int shift, | ||
58 | unsigned long add); | ||
59 | extern int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key, struct drm_hash_item **item); | ||
60 | |||
61 | extern void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key); | ||
62 | extern int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key); | ||
63 | extern int drm_ht_remove_item(struct drm_open_hash *ht, struct drm_hash_item *item); | ||
64 | extern void drm_ht_remove(struct drm_open_hash *ht); | ||
65 | |||
66 | |||
67 | #endif | ||
diff --git a/include/drm/drm_memory.h b/include/drm/drm_memory.h new file mode 100644 index 000000000000..63e425b5ea82 --- /dev/null +++ b/include/drm/drm_memory.h | |||
@@ -0,0 +1,61 @@ | |||
1 | /** | ||
2 | * \file drm_memory.h | ||
3 | * Memory management wrappers for DRM | ||
4 | * | ||
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> | ||
6 | * \author Gareth Hughes <gareth@valinux.com> | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com | ||
11 | * | ||
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | ||
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
14 | * All Rights Reserved. | ||
15 | * | ||
16 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
17 | * copy of this software and associated documentation files (the "Software"), | ||
18 | * to deal in the Software without restriction, including without limitation | ||
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
20 | * and/or sell copies of the Software, and to permit persons to whom the | ||
21 | * Software is furnished to do so, subject to the following conditions: | ||
22 | * | ||
23 | * The above copyright notice and this permission notice (including the next | ||
24 | * paragraph) shall be included in all copies or substantial portions of the | ||
25 | * Software. | ||
26 | * | ||
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
33 | * OTHER DEALINGS IN THE SOFTWARE. | ||
34 | */ | ||
35 | |||
36 | #include <linux/highmem.h> | ||
37 | #include <linux/vmalloc.h> | ||
38 | #include "drmP.h" | ||
39 | |||
40 | /** | ||
41 | * Cut down version of drm_memory_debug.h, which used to be called | ||
42 | * drm_memory.h. | ||
43 | */ | ||
44 | |||
45 | #if __OS_HAS_AGP | ||
46 | |||
47 | #include <linux/vmalloc.h> | ||
48 | |||
49 | #ifdef HAVE_PAGE_AGP | ||
50 | #include <asm/agp.h> | ||
51 | #else | ||
52 | # ifdef __powerpc__ | ||
53 | # define PAGE_AGP __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) | ||
54 | # else | ||
55 | # define PAGE_AGP PAGE_KERNEL | ||
56 | # endif | ||
57 | #endif | ||
58 | |||
59 | #else /* __OS_HAS_AGP */ | ||
60 | |||
61 | #endif | ||
diff --git a/include/drm/drm_memory_debug.h b/include/drm/drm_memory_debug.h new file mode 100644 index 000000000000..6463271deea8 --- /dev/null +++ b/include/drm/drm_memory_debug.h | |||
@@ -0,0 +1,309 @@ | |||
1 | /** | ||
2 | * \file drm_memory_debug.h | ||
3 | * Memory management wrappers for DRM. | ||
4 | * | ||
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> | ||
6 | * \author Gareth Hughes <gareth@valinux.com> | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | ||
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
12 | * All Rights Reserved. | ||
13 | * | ||
14 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
15 | * copy of this software and associated documentation files (the "Software"), | ||
16 | * to deal in the Software without restriction, including without limitation | ||
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
18 | * and/or sell copies of the Software, and to permit persons to whom the | ||
19 | * Software is furnished to do so, subject to the following conditions: | ||
20 | * | ||
21 | * The above copyright notice and this permission notice (including the next | ||
22 | * paragraph) shall be included in all copies or substantial portions of the | ||
23 | * Software. | ||
24 | * | ||
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
28 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
31 | * OTHER DEALINGS IN THE SOFTWARE. | ||
32 | */ | ||
33 | |||
34 | #include "drmP.h" | ||
35 | |||
36 | typedef struct drm_mem_stats { | ||
37 | const char *name; | ||
38 | int succeed_count; | ||
39 | int free_count; | ||
40 | int fail_count; | ||
41 | unsigned long bytes_allocated; | ||
42 | unsigned long bytes_freed; | ||
43 | } drm_mem_stats_t; | ||
44 | |||
45 | static DEFINE_SPINLOCK(drm_mem_lock); | ||
46 | static unsigned long drm_ram_available = 0; /* In pages */ | ||
47 | static unsigned long drm_ram_used = 0; | ||
48 | static drm_mem_stats_t drm_mem_stats[] = | ||
49 | { | ||
50 | [DRM_MEM_DMA] = {"dmabufs"}, | ||
51 | [DRM_MEM_SAREA] = {"sareas"}, | ||
52 | [DRM_MEM_DRIVER] = {"driver"}, | ||
53 | [DRM_MEM_MAGIC] = {"magic"}, | ||
54 | [DRM_MEM_IOCTLS] = {"ioctltab"}, | ||
55 | [DRM_MEM_MAPS] = {"maplist"}, | ||
56 | [DRM_MEM_VMAS] = {"vmalist"}, | ||
57 | [DRM_MEM_BUFS] = {"buflist"}, | ||
58 | [DRM_MEM_SEGS] = {"seglist"}, | ||
59 | [DRM_MEM_PAGES] = {"pagelist"}, | ||
60 | [DRM_MEM_FILES] = {"files"}, | ||
61 | [DRM_MEM_QUEUES] = {"queues"}, | ||
62 | [DRM_MEM_CMDS] = {"commands"}, | ||
63 | [DRM_MEM_MAPPINGS] = {"mappings"}, | ||
64 | [DRM_MEM_BUFLISTS] = {"buflists"}, | ||
65 | [DRM_MEM_AGPLISTS] = {"agplist"}, | ||
66 | [DRM_MEM_SGLISTS] = {"sglist"}, | ||
67 | [DRM_MEM_TOTALAGP] = {"totalagp"}, | ||
68 | [DRM_MEM_BOUNDAGP] = {"boundagp"}, | ||
69 | [DRM_MEM_CTXBITMAP] = {"ctxbitmap"}, | ||
70 | [DRM_MEM_CTXLIST] = {"ctxlist"}, | ||
71 | [DRM_MEM_STUB] = {"stub"}, | ||
72 | {NULL, 0,} /* Last entry must be null */ | ||
73 | }; | ||
74 | |||
75 | void drm_mem_init (void) { | ||
76 | drm_mem_stats_t *mem; | ||
77 | struct sysinfo si; | ||
78 | |||
79 | for (mem = drm_mem_stats; mem->name; ++mem) { | ||
80 | mem->succeed_count = 0; | ||
81 | mem->free_count = 0; | ||
82 | mem->fail_count = 0; | ||
83 | mem->bytes_allocated = 0; | ||
84 | mem->bytes_freed = 0; | ||
85 | } | ||
86 | |||
87 | si_meminfo(&si); | ||
88 | drm_ram_available = si.totalram; | ||
89 | drm_ram_used = 0; | ||
90 | } | ||
91 | |||
92 | /* drm_mem_info is called whenever a process reads /dev/drm/mem. */ | ||
93 | |||
94 | static int drm__mem_info (char *buf, char **start, off_t offset, | ||
95 | int request, int *eof, void *data) { | ||
96 | drm_mem_stats_t *pt; | ||
97 | int len = 0; | ||
98 | |||
99 | if (offset > DRM_PROC_LIMIT) { | ||
100 | *eof = 1; | ||
101 | return 0; | ||
102 | } | ||
103 | |||
104 | *eof = 0; | ||
105 | *start = &buf[offset]; | ||
106 | |||
107 | DRM_PROC_PRINT(" total counts " | ||
108 | " | outstanding \n"); | ||
109 | DRM_PROC_PRINT("type alloc freed fail bytes freed" | ||
110 | " | allocs bytes\n\n"); | ||
111 | DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", | ||
112 | "system", 0, 0, 0, | ||
113 | drm_ram_available << (PAGE_SHIFT - 10)); | ||
114 | DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n", | ||
115 | "locked", 0, 0, 0, drm_ram_used >> 10); | ||
116 | DRM_PROC_PRINT("\n"); | ||
117 | for (pt = drm_mem_stats; pt->name; pt++) { | ||
118 | DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n", | ||
119 | pt->name, | ||
120 | pt->succeed_count, | ||
121 | pt->free_count, | ||
122 | pt->fail_count, | ||
123 | pt->bytes_allocated, | ||
124 | pt->bytes_freed, | ||
125 | pt->succeed_count - pt->free_count, | ||
126 | (long)pt->bytes_allocated | ||
127 | - (long)pt->bytes_freed); | ||
128 | } | ||
129 | |||
130 | if (len > request + offset) | ||
131 | return request; | ||
132 | *eof = 1; | ||
133 | return len - offset; | ||
134 | } | ||
135 | |||
136 | int drm_mem_info (char *buf, char **start, off_t offset, | ||
137 | int len, int *eof, void *data) { | ||
138 | int ret; | ||
139 | |||
140 | spin_lock(&drm_mem_lock); | ||
141 | ret = drm__mem_info (buf, start, offset, len, eof, data); | ||
142 | spin_unlock(&drm_mem_lock); | ||
143 | return ret; | ||
144 | } | ||
145 | |||
146 | void *drm_alloc (size_t size, int area) { | ||
147 | void *pt; | ||
148 | |||
149 | if (!size) { | ||
150 | DRM_MEM_ERROR(area, "Allocating 0 bytes\n"); | ||
151 | return NULL; | ||
152 | } | ||
153 | |||
154 | if (!(pt = kmalloc(size, GFP_KERNEL))) { | ||
155 | spin_lock(&drm_mem_lock); | ||
156 | ++drm_mem_stats[area].fail_count; | ||
157 | spin_unlock(&drm_mem_lock); | ||
158 | return NULL; | ||
159 | } | ||
160 | spin_lock(&drm_mem_lock); | ||
161 | ++drm_mem_stats[area].succeed_count; | ||
162 | drm_mem_stats[area].bytes_allocated += size; | ||
163 | spin_unlock(&drm_mem_lock); | ||
164 | return pt; | ||
165 | } | ||
166 | |||
167 | void *drm_calloc (size_t nmemb, size_t size, int area) { | ||
168 | void *addr; | ||
169 | |||
170 | addr = drm_alloc (nmemb * size, area); | ||
171 | if (addr != NULL) | ||
172 | memset((void *)addr, 0, size * nmemb); | ||
173 | |||
174 | return addr; | ||
175 | } | ||
176 | |||
177 | void *drm_realloc (void *oldpt, size_t oldsize, size_t size, int area) { | ||
178 | void *pt; | ||
179 | |||
180 | if (!(pt = drm_alloc (size, area))) | ||
181 | return NULL; | ||
182 | if (oldpt && oldsize) { | ||
183 | memcpy(pt, oldpt, oldsize); | ||
184 | drm_free (oldpt, oldsize, area); | ||
185 | } | ||
186 | return pt; | ||
187 | } | ||
188 | |||
189 | void drm_free (void *pt, size_t size, int area) { | ||
190 | int alloc_count; | ||
191 | int free_count; | ||
192 | |||
193 | if (!pt) | ||
194 | DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); | ||
195 | else | ||
196 | kfree(pt); | ||
197 | spin_lock(&drm_mem_lock); | ||
198 | drm_mem_stats[area].bytes_freed += size; | ||
199 | free_count = ++drm_mem_stats[area].free_count; | ||
200 | alloc_count = drm_mem_stats[area].succeed_count; | ||
201 | spin_unlock(&drm_mem_lock); | ||
202 | if (free_count > alloc_count) { | ||
203 | DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", | ||
204 | free_count, alloc_count); | ||
205 | } | ||
206 | } | ||
207 | |||
208 | #if __OS_HAS_AGP | ||
209 | |||
210 | DRM_AGP_MEM *drm_alloc_agp (drm_device_t *dev, int pages, u32 type) { | ||
211 | DRM_AGP_MEM *handle; | ||
212 | |||
213 | if (!pages) { | ||
214 | DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n"); | ||
215 | return NULL; | ||
216 | } | ||
217 | |||
218 | if ((handle = drm_agp_allocate_memory (pages, type))) { | ||
219 | spin_lock(&drm_mem_lock); | ||
220 | ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; | ||
221 | drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated | ||
222 | += pages << PAGE_SHIFT; | ||
223 | spin_unlock(&drm_mem_lock); | ||
224 | return handle; | ||
225 | } | ||
226 | spin_lock(&drm_mem_lock); | ||
227 | ++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count; | ||
228 | spin_unlock(&drm_mem_lock); | ||
229 | return NULL; | ||
230 | } | ||
231 | |||
232 | int drm_free_agp (DRM_AGP_MEM * handle, int pages) { | ||
233 | int alloc_count; | ||
234 | int free_count; | ||
235 | int retval = -EINVAL; | ||
236 | |||
237 | if (!handle) { | ||
238 | DRM_MEM_ERROR(DRM_MEM_TOTALAGP, | ||
239 | "Attempt to free NULL AGP handle\n"); | ||
240 | return retval; | ||
241 | } | ||
242 | |||
243 | if (drm_agp_free_memory (handle)) { | ||
244 | spin_lock(&drm_mem_lock); | ||
245 | free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count; | ||
246 | alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; | ||
247 | drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed | ||
248 | += pages << PAGE_SHIFT; | ||
249 | spin_unlock(&drm_mem_lock); | ||
250 | if (free_count > alloc_count) { | ||
251 | DRM_MEM_ERROR(DRM_MEM_TOTALAGP, | ||
252 | "Excess frees: %d frees, %d allocs\n", | ||
253 | free_count, alloc_count); | ||
254 | } | ||
255 | return 0; | ||
256 | } | ||
257 | return retval; | ||
258 | } | ||
259 | |||
260 | int drm_bind_agp (DRM_AGP_MEM * handle, unsigned int start) { | ||
261 | int retcode = -EINVAL; | ||
262 | |||
263 | if (!handle) { | ||
264 | DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, | ||
265 | "Attempt to bind NULL AGP handle\n"); | ||
266 | return retcode; | ||
267 | } | ||
268 | |||
269 | if (!(retcode = drm_agp_bind_memory (handle, start))) { | ||
270 | spin_lock(&drm_mem_lock); | ||
271 | ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; | ||
272 | drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated | ||
273 | += handle->page_count << PAGE_SHIFT; | ||
274 | spin_unlock(&drm_mem_lock); | ||
275 | return retcode; | ||
276 | } | ||
277 | spin_lock(&drm_mem_lock); | ||
278 | ++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count; | ||
279 | spin_unlock(&drm_mem_lock); | ||
280 | return retcode; | ||
281 | } | ||
282 | |||
283 | int drm_unbind_agp (DRM_AGP_MEM * handle) { | ||
284 | int alloc_count; | ||
285 | int free_count; | ||
286 | int retcode = -EINVAL; | ||
287 | |||
288 | if (!handle) { | ||
289 | DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, | ||
290 | "Attempt to unbind NULL AGP handle\n"); | ||
291 | return retcode; | ||
292 | } | ||
293 | |||
294 | if ((retcode = drm_agp_unbind_memory (handle))) | ||
295 | return retcode; | ||
296 | spin_lock(&drm_mem_lock); | ||
297 | free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count; | ||
298 | alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; | ||
299 | drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed | ||
300 | += handle->page_count << PAGE_SHIFT; | ||
301 | spin_unlock(&drm_mem_lock); | ||
302 | if (free_count > alloc_count) { | ||
303 | DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, | ||
304 | "Excess frees: %d frees, %d allocs\n", | ||
305 | free_count, alloc_count); | ||
306 | } | ||
307 | return retcode; | ||
308 | } | ||
309 | #endif | ||
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h new file mode 100644 index 000000000000..8dbd2572b7c3 --- /dev/null +++ b/include/drm/drm_os_linux.h | |||
@@ -0,0 +1,108 @@ | |||
1 | /** | ||
2 | * \file drm_os_linux.h | ||
3 | * OS abstraction macros. | ||
4 | */ | ||
5 | |||
6 | #include <linux/interrupt.h> /* For task queue support */ | ||
7 | #include <linux/delay.h> | ||
8 | |||
9 | /** Current process ID */ | ||
10 | #define DRM_CURRENTPID task_pid_nr(current) | ||
11 | #define DRM_SUSER(p) capable(CAP_SYS_ADMIN) | ||
12 | #define DRM_UDELAY(d) udelay(d) | ||
13 | /** Read a byte from a MMIO region */ | ||
14 | #define DRM_READ8(map, offset) readb(((void __iomem *)(map)->handle) + (offset)) | ||
15 | /** Read a word from a MMIO region */ | ||
16 | #define DRM_READ16(map, offset) readw(((void __iomem *)(map)->handle) + (offset)) | ||
17 | /** Read a dword from a MMIO region */ | ||
18 | #define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset)) | ||
19 | /** Write a byte into a MMIO region */ | ||
20 | #define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset)) | ||
21 | /** Write a word into a MMIO region */ | ||
22 | #define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset)) | ||
23 | /** Write a dword into a MMIO region */ | ||
24 | #define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset)) | ||
25 | /** Read memory barrier */ | ||
26 | #define DRM_READMEMORYBARRIER() rmb() | ||
27 | /** Write memory barrier */ | ||
28 | #define DRM_WRITEMEMORYBARRIER() wmb() | ||
29 | /** Read/write memory barrier */ | ||
30 | #define DRM_MEMORYBARRIER() mb() | ||
31 | |||
32 | /** IRQ handler arguments and return type and values */ | ||
33 | #define DRM_IRQ_ARGS int irq, void *arg | ||
34 | |||
35 | /** AGP types */ | ||
36 | #if __OS_HAS_AGP | ||
37 | #define DRM_AGP_MEM struct agp_memory | ||
38 | #define DRM_AGP_KERN struct agp_kern_info | ||
39 | #else | ||
40 | /* define some dummy types for non AGP supporting kernels */ | ||
41 | struct no_agp_kern { | ||
42 | unsigned long aper_base; | ||
43 | unsigned long aper_size; | ||
44 | }; | ||
45 | #define DRM_AGP_MEM int | ||
46 | #define DRM_AGP_KERN struct no_agp_kern | ||
47 | #endif | ||
48 | |||
49 | #if !(__OS_HAS_MTRR) | ||
50 | static __inline__ int mtrr_add(unsigned long base, unsigned long size, | ||
51 | unsigned int type, char increment) | ||
52 | { | ||
53 | return -ENODEV; | ||
54 | } | ||
55 | |||
56 | static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size) | ||
57 | { | ||
58 | return -ENODEV; | ||
59 | } | ||
60 | |||
61 | #define MTRR_TYPE_WRCOMB 1 | ||
62 | |||
63 | #endif | ||
64 | |||
65 | /** Other copying of data to kernel space */ | ||
66 | #define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ | ||
67 | copy_from_user(arg1, arg2, arg3) | ||
68 | /** Other copying of data from kernel space */ | ||
69 | #define DRM_COPY_TO_USER(arg1, arg2, arg3) \ | ||
70 | copy_to_user(arg1, arg2, arg3) | ||
71 | /* Macros for copyfrom user, but checking readability only once */ | ||
72 | #define DRM_VERIFYAREA_READ( uaddr, size ) \ | ||
73 | (access_ok( VERIFY_READ, uaddr, size ) ? 0 : -EFAULT) | ||
74 | #define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \ | ||
75 | __copy_from_user(arg1, arg2, arg3) | ||
76 | #define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \ | ||
77 | __copy_to_user(arg1, arg2, arg3) | ||
78 | #define DRM_GET_USER_UNCHECKED(val, uaddr) \ | ||
79 | __get_user(val, uaddr) | ||
80 | |||
81 | #define DRM_HZ HZ | ||
82 | |||
83 | #define DRM_WAIT_ON( ret, queue, timeout, condition ) \ | ||
84 | do { \ | ||
85 | DECLARE_WAITQUEUE(entry, current); \ | ||
86 | unsigned long end = jiffies + (timeout); \ | ||
87 | add_wait_queue(&(queue), &entry); \ | ||
88 | \ | ||
89 | for (;;) { \ | ||
90 | __set_current_state(TASK_INTERRUPTIBLE); \ | ||
91 | if (condition) \ | ||
92 | break; \ | ||
93 | if (time_after_eq(jiffies, end)) { \ | ||
94 | ret = -EBUSY; \ | ||
95 | break; \ | ||
96 | } \ | ||
97 | schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \ | ||
98 | if (signal_pending(current)) { \ | ||
99 | ret = -EINTR; \ | ||
100 | break; \ | ||
101 | } \ | ||
102 | } \ | ||
103 | __set_current_state(TASK_RUNNING); \ | ||
104 | remove_wait_queue(&(queue), &entry); \ | ||
105 | } while (0) | ||
106 | |||
107 | #define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) | ||
108 | #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) | ||
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h new file mode 100644 index 000000000000..135bd19499fc --- /dev/null +++ b/include/drm/drm_pciids.h | |||
@@ -0,0 +1,415 @@ | |||
1 | /* | ||
2 | This file is auto-generated from the drm_pciids.txt in the DRM CVS | ||
3 | Please contact dri-devel@lists.sf.net to add new cards to this list | ||
4 | */ | ||
5 | #define radeon_PCI_IDS \ | ||
6 | {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ | ||
7 | {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
8 | {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
9 | {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
10 | {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
11 | {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ | ||
12 | {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ | ||
13 | {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
14 | {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
15 | {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
16 | {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
17 | {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
18 | {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
19 | {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
20 | {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
21 | {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
22 | {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
23 | {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
24 | {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
25 | {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
26 | {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
27 | {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ | ||
28 | {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ | ||
29 | {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ | ||
30 | {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ | ||
31 | {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ | ||
32 | {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ | ||
33 | {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ | ||
34 | {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ | ||
35 | {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ | ||
36 | {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
37 | {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
38 | {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
39 | {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
40 | {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
41 | {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
42 | {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
43 | {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
44 | {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
45 | {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
46 | {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
47 | {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
48 | {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
49 | {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
50 | {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ | ||
51 | {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ | ||
52 | {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ | ||
53 | {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ | ||
54 | {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ | ||
55 | {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ | ||
56 | {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ | ||
57 | {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
58 | {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
59 | {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
60 | {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ | ||
61 | {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
62 | {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
63 | {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
64 | {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ | ||
65 | {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
66 | {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
67 | {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
68 | {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
69 | {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
70 | {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ | ||
71 | {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ | ||
72 | {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ | ||
73 | {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ | ||
74 | {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ | ||
75 | {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ | ||
76 | {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ | ||
77 | {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ | ||
78 | {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ | ||
79 | {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ | ||
80 | {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ | ||
81 | {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ | ||
82 | {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ | ||
83 | {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ | ||
84 | {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ | ||
85 | {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ | ||
86 | {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
87 | {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
88 | {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
89 | {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
90 | {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
91 | {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
92 | {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
93 | {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
94 | {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
95 | {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
96 | {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
97 | {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
98 | {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
99 | {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
100 | {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
101 | {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
102 | {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
103 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
104 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ | ||
105 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ | ||
106 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
107 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
108 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
109 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
110 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | ||
111 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | ||
112 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | ||
113 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | ||
114 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | ||
115 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ | ||
116 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
117 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
118 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
119 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
120 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
121 | {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
122 | {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | ||
123 | {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ | ||
124 | {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ | ||
125 | {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
126 | {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
127 | {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
128 | {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
129 | {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
130 | {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
131 | {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
132 | {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
133 | {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
134 | {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ | ||
135 | {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
136 | {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
137 | {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
138 | {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
139 | {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
140 | {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ | ||
141 | {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
142 | {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
143 | {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
144 | {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
145 | {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
146 | {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
147 | {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
148 | {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
149 | {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
150 | {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
151 | {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
152 | {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
153 | {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
154 | {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ | ||
155 | {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
156 | {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
157 | {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
158 | {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
159 | {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
160 | {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
161 | {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
162 | {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
163 | {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
164 | {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
165 | {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
166 | {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
167 | {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
168 | {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
169 | {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
170 | {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
171 | {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
172 | {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
173 | {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
174 | {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
175 | {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
176 | {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
177 | {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
178 | {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
179 | {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
180 | {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
181 | {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
182 | {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
183 | {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
184 | {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
185 | {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
186 | {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
187 | {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
188 | {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
189 | {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
190 | {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
191 | {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
192 | {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
193 | {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
194 | {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
195 | {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
196 | {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
197 | {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
198 | {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
199 | {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
200 | {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
201 | {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
202 | {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
203 | {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
204 | {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ | ||
205 | {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
206 | {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ | ||
207 | {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
208 | {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
209 | {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
210 | {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
211 | {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
212 | {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
213 | {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
214 | {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
215 | {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
216 | {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
217 | {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
218 | {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
219 | {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
220 | {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
221 | {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
222 | {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ | ||
223 | {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ | ||
224 | {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
225 | {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
226 | {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
227 | {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
228 | {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ | ||
229 | {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ | ||
230 | {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ | ||
231 | {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ | ||
232 | {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
233 | {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
234 | {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
235 | {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ | ||
236 | {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ | ||
237 | {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | ||
238 | {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ | ||
239 | {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ | ||
240 | {0, 0, 0} | ||
241 | |||
242 | #define r128_PCI_IDS \ | ||
243 | {0x1002, 0x4c45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
244 | {0x1002, 0x4c46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
245 | {0x1002, 0x4d46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
246 | {0x1002, 0x4d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
247 | {0x1002, 0x5041, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
248 | {0x1002, 0x5042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
249 | {0x1002, 0x5043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
250 | {0x1002, 0x5044, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
251 | {0x1002, 0x5045, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
252 | {0x1002, 0x5046, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
253 | {0x1002, 0x5047, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
254 | {0x1002, 0x5048, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
255 | {0x1002, 0x5049, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
256 | {0x1002, 0x504A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
257 | {0x1002, 0x504B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
258 | {0x1002, 0x504C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
259 | {0x1002, 0x504D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
260 | {0x1002, 0x504E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
261 | {0x1002, 0x504F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
262 | {0x1002, 0x5050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
263 | {0x1002, 0x5051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
264 | {0x1002, 0x5052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
265 | {0x1002, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
266 | {0x1002, 0x5054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
267 | {0x1002, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
268 | {0x1002, 0x5056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
269 | {0x1002, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
270 | {0x1002, 0x5058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
271 | {0x1002, 0x5245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
272 | {0x1002, 0x5246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
273 | {0x1002, 0x5247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
274 | {0x1002, 0x524b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
275 | {0x1002, 0x524c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
276 | {0x1002, 0x534d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
277 | {0x1002, 0x5446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
278 | {0x1002, 0x544C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
279 | {0x1002, 0x5452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
280 | {0, 0, 0} | ||
281 | |||
282 | #define mga_PCI_IDS \ | ||
283 | {0x102b, 0x0520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \ | ||
284 | {0x102b, 0x0521, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \ | ||
285 | {0x102b, 0x0525, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G400}, \ | ||
286 | {0x102b, 0x2527, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G550}, \ | ||
287 | {0, 0, 0} | ||
288 | |||
289 | #define mach64_PCI_IDS \ | ||
290 | {0x1002, 0x4749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
291 | {0x1002, 0x4750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
292 | {0x1002, 0x4751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
293 | {0x1002, 0x4742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
294 | {0x1002, 0x4744, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
295 | {0x1002, 0x4c49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
296 | {0x1002, 0x4c50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
297 | {0x1002, 0x4c51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
298 | {0x1002, 0x4c42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
299 | {0x1002, 0x4c44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
300 | {0x1002, 0x474c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
301 | {0x1002, 0x474f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
302 | {0x1002, 0x4752, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
303 | {0x1002, 0x4753, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
304 | {0x1002, 0x474d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
305 | {0x1002, 0x474e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
306 | {0x1002, 0x4c52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
307 | {0x1002, 0x4c53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
308 | {0x1002, 0x4c4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
309 | {0x1002, 0x4c4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
310 | {0, 0, 0} | ||
311 | |||
312 | #define sisdrv_PCI_IDS \ | ||
313 | {0x1039, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
314 | {0x1039, 0x5300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
315 | {0x1039, 0x6300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
316 | {0x1039, 0x6330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \ | ||
317 | {0x1039, 0x6351, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
318 | {0x1039, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
319 | {0x18CA, 0x0040, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \ | ||
320 | {0x18CA, 0x0042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \ | ||
321 | {0, 0, 0} | ||
322 | |||
323 | #define tdfx_PCI_IDS \ | ||
324 | {0x121a, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
325 | {0x121a, 0x0004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
326 | {0x121a, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
327 | {0x121a, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
328 | {0x121a, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
329 | {0x121a, 0x000b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
330 | {0, 0, 0} | ||
331 | |||
332 | #define viadrv_PCI_IDS \ | ||
333 | {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
334 | {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \ | ||
335 | {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
336 | {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
337 | {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
338 | {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
339 | {0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
340 | {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \ | ||
341 | {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \ | ||
342 | {0, 0, 0} | ||
343 | |||
344 | #define i810_PCI_IDS \ | ||
345 | {0x8086, 0x7121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
346 | {0x8086, 0x7123, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
347 | {0x8086, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
348 | {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
349 | {0, 0, 0} | ||
350 | |||
351 | #define i830_PCI_IDS \ | ||
352 | {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
353 | {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
354 | {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
355 | {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
356 | {0, 0, 0} | ||
357 | |||
358 | #define gamma_PCI_IDS \ | ||
359 | {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
360 | {0, 0, 0} | ||
361 | |||
362 | #define savage_PCI_IDS \ | ||
363 | {0x5333, 0x8a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \ | ||
364 | {0x5333, 0x8a21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \ | ||
365 | {0x5333, 0x8a22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \ | ||
366 | {0x5333, 0x8a23, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \ | ||
367 | {0x5333, 0x8c10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \ | ||
368 | {0x5333, 0x8c11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \ | ||
369 | {0x5333, 0x8c12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \ | ||
370 | {0x5333, 0x8c13, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \ | ||
371 | {0x5333, 0x8c22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
372 | {0x5333, 0x8c24, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
373 | {0x5333, 0x8c26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
374 | {0x5333, 0x8c2a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
375 | {0x5333, 0x8c2b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
376 | {0x5333, 0x8c2c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
377 | {0x5333, 0x8c2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
378 | {0x5333, 0x8c2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
379 | {0x5333, 0x8c2f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \ | ||
380 | {0x5333, 0x8a25, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \ | ||
381 | {0x5333, 0x8a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \ | ||
382 | {0x5333, 0x8d01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \ | ||
383 | {0x5333, 0x8d02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \ | ||
384 | {0x5333, 0x8d03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \ | ||
385 | {0x5333, 0x8d04, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \ | ||
386 | {0, 0, 0} | ||
387 | |||
388 | #define ffb_PCI_IDS \ | ||
389 | {0, 0, 0} | ||
390 | |||
391 | #define i915_PCI_IDS \ | ||
392 | {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
393 | {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
394 | {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
395 | {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
396 | {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
397 | {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
398 | {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
399 | {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
400 | {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
401 | {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
402 | {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
403 | {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
404 | {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
405 | {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
406 | {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
407 | {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
408 | {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
409 | {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
410 | {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
411 | {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
412 | {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
413 | {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
414 | {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
415 | {0, 0, 0} | ||
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h new file mode 100644 index 000000000000..480037331e4e --- /dev/null +++ b/include/drm/drm_sarea.h | |||
@@ -0,0 +1,84 @@ | |||
1 | /** | ||
2 | * \file drm_sarea.h | ||
3 | * \brief SAREA definitions | ||
4 | * | ||
5 | * \author Michel Dänzer <michel@daenzer.net> | ||
6 | */ | ||
7 | |||
8 | /* | ||
9 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
10 | * All Rights Reserved. | ||
11 | * | ||
12 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
13 | * copy of this software and associated documentation files (the "Software"), | ||
14 | * to deal in the Software without restriction, including without limitation | ||
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
16 | * and/or sell copies of the Software, and to permit persons to whom the | ||
17 | * Software is furnished to do so, subject to the following conditions: | ||
18 | * | ||
19 | * The above copyright notice and this permission notice (including the next | ||
20 | * paragraph) shall be included in all copies or substantial portions of the | ||
21 | * Software. | ||
22 | * | ||
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
26 | * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
29 | * OTHER DEALINGS IN THE SOFTWARE. | ||
30 | */ | ||
31 | |||
32 | #ifndef _DRM_SAREA_H_ | ||
33 | #define _DRM_SAREA_H_ | ||
34 | |||
35 | #include "drm.h" | ||
36 | |||
37 | /* SAREA area needs to be at least a page */ | ||
38 | #if defined(__alpha__) | ||
39 | #define SAREA_MAX 0x2000 | ||
40 | #elif defined(__ia64__) | ||
41 | #define SAREA_MAX 0x10000 /* 64kB */ | ||
42 | #else | ||
43 | /* Intel 830M driver needs at least 8k SAREA */ | ||
44 | #define SAREA_MAX 0x2000 | ||
45 | #endif | ||
46 | |||
47 | /** Maximum number of drawables in the SAREA */ | ||
48 | #define SAREA_MAX_DRAWABLES 256 | ||
49 | |||
50 | #define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 | ||
51 | |||
52 | /** SAREA drawable */ | ||
53 | struct drm_sarea_drawable { | ||
54 | unsigned int stamp; | ||
55 | unsigned int flags; | ||
56 | }; | ||
57 | |||
58 | /** SAREA frame */ | ||
59 | struct drm_sarea_frame { | ||
60 | unsigned int x; | ||
61 | unsigned int y; | ||
62 | unsigned int width; | ||
63 | unsigned int height; | ||
64 | unsigned int fullscreen; | ||
65 | }; | ||
66 | |||
67 | /** SAREA */ | ||
68 | struct drm_sarea { | ||
69 | /** first thing is always the DRM locking structure */ | ||
70 | struct drm_hw_lock lock; | ||
71 | /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ | ||
72 | struct drm_hw_lock drawable_lock; | ||
73 | struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ | ||
74 | struct drm_sarea_frame frame; /**< frame */ | ||
75 | drm_context_t dummy_context; | ||
76 | }; | ||
77 | |||
78 | #ifndef __KERNEL__ | ||
79 | typedef struct drm_sarea_drawable drm_sarea_drawable_t; | ||
80 | typedef struct drm_sarea_frame drm_sarea_frame_t; | ||
81 | typedef struct drm_sarea drm_sarea_t; | ||
82 | #endif | ||
83 | |||
84 | #endif /* _DRM_SAREA_H_ */ | ||
diff --git a/include/drm/drm_sman.h b/include/drm/drm_sman.h new file mode 100644 index 000000000000..08ecf83ad5d4 --- /dev/null +++ b/include/drm/drm_sman.h | |||
@@ -0,0 +1,176 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA. | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | * | ||
27 | **************************************************************************/ | ||
28 | /* | ||
29 | * Simple memory MANager interface that keeps track on allocate regions on a | ||
30 | * per "owner" basis. All regions associated with an "owner" can be released | ||
31 | * with a simple call. Typically if the "owner" exists. The owner is any | ||
32 | * "unsigned long" identifier. Can typically be a pointer to a file private | ||
33 | * struct or a context identifier. | ||
34 | * | ||
35 | * Authors: | ||
36 | * Thomas Hellström <thomas-at-tungstengraphics-dot-com> | ||
37 | */ | ||
38 | |||
39 | #ifndef DRM_SMAN_H | ||
40 | #define DRM_SMAN_H | ||
41 | |||
42 | #include "drmP.h" | ||
43 | #include "drm_hashtab.h" | ||
44 | |||
45 | /* | ||
46 | * A class that is an abstration of a simple memory allocator. | ||
47 | * The sman implementation provides a default such allocator | ||
48 | * using the drm_mm.c implementation. But the user can replace it. | ||
49 | * See the SiS implementation, which may use the SiS FB kernel module | ||
50 | * for memory management. | ||
51 | */ | ||
52 | |||
53 | struct drm_sman_mm { | ||
54 | /* private info. If allocated, needs to be destroyed by the destroy | ||
55 | function */ | ||
56 | void *private; | ||
57 | |||
58 | /* Allocate a memory block with given size and alignment. | ||
59 | Return an opaque reference to the memory block */ | ||
60 | |||
61 | void *(*allocate) (void *private, unsigned long size, | ||
62 | unsigned alignment); | ||
63 | |||
64 | /* Free a memory block. "ref" is the opaque reference that we got from | ||
65 | the "alloc" function */ | ||
66 | |||
67 | void (*free) (void *private, void *ref); | ||
68 | |||
69 | /* Free all resources associated with this allocator */ | ||
70 | |||
71 | void (*destroy) (void *private); | ||
72 | |||
73 | /* Return a memory offset from the opaque reference returned from the | ||
74 | "alloc" function */ | ||
75 | |||
76 | unsigned long (*offset) (void *private, void *ref); | ||
77 | }; | ||
78 | |||
79 | struct drm_memblock_item { | ||
80 | struct list_head owner_list; | ||
81 | struct drm_hash_item user_hash; | ||
82 | void *mm_info; | ||
83 | struct drm_sman_mm *mm; | ||
84 | struct drm_sman *sman; | ||
85 | }; | ||
86 | |||
87 | struct drm_sman { | ||
88 | struct drm_sman_mm *mm; | ||
89 | int num_managers; | ||
90 | struct drm_open_hash owner_hash_tab; | ||
91 | struct drm_open_hash user_hash_tab; | ||
92 | struct list_head owner_items; | ||
93 | }; | ||
94 | |||
95 | /* | ||
96 | * Take down a memory manager. This function should only be called after a | ||
97 | * successful init and after a call to drm_sman_cleanup. | ||
98 | */ | ||
99 | |||
100 | extern void drm_sman_takedown(struct drm_sman * sman); | ||
101 | |||
102 | /* | ||
103 | * Allocate structures for a manager. | ||
104 | * num_managers are the number of memory pools to manage. (VRAM, AGP, ....) | ||
105 | * user_order is the log2 of the number of buckets in the user hash table. | ||
106 | * set this to approximately log2 of the max number of memory regions | ||
107 | * that will be allocated for _all_ pools together. | ||
108 | * owner_order is the log2 of the number of buckets in the owner hash table. | ||
109 | * set this to approximately log2 of | ||
110 | * the number of client file connections that will | ||
111 | * be using the manager. | ||
112 | * | ||
113 | */ | ||
114 | |||
115 | extern int drm_sman_init(struct drm_sman * sman, unsigned int num_managers, | ||
116 | unsigned int user_order, unsigned int owner_order); | ||
117 | |||
118 | /* | ||
119 | * Initialize a drm_mm.c allocator. Should be called only once for each | ||
120 | * manager unless a customized allogator is used. | ||
121 | */ | ||
122 | |||
123 | extern int drm_sman_set_range(struct drm_sman * sman, unsigned int manager, | ||
124 | unsigned long start, unsigned long size); | ||
125 | |||
126 | /* | ||
127 | * Initialize a customized allocator for one of the managers. | ||
128 | * (See the SiS module). The object pointed to by "allocator" is copied, | ||
129 | * so it can be destroyed after this call. | ||
130 | */ | ||
131 | |||
132 | extern int drm_sman_set_manager(struct drm_sman * sman, unsigned int mananger, | ||
133 | struct drm_sman_mm * allocator); | ||
134 | |||
135 | /* | ||
136 | * Allocate a memory block. Aligment is not implemented yet. | ||
137 | */ | ||
138 | |||
139 | extern struct drm_memblock_item *drm_sman_alloc(struct drm_sman * sman, | ||
140 | unsigned int manager, | ||
141 | unsigned long size, | ||
142 | unsigned alignment, | ||
143 | unsigned long owner); | ||
144 | /* | ||
145 | * Free a memory block identified by its user hash key. | ||
146 | */ | ||
147 | |||
148 | extern int drm_sman_free_key(struct drm_sman * sman, unsigned int key); | ||
149 | |||
150 | /* | ||
151 | * returns 1 iff there are no stale memory blocks associated with this owner. | ||
152 | * Typically called to determine if we need to idle the hardware and call | ||
153 | * drm_sman_owner_cleanup. If there are no stale memory blocks, it removes all | ||
154 | * resources associated with owner. | ||
155 | */ | ||
156 | |||
157 | extern int drm_sman_owner_clean(struct drm_sman * sman, unsigned long owner); | ||
158 | |||
159 | /* | ||
160 | * Frees all stale memory blocks associated with this owner. Note that this | ||
161 | * requires that the hardware is finished with all blocks, so the graphics engine | ||
162 | * should be idled before this call is made. This function also frees | ||
163 | * any resources associated with "owner" and should be called when owner | ||
164 | * is not going to be referenced anymore. | ||
165 | */ | ||
166 | |||
167 | extern void drm_sman_owner_cleanup(struct drm_sman * sman, unsigned long owner); | ||
168 | |||
169 | /* | ||
170 | * Frees all stale memory blocks associated with the memory manager. | ||
171 | * See idling above. | ||
172 | */ | ||
173 | |||
174 | extern void drm_sman_cleanup(struct drm_sman * sman); | ||
175 | |||
176 | #endif | ||
diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h new file mode 100644 index 000000000000..7a10bb6f2c0f --- /dev/null +++ b/include/drm/i810_drm.h | |||
@@ -0,0 +1,281 @@ | |||
1 | #ifndef _I810_DRM_H_ | ||
2 | #define _I810_DRM_H_ | ||
3 | |||
4 | /* WARNING: These defines must be the same as what the Xserver uses. | ||
5 | * if you change them, you must change the defines in the Xserver. | ||
6 | */ | ||
7 | |||
8 | #ifndef _I810_DEFINES_ | ||
9 | #define _I810_DEFINES_ | ||
10 | |||
11 | #define I810_DMA_BUF_ORDER 12 | ||
12 | #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) | ||
13 | #define I810_DMA_BUF_NR 256 | ||
14 | #define I810_NR_SAREA_CLIPRECTS 8 | ||
15 | |||
16 | /* Each region is a minimum of 64k, and there are at most 64 of them. | ||
17 | */ | ||
18 | #define I810_NR_TEX_REGIONS 64 | ||
19 | #define I810_LOG_MIN_TEX_REGION_SIZE 16 | ||
20 | #endif | ||
21 | |||
22 | #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ | ||
23 | #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ | ||
24 | #define I810_UPLOAD_CTX 0x4 | ||
25 | #define I810_UPLOAD_BUFFERS 0x8 | ||
26 | #define I810_UPLOAD_TEX0 0x10 | ||
27 | #define I810_UPLOAD_TEX1 0x20 | ||
28 | #define I810_UPLOAD_CLIPRECTS 0x40 | ||
29 | |||
30 | /* Indices into buf.Setup where various bits of state are mirrored per | ||
31 | * context and per buffer. These can be fired at the card as a unit, | ||
32 | * or in a piecewise fashion as required. | ||
33 | */ | ||
34 | |||
35 | /* Destbuffer state | ||
36 | * - backbuffer linear offset and pitch -- invarient in the current dri | ||
37 | * - zbuffer linear offset and pitch -- also invarient | ||
38 | * - drawing origin in back and depth buffers. | ||
39 | * | ||
40 | * Keep the depth/back buffer state here to accommodate private buffers | ||
41 | * in the future. | ||
42 | */ | ||
43 | #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ | ||
44 | #define I810_DESTREG_DI1 1 | ||
45 | #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ | ||
46 | #define I810_DESTREG_DV1 3 | ||
47 | #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ | ||
48 | #define I810_DESTREG_DR1 5 | ||
49 | #define I810_DESTREG_DR2 6 | ||
50 | #define I810_DESTREG_DR3 7 | ||
51 | #define I810_DESTREG_DR4 8 | ||
52 | #define I810_DEST_SETUP_SIZE 10 | ||
53 | |||
54 | /* Context state | ||
55 | */ | ||
56 | #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ | ||
57 | #define I810_CTXREG_CF1 1 | ||
58 | #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ | ||
59 | #define I810_CTXREG_ST1 3 | ||
60 | #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ | ||
61 | #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ | ||
62 | #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ | ||
63 | #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ | ||
64 | #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ | ||
65 | #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ | ||
66 | #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ | ||
67 | #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ | ||
68 | #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ | ||
69 | #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ | ||
70 | #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ | ||
71 | #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ | ||
72 | #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ | ||
73 | #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ | ||
74 | #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ | ||
75 | #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ | ||
76 | #define I810_CTX_SETUP_SIZE 20 | ||
77 | |||
78 | /* Texture state (per tex unit) | ||
79 | */ | ||
80 | #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ | ||
81 | #define I810_TEXREG_MI1 1 | ||
82 | #define I810_TEXREG_MI2 2 | ||
83 | #define I810_TEXREG_MI3 3 | ||
84 | #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ | ||
85 | #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ | ||
86 | #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ | ||
87 | #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ | ||
88 | #define I810_TEX_SETUP_SIZE 8 | ||
89 | |||
90 | /* Flags for clear ioctl | ||
91 | */ | ||
92 | #define I810_FRONT 0x1 | ||
93 | #define I810_BACK 0x2 | ||
94 | #define I810_DEPTH 0x4 | ||
95 | |||
96 | typedef enum _drm_i810_init_func { | ||
97 | I810_INIT_DMA = 0x01, | ||
98 | I810_CLEANUP_DMA = 0x02, | ||
99 | I810_INIT_DMA_1_4 = 0x03 | ||
100 | } drm_i810_init_func_t; | ||
101 | |||
102 | /* This is the init structure after v1.2 */ | ||
103 | typedef struct _drm_i810_init { | ||
104 | drm_i810_init_func_t func; | ||
105 | unsigned int mmio_offset; | ||
106 | unsigned int buffers_offset; | ||
107 | int sarea_priv_offset; | ||
108 | unsigned int ring_start; | ||
109 | unsigned int ring_end; | ||
110 | unsigned int ring_size; | ||
111 | unsigned int front_offset; | ||
112 | unsigned int back_offset; | ||
113 | unsigned int depth_offset; | ||
114 | unsigned int overlay_offset; | ||
115 | unsigned int overlay_physical; | ||
116 | unsigned int w; | ||
117 | unsigned int h; | ||
118 | unsigned int pitch; | ||
119 | unsigned int pitch_bits; | ||
120 | } drm_i810_init_t; | ||
121 | |||
122 | /* This is the init structure prior to v1.2 */ | ||
123 | typedef struct _drm_i810_pre12_init { | ||
124 | drm_i810_init_func_t func; | ||
125 | unsigned int mmio_offset; | ||
126 | unsigned int buffers_offset; | ||
127 | int sarea_priv_offset; | ||
128 | unsigned int ring_start; | ||
129 | unsigned int ring_end; | ||
130 | unsigned int ring_size; | ||
131 | unsigned int front_offset; | ||
132 | unsigned int back_offset; | ||
133 | unsigned int depth_offset; | ||
134 | unsigned int w; | ||
135 | unsigned int h; | ||
136 | unsigned int pitch; | ||
137 | unsigned int pitch_bits; | ||
138 | } drm_i810_pre12_init_t; | ||
139 | |||
140 | /* Warning: If you change the SAREA structure you must change the Xserver | ||
141 | * structure as well */ | ||
142 | |||
143 | typedef struct _drm_i810_tex_region { | ||
144 | unsigned char next, prev; /* indices to form a circular LRU */ | ||
145 | unsigned char in_use; /* owned by a client, or free? */ | ||
146 | int age; /* tracked by clients to update local LRU's */ | ||
147 | } drm_i810_tex_region_t; | ||
148 | |||
149 | typedef struct _drm_i810_sarea { | ||
150 | unsigned int ContextState[I810_CTX_SETUP_SIZE]; | ||
151 | unsigned int BufferState[I810_DEST_SETUP_SIZE]; | ||
152 | unsigned int TexState[2][I810_TEX_SETUP_SIZE]; | ||
153 | unsigned int dirty; | ||
154 | |||
155 | unsigned int nbox; | ||
156 | struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; | ||
157 | |||
158 | /* Maintain an LRU of contiguous regions of texture space. If | ||
159 | * you think you own a region of texture memory, and it has an | ||
160 | * age different to the one you set, then you are mistaken and | ||
161 | * it has been stolen by another client. If global texAge | ||
162 | * hasn't changed, there is no need to walk the list. | ||
163 | * | ||
164 | * These regions can be used as a proxy for the fine-grained | ||
165 | * texture information of other clients - by maintaining them | ||
166 | * in the same lru which is used to age their own textures, | ||
167 | * clients have an approximate lru for the whole of global | ||
168 | * texture space, and can make informed decisions as to which | ||
169 | * areas to kick out. There is no need to choose whether to | ||
170 | * kick out your own texture or someone else's - simply eject | ||
171 | * them all in LRU order. | ||
172 | */ | ||
173 | |||
174 | drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; | ||
175 | /* Last elt is sentinal */ | ||
176 | int texAge; /* last time texture was uploaded */ | ||
177 | int last_enqueue; /* last time a buffer was enqueued */ | ||
178 | int last_dispatch; /* age of the most recently dispatched buffer */ | ||
179 | int last_quiescent; /* */ | ||
180 | int ctxOwner; /* last context to upload state */ | ||
181 | |||
182 | int vertex_prim; | ||
183 | |||
184 | int pf_enabled; /* is pageflipping allowed? */ | ||
185 | int pf_active; | ||
186 | int pf_current_page; /* which buffer is being displayed? */ | ||
187 | } drm_i810_sarea_t; | ||
188 | |||
189 | /* WARNING: If you change any of these defines, make sure to change the | ||
190 | * defines in the Xserver file (xf86drmMga.h) | ||
191 | */ | ||
192 | |||
193 | /* i810 specific ioctls | ||
194 | * The device specific ioctl range is 0x40 to 0x79. | ||
195 | */ | ||
196 | #define DRM_I810_INIT 0x00 | ||
197 | #define DRM_I810_VERTEX 0x01 | ||
198 | #define DRM_I810_CLEAR 0x02 | ||
199 | #define DRM_I810_FLUSH 0x03 | ||
200 | #define DRM_I810_GETAGE 0x04 | ||
201 | #define DRM_I810_GETBUF 0x05 | ||
202 | #define DRM_I810_SWAP 0x06 | ||
203 | #define DRM_I810_COPY 0x07 | ||
204 | #define DRM_I810_DOCOPY 0x08 | ||
205 | #define DRM_I810_OV0INFO 0x09 | ||
206 | #define DRM_I810_FSTATUS 0x0a | ||
207 | #define DRM_I810_OV0FLIP 0x0b | ||
208 | #define DRM_I810_MC 0x0c | ||
209 | #define DRM_I810_RSTATUS 0x0d | ||
210 | #define DRM_I810_FLIP 0x0e | ||
211 | |||
212 | #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) | ||
213 | #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) | ||
214 | #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) | ||
215 | #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) | ||
216 | #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) | ||
217 | #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) | ||
218 | #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) | ||
219 | #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) | ||
220 | #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) | ||
221 | #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) | ||
222 | #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) | ||
223 | #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) | ||
224 | #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) | ||
225 | #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) | ||
226 | #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) | ||
227 | |||
228 | typedef struct _drm_i810_clear { | ||
229 | int clear_color; | ||
230 | int clear_depth; | ||
231 | int flags; | ||
232 | } drm_i810_clear_t; | ||
233 | |||
234 | /* These may be placeholders if we have more cliprects than | ||
235 | * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to | ||
236 | * false, indicating that the buffer will be dispatched again with a | ||
237 | * new set of cliprects. | ||
238 | */ | ||
239 | typedef struct _drm_i810_vertex { | ||
240 | int idx; /* buffer index */ | ||
241 | int used; /* nr bytes in use */ | ||
242 | int discard; /* client is finished with the buffer? */ | ||
243 | } drm_i810_vertex_t; | ||
244 | |||
245 | typedef struct _drm_i810_copy_t { | ||
246 | int idx; /* buffer index */ | ||
247 | int used; /* nr bytes in use */ | ||
248 | void *address; /* Address to copy from */ | ||
249 | } drm_i810_copy_t; | ||
250 | |||
251 | #define PR_TRIANGLES (0x0<<18) | ||
252 | #define PR_TRISTRIP_0 (0x1<<18) | ||
253 | #define PR_TRISTRIP_1 (0x2<<18) | ||
254 | #define PR_TRIFAN (0x3<<18) | ||
255 | #define PR_POLYGON (0x4<<18) | ||
256 | #define PR_LINES (0x5<<18) | ||
257 | #define PR_LINESTRIP (0x6<<18) | ||
258 | #define PR_RECTS (0x7<<18) | ||
259 | #define PR_MASK (0x7<<18) | ||
260 | |||
261 | typedef struct drm_i810_dma { | ||
262 | void *virtual; | ||
263 | int request_idx; | ||
264 | int request_size; | ||
265 | int granted; | ||
266 | } drm_i810_dma_t; | ||
267 | |||
268 | typedef struct _drm_i810_overlay_t { | ||
269 | unsigned int offset; /* Address of the Overlay Regs */ | ||
270 | unsigned int physical; | ||
271 | } drm_i810_overlay_t; | ||
272 | |||
273 | typedef struct _drm_i810_mc { | ||
274 | int idx; /* buffer index */ | ||
275 | int used; /* nr bytes in use */ | ||
276 | int num_blocks; /* number of GFXBlocks */ | ||
277 | int *length; /* List of lengths for GFXBlocks (FUTURE) */ | ||
278 | unsigned int last_render; /* Last Render Request */ | ||
279 | } drm_i810_mc_t; | ||
280 | |||
281 | #endif /* _I810_DRM_H_ */ | ||
diff --git a/include/drm/i830_drm.h b/include/drm/i830_drm.h new file mode 100644 index 000000000000..4b00d2dd4f68 --- /dev/null +++ b/include/drm/i830_drm.h | |||
@@ -0,0 +1,342 @@ | |||
1 | #ifndef _I830_DRM_H_ | ||
2 | #define _I830_DRM_H_ | ||
3 | |||
4 | /* WARNING: These defines must be the same as what the Xserver uses. | ||
5 | * if you change them, you must change the defines in the Xserver. | ||
6 | * | ||
7 | * KW: Actually, you can't ever change them because doing so would | ||
8 | * break backwards compatibility. | ||
9 | */ | ||
10 | |||
11 | #ifndef _I830_DEFINES_ | ||
12 | #define _I830_DEFINES_ | ||
13 | |||
14 | #define I830_DMA_BUF_ORDER 12 | ||
15 | #define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER) | ||
16 | #define I830_DMA_BUF_NR 256 | ||
17 | #define I830_NR_SAREA_CLIPRECTS 8 | ||
18 | |||
19 | /* Each region is a minimum of 64k, and there are at most 64 of them. | ||
20 | */ | ||
21 | #define I830_NR_TEX_REGIONS 64 | ||
22 | #define I830_LOG_MIN_TEX_REGION_SIZE 16 | ||
23 | |||
24 | /* KW: These aren't correct but someone set them to two and then | ||
25 | * released the module. Now we can't change them as doing so would | ||
26 | * break backwards compatibility. | ||
27 | */ | ||
28 | #define I830_TEXTURE_COUNT 2 | ||
29 | #define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT | ||
30 | |||
31 | #define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */ | ||
32 | |||
33 | #define I830_UPLOAD_CTX 0x1 | ||
34 | #define I830_UPLOAD_BUFFERS 0x2 | ||
35 | #define I830_UPLOAD_CLIPRECTS 0x4 | ||
36 | #define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ | ||
37 | #define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ | ||
38 | #define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ | ||
39 | #define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ | ||
40 | #define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ | ||
41 | #define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ | ||
42 | #define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ | ||
43 | #define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ | ||
44 | #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) | ||
45 | #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) | ||
46 | #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 | ||
47 | #define I830_UPLOAD_TEX0 0x10000 | ||
48 | #define I830_UPLOAD_TEX1 0x20000 | ||
49 | #define I830_UPLOAD_TEX2 0x40000 | ||
50 | #define I830_UPLOAD_TEX3 0x80000 | ||
51 | #define I830_UPLOAD_TEX_N(n) (0x10000 << (n)) | ||
52 | #define I830_UPLOAD_TEX_MASK 0xf0000 | ||
53 | #define I830_UPLOAD_TEXBLEND0 0x100000 | ||
54 | #define I830_UPLOAD_TEXBLEND1 0x200000 | ||
55 | #define I830_UPLOAD_TEXBLEND2 0x400000 | ||
56 | #define I830_UPLOAD_TEXBLEND3 0x800000 | ||
57 | #define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n)) | ||
58 | #define I830_UPLOAD_TEXBLEND_MASK 0xf00000 | ||
59 | #define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n)) | ||
60 | #define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000 | ||
61 | #define I830_UPLOAD_STIPPLE 0x8000000 | ||
62 | |||
63 | /* Indices into buf.Setup where various bits of state are mirrored per | ||
64 | * context and per buffer. These can be fired at the card as a unit, | ||
65 | * or in a piecewise fashion as required. | ||
66 | */ | ||
67 | |||
68 | /* Destbuffer state | ||
69 | * - backbuffer linear offset and pitch -- invarient in the current dri | ||
70 | * - zbuffer linear offset and pitch -- also invarient | ||
71 | * - drawing origin in back and depth buffers. | ||
72 | * | ||
73 | * Keep the depth/back buffer state here to accommodate private buffers | ||
74 | * in the future. | ||
75 | */ | ||
76 | |||
77 | #define I830_DESTREG_CBUFADDR 0 | ||
78 | #define I830_DESTREG_DBUFADDR 1 | ||
79 | #define I830_DESTREG_DV0 2 | ||
80 | #define I830_DESTREG_DV1 3 | ||
81 | #define I830_DESTREG_SENABLE 4 | ||
82 | #define I830_DESTREG_SR0 5 | ||
83 | #define I830_DESTREG_SR1 6 | ||
84 | #define I830_DESTREG_SR2 7 | ||
85 | #define I830_DESTREG_DR0 8 | ||
86 | #define I830_DESTREG_DR1 9 | ||
87 | #define I830_DESTREG_DR2 10 | ||
88 | #define I830_DESTREG_DR3 11 | ||
89 | #define I830_DESTREG_DR4 12 | ||
90 | #define I830_DEST_SETUP_SIZE 13 | ||
91 | |||
92 | /* Context state | ||
93 | */ | ||
94 | #define I830_CTXREG_STATE1 0 | ||
95 | #define I830_CTXREG_STATE2 1 | ||
96 | #define I830_CTXREG_STATE3 2 | ||
97 | #define I830_CTXREG_STATE4 3 | ||
98 | #define I830_CTXREG_STATE5 4 | ||
99 | #define I830_CTXREG_IALPHAB 5 | ||
100 | #define I830_CTXREG_STENCILTST 6 | ||
101 | #define I830_CTXREG_ENABLES_1 7 | ||
102 | #define I830_CTXREG_ENABLES_2 8 | ||
103 | #define I830_CTXREG_AA 9 | ||
104 | #define I830_CTXREG_FOGCOLOR 10 | ||
105 | #define I830_CTXREG_BLENDCOLR0 11 | ||
106 | #define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ | ||
107 | #define I830_CTXREG_VF 13 | ||
108 | #define I830_CTXREG_VF2 14 | ||
109 | #define I830_CTXREG_MCSB0 15 | ||
110 | #define I830_CTXREG_MCSB1 16 | ||
111 | #define I830_CTX_SETUP_SIZE 17 | ||
112 | |||
113 | /* 1.3: Stipple state | ||
114 | */ | ||
115 | #define I830_STPREG_ST0 0 | ||
116 | #define I830_STPREG_ST1 1 | ||
117 | #define I830_STP_SETUP_SIZE 2 | ||
118 | |||
119 | /* Texture state (per tex unit) | ||
120 | */ | ||
121 | |||
122 | #define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */ | ||
123 | #define I830_TEXREG_MI1 1 | ||
124 | #define I830_TEXREG_MI2 2 | ||
125 | #define I830_TEXREG_MI3 3 | ||
126 | #define I830_TEXREG_MI4 4 | ||
127 | #define I830_TEXREG_MI5 5 | ||
128 | #define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */ | ||
129 | #define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */ | ||
130 | #define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */ | ||
131 | #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ | ||
132 | #define I830_TEX_SETUP_SIZE 10 | ||
133 | |||
134 | #define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ | ||
135 | #define I830_TEXREG_TM0S0 1 | ||
136 | #define I830_TEXREG_TM0S1 2 | ||
137 | #define I830_TEXREG_TM0S2 3 | ||
138 | #define I830_TEXREG_TM0S3 4 | ||
139 | #define I830_TEXREG_TM0S4 5 | ||
140 | #define I830_TEXREG_NOP0 6 /* noop */ | ||
141 | #define I830_TEXREG_NOP1 7 /* noop */ | ||
142 | #define I830_TEXREG_NOP2 8 /* noop */ | ||
143 | #define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ | ||
144 | #define __I830_TEX_SETUP_SIZE 10 | ||
145 | |||
146 | #define I830_FRONT 0x1 | ||
147 | #define I830_BACK 0x2 | ||
148 | #define I830_DEPTH 0x4 | ||
149 | |||
150 | #endif /* _I830_DEFINES_ */ | ||
151 | |||
152 | typedef struct _drm_i830_init { | ||
153 | enum { | ||
154 | I830_INIT_DMA = 0x01, | ||
155 | I830_CLEANUP_DMA = 0x02 | ||
156 | } func; | ||
157 | unsigned int mmio_offset; | ||
158 | unsigned int buffers_offset; | ||
159 | int sarea_priv_offset; | ||
160 | unsigned int ring_start; | ||
161 | unsigned int ring_end; | ||
162 | unsigned int ring_size; | ||
163 | unsigned int front_offset; | ||
164 | unsigned int back_offset; | ||
165 | unsigned int depth_offset; | ||
166 | unsigned int w; | ||
167 | unsigned int h; | ||
168 | unsigned int pitch; | ||
169 | unsigned int pitch_bits; | ||
170 | unsigned int back_pitch; | ||
171 | unsigned int depth_pitch; | ||
172 | unsigned int cpp; | ||
173 | } drm_i830_init_t; | ||
174 | |||
175 | /* Warning: If you change the SAREA structure you must change the Xserver | ||
176 | * structure as well */ | ||
177 | |||
178 | typedef struct _drm_i830_tex_region { | ||
179 | unsigned char next, prev; /* indices to form a circular LRU */ | ||
180 | unsigned char in_use; /* owned by a client, or free? */ | ||
181 | int age; /* tracked by clients to update local LRU's */ | ||
182 | } drm_i830_tex_region_t; | ||
183 | |||
184 | typedef struct _drm_i830_sarea { | ||
185 | unsigned int ContextState[I830_CTX_SETUP_SIZE]; | ||
186 | unsigned int BufferState[I830_DEST_SETUP_SIZE]; | ||
187 | unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; | ||
188 | unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; | ||
189 | unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; | ||
190 | unsigned int Palette[2][256]; | ||
191 | unsigned int dirty; | ||
192 | |||
193 | unsigned int nbox; | ||
194 | struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS]; | ||
195 | |||
196 | /* Maintain an LRU of contiguous regions of texture space. If | ||
197 | * you think you own a region of texture memory, and it has an | ||
198 | * age different to the one you set, then you are mistaken and | ||
199 | * it has been stolen by another client. If global texAge | ||
200 | * hasn't changed, there is no need to walk the list. | ||
201 | * | ||
202 | * These regions can be used as a proxy for the fine-grained | ||
203 | * texture information of other clients - by maintaining them | ||
204 | * in the same lru which is used to age their own textures, | ||
205 | * clients have an approximate lru for the whole of global | ||
206 | * texture space, and can make informed decisions as to which | ||
207 | * areas to kick out. There is no need to choose whether to | ||
208 | * kick out your own texture or someone else's - simply eject | ||
209 | * them all in LRU order. | ||
210 | */ | ||
211 | |||
212 | drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1]; | ||
213 | /* Last elt is sentinal */ | ||
214 | int texAge; /* last time texture was uploaded */ | ||
215 | int last_enqueue; /* last time a buffer was enqueued */ | ||
216 | int last_dispatch; /* age of the most recently dispatched buffer */ | ||
217 | int last_quiescent; /* */ | ||
218 | int ctxOwner; /* last context to upload state */ | ||
219 | |||
220 | int vertex_prim; | ||
221 | |||
222 | int pf_enabled; /* is pageflipping allowed? */ | ||
223 | int pf_active; | ||
224 | int pf_current_page; /* which buffer is being displayed? */ | ||
225 | |||
226 | int perf_boxes; /* performance boxes to be displayed */ | ||
227 | |||
228 | /* Here's the state for texunits 2,3: | ||
229 | */ | ||
230 | unsigned int TexState2[I830_TEX_SETUP_SIZE]; | ||
231 | unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; | ||
232 | unsigned int TexBlendStateWordsUsed2; | ||
233 | |||
234 | unsigned int TexState3[I830_TEX_SETUP_SIZE]; | ||
235 | unsigned int TexBlendState3[I830_TEXBLEND_SIZE]; | ||
236 | unsigned int TexBlendStateWordsUsed3; | ||
237 | |||
238 | unsigned int StippleState[I830_STP_SETUP_SIZE]; | ||
239 | } drm_i830_sarea_t; | ||
240 | |||
241 | /* Flags for perf_boxes | ||
242 | */ | ||
243 | #define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ | ||
244 | #define I830_BOX_FLIP 0x2 /* populated by kernel */ | ||
245 | #define I830_BOX_WAIT 0x4 /* populated by kernel & client */ | ||
246 | #define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ | ||
247 | #define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ | ||
248 | |||
249 | /* I830 specific ioctls | ||
250 | * The device specific ioctl range is 0x40 to 0x79. | ||
251 | */ | ||
252 | #define DRM_I830_INIT 0x00 | ||
253 | #define DRM_I830_VERTEX 0x01 | ||
254 | #define DRM_I830_CLEAR 0x02 | ||
255 | #define DRM_I830_FLUSH 0x03 | ||
256 | #define DRM_I830_GETAGE 0x04 | ||
257 | #define DRM_I830_GETBUF 0x05 | ||
258 | #define DRM_I830_SWAP 0x06 | ||
259 | #define DRM_I830_COPY 0x07 | ||
260 | #define DRM_I830_DOCOPY 0x08 | ||
261 | #define DRM_I830_FLIP 0x09 | ||
262 | #define DRM_I830_IRQ_EMIT 0x0a | ||
263 | #define DRM_I830_IRQ_WAIT 0x0b | ||
264 | #define DRM_I830_GETPARAM 0x0c | ||
265 | #define DRM_I830_SETPARAM 0x0d | ||
266 | |||
267 | #define DRM_IOCTL_I830_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t) | ||
268 | #define DRM_IOCTL_I830_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t) | ||
269 | #define DRM_IOCTL_I830_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t) | ||
270 | #define DRM_IOCTL_I830_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH) | ||
271 | #define DRM_IOCTL_I830_GETAGE DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE) | ||
272 | #define DRM_IOCTL_I830_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t) | ||
273 | #define DRM_IOCTL_I830_SWAP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP) | ||
274 | #define DRM_IOCTL_I830_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t) | ||
275 | #define DRM_IOCTL_I830_DOCOPY DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY) | ||
276 | #define DRM_IOCTL_I830_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP) | ||
277 | #define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t) | ||
278 | #define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t) | ||
279 | #define DRM_IOCTL_I830_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t) | ||
280 | #define DRM_IOCTL_I830_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t) | ||
281 | |||
282 | typedef struct _drm_i830_clear { | ||
283 | int clear_color; | ||
284 | int clear_depth; | ||
285 | int flags; | ||
286 | unsigned int clear_colormask; | ||
287 | unsigned int clear_depthmask; | ||
288 | } drm_i830_clear_t; | ||
289 | |||
290 | /* These may be placeholders if we have more cliprects than | ||
291 | * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to | ||
292 | * false, indicating that the buffer will be dispatched again with a | ||
293 | * new set of cliprects. | ||
294 | */ | ||
295 | typedef struct _drm_i830_vertex { | ||
296 | int idx; /* buffer index */ | ||
297 | int used; /* nr bytes in use */ | ||
298 | int discard; /* client is finished with the buffer? */ | ||
299 | } drm_i830_vertex_t; | ||
300 | |||
301 | typedef struct _drm_i830_copy_t { | ||
302 | int idx; /* buffer index */ | ||
303 | int used; /* nr bytes in use */ | ||
304 | void __user *address; /* Address to copy from */ | ||
305 | } drm_i830_copy_t; | ||
306 | |||
307 | typedef struct drm_i830_dma { | ||
308 | void __user *virtual; | ||
309 | int request_idx; | ||
310 | int request_size; | ||
311 | int granted; | ||
312 | } drm_i830_dma_t; | ||
313 | |||
314 | /* 1.3: Userspace can request & wait on irq's: | ||
315 | */ | ||
316 | typedef struct drm_i830_irq_emit { | ||
317 | int __user *irq_seq; | ||
318 | } drm_i830_irq_emit_t; | ||
319 | |||
320 | typedef struct drm_i830_irq_wait { | ||
321 | int irq_seq; | ||
322 | } drm_i830_irq_wait_t; | ||
323 | |||
324 | /* 1.3: New ioctl to query kernel params: | ||
325 | */ | ||
326 | #define I830_PARAM_IRQ_ACTIVE 1 | ||
327 | |||
328 | typedef struct drm_i830_getparam { | ||
329 | int param; | ||
330 | int __user *value; | ||
331 | } drm_i830_getparam_t; | ||
332 | |||
333 | /* 1.3: New ioctl to set kernel params: | ||
334 | */ | ||
335 | #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 | ||
336 | |||
337 | typedef struct drm_i830_setparam { | ||
338 | int param; | ||
339 | int value; | ||
340 | } drm_i830_setparam_t; | ||
341 | |||
342 | #endif /* _I830_DRM_H_ */ | ||
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h new file mode 100644 index 000000000000..05c66cf03a9e --- /dev/null +++ b/include/drm/i915_drm.h | |||
@@ -0,0 +1,270 @@ | |||
1 | /* | ||
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the | ||
7 | * "Software"), to deal in the Software without restriction, including | ||
8 | * without limitation the rights to use, copy, modify, merge, publish, | ||
9 | * distribute, sub license, and/or sell copies of the Software, and to | ||
10 | * permit persons to whom the Software is furnished to do so, subject to | ||
11 | * the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice (including the | ||
14 | * next paragraph) shall be included in all copies or substantial portions | ||
15 | * of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | ||
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | ||
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | ||
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | ||
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | ||
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
24 | * | ||
25 | */ | ||
26 | |||
27 | #ifndef _I915_DRM_H_ | ||
28 | #define _I915_DRM_H_ | ||
29 | |||
30 | /* Please note that modifications to all structs defined here are | ||
31 | * subject to backwards-compatibility constraints. | ||
32 | */ | ||
33 | |||
34 | #include "drm.h" | ||
35 | |||
36 | /* Each region is a minimum of 16k, and there are at most 255 of them. | ||
37 | */ | ||
38 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | ||
39 | * of chars for next/prev indices */ | ||
40 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | ||
41 | |||
42 | typedef struct _drm_i915_init { | ||
43 | enum { | ||
44 | I915_INIT_DMA = 0x01, | ||
45 | I915_CLEANUP_DMA = 0x02, | ||
46 | I915_RESUME_DMA = 0x03 | ||
47 | } func; | ||
48 | unsigned int mmio_offset; | ||
49 | int sarea_priv_offset; | ||
50 | unsigned int ring_start; | ||
51 | unsigned int ring_end; | ||
52 | unsigned int ring_size; | ||
53 | unsigned int front_offset; | ||
54 | unsigned int back_offset; | ||
55 | unsigned int depth_offset; | ||
56 | unsigned int w; | ||
57 | unsigned int h; | ||
58 | unsigned int pitch; | ||
59 | unsigned int pitch_bits; | ||
60 | unsigned int back_pitch; | ||
61 | unsigned int depth_pitch; | ||
62 | unsigned int cpp; | ||
63 | unsigned int chipset; | ||
64 | } drm_i915_init_t; | ||
65 | |||
66 | typedef struct _drm_i915_sarea { | ||
67 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; | ||
68 | int last_upload; /* last time texture was uploaded */ | ||
69 | int last_enqueue; /* last time a buffer was enqueued */ | ||
70 | int last_dispatch; /* age of the most recently dispatched buffer */ | ||
71 | int ctxOwner; /* last context to upload state */ | ||
72 | int texAge; | ||
73 | int pf_enabled; /* is pageflipping allowed? */ | ||
74 | int pf_active; | ||
75 | int pf_current_page; /* which buffer is being displayed? */ | ||
76 | int perf_boxes; /* performance boxes to be displayed */ | ||
77 | int width, height; /* screen size in pixels */ | ||
78 | |||
79 | drm_handle_t front_handle; | ||
80 | int front_offset; | ||
81 | int front_size; | ||
82 | |||
83 | drm_handle_t back_handle; | ||
84 | int back_offset; | ||
85 | int back_size; | ||
86 | |||
87 | drm_handle_t depth_handle; | ||
88 | int depth_offset; | ||
89 | int depth_size; | ||
90 | |||
91 | drm_handle_t tex_handle; | ||
92 | int tex_offset; | ||
93 | int tex_size; | ||
94 | int log_tex_granularity; | ||
95 | int pitch; | ||
96 | int rotation; /* 0, 90, 180 or 270 */ | ||
97 | int rotated_offset; | ||
98 | int rotated_size; | ||
99 | int rotated_pitch; | ||
100 | int virtualX, virtualY; | ||
101 | |||
102 | unsigned int front_tiled; | ||
103 | unsigned int back_tiled; | ||
104 | unsigned int depth_tiled; | ||
105 | unsigned int rotated_tiled; | ||
106 | unsigned int rotated2_tiled; | ||
107 | |||
108 | int pipeA_x; | ||
109 | int pipeA_y; | ||
110 | int pipeA_w; | ||
111 | int pipeA_h; | ||
112 | int pipeB_x; | ||
113 | int pipeB_y; | ||
114 | int pipeB_w; | ||
115 | int pipeB_h; | ||
116 | } drm_i915_sarea_t; | ||
117 | |||
118 | /* Flags for perf_boxes | ||
119 | */ | ||
120 | #define I915_BOX_RING_EMPTY 0x1 | ||
121 | #define I915_BOX_FLIP 0x2 | ||
122 | #define I915_BOX_WAIT 0x4 | ||
123 | #define I915_BOX_TEXTURE_LOAD 0x8 | ||
124 | #define I915_BOX_LOST_CONTEXT 0x10 | ||
125 | |||
126 | /* I915 specific ioctls | ||
127 | * The device specific ioctl range is 0x40 to 0x79. | ||
128 | */ | ||
129 | #define DRM_I915_INIT 0x00 | ||
130 | #define DRM_I915_FLUSH 0x01 | ||
131 | #define DRM_I915_FLIP 0x02 | ||
132 | #define DRM_I915_BATCHBUFFER 0x03 | ||
133 | #define DRM_I915_IRQ_EMIT 0x04 | ||
134 | #define DRM_I915_IRQ_WAIT 0x05 | ||
135 | #define DRM_I915_GETPARAM 0x06 | ||
136 | #define DRM_I915_SETPARAM 0x07 | ||
137 | #define DRM_I915_ALLOC 0x08 | ||
138 | #define DRM_I915_FREE 0x09 | ||
139 | #define DRM_I915_INIT_HEAP 0x0a | ||
140 | #define DRM_I915_CMDBUFFER 0x0b | ||
141 | #define DRM_I915_DESTROY_HEAP 0x0c | ||
142 | #define DRM_I915_SET_VBLANK_PIPE 0x0d | ||
143 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | ||
144 | #define DRM_I915_VBLANK_SWAP 0x0f | ||
145 | #define DRM_I915_HWS_ADDR 0x11 | ||
146 | |||
147 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | ||
148 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | ||
149 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) | ||
150 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) | ||
151 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | ||
152 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | ||
153 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | ||
154 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | ||
155 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | ||
156 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | ||
157 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | ||
158 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | ||
159 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) | ||
160 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | ||
161 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | ||
162 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) | ||
163 | |||
164 | /* Allow drivers to submit batchbuffers directly to hardware, relying | ||
165 | * on the security mechanisms provided by hardware. | ||
166 | */ | ||
167 | typedef struct _drm_i915_batchbuffer { | ||
168 | int start; /* agp offset */ | ||
169 | int used; /* nr bytes in use */ | ||
170 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | ||
171 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | ||
172 | int num_cliprects; /* mulitpass with multiple cliprects? */ | ||
173 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | ||
174 | } drm_i915_batchbuffer_t; | ||
175 | |||
176 | /* As above, but pass a pointer to userspace buffer which can be | ||
177 | * validated by the kernel prior to sending to hardware. | ||
178 | */ | ||
179 | typedef struct _drm_i915_cmdbuffer { | ||
180 | char __user *buf; /* pointer to userspace command buffer */ | ||
181 | int sz; /* nr bytes in buf */ | ||
182 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | ||
183 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | ||
184 | int num_cliprects; /* mulitpass with multiple cliprects? */ | ||
185 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | ||
186 | } drm_i915_cmdbuffer_t; | ||
187 | |||
188 | /* Userspace can request & wait on irq's: | ||
189 | */ | ||
190 | typedef struct drm_i915_irq_emit { | ||
191 | int __user *irq_seq; | ||
192 | } drm_i915_irq_emit_t; | ||
193 | |||
194 | typedef struct drm_i915_irq_wait { | ||
195 | int irq_seq; | ||
196 | } drm_i915_irq_wait_t; | ||
197 | |||
198 | /* Ioctl to query kernel params: | ||
199 | */ | ||
200 | #define I915_PARAM_IRQ_ACTIVE 1 | ||
201 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | ||
202 | #define I915_PARAM_LAST_DISPATCH 3 | ||
203 | |||
204 | typedef struct drm_i915_getparam { | ||
205 | int param; | ||
206 | int __user *value; | ||
207 | } drm_i915_getparam_t; | ||
208 | |||
209 | /* Ioctl to set kernel params: | ||
210 | */ | ||
211 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | ||
212 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | ||
213 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | ||
214 | |||
215 | typedef struct drm_i915_setparam { | ||
216 | int param; | ||
217 | int value; | ||
218 | } drm_i915_setparam_t; | ||
219 | |||
220 | /* A memory manager for regions of shared memory: | ||
221 | */ | ||
222 | #define I915_MEM_REGION_AGP 1 | ||
223 | |||
224 | typedef struct drm_i915_mem_alloc { | ||
225 | int region; | ||
226 | int alignment; | ||
227 | int size; | ||
228 | int __user *region_offset; /* offset from start of fb or agp */ | ||
229 | } drm_i915_mem_alloc_t; | ||
230 | |||
231 | typedef struct drm_i915_mem_free { | ||
232 | int region; | ||
233 | int region_offset; | ||
234 | } drm_i915_mem_free_t; | ||
235 | |||
236 | typedef struct drm_i915_mem_init_heap { | ||
237 | int region; | ||
238 | int size; | ||
239 | int start; | ||
240 | } drm_i915_mem_init_heap_t; | ||
241 | |||
242 | /* Allow memory manager to be torn down and re-initialized (eg on | ||
243 | * rotate): | ||
244 | */ | ||
245 | typedef struct drm_i915_mem_destroy_heap { | ||
246 | int region; | ||
247 | } drm_i915_mem_destroy_heap_t; | ||
248 | |||
249 | /* Allow X server to configure which pipes to monitor for vblank signals | ||
250 | */ | ||
251 | #define DRM_I915_VBLANK_PIPE_A 1 | ||
252 | #define DRM_I915_VBLANK_PIPE_B 2 | ||
253 | |||
254 | typedef struct drm_i915_vblank_pipe { | ||
255 | int pipe; | ||
256 | } drm_i915_vblank_pipe_t; | ||
257 | |||
258 | /* Schedule buffer swap at given vertical blank: | ||
259 | */ | ||
260 | typedef struct drm_i915_vblank_swap { | ||
261 | drm_drawable_t drawable; | ||
262 | enum drm_vblank_seq_type seqtype; | ||
263 | unsigned int sequence; | ||
264 | } drm_i915_vblank_swap_t; | ||
265 | |||
266 | typedef struct drm_i915_hws_addr { | ||
267 | uint64_t addr; | ||
268 | } drm_i915_hws_addr_t; | ||
269 | |||
270 | #endif /* _I915_DRM_H_ */ | ||
diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h new file mode 100644 index 000000000000..944b50a5ff24 --- /dev/null +++ b/include/drm/mga_drm.h | |||
@@ -0,0 +1,417 @@ | |||
1 | /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- | ||
2 | * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com | ||
3 | * | ||
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | ||
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
6 | * All rights reserved. | ||
7 | * | ||
8 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
9 | * copy of this software and associated documentation files (the "Software"), | ||
10 | * to deal in the Software without restriction, including without limitation | ||
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
12 | * and/or sell copies of the Software, and to permit persons to whom the | ||
13 | * Software is furnished to do so, subject to the following conditions: | ||
14 | * | ||
15 | * The above copyright notice and this permission notice (including the next | ||
16 | * paragraph) shall be included in all copies or substantial portions of the | ||
17 | * Software. | ||
18 | * | ||
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
22 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
25 | * OTHER DEALINGS IN THE SOFTWARE. | ||
26 | * | ||
27 | * Authors: | ||
28 | * Jeff Hartmann <jhartmann@valinux.com> | ||
29 | * Keith Whitwell <keith@tungstengraphics.com> | ||
30 | * | ||
31 | * Rewritten by: | ||
32 | * Gareth Hughes <gareth@valinux.com> | ||
33 | */ | ||
34 | |||
35 | #ifndef __MGA_DRM_H__ | ||
36 | #define __MGA_DRM_H__ | ||
37 | |||
38 | /* WARNING: If you change any of these defines, make sure to change the | ||
39 | * defines in the Xserver file (mga_sarea.h) | ||
40 | */ | ||
41 | |||
42 | #ifndef __MGA_SAREA_DEFINES__ | ||
43 | #define __MGA_SAREA_DEFINES__ | ||
44 | |||
45 | /* WARP pipe flags | ||
46 | */ | ||
47 | #define MGA_F 0x1 /* fog */ | ||
48 | #define MGA_A 0x2 /* alpha */ | ||
49 | #define MGA_S 0x4 /* specular */ | ||
50 | #define MGA_T2 0x8 /* multitexture */ | ||
51 | |||
52 | #define MGA_WARP_TGZ 0 | ||
53 | #define MGA_WARP_TGZF (MGA_F) | ||
54 | #define MGA_WARP_TGZA (MGA_A) | ||
55 | #define MGA_WARP_TGZAF (MGA_F|MGA_A) | ||
56 | #define MGA_WARP_TGZS (MGA_S) | ||
57 | #define MGA_WARP_TGZSF (MGA_S|MGA_F) | ||
58 | #define MGA_WARP_TGZSA (MGA_S|MGA_A) | ||
59 | #define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) | ||
60 | #define MGA_WARP_T2GZ (MGA_T2) | ||
61 | #define MGA_WARP_T2GZF (MGA_T2|MGA_F) | ||
62 | #define MGA_WARP_T2GZA (MGA_T2|MGA_A) | ||
63 | #define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) | ||
64 | #define MGA_WARP_T2GZS (MGA_T2|MGA_S) | ||
65 | #define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) | ||
66 | #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) | ||
67 | #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) | ||
68 | |||
69 | #define MGA_MAX_G200_PIPES 8 /* no multitex */ | ||
70 | #define MGA_MAX_G400_PIPES 16 | ||
71 | #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES | ||
72 | #define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ | ||
73 | |||
74 | #define MGA_CARD_TYPE_G200 1 | ||
75 | #define MGA_CARD_TYPE_G400 2 | ||
76 | #define MGA_CARD_TYPE_G450 3 /* not currently used */ | ||
77 | #define MGA_CARD_TYPE_G550 4 | ||
78 | |||
79 | #define MGA_FRONT 0x1 | ||
80 | #define MGA_BACK 0x2 | ||
81 | #define MGA_DEPTH 0x4 | ||
82 | |||
83 | /* What needs to be changed for the current vertex dma buffer? | ||
84 | */ | ||
85 | #define MGA_UPLOAD_CONTEXT 0x1 | ||
86 | #define MGA_UPLOAD_TEX0 0x2 | ||
87 | #define MGA_UPLOAD_TEX1 0x4 | ||
88 | #define MGA_UPLOAD_PIPE 0x8 | ||
89 | #define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ | ||
90 | #define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ | ||
91 | #define MGA_UPLOAD_2D 0x40 | ||
92 | #define MGA_WAIT_AGE 0x80 /* handled client-side */ | ||
93 | #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ | ||
94 | #if 0 | ||
95 | #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock | ||
96 | quiescent */ | ||
97 | #endif | ||
98 | |||
99 | /* 32 buffers of 64k each, total 2 meg. | ||
100 | */ | ||
101 | #define MGA_BUFFER_SIZE (1 << 16) | ||
102 | #define MGA_NUM_BUFFERS 128 | ||
103 | |||
104 | /* Keep these small for testing. | ||
105 | */ | ||
106 | #define MGA_NR_SAREA_CLIPRECTS 8 | ||
107 | |||
108 | /* 2 heaps (1 for card, 1 for agp), each divided into upto 128 | ||
109 | * regions, subject to a minimum region size of (1<<16) == 64k. | ||
110 | * | ||
111 | * Clients may subdivide regions internally, but when sharing between | ||
112 | * clients, the region size is the minimum granularity. | ||
113 | */ | ||
114 | |||
115 | #define MGA_CARD_HEAP 0 | ||
116 | #define MGA_AGP_HEAP 1 | ||
117 | #define MGA_NR_TEX_HEAPS 2 | ||
118 | #define MGA_NR_TEX_REGIONS 16 | ||
119 | #define MGA_LOG_MIN_TEX_REGION_SIZE 16 | ||
120 | |||
121 | #define DRM_MGA_IDLE_RETRY 2048 | ||
122 | |||
123 | #endif /* __MGA_SAREA_DEFINES__ */ | ||
124 | |||
125 | /* Setup registers for 3D context | ||
126 | */ | ||
127 | typedef struct { | ||
128 | unsigned int dstorg; | ||
129 | unsigned int maccess; | ||
130 | unsigned int plnwt; | ||
131 | unsigned int dwgctl; | ||
132 | unsigned int alphactrl; | ||
133 | unsigned int fogcolor; | ||
134 | unsigned int wflag; | ||
135 | unsigned int tdualstage0; | ||
136 | unsigned int tdualstage1; | ||
137 | unsigned int fcol; | ||
138 | unsigned int stencil; | ||
139 | unsigned int stencilctl; | ||
140 | } drm_mga_context_regs_t; | ||
141 | |||
142 | /* Setup registers for 2D, X server | ||
143 | */ | ||
144 | typedef struct { | ||
145 | unsigned int pitch; | ||
146 | } drm_mga_server_regs_t; | ||
147 | |||
148 | /* Setup registers for each texture unit | ||
149 | */ | ||
150 | typedef struct { | ||
151 | unsigned int texctl; | ||
152 | unsigned int texctl2; | ||
153 | unsigned int texfilter; | ||
154 | unsigned int texbordercol; | ||
155 | unsigned int texorg; | ||
156 | unsigned int texwidth; | ||
157 | unsigned int texheight; | ||
158 | unsigned int texorg1; | ||
159 | unsigned int texorg2; | ||
160 | unsigned int texorg3; | ||
161 | unsigned int texorg4; | ||
162 | } drm_mga_texture_regs_t; | ||
163 | |||
164 | /* General aging mechanism | ||
165 | */ | ||
166 | typedef struct { | ||
167 | unsigned int head; /* Position of head pointer */ | ||
168 | unsigned int wrap; /* Primary DMA wrap count */ | ||
169 | } drm_mga_age_t; | ||
170 | |||
171 | typedef struct _drm_mga_sarea { | ||
172 | /* The channel for communication of state information to the kernel | ||
173 | * on firing a vertex dma buffer. | ||
174 | */ | ||
175 | drm_mga_context_regs_t context_state; | ||
176 | drm_mga_server_regs_t server_state; | ||
177 | drm_mga_texture_regs_t tex_state[2]; | ||
178 | unsigned int warp_pipe; | ||
179 | unsigned int dirty; | ||
180 | unsigned int vertsize; | ||
181 | |||
182 | /* The current cliprects, or a subset thereof. | ||
183 | */ | ||
184 | struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; | ||
185 | unsigned int nbox; | ||
186 | |||
187 | /* Information about the most recently used 3d drawable. The | ||
188 | * client fills in the req_* fields, the server fills in the | ||
189 | * exported_ fields and puts the cliprects into boxes, above. | ||
190 | * | ||
191 | * The client clears the exported_drawable field before | ||
192 | * clobbering the boxes data. | ||
193 | */ | ||
194 | unsigned int req_drawable; /* the X drawable id */ | ||
195 | unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ | ||
196 | |||
197 | unsigned int exported_drawable; | ||
198 | unsigned int exported_index; | ||
199 | unsigned int exported_stamp; | ||
200 | unsigned int exported_buffers; | ||
201 | unsigned int exported_nfront; | ||
202 | unsigned int exported_nback; | ||
203 | int exported_back_x, exported_front_x, exported_w; | ||
204 | int exported_back_y, exported_front_y, exported_h; | ||
205 | struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; | ||
206 | |||
207 | /* Counters for aging textures and for client-side throttling. | ||
208 | */ | ||
209 | unsigned int status[4]; | ||
210 | unsigned int last_wrap; | ||
211 | |||
212 | drm_mga_age_t last_frame; | ||
213 | unsigned int last_enqueue; /* last time a buffer was enqueued */ | ||
214 | unsigned int last_dispatch; /* age of the most recently dispatched buffer */ | ||
215 | unsigned int last_quiescent; /* */ | ||
216 | |||
217 | /* LRU lists for texture memory in agp space and on the card. | ||
218 | */ | ||
219 | struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; | ||
220 | unsigned int texAge[MGA_NR_TEX_HEAPS]; | ||
221 | |||
222 | /* Mechanism to validate card state. | ||
223 | */ | ||
224 | int ctxOwner; | ||
225 | } drm_mga_sarea_t; | ||
226 | |||
227 | /* MGA specific ioctls | ||
228 | * The device specific ioctl range is 0x40 to 0x79. | ||
229 | */ | ||
230 | #define DRM_MGA_INIT 0x00 | ||
231 | #define DRM_MGA_FLUSH 0x01 | ||
232 | #define DRM_MGA_RESET 0x02 | ||
233 | #define DRM_MGA_SWAP 0x03 | ||
234 | #define DRM_MGA_CLEAR 0x04 | ||
235 | #define DRM_MGA_VERTEX 0x05 | ||
236 | #define DRM_MGA_INDICES 0x06 | ||
237 | #define DRM_MGA_ILOAD 0x07 | ||
238 | #define DRM_MGA_BLIT 0x08 | ||
239 | #define DRM_MGA_GETPARAM 0x09 | ||
240 | |||
241 | /* 3.2: | ||
242 | * ioctls for operating on fences. | ||
243 | */ | ||
244 | #define DRM_MGA_SET_FENCE 0x0a | ||
245 | #define DRM_MGA_WAIT_FENCE 0x0b | ||
246 | #define DRM_MGA_DMA_BOOTSTRAP 0x0c | ||
247 | |||
248 | #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) | ||
249 | #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) | ||
250 | #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) | ||
251 | #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) | ||
252 | #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) | ||
253 | #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) | ||
254 | #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) | ||
255 | #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) | ||
256 | #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) | ||
257 | #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) | ||
258 | #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) | ||
259 | #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) | ||
260 | #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) | ||
261 | |||
262 | typedef struct _drm_mga_warp_index { | ||
263 | int installed; | ||
264 | unsigned long phys_addr; | ||
265 | int size; | ||
266 | } drm_mga_warp_index_t; | ||
267 | |||
268 | typedef struct drm_mga_init { | ||
269 | enum { | ||
270 | MGA_INIT_DMA = 0x01, | ||
271 | MGA_CLEANUP_DMA = 0x02 | ||
272 | } func; | ||
273 | |||
274 | unsigned long sarea_priv_offset; | ||
275 | |||
276 | int chipset; | ||
277 | int sgram; | ||
278 | |||
279 | unsigned int maccess; | ||
280 | |||
281 | unsigned int fb_cpp; | ||
282 | unsigned int front_offset, front_pitch; | ||
283 | unsigned int back_offset, back_pitch; | ||
284 | |||
285 | unsigned int depth_cpp; | ||
286 | unsigned int depth_offset, depth_pitch; | ||
287 | |||
288 | unsigned int texture_offset[MGA_NR_TEX_HEAPS]; | ||
289 | unsigned int texture_size[MGA_NR_TEX_HEAPS]; | ||
290 | |||
291 | unsigned long fb_offset; | ||
292 | unsigned long mmio_offset; | ||
293 | unsigned long status_offset; | ||
294 | unsigned long warp_offset; | ||
295 | unsigned long primary_offset; | ||
296 | unsigned long buffers_offset; | ||
297 | } drm_mga_init_t; | ||
298 | |||
299 | typedef struct drm_mga_dma_bootstrap { | ||
300 | /** | ||
301 | * \name AGP texture region | ||
302 | * | ||
303 | * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will | ||
304 | * be filled in with the actual AGP texture settings. | ||
305 | * | ||
306 | * \warning | ||
307 | * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode | ||
308 | * is zero, it means that PCI memory (most likely through the use of | ||
309 | * an IOMMU) is being used for "AGP" textures. | ||
310 | */ | ||
311 | /*@{ */ | ||
312 | unsigned long texture_handle; /**< Handle used to map AGP textures. */ | ||
313 | uint32_t texture_size; /**< Size of the AGP texture region. */ | ||
314 | /*@} */ | ||
315 | |||
316 | /** | ||
317 | * Requested size of the primary DMA region. | ||
318 | * | ||
319 | * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be | ||
320 | * filled in with the actual AGP mode. If AGP was not available | ||
321 | */ | ||
322 | uint32_t primary_size; | ||
323 | |||
324 | /** | ||
325 | * Requested number of secondary DMA buffers. | ||
326 | * | ||
327 | * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be | ||
328 | * filled in with the actual number of secondary DMA buffers | ||
329 | * allocated. Particularly when PCI DMA is used, this may be | ||
330 | * (subtantially) less than the number requested. | ||
331 | */ | ||
332 | uint32_t secondary_bin_count; | ||
333 | |||
334 | /** | ||
335 | * Requested size of each secondary DMA buffer. | ||
336 | * | ||
337 | * While the kernel \b is free to reduce | ||
338 | * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed | ||
339 | * to reduce dma_mga_dma_bootstrap::secondary_bin_size. | ||
340 | */ | ||
341 | uint32_t secondary_bin_size; | ||
342 | |||
343 | /** | ||
344 | * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, | ||
345 | * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is | ||
346 | * zero, it means that PCI DMA should be used, even if AGP is | ||
347 | * possible. | ||
348 | * | ||
349 | * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be | ||
350 | * filled in with the actual AGP mode. If AGP was not available | ||
351 | * (i.e., PCI DMA was used), this value will be zero. | ||
352 | */ | ||
353 | uint32_t agp_mode; | ||
354 | |||
355 | /** | ||
356 | * Desired AGP GART size, measured in megabytes. | ||
357 | */ | ||
358 | uint8_t agp_size; | ||
359 | } drm_mga_dma_bootstrap_t; | ||
360 | |||
361 | typedef struct drm_mga_clear { | ||
362 | unsigned int flags; | ||
363 | unsigned int clear_color; | ||
364 | unsigned int clear_depth; | ||
365 | unsigned int color_mask; | ||
366 | unsigned int depth_mask; | ||
367 | } drm_mga_clear_t; | ||
368 | |||
369 | typedef struct drm_mga_vertex { | ||
370 | int idx; /* buffer to queue */ | ||
371 | int used; /* bytes in use */ | ||
372 | int discard; /* client finished with buffer? */ | ||
373 | } drm_mga_vertex_t; | ||
374 | |||
375 | typedef struct drm_mga_indices { | ||
376 | int idx; /* buffer to queue */ | ||
377 | unsigned int start; | ||
378 | unsigned int end; | ||
379 | int discard; /* client finished with buffer? */ | ||
380 | } drm_mga_indices_t; | ||
381 | |||
382 | typedef struct drm_mga_iload { | ||
383 | int idx; | ||
384 | unsigned int dstorg; | ||
385 | unsigned int length; | ||
386 | } drm_mga_iload_t; | ||
387 | |||
388 | typedef struct _drm_mga_blit { | ||
389 | unsigned int planemask; | ||
390 | unsigned int srcorg; | ||
391 | unsigned int dstorg; | ||
392 | int src_pitch, dst_pitch; | ||
393 | int delta_sx, delta_sy; | ||
394 | int delta_dx, delta_dy; | ||
395 | int height, ydir; /* flip image vertically */ | ||
396 | int source_pitch, dest_pitch; | ||
397 | } drm_mga_blit_t; | ||
398 | |||
399 | /* 3.1: An ioctl to get parameters that aren't available to the 3d | ||
400 | * client any other way. | ||
401 | */ | ||
402 | #define MGA_PARAM_IRQ_NR 1 | ||
403 | |||
404 | /* 3.2: Query the actual card type. The DDX only distinguishes between | ||
405 | * G200 chips and non-G200 chips, which it calls G400. It turns out that | ||
406 | * there are some very sublte differences between the G4x0 chips and the G550 | ||
407 | * chips. Using this parameter query, a client-side driver can detect the | ||
408 | * difference between a G4x0 and a G550. | ||
409 | */ | ||
410 | #define MGA_PARAM_CARD_TYPE 2 | ||
411 | |||
412 | typedef struct drm_mga_getparam { | ||
413 | int param; | ||
414 | void __user *value; | ||
415 | } drm_mga_getparam_t; | ||
416 | |||
417 | #endif | ||
diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h new file mode 100644 index 000000000000..8d8878b55f55 --- /dev/null +++ b/include/drm/r128_drm.h | |||
@@ -0,0 +1,326 @@ | |||
1 | /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- | ||
2 | * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com | ||
3 | */ | ||
4 | /* | ||
5 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | ||
6 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | ||
7 | * All rights reserved. | ||
8 | * | ||
9 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
10 | * copy of this software and associated documentation files (the "Software"), | ||
11 | * to deal in the Software without restriction, including without limitation | ||
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
13 | * and/or sell copies of the Software, and to permit persons to whom the | ||
14 | * Software is furnished to do so, subject to the following conditions: | ||
15 | * | ||
16 | * The above copyright notice and this permission notice (including the next | ||
17 | * paragraph) shall be included in all copies or substantial portions of the | ||
18 | * Software. | ||
19 | * | ||
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
23 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
26 | * DEALINGS IN THE SOFTWARE. | ||
27 | * | ||
28 | * Authors: | ||
29 | * Gareth Hughes <gareth@valinux.com> | ||
30 | * Kevin E. Martin <martin@valinux.com> | ||
31 | */ | ||
32 | |||
33 | #ifndef __R128_DRM_H__ | ||
34 | #define __R128_DRM_H__ | ||
35 | |||
36 | /* WARNING: If you change any of these defines, make sure to change the | ||
37 | * defines in the X server file (r128_sarea.h) | ||
38 | */ | ||
39 | #ifndef __R128_SAREA_DEFINES__ | ||
40 | #define __R128_SAREA_DEFINES__ | ||
41 | |||
42 | /* What needs to be changed for the current vertex buffer? | ||
43 | */ | ||
44 | #define R128_UPLOAD_CONTEXT 0x001 | ||
45 | #define R128_UPLOAD_SETUP 0x002 | ||
46 | #define R128_UPLOAD_TEX0 0x004 | ||
47 | #define R128_UPLOAD_TEX1 0x008 | ||
48 | #define R128_UPLOAD_TEX0IMAGES 0x010 | ||
49 | #define R128_UPLOAD_TEX1IMAGES 0x020 | ||
50 | #define R128_UPLOAD_CORE 0x040 | ||
51 | #define R128_UPLOAD_MASKS 0x080 | ||
52 | #define R128_UPLOAD_WINDOW 0x100 | ||
53 | #define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ | ||
54 | #define R128_REQUIRE_QUIESCENCE 0x400 | ||
55 | #define R128_UPLOAD_ALL 0x7ff | ||
56 | |||
57 | #define R128_FRONT 0x1 | ||
58 | #define R128_BACK 0x2 | ||
59 | #define R128_DEPTH 0x4 | ||
60 | |||
61 | /* Primitive types | ||
62 | */ | ||
63 | #define R128_POINTS 0x1 | ||
64 | #define R128_LINES 0x2 | ||
65 | #define R128_LINE_STRIP 0x3 | ||
66 | #define R128_TRIANGLES 0x4 | ||
67 | #define R128_TRIANGLE_FAN 0x5 | ||
68 | #define R128_TRIANGLE_STRIP 0x6 | ||
69 | |||
70 | /* Vertex/indirect buffer size | ||
71 | */ | ||
72 | #define R128_BUFFER_SIZE 16384 | ||
73 | |||
74 | /* Byte offsets for indirect buffer data | ||
75 | */ | ||
76 | #define R128_INDEX_PRIM_OFFSET 20 | ||
77 | #define R128_HOSTDATA_BLIT_OFFSET 32 | ||
78 | |||
79 | /* Keep these small for testing. | ||
80 | */ | ||
81 | #define R128_NR_SAREA_CLIPRECTS 12 | ||
82 | |||
83 | /* There are 2 heaps (local/AGP). Each region within a heap is a | ||
84 | * minimum of 64k, and there are at most 64 of them per heap. | ||
85 | */ | ||
86 | #define R128_LOCAL_TEX_HEAP 0 | ||
87 | #define R128_AGP_TEX_HEAP 1 | ||
88 | #define R128_NR_TEX_HEAPS 2 | ||
89 | #define R128_NR_TEX_REGIONS 64 | ||
90 | #define R128_LOG_TEX_GRANULARITY 16 | ||
91 | |||
92 | #define R128_NR_CONTEXT_REGS 12 | ||
93 | |||
94 | #define R128_MAX_TEXTURE_LEVELS 11 | ||
95 | #define R128_MAX_TEXTURE_UNITS 2 | ||
96 | |||
97 | #endif /* __R128_SAREA_DEFINES__ */ | ||
98 | |||
99 | typedef struct { | ||
100 | /* Context state - can be written in one large chunk */ | ||
101 | unsigned int dst_pitch_offset_c; | ||
102 | unsigned int dp_gui_master_cntl_c; | ||
103 | unsigned int sc_top_left_c; | ||
104 | unsigned int sc_bottom_right_c; | ||
105 | unsigned int z_offset_c; | ||
106 | unsigned int z_pitch_c; | ||
107 | unsigned int z_sten_cntl_c; | ||
108 | unsigned int tex_cntl_c; | ||
109 | unsigned int misc_3d_state_cntl_reg; | ||
110 | unsigned int texture_clr_cmp_clr_c; | ||
111 | unsigned int texture_clr_cmp_msk_c; | ||
112 | unsigned int fog_color_c; | ||
113 | |||
114 | /* Texture state */ | ||
115 | unsigned int tex_size_pitch_c; | ||
116 | unsigned int constant_color_c; | ||
117 | |||
118 | /* Setup state */ | ||
119 | unsigned int pm4_vc_fpu_setup; | ||
120 | unsigned int setup_cntl; | ||
121 | |||
122 | /* Mask state */ | ||
123 | unsigned int dp_write_mask; | ||
124 | unsigned int sten_ref_mask_c; | ||
125 | unsigned int plane_3d_mask_c; | ||
126 | |||
127 | /* Window state */ | ||
128 | unsigned int window_xy_offset; | ||
129 | |||
130 | /* Core state */ | ||
131 | unsigned int scale_3d_cntl; | ||
132 | } drm_r128_context_regs_t; | ||
133 | |||
134 | /* Setup registers for each texture unit | ||
135 | */ | ||
136 | typedef struct { | ||
137 | unsigned int tex_cntl; | ||
138 | unsigned int tex_combine_cntl; | ||
139 | unsigned int tex_size_pitch; | ||
140 | unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; | ||
141 | unsigned int tex_border_color; | ||
142 | } drm_r128_texture_regs_t; | ||
143 | |||
144 | typedef struct drm_r128_sarea { | ||
145 | /* The channel for communication of state information to the kernel | ||
146 | * on firing a vertex buffer. | ||
147 | */ | ||
148 | drm_r128_context_regs_t context_state; | ||
149 | drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; | ||
150 | unsigned int dirty; | ||
151 | unsigned int vertsize; | ||
152 | unsigned int vc_format; | ||
153 | |||
154 | /* The current cliprects, or a subset thereof. | ||
155 | */ | ||
156 | struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; | ||
157 | unsigned int nbox; | ||
158 | |||
159 | /* Counters for client-side throttling of rendering clients. | ||
160 | */ | ||
161 | unsigned int last_frame; | ||
162 | unsigned int last_dispatch; | ||
163 | |||
164 | struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; | ||
165 | unsigned int tex_age[R128_NR_TEX_HEAPS]; | ||
166 | int ctx_owner; | ||
167 | int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ | ||
168 | int pfCurrentPage; /* which buffer is being displayed? */ | ||
169 | } drm_r128_sarea_t; | ||
170 | |||
171 | /* WARNING: If you change any of these defines, make sure to change the | ||
172 | * defines in the Xserver file (xf86drmR128.h) | ||
173 | */ | ||
174 | |||
175 | /* Rage 128 specific ioctls | ||
176 | * The device specific ioctl range is 0x40 to 0x79. | ||
177 | */ | ||
178 | #define DRM_R128_INIT 0x00 | ||
179 | #define DRM_R128_CCE_START 0x01 | ||
180 | #define DRM_R128_CCE_STOP 0x02 | ||
181 | #define DRM_R128_CCE_RESET 0x03 | ||
182 | #define DRM_R128_CCE_IDLE 0x04 | ||
183 | /* 0x05 not used */ | ||
184 | #define DRM_R128_RESET 0x06 | ||
185 | #define DRM_R128_SWAP 0x07 | ||
186 | #define DRM_R128_CLEAR 0x08 | ||
187 | #define DRM_R128_VERTEX 0x09 | ||
188 | #define DRM_R128_INDICES 0x0a | ||
189 | #define DRM_R128_BLIT 0x0b | ||
190 | #define DRM_R128_DEPTH 0x0c | ||
191 | #define DRM_R128_STIPPLE 0x0d | ||
192 | /* 0x0e not used */ | ||
193 | #define DRM_R128_INDIRECT 0x0f | ||
194 | #define DRM_R128_FULLSCREEN 0x10 | ||
195 | #define DRM_R128_CLEAR2 0x11 | ||
196 | #define DRM_R128_GETPARAM 0x12 | ||
197 | #define DRM_R128_FLIP 0x13 | ||
198 | |||
199 | #define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) | ||
200 | #define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) | ||
201 | #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) | ||
202 | #define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) | ||
203 | #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) | ||
204 | /* 0x05 not used */ | ||
205 | #define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) | ||
206 | #define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) | ||
207 | #define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) | ||
208 | #define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) | ||
209 | #define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) | ||
210 | #define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) | ||
211 | #define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) | ||
212 | #define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) | ||
213 | /* 0x0e not used */ | ||
214 | #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) | ||
215 | #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) | ||
216 | #define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) | ||
217 | #define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) | ||
218 | #define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) | ||
219 | |||
220 | typedef struct drm_r128_init { | ||
221 | enum { | ||
222 | R128_INIT_CCE = 0x01, | ||
223 | R128_CLEANUP_CCE = 0x02 | ||
224 | } func; | ||
225 | unsigned long sarea_priv_offset; | ||
226 | int is_pci; | ||
227 | int cce_mode; | ||
228 | int cce_secure; | ||
229 | int ring_size; | ||
230 | int usec_timeout; | ||
231 | |||
232 | unsigned int fb_bpp; | ||
233 | unsigned int front_offset, front_pitch; | ||
234 | unsigned int back_offset, back_pitch; | ||
235 | unsigned int depth_bpp; | ||
236 | unsigned int depth_offset, depth_pitch; | ||
237 | unsigned int span_offset; | ||
238 | |||
239 | unsigned long fb_offset; | ||
240 | unsigned long mmio_offset; | ||
241 | unsigned long ring_offset; | ||
242 | unsigned long ring_rptr_offset; | ||
243 | unsigned long buffers_offset; | ||
244 | unsigned long agp_textures_offset; | ||
245 | } drm_r128_init_t; | ||
246 | |||
247 | typedef struct drm_r128_cce_stop { | ||
248 | int flush; | ||
249 | int idle; | ||
250 | } drm_r128_cce_stop_t; | ||
251 | |||
252 | typedef struct drm_r128_clear { | ||
253 | unsigned int flags; | ||
254 | unsigned int clear_color; | ||
255 | unsigned int clear_depth; | ||
256 | unsigned int color_mask; | ||
257 | unsigned int depth_mask; | ||
258 | } drm_r128_clear_t; | ||
259 | |||
260 | typedef struct drm_r128_vertex { | ||
261 | int prim; | ||
262 | int idx; /* Index of vertex buffer */ | ||
263 | int count; /* Number of vertices in buffer */ | ||
264 | int discard; /* Client finished with buffer? */ | ||
265 | } drm_r128_vertex_t; | ||
266 | |||
267 | typedef struct drm_r128_indices { | ||
268 | int prim; | ||
269 | int idx; | ||
270 | int start; | ||
271 | int end; | ||
272 | int discard; /* Client finished with buffer? */ | ||
273 | } drm_r128_indices_t; | ||
274 | |||
275 | typedef struct drm_r128_blit { | ||
276 | int idx; | ||
277 | int pitch; | ||
278 | int offset; | ||
279 | int format; | ||
280 | unsigned short x, y; | ||
281 | unsigned short width, height; | ||
282 | } drm_r128_blit_t; | ||
283 | |||
284 | typedef struct drm_r128_depth { | ||
285 | enum { | ||
286 | R128_WRITE_SPAN = 0x01, | ||
287 | R128_WRITE_PIXELS = 0x02, | ||
288 | R128_READ_SPAN = 0x03, | ||
289 | R128_READ_PIXELS = 0x04 | ||
290 | } func; | ||
291 | int n; | ||
292 | int __user *x; | ||
293 | int __user *y; | ||
294 | unsigned int __user *buffer; | ||
295 | unsigned char __user *mask; | ||
296 | } drm_r128_depth_t; | ||
297 | |||
298 | typedef struct drm_r128_stipple { | ||
299 | unsigned int __user *mask; | ||
300 | } drm_r128_stipple_t; | ||
301 | |||
302 | typedef struct drm_r128_indirect { | ||
303 | int idx; | ||
304 | int start; | ||
305 | int end; | ||
306 | int discard; | ||
307 | } drm_r128_indirect_t; | ||
308 | |||
309 | typedef struct drm_r128_fullscreen { | ||
310 | enum { | ||
311 | R128_INIT_FULLSCREEN = 0x01, | ||
312 | R128_CLEANUP_FULLSCREEN = 0x02 | ||
313 | } func; | ||
314 | } drm_r128_fullscreen_t; | ||
315 | |||
316 | /* 2.3: An ioctl to get parameters that aren't available to the 3d | ||
317 | * client any other way. | ||
318 | */ | ||
319 | #define R128_PARAM_IRQ_NR 1 | ||
320 | |||
321 | typedef struct drm_r128_getparam { | ||
322 | int param; | ||
323 | void __user *value; | ||
324 | } drm_r128_getparam_t; | ||
325 | |||
326 | #endif | ||
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h new file mode 100644 index 000000000000..73ff51f12311 --- /dev/null +++ b/include/drm/radeon_drm.h | |||
@@ -0,0 +1,749 @@ | |||
1 | /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- | ||
2 | * | ||
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | ||
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | ||
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | ||
6 | * All rights reserved. | ||
7 | * | ||
8 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
9 | * copy of this software and associated documentation files (the "Software"), | ||
10 | * to deal in the Software without restriction, including without limitation | ||
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
12 | * and/or sell copies of the Software, and to permit persons to whom the | ||
13 | * Software is furnished to do so, subject to the following conditions: | ||
14 | * | ||
15 | * The above copyright notice and this permission notice (including the next | ||
16 | * paragraph) shall be included in all copies or substantial portions of the | ||
17 | * Software. | ||
18 | * | ||
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
25 | * DEALINGS IN THE SOFTWARE. | ||
26 | * | ||
27 | * Authors: | ||
28 | * Kevin E. Martin <martin@valinux.com> | ||
29 | * Gareth Hughes <gareth@valinux.com> | ||
30 | * Keith Whitwell <keith@tungstengraphics.com> | ||
31 | */ | ||
32 | |||
33 | #ifndef __RADEON_DRM_H__ | ||
34 | #define __RADEON_DRM_H__ | ||
35 | |||
36 | /* WARNING: If you change any of these defines, make sure to change the | ||
37 | * defines in the X server file (radeon_sarea.h) | ||
38 | */ | ||
39 | #ifndef __RADEON_SAREA_DEFINES__ | ||
40 | #define __RADEON_SAREA_DEFINES__ | ||
41 | |||
42 | /* Old style state flags, required for sarea interface (1.1 and 1.2 | ||
43 | * clears) and 1.2 drm_vertex2 ioctl. | ||
44 | */ | ||
45 | #define RADEON_UPLOAD_CONTEXT 0x00000001 | ||
46 | #define RADEON_UPLOAD_VERTFMT 0x00000002 | ||
47 | #define RADEON_UPLOAD_LINE 0x00000004 | ||
48 | #define RADEON_UPLOAD_BUMPMAP 0x00000008 | ||
49 | #define RADEON_UPLOAD_MASKS 0x00000010 | ||
50 | #define RADEON_UPLOAD_VIEWPORT 0x00000020 | ||
51 | #define RADEON_UPLOAD_SETUP 0x00000040 | ||
52 | #define RADEON_UPLOAD_TCL 0x00000080 | ||
53 | #define RADEON_UPLOAD_MISC 0x00000100 | ||
54 | #define RADEON_UPLOAD_TEX0 0x00000200 | ||
55 | #define RADEON_UPLOAD_TEX1 0x00000400 | ||
56 | #define RADEON_UPLOAD_TEX2 0x00000800 | ||
57 | #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 | ||
58 | #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 | ||
59 | #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 | ||
60 | #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ | ||
61 | #define RADEON_REQUIRE_QUIESCENCE 0x00010000 | ||
62 | #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ | ||
63 | #define RADEON_UPLOAD_ALL 0x003effff | ||
64 | #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff | ||
65 | |||
66 | /* New style per-packet identifiers for use in cmd_buffer ioctl with | ||
67 | * the RADEON_EMIT_PACKET command. Comments relate new packets to old | ||
68 | * state bits and the packet size: | ||
69 | */ | ||
70 | #define RADEON_EMIT_PP_MISC 0 /* context/7 */ | ||
71 | #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ | ||
72 | #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ | ||
73 | #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ | ||
74 | #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ | ||
75 | #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ | ||
76 | #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ | ||
77 | #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ | ||
78 | #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ | ||
79 | #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ | ||
80 | #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ | ||
81 | #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ | ||
82 | #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ | ||
83 | #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ | ||
84 | #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ | ||
85 | #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ | ||
86 | #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ | ||
87 | #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ | ||
88 | #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ | ||
89 | #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ | ||
90 | #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ | ||
91 | #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ | ||
92 | #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ | ||
93 | #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ | ||
94 | #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ | ||
95 | #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ | ||
96 | #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ | ||
97 | #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ | ||
98 | #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ | ||
99 | #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ | ||
100 | #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ | ||
101 | #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ | ||
102 | #define R200_EMIT_VAP_CTL 32 /* vap/1 */ | ||
103 | #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ | ||
104 | #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ | ||
105 | #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ | ||
106 | #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ | ||
107 | #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ | ||
108 | #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ | ||
109 | #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ | ||
110 | #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ | ||
111 | #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ | ||
112 | #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ | ||
113 | #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ | ||
114 | #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ | ||
115 | #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ | ||
116 | #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ | ||
117 | #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ | ||
118 | #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ | ||
119 | #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ | ||
120 | #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ | ||
121 | #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ | ||
122 | #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ | ||
123 | #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ | ||
124 | #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ | ||
125 | #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ | ||
126 | #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ | ||
127 | #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ | ||
128 | #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ | ||
129 | #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ | ||
130 | #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ | ||
131 | #define R200_EMIT_PP_CUBIC_FACES_0 61 | ||
132 | #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 | ||
133 | #define R200_EMIT_PP_CUBIC_FACES_1 63 | ||
134 | #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 | ||
135 | #define R200_EMIT_PP_CUBIC_FACES_2 65 | ||
136 | #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 | ||
137 | #define R200_EMIT_PP_CUBIC_FACES_3 67 | ||
138 | #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 | ||
139 | #define R200_EMIT_PP_CUBIC_FACES_4 69 | ||
140 | #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 | ||
141 | #define R200_EMIT_PP_CUBIC_FACES_5 71 | ||
142 | #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 | ||
143 | #define RADEON_EMIT_PP_TEX_SIZE_0 73 | ||
144 | #define RADEON_EMIT_PP_TEX_SIZE_1 74 | ||
145 | #define RADEON_EMIT_PP_TEX_SIZE_2 75 | ||
146 | #define R200_EMIT_RB3D_BLENDCOLOR 76 | ||
147 | #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 | ||
148 | #define RADEON_EMIT_PP_CUBIC_FACES_0 78 | ||
149 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 | ||
150 | #define RADEON_EMIT_PP_CUBIC_FACES_1 80 | ||
151 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 | ||
152 | #define RADEON_EMIT_PP_CUBIC_FACES_2 82 | ||
153 | #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 | ||
154 | #define R200_EMIT_PP_TRI_PERF_CNTL 84 | ||
155 | #define R200_EMIT_PP_AFS_0 85 | ||
156 | #define R200_EMIT_PP_AFS_1 86 | ||
157 | #define R200_EMIT_ATF_TFACTOR 87 | ||
158 | #define R200_EMIT_PP_TXCTLALL_0 88 | ||
159 | #define R200_EMIT_PP_TXCTLALL_1 89 | ||
160 | #define R200_EMIT_PP_TXCTLALL_2 90 | ||
161 | #define R200_EMIT_PP_TXCTLALL_3 91 | ||
162 | #define R200_EMIT_PP_TXCTLALL_4 92 | ||
163 | #define R200_EMIT_PP_TXCTLALL_5 93 | ||
164 | #define R200_EMIT_VAP_PVS_CNTL 94 | ||
165 | #define RADEON_MAX_STATE_PACKETS 95 | ||
166 | |||
167 | /* Commands understood by cmd_buffer ioctl. More can be added but | ||
168 | * obviously these can't be removed or changed: | ||
169 | */ | ||
170 | #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ | ||
171 | #define RADEON_CMD_SCALARS 2 /* emit scalar data */ | ||
172 | #define RADEON_CMD_VECTORS 3 /* emit vector data */ | ||
173 | #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ | ||
174 | #define RADEON_CMD_PACKET3 5 /* emit hw packet */ | ||
175 | #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ | ||
176 | #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ | ||
177 | #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: | ||
178 | * doesn't make the cpu wait, just | ||
179 | * the graphics hardware */ | ||
180 | #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ | ||
181 | |||
182 | typedef union { | ||
183 | int i; | ||
184 | struct { | ||
185 | unsigned char cmd_type, pad0, pad1, pad2; | ||
186 | } header; | ||
187 | struct { | ||
188 | unsigned char cmd_type, packet_id, pad0, pad1; | ||
189 | } packet; | ||
190 | struct { | ||
191 | unsigned char cmd_type, offset, stride, count; | ||
192 | } scalars; | ||
193 | struct { | ||
194 | unsigned char cmd_type, offset, stride, count; | ||
195 | } vectors; | ||
196 | struct { | ||
197 | unsigned char cmd_type, addr_lo, addr_hi, count; | ||
198 | } veclinear; | ||
199 | struct { | ||
200 | unsigned char cmd_type, buf_idx, pad0, pad1; | ||
201 | } dma; | ||
202 | struct { | ||
203 | unsigned char cmd_type, flags, pad0, pad1; | ||
204 | } wait; | ||
205 | } drm_radeon_cmd_header_t; | ||
206 | |||
207 | #define RADEON_WAIT_2D 0x1 | ||
208 | #define RADEON_WAIT_3D 0x2 | ||
209 | |||
210 | /* Allowed parameters for R300_CMD_PACKET3 | ||
211 | */ | ||
212 | #define R300_CMD_PACKET3_CLEAR 0 | ||
213 | #define R300_CMD_PACKET3_RAW 1 | ||
214 | |||
215 | /* Commands understood by cmd_buffer ioctl for R300. | ||
216 | * The interface has not been stabilized, so some of these may be removed | ||
217 | * and eventually reordered before stabilization. | ||
218 | */ | ||
219 | #define R300_CMD_PACKET0 1 | ||
220 | #define R300_CMD_VPU 2 /* emit vertex program upload */ | ||
221 | #define R300_CMD_PACKET3 3 /* emit a packet3 */ | ||
222 | #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ | ||
223 | #define R300_CMD_CP_DELAY 5 | ||
224 | #define R300_CMD_DMA_DISCARD 6 | ||
225 | #define R300_CMD_WAIT 7 | ||
226 | # define R300_WAIT_2D 0x1 | ||
227 | # define R300_WAIT_3D 0x2 | ||
228 | /* these two defines are DOING IT WRONG - however | ||
229 | * we have userspace which relies on using these. | ||
230 | * The wait interface is backwards compat new | ||
231 | * code should use the NEW_WAIT defines below | ||
232 | * THESE ARE NOT BIT FIELDS | ||
233 | */ | ||
234 | # define R300_WAIT_2D_CLEAN 0x3 | ||
235 | # define R300_WAIT_3D_CLEAN 0x4 | ||
236 | |||
237 | # define R300_NEW_WAIT_2D_3D 0x3 | ||
238 | # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 | ||
239 | # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 | ||
240 | # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 | ||
241 | |||
242 | #define R300_CMD_SCRATCH 8 | ||
243 | #define R300_CMD_R500FP 9 | ||
244 | |||
245 | typedef union { | ||
246 | unsigned int u; | ||
247 | struct { | ||
248 | unsigned char cmd_type, pad0, pad1, pad2; | ||
249 | } header; | ||
250 | struct { | ||
251 | unsigned char cmd_type, count, reglo, reghi; | ||
252 | } packet0; | ||
253 | struct { | ||
254 | unsigned char cmd_type, count, adrlo, adrhi; | ||
255 | } vpu; | ||
256 | struct { | ||
257 | unsigned char cmd_type, packet, pad0, pad1; | ||
258 | } packet3; | ||
259 | struct { | ||
260 | unsigned char cmd_type, packet; | ||
261 | unsigned short count; /* amount of packet2 to emit */ | ||
262 | } delay; | ||
263 | struct { | ||
264 | unsigned char cmd_type, buf_idx, pad0, pad1; | ||
265 | } dma; | ||
266 | struct { | ||
267 | unsigned char cmd_type, flags, pad0, pad1; | ||
268 | } wait; | ||
269 | struct { | ||
270 | unsigned char cmd_type, reg, n_bufs, flags; | ||
271 | } scratch; | ||
272 | struct { | ||
273 | unsigned char cmd_type, count, adrlo, adrhi_flags; | ||
274 | } r500fp; | ||
275 | } drm_r300_cmd_header_t; | ||
276 | |||
277 | #define RADEON_FRONT 0x1 | ||
278 | #define RADEON_BACK 0x2 | ||
279 | #define RADEON_DEPTH 0x4 | ||
280 | #define RADEON_STENCIL 0x8 | ||
281 | #define RADEON_CLEAR_FASTZ 0x80000000 | ||
282 | #define RADEON_USE_HIERZ 0x40000000 | ||
283 | #define RADEON_USE_COMP_ZBUF 0x20000000 | ||
284 | |||
285 | #define R500FP_CONSTANT_TYPE (1 << 1) | ||
286 | #define R500FP_CONSTANT_CLAMP (1 << 2) | ||
287 | |||
288 | /* Primitive types | ||
289 | */ | ||
290 | #define RADEON_POINTS 0x1 | ||
291 | #define RADEON_LINES 0x2 | ||
292 | #define RADEON_LINE_STRIP 0x3 | ||
293 | #define RADEON_TRIANGLES 0x4 | ||
294 | #define RADEON_TRIANGLE_FAN 0x5 | ||
295 | #define RADEON_TRIANGLE_STRIP 0x6 | ||
296 | |||
297 | /* Vertex/indirect buffer size | ||
298 | */ | ||
299 | #define RADEON_BUFFER_SIZE 65536 | ||
300 | |||
301 | /* Byte offsets for indirect buffer data | ||
302 | */ | ||
303 | #define RADEON_INDEX_PRIM_OFFSET 20 | ||
304 | |||
305 | #define RADEON_SCRATCH_REG_OFFSET 32 | ||
306 | |||
307 | #define RADEON_NR_SAREA_CLIPRECTS 12 | ||
308 | |||
309 | /* There are 2 heaps (local/GART). Each region within a heap is a | ||
310 | * minimum of 64k, and there are at most 64 of them per heap. | ||
311 | */ | ||
312 | #define RADEON_LOCAL_TEX_HEAP 0 | ||
313 | #define RADEON_GART_TEX_HEAP 1 | ||
314 | #define RADEON_NR_TEX_HEAPS 2 | ||
315 | #define RADEON_NR_TEX_REGIONS 64 | ||
316 | #define RADEON_LOG_TEX_GRANULARITY 16 | ||
317 | |||
318 | #define RADEON_MAX_TEXTURE_LEVELS 12 | ||
319 | #define RADEON_MAX_TEXTURE_UNITS 3 | ||
320 | |||
321 | #define RADEON_MAX_SURFACES 8 | ||
322 | |||
323 | /* Blits have strict offset rules. All blit offset must be aligned on | ||
324 | * a 1K-byte boundary. | ||
325 | */ | ||
326 | #define RADEON_OFFSET_SHIFT 10 | ||
327 | #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) | ||
328 | #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) | ||
329 | |||
330 | #endif /* __RADEON_SAREA_DEFINES__ */ | ||
331 | |||
332 | typedef struct { | ||
333 | unsigned int red; | ||
334 | unsigned int green; | ||
335 | unsigned int blue; | ||
336 | unsigned int alpha; | ||
337 | } radeon_color_regs_t; | ||
338 | |||
339 | typedef struct { | ||
340 | /* Context state */ | ||
341 | unsigned int pp_misc; /* 0x1c14 */ | ||
342 | unsigned int pp_fog_color; | ||
343 | unsigned int re_solid_color; | ||
344 | unsigned int rb3d_blendcntl; | ||
345 | unsigned int rb3d_depthoffset; | ||
346 | unsigned int rb3d_depthpitch; | ||
347 | unsigned int rb3d_zstencilcntl; | ||
348 | |||
349 | unsigned int pp_cntl; /* 0x1c38 */ | ||
350 | unsigned int rb3d_cntl; | ||
351 | unsigned int rb3d_coloroffset; | ||
352 | unsigned int re_width_height; | ||
353 | unsigned int rb3d_colorpitch; | ||
354 | unsigned int se_cntl; | ||
355 | |||
356 | /* Vertex format state */ | ||
357 | unsigned int se_coord_fmt; /* 0x1c50 */ | ||
358 | |||
359 | /* Line state */ | ||
360 | unsigned int re_line_pattern; /* 0x1cd0 */ | ||
361 | unsigned int re_line_state; | ||
362 | |||
363 | unsigned int se_line_width; /* 0x1db8 */ | ||
364 | |||
365 | /* Bumpmap state */ | ||
366 | unsigned int pp_lum_matrix; /* 0x1d00 */ | ||
367 | |||
368 | unsigned int pp_rot_matrix_0; /* 0x1d58 */ | ||
369 | unsigned int pp_rot_matrix_1; | ||
370 | |||
371 | /* Mask state */ | ||
372 | unsigned int rb3d_stencilrefmask; /* 0x1d7c */ | ||
373 | unsigned int rb3d_ropcntl; | ||
374 | unsigned int rb3d_planemask; | ||
375 | |||
376 | /* Viewport state */ | ||
377 | unsigned int se_vport_xscale; /* 0x1d98 */ | ||
378 | unsigned int se_vport_xoffset; | ||
379 | unsigned int se_vport_yscale; | ||
380 | unsigned int se_vport_yoffset; | ||
381 | unsigned int se_vport_zscale; | ||
382 | unsigned int se_vport_zoffset; | ||
383 | |||
384 | /* Setup state */ | ||
385 | unsigned int se_cntl_status; /* 0x2140 */ | ||
386 | |||
387 | /* Misc state */ | ||
388 | unsigned int re_top_left; /* 0x26c0 */ | ||
389 | unsigned int re_misc; | ||
390 | } drm_radeon_context_regs_t; | ||
391 | |||
392 | typedef struct { | ||
393 | /* Zbias state */ | ||
394 | unsigned int se_zbias_factor; /* 0x1dac */ | ||
395 | unsigned int se_zbias_constant; | ||
396 | } drm_radeon_context2_regs_t; | ||
397 | |||
398 | /* Setup registers for each texture unit | ||
399 | */ | ||
400 | typedef struct { | ||
401 | unsigned int pp_txfilter; | ||
402 | unsigned int pp_txformat; | ||
403 | unsigned int pp_txoffset; | ||
404 | unsigned int pp_txcblend; | ||
405 | unsigned int pp_txablend; | ||
406 | unsigned int pp_tfactor; | ||
407 | unsigned int pp_border_color; | ||
408 | } drm_radeon_texture_regs_t; | ||
409 | |||
410 | typedef struct { | ||
411 | unsigned int start; | ||
412 | unsigned int finish; | ||
413 | unsigned int prim:8; | ||
414 | unsigned int stateidx:8; | ||
415 | unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ | ||
416 | unsigned int vc_format; /* vertex format */ | ||
417 | } drm_radeon_prim_t; | ||
418 | |||
419 | typedef struct { | ||
420 | drm_radeon_context_regs_t context; | ||
421 | drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; | ||
422 | drm_radeon_context2_regs_t context2; | ||
423 | unsigned int dirty; | ||
424 | } drm_radeon_state_t; | ||
425 | |||
426 | typedef struct { | ||
427 | /* The channel for communication of state information to the | ||
428 | * kernel on firing a vertex buffer with either of the | ||
429 | * obsoleted vertex/index ioctls. | ||
430 | */ | ||
431 | drm_radeon_context_regs_t context_state; | ||
432 | drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; | ||
433 | unsigned int dirty; | ||
434 | unsigned int vertsize; | ||
435 | unsigned int vc_format; | ||
436 | |||
437 | /* The current cliprects, or a subset thereof. | ||
438 | */ | ||
439 | struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; | ||
440 | unsigned int nbox; | ||
441 | |||
442 | /* Counters for client-side throttling of rendering clients. | ||
443 | */ | ||
444 | unsigned int last_frame; | ||
445 | unsigned int last_dispatch; | ||
446 | unsigned int last_clear; | ||
447 | |||
448 | struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + | ||
449 | 1]; | ||
450 | unsigned int tex_age[RADEON_NR_TEX_HEAPS]; | ||
451 | int ctx_owner; | ||
452 | int pfState; /* number of 3d windows (0,1,2ormore) */ | ||
453 | int pfCurrentPage; /* which buffer is being displayed? */ | ||
454 | int crtc2_base; /* CRTC2 frame offset */ | ||
455 | int tiling_enabled; /* set by drm, read by 2d + 3d clients */ | ||
456 | } drm_radeon_sarea_t; | ||
457 | |||
458 | /* WARNING: If you change any of these defines, make sure to change the | ||
459 | * defines in the Xserver file (xf86drmRadeon.h) | ||
460 | * | ||
461 | * KW: actually it's illegal to change any of this (backwards compatibility). | ||
462 | */ | ||
463 | |||
464 | /* Radeon specific ioctls | ||
465 | * The device specific ioctl range is 0x40 to 0x79. | ||
466 | */ | ||
467 | #define DRM_RADEON_CP_INIT 0x00 | ||
468 | #define DRM_RADEON_CP_START 0x01 | ||
469 | #define DRM_RADEON_CP_STOP 0x02 | ||
470 | #define DRM_RADEON_CP_RESET 0x03 | ||
471 | #define DRM_RADEON_CP_IDLE 0x04 | ||
472 | #define DRM_RADEON_RESET 0x05 | ||
473 | #define DRM_RADEON_FULLSCREEN 0x06 | ||
474 | #define DRM_RADEON_SWAP 0x07 | ||
475 | #define DRM_RADEON_CLEAR 0x08 | ||
476 | #define DRM_RADEON_VERTEX 0x09 | ||
477 | #define DRM_RADEON_INDICES 0x0A | ||
478 | #define DRM_RADEON_NOT_USED | ||
479 | #define DRM_RADEON_STIPPLE 0x0C | ||
480 | #define DRM_RADEON_INDIRECT 0x0D | ||
481 | #define DRM_RADEON_TEXTURE 0x0E | ||
482 | #define DRM_RADEON_VERTEX2 0x0F | ||
483 | #define DRM_RADEON_CMDBUF 0x10 | ||
484 | #define DRM_RADEON_GETPARAM 0x11 | ||
485 | #define DRM_RADEON_FLIP 0x12 | ||
486 | #define DRM_RADEON_ALLOC 0x13 | ||
487 | #define DRM_RADEON_FREE 0x14 | ||
488 | #define DRM_RADEON_INIT_HEAP 0x15 | ||
489 | #define DRM_RADEON_IRQ_EMIT 0x16 | ||
490 | #define DRM_RADEON_IRQ_WAIT 0x17 | ||
491 | #define DRM_RADEON_CP_RESUME 0x18 | ||
492 | #define DRM_RADEON_SETPARAM 0x19 | ||
493 | #define DRM_RADEON_SURF_ALLOC 0x1a | ||
494 | #define DRM_RADEON_SURF_FREE 0x1b | ||
495 | |||
496 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) | ||
497 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) | ||
498 | #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) | ||
499 | #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) | ||
500 | #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) | ||
501 | #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) | ||
502 | #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) | ||
503 | #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) | ||
504 | #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) | ||
505 | #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) | ||
506 | #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) | ||
507 | #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) | ||
508 | #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) | ||
509 | #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) | ||
510 | #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) | ||
511 | #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) | ||
512 | #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) | ||
513 | #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) | ||
514 | #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) | ||
515 | #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) | ||
516 | #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) | ||
517 | #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) | ||
518 | #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) | ||
519 | #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) | ||
520 | #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) | ||
521 | #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) | ||
522 | #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) | ||
523 | |||
524 | typedef struct drm_radeon_init { | ||
525 | enum { | ||
526 | RADEON_INIT_CP = 0x01, | ||
527 | RADEON_CLEANUP_CP = 0x02, | ||
528 | RADEON_INIT_R200_CP = 0x03, | ||
529 | RADEON_INIT_R300_CP = 0x04 | ||
530 | } func; | ||
531 | unsigned long sarea_priv_offset; | ||
532 | int is_pci; | ||
533 | int cp_mode; | ||
534 | int gart_size; | ||
535 | int ring_size; | ||
536 | int usec_timeout; | ||
537 | |||
538 | unsigned int fb_bpp; | ||
539 | unsigned int front_offset, front_pitch; | ||
540 | unsigned int back_offset, back_pitch; | ||
541 | unsigned int depth_bpp; | ||
542 | unsigned int depth_offset, depth_pitch; | ||
543 | |||
544 | unsigned long fb_offset; | ||
545 | unsigned long mmio_offset; | ||
546 | unsigned long ring_offset; | ||
547 | unsigned long ring_rptr_offset; | ||
548 | unsigned long buffers_offset; | ||
549 | unsigned long gart_textures_offset; | ||
550 | } drm_radeon_init_t; | ||
551 | |||
552 | typedef struct drm_radeon_cp_stop { | ||
553 | int flush; | ||
554 | int idle; | ||
555 | } drm_radeon_cp_stop_t; | ||
556 | |||
557 | typedef struct drm_radeon_fullscreen { | ||
558 | enum { | ||
559 | RADEON_INIT_FULLSCREEN = 0x01, | ||
560 | RADEON_CLEANUP_FULLSCREEN = 0x02 | ||
561 | } func; | ||
562 | } drm_radeon_fullscreen_t; | ||
563 | |||
564 | #define CLEAR_X1 0 | ||
565 | #define CLEAR_Y1 1 | ||
566 | #define CLEAR_X2 2 | ||
567 | #define CLEAR_Y2 3 | ||
568 | #define CLEAR_DEPTH 4 | ||
569 | |||
570 | typedef union drm_radeon_clear_rect { | ||
571 | float f[5]; | ||
572 | unsigned int ui[5]; | ||
573 | } drm_radeon_clear_rect_t; | ||
574 | |||
575 | typedef struct drm_radeon_clear { | ||
576 | unsigned int flags; | ||
577 | unsigned int clear_color; | ||
578 | unsigned int clear_depth; | ||
579 | unsigned int color_mask; | ||
580 | unsigned int depth_mask; /* misnamed field: should be stencil */ | ||
581 | drm_radeon_clear_rect_t __user *depth_boxes; | ||
582 | } drm_radeon_clear_t; | ||
583 | |||
584 | typedef struct drm_radeon_vertex { | ||
585 | int prim; | ||
586 | int idx; /* Index of vertex buffer */ | ||
587 | int count; /* Number of vertices in buffer */ | ||
588 | int discard; /* Client finished with buffer? */ | ||
589 | } drm_radeon_vertex_t; | ||
590 | |||
591 | typedef struct drm_radeon_indices { | ||
592 | int prim; | ||
593 | int idx; | ||
594 | int start; | ||
595 | int end; | ||
596 | int discard; /* Client finished with buffer? */ | ||
597 | } drm_radeon_indices_t; | ||
598 | |||
599 | /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices | ||
600 | * - allows multiple primitives and state changes in a single ioctl | ||
601 | * - supports driver change to emit native primitives | ||
602 | */ | ||
603 | typedef struct drm_radeon_vertex2 { | ||
604 | int idx; /* Index of vertex buffer */ | ||
605 | int discard; /* Client finished with buffer? */ | ||
606 | int nr_states; | ||
607 | drm_radeon_state_t __user *state; | ||
608 | int nr_prims; | ||
609 | drm_radeon_prim_t __user *prim; | ||
610 | } drm_radeon_vertex2_t; | ||
611 | |||
612 | /* v1.3 - obsoletes drm_radeon_vertex2 | ||
613 | * - allows arbitarily large cliprect list | ||
614 | * - allows updating of tcl packet, vector and scalar state | ||
615 | * - allows memory-efficient description of state updates | ||
616 | * - allows state to be emitted without a primitive | ||
617 | * (for clears, ctx switches) | ||
618 | * - allows more than one dma buffer to be referenced per ioctl | ||
619 | * - supports tcl driver | ||
620 | * - may be extended in future versions with new cmd types, packets | ||
621 | */ | ||
622 | typedef struct drm_radeon_cmd_buffer { | ||
623 | int bufsz; | ||
624 | char __user *buf; | ||
625 | int nbox; | ||
626 | struct drm_clip_rect __user *boxes; | ||
627 | } drm_radeon_cmd_buffer_t; | ||
628 | |||
629 | typedef struct drm_radeon_tex_image { | ||
630 | unsigned int x, y; /* Blit coordinates */ | ||
631 | unsigned int width, height; | ||
632 | const void __user *data; | ||
633 | } drm_radeon_tex_image_t; | ||
634 | |||
635 | typedef struct drm_radeon_texture { | ||
636 | unsigned int offset; | ||
637 | int pitch; | ||
638 | int format; | ||
639 | int width; /* Texture image coordinates */ | ||
640 | int height; | ||
641 | drm_radeon_tex_image_t __user *image; | ||
642 | } drm_radeon_texture_t; | ||
643 | |||
644 | typedef struct drm_radeon_stipple { | ||
645 | unsigned int __user *mask; | ||
646 | } drm_radeon_stipple_t; | ||
647 | |||
648 | typedef struct drm_radeon_indirect { | ||
649 | int idx; | ||
650 | int start; | ||
651 | int end; | ||
652 | int discard; | ||
653 | } drm_radeon_indirect_t; | ||
654 | |||
655 | /* enum for card type parameters */ | ||
656 | #define RADEON_CARD_PCI 0 | ||
657 | #define RADEON_CARD_AGP 1 | ||
658 | #define RADEON_CARD_PCIE 2 | ||
659 | |||
660 | /* 1.3: An ioctl to get parameters that aren't available to the 3d | ||
661 | * client any other way. | ||
662 | */ | ||
663 | #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ | ||
664 | #define RADEON_PARAM_LAST_FRAME 2 | ||
665 | #define RADEON_PARAM_LAST_DISPATCH 3 | ||
666 | #define RADEON_PARAM_LAST_CLEAR 4 | ||
667 | /* Added with DRM version 1.6. */ | ||
668 | #define RADEON_PARAM_IRQ_NR 5 | ||
669 | #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ | ||
670 | /* Added with DRM version 1.8. */ | ||
671 | #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ | ||
672 | #define RADEON_PARAM_STATUS_HANDLE 8 | ||
673 | #define RADEON_PARAM_SAREA_HANDLE 9 | ||
674 | #define RADEON_PARAM_GART_TEX_HANDLE 10 | ||
675 | #define RADEON_PARAM_SCRATCH_OFFSET 11 | ||
676 | #define RADEON_PARAM_CARD_TYPE 12 | ||
677 | #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ | ||
678 | #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ | ||
679 | #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ | ||
680 | |||
681 | typedef struct drm_radeon_getparam { | ||
682 | int param; | ||
683 | void __user *value; | ||
684 | } drm_radeon_getparam_t; | ||
685 | |||
686 | /* 1.6: Set up a memory manager for regions of shared memory: | ||
687 | */ | ||
688 | #define RADEON_MEM_REGION_GART 1 | ||
689 | #define RADEON_MEM_REGION_FB 2 | ||
690 | |||
691 | typedef struct drm_radeon_mem_alloc { | ||
692 | int region; | ||
693 | int alignment; | ||
694 | int size; | ||
695 | int __user *region_offset; /* offset from start of fb or GART */ | ||
696 | } drm_radeon_mem_alloc_t; | ||
697 | |||
698 | typedef struct drm_radeon_mem_free { | ||
699 | int region; | ||
700 | int region_offset; | ||
701 | } drm_radeon_mem_free_t; | ||
702 | |||
703 | typedef struct drm_radeon_mem_init_heap { | ||
704 | int region; | ||
705 | int size; | ||
706 | int start; | ||
707 | } drm_radeon_mem_init_heap_t; | ||
708 | |||
709 | /* 1.6: Userspace can request & wait on irq's: | ||
710 | */ | ||
711 | typedef struct drm_radeon_irq_emit { | ||
712 | int __user *irq_seq; | ||
713 | } drm_radeon_irq_emit_t; | ||
714 | |||
715 | typedef struct drm_radeon_irq_wait { | ||
716 | int irq_seq; | ||
717 | } drm_radeon_irq_wait_t; | ||
718 | |||
719 | /* 1.10: Clients tell the DRM where they think the framebuffer is located in | ||
720 | * the card's address space, via a new generic ioctl to set parameters | ||
721 | */ | ||
722 | |||
723 | typedef struct drm_radeon_setparam { | ||
724 | unsigned int param; | ||
725 | int64_t value; | ||
726 | } drm_radeon_setparam_t; | ||
727 | |||
728 | #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ | ||
729 | #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ | ||
730 | #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ | ||
731 | #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ | ||
732 | #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ | ||
733 | #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ | ||
734 | /* 1.14: Clients can allocate/free a surface | ||
735 | */ | ||
736 | typedef struct drm_radeon_surface_alloc { | ||
737 | unsigned int address; | ||
738 | unsigned int size; | ||
739 | unsigned int flags; | ||
740 | } drm_radeon_surface_alloc_t; | ||
741 | |||
742 | typedef struct drm_radeon_surface_free { | ||
743 | unsigned int address; | ||
744 | } drm_radeon_surface_free_t; | ||
745 | |||
746 | #define DRM_RADEON_VBLANK_CRTC1 1 | ||
747 | #define DRM_RADEON_VBLANK_CRTC2 2 | ||
748 | |||
749 | #endif | ||
diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h new file mode 100644 index 000000000000..8a576ef01821 --- /dev/null +++ b/include/drm/savage_drm.h | |||
@@ -0,0 +1,210 @@ | |||
1 | /* savage_drm.h -- Public header for the savage driver | ||
2 | * | ||
3 | * Copyright 2004 Felix Kuehling | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice (including the | ||
14 | * next paragraph) shall be included in all copies or substantial portions | ||
15 | * of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
20 | * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR | ||
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF | ||
22 | * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
24 | */ | ||
25 | |||
26 | #ifndef __SAVAGE_DRM_H__ | ||
27 | #define __SAVAGE_DRM_H__ | ||
28 | |||
29 | #ifndef __SAVAGE_SAREA_DEFINES__ | ||
30 | #define __SAVAGE_SAREA_DEFINES__ | ||
31 | |||
32 | /* 2 heaps (1 for card, 1 for agp), each divided into upto 128 | ||
33 | * regions, subject to a minimum region size of (1<<16) == 64k. | ||
34 | * | ||
35 | * Clients may subdivide regions internally, but when sharing between | ||
36 | * clients, the region size is the minimum granularity. | ||
37 | */ | ||
38 | |||
39 | #define SAVAGE_CARD_HEAP 0 | ||
40 | #define SAVAGE_AGP_HEAP 1 | ||
41 | #define SAVAGE_NR_TEX_HEAPS 2 | ||
42 | #define SAVAGE_NR_TEX_REGIONS 16 | ||
43 | #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 | ||
44 | |||
45 | #endif /* __SAVAGE_SAREA_DEFINES__ */ | ||
46 | |||
47 | typedef struct _drm_savage_sarea { | ||
48 | /* LRU lists for texture memory in agp space and on the card. | ||
49 | */ | ||
50 | struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + | ||
51 | 1]; | ||
52 | unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; | ||
53 | |||
54 | /* Mechanism to validate card state. | ||
55 | */ | ||
56 | int ctxOwner; | ||
57 | } drm_savage_sarea_t, *drm_savage_sarea_ptr; | ||
58 | |||
59 | /* Savage-specific ioctls | ||
60 | */ | ||
61 | #define DRM_SAVAGE_BCI_INIT 0x00 | ||
62 | #define DRM_SAVAGE_BCI_CMDBUF 0x01 | ||
63 | #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 | ||
64 | #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 | ||
65 | |||
66 | #define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) | ||
67 | #define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) | ||
68 | #define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) | ||
69 | #define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) | ||
70 | |||
71 | #define SAVAGE_DMA_PCI 1 | ||
72 | #define SAVAGE_DMA_AGP 3 | ||
73 | typedef struct drm_savage_init { | ||
74 | enum { | ||
75 | SAVAGE_INIT_BCI = 1, | ||
76 | SAVAGE_CLEANUP_BCI = 2 | ||
77 | } func; | ||
78 | unsigned int sarea_priv_offset; | ||
79 | |||
80 | /* some parameters */ | ||
81 | unsigned int cob_size; | ||
82 | unsigned int bci_threshold_lo, bci_threshold_hi; | ||
83 | unsigned int dma_type; | ||
84 | |||
85 | /* frame buffer layout */ | ||
86 | unsigned int fb_bpp; | ||
87 | unsigned int front_offset, front_pitch; | ||
88 | unsigned int back_offset, back_pitch; | ||
89 | unsigned int depth_bpp; | ||
90 | unsigned int depth_offset, depth_pitch; | ||
91 | |||
92 | /* local textures */ | ||
93 | unsigned int texture_offset; | ||
94 | unsigned int texture_size; | ||
95 | |||
96 | /* physical locations of non-permanent maps */ | ||
97 | unsigned long status_offset; | ||
98 | unsigned long buffers_offset; | ||
99 | unsigned long agp_textures_offset; | ||
100 | unsigned long cmd_dma_offset; | ||
101 | } drm_savage_init_t; | ||
102 | |||
103 | typedef union drm_savage_cmd_header drm_savage_cmd_header_t; | ||
104 | typedef struct drm_savage_cmdbuf { | ||
105 | /* command buffer in client's address space */ | ||
106 | drm_savage_cmd_header_t __user *cmd_addr; | ||
107 | unsigned int size; /* size of the command buffer in 64bit units */ | ||
108 | |||
109 | unsigned int dma_idx; /* DMA buffer index to use */ | ||
110 | int discard; /* discard DMA buffer when done */ | ||
111 | /* vertex buffer in client's address space */ | ||
112 | unsigned int __user *vb_addr; | ||
113 | unsigned int vb_size; /* size of client vertex buffer in bytes */ | ||
114 | unsigned int vb_stride; /* stride of vertices in 32bit words */ | ||
115 | /* boxes in client's address space */ | ||
116 | struct drm_clip_rect __user *box_addr; | ||
117 | unsigned int nbox; /* number of clipping boxes */ | ||
118 | } drm_savage_cmdbuf_t; | ||
119 | |||
120 | #define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ | ||
121 | #define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ | ||
122 | #define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ | ||
123 | typedef struct drm_savage_event { | ||
124 | unsigned int count; | ||
125 | unsigned int flags; | ||
126 | } drm_savage_event_emit_t, drm_savage_event_wait_t; | ||
127 | |||
128 | /* Commands for the cmdbuf ioctl | ||
129 | */ | ||
130 | #define SAVAGE_CMD_STATE 0 /* a range of state registers */ | ||
131 | #define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ | ||
132 | #define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ | ||
133 | #define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ | ||
134 | #define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ | ||
135 | #define SAVAGE_CMD_CLEAR 5 /* clear buffers */ | ||
136 | #define SAVAGE_CMD_SWAP 6 /* swap buffers */ | ||
137 | |||
138 | /* Primitive types | ||
139 | */ | ||
140 | #define SAVAGE_PRIM_TRILIST 0 /* triangle list */ | ||
141 | #define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ | ||
142 | #define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ | ||
143 | #define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat | ||
144 | * shading on s3d */ | ||
145 | |||
146 | /* Skip flags (vertex format) | ||
147 | */ | ||
148 | #define SAVAGE_SKIP_Z 0x01 | ||
149 | #define SAVAGE_SKIP_W 0x02 | ||
150 | #define SAVAGE_SKIP_C0 0x04 | ||
151 | #define SAVAGE_SKIP_C1 0x08 | ||
152 | #define SAVAGE_SKIP_S0 0x10 | ||
153 | #define SAVAGE_SKIP_T0 0x20 | ||
154 | #define SAVAGE_SKIP_ST0 0x30 | ||
155 | #define SAVAGE_SKIP_S1 0x40 | ||
156 | #define SAVAGE_SKIP_T1 0x80 | ||
157 | #define SAVAGE_SKIP_ST1 0xc0 | ||
158 | #define SAVAGE_SKIP_ALL_S3D 0x3f | ||
159 | #define SAVAGE_SKIP_ALL_S4 0xff | ||
160 | |||
161 | /* Buffer names for clear command | ||
162 | */ | ||
163 | #define SAVAGE_FRONT 0x1 | ||
164 | #define SAVAGE_BACK 0x2 | ||
165 | #define SAVAGE_DEPTH 0x4 | ||
166 | |||
167 | /* 64-bit command header | ||
168 | */ | ||
169 | union drm_savage_cmd_header { | ||
170 | struct { | ||
171 | unsigned char cmd; /* command */ | ||
172 | unsigned char pad0; | ||
173 | unsigned short pad1; | ||
174 | unsigned short pad2; | ||
175 | unsigned short pad3; | ||
176 | } cmd; /* generic */ | ||
177 | struct { | ||
178 | unsigned char cmd; | ||
179 | unsigned char global; /* need idle engine? */ | ||
180 | unsigned short count; /* number of consecutive registers */ | ||
181 | unsigned short start; /* first register */ | ||
182 | unsigned short pad3; | ||
183 | } state; /* SAVAGE_CMD_STATE */ | ||
184 | struct { | ||
185 | unsigned char cmd; | ||
186 | unsigned char prim; /* primitive type */ | ||
187 | unsigned short skip; /* vertex format (skip flags) */ | ||
188 | unsigned short count; /* number of vertices */ | ||
189 | unsigned short start; /* first vertex in DMA/vertex buffer */ | ||
190 | } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ | ||
191 | struct { | ||
192 | unsigned char cmd; | ||
193 | unsigned char prim; | ||
194 | unsigned short skip; | ||
195 | unsigned short count; /* number of indices that follow */ | ||
196 | unsigned short pad3; | ||
197 | } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ | ||
198 | struct { | ||
199 | unsigned char cmd; | ||
200 | unsigned char pad0; | ||
201 | unsigned short pad1; | ||
202 | unsigned int flags; | ||
203 | } clear0; /* SAVAGE_CMD_CLEAR */ | ||
204 | struct { | ||
205 | unsigned int mask; | ||
206 | unsigned int value; | ||
207 | } clear1; /* SAVAGE_CMD_CLEAR data */ | ||
208 | }; | ||
209 | |||
210 | #endif | ||
diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h new file mode 100644 index 000000000000..30f7b3827466 --- /dev/null +++ b/include/drm/sis_drm.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ | ||
2 | /* | ||
3 | * Copyright 2005 Eric Anholt | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice (including the next | ||
14 | * paragraph) shall be included in all copies or substantial portions of the | ||
15 | * Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
23 | * SOFTWARE. | ||
24 | * | ||
25 | */ | ||
26 | |||
27 | #ifndef __SIS_DRM_H__ | ||
28 | #define __SIS_DRM_H__ | ||
29 | |||
30 | /* SiS specific ioctls */ | ||
31 | #define NOT_USED_0_3 | ||
32 | #define DRM_SIS_FB_ALLOC 0x04 | ||
33 | #define DRM_SIS_FB_FREE 0x05 | ||
34 | #define NOT_USED_6_12 | ||
35 | #define DRM_SIS_AGP_INIT 0x13 | ||
36 | #define DRM_SIS_AGP_ALLOC 0x14 | ||
37 | #define DRM_SIS_AGP_FREE 0x15 | ||
38 | #define DRM_SIS_FB_INIT 0x16 | ||
39 | |||
40 | #define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) | ||
41 | #define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) | ||
42 | #define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) | ||
43 | #define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) | ||
44 | #define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) | ||
45 | #define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) | ||
46 | /* | ||
47 | #define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) | ||
48 | #define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) | ||
49 | #define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) | ||
50 | */ | ||
51 | |||
52 | typedef struct { | ||
53 | int context; | ||
54 | unsigned int offset; | ||
55 | unsigned int size; | ||
56 | unsigned long free; | ||
57 | } drm_sis_mem_t; | ||
58 | |||
59 | typedef struct { | ||
60 | unsigned int offset, size; | ||
61 | } drm_sis_agp_t; | ||
62 | |||
63 | typedef struct { | ||
64 | unsigned int offset, size; | ||
65 | } drm_sis_fb_t; | ||
66 | |||
67 | #endif /* __SIS_DRM_H__ */ | ||
diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h new file mode 100644 index 000000000000..a3b5c102b067 --- /dev/null +++ b/include/drm/via_drm.h | |||
@@ -0,0 +1,275 @@ | |||
1 | /* | ||
2 | * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. | ||
3 | * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the "Software"), | ||
7 | * to deal in the Software without restriction, including without limitation | ||
8 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | ||
9 | * and/or sell copies of the Software, and to permit persons to whom the | ||
10 | * Software is furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice (including the | ||
13 | * next paragraph) shall be included in all copies or substantial portions | ||
14 | * of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
19 | * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _VIA_DRM_H_ | ||
25 | #define _VIA_DRM_H_ | ||
26 | |||
27 | /* WARNING: These defines must be the same as what the Xserver uses. | ||
28 | * if you change them, you must change the defines in the Xserver. | ||
29 | */ | ||
30 | |||
31 | #ifndef _VIA_DEFINES_ | ||
32 | #define _VIA_DEFINES_ | ||
33 | |||
34 | #ifndef __KERNEL__ | ||
35 | #include "via_drmclient.h" | ||
36 | #endif | ||
37 | |||
38 | #define VIA_NR_SAREA_CLIPRECTS 8 | ||
39 | #define VIA_NR_XVMC_PORTS 10 | ||
40 | #define VIA_NR_XVMC_LOCKS 5 | ||
41 | #define VIA_MAX_CACHELINE_SIZE 64 | ||
42 | #define XVMCLOCKPTR(saPriv,lockNo) \ | ||
43 | ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ | ||
44 | (VIA_MAX_CACHELINE_SIZE - 1)) & \ | ||
45 | ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ | ||
46 | VIA_MAX_CACHELINE_SIZE*(lockNo))) | ||
47 | |||
48 | /* Each region is a minimum of 64k, and there are at most 64 of them. | ||
49 | */ | ||
50 | #define VIA_NR_TEX_REGIONS 64 | ||
51 | #define VIA_LOG_MIN_TEX_REGION_SIZE 16 | ||
52 | #endif | ||
53 | |||
54 | #define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ | ||
55 | #define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ | ||
56 | #define VIA_UPLOAD_CTX 0x4 | ||
57 | #define VIA_UPLOAD_BUFFERS 0x8 | ||
58 | #define VIA_UPLOAD_TEX0 0x10 | ||
59 | #define VIA_UPLOAD_TEX1 0x20 | ||
60 | #define VIA_UPLOAD_CLIPRECTS 0x40 | ||
61 | #define VIA_UPLOAD_ALL 0xff | ||
62 | |||
63 | /* VIA specific ioctls */ | ||
64 | #define DRM_VIA_ALLOCMEM 0x00 | ||
65 | #define DRM_VIA_FREEMEM 0x01 | ||
66 | #define DRM_VIA_AGP_INIT 0x02 | ||
67 | #define DRM_VIA_FB_INIT 0x03 | ||
68 | #define DRM_VIA_MAP_INIT 0x04 | ||
69 | #define DRM_VIA_DEC_FUTEX 0x05 | ||
70 | #define NOT_USED | ||
71 | #define DRM_VIA_DMA_INIT 0x07 | ||
72 | #define DRM_VIA_CMDBUFFER 0x08 | ||
73 | #define DRM_VIA_FLUSH 0x09 | ||
74 | #define DRM_VIA_PCICMD 0x0a | ||
75 | #define DRM_VIA_CMDBUF_SIZE 0x0b | ||
76 | #define NOT_USED | ||
77 | #define DRM_VIA_WAIT_IRQ 0x0d | ||
78 | #define DRM_VIA_DMA_BLIT 0x0e | ||
79 | #define DRM_VIA_BLIT_SYNC 0x0f | ||
80 | |||
81 | #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) | ||
82 | #define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) | ||
83 | #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) | ||
84 | #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) | ||
85 | #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) | ||
86 | #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) | ||
87 | #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) | ||
88 | #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) | ||
89 | #define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) | ||
90 | #define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) | ||
91 | #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ | ||
92 | drm_via_cmdbuf_size_t) | ||
93 | #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) | ||
94 | #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) | ||
95 | #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) | ||
96 | |||
97 | /* Indices into buf.Setup where various bits of state are mirrored per | ||
98 | * context and per buffer. These can be fired at the card as a unit, | ||
99 | * or in a piecewise fashion as required. | ||
100 | */ | ||
101 | |||
102 | #define VIA_TEX_SETUP_SIZE 8 | ||
103 | |||
104 | /* Flags for clear ioctl | ||
105 | */ | ||
106 | #define VIA_FRONT 0x1 | ||
107 | #define VIA_BACK 0x2 | ||
108 | #define VIA_DEPTH 0x4 | ||
109 | #define VIA_STENCIL 0x8 | ||
110 | #define VIA_MEM_VIDEO 0 /* matches drm constant */ | ||
111 | #define VIA_MEM_AGP 1 /* matches drm constant */ | ||
112 | #define VIA_MEM_SYSTEM 2 | ||
113 | #define VIA_MEM_MIXED 3 | ||
114 | #define VIA_MEM_UNKNOWN 4 | ||
115 | |||
116 | typedef struct { | ||
117 | uint32_t offset; | ||
118 | uint32_t size; | ||
119 | } drm_via_agp_t; | ||
120 | |||
121 | typedef struct { | ||
122 | uint32_t offset; | ||
123 | uint32_t size; | ||
124 | } drm_via_fb_t; | ||
125 | |||
126 | typedef struct { | ||
127 | uint32_t context; | ||
128 | uint32_t type; | ||
129 | uint32_t size; | ||
130 | unsigned long index; | ||
131 | unsigned long offset; | ||
132 | } drm_via_mem_t; | ||
133 | |||
134 | typedef struct _drm_via_init { | ||
135 | enum { | ||
136 | VIA_INIT_MAP = 0x01, | ||
137 | VIA_CLEANUP_MAP = 0x02 | ||
138 | } func; | ||
139 | |||
140 | unsigned long sarea_priv_offset; | ||
141 | unsigned long fb_offset; | ||
142 | unsigned long mmio_offset; | ||
143 | unsigned long agpAddr; | ||
144 | } drm_via_init_t; | ||
145 | |||
146 | typedef struct _drm_via_futex { | ||
147 | enum { | ||
148 | VIA_FUTEX_WAIT = 0x00, | ||
149 | VIA_FUTEX_WAKE = 0X01 | ||
150 | } func; | ||
151 | uint32_t ms; | ||
152 | uint32_t lock; | ||
153 | uint32_t val; | ||
154 | } drm_via_futex_t; | ||
155 | |||
156 | typedef struct _drm_via_dma_init { | ||
157 | enum { | ||
158 | VIA_INIT_DMA = 0x01, | ||
159 | VIA_CLEANUP_DMA = 0x02, | ||
160 | VIA_DMA_INITIALIZED = 0x03 | ||
161 | } func; | ||
162 | |||
163 | unsigned long offset; | ||
164 | unsigned long size; | ||
165 | unsigned long reg_pause_addr; | ||
166 | } drm_via_dma_init_t; | ||
167 | |||
168 | typedef struct _drm_via_cmdbuffer { | ||
169 | char __user *buf; | ||
170 | unsigned long size; | ||
171 | } drm_via_cmdbuffer_t; | ||
172 | |||
173 | /* Warning: If you change the SAREA structure you must change the Xserver | ||
174 | * structure as well */ | ||
175 | |||
176 | typedef struct _drm_via_tex_region { | ||
177 | unsigned char next, prev; /* indices to form a circular LRU */ | ||
178 | unsigned char inUse; /* owned by a client, or free? */ | ||
179 | int age; /* tracked by clients to update local LRU's */ | ||
180 | } drm_via_tex_region_t; | ||
181 | |||
182 | typedef struct _drm_via_sarea { | ||
183 | unsigned int dirty; | ||
184 | unsigned int nbox; | ||
185 | struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; | ||
186 | drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; | ||
187 | int texAge; /* last time texture was uploaded */ | ||
188 | int ctxOwner; /* last context to upload state */ | ||
189 | int vertexPrim; | ||
190 | |||
191 | /* | ||
192 | * Below is for XvMC. | ||
193 | * We want the lock integers alone on, and aligned to, a cache line. | ||
194 | * Therefore this somewhat strange construct. | ||
195 | */ | ||
196 | |||
197 | char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; | ||
198 | |||
199 | unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; | ||
200 | unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; | ||
201 | unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ | ||
202 | |||
203 | /* Used by the 3d driver only at this point, for pageflipping: | ||
204 | */ | ||
205 | unsigned int pfCurrentOffset; | ||
206 | } drm_via_sarea_t; | ||
207 | |||
208 | typedef struct _drm_via_cmdbuf_size { | ||
209 | enum { | ||
210 | VIA_CMDBUF_SPACE = 0x01, | ||
211 | VIA_CMDBUF_LAG = 0x02 | ||
212 | } func; | ||
213 | int wait; | ||
214 | uint32_t size; | ||
215 | } drm_via_cmdbuf_size_t; | ||
216 | |||
217 | typedef enum { | ||
218 | VIA_IRQ_ABSOLUTE = 0x0, | ||
219 | VIA_IRQ_RELATIVE = 0x1, | ||
220 | VIA_IRQ_SIGNAL = 0x10000000, | ||
221 | VIA_IRQ_FORCE_SEQUENCE = 0x20000000 | ||
222 | } via_irq_seq_type_t; | ||
223 | |||
224 | #define VIA_IRQ_FLAGS_MASK 0xF0000000 | ||
225 | |||
226 | enum drm_via_irqs { | ||
227 | drm_via_irq_hqv0 = 0, | ||
228 | drm_via_irq_hqv1, | ||
229 | drm_via_irq_dma0_dd, | ||
230 | drm_via_irq_dma0_td, | ||
231 | drm_via_irq_dma1_dd, | ||
232 | drm_via_irq_dma1_td, | ||
233 | drm_via_irq_num | ||
234 | }; | ||
235 | |||
236 | struct drm_via_wait_irq_request { | ||
237 | unsigned irq; | ||
238 | via_irq_seq_type_t type; | ||
239 | uint32_t sequence; | ||
240 | uint32_t signal; | ||
241 | }; | ||
242 | |||
243 | typedef union drm_via_irqwait { | ||
244 | struct drm_via_wait_irq_request request; | ||
245 | struct drm_wait_vblank_reply reply; | ||
246 | } drm_via_irqwait_t; | ||
247 | |||
248 | typedef struct drm_via_blitsync { | ||
249 | uint32_t sync_handle; | ||
250 | unsigned engine; | ||
251 | } drm_via_blitsync_t; | ||
252 | |||
253 | /* - * Below,"flags" is currently unused but will be used for possible future | ||
254 | * extensions like kernel space bounce buffers for bad alignments and | ||
255 | * blit engine busy-wait polling for better latency in the absence of | ||
256 | * interrupts. | ||
257 | */ | ||
258 | |||
259 | typedef struct drm_via_dmablit { | ||
260 | uint32_t num_lines; | ||
261 | uint32_t line_length; | ||
262 | |||
263 | uint32_t fb_addr; | ||
264 | uint32_t fb_stride; | ||
265 | |||
266 | unsigned char *mem_addr; | ||
267 | uint32_t mem_stride; | ||
268 | |||
269 | uint32_t flags; | ||
270 | int to_fb; | ||
271 | |||
272 | drm_via_blitsync_t sync; | ||
273 | } drm_via_dmablit_t; | ||
274 | |||
275 | #endif /* _VIA_DRM_H_ */ | ||